diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
index 11f1574b41..f414cb5ebe 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
index 4556c88ec4..c9d0601bbe 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xxa_cm0plus.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
index f99cad47c8..1b78e0af5f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xxa_cm0plus.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
index 74bb3c8cbd..7fc4d7223f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
index 72e55e3d19..cd487a6e9a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xxa_cm4_dual.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
index dfb3fe373f..eab579e226 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xxa_cm4_dual.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -125,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
@@ -160,7 +165,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +238,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h
index 0ad244b658..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,6 +321,21 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
index 7a99d7b707..d2d8464543 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
index b78effb0c8..ec8378cb2d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm0plus.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
index 61d4a4b17b..ef9e33a6f2 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm0plus.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index e9a6874e34..56dec8710d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
index f0a3d746f1..cd0a072251 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm4_dual.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
index 51808a1db4..3f44a41c3f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm4_dual.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -125,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
@@ -160,7 +165,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +238,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h
index 0ad244b658..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,6 +321,21 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
index 7a99d7b707..d2d8464543 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
index b78effb0c8..ec8378cb2d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm0plus.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
index 61d4a4b17b..ef9e33a6f2 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm0plus.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index e9a6874e34..56dec8710d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
index f0a3d746f1..cd0a072251 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm4_dual.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
index 51808a1db4..3f44a41c3f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm4_dual.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -125,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
@@ -160,7 +165,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +238,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h
index 0ad244b658..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,6 +321,21 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
index 41d333f414..43c539760b 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cyb06xxa_cm0plus.sct
-;* \version 2.80
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
index 332737ec48..250aeb64db 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
@@ -1,5 +1,5 @@
 ;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.s
+; * @file     startup_psoc6_02_cm0plus.S
 ; * @brief    CMSIS Core Device Startup File for
 ; *           ARMCM0plus Device Series
 ; * @version  V5.00
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld
index 633610f14f..58c0b982c8 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cyb06xxa_cm0plus.ld
-* \version 2.80
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf
index 31f77fc13a..94087e244c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cyb06xxa_cm0plus.icf
-* \version 2.80
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S
index 3fa2e866e7..12bd881c67 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S
@@ -1,5 +1,5 @@
 ;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.s
+; * @file     startup_psoc6_02_cm0plus.S
 ; * @brief    CMSIS Core Device Startup File for
 ; *           ARMCM0plus Device Series
 ; * @version  V5.00
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
index 9b638fcf4e..9f0ca65ed1 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cyb06xxa_cm4_dual.sct
-;* \version 2.80
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
@@ -66,7 +66,7 @@
 #define BOOT_HEADER_SIZE        0x00000400
 
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00E8000
+  #define MBED_ROM_SIZE     0x000E8000
 #endif
 
 ;* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -188,11 +188,11 @@ LR_IROM1 FLASH_START FLASH_SIZE
 
     ; Application heap area (HEAP)
     ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    { 
+    {
     }
-    
+
     ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
     {
     }
 
@@ -290,7 +290,7 @@ CYMETA 0x90500000
 /* The following symbols used by the cymcuelftool. */
 /* Flash */
 #define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_length  0x001D0000
 #define __cy_memory_0_row_size 0x200
 
 /* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
index 4d54e8bed1..bb0ae5780c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
@@ -1,5 +1,5 @@
 ;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm4.s
+; * @file     startup_psoc6_02_cm4.S
 ; * @brief    CMSIS Core Device Startup File for
 ; *           ARMCM4 Device Series
 ; * @version  V5.00
@@ -282,7 +282,7 @@ Vectors_Copy
                 ; Enable the FPU if used
                 LDR     R0, =Cy_SystemInitFpuEnable
                 BLX     R0
-                
+
                 LDR     R0, =__main
                 BLX     R0
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld
index 873c29b451..626d058992 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cyb06xxa_cm4_dual.ld
-* \version 2.80
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
@@ -64,7 +64,7 @@ BOOT_HEADER_SIZE = 0x400;
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0xE8000
+  #define MBED_ROM_SIZE     0x000E8000
 #endif
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -180,6 +180,7 @@ SECTIONS
     /* Cortex-M4 application flash area */
     .text ORIGIN(flash) :
     {
+        /* Cortex-M4 flash vector table */
         . = ALIGN(4);
         __Vectors = . ;
         KEEP(*(.vectors))
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf
index c3ca5c295c..2d138f0cda 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cyb06xxa_cm4_dual.icf
-* \version 2.80
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
@@ -65,7 +65,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
 }
 
 if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x00E8000;
+  define symbol MBED_ROM_SIZE = 0x000E8000;
 }
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -267,7 +267,7 @@ keep {  section .cy_m0p_image,
 /* The following symbols used by the cymcuelftool. */
 /* Flash */
 define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00200000;
+define exported symbol __cy_memory_0_length   = 0x001D0000;
 define exported symbol __cy_memory_0_row_size = 0x200;
 
 /* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
index c58b712a10..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.80
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -129,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h
index bd27b72ad6..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.80
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,13 +321,18 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
 *       <td rowspan="2">2.80</td>
 *       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
 *       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
 *           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
 *   </tr>
 *   <tr>
-*       <td>Added \ref Cy_PRA_Init() function call to \ref SystemInit() API for CM0+ core of PSoC 64 Secure MCU.</td>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
 *       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
 *   </tr>
 *   <tr>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
index 70210e6765..36fb25ed5d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx5_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld
index c4b744affc..1d5a68d980 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx5_cm0plus.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
index d943f2eb76..827c69d6b5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx5_cm0plus.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
index f50a59217b..47a2b1f4b1 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx5_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld
index c7170ad30d..1f03713ce0 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx5_cm4_dual.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf
index f6e8888afa..1a8d7f2139 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx5_cm4_dual.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -125,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
@@ -160,7 +165,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +238,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h
index 0ad244b658..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,6 +321,21 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
index 11f1574b41..f414cb5ebe 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
index 4556c88ec4..c9d0601bbe 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xxa_cm0plus.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
index f99cad47c8..1b78e0af5f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xxa_cm0plus.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
index 74bb3c8cbd..7fc4d7223f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
index 72e55e3d19..cd487a6e9a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xxa_cm4_dual.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
index dfb3fe373f..eab579e226 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xxa_cm4_dual.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -125,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
@@ -160,7 +165,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +238,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h
index 0ad244b658..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,6 +321,21 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
index 4d54e8bed1..bb0ae5780c 100755
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
@@ -1,5 +1,5 @@
 ;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm4.s
+; * @file     startup_psoc6_02_cm4.S
 ; * @brief    CMSIS Core Device Startup File for
 ; *           ARMCM4 Device Series
 ; * @version  V5.00
@@ -282,7 +282,7 @@ Vectors_Copy
                 ; Enable the FPU if used
                 LDR     R0, =Cy_SystemInitFpuEnable
                 BLX     R0
-                
+
                 LDR     R0, =__main
                 BLX     R0
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
index c58b712a10..4431a9c82d 100755
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.80
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -129,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/system_psoc6.h
index bd27b72ad6..bec52039ad 100755
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.80
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,13 +321,18 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
 *       <td rowspan="2">2.80</td>
 *       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
 *       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
 *           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
 *   </tr>
 *   <tr>
-*       <td>Added \ref Cy_PRA_Init() function call to \ref SystemInit() API for CM0+ core of PSoC 64 Secure MCU.</td>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
 *       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
 *   </tr>
 *   <tr>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
index 7a99d7b707..d2d8464543 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
index b78effb0c8..ec8378cb2d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm0plus.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
index 61d4a4b17b..ef9e33a6f2 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm0plus.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index e9a6874e34..56dec8710d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
index f0a3d746f1..cd0a072251 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm4_dual.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
index 51808a1db4..3f44a41c3f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm4_dual.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -125,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
@@ -160,7 +165,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +238,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h
index 0ad244b658..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,6 +321,21 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
index 7a99d7b707..d2d8464543 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
index b78effb0c8..ec8378cb2d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm0plus.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
index 61d4a4b17b..ef9e33a6f2 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm0plus.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 2e2b15209a..ab66b4fc68 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -126,6 +130,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 *
 *******************************************************************************/
@@ -219,6 +224,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
@@ -263,7 +273,7 @@ void SystemCoreClockUpdate (void)
         cy_Hfclk0FreqHz = locHf0Clock;
         cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
         SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
+
         /* Sets clock frequency for Delay API */
         cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
         cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index e9a6874e34..56dec8710d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.90
 ;*
 ;* Linker file for the ARMCC.
 ;*
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
index f0a3d746f1..cd0a072251 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm4_dual.ld
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the GNU C compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
index 51808a1db4..3f44a41c3f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cy8c6xx7_cm4_dual.icf
-* \version 2.70.1
+* \version 2.90
 *
 * Linker file for the IAR compiler.
 *
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
index 7e634e2f31..4431a9c82d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.90
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -125,6 +129,7 @@ uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
 * - Unlocks and disables WDT.
 * - Calls Cy_PDL_Init() function to define the driver library.
 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
 * - Calls \ref SystemCoreClockUpdate().
 * \endcond
 *******************************************************************************/
@@ -160,7 +165,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +238,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h
index 0ad244b658..bec52039ad 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/device/system_psoc6.h
@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.90
 *
 * \brief Device system header file.
 *
@@ -85,20 +85,20 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
 * or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
 * 'xx' is the device family:\n
 * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
 *
 * <b>ARM Compiler</b>\n
 * The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
 * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
 * \note If the start of the Cortex-M4 application image is changed, the value
 * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
@@ -135,9 +135,9 @@
 * \endcode
 *
 * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
 * Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -175,11 +175,11 @@
 * define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
 * \endcode
 *
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
 * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
 * 'xx_cm0plus.icf'. Do this by either:
 * - Passing the following commands to the compiler:\n
 * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
@@ -212,8 +212,8 @@
 * -# Editing source code files
 * -# Specifying via command line
 *
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
 * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
 *
 * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
@@ -321,6 +321,21 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*     <td>2.90</td>
+*     <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+*     <td>Flash allocation adjustment.</td>
+*   </tr>
+*   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>