diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c index 748b7c7885..f6b2027d4a 100644 --- a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c @@ -35,10 +35,10 @@ int EFlash_IdCheck() { unsigned int eflash_id; - eflash_id = readl(SYS_EFLASH_PIDR2) & (EFLASH_DES_1 | EFLASH_JEDEC); + eflash_id = EFlash_Readl(SYS_EFLASH_PIDR2) & (EFLASH_DES_1 | EFLASH_JEDEC); - if (readl(SYS_EFLASH_PIDR0) != FLS_PID0 - || readl(SYS_EFLASH_PIDR1) != FLS_PID1 + if (EFlash_Readl(SYS_EFLASH_PIDR0) != FLS_PID0 + || EFlash_Readl(SYS_EFLASH_PIDR1) != FLS_PID1 || eflash_id != FLS_PID2) /* port ID and ARM ID does not match */ return 1; @@ -52,7 +52,7 @@ int EFlash_ReturnBank1BaseAddress() unsigned int hwparams0; int baseaddr; - hwparams0 = readl(SYS_EFLASH_HWPARAMS0) & EFLASH_FLASHSIZE; + hwparams0 = EFlash_Readl(SYS_EFLASH_HWPARAMS0) & EFLASH_FLASHSIZE; switch(hwparams0) { @@ -73,31 +73,35 @@ int EFlash_ReturnBank1BaseAddress() return baseaddr; } -/* EFlash_Initialize: eFlash Initialize function */ -void EFlash_Initialize() +/* EFlash_DriverInitialize: eFlash Driver Initialize function */ +void EFlash_DriverInitialize() { /* Find the start address of banks */ eflash.basebank0 = 0x0; eflash.basebank0_me = 0x40000000; eflash.basebank1 = EFlash_ReturnBank1BaseAddress(); eflash.basebank1_me = 0x80000000; +} +/* EFlash_ClockConfig: eFlash Clock Configuration */ +void EFlash_ClockConfig() +{ /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* - * Configure to use external clock - * EXTCL = 31250 ns -> - * 1 ms = 32 clock count 32khz ext_clk -> ER_CLK_COUNT = 32 - * 1 us = 84 clock count system_clk -> WR_CLK_COUNT = 84 - * EXT_CLK_CONF = 0x1 [Erase] External clock used for erase counters (>1ms) - * HCLK used for write counters - * RD_CLK_COUNT = 0x3 - */ - writel(SYS_EFLASH_CONFIG0, 0x00200B43); + * Configure to use external clock + * EXTCL = 31250 ns -> + * 1 ms = 32 clock count 32khz ext_clk -> ER_CLK_COUNT = 32 + * 1 us = 84 clock count system_clk -> WR_CLK_COUNT = 84 + * EXT_CLK_CONF = 0x1 [Erase] External clock used for erase counters (>1ms) + * HCLK used for write counters + * RD_CLK_COUNT = 0x3 + */ + EFlash_Writel(SYS_EFLASH_CONFIG0, 0x00200B43); /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); } /* @@ -116,87 +120,87 @@ void EFlash_Erase(int mode) { case 0: /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #0 */ - writel(SYS_EFLASH_WADDR, eflash.basebank0); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); break; case 1: /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #1 */ - writel(SYS_EFLASH_WADDR, eflash.basebank1); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); break; case 2: /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #0 + info pages */ - writel(SYS_EFLASH_WADDR, eflash.basebank0_me); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0_me); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); break; case 3: /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #1 + info pages */ - writel(SYS_EFLASH_WADDR, eflash.basebank1_me); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1_me); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); break; case 4: /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #0 */ - writel(SYS_EFLASH_WADDR, eflash.basebank0); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #1 */ - writel(SYS_EFLASH_WADDR, eflash.basebank1); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller gets unlocked */ /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); break; case 5: /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #0 + info pages */ - writel(SYS_EFLASH_WADDR, eflash.basebank0_me); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0_me); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); /* Erase Block #1 + info pages */ - writel(SYS_EFLASH_WADDR, eflash.basebank1_me); - writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1_me); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); /* Wait until eFlash controller is not busy */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); break; default: @@ -208,10 +212,10 @@ void EFlash_Erase(int mode) void EFlash_ErasePage(unsigned int waddr) { /* Erase the page starting a waddr */ - writel(SYS_EFLASH_WADDR, waddr); - writel(SYS_EFLASH_CTRL, EFLASH_ERASE); + EFlash_Writel(SYS_EFLASH_WADDR, waddr); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_ERASE); /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); } @@ -224,13 +228,13 @@ void EFlash_ErasePage(unsigned int waddr) void EFlash_Write(unsigned int waddr, unsigned int data) { /* Set Write Data Register */ - writel(SYS_EFLASH_WDATA, data); + EFlash_Writel(SYS_EFLASH_WDATA, data); /* Set Write Address Register */ - writel(SYS_EFLASH_WADDR, waddr); + EFlash_Writel(SYS_EFLASH_WADDR, waddr); /* Start Write Operation through CTRL register */ - writel(SYS_EFLASH_CTRL, EFLASH_WRITE); + EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_WRITE); /* Wait until eFlash controller gets unlocked */ - while ((readl(SYS_EFLASH_STATUS) + while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); /* Flash Cache invalidate if FCache enabled */ @@ -275,7 +279,7 @@ int EFlash_WritePage(unsigned int waddr, unsigned int page_size, */ unsigned int EFlash_Read(unsigned int waddr) { - unsigned int eflash_read = readl(waddr); + unsigned int eflash_read = EFlash_Readl(waddr); return eflash_read; } diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h index 84f278e2a9..cc755631bd 100644 --- a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h @@ -62,8 +62,8 @@ extern "C" { #define EFLASH_REVISION 0xF0 /* Revision number */ /* Macros */ -#define readl(reg) *(volatile unsigned int *)reg -#define writel(reg, val) *(unsigned int *)reg = val; +#define EFlash_Readl(reg) *(volatile unsigned int *)reg +#define EFlash_Writel(reg, val) *(volatile unsigned int *)reg = val; /* peripheral and component ID values */ #define FLS_PID4 0x14 @@ -80,8 +80,12 @@ extern "C" { #define FLS_CID3 0xB1 /* Functions */ -/* EFlash_Initialize: eFlash Initialize function */ -void EFlash_Initialize(void); +/* EFlash_DriverInitialize: eFlash Driver Initialize function */ +void EFlash_DriverInitialize(void); + +/* EFlash_ClockConfig: eFlash Clock Configuration */ +void EFlash_ClockConfig(void); + /* * EFlash_Erase: Erases flash banks * Mode: diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c index a3aa0367f3..b1bb67d4f2 100644 --- a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c @@ -21,22 +21,22 @@ static unsigned int fcache_mode; /* Functions */ /* - * FCache_Initialize: flash cache initialize funtion + * FCache_DriverInitialize: flash cache driver initialize funtion */ -void FCache_Initialize() +void FCache_DriverInitialize() { unsigned int irqstat; /* Clear interrupt status register */ - irqstat = readl(SYS_FCACHE_IRQSTAT) & (FCACHE_POW_ERR | FCACHE_MAN_INV_ERR); - writel(SYS_FCACHE_IRQSTAT, irqstat); + irqstat = FCache_Readl(SYS_FCACHE_IRQSTAT) & (FCACHE_POW_ERR | FCACHE_MAN_INV_ERR); + FCache_Writel(SYS_FCACHE_IRQSTAT, irqstat); /* Cache Disabled: Set enabled to 0 */ enabled = 0; } /* - * FCache_Enable: Enables the flash cache + * FCache_Enable: Enables the flash cache mode * mode: supported modes: * 0 - auto-power auto-invalidate * 1 - manual-power, manual-invalidate @@ -52,9 +52,9 @@ void FCache_Enable(int mode) /* Statistic counters enabled, Cache enable, * auto-inval, auto-power control */ - writel(SYS_FCACHE_CCR, (FCACHE_EN | FCACHE_STATISTIC_EN)); + FCache_Writel(SYS_FCACHE_CCR, (FCACHE_EN | FCACHE_STATISTIC_EN)); /* Wait until the cache is enabled */ - while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED); + while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED); /* Cache Enabled: Set enabled to 1 */ enabled = 1; break; @@ -64,33 +64,33 @@ void FCache_Enable(int mode) * Manual power request (Setting: Power CTRL: * Manual, Invalidate: Manual) */ - writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ + FCache_Writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ | FCACHE_SET_MAN_POW | FCACHE_SET_MAN_INV | FCACHE_STATISTIC_EN)); /* Wait until the cache rams are powered */ - while ((readl(SYS_FCACHE_SR) & FCACHE_POW_STAT) != FCACHE_POW_STAT); + while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_POW_STAT) != FCACHE_POW_STAT); /* Statistic counters enabled, Cache enabled * Manual invalidate request (Setting: Power CTRL: * Manual, Invalidate: Manual) */ - writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ + FCache_Writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ | FCACHE_POW_REQ | FCACHE_SET_MAN_POW | FCACHE_SET_MAN_INV | FCACHE_STATISTIC_EN)); /* Wait until the cache is invalidated */ - while ((readl(SYS_FCACHE_SR) & FCACHE_INV_STAT) == FCACHE_INV_STAT); + while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_INV_STAT) == FCACHE_INV_STAT); /* Statistic counters enabled, Cache enable, * manual-inval, manual-power control */ - writel(SYS_FCACHE_CCR, (FCACHE_EN + FCache_Writel(SYS_FCACHE_CCR, (FCACHE_EN | FCACHE_POW_REQ | FCACHE_SET_MAN_POW | FCACHE_SET_MAN_INV | FCACHE_STATISTIC_EN)); /* Wait until the cache is enabled */ - while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED); + while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED); /* Cache Enabled: Set enabled to 1 */ enabled = 1; break; @@ -100,7 +100,7 @@ void FCache_Enable(int mode) } /* - * FCache_Disable: Disables the cache + * FCache_Disable: Disables the flash cache mode previously enabled */ void FCache_Disable() { @@ -110,9 +110,9 @@ void FCache_Disable() /* Statistic counters enabled, Cache disable, * auto-inval, auto-power control */ - writel(SYS_FCACHE_CCR, FCACHE_STATISTIC_EN); + FCache_Writel(SYS_FCACHE_CCR, FCACHE_STATISTIC_EN); /* Wait until the cache is disabled */ - while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); + while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); /* Cache Enabled: Set enabled to 0 */ enabled = 0; break; @@ -120,12 +120,12 @@ void FCache_Disable() /* Statistic counters enabled, Cache disable, * manual-inval, manual-power control */ - writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ + FCache_Writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ | FCACHE_SET_MAN_POW | FCACHE_SET_MAN_INV | FCACHE_STATISTIC_EN)); /* Wait until the cache is disabled */ - while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); + while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); /* Cache Enabled: Set enabled to 0 */ enabled = 0; break; @@ -151,18 +151,18 @@ int FCache_Invalidate() goto error; /* Trigger INV_REQ */ - writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ + FCache_Writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ | FCACHE_POW_REQ | FCACHE_SET_MAN_POW | FCACHE_SET_MAN_INV | FCACHE_STATISTIC_EN)); /* Wait until INV_REQ is finished */ - while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); + while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); /* Clear Stats */ - writel(SYS_FCACHE_CSHR, 0); - writel(SYS_FCACHE_CSMR, 0); + FCache_Writel(SYS_FCACHE_CSHR, 0); + FCache_Writel(SYS_FCACHE_CSMR, 0); /* Enable Flash Cache */ if (enabled == 0) @@ -183,9 +183,9 @@ unsigned int * FCache_GetStats() static unsigned int stats[2]; /* Cache Statistics HIT Register */ - stats[0] = readl(SYS_FCACHE_CSHR); + stats[0] = FCache_Readl(SYS_FCACHE_CSHR); /* Cache Statistics MISS Register */ - stats[1] = readl(SYS_FCACHE_CSMR); + stats[1] = FCache_Readl(SYS_FCACHE_CSMR); return stats; } @@ -197,4 +197,3 @@ unsigned int FCache_isEnabled() { return enabled; } - diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h index 3060188c4e..dc7d0c50dc 100644 --- a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h @@ -60,18 +60,18 @@ extern "C" { #define FCACHE_MAN_INV_ERR (1 << 1) /* Manual Invalidation error status */ /* Macros */ -#define readl(reg) *(volatile unsigned int *)reg -#define writel(reg, val) *(unsigned int *)reg = val; +#define FCache_Readl(reg) *(volatile unsigned int *)reg +#define FCache_Writel(reg, val) *(volatile unsigned int *)reg = val; /* Functions */ /* - * FCache_Initialize: flash cache initialize funtion + * FCache_DriverInitialize: flash cache driver initialize funtion */ -void FCache_Initialize(void); +void FCache_DriverInitialize(void); /* - * FCache_Enable: Enables the flash cache + * FCache_Enable: Enables the flash cache mode * mode: supported modes: * 0 - auto-power auto-invalidate * 1 - manual-power, manual-invalidate @@ -79,7 +79,7 @@ void FCache_Initialize(void); void FCache_Enable(int mode); /* - * FCache_Disable: Disables the cache + * FCache_Disable: Disables the flash cache mode previously enabled */ void FCache_Disable(void);