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Merge pull request #10213 from d-kato/rza1xx_wait_ns 

GR_LYCHEE,RZ_A1H,VK_RZ_A1H: Fix greentea ticker test case failures
pull/9904/head
Cruz Monrreal 2019-03-27 00:35:33 -05:00 committed by GitHub
parent be38d95383 090fcb007f
commit 54e1ec6ea5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 68 additions and 110 deletions
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5
platform/mbed_wait_api_no_rtos.c
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@ -75,9 +75,8 @@ void wait_us(int us)
#endif #endif
#elif defined __CORTEX_A #elif defined __CORTEX_A
#if __CORTEX_A == 9 #if __CORTEX_A == 9
// Cortex-A9 is dual-issue, so let's assume same performance as Cortex-M7. // Cortex-A9 can dual issue for 3 cycles per iteration (SUB,NOP) = 1, (NOP,BCS) = 2
// TODO - test. #define LOOP_SCALER 3000
#define LOOP_SCALER 2000
#endif #endif
#endif #endif

19
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c
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@ -26,10 +26,8 @@
#include "os_tick.h" #include "os_tick.h"
#include "irq_ctrl.h" #include "irq_ctrl.h"
#include "cmsis.h"
#include <MBRZA1LU.h> #include "mbed_drv_cfg.h"
#include <cmsis.h>
// Define OS TImer interrupt priority // Define OS TImer interrupt priority
@ -62,15 +60,15 @@ int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
// Get CPG.FRQCR[IFC] bits // Get CPG.FRQCR[IFC] bits
clock = (CPG.FRQCR >> 8) & 0x03; clock = (CPG.FRQCR >> 8) & 0x03;
// Determine Divider 2 output clock by using SystemCoreClock // Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK
if (clock == 0x03U) { if (clock == 0x03U) {
clock = (SystemCoreClock * 3U); clock = (RENESAS_RZ_A1_P0_CLK * 3U);
} }
else if (clock == 0x01U) { else if (clock == 0x01U) {
clock = (SystemCoreClock * 3U)/2U; clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U;
} }
else { else {
clock = SystemCoreClock; clock = RENESAS_RZ_A1_P0_CLK;
} }
// Determine tick frequency // Determine tick frequency
@ -144,7 +142,8 @@ void OS_Tick_Enable (void)
} }
/// Disable OS Tick. /// Disable OS Tick.
void OS_Tick_Disable (void) { void OS_Tick_Disable (void)
{
// Stop the OSTM counter // Stop the OSTM counter
OSTM.OSTMnTT = 0x01U; OSTM.OSTMnTT = 0x01U;
@ -156,7 +155,7 @@ void OS_Tick_Disable (void) {
} }
// Acknowledge OS Tick IRQ. // Acknowledge OS Tick IRQ.
void OS_Tick_AcknowledgeIRQ (void) void OS_Tick_AcknowledgeIRQ (void)
{ {
IRQ_ClearPending (OSTM_IRQn); IRQ_ClearPending (OSTM_IRQn);
} }

35
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c
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@ -26,13 +26,10 @@
* limitations under the License. * limitations under the License.
*/ */
#include <RZ_A1LU.h> #include "RZ_A1LU.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "irq_ctrl.h" #include "irq_ctrl.h"
#include "mbed_drv_cfg.h"
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/* /*
Port 0 (P0) MD pin assignment Port 0 (P0) MD pin assignment
@ -45,7 +42,7 @@
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
System Core Clock Variable System Core Clock Variable
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = CM1_RENESAS_RZ_A1_P0_CLK; uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
System Core Clock update function System Core Clock update function
@ -53,22 +50,9 @@ uint32_t SystemCoreClock = CM1_RENESAS_RZ_A1_P0_CLK;
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate (void)
{ {
uint32_t freq; uint32_t freq;
uint16_t mode;
uint16_t ifc; uint16_t ifc;
mode = (GPIO.PPR0 >> 2U) & 0x01U; freq = RENESAS_RZ_A1_SYS_CLK;
if (mode == 0) {
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
} else {
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
}
/* Get CPG.FRQCR[IFC] bits */ /* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U; ifc = (CPG.FRQCR >> 8U) & 0x03U;
@ -77,12 +61,11 @@ void SystemCoreClockUpdate (void)
if (ifc == 0x03U) { if (ifc == 0x03U) {
/* Division ratio is 1/3 */ /* Division ratio is 1/3 */
freq = (freq / 3U); freq = (freq / 3U);
} } else if (ifc == 0x01U) {
else { /* Division ratio is 2/3 */
if (ifc == 0x01U) { freq = (freq * 2U) / 3U;
/* Division ratio is 2/3 */ } else {
freq = (freq * 2U) / 3U; /* do nothing */
}
} }
SystemCoreClock = freq; SystemCoreClock = freq;

5
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h
View File

@ -34,6 +34,11 @@
#define RENESAS_RZ_A1_P0_CLK CM1_RENESAS_RZ_A1_P0_CLK #define RENESAS_RZ_A1_P0_CLK CM1_RENESAS_RZ_A1_P0_CLK
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
#define RENESAS_RZ_A1_SYS_CLK ((CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U)
#define LP_TICKER_MTU2_CH 2 #define LP_TICKER_MTU2_CH 2
/* flash (W25Q64JV) */ /* flash (W25Q64JV) */

14
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c
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@ -26,10 +26,8 @@
#include "os_tick.h" #include "os_tick.h"
#include "irq_ctrl.h" #include "irq_ctrl.h"
#include "cmsis.h"
#include <MBRZA1H.h> #include "mbed_drv_cfg.h"
#include <cmsis.h>
// Define OS TImer interrupt priority // Define OS TImer interrupt priority
@ -62,15 +60,15 @@ int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
// Get CPG.FRQCR[IFC] bits // Get CPG.FRQCR[IFC] bits
clock = (CPG.FRQCR >> 8) & 0x03; clock = (CPG.FRQCR >> 8) & 0x03;
// Determine Divider 2 output clock by using SystemCoreClock // Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK
if (clock == 0x03U) { if (clock == 0x03U) {
clock = (SystemCoreClock * 3U); clock = (RENESAS_RZ_A1_P0_CLK * 3U);
} }
else if (clock == 0x01U) { else if (clock == 0x01U) {
clock = (SystemCoreClock * 3U)/2U; clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U;
} }
else { else {
clock = SystemCoreClock; clock = RENESAS_RZ_A1_P0_CLK;
} }
// Determine tick frequency // Determine tick frequency

35
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c
View File

@ -26,13 +26,10 @@
* limitations under the License. * limitations under the License.
*/ */
#include <RZ_A1H.h> #include "RZ_A1H.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "irq_ctrl.h" #include "irq_ctrl.h"
#include "mbed_drv_cfg.h"
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/* /*
Port 0 (P0) MD pin assignment Port 0 (P0) MD pin assignment
@ -45,7 +42,7 @@
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
System Core Clock Variable System Core Clock Variable
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK; uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
System Core Clock update function System Core Clock update function
@ -53,22 +50,9 @@ uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate (void)
{ {
uint32_t freq; uint32_t freq;
uint16_t mode;
uint16_t ifc; uint16_t ifc;
mode = (GPIO.PPR0 >> 2U) & 0x01U; freq = RENESAS_RZ_A1_SYS_CLK;
if (mode == 0) {
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
} else {
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
}
/* Get CPG.FRQCR[IFC] bits */ /* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U; ifc = (CPG.FRQCR >> 8U) & 0x03U;
@ -77,12 +61,11 @@ void SystemCoreClockUpdate (void)
if (ifc == 0x03U) { if (ifc == 0x03U) {
/* Division ratio is 1/3 */ /* Division ratio is 1/3 */
freq = (freq / 3U); freq = (freq / 3U);
} } else if (ifc == 0x01U) {
else { /* Division ratio is 2/3 */
if (ifc == 0x01U) { freq = (freq * 2U) / 3U;
/* Division ratio is 2/3 */ } else {
freq = (freq * 2U) / 3U; /* do nothing */
}
} }
SystemCoreClock = freq; SystemCoreClock = freq;

5
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h
View File

@ -34,6 +34,11 @@
#define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK #define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
#define RENESAS_RZ_A1_SYS_CLK (CM0_RENESAS_RZ_A1_CLKIN * 30U)
#define LP_TICKER_MTU2_CH 3 #define LP_TICKER_MTU2_CH 3
/* flash (MX25L6433FM2I) */ /* flash (MX25L6433FM2I) */

14
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c
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@ -26,10 +26,8 @@
#include "os_tick.h" #include "os_tick.h"
#include "irq_ctrl.h" #include "irq_ctrl.h"
#include "cmsis.h"
#include <VKRZA1H.h> #include "mbed_drv_cfg.h"
#include <cmsis.h>
// Define OS TImer interrupt priority // Define OS TImer interrupt priority
@ -62,15 +60,15 @@ int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
// Get CPG.FRQCR[IFC] bits // Get CPG.FRQCR[IFC] bits
clock = (CPG.FRQCR >> 8) & 0x03; clock = (CPG.FRQCR >> 8) & 0x03;
// Determine Divider 2 output clock by using SystemCoreClock // Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK
if (clock == 0x03U) { if (clock == 0x03U) {
clock = (SystemCoreClock * 3U); clock = (RENESAS_RZ_A1_P0_CLK * 3U);
} }
else if (clock == 0x01U) { else if (clock == 0x01U) {
clock = (SystemCoreClock * 3U)/2U; clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U;
} }
else { else {
clock = SystemCoreClock; clock = RENESAS_RZ_A1_P0_CLK;
} }
// Determine tick frequency // Determine tick frequency

41
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c
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@ -26,13 +26,10 @@
* limitations under the License. * limitations under the License.
*/ */
#include <VK_RZ_A1H.h> #include "VK_RZ_A1H.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "irq_ctrl.h" #include "irq_ctrl.h"
#include "mbed_drv_cfg.h"
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/* /*
Port 0 (P0) MD pin assignment Port 0 (P0) MD pin assignment
@ -45,48 +42,34 @@
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
System Core Clock Variable System Core Clock Variable
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK; uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
System Core Clock update function System Core Clock update function
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate (void)
{ {
uint32_t freq; uint32_t freq;
uint16_t mode;
uint16_t ifc; uint16_t ifc;
mode = (GPIO.PPR0 >> 2U) & 0x01U; freq = RENESAS_RZ_A1_SYS_CLK;
if (mode == 0) {
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
} else {
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
}
/* Get CPG.FRQCR[IFC] bits */ /* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U; ifc = (CPG.FRQCR >> 8U) & 0x03U;
/* Determine Divider 2 output clock */ /* Determine Divider 2 output clock */
if (ifc == 0x03U) { if (ifc == 0x03U) {
/* Division ratio is 1/3 */ /* Division ratio is 1/3 */
freq = (freq / 3U); freq = (freq / 3U);
} else if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
} else {
/* do nothing */
} }
else {
if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
}
}
SystemCoreClock = freq; SystemCoreClock = freq;
} }
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
IRQ Handler Register/Unregister IRQ Handler Register/Unregister

5
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h
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@ -34,4 +34,9 @@
#define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK #define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
#define RENESAS_RZ_A1_SYS_CLK (CM0_RENESAS_RZ_A1_CLKIN * 30U)
#endif #endif