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Moved TriggerMux initialization out of the HAL and into the BSP since that is what dictates what trigger muxes actually need to be used

pull/11590/head
Ryan Morse 2019-09-26 13:40:33 -07:00
parent 372a3f19c9
commit 54d962a240
7 changed files with 34 additions and 11 deletions
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1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c
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@ -141,6 +141,7 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb)
if ( !udb_initialized )
{
udb_initialized = 1;
SDIO_Host_Config_TriggerMuxes();
SDIO_Host_Config_UDBs();
}

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c
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@ -969,6 +969,20 @@ static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
{(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u},
};
void SDIO_Host_Config_TriggerMuxes(void)
{
/* Connect UDB to DMA */
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL);
}
void SDIO_Host_Config_UDBs(void)
{
size_t i;

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h
View File

@ -892,6 +892,8 @@ extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
/* The peripheral clock divider type */
#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT)
/*Function for configuring TriggerMuxes*/
void SDIO_Host_Config_TriggerMuxes(void);
/*Function for configuring UDBs*/
void SDIO_Host_Config_UDBs(void);

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c
View File

@ -141,6 +141,7 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb)
if ( !udb_initialized )
{
udb_initialized = 1;
SDIO_Host_Config_TriggerMuxes();
SDIO_Host_Config_UDBs();
}

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c
View File

@ -969,6 +969,20 @@ static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
{(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u},
};
void SDIO_Host_Config_TriggerMuxes(void)
{
/* Connect UDB to DMA */
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL);
}
void SDIO_Host_Config_UDBs(void)
{
size_t i;

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h
View File

@ -892,6 +892,8 @@ extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc;
/* The peripheral clock divider type */
#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT)
/*Function for configuring TriggerMuxes*/
void SDIO_Host_Config_TriggerMuxes(void);
/*Function for configuring UDBs*/
void SDIO_Host_Config_UDBs(void);

11
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c
View File

@ -462,17 +462,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
Cy_SysInt_Init(&irqDma1_3, &SDIO_READ_DMA_IRQ);
NVIC_EnableIRQ(cpuss_interrupts_dw1_3_IRQn);
/* Connect UDB to DMA */
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL);
stc_sdio_irq_cb_t irq_cbs;
irq_cbs.pfnCardIntCb = cyhal_sdio_interrupts_dispatcher_IRQHandler;