diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.c b/features/mbedtls/targets/TARGET_STM/aes_alt.c index 84d3ed2c64..835827e044 100644 --- a/features/mbedtls/targets/TARGET_STM/aes_alt.c +++ b/features/mbedtls/targets/TARGET_STM/aes_alt.c @@ -103,11 +103,19 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx) if (ctx == NULL) { return; } +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ /* Force the CRYP Periheral Clock Reset */ __HAL_RCC_CRYP_FORCE_RESET(); /* Release the CRYP Periheral Clock Reset */ __HAL_RCC_CRYP_RELEASE_RESET(); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ mbedtls_zeroize(ctx, sizeof(mbedtls_aes_context)); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c index f6f63a0147..76e6beb4f9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c @@ -198,14 +198,14 @@ MBED_WEAK const PinMap PinMap_I2C_SCL[] = { // You have to comment all PWM using TIM_MST defined in hal_tick.h file // or update python script (check TIM_MST_LIST) and re-run it MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS - {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PMOD\#1- USART2_CTS_NSS - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK - {PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK - {PA_1_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO - {PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO - {PA_2_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS +// {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PMOD\#1- USART2_CTS_NSS +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK +// {PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO +// {PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ULPI_D0 {PA_3_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ULPI_D0 {PA_3_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 // Connected to ULPI_D0 diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S new file mode 100644 index 0000000000..65b774c60d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S @@ -0,0 +1,574 @@ +;******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h747xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD DSI_IRQHandler ; DSI global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT CM7_SEV_IRQHandler [WEAK] + EXPORT CM4_SEV_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT HSEM2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT WWDG_RST_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT HOLD_CORE_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +CM7_SEV_IRQHandler +CM4_SEV_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +DSI_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +HSEM2_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +WWDG_RST_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +HOLD_CORE_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/stm32h747xI_CM4.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/stm32h747xI_CM4.sct new file mode 100644 index 0000000000..07df525113 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/stm32h747xI_CM4.sct @@ -0,0 +1,51 @@ +#! armcc -E +; Scatter-Loading Description File +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08100000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define Stack_Size MBED_BOOT_STACK_SIZE + +#define MBED_RAM_START 0x10000000 +#define MBED_RAM_SIZE 0x48000 +#define MBED_VECTTABLE_RAM_START (MBED_RAM_START) +#define MBED_VECTTABLE_RAM_SIZE 0x298 +#define MBED_RAM0_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld new file mode 100644 index 0000000000..17bb27d67b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld @@ -0,0 +1,182 @@ +/* Linker script to configure memory regions. */ +/******************************************************************************* + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08100000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 1024K +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = 0x10000298, LENGTH = 288K - 0x298 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S new file mode 100644 index 0000000000..ceee064d18 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S @@ -0,0 +1,771 @@ +/** + ****************************************************************************** + * @file startup_stm32h747xx.s + * @author MCD Application Team + * @brief STM32H747xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */ + .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */ + .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ + .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ + .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ + .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ + .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ + .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ + .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ + .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word SAI3_IRQHandler /* SAI3 global Interrupt */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word DSI_IRQHandler /* DSI global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word HSEM2_IRQHandler /* HSEM1 global Interrupt */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word 0 /* Reserved */ + .word HOLD_CORE_IRQHandler /* Hold core interrupt */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak CM7_SEV_IRQHandler + .thumb_set CM7_SEV_IRQHandler,Default_Handler + + .weak CM4_SEV_IRQHandler + .thumb_set CM4_SEV_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_OUT_IRQHandler + .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_IN_IRQHandler + .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SAI3_IRQHandler + .thumb_set SAI3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak HSEM2_IRQHandler + .thumb_set HSEM2_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WWDG_RST_IRQHandler + .thumb_set WWDG_RST_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak HOLD_CORE_IRQHandler + .thumb_set HOLD_CORE_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_IAR/startup_stm32h747xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_IAR/startup_stm32h747xx.S new file mode 100644 index 0000000000..1d9887a66a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_IAR/startup_stm32h747xx.S @@ -0,0 +1,1009 @@ +;/******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h747xx.s +;* Author : MCD Application Team +;* Description : STM32H747xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD DSI_IRQHandler ; DSI global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_AVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_AVD_IRQHandler + B PVD_AVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler + B CM7_SEV_IRQHandler + + PUBWEAK CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler + B CM4_SEV_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler + + PUBWEAK OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler + B OTG_FS_EP1_IN_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler + + PUBWEAK HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler + + PUBWEAK HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler + + PUBWEAK HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler + + PUBWEAK HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler + B HRTIM1_TIMD_IRQHandler + + PUBWEAK HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler + B HRTIM1_TIME_IRQHandler + + PUBWEAK HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler + B HRTIM1_FLT_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler + B SAI3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DSI_IRQHandler + B DSI_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler + B HSEM2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler + B BDMA_Channel0_IRQHandler + + PUBWEAK BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler + B BDMA_Channel1_IRQHandler + + PUBWEAK BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler + B BDMA_Channel2_IRQHandler + + PUBWEAK BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler + B BDMA_Channel3_IRQHandler + + PUBWEAK BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler + B BDMA_Channel4_IRQHandler + + PUBWEAK BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler + B BDMA_Channel5_IRQHandler + + PUBWEAK BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler + B BDMA_Channel6_IRQHandler + + PUBWEAK BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler + B BDMA_Channel7_IRQHandler + + PUBWEAK COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler + B COMP1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler + B WWDG_RST_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler + B SAI4_IRQHandler + + PUBWEAK HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler + B HOLD_CORE_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_IAR/stm32h747xI_CM4.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_IAR/stm32h747xI_CM4.icf new file mode 100644 index 0000000000..b97abc7c7e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_IAR/stm32h747xI_CM4.icf @@ -0,0 +1,48 @@ +//****************************************************************************** +//* @attention +//* +//* Copyright (c) 2019 STMicroelectronics. +//* All rights reserved. +//* +//* This software component is licensed by ST under BSD 3-Clause license, +//* the "License"; You may not use this file except in compliance with the +//* License. You may obtain a copy of the License at: +//* opensource.org/licenses/BSD-3-Clause +//* +//****************************************************************************** + +// 1MB FLASH (0x100000) +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08100000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } + +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; + +// Vector table dynamic copy: 166 vectors = 664 bytes (0x298) reserved +define symbol __NVIC_start__ = 0x10000000; +define symbol __NVIC_end__ = 0x10000297; +define symbol __region_RAM_start__ = 0x10000298; // Aligned on 8 bytes +define symbol __region_RAM_end__ = 0x10000000 + 0x48000 - 1; + + +// Memory regions +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +// Stack and Heap +define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; +define symbol __size_heap__ = 0x10000; // 64KB +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S index 317b969fbd..65b774c60d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S @@ -24,7 +24,7 @@ ;* ;****************************************************************************** -__initial_sp EQU 0x20020000 ; Top of RAM + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| PRESERVE8 THUMB @@ -36,7 +36,7 @@ __initial_sp EQU 0x20020000 ; Top of RAM EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct index a68f4cf7ee..4a2b772060 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct @@ -18,7 +18,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x200000 + #define MBED_APP_SIZE 0x100000 #endif #if !defined(MBED_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld index 9a4969bec9..bba6ca3a7a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld @@ -18,7 +18,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 2048K + #define MBED_APP_SIZE 1024K #endif #if !defined(MBED_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf index 3408ed389f..19c2ac2c77 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf @@ -11,9 +11,9 @@ //* //****************************************************************************** -// 2MB FLASH (0x200000) +// 1MB FLASH (0x100000) if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } define symbol __intvec_start__ = MBED_APP_START; @@ -27,6 +27,11 @@ define symbol __NVIC_end__ = 0x20000297; define symbol __region_RAM_start__ = 0x20000298; // Aligned on 8 bytes define symbol __region_RAM_end__ = 0x20000000 + 0x20000 - 1; +// 64KB ITCM RAM (0x10000) +// ITCM not currently used, but could be used for critical code to improve performances +define symbol __region_ITCMRAM_start__ = 0x00000000; +define symbol __region_ITCMRAM_end__ = 0x0000FFFF; + // Memory regions define memory mem with size = 4G; define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c new file mode 100644 index 0000000000..1f71d75495 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c @@ -0,0 +1,23 @@ +/* mbed Microcontroller Library + ******************************************************************************* + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * SPDX-License-Identifier: BSD-3-Clause + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + ******************************************************************************* + */ +#if DEVICE_SLEEP + +/* Deepsleep temporarily not supported on STM32H747I + * wrap it to sleep + */ +void hal_deepsleep(void) +{ + hal_sleep(); +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index 398a23f853..5b593736c1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -88,8 +88,16 @@ void analogin_init(analogin_t *obj, PinName pin) PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP; PeriphClkInitStruct.PLL2.PLL2P = 4; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_CLKP); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ #if defined(ADC1) if ((ADCName)obj->handle.Instance == ADC_1) { diff --git a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c index 1bd2e96847..1186f8c28a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c @@ -26,8 +26,16 @@ static uint32_t GetSectorSize(uint32_t Sector); int32_t flash_init(flash_t *obj) { +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ /* Clear pending flags (if any) */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_WRPERR); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ return 0; } @@ -49,7 +57,15 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return -1; } +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ if (HAL_FLASH_Unlock() != HAL_OK) { +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ return -1; } @@ -76,7 +92,9 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) } HAL_FLASH_Lock(); - +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ return status; } @@ -95,7 +113,15 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, return -1; } +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ if (HAL_FLASH_Unlock() != HAL_OK) { +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ return -1; } @@ -110,6 +136,9 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, } HAL_FLASH_Lock(); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ return status; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h index 2a6e60dba6..42fa1a1b33 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -37,6 +37,12 @@ #include "stm32h7xx_ll_usart.h" #include "stm32h7xx_ll_rtc.h" #include "stm32h7xx_ll_tim.h" +#if defined(DUAL_CORE) +#include "stm32h7xx_ll_hsem.h" +#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_pwr.h" +#include "stm32h7xx_ll_cortex.h" +#endif /* CONFIG_STM32H7_DUAL_CORE */ #ifdef __cplusplus extern "C" { @@ -141,6 +147,30 @@ struct analogin_s { }; #define GPIO_IP_WITHOUT_BRR + +#if defined(DUAL_CORE) +/* HW semaphore Complement ID list defined in hw_conf.h from STM32WB */ +/* Index of the semaphore used to manage the entry Stop Mode procedure */ +#define CFG_HW_ENTRY_STOP_MODE_SEMID 4 +#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1 << CFG_HW_ENTRY_STOP_MODE_SEMID) + +/* Index of the semaphore used to access the RCC */ +#define CFG_HW_RCC_SEMID 3 + +/* Index of the semaphore used to access the FLASH */ +#define CFG_HW_FLASH_SEMID 2 + +/* Index of the semaphore used to access the PKA */ +#define CFG_HW_PKA_SEMID 1 + +/* Index of the semaphore used to access the RNG */ +#define CFG_HW_RNG_SEMID 0 + +/* Index of the semaphore used to access GPIO */ +#define CFG_HW_GPIO_SEMID 5 + +#define HSEM_TIMEOUT 0xFFFF +#endif /* DUAL_CORE */ #include "gpio_object.h" struct dac_s { diff --git a/targets/TARGET_STM/TARGET_STM32H7/pin_device.h b/targets/TARGET_STM/TARGET_STM32H7/pin_device.h index b622bb3bee..eb459d54a6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32H7/pin_device.h @@ -32,6 +32,7 @@ #include "cmsis.h" #include "stm32h7xx_ll_gpio.h" +#include "objects.h" extern const uint32_t ll_pin_defines[16]; @@ -43,6 +44,12 @@ static inline void stm_pin_DisconnectDebug(PinName pin) static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config) { +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ + switch (pull_config) { case GPIO_PULLUP: LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP); @@ -54,17 +61,31 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_NO); break; } + +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); } + +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32H7/us_ticker_data.h index a3275a5bfc..36619800e1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32H7/us_ticker_data.h @@ -17,13 +17,15 @@ #define __US_TICKER_DATA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "stm32h7xx.h" #include "stm32h7xx_ll_tim.h" #include "cmsis_nvic.h" +#if defined(DUAL_CORE) +#if defined(CORE_CM7) #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() @@ -36,6 +38,36 @@ #define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) +#elif defined(CORE_CM4) +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#define TIM_MST_BIT_WIDTH 32 // 16 or 32 + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) +#else +#error "Core not supported" +#endif +#else +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define TIM_MST_BIT_WIDTH 32 // 16 or 32 + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) +#endif + + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 7ab05cb9cf..10fe11517e 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -90,10 +90,17 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80) +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { error("HAL_RCCEx_PeriphCLKConfig error\n"); } - +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Configure CAN pins pinmap_pinout(rd, PinMap_CAN_RD); pinmap_pinout(td, PinMap_CAN_TD); @@ -182,8 +189,16 @@ void can_irq_free(can_t *obj) void can_free(can_t *obj) { +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ __HAL_RCC_FDCAN_FORCE_RESET(); __HAL_RCC_FDCAN_RELEASE_RESET(); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ __HAL_RCC_FDCAN_CLK_DISABLE(); } @@ -622,6 +637,11 @@ void can_irq_free(can_t *obj) void can_free(can_t *obj) { CANName can = (CANName) obj->CanHandle.Instance; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ // Reset CAN and disable clock if (can == CAN_1) { __HAL_RCC_CAN1_FORCE_RESET(); @@ -642,6 +662,9 @@ void can_free(can_t *obj) __HAL_RCC_CAN3_CLK_DISABLE(); } #endif +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } // The following table is used to program bit_timing. It is an adjustment of the sample diff --git a/targets/TARGET_STM/gpio_api.c b/targets/TARGET_STM/gpio_api.c index 02e6a5ca16..cfea965ee8 100644 --- a/targets/TARGET_STM/gpio_api.c +++ b/targets/TARGET_STM/gpio_api.c @@ -155,10 +155,20 @@ void gpio_mode(gpio_t *obj, PinMode mode) inline void gpio_dir(gpio_t *obj, PinDirection direction) { +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ + if (direction == PIN_INPUT) { LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT); } else { LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT); } + +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } diff --git a/targets/TARGET_STM/gpio_object.h b/targets/TARGET_STM/gpio_object.h index 230c8a0e26..a9c13b5b0a 100644 --- a/targets/TARGET_STM/gpio_object.h +++ b/targets/TARGET_STM/gpio_object.h @@ -57,6 +57,12 @@ typedef struct { static inline void gpio_write(gpio_t *obj, int value) { +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ + if (value) { *obj->reg_set = obj->mask; } else { @@ -66,6 +72,10 @@ static inline void gpio_write(gpio_t *obj, int value) *obj->reg_clr = obj->mask; #endif } + +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } static inline int gpio_read(gpio_t *obj) diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 995bda07cb..09c2346e7a 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -214,6 +214,11 @@ void i2c_hw_reset(i2c_t *obj) // wait before reset timeout = BYTE_TIMEOUT; while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0)); +#if defined(DUAL_CORE) + timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ #if defined I2C1_BASE if (obj_s->i2c == I2C_1) { __HAL_RCC_I2C1_FORCE_RESET(); @@ -244,6 +249,9 @@ void i2c_hw_reset(i2c_t *obj) __HAL_RCC_FMPI2C1_RELEASE_RESET(); } #endif +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } void i2c_sw_reset(i2c_t *obj) @@ -405,6 +413,11 @@ void i2c_frequency(i2c_t *obj, int hz) #endif //I2C_IP_VERSION_V2 /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/ +#if defined(DUAL_CORE) + timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG) if (obj_s->i2c == I2C_1) { __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC); @@ -425,6 +438,9 @@ void i2c_frequency(i2c_t *obj, int hz) __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC); } #endif +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ #ifdef I2C_ANALOGFILTER_ENABLE /* Enable the Analog I2C Filter */ diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index 1cd5c1e05f..8844bdac92 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -54,6 +54,59 @@ * between is unreliable */ #define LP_TIMER_SAFE_GUARD 5 + +#if defined(DUAL_CORE) +#if defined(CORE_CM7) +#define LPTIM_MST_BASE LPTIM4_BASE +#define LPTIM_MST ((LPTIM_TypeDef *)LPTIM_MST_BASE) + +#define RCC_PERIPHCLK_LPTIM RCC_PERIPHCLK_LPTIM4 +#define RCC_LPTIMCLKSOURCE_LSE RCC_LPTIM4CLKSOURCE_LSE +#define RCC_LPTIMCLKSOURCE_LSI RCC_LPTIM4CLKSOURCE_LSI + +#define LPTIM_MST_IRQ LPTIM4_IRQn +#define LPTIM_MST_RCC __HAL_RCC_LPTIM4_CLK_ENABLE + +#define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM4_FORCE_RESET +#define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM4_RELEASE_RESET + +//#define LPTIM_MST_BIT_WIDTH 32 // 16 or 32 + +//#define LPTIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + +#elif defined(CORE_CM4) +#define LPTIM_MST_BASE LPTIM5_BASE +#define LPTIM_MST ((LPTIM_TypeDef *)LPTIM_MST_BASE) + +#define RCC_PERIPHCLK_LPTIM RCC_PERIPHCLK_LPTIM5 +#define RCC_LPTIMCLKSOURCE_LSE RCC_LPTIM5CLKSOURCE_LSE +#define RCC_LPTIMCLKSOURCE_LSI RCC_LPTIM5CLKSOURCE_LSI + +#define LPTIM_MST_IRQ LPTIM5_IRQn +#define LPTIM_MST_RCC __HAL_RCC_LPTIM5_CLK_ENABLE + +#define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM5_FORCE_RESET +#define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM5_RELEASE_RESET +#else +#error "Core not supported" +#endif +#else +#define LPTIM_MST_BASE LPTIM1_BASE +#define LPTIM_MST ((LPTIM_TypeDef *)LPTIM_MST_BASE) + +#define RCC_PERIPHCLK_LPTIM RCC_PERIPHCLK_LPTIM1 +#define RCC_LPTIMCLKSOURCE_LSE RCC_LPTIM1CLKSOURCE_LSE +#define RCC_LPTIMCLKSOURCE_LSI RCC_LPTIM1CLKSOURCE_LSI + +#define LPTIM_MST_IRQ LPTIM1_IRQn +#define LPTIM_MST_RCC __HAL_RCC_LPTIM1_CLK_ENABLE + +#define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM1_FORCE_RESET +#define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM1_RELEASE_RESET +#endif + + + LPTIM_HandleTypeDef LptimHandle; const ticker_info_t *lp_ticker_get_info() @@ -81,7 +134,7 @@ volatile timestamp_t lp_delayed_counter = 0; volatile bool sleep_manager_locked = false; static int LPTICKER_inited = 0; -static void LPTIM1_IRQHandler(void); +static void LPTIM_IRQHandler(void); void lp_ticker_init(void) { @@ -103,13 +156,16 @@ void lp_ticker_init(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Select the LSE clock as LPTIM peripheral clock */ - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM; #if (TARGET_STM32L0) - RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSE; + RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSE; #else - RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE; -#endif - +#if (LPTIM_MST_BASE == LPTIM1_BASE) + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSE; +#elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE) + RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSE; +#endif /* LPTIM_MST_BASE == LPTIM1 */ +#endif /* TARGET_STM32L0 */ #else /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable LSI clock */ @@ -122,15 +178,23 @@ void lp_ticker_init(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Select the LSI clock as LPTIM peripheral clock */ - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM; #if (TARGET_STM32L0) - RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSI; + RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSI; #else - RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; -#endif +#if (LPTIM_MST_BASE == LPTIM1_BASE) + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSI; +#elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE) + RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSI; +#endif /* LPTIM_MST_BASE == LPTIM1 */ +#endif /* TARGET_STM32L0 */ #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ - +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { error("HAL_RCC_OscConfig ERROR\n"); return; @@ -141,12 +205,15 @@ void lp_ticker_init(void) return; } - __HAL_RCC_LPTIM1_CLK_ENABLE(); - __HAL_RCC_LPTIM1_FORCE_RESET(); - __HAL_RCC_LPTIM1_RELEASE_RESET(); + LPTIM_MST_RCC(); + LPTIM_MST_RESET_ON(); + LPTIM_MST_RESET_OFF(); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ /* Initialize the LPTIM peripheral */ - LptimHandle.Instance = LPTIM1; + LptimHandle.Instance = LPTIM_MST; LptimHandle.State = HAL_LPTIM_STATE_RESET; LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; #if defined(MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK) @@ -182,7 +249,7 @@ void lp_ticker_init(void) return; } - NVIC_SetVector(LPTIM1_IRQn, (uint32_t)LPTIM1_IRQHandler); + NVIC_SetVector(LPTIM_MST_IRQ, (uint32_t)LPTIM_IRQHandler); #if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT) /* EXTI lines are not configured by default */ @@ -208,7 +275,7 @@ void lp_ticker_init(void) lp_cmpok = true; } -static void LPTIM1_IRQHandler(void) +static void LPTIM_IRQHandler(void) { core_util_critical_section_enter(); @@ -275,11 +342,11 @@ static void LPTIM1_IRQHandler(void) uint32_t lp_ticker_read(void) { - uint32_t lp_time = LPTIM1->CNT; + uint32_t lp_time = LPTIM_MST->CNT; /* Reading the LPTIM_CNT register may return unreliable values. It is necessary to perform two consecutive read accesses and verify that the two returned values are identical */ - while (lp_time != LPTIM1->CNT) { - lp_time = LPTIM1->CNT; + while (lp_time != LPTIM_MST->CNT) { + lp_time = LPTIM_MST->CNT; } return lp_time; } @@ -293,7 +360,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp) /* Always store the last requested timestamp */ lp_delayed_counter = timestamp; - NVIC_EnableIRQ(LPTIM1_IRQn); + NVIC_EnableIRQ(LPTIM_MST_IRQ); /* CMPOK is set by hardware to inform application that the APB bus write operation to the * LPTIM_CMP register has been successfully completed. @@ -377,8 +444,8 @@ void lp_ticker_fire_interrupt(void) lp_Fired = 1; /* In case we fire interrupt now, then cancel pending programing */ lp_delayed_prog = false; - NVIC_SetPendingIRQ(LPTIM1_IRQn); - NVIC_EnableIRQ(LPTIM1_IRQn); + NVIC_SetPendingIRQ(LPTIM_MST_IRQ); + NVIC_EnableIRQ(LPTIM_MST_IRQ); core_util_critical_section_exit(); } @@ -399,8 +466,8 @@ void lp_ticker_disable_interrupt(void) } lp_delayed_prog = false; lp_Fired = 0; - NVIC_DisableIRQ(LPTIM1_IRQn); - NVIC_ClearPendingIRQ(LPTIM1_IRQn); + NVIC_DisableIRQ(LPTIM_MST_IRQ); + NVIC_ClearPendingIRQ(LPTIM_MST_IRQ); core_util_critical_section_exit(); } @@ -409,7 +476,7 @@ void lp_ticker_clear_interrupt(void) { core_util_critical_section_enter(); __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM); - NVIC_ClearPendingIRQ(LPTIM1_IRQn); + NVIC_ClearPendingIRQ(LPTIM_MST_IRQ); core_util_critical_section_exit(); } diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index e74d4960d4..4f0e0bbcab 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "cmsis.h" +#include "objects.h" int mbed_sdk_inited = 0; extern void SetSysClock(void); @@ -46,6 +47,56 @@ void mbed_sdk_init() } #endif /* __ICACHE_PRESENT */ +#if defined(DUAL_CORE) + /* HW semaphore Clock enable*/ + __HAL_RCC_HSEM_CLK_ENABLE(); + +#if defined(CORE_CM4) + __HAL_RCC_FLASH_C2_ALLOCATE(); + + /* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization. + otherwise wait for CM7, which is in charge of sytem clock configuration */ + if (!LL_RCC_IsCM4BootForced()) { + /* CM4 boots at the same time than CM7. It is necessary to synchronize with CM7, by mean of HSEM, that CM7 finishes its initialization. */ + + /* Activate HSEM notification for Cortex-M4*/ + LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID); + + /* + * Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for + * Cortex-M7 to perform system initialization (system clock config, + * external memory configuration.. ) + */ + + /* Select the domain Power Down DeepSleep */ + LL_PWR_SetRegulModeDS(LL_PWR_REGU_DSMODE_MAIN); + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + LL_PWR_CPU_SetD2PowerMode(LL_PWR_CPU_MODE_D2STOP); + LL_PWR_CPU2_SetD2PowerMode(LL_PWR_CPU2_MODE_D2STOP); + /* Set SLEEPDEEP bit of Cortex System Control Register */ + LL_LPM_EnableDeepSleep(); + + /* Ensure that all instructions done before entering STOP mode */ + __DSB(); + __ISB(); + /* Request Wait For Event */ + __WFE(); + + /* Reset SLEEPDEEP bit of Cortex System Control Register, + * the following LL API Clear SLEEPDEEP bit of Cortex + * System Control Register + */ + LL_LPM_EnableSleep(); + + /* Clear HSEM flag */ + LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID); + } + + // Update the SystemCoreClock variable. + SystemCoreClockUpdate(); + HAL_Init(); +#else + /* CORE_M7 */ // Update the SystemCoreClock variable. SystemCoreClockUpdate(); HAL_Init(); @@ -55,6 +106,29 @@ void mbed_sdk_init() SetSysClock(); SystemCoreClockUpdate(); + /* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization. + otherwise CM7 should wakeup CM4 when system clocks initialization is done. */ + if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) { + LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID); + /*Release HSEM in order to notify the CPU2(CM4)*/ + LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0); + } else { + LL_RCC_ForceCM4Boot(); + } + /* wait until CPU2 wakes up from stop mode */ + while (LL_RCC_D2CK_IsReady() == 0); +#endif /* CORE_M4 */ +#else /* Single core */ + // Update the SystemCoreClock variable. + SystemCoreClockUpdate(); + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + SystemCoreClockUpdate(); +#endif /* DUAL_CORE */ + /* Start LSI clock for RTC */ #if DEVICE_RTC #if !MBED_CONF_TARGET_LSE_AVAILABLE diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index 1331d4eba7..336cc133f5 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -70,7 +70,7 @@ void pin_function(PinName pin, int data) uint32_t ll_mode = 0; // Enable GPIO clock - GPIO_TypeDef * const gpio = Set_GPIO_Clock(port); + GPIO_TypeDef *const gpio = Set_GPIO_Clock(port); /* Set default speed to high. * For most families there are dedicated registers so it is @@ -80,6 +80,11 @@ void pin_function(PinName pin, int data) #if defined (TARGET_STM32F1) if (mode == STM_PIN_OUTPUT) { #endif +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ switch (speed) { /* Default value for backward compatibility */ case STM_PIN_SPEED_MASK: @@ -93,6 +98,9 @@ void pin_function(PinName pin, int data) LL_GPIO_SetPinSpeed(gpio, ll_pin, speed); break; } +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ #if defined (TARGET_STM32F1) } #endif @@ -116,6 +124,12 @@ void pin_function(PinName pin, int data) MBED_ASSERT(0); break; } + +#if defined(DUAL_CORE) + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ + LL_GPIO_SetPinMode(gpio, ll_pin, ll_mode); #if defined(GPIO_ASCR_ASC0) @@ -139,6 +153,10 @@ void pin_function(PinName pin, int data) stm_pin_PullConfig(gpio, ll_pin, STM_PIN_PUPD(data)); stm_pin_DisconnectDebug(pin); + +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } /** @@ -152,6 +170,13 @@ void pin_mode(PinName pin, PinMode mode) uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; // Enable GPIO clock GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index); + +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ + uint32_t function = LL_GPIO_GetPinMode(gpio, ll_pin); if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE)) { @@ -169,4 +194,8 @@ void pin_mode(PinName pin, PinMode mode) } else { stm_pin_PullConfig(gpio, ll_pin, GPIO_NOPULL); } + +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index 8528968c74..097ed143da 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -46,7 +46,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef *st_command) { debug_if(qspi_api_c_debug, "qspi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n", - command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); + command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); st_command->FlashId = HAL_OSPI_FLASH_ID_1; @@ -101,7 +101,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm error("Command param error: wrong address size\n"); return QSPI_STATUS_ERROR; } - switch(command->address.size) { + switch (command->address.size) { case QSPI_CFG_ADDR_SIZE_8: st_command->AddressSize = HAL_OSPI_ADDRESS_8_BITS; break; @@ -143,7 +143,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm error("Command param error: invalid alt bytes mode\n"); return QSPI_STATUS_ERROR; } - + // Alt size must be a multiple of the number of bus lines used (i.e. a whole number of cycles) if (command->alt.size % alt_lines != 0) { error("Command param error: incompatible alt size and alt bus width\n"); @@ -157,14 +157,13 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm error("Command param error: alt size exceeds maximum of 32 bits\n"); return QSPI_STATUS_ERROR; } - + // Unused bits in most significant byte of alt uint8_t leftover_bits = (rounded_size << 3) - command->alt.size; if (leftover_bits != 0) { // Account for dummy cycles that will be spent in the alt portion of the command uint8_t integrated_dummy_cycles = leftover_bits / alt_lines; - if (st_command->DummyCycles < integrated_dummy_cycles) - { + if (st_command->DummyCycles < integrated_dummy_cycles) { // Not enough dummy cycles to account for a short alt error("Command param error: not enough dummy cycles to make up for given alt size\n"); return QSPI_STATUS_ERROR; @@ -176,7 +175,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm } else { st_command->AlternateBytes = command->alt.value; } - + /* command->AlternateBytesSize needs to be shifted by OCTOSPI_CCR_ABSIZE_Pos */ // 0b00 = 1 byte, 0b01 = 2 bytes, 0b10 = 3 bytes, 0b11 = 4 bytes st_command->AlternateBytesSize = ((rounded_size - 1) << OCTOSPI_CCR_ABSIZE_Pos) & OCTOSPI_CCR_ABSIZE_Msk; @@ -198,7 +197,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm } debug_if(qspi_api_c_debug, "qspi_prepare_command Out: InstructionMode %x Instruction %x AddressMode %x AddressSize %x Address %x DataMode %x\n", - st_command->InstructionMode, st_command->Instruction, st_command->AddressMode, st_command->AddressSize, st_command->Address, st_command->DataMode); + st_command->InstructionMode, st_command->Instruction, st_command->AddressMode, st_command->AddressSize, st_command->Address, st_command->DataMode); return QSPI_STATUS_OK; } @@ -206,7 +205,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st_command) { debug_if(qspi_api_c_debug, "qspi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n", - command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); + command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); // TODO: shift these around to get more dynamic mapping switch (command->instruction.bus_width) { @@ -289,14 +288,13 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTy if (rounded_size > 4) { return QSPI_STATUS_ERROR; } - + // Unused bits in most significant byte of alt uint8_t leftover_bits = (rounded_size << 3) - command->alt.size; if (leftover_bits != 0) { // Account for dummy cycles that will be spent in the alt portion of the command uint8_t integrated_dummy_cycles = leftover_bits / alt_lines; - if (st_command->DummyCycles < integrated_dummy_cycles) - { + if (st_command->DummyCycles < integrated_dummy_cycles) { // Not enough dummy cycles to account for a short alt return QSPI_STATUS_ERROR; } @@ -307,7 +305,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTy } else { st_command->AlternateBytes = command->alt.value; } - + /* command->AlternateBytesSize needs to be shifted by QUADSPI_CCR_ABSIZE_Pos */ // 0b00 = 1 byte, 0b01 = 2 bytes, 0b10 = 3 bytes, 0b11 = 4 bytes st_command->AlternateBytesSize = ((rounded_size - 1) << QUADSPI_CCR_ABSIZE_Pos) & QUADSPI_CCR_ABSIZE_Msk; @@ -331,7 +329,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTy st_command->NbData = 0; debug_if(qspi_api_c_debug, "qspi_prepare_command Out: InstructionMode %x Instruction %x AddressMode %x AddressSize %x Address %x DataMode %x\n", - st_command->InstructionMode, st_command->Instruction, st_command->AddressMode, st_command->AddressSize, st_command->Address, st_command->DataMode); + st_command->InstructionMode, st_command->Instruction, st_command->AddressMode, st_command->AddressSize, st_command->Address, st_command->DataMode); return QSPI_STATUS_OK; } @@ -382,18 +380,18 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN obj->qspi = qspi_data_third; #if defined(OCTOSPI1) - if(obj->qspi == QSPI_1) { + if (obj->qspi == QSPI_1) { obj->handle.Instance = OCTOSPI1; } #endif #if defined(OCTOSPI2) - if(obj->qspi == QSPI_2) { + if (obj->qspi == QSPI_2) { obj->handle.Instance = OCTOSPI2; } #endif #if defined(OCTOSPI1) - if(obj->qspi == QSPI_1) { + if (obj->qspi == QSPI_1) { __HAL_RCC_OSPI1_CLK_ENABLE(); __HAL_RCC_OSPIM_CLK_ENABLE(); __HAL_RCC_OSPI1_FORCE_RESET(); @@ -401,7 +399,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN } #endif #if defined(OCTOSPI2) - if(obj->qspi == QSPI_2) { + if (obj->qspi == QSPI_2) { __HAL_RCC_OSPI2_CLK_ENABLE(); __HAL_RCC_OSPIM_CLK_ENABLE(); __HAL_RCC_OSPI2_FORCE_RESET(); @@ -427,7 +425,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN /* The OctoSPI IO Manager OCTOSPIM configuration is supported in a simplified mode in mbed-os * QSPI1 signals are mapped to port 1 and QSPI2 signals are mapped to port 2. * This is coded in this way in PeripheralPins.c */ - if(obj->qspi == QSPI_1) { + if (obj->qspi == QSPI_1) { OSPIM_Cfg_Struct.ClkPort = 1; OSPIM_Cfg_Struct.DQSPort = 1; OSPIM_Cfg_Struct.NCSPort = 1; @@ -441,8 +439,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN OSPIM_Cfg_Struct.IOHighPort = HAL_OSPIM_IOPORT_2_HIGH; } - if (HAL_OSPIM_Config(&obj->handle, &OSPIM_Cfg_Struct, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { + if (HAL_OSPIM_Config(&obj->handle, &OSPIM_Cfg_Struct, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { debug_if(qspi_api_c_debug, "HAL_OSPIM_Config error\n"); return QSPI_STATUS_ERROR; } @@ -457,8 +454,16 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN __HAL_RCC_QSPI_CLK_ENABLE(); // Reset QSPI +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ __HAL_RCC_QSPI_FORCE_RESET(); __HAL_RCC_QSPI_RELEASE_RESET(); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Reset handle internal state obj->handle.State = HAL_QSPI_STATE_RESET; @@ -526,13 +531,13 @@ qspi_status_t qspi_free(qspi_t *obj) } #if defined(OCTOSPI1) - if(obj->qspi == QSPI_1) { + if (obj->qspi == QSPI_1) { __HAL_RCC_OSPI1_FORCE_RESET(); __HAL_RCC_OSPI1_CLK_DISABLE(); } #endif #if defined(OCTOSPI2) - if(obj->qspi == QSPI_2) { + if (obj->qspi == QSPI_2) { __HAL_RCC_OSPI2_FORCE_RESET(); __HAL_RCC_OSPI2_CLK_DISABLE(); } @@ -557,8 +562,16 @@ qspi_status_t qspi_free(qspi_t *obj) } // Reset QSPI +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ __HAL_RCC_QSPI_FORCE_RESET(); __HAL_RCC_QSPI_RELEASE_RESET(); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Disable interface clock for QSPI __HAL_RCC_QSPI_CLK_DISABLE(); @@ -725,7 +738,7 @@ qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, if (status != QSPI_STATUS_OK) { return status; } - + st_command.NbData = *length; if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index e100520671..a9728b68f4 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -58,10 +58,16 @@ void rtc_init(void) __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWR_EnableBkUpAccess(); +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ #if MBED_CONF_TARGET_LSE_AVAILABLE RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { error("Cannot initialize RTC with LSE\n"); } @@ -93,6 +99,9 @@ void rtc_init(void) error("PeriphClkInitStruct RTC failed with LSI\n"); } #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Enable RTC __HAL_RCC_RTC_ENABLE(); diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index a18b85ba41..fe33165d03 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -210,6 +210,11 @@ void serial_free(serial_t *obj) struct serial_s *obj_s = SERIAL_S(obj); // Reset UART and disable clock +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ #if defined(USART1_BASE) if (obj_s->uart == UART_1) { __HAL_RCC_USART1_FORCE_RESET(); @@ -329,6 +334,9 @@ void serial_free(serial_t *obj) __HAL_RCC_LPUART1_CLK_DISABLE(); } #endif +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Configure GPIOs pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -356,12 +364,28 @@ void serial_baud(serial_t *obj, int baudrate) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ HAL_RCC_OscConfig(&RCC_OscInitStruct); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } // Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) { +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ if (init_uart(obj) == HAL_OK) { return; } @@ -383,12 +407,28 @@ void serial_baud(serial_t *obj, int baudrate) RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ HAL_RCC_OscConfig(&RCC_OscInitStruct); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } // Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) { PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ if (init_uart(obj) == HAL_OK) { return; } @@ -396,7 +436,15 @@ void serial_baud(serial_t *obj, int baudrate) #endif // Last chance using SYSCLK PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } #endif /* LPUART1_BASE */ diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index 4aa611debb..d1ba586451 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -57,6 +57,11 @@ static void ForcePeriphOutofDeepSleep(void) uint32_t pFLatency = 0; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ /* Get the Clocks configuration according to the internal RCC registers */ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency); @@ -81,6 +86,9 @@ static void ForcePeriphOutofDeepSleep(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) { error("ForcePeriphOutofDeepSleep clock issue\r\n"); } +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } @@ -91,6 +99,11 @@ static void ForceOscOutofDeepSleep(void) /* Enable Power Control clock */ __HAL_RCC_PWR_CLK_ENABLE(); +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ /* Get the Oscillators configuration according to the internal RCC registers */ HAL_RCC_GetOscConfig(&RCC_OscInitStruct); @@ -110,6 +123,9 @@ static void ForceOscOutofDeepSleep(void) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { error("ForceOscOutofDeepSleep clock issue\r\n"); } +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ } diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index 525f731c89..0721154529 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -220,7 +220,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel * According the STM32 Datasheet for SPI peripheral we need to PULLDOWN * or PULLUP the SCK pin according the polarity used. */ - pin_mode(spiobj->pin_sclk, (handle->Init.CLKPolarity == SPI_POLARITY_LOW) ? PullDown: PullUp); + pin_mode(spiobj->pin_sclk, (handle->Init.CLKPolarity == SPI_POLARITY_LOW) ? PullDown : PullUp); init_spi(obj); } @@ -235,6 +235,11 @@ void spi_free(spi_t *obj) __HAL_SPI_DISABLE(handle); HAL_SPI_DeInit(handle); +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ #if defined SPI1_BASE // Reset SPI and disable clock if (spiobj->spi == SPI_1) { @@ -282,7 +287,9 @@ void spi_free(spi_t *obj) __HAL_RCC_SPI6_CLK_DISABLE(); } #endif - +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Configure GPIOs pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -342,7 +349,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) * According the STM32 Datasheet for SPI peripheral we need to PULLDOWN * or PULLUP the SCK pin according the polarity used. */ - pull = (handle->Init.CLKPolarity == SPI_POLARITY_LOW) ? PullDown: PullUp; + pull = (handle->Init.CLKPolarity == SPI_POLARITY_LOW) ? PullDown : PullUp; pin_mode(spiobj->pin_sclk, pull); init_spi(obj); diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c index c003b39d81..14e4807f8a 100644 --- a/targets/TARGET_STM/trng_api.c +++ b/targets/TARGET_STM/trng_api.c @@ -54,9 +54,17 @@ void trng_init(trng_t *obj) #else PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL; #endif +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { error("RNG clock configuration error\n"); } +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ #endif #endif //!defined(TARGET_STM32WB) diff --git a/targets/TARGET_STM/us_ticker.c b/targets/TARGET_STM/us_ticker.c index ddf2e62ad7..a731383ef5 100644 --- a/targets/TARGET_STM/us_ticker.c +++ b/targets/TARGET_STM/us_ticker.c @@ -75,8 +75,16 @@ void init_16bit_timer(void) TIM_MST_RCC; // Reset timer +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ TIM_MST_RESET_ON; TIM_MST_RESET_OFF; +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Update the SystemCoreClock variable SystemCoreClockUpdate(); @@ -161,8 +169,16 @@ void init_32bit_timer(void) TIM_MST_RCC; // Reset timer +#if defined(DUAL_CORE) + uint32_t timeout = HSEM_TIMEOUT; + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + } +#endif /* DUAL_CORE */ TIM_MST_RESET_ON; TIM_MST_RESET_OFF; +#if defined(DUAL_CORE) + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#endif /* DUAL_CORE */ // Configure time base TimMasterHandle.Instance = TIM_MST; diff --git a/targets/targets.json b/targets/targets.json index a2a9cdf5b8..77b81a3994 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3345,8 +3345,7 @@ "macros_add": [ "STM32H747xx", "CORE_CM7", - "EXTRA_IDLE_STACK_REQUIRED", - "MBED_TICKLESS" + "EXTRA_IDLE_STACK_REQUIRED" ], "overrides": { "lpticker_delay_ticks": 0 }, "supported_form_factors": ["ARDUINO"], @@ -3362,6 +3361,36 @@ "release_versions": ["2", "5"], "bootloader_supported": true }, + "DISCO_H747I_CM4": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": [ + "STM32H7", + "STM32H747xI", + "DISCO_H747I" + ], + "config": { + "lpticker_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", + "value": 1 + } + }, + "macros_add": [ + "STM32H747xx", + "CORE_CM4", + "EXTRA_IDLE_STACK_REQUIRED" + ], + "overrides": { "lpticker_delay_ticks": 0 }, + "supported_form_factors": ["ARDUINO"], + "device_has_add": [ + "ANALOGOUT", + "CAN", + "CRC", + "TRNG", + "FLASH", + "MPU" + ] + }, "DISCO_H747I_CM7": { "inherits": ["DISCO_H747I"] }, diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 753aca9dcb..04a241c190 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -371,6 +371,12 @@ "STM32H743ZI": { "OGChipSelectEditMenu": "STM32H743ZI\tST STM32H743ZI" }, + "DISCO_H747I": { + "OGChipSelectEditMenu": "STM32H747XI_CM7\tST STM32H747XI_CM7" + }, + "DISCO_H747I_CM4": { + "OGChipSelectEditMenu": "STM32H747XI_CM4\tST STM32H747XI_CM4" + }, "CC3220SF": { "OGChipSelectEditMenu": "CC3220SF\tTexasInstruments CC3220SF", "CoreVariant": 39,