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Merge pull request #14363 from harmut01/baremetal_si 

Add bare metal support to Silicon Labs targets
pull/14374/head
Martin Kojtal 2021-03-03 08:53:10 +00:00 committed by GitHub
parent 71de6e24af ee5946c990
commit 53f87aada1
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 97 additions and 319 deletions
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54
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/efm32gg.sct
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@ -1,54 +0,0 @@
#! armcc -E
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00100000
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00020000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
#define VECTOR_SIZE 0xE0
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE+VECTOR_SIZE)
#define MBED_RAM1_START (MBED_RAM_START+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 MBED_RAM1_START (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack
}
}

245
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/startup_efm32gg.S
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@ -1,245 +0,0 @@
;/**************************************************************************//**
; * @file startup_efm32gg.s
; * @brief CMSIS Core Device Startup File for
; * Silicon Labs EFM32GG Device Series
; * @version 4.2.1
; * @date 03. February 2012
; *
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY, ALIGN=8
EXPORT __Vectors
EXPORT __Vectors_End
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA_IRQHandler ; 0: DMA Interrupt
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
DCD USB_IRQHandler ; 5: USB Interrupt
DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt
DCD ADC0_IRQHandler ; 7: ADC0 Interrupt
DCD DAC0_IRQHandler ; 8: DAC0 Interrupt
DCD I2C0_IRQHandler ; 9: I2C0 Interrupt
DCD I2C1_IRQHandler ; 10: I2C1 Interrupt
DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt
DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt
DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt
DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt
DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt
DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt
DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt
DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt
DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt
DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt
DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt
DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt
DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt
DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt
DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt
DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt
DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt
DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt
DCD RTC_IRQHandler ; 30: RTC Interrupt
DCD BURTC_IRQHandler ; 31: BURTC Interrupt
DCD CMU_IRQHandler ; 32: CMU Interrupt
DCD VCMP_IRQHandler ; 33: VCMP Interrupt
DCD LCD_IRQHandler ; 34: LCD Interrupt
DCD MSC_IRQHandler ; 35: MSC Interrupt
DCD AES_IRQHandler ; 36: AES Interrupt
DCD EBI_IRQHandler ; 37: EBI Interrupt
DCD EMU_IRQHandler ; 38: EMU Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA_IRQHandler [WEAK]
EXPORT GPIO_EVEN_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT USART0_RX_IRQHandler [WEAK]
EXPORT USART0_TX_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT ACMP0_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT GPIO_ODD_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT USART1_RX_IRQHandler [WEAK]
EXPORT USART1_TX_IRQHandler [WEAK]
EXPORT LESENSE_IRQHandler [WEAK]
EXPORT USART2_RX_IRQHandler [WEAK]
EXPORT USART2_TX_IRQHandler [WEAK]
EXPORT UART0_RX_IRQHandler [WEAK]
EXPORT UART0_TX_IRQHandler [WEAK]
EXPORT UART1_RX_IRQHandler [WEAK]
EXPORT UART1_TX_IRQHandler [WEAK]
EXPORT LEUART0_IRQHandler [WEAK]
EXPORT LEUART1_IRQHandler [WEAK]
EXPORT LETIMER0_IRQHandler [WEAK]
EXPORT PCNT0_IRQHandler [WEAK]
EXPORT PCNT1_IRQHandler [WEAK]
EXPORT PCNT2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT BURTC_IRQHandler [WEAK]
EXPORT CMU_IRQHandler [WEAK]
EXPORT VCMP_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT MSC_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT EBI_IRQHandler [WEAK]
EXPORT EMU_IRQHandler [WEAK]
DMA_IRQHandler
GPIO_EVEN_IRQHandler
TIMER0_IRQHandler
USART0_RX_IRQHandler
USART0_TX_IRQHandler
USB_IRQHandler
ACMP0_IRQHandler
ADC0_IRQHandler
DAC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
GPIO_ODD_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
USART1_RX_IRQHandler
USART1_TX_IRQHandler
LESENSE_IRQHandler
USART2_RX_IRQHandler
USART2_TX_IRQHandler
UART0_RX_IRQHandler
UART0_TX_IRQHandler
UART1_RX_IRQHandler
UART1_TX_IRQHandler
LEUART0_IRQHandler
LEUART1_IRQHandler
LETIMER0_IRQHandler
PCNT0_IRQHandler
PCNT1_IRQHandler
PCNT2_IRQHandler
RTC_IRQHandler
BURTC_IRQHandler
CMU_IRQHandler
VCMP_IRQHandler
LCD_IRQHandler
MSC_IRQHandler
AES_IRQHandler
EBI_IRQHandler
EMU_IRQHandler
B .
ENDP
ALIGN
END

20
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_STD/efm32gg.sct
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@ -11,6 +11,14 @@
#define MBED_APP_SIZE 0x00100000
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x20000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
@ -19,19 +27,25 @@
# endif
#endif
#define Vector_Size 0xE0
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
#define MBED_IRAM1_SIZE (MBED_RAM_SIZE - Vector_Size - Stack_Size)
#define MBED_IRAM1_START (MBED_RAM_START + Vector_Size)
#define RAM_FIXED_SIZE (Vector_Size + Stack_Size)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x200000E0 0x0001FF20-Stack_Size { ; RW data
RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (0x200000E0+0x0001FF20) EMPTY -Stack_Size { ; stack
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - MBED_IRAM1_START)) { ; heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack
}
}

21
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/TOOLCHAIN_ARM_STD/efm32gg11.sct
View File

@ -11,6 +11,14 @@
#define MBED_APP_SIZE 0x00200000
#endif
#if !defined(MBED_RAM_)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_)
#define MBED_RAM_SIZE 0x80000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
@ -19,19 +27,26 @@
# endif
#endif
#define Vector_Size 0x158
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
#define MBED_IRAM1_START (MBED_RAM_START + Vector_Size)
#define MBED_IRAM1_SIZE (MBED_RAM_SIZE - Vector_Size - Stack_Size)
#define RAM_FIXED_SIZE (Vector_Size + Stack_Size)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000158 0x0007FEA8-Stack_Size { ; RW data
RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (0x20000158+0x0007FEA8) EMPTY -Stack_Size { ; stack
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - MBED_IRAM1_START)) { ; heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack
}
}

19
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct
View File

@ -11,6 +11,14 @@
#define MBED_APP_SIZE 0x00100000
#endif
#if !defined(MBED_RAM_)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_)
#define MBED_RAM_SIZE 0x40000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
@ -19,18 +27,25 @@
# endif
#endif
#define Vector_Size 0x110
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
#define MBED_IRAM1_START (MBED_RAM_START + Vector_Size)
#define MBED_IRAM1_SIZE (MBED_RAM_SIZE - Vector_Size - Stack_Size)
#define RAM_FIXED_SIZE (Vector_Size + Stack_Size)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000110 0x0003FEF0-Stack_Size { ; RW data
RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (0x20000110+0x0003FEF0) EMPTY -Stack_Size { ; stack
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - MBED_IRAM1_START)) { ; heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack
}
}

57
targets/targets.json
View File

@ -5358,16 +5358,27 @@
],
"supported_toolchains": [
"GCC_ARM",
"ARM",
"uARM",
"IAR"
"ARM"
],
"release_versions": [
"5"
],
"device_name": "EFM32GG990F1024",
"public": false,
"bootloader_supported": true
"bootloader_supported": true,
"supported_c_libs": {
"arm": [
"std",
"small"
],
"gcc_arm": [
"std",
"small"
]
},
"supported_application_profiles": [
"full", "bare-metal"
]
},
"EFM32GG_STK3700": {
"inherits": [
@ -5463,16 +5474,27 @@
],
"supported_toolchains": [
"GCC_ARM",
"ARM",
"uARM",
"IAR"
"ARM"
],
"release_versions": [
"5"
],
"device_name": "EFR32MG12P332F1024GL125",
"public": false,
"bootloader_supported": true
"bootloader_supported": true,
"supported_c_libs": {
"arm": [
"std",
"small"
],
"gcc_arm": [
"std",
"small"
]
},
"supported_application_profiles": [
"full", "bare-metal"
]
},
"TB_SENSE_12": {
"inherits": [
@ -5563,16 +5585,27 @@
],
"supported_toolchains": [
"GCC_ARM",
"ARM",
"uARM",
"IAR"
"ARM"
],
"release_versions": [
"5"
],
"device_name": "EFM32GG11B820F2048GL192",
"public": false,
"bootloader_supported": true
"bootloader_supported": true,
"supported_c_libs": {
"arm": [
"std",
"small"
],
"gcc_arm": [
"std",
"small"
]
},
"supported_application_profiles": [
"full", "bare-metal"
]
},
"EFM32GG11_STK3701": {
"inherits": [