mirror of https://github.com/ARMmbed/mbed-os.git
Added IAR export for LPC11U68.
GustavWi
parent
02497b1f62
commit
5311efaae6
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@ -0,0 +1,44 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x00000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define symbol __ICFEDIT_size_heap__ = 0x800;
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/**** End of ICF editor section. ###ICF###*/
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define symbol __CRP_start__ = 0x000002FC;
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define symbol __CRP_end__ = 0x000002FF;
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define symbol __RAM1_start__ = 0x20000000;
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define symbol __RAM1_end__ = 0x200007FF;
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define symbol __RAM_USB_start__= 0x20004000;
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define symbol __RAM_USB_end__ = 0x200047FF;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
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define region RAM_USB_region = mem:[from __RAM_USB_start__ to __RAM_USB_end__];
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define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };
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place in CRP_region { section .crp };
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place in RAM1_region { section .sram1 };
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place in RAM_USB_region { section .sram_usb };
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@ -0,0 +1,251 @@
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;/*****************************************************************************
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; * @file: startup_LPC11u6x.s
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; * @purpose: CMSIS Cortex-M0PLUS Core Device Startup File
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; * for the NXP LPC11u6x Device Series (manually edited)
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; * @version: V1.00
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; * @date: 19. October 2009
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; *----------------------------------------------------------------------------
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; *
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; * Copyright (C) 2009 ARM Limited. All rights reserved.
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; *
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; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD 0
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DCD 0
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DCD 0
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler
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DCD 0
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DCD 0
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DCD PendSV_Handler
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DCD SysTick_Handler
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DCD PIN_INT0_IRQHandler ; Pin interrupt 0
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DCD PIN_INT1_IRQHandler ; Pin interrupt 1
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DCD PIN_INT2_IRQHandler ; Pin interrupt 2
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DCD PIN_INT3_IRQHandler ; Pin interrupt 3
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DCD PIN_INT4_IRQHandler ; Pin interrupt 4
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DCD PIN_INT5_IRQHandler ; Pin interrupt 5
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DCD PIN_INT6_IRQHandler ; Pin interrupt 6
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DCD PIN_INT7_IRQHandler ; Pin interrupt 7
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DCD GINT0_IRQHandler ; Port interrupt group 0
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DCD GINT1_IRQHandler ; Port interrupt group 1
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DCD I2C1_IRQHandler ; I2C1 interrupt
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DCD USART1_4_IRQHandler ; USARTS 1 and 4 shared interrupt
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DCD USART2_3_IRQHandler ; USARTS 2 and 3 shared interrupt
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DCD SCT0_1_IRQHandler ; SCT 0 and 1 shared interrupt
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DCD SSP1_IRQHandler ; SSP1 interrupt
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD CT16B0_IRQHandler ; CT16B0 (16-bit Timer 0)
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DCD CT16B1_IRQHandler ; CT16B1 (16-bit Timer 1)
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DCD CT32B0_IRQHandler ; CT32B0 (32-bit Timer 0)
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DCD CT32B1_IRQHandler ; CT32B0 (32-bit Timer 1)
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DCD SSP0_IRQHandler ; SSP0 interrupt interrupt
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DCD USART0_IRQHandler ; USART 0 interrupt interrupt
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DCD USB_IRQHandler ; USB IRQ interrupt
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DCD USB_FIQ_IRQHandler ; USB FIQ interrupt
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DCD ADC_A_IRQHandler ; ADC A sequence (A/D Converter) interrupt
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DCD RTC_IRQHandler ; RTC interrupt
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DCD BOD_WDT_IRQHandler ; Shared BOD (Brownout Detect) and WDT interrupts
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DCD FLASH_IRQHandler ; Flash Memory Controller interrupt
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DCD DMA_IRQHandler ; DMA Controller interrupt
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DCD ADC_B_IRQHandler ; ADC B sequence interrupt
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DCD USBWakeup_IRQHandler ; USB wake-up interrupt
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DCD Reserved_IRQHandler
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:NOROOT:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B .
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B .
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B .
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B .
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B .
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PUBWEAK Reserved_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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Reserved_IRQHandler
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B .
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PUBWEAK PIN_INT0_IRQHandler
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PUBWEAK PIN_INT1_IRQHandler
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PUBWEAK PIN_INT2_IRQHandler
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PUBWEAK PIN_INT3_IRQHandler
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PUBWEAK PIN_INT4_IRQHandler
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PUBWEAK PIN_INT5_IRQHandler
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PUBWEAK PIN_INT6_IRQHandler
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PUBWEAK PIN_INT7_IRQHandler
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PUBWEAK GINT0_IRQHandler
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PUBWEAK GINT1_IRQHandler
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PUBWEAK I2C1_IRQHandler
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PUBWEAK USART1_4_IRQHandler
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PUBWEAK USART2_3_IRQHandler
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PUBWEAK SCT0_1_IRQHandler
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PUBWEAK SSP1_IRQHandler
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PUBWEAK I2C0_IRQHandler
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PUBWEAK CT16B0_IRQHandler
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PUBWEAK CT16B1_IRQHandler
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PUBWEAK CT32B0_IRQHandler
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PUBWEAK CT32B1_IRQHandler
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PUBWEAK SSP0_IRQHandler
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PUBWEAK USART0_IRQHandler
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PUBWEAK USB_IRQHandler
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PUBWEAK USB_FIQ_IRQHandler
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PUBWEAK ADC_A_IRQHandler
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PUBWEAK RTC_IRQHandler
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PUBWEAK BOD_WDT_IRQHandler
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PUBWEAK FLASH_IRQHandler
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PUBWEAK DMA_IRQHandler
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PUBWEAK ADC_B_IRQHandler
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PUBWEAK USBWakeup_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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THUMB
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PIN_INT0_IRQHandler
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PIN_INT1_IRQHandler
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PIN_INT2_IRQHandler
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PIN_INT3_IRQHandler
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PIN_INT4_IRQHandler
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PIN_INT5_IRQHandler
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PIN_INT6_IRQHandler
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PIN_INT7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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I2C1_IRQHandler
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USART1_4_IRQHandler
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USART2_3_IRQHandler
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SCT0_1_IRQHandler
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SSP1_IRQHandler
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I2C0_IRQHandler
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CT16B0_IRQHandler
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CT16B1_IRQHandler
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CT32B0_IRQHandler
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CT32B1_IRQHandler
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SSP0_IRQHandler
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USART0_IRQHandler
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USB_IRQHandler
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USB_FIQ_IRQHandler
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ADC_A_IRQHandler
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RTC_IRQHandler
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BOD_WDT_IRQHandler
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FLASH_IRQHandler
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DMA_IRQHandler
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ADC_B_IRQHandler
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USBWakeup_IRQHandler
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Default_Handler
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B Default_Handler
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SECTION .crp:CODE:ROOT(2)
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DATA
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/* Code Read Protection
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NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
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CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
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- Copy RAM to flash command can not write to Sector 0.
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- Erase command can erase Sector 0 only when all sectors
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are selected for erase.
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- Compare command is disabled.
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- Read Memory command is disabled.
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CRP2 0x87654321 - Read Memory is disabled.
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- Write to RAM is disabled.
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- "Go" command is disabled.
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- Copy RAM to flash is disabled.
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- Compare is disabled.
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CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
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by pulling PIO0_1 LOW is disabled if a valid user code is
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present in flash sector 0.
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Caution: If CRP3 is selected, no future factory testing can be
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performed on the device.
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*/
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DCD 0xFFFFFFFF
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END
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@ -76,7 +76,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
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('RBLAB_BLENANO', ('ARM', 'GCC_ARM')),
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('RBLAB_BLENANO', ('ARM', 'GCC_ARM')),
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('WALLBOT_BLE', ('ARM', 'GCC_ARM')),
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('WALLBOT_BLE', ('ARM', 'GCC_ARM')),
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('LPC11U68', ('uARM','GCC_ARM','GCC_CR')),
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('LPC11U68', ('uARM','GCC_ARM','GCC_CR', 'IAR')),
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('OC_MBUINO', ('ARM', 'uARM', 'GCC_ARM')),
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('OC_MBUINO', ('ARM', 'uARM', 'GCC_ARM')),
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# ('RZ_A1H' , ('ARM',)),
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# ('RZ_A1H' , ('ARM',)),
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@ -161,7 +161,7 @@ class LPC11U68(LPCTarget):
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LPCTarget.__init__(self)
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LPCTarget.__init__(self)
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self.core = "Cortex-M0+"
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self.core = "Cortex-M0+"
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self.extra_labels = ['NXP', 'LPC11U6X']
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self.extra_labels = ['NXP', 'LPC11U6X']
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self.supported_toolchains = ["uARM", "GCC_CR", "GCC_ARM"]
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self.supported_toolchains = ["uARM", "GCC_CR", "GCC_ARM", "IAR"]
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self.default_toolchain = "uARM"
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self.default_toolchain = "uARM"
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self.supported_form_factors = ["ARDUINO"]
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self.supported_form_factors = ["ARDUINO"]
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self.detect_code = "1168"
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self.detect_code = "1168"
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