From e7e5931fe9477de329a0f765cff4064b1b79a851 Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Tue, 29 Jan 2019 12:45:48 +0200 Subject: [PATCH 001/109] Mutex-protect mbedtls_hardware_poll Like all HAL APIs, the calls in trng_api.h are not expected to be thread-safe. All current accesses to the TRNG HAL are currently via `mbedtls_hardware_poll`. Mbed TLS does not currently serialise these calls itself, as `MBEDTLS_THREADING_C` is not enabled. But even if Mbed TLS's own accesses were serialised, there are other direct users of `mbedtls_hardware_poll` such as randLIB, that need to use direct calls due to lack of API to extract entropy from Mbed TLS. As such it makes sense to treat `mbedtls_hardware_poll` as a de facto public Mbed OS API, akin to the C++ veneers on top of the HAL, and add a PlatformMutex there so that it is safe for multithreaded use. --- features/mbedtls/platform/src/{mbed_trng.c => mbed_trng.cpp} | 5 +++++ 1 file changed, 5 insertions(+) rename features/mbedtls/platform/src/{mbed_trng.c => mbed_trng.cpp} (87%) diff --git a/features/mbedtls/platform/src/mbed_trng.c b/features/mbedtls/platform/src/mbed_trng.cpp similarity index 87% rename from features/mbedtls/platform/src/mbed_trng.c rename to features/mbedtls/platform/src/mbed_trng.cpp index d4dd771c01..53c1c21097 100644 --- a/features/mbedtls/platform/src/mbed_trng.c +++ b/features/mbedtls/platform/src/mbed_trng.cpp @@ -17,12 +17,17 @@ #if DEVICE_TRNG #include "hal/trng_api.h" +#include "platform/PlatformMutex.h" +extern "C" int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen ) { + static PlatformMutex trng_mutex; trng_t trng_obj; + trng_mutex.lock(); trng_init(&trng_obj); int ret = trng_get_bytes(&trng_obj, output, len, olen); trng_free(&trng_obj); + trng_mutex.unlock(); return ret; } From d7b58e99fa4ee9473cc39acda224b2825c983eba Mon Sep 17 00:00:00 2001 From: Alexander Zilberkant Date: Sun, 10 Feb 2019 11:06:34 +0200 Subject: [PATCH 002/109] FUTURE_SEQUANA_M0_PSA - fix CM4 starting address Use PSA_NON_SECURE_ROM_START configuration value instead of hardcoded CY_CORTEX_M4_APPL_ADDR. --- .../TARGET_FUTURE_SEQUANA_M0_PSA/spm_hal_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA_M0_PSA/spm_hal_api.c b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA_M0_PSA/spm_hal_api.c index 4d0352cc98..a6f6fff74e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA_M0_PSA/spm_hal_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA_M0_PSA/spm_hal_api.c @@ -32,7 +32,7 @@ void spm_hal_start_nspe(void) { - Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR); + Cy_SysEnableCM4(PSA_NON_SECURE_ROM_START); } void spm_hal_memory_protection_init(void) From 275572c9669c8a5e66e676dc564035caaf365579 Mon Sep 17 00:00:00 2001 From: Veijo Pesonen Date: Thu, 7 Feb 2019 12:01:09 +0200 Subject: [PATCH 003/109] tests-netsocket-tls: TLSSOCKET_ECHOTEST deletes socket on failure case --- TESTS/netsocket/tls/tlssocket_echotest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/netsocket/tls/tlssocket_echotest.cpp b/TESTS/netsocket/tls/tlssocket_echotest.cpp index b7b91b1ef4..56f8fa7fbd 100644 --- a/TESTS/netsocket/tls/tlssocket_echotest.cpp +++ b/TESTS/netsocket/tls/tlssocket_echotest.cpp @@ -63,8 +63,8 @@ void TLSSOCKET_ECHOTEST() if (tlssocket_connect_to_echo_srv(*sock) != NSAPI_ERROR_OK) { printf("Error from tlssocket_connect_to_echo_srv\n"); TEST_FAIL(); - return; delete sock; + return; } int recvd; From 70d8214d3095b20eba44793aeaec6aad9c0c162a Mon Sep 17 00:00:00 2001 From: Veijo Pesonen Date: Thu, 7 Feb 2019 12:04:09 +0200 Subject: [PATCH 004/109] tests-network-interface: drops unreferenced variable --- TESTS/network/interface/networkinterface_status.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/TESTS/network/interface/networkinterface_status.cpp b/TESTS/network/interface/networkinterface_status.cpp index 32d1a2bd8e..f19a31fa9b 100644 --- a/TESTS/network/interface/networkinterface_status.cpp +++ b/TESTS/network/interface/networkinterface_status.cpp @@ -137,8 +137,6 @@ void NETWORKINTERFACE_STATUS_NONBLOCK() void NETWORKINTERFACE_STATUS_GET() { - nsapi_connection_status_t status; - net = NetworkInterface::get_default_instance(); net->set_blocking(true); From f886fc67c8d0c1167dd05b332d09e2e4df20159d Mon Sep 17 00:00:00 2001 From: Veijo Pesonen Date: Thu, 7 Feb 2019 12:17:08 +0200 Subject: [PATCH 005/109] platform: includes string.h needed by memcpy and strlen --- platform/mbed_board.c | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/mbed_board.c b/platform/mbed_board.c index 4b3844e2a4..9982182940 100644 --- a/platform/mbed_board.c +++ b/platform/mbed_board.c @@ -15,6 +15,7 @@ * limitations under the License. */ #include +#include #include "hal/gpio_api.h" #include "platform/mbed_wait_api.h" #include "platform/mbed_toolchain.h" From fe9020b11a1fd9a20a7447af2d6fa3470abebc0e Mon Sep 17 00:00:00 2001 From: Leszek Rusinowicz Date: Fri, 8 Feb 2019 16:51:01 +0100 Subject: [PATCH 006/109] FUTURE_SEQUANA: SPI HAL fixes 1. Removed random i/o glitches occurring during device reconfiguration 2. Fixed hazardous reads occurring at the end of transfer resulting in incorrect values being received 3. Added spi_free() function 4. Replaced default M0 image with a one ignoring i/o reservation. This is a workaround for missing proper destructors in Mbed drivers and BlockDevice tests failing on repeated initialization Fixes issue #9620. --- .../hex/psoc63_m0_ble_controller_1.01.hex | 1655 ----------------- .../hex/psoc63_m0_default_1.02.hex | 146 -- .../hex/psoc63_m0_default_1.03.hex | 146 ++ .../TARGET_PSOC6_FUTURE/objects.h | 9 +- .../TARGET_PSOC6_FUTURE/pinmap.c | 7 +- .../TARGET_PSOC6_FUTURE/spi_api.c | 152 +- targets/targets.json | 2 +- 7 files changed, 274 insertions(+), 1843 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_default_1.02.hex create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_default_1.03.hex diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex deleted file mode 100644 index 3942055ebc..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex +++ /dev/null @@ -1,1655 +0,0 @@ -:020000041000EA -:4000000000000108310100100D00000095010010000000000000000000000000000000000000000000000000000000009101001000000000000000009101001091010010DC -:400040009101001061080010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001089 -:400080009101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001020 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+:40230000844601BC604700BFA110001001B40248844601BC604700BF6317001001B40248844601BC604700BFE503001001B40248844601BC604700BFC50C001001B40248C9 +:40234000844601BC604700BF5B17001001B40248844601BC604700BFBD0D001001B40248844601BC604700BFA50B001000000000000000000000000000000000000000007C +:40238000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001D +:4023C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000DD +:00000001FF \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/objects.h b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/objects.h index 0ba07af1f7..d7d88e26f8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/objects.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/objects.h @@ -53,16 +53,8 @@ struct port_s { uint32_t mask; PinDirection direction; PinMode mode; -// __IO uint32_t *reg_in; -// __IO uint32_t *reg_out; }; -// struct analogin_s { -// ADCName adc; -// PinName pin; -// uint32_t channel; -// }; - #if DEVICE_SERIAL #include "cy_scb_uart.h" @@ -107,6 +99,7 @@ struct spi_s { uint32_t div_num; cy_en_divider_types_t div_type; uint32_t clk_frequency; + uint32_t clk_delay; cy_en_scb_spi_mode_t ms_mode; cy_en_scb_spi_sclk_mode_t clk_mode; uint8_t data_bits; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/pinmap.c b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/pinmap.c index 23fe537aa7..8f637b70cf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/pinmap.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/pinmap.c @@ -26,20 +26,21 @@ void pin_function(PinName pin, int function) if (pin != NC) { GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CY_PORT(pin)); uint32_t mode = gpio_get_cy_drive_mode(CY_PIN_DIRECTION(function), CY_PIN_MODE(function)); + uint32_t state = Cy_GPIO_ReadOut(port, CY_PIN(pin)); - Cy_GPIO_Pin_FastInit(port, CY_PIN(pin), mode, 1, CY_PIN_HSIOM(function)); // Force output to enable pulls. switch (mode) { case CY_GPIO_DM_PULLUP: - Cy_GPIO_Write(port, CY_PIN(pin), 1); + state = 1; break; case CY_GPIO_DM_PULLDOWN: - Cy_GPIO_Write(port, CY_PIN(pin), 0); + state = 0; break; default: /* do nothing */ break; } + Cy_GPIO_Pin_FastInit(port, CY_PIN(pin), mode, state, CY_PIN_HSIOM(function)); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/spi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/spi_api.c index 45f71cc148..9ae3e9ac1f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/spi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/spi_api.c @@ -87,10 +87,10 @@ static IRQn_Type spi_irq_allocate_channel(spi_obj_t *obj) #endif // M0 } -static void spi_irq_release_channel(IRQn_Type channel, uint32_t spi_id) +static void spi_irq_release_channel(spi_obj_t *obj) { #if defined (TARGET_MCU_PSOC6_M0) - cy_m0_nvic_release_channel(channel, CY_SERIAL_IRQN_ID + spi_id); + cy_m0_nvic_release_channel(obj->irqn, CY_SERIAL_IRQN_ID + obj->spi_id); #endif //M0 } @@ -130,6 +130,14 @@ static int allocate_divider(spi_obj_t *obj) return (obj->div_num == CY_INVALID_DIVIDER)? -1 : 0; } +static void free_divider(spi_obj_t *obj) +{ + if (obj->div_num != CY_INVALID_DIVIDER) { + cy_clk_free_divider(obj->div_type, obj->div_num); + obj->div_num = CY_INVALID_DIVIDER; + } +} + /* * Initializes spi clock for the required speed @@ -149,6 +157,8 @@ static cy_en_sysclk_status_t spi_init_clock(spi_obj_t *obj, uint32_t frequency) // Set up proper frequency; round up the divider so the frequency is not higher than specified. div_value = (CY_CLK_PERICLK_FREQ_HZ + frequency *(SPI_OVERSAMPLE - 1)) / frequency / SPI_OVERSAMPLE; obj->clk_frequency = CY_CLK_PERICLK_FREQ_HZ / div_value / SPI_OVERSAMPLE; + // Delay (in us) required for serialized read operation == 1.5 clocks, min 1us. + obj->clk_delay = (1500000UL - 1 + obj->clk_frequency) / obj->clk_frequency; Cy_SysClk_PeriphDisableDivider(obj->div_type, obj->div_num); if (Cy_SysClk_PeriphSetDivider(obj->div_type, obj->div_num, div_value) != CY_SYSCLK_SUCCESS) { obj->div_num = CY_INVALID_DIVIDER; @@ -166,40 +176,20 @@ static cy_en_sysclk_status_t spi_init_clock(spi_obj_t *obj, uint32_t frequency) } /* - * Initializes i/o pins for spi. + * Sets up i/o connections for spi. */ -static void spi_init_pins(spi_obj_t *obj) +static void spi_set_pins(spi_obj_t *obj) { - bool conflict = false; - conflict = cy_reserve_io_pin(obj->pin_sclk); - if (!conflict) { - pin_function(obj->pin_sclk, pinmap_function(obj->pin_sclk, PinMap_SPI_SCLK)); - } if (obj->pin_mosi != NC) { - if (!cy_reserve_io_pin(obj->pin_mosi)) { - pin_function(obj->pin_mosi, pinmap_function(obj->pin_mosi, PinMap_SPI_MOSI)); - } else { - conflict = true; - } + pin_function(obj->pin_mosi, pinmap_function(obj->pin_mosi, PinMap_SPI_MOSI)); } if (obj->pin_miso != NC) { - if (!cy_reserve_io_pin(obj->pin_miso)) { - pin_function(obj->pin_miso, pinmap_function(obj->pin_miso, PinMap_SPI_MISO)); - } else { - conflict = true; - } + pin_function(obj->pin_miso, pinmap_function(obj->pin_miso, PinMap_SPI_MISO)); } if (obj->pin_ssel != NC) { - if (!cy_reserve_io_pin(obj->pin_ssel)) { - pin_function(obj->pin_ssel, pinmap_function(obj->pin_ssel, PinMap_SPI_SSEL)); - } else { - conflict = true; - } + pin_function(obj->pin_ssel, pinmap_function(obj->pin_ssel, PinMap_SPI_SSEL)); } - if (conflict) { - error("SPI pin reservation conflict."); - } - + pin_function(obj->pin_sclk, pinmap_function(obj->pin_sclk, PinMap_SPI_SCLK)); // Pin configuration in PinMap defaults to Master mode; revert for Slave. if (obj->ms_mode == CY_SCB_SPI_SLAVE) { pin_mode(obj->pin_sclk, PullNone); @@ -209,6 +199,55 @@ static void spi_init_pins(spi_obj_t *obj) } } +/* + * Sets i/o output pins into safe mode while re-configuring peripheral. + */ +static void spi_default_pins(spi_obj_t *obj) +{ + + if (obj->ms_mode == CY_SCB_SPI_MASTER) { + pin_function(obj->pin_sclk, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullDown, PIN_OUTPUT)); + if (obj->pin_mosi != NC) { + pin_function(obj->pin_mosi, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullUp, PIN_OUTPUT)); + } + if (obj->pin_ssel != NC) { + pin_function(obj->pin_ssel, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullUp, PIN_OUTPUT)); + } + } else { + if (obj->pin_miso != NC) { + pin_function(obj->pin_miso, CY_PIN_FUNCTION(HSIOM_SEL_GPIO, 0, PullUp, PIN_OUTPUT)); + } + } +} + +/* + * Initializes i/o pins for spi. + */ +static void spi_init_pins(spi_obj_t *obj) +{ + bool conflict = false; + conflict = cy_reserve_io_pin(obj->pin_sclk); + if (obj->pin_mosi != NC) { + if (cy_reserve_io_pin(obj->pin_mosi)) { + conflict = true; + } + } + if (obj->pin_miso != NC) { + if (cy_reserve_io_pin(obj->pin_miso)) { + conflict = true; + } + } + if (obj->pin_ssel != NC) { + if (cy_reserve_io_pin(obj->pin_ssel)) { + conflict = true; + } + } + if (conflict) { + error("SPI pin reservation conflict."); + } + spi_set_pins(obj); +} + /* * Initializes and enables SPI/SCB. */ @@ -282,8 +321,8 @@ void spi_init(spi_t *obj_in, PinName mosi, PinName miso, PinName sclk, PinName s obj->rx_buffer_size = 0; #endif // DEVICE_SPI_ASYNCH spi_init_clock(obj, SPI_DEFAULT_SPEED); - spi_init_pins(obj); spi_init_peripheral(obj); + spi_init_pins(obj); #if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER obj->pm_callback_handler.callback = spi_pm_callback; obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP; @@ -300,27 +339,73 @@ void spi_init(spi_t *obj_in, PinName mosi, PinName miso, PinName sclk, PinName s } } + +void spi_free(spi_t *obj_in) +{ + spi_obj_t *obj = OBJ_P(obj_in); + + spi_default_pins(obj); + Cy_SCB_SPI_Disable(obj->base, &obj->context); + Cy_SCB_SPI_DeInit (obj->base); + +#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER + Cy_SysPm_UnregisterCallback(&obj->pm_callback_handler); +#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER + +#if DEVICE_SPI_ASYNCH + if (obj->irqn != unconnected_IRQn) { + NVIC_DisableIRQ(obj->irqn); + spi_irq_release_channel(obj); + + obj->irqn = unconnected_IRQn; + } +#endif // DEVICE_SPI_ASYNCH + + if (obj->pin_sclk != NC) { + cy_free_io_pin(obj->pin_sclk); + obj->pin_sclk = NC; + } + if (obj->pin_mosi != NC) { + cy_free_io_pin(obj->pin_mosi); + obj->pin_mosi = NC; + } + if (obj->pin_miso != NC) { + cy_free_io_pin(obj->pin_miso); + obj->pin_miso = NC; + } + if (obj->pin_ssel != NC) { + cy_free_io_pin(obj->pin_ssel); + obj->pin_ssel = NC; + } + + free_divider(obj); +} + + void spi_format(spi_t *obj_in, int bits, int mode, int slave) { spi_obj_t *obj = OBJ_P(obj_in); cy_en_scb_spi_mode_t new_mode = slave? CY_SCB_SPI_SLAVE : CY_SCB_SPI_MASTER; if ((bits < 4) || (bits > 16)) return; + spi_default_pins(obj); Cy_SCB_SPI_Disable(obj->base, &obj->context); obj->data_bits = bits; obj->clk_mode = (cy_en_scb_spi_sclk_mode_t)(mode & 0x3); if (obj->ms_mode != new_mode) { obj->ms_mode = new_mode; - spi_init_pins(obj); } spi_init_peripheral(obj); + spi_set_pins(obj); } void spi_frequency(spi_t *obj_in, int hz) { spi_obj_t *obj = OBJ_P(obj_in); + spi_default_pins(obj); Cy_SCB_SPI_Disable(obj->base, &obj->context); spi_init_clock(obj, hz); Cy_SCB_SPI_Enable(obj->base); + spi_set_pins(obj); } int spi_master_write(spi_t *obj_in, int value) @@ -335,6 +420,10 @@ int spi_master_write(spi_t *obj_in, int value) while (!Cy_SCB_SPI_IsTxComplete(obj->base)) { // wait for the transmission to complete } + // Wait until RX FIFO is filled from the serial register. + while (Cy_SCB_SPI_GetNumInRxFifo(obj->base) == 0) { + /* busy loop */ + } return Cy_SCB_SPI_Read(obj->base); } else { return (int)CY_SCB_SPI_RX_NO_DATA; @@ -387,6 +476,9 @@ int spi_master_block_write(spi_t *obj_in, const char *tx_buffer, int tx_length, ++rx_count; } } + // Delay at least 1.5 clock cycle, so that FIFO is filled with the last char + // and SCLK returns to idle state. + Cy_SysLib_DelayUs(obj->clk_delay); // Read any remaining bytes from the fifo. while (rx_count < rx_length) { *rx_buffer++ = (char)Cy_SCB_SPI_Read(obj->base); diff --git a/targets/targets.json b/targets/targets.json index 3ac3789b38..a64966fd42 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -7954,7 +7954,7 @@ "device_has_remove": ["TRNG", "CRC"], "macros_add": ["CY8C6347BZI_BLD53"], "detect_code": ["6000"], - "hex_filename": "psoc63_m0_default_1.02.hex", + "hex_filename": "psoc63_m0_default_1.03.hex", "post_binary_hook": { "function": "PSOC6Code.complete" }, From bd056c680a614203232a80c0cf6cb575ba4a944c Mon Sep 17 00:00:00 2001 From: Przemyslaw Stekiel Date: Tue, 5 Feb 2019 09:08:49 +0100 Subject: [PATCH 007/109] K64/ARM: Update to 2-region model for HEAP and Stack Memory --- .../TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct | 4 +- .../device/TOOLCHAIN_ARM_STD/sys.cpp | 86 +++++++++++++++++++ targets/TARGET_Freescale/mbed_rtx.h | 12 +++ 3 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct index 72a6efafe2..76653b8e6f 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct @@ -126,11 +126,13 @@ LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; lo RW_m_data m_data_start m_data_size { ; RW data .ANY (+RW +ZI) } - RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data + RW_m_data_2 m_data_2_start m_data_2_size { ; RW data .ANY (+RW +ZI) } RW_IRAM1 ImageLimit(RW_m_data_2) { ; Heap region growing up } + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_2_start + m_data_2_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) { + } ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down } } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..604ba18369 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,86 @@ + /* + * Copyright (c) 2019-2019 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include +#endif + +#include +#include + +extern char Image$$ARM_LIB_STACK$$ZI$$Limit[]; +extern char Image$$ARM_LIB_HEAP$$Base[]; +extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[]; +extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + + struct __initial_stackheap r; + r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base; + r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit; + return r; +} + +#if !defined(MBED_CONF_RTOS_PRESENT) || !MBED_CONF_RTOS_PRESENT + +/* The single region memory model would check stack collision at run time, verifying that + * the heap pointer is underneath the stack pointer. With two-region memory model/RTOS-less or + * multiple threads(stacks)/RTOS, the check gets meaningless and we must disable it. */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +__asm(".global __use_two_region_memory\n\t"); +__asm(".global __use_no_semihosting\n\t"); +#else +#pragma import(__use_two_region_memory) +#endif + +/* Fix __user_setup_stackheap and ARM_LIB_STACK/ARM_LIB_HEAP cannot co-exist in RTOS-less build + * + * According AN241 (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0241b/index.html), + * __rt_entry has the following call sequence: + * 1. _platform_pre_stackheap_init + * 2. __user_setup_stackheap or setup the Stack Pointer (SP) by another method + * 3. _platform_post_stackheap_init + * 4. __rt_lib_init + * 5. _platform_post_lib_init + * 6. main() + * 7. exit() + * + * Per our check, when __user_setup_stackheap and ARM_LIB_STACK/ARM_LIB_HEAP co-exist, neither + * does __user_setup_stackheap get called and nor is ARM_LIB_HEAP used to get heap base/limit, + * which are required to pass to __rt_lib_init later. To fix the issue, by subclass'ing + * __rt_lib_init, heap base/limit are replaced with Image$$ARM_LIB_HEAP$$ZI$$Base/Limit if + * ARM_LIB_HEAP region is defined in scatter file. + * + * The overriding __rt_lib_init is needed only for rtos-less code. For rtos code, __rt_entry is + * overridden and the overriding __rt_lib_init here gets meaningless. + */ +extern __value_in_regs struct __argc_argv $Super$$__rt_lib_init(unsigned heapbase, unsigned heaptop); + +__value_in_regs struct __argc_argv $Sub$$__rt_lib_init (unsigned heapbase, unsigned heaptop) +{ + return $Super$$__rt_lib_init((unsigned) Image$$ARM_LIB_HEAP$$Base, (unsigned) Image$$ARM_LIB_HEAP$$ZI$$Limit); +} + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Freescale/mbed_rtx.h b/targets/TARGET_Freescale/mbed_rtx.h index 507c042e2e..172dce07a6 100644 --- a/targets/TARGET_Freescale/mbed_rtx.h +++ b/targets/TARGET_Freescale/mbed_rtx.h @@ -17,6 +17,8 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H +#include + #if defined(TARGET_K20D50M) #ifndef INITIAL_SP @@ -87,6 +89,16 @@ #ifndef INITIAL_SP #define INITIAL_SP (0x20030000UL) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[]; +#define HEAP_START ((unsigned char*) Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_SIZE ((uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length) +#define ISR_STACK_START ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base) +#define ISR_STACK_SIZE ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length) +#endif #endif #elif defined(TARGET_SDT64B) From 8482fb7676ce362c336823c36c2cb7e928b39324 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Mon, 11 Feb 2019 09:36:18 +0000 Subject: [PATCH 008/109] Revert "MIMXRT1050_EVK: Add IAR support in the exporter" --- tools/export/iar/iar_definitions.json | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index f5e588be61..5ef5b21a90 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -96,9 +96,6 @@ "LPC54628J512ET180": { "OGChipSelectEditMenu": "LPC54618J512\tNXP LPC54618J512" }, - "MIMXRT1052": { - "OGChipSelectEditMenu": "MIMXRT1052xxx6B\tNXP MIMXRT1052xxx6B" - }, "STM32F072RB": { "OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB" }, From a4ed28163e8aae1a3791a87ab1a91399646fbac8 Mon Sep 17 00:00:00 2001 From: Michael Schwarcz Date: Sun, 13 Jan 2019 15:58:27 +0200 Subject: [PATCH 009/109] Force adding mbed-os root to include dirs --- tools/resources/__init__.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/resources/__init__.py b/tools/resources/__init__.py index d1b948999d..243b6c0c5d 100644 --- a/tools/resources/__init__.py +++ b/tools/resources/__init__.py @@ -38,7 +38,7 @@ from collections import namedtuple, defaultdict from copy import copy from itertools import chain from os import walk, sep -from os.path import (join, splitext, dirname, relpath, basename, split, normcase, +from os.path import (join, splitext, dirname, relpath, basename, split, normpath, abspath, exists) from .ignore import MbedIgnoreSet, IGNORE_FILENAME @@ -148,6 +148,11 @@ class Resources(object): self._ignoreset = MbedIgnoreSet() + # make sure mbed-os root is added as include directory + script_dir = dirname(abspath(__file__)) + mbed_os_root_dir = normpath(join(script_dir, '..', '..')) + self.add_file_ref(FileType.INC_DIR, mbed_os_root_dir, mbed_os_root_dir) + def ignore_dir(self, directory): if self._collect_ignores: self.ignored_dirs.append(directory) From 2636b7ea119e12268d5b1f4ae5ce010d55277760 Mon Sep 17 00:00:00 2001 From: Oren Cohen Date: Sun, 10 Feb 2019 16:53:47 +0200 Subject: [PATCH 010/109] Check source relative to ROOT on secure targets When building secure targets, we would like compile only files that are in the the mbe-os root folder. This Fixes an issue when sending multiple --source parameters that are all inside the mbed-os tree --- tools/build.py | 19 ++++++------------- tools/make.py | 6 ++++-- tools/paths.py | 10 +++++++++- tools/test.py | 6 ++++-- 4 files changed, 23 insertions(+), 18 deletions(-) diff --git a/tools/build.py b/tools/build.py index 40b0a52771..c7962c5d2b 100644 --- a/tools/build.py +++ b/tools/build.py @@ -43,6 +43,7 @@ from tools.settings import CPPCHECK_CMD, CPPCHECK_MSG_FORMAT, CLI_COLOR_MAP from tools.notifier.term import TerminalNotifier from tools.utils import argparse_filestring_type, args_error, argparse_many from tools.utils import argparse_filestring_type, argparse_dir_not_parent +from tools.paths import is_relative_to_root if __name__ == '__main__': start = time() @@ -188,19 +189,11 @@ if __name__ == '__main__': mcu = TARGET_MAP[target] profile = extract_profile(parser, options, toolchain) - if mcu.is_PSA_secure_target: - lib_build_res = build_library( - ROOT, options.build_dir, mcu, toolchain, - jobs=options.jobs, - clean=options.clean, - archive=(not options.no_archive), - macros=options.macros, - name=options.artifact_name, - build_profile=profile, - ignore=options.ignore, - notify=notifier, - ) - elif options.source_dir: + if mcu.is_PSA_secure_target and \ + not is_relative_to_root(options.source_dir): + options.source_dir = ROOT + + if options.source_dir: lib_build_res = build_library( options.source_dir, options.build_dir, mcu, toolchain, jobs=options.jobs, diff --git a/tools/make.py b/tools/make.py index 606ed257f0..17802b5bb1 100644 --- a/tools/make.py +++ b/tools/make.py @@ -34,6 +34,7 @@ from tools.paths import MBED_LIBRARIES from tools.paths import RPC_LIBRARY from tools.paths import USB_LIBRARIES from tools.paths import DSP_LIBRARIES +from tools.paths import is_relative_to_root from tools.tests import TESTS, Test, TEST_MAP from tools.tests import TEST_MBED_LIB from tools.tests import test_known, test_name_known @@ -307,8 +308,9 @@ if __name__ == '__main__': args_error(parser, "argument -t/--tool is required") toolchain = options.tool[0] - if Target.get_target(mcu).is_PSA_secure_target: - options.source_dir = ROOT + if Target.get_target(mcu).is_PSA_secure_target and \ + not is_relative_to_root(options.source_dir): + options.source_dir = ROOT if (options.program is None) and (not options.source_dir): args_error(parser, "one of -p, -n, or --source is required") diff --git a/tools/paths.py b/tools/paths.py index c8e745b00b..d29eb15d96 100644 --- a/tools/paths.py +++ b/tools/paths.py @@ -14,7 +14,7 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. """ -from os.path import join +from os.path import join, commonprefix, realpath from os import getenv # Conventions about the directory structure @@ -85,3 +85,11 @@ CPPUTEST_TESTRUNNER_SCR = join(TEST_DIR, "utest", "testrunner") CPPUTEST_TESTRUNNER_INC = join(TEST_DIR, "utest", "testrunner") CPPUTEST_LIBRARY = join(BUILD_DIR, "cpputest") + + +def is_relative_to_root(dirs): + if not isinstance(dirs, list): + dirs = [dirs] + dirs = [realpath(d) for d in dirs] + out = commonprefix(dirs + [ROOT]) + return out == ROOT diff --git a/tools/test.py b/tools/test.py index 84bfd6bbbe..0c7ee08300 100644 --- a/tools/test.py +++ b/tools/test.py @@ -45,6 +45,8 @@ from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS, TOOLCHAIN_CLASSES from tools.settings import CLI_COLOR_MAP from tools.settings import ROOT from tools.targets import Target +from tools.paths import is_relative_to_root + if __name__ == '__main__': try: # Parse Options @@ -211,8 +213,8 @@ if __name__ == '__main__': if not options.build_dir: args_error(parser, "argument --build is required") - if mcu_secured: - base_source_paths = ROOT + if mcu_secured and not is_relative_to_root(options.source_dir): + options.source_dir = ROOT else: base_source_paths = options.source_dir From 1b8fe3e58e5961fc90e27b84b61105e91f138c96 Mon Sep 17 00:00:00 2001 From: Oren Cohen Date: Mon, 11 Feb 2019 10:38:41 +0200 Subject: [PATCH 011/109] Update test.py --- tools/test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/test.py b/tools/test.py index 0c7ee08300..3e0996a2b1 100644 --- a/tools/test.py +++ b/tools/test.py @@ -214,7 +214,7 @@ if __name__ == '__main__': args_error(parser, "argument --build is required") if mcu_secured and not is_relative_to_root(options.source_dir): - options.source_dir = ROOT + base_source_paths = ROOT else: base_source_paths = options.source_dir From 36bf40cd79656c8bcb5df28ff9db6ede063ad042 Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Mon, 14 Jan 2019 16:56:07 +0000 Subject: [PATCH 012/109] BLE - Nordic: Release crypto cell when not in use. Previously, the CryptoToolbox was allocated once as part of the security manager. This was inneficient memory wise as it is only use to prepare key at initialization and when we need to compute shared keys. This was also inneficient power consumption wise as the Crypto cell was kept enabled even when it wasn't used. This fix creates a CryptoToolbox whenever it is needed and release it once it has fulfilled its purpose. Note that CryptoToolbox allocation happens on the heap as mbed tls data structure are huge and there's an high risk of crushing the stack. --- .../source/nRF5xPalSecurityManager.cpp | 18 ++++++++++++------ .../source/nRF5xPalSecurityManager.h | 1 - 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.cpp index 01126720b4..78904d3312 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.cpp @@ -107,15 +107,17 @@ nRF5xSecurityManager::~nRF5xSecurityManager() ble_error_t nRF5xSecurityManager::initialize() { #if defined(MBEDTLS_ECDH_C) - if (_crypto.generate_keys( + // Note: we do not use the object on the stack as the CryptoToolbox is quite large + // Please do not change or we risk a stack overflow. + CryptoToolbox* crypto = new CryptoToolbox(); + bool success = crypto->generate_keys( make_ArrayView(X), make_ArrayView(Y), make_ArrayView(secret) - )) { - return BLE_ERROR_NONE; - } + ); + delete crypto; - return BLE_ERROR_INTERNAL_STACK_FAILURE; + return success ? BLE_ERROR_NONE : BLE_ERROR_INTERNAL_STACK_FAILURE; #endif return BLE_ERROR_NONE; } @@ -943,12 +945,16 @@ bool nRF5xSecurityManager::sm_handler(const ble_evt_t *evt) static const size_t key_size = public_key_coord_t::size_; ble_gap_lesc_dhkey_t shared_secret; - _crypto.generate_shared_secret( + // Allocated on the heap to reduce stack pressure. + // Risk stack overflows if allocated on stack. + CryptoToolbox* crypto = new CryptoToolbox(); + crypto->generate_shared_secret( make_const_ArrayView(dhkey_request.p_pk_peer->pk), make_const_ArrayView(dhkey_request.p_pk_peer->pk + key_size), make_const_ArrayView(secret), shared_secret.key ); + delete crypto; sd_ble_gap_lesc_dhkey_reply(connection, &shared_secret); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.h index 30ac7e20cc..b5a55d9dc0 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xPalSecurityManager.h @@ -360,7 +360,6 @@ private: pairing_control_block_t* _control_blocks; #if defined(MBEDTLS_ECDH_C) - CryptoToolbox _crypto; ble::public_key_coord_t X; ble::public_key_coord_t Y; ble::public_key_coord_t secret; From 42d9fdd69d9a134628aaa465d0d26abd8b5fbc3f Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Fri, 1 Feb 2019 14:22:05 +0200 Subject: [PATCH 013/109] Greentea UDPSOCKET_RECV_TIMEOUT increase time tolerance --- TESTS/netsocket/udp/udpsocket_recv_timeout.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/netsocket/udp/udpsocket_recv_timeout.cpp b/TESTS/netsocket/udp/udpsocket_recv_timeout.cpp index 3592d307ce..6db0e22b82 100644 --- a/TESTS/netsocket/udp/udpsocket_recv_timeout.cpp +++ b/TESTS/netsocket/udp/udpsocket_recv_timeout.cpp @@ -62,7 +62,7 @@ void UDPSOCKET_RECV_TIMEOUT() if (recvd == NSAPI_ERROR_WOULD_BLOCK) { osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT); printf("MBED: recvfrom() took: %dms\n", timer.read_ms()); - TEST_ASSERT_INT_WITHIN(50, 150, timer.read_ms()); + TEST_ASSERT_INT_WITHIN(51, 150, timer.read_ms()); continue; } else if (recvd < 0) { printf("[bt#%02d] network error %d\n", i, recvd); From b88d69d1198e0d145be16aba488ceca22f0dadb0 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Fri, 1 Feb 2019 14:23:22 +0200 Subject: [PATCH 014/109] Greentea Socket bind tests made ipv6-aware --- TESTS/netsocket/tcp/main.cpp | 9 +++++++++ TESTS/netsocket/tcp/tcp_tests.h | 1 + .../netsocket/tcp/tcpsocket_bind_address_invalid.cpp | 9 ++++++++- TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp | 9 ++++++++- TESTS/netsocket/udp/main.cpp | 9 +++++++++ TESTS/netsocket/udp/udp_tests.h | 1 + .../netsocket/udp/udpsocket_bind_address_invalid.cpp | 11 ++++++++++- TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp | 9 ++++++++- 8 files changed, 54 insertions(+), 4 deletions(-) diff --git a/TESTS/netsocket/tcp/main.cpp b/TESTS/netsocket/tcp/main.cpp index 36f453532a..b49e9a9689 100644 --- a/TESTS/netsocket/tcp/main.cpp +++ b/TESTS/netsocket/tcp/main.cpp @@ -57,6 +57,15 @@ void drop_bad_packets(TCPSocket &sock, int orig_timeout) sock.set_timeout(orig_timeout); } +nsapi_version_t get_ip_version() +{ + SocketAddress test; + if (!test.set_ip_address(NetworkInterface::get_default_instance()->get_ip_address())) { + return NSAPI_UNSPEC; + } + return test.get_ip_version(); +} + static void _ifup() { NetworkInterface *net = NetworkInterface::get_default_instance(); diff --git a/TESTS/netsocket/tcp/tcp_tests.h b/TESTS/netsocket/tcp/tcp_tests.h index 8314a30da5..e03f8414ef 100644 --- a/TESTS/netsocket/tcp/tcp_tests.h +++ b/TESTS/netsocket/tcp/tcp_tests.h @@ -20,6 +20,7 @@ NetworkInterface *get_interface(); void drop_bad_packets(TCPSocket &sock, int orig_timeout); +nsapi_version_t get_ip_version(); void fill_tx_buffer_ascii(char *buff, size_t len); nsapi_error_t tcpsocket_connect_to_echo_srv(TCPSocket &sock); nsapi_error_t tcpsocket_connect_to_discard_srv(TCPSocket &sock); diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_address_invalid.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_address_invalid.cpp index 4e0c568ce7..933926ede4 100644 --- a/TESTS/netsocket/tcp/tcpsocket_bind_address_invalid.cpp +++ b/TESTS/netsocket/tcp/tcpsocket_bind_address_invalid.cpp @@ -39,7 +39,14 @@ void TCPSOCKET_BIND_ADDRESS_INVALID() return; } TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(NetworkInterface::get_default_instance())); - nsapi_error_t bind_result = sock->bind("190.2.3.4", 1024); + nsapi_error_t bind_result = NSAPI_ERROR_OK; + if (get_ip_version() == NSAPI_IPv4) { + bind_result = sock->bind("190.2.3.4", 1024); + } else if (get_ip_version() == NSAPI_IPv6) { + bind_result = sock->bind("fe80::ff01", 1024); + } else { + TEST_FAIL_MESSAGE("This stack is neither IPv4 nor IPv6"); + } if (bind_result == NSAPI_ERROR_UNSUPPORTED) { TEST_IGNORE_MESSAGE("bind() not supported"); } else { diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp index be223b0f2c..6a388b5ca6 100644 --- a/TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp +++ b/TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp @@ -40,7 +40,14 @@ void TCPSOCKET_BIND_WRONG_TYPE() } TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(NetworkInterface::get_default_instance())); char addr_bytes[16] = {0xfe, 0x80, 0xff, 0x1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - SocketAddress sockAddr = SocketAddress(addr_bytes, NSAPI_IPv4, 80); + SocketAddress sockAddr; + if (get_ip_version() == NSAPI_IPv4) { + sockAddr = SocketAddress(addr_bytes, NSAPI_IPv4, 80); + } else if (get_ip_version() == NSAPI_IPv6) { + sockAddr = SocketAddress(addr_bytes, NSAPI_IPv6, 80); + } else { + TEST_FAIL_MESSAGE("This stack is neither IPv4 nor IPv6"); + } nsapi_error_t bind_result = sock->bind(sockAddr); if (bind_result == NSAPI_ERROR_UNSUPPORTED) { TEST_IGNORE_MESSAGE("bind() not supported"); diff --git a/TESTS/netsocket/udp/main.cpp b/TESTS/netsocket/udp/main.cpp index 9f9b7e950a..f8b87e30b7 100644 --- a/TESTS/netsocket/udp/main.cpp +++ b/TESTS/netsocket/udp/main.cpp @@ -64,6 +64,15 @@ void drop_bad_packets(UDPSocket &sock, int orig_timeout) sock.set_timeout(orig_timeout); } +nsapi_version_t get_ip_version() +{ + SocketAddress test; + if (!test.set_ip_address(NetworkInterface::get_default_instance()->get_ip_address())) { + return NSAPI_UNSPEC; + } + return test.get_ip_version(); +} + void fill_tx_buffer_ascii(char *buff, size_t len) { for (size_t i = 0; i < len; ++i) { diff --git a/TESTS/netsocket/udp/udp_tests.h b/TESTS/netsocket/udp/udp_tests.h index b740ada298..34a06670a3 100644 --- a/TESTS/netsocket/udp/udp_tests.h +++ b/TESTS/netsocket/udp/udp_tests.h @@ -20,6 +20,7 @@ NetworkInterface *get_interface(); void drop_bad_packets(UDPSocket &sock, int orig_timeout); +nsapi_version_t get_ip_version(); void fill_tx_buffer_ascii(char *buff, size_t len); #if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE diff --git a/TESTS/netsocket/udp/udpsocket_bind_address_invalid.cpp b/TESTS/netsocket/udp/udpsocket_bind_address_invalid.cpp index e0cee8a360..44b0717685 100644 --- a/TESTS/netsocket/udp/udpsocket_bind_address_invalid.cpp +++ b/TESTS/netsocket/udp/udpsocket_bind_address_invalid.cpp @@ -38,7 +38,16 @@ void UDPSOCKET_BIND_ADDRESS_INVALID() TEST_FAIL(); } TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(NetworkInterface::get_default_instance())); - nsapi_error_t bind_result = sock->bind("190.2.3.4", 1024); + + nsapi_error_t bind_result = NSAPI_ERROR_OK; + if (get_ip_version() == NSAPI_IPv4) { + bind_result = sock->bind("190.2.3.4", 1024); + } else if (get_ip_version() == NSAPI_IPv6) { + bind_result = sock->bind("fe80::ff01", 1024); + } else { + TEST_FAIL_MESSAGE("This stack is neither IPv4 nor IPv6"); + } + if (bind_result == NSAPI_ERROR_UNSUPPORTED) { TEST_IGNORE_MESSAGE("bind() not supported"); } else { diff --git a/TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp b/TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp index 5925af6254..f6a6e7928b 100644 --- a/TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp +++ b/TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp @@ -39,7 +39,14 @@ void UDPSOCKET_BIND_WRONG_TYPE() } TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(NetworkInterface::get_default_instance())); char addr_bytes[16] = {0xfe, 0x80, 0xff, 0x1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - SocketAddress sockAddr = SocketAddress(addr_bytes, NSAPI_IPv4, 80); + SocketAddress sockAddr; + if (get_ip_version() == NSAPI_IPv4) { + sockAddr = SocketAddress(addr_bytes, NSAPI_IPv4, 80); + } else if (get_ip_version() == NSAPI_IPv6) { + sockAddr = SocketAddress(addr_bytes, NSAPI_IPv6, 80); + } else { + TEST_FAIL_MESSAGE("This stack is neither IPv4 nor IPv6"); + } nsapi_error_t bind_result = sock->bind(sockAddr); if (bind_result == NSAPI_ERROR_UNSUPPORTED) { TEST_IGNORE_MESSAGE("bind() not supported"); From 4a92a1361c904e27508913206dd62f30519e5ac5 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Fri, 1 Feb 2019 14:48:15 +0200 Subject: [PATCH 015/109] Greentea DNS test: added debug print --- TESTS/netsocket/dns/asynchronous_dns_cancel.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/TESTS/netsocket/dns/asynchronous_dns_cancel.cpp b/TESTS/netsocket/dns/asynchronous_dns_cancel.cpp index 2c866cf6f7..e5594e16f4 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_cancel.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_cancel.cpp @@ -42,6 +42,7 @@ void ASYNCHRONOUS_DNS_CANCEL() count++; } else { // No memory to initiate DNS query, callback will not be called + printf("Error: No memory to initiate DNS query for %s\n", dns_test_hosts[i]); data[i].result = NSAPI_ERROR_NO_MEMORY; data[i].value_set = true; } From 3f11bf5d915117dbea16578d8cc3c8f722e303da Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Fri, 1 Feb 2019 17:11:53 +0200 Subject: [PATCH 016/109] TLSSocket returns WOULD_BLOCK error instead of ALREADY In case mbedtls fails to execute handshake advertising MBEDTLS_ERR_SSL_WANT_READ or MBEDTLS_ERR_SSL_WANT_WRITE, TLSSocketWrapper::continue_handshake returns NSAPI_ERROR_WOULD_BLOCK. --- features/netsocket/TLSSocketWrapper.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/netsocket/TLSSocketWrapper.cpp b/features/netsocket/TLSSocketWrapper.cpp index eb75479a84..5e65758784 100644 --- a/features/netsocket/TLSSocketWrapper.cpp +++ b/features/netsocket/TLSSocketWrapper.cpp @@ -287,7 +287,7 @@ nsapi_error_t TLSSocketWrapper::send(const void *data, nsapi_size_t size) ret = continue_handshake(); if (ret != NSAPI_ERROR_IS_CONNECTED) { if (ret == NSAPI_ERROR_ALREADY) { - ret = NSAPI_ERROR_NO_CONNECTION; + ret = NSAPI_ERROR_WOULD_BLOCK; } return ret; } @@ -341,7 +341,7 @@ nsapi_size_or_error_t TLSSocketWrapper::recv(void *data, nsapi_size_t size) ret = continue_handshake(); if (ret != NSAPI_ERROR_IS_CONNECTED) { if (ret == NSAPI_ERROR_ALREADY) { - ret = NSAPI_ERROR_NO_CONNECTION; + ret = NSAPI_ERROR_WOULD_BLOCK; } return ret; } From 035ecc15d633763ab8d3d60ab0869dee210e2472 Mon Sep 17 00:00:00 2001 From: Alexander Zilberkant Date: Mon, 4 Feb 2019 21:52:39 +0200 Subject: [PATCH 017/109] Restore MBEDTLS_PSA_CRYPTO_C for PSA targets Removed by mistake in 763cb4c157f2c99babae932f88315ad67d2bc173 --- targets/targets.json | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index a64966fd42..8d99432812 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1743,7 +1743,7 @@ "PSA" ], "is_disk_virtual": true, - "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"], + "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED", "MBEDTLS_PSA_CRYPTO_C"], "inherits": ["Target"], "detect_code": ["0311"], "device_has": [ @@ -2435,7 +2435,7 @@ "macro_name": "CLOCK_SOURCE_USB" } }, - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "MBEDTLS_PSA_CRYPTO_C"], "device_has_add": [ "SERIAL_ASYNCH", "FLASH", @@ -2684,7 +2684,8 @@ "components_add": ["FLASHIAP"], "macros_add": [ "USB_STM_HAL", - "USBHOST_OTHER" + "USBHOST_OTHER", + "MBEDTLS_PSA_CRYPTO_C" ], "device_has_add": [ "ANALOGOUT", @@ -4231,6 +4232,9 @@ "device_has_remove": [], "extra_labels_add": ["PSA"], "components_add": ["FLASHIAP"], + "macros_add": [ + "MBEDTLS_PSA_CRYPTO_C" + ], "config": { "stdio_uart_tx_help": { "help": "Value: D8(default) or D1" From b2b7afeeb5e70f8278ae82e4d0d5471b2a83fd72 Mon Sep 17 00:00:00 2001 From: offirko Date: Sun, 10 Feb 2019 10:38:46 +0200 Subject: [PATCH 018/109] Fix general block device test to ensure unique block address per test --- .../storage/TESTS/blockdevice/general_block_device/main.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/features/storage/TESTS/blockdevice/general_block_device/main.cpp b/features/storage/TESTS/blockdevice/general_block_device/main.cpp index 5e47ad8b0e..fecfe1a0db 100644 --- a/features/storage/TESTS/blockdevice/general_block_device/main.cpp +++ b/features/storage/TESTS/blockdevice/general_block_device/main.cpp @@ -187,6 +187,11 @@ void basic_erase_program_read_test(BlockDevice *block_device, bd_size_t block_si { int err = 0; _mutex->lock(); + + // Make sure block address per each test is unique + static unsigned block_seed = 1; + srand(block_seed++); + // Find a random block bd_addr_t block = (rand() * block_size) % (block_device->size()); From 19b50ef7a83d8c538a1ecd4ec4853f1cf94d9e0e Mon Sep 17 00:00:00 2001 From: offirko Date: Sun, 10 Feb 2019 10:49:19 +0200 Subject: [PATCH 019/109] Ensure unique block address for multi threaded test. The addresses dont have to change each run, just be unique. Because address seeds repeat themselves each run, rand() will produce repeating results that should not collide between different threads. --- .../COMPONENT_SPIF/TESTS/block_device/spif/main.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/components/storage/blockdevice/COMPONENT_SPIF/TESTS/block_device/spif/main.cpp b/components/storage/blockdevice/COMPONENT_SPIF/TESTS/block_device/spif/main.cpp index c012c4a6e9..ad2b2636ed 100644 --- a/components/storage/blockdevice/COMPONENT_SPIF/TESTS/block_device/spif/main.cpp +++ b/components/storage/blockdevice/COMPONENT_SPIF/TESTS/block_device/spif/main.cpp @@ -47,6 +47,11 @@ void basic_erase_program_read_test(SPIFBlockDevice &block_device, bd_size_t bloc { int err = 0; _mutex->lock(); + + // Make sure block address per each test is unique + static unsigned block_seed = 1; + srand(block_seed++); + // Find a random block bd_addr_t block = (rand() * block_size) % block_device.size(); From 693245d802225468c85f9d5e8549799dc3d7d857 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Mon, 11 Feb 2019 13:36:15 +0800 Subject: [PATCH 020/109] Fix crypto AC mgmt Port of NUC472/M487 crypto AC mgmt work to M2351: 1. Choose mutex to synchronize access to crypto non-SHA AC 2. Choose atomic flag to synchronize access to crypto SHA AC --- .../crypto/{crypto-misc.c => crypto-misc.cpp} | 103 +++++++++++------- .../TARGET_M2351/crypto/crypto-misc.h | 39 ++++--- 2 files changed, 84 insertions(+), 58 deletions(-) rename targets/TARGET_NUVOTON/TARGET_M2351/crypto/{crypto-misc.c => crypto-misc.cpp} (79%) diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp similarity index 79% rename from targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.c rename to targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp index 57c960924b..a2a8426a0a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp @@ -19,33 +19,56 @@ #include "mbed_assert.h" #include "mbed_critical.h" #include "mbed_error.h" +#if MBED_CONF_RTOS_PRESENT +#include "cmsis_os2.h" +#endif +#include #include #include "nu_modutil.h" #include "nu_bitutil.h" #include "crypto-misc.h" +#include "platform/SingletonPtr.h" +#include "platform/PlatformMutex.h" #if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) +/* Consideration for choosing proper synchronization mechanism + * + * 1. We choose mutex to synchronize access to crypto non-SHA AC. We can guarantee: + * (1) No deadlock + * We just lock mutex for a short sequence of operations rather than the whole lifetime + * of crypto context. + * (2) No priority inversion + * Mutex supports priority inheritance and it is enabled. + * 2. We choose atomic flag to synchronize access to crypto SHA AC. We can guarantee: + * (1) No deadlock + * With SHA AC not supporting context save & restore, we provide SHA S/W fallback when + * SHA AC is not available. + * (2) No biting CPU + * Same reason as above. + */ + +/* Mutex for crypto AES AC management */ +static SingletonPtr crypto_aes_mutex; + +/* Mutex for crypto DES AC management */ +static SingletonPtr crypto_des_mutex; + +/* Mutex for crypto ECC AC management */ +static SingletonPtr crypto_ecc_mutex; + +/* Atomic flag for crypto SHA AC management */ +static core_util_atomic_flag crypto_sha_atomic_flag = CORE_UTIL_ATOMIC_FLAG_INIT; + /* NOTE: There's inconsistency in cryptography related naming, Crpt or Crypto. For example, cryptography IRQ * handler could be CRPT_IRQHandler or CRYPTO_IRQHandler. To override default cryptography IRQ handler, see * device/startup_{CHIP}.c for its name or call NVIC_SetVector regardless of its name. */ void CRPT_IRQHandler(); -/* Track if AES H/W is available */ -static uint16_t crypto_aes_avail = 1; -/* Track if DES H/W is available */ -static uint16_t crypto_des_avail = 1; -/* Track if SHA H/W is available */ -static uint16_t crypto_sha_avail = 1; -/* Track if ECC H/W is available */ -static uint16_t crypto_ecc_avail = 1; /* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ static uint16_t crypto_init_counter = 0U; -static bool crypto_submodule_acquire(uint16_t *submodule_avail); -static void crypto_submodule_release(uint16_t *submodule_avail); - /* Crypto done flags */ #define CRYPTO_DONE_OK BIT0 /* Done with OK */ #define CRYPTO_DONE_ERR BIT1 /* Done with error */ @@ -131,44 +154,52 @@ void crypto_zeroize32(uint32_t *v, size_t n) } } -bool crypto_aes_acquire(void) +void crypto_aes_acquire(void) { - return crypto_submodule_acquire(&crypto_aes_avail); + /* Don't check return code of Mutex::lock(void) + * + * This function treats RTOS errors as fatal system errors, so it can only return osOK. + * Use of the return value is deprecated, as the return is expected to become void in + * the future. + */ + crypto_aes_mutex->lock(); } void crypto_aes_release(void) { - crypto_submodule_release(&crypto_aes_avail); + crypto_aes_mutex->unlock(); } -bool crypto_des_acquire(void) +void crypto_des_acquire(void) { - return crypto_submodule_acquire(&crypto_des_avail); + /* Don't check return code of Mutex::lock(void) */ + crypto_des_mutex->lock(); } void crypto_des_release(void) { - crypto_submodule_release(&crypto_des_avail); + crypto_des_mutex->unlock(); } -bool crypto_sha_acquire(void) +void crypto_ecc_acquire(void) { - return crypto_submodule_acquire(&crypto_sha_avail); -} - -void crypto_sha_release(void) -{ - crypto_submodule_release(&crypto_sha_avail); -} - -bool crypto_ecc_acquire(void) -{ - return crypto_submodule_acquire(&crypto_ecc_avail); + /* Don't check return code of Mutex::lock(void) */ + crypto_ecc_mutex->lock(); } void crypto_ecc_release(void) { - crypto_submodule_release(&crypto_ecc_avail); + crypto_ecc_mutex->unlock(); +} + +bool crypto_sha_try_acquire(void) +{ + return !core_util_atomic_flag_test_and_set(&crypto_sha_atomic_flag); +} + +void crypto_sha_release(void) +{ + core_util_atomic_flag_clear(&crypto_sha_atomic_flag); } void crypto_prng_prestart(void) @@ -252,18 +283,6 @@ bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const vo return overlap; } -static bool crypto_submodule_acquire(uint16_t *submodule_avail) -{ - uint16_t expectedCurrentValue = 1; - return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0); -} - -static void crypto_submodule_release(uint16_t *submodule_avail) -{ - uint16_t expectedCurrentValue = 0; - while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); -} - static void crypto_submodule_prestart(volatile uint16_t *submodule_done) { *submodule_done = 0; diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.h index c675cd76e3..a29e790c17 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.h @@ -66,26 +66,33 @@ void crypto_uninit(void); void crypto_zeroize(void *v, size_t n); void crypto_zeroize32(uint32_t *v, size_t n); -/* Acquire/release ownership of AES H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_aes_acquire(void); +/* Acquire/release ownership of crypto sub-module + * + * \note "acquire" is blocking until ownership is acquired + * + * \note "acquire"/"release" must be paired. + * + * \note Recursive "acquire" is allowed because the underlying synchronization + * primitive mutex supports it. + */ +void crypto_aes_acquire(void); void crypto_aes_release(void); - -/* Acquire/release ownership of DES H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_des_acquire(void); +void crypto_des_acquire(void); void crypto_des_release(void); - -/* Acquire/release ownership of SHA H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_sha_acquire(void); -void crypto_sha_release(void); - -/* Acquire/release ownership of ECC H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_ecc_acquire(void); +void crypto_ecc_acquire(void); void crypto_ecc_release(void); +/* Acquire/release ownership of crypto sub-module + * + * \return false if crytpo sub-module is held by another thread or + * another mbedtls context. + * true if successful + * + * \note Successful "try_acquire" and "release" must be paired. + */ +bool crypto_sha_try_acquire(void); +void crypto_sha_release(void); + /* Flow control between crypto/xxx start and crypto/xxx ISR * * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. From e5e9e4f3891e5c7df09eb8ddc84dfd76a9d1fdd7 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Mon, 11 Feb 2019 14:21:41 +0800 Subject: [PATCH 021/109] Hook crypto interrupt handler without NVIC_SetVector --- .../TARGET_M2351/crypto/crypto-misc.cpp | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp index a2a8426a0a..9a6df270ab 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp +++ b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp @@ -60,11 +60,6 @@ static SingletonPtr crypto_ecc_mutex; /* Atomic flag for crypto SHA AC management */ static core_util_atomic_flag crypto_sha_atomic_flag = CORE_UTIL_ATOMIC_FLAG_INIT; -/* NOTE: There's inconsistency in cryptography related naming, Crpt or Crypto. For example, cryptography IRQ - * handler could be CRPT_IRQHandler or CRYPTO_IRQHandler. To override default cryptography IRQ handler, see - * device/startup_{CHIP}.c for its name or call NVIC_SetVector regardless of its name. */ -void CRPT_IRQHandler(); - /* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ static uint16_t crypto_init_counter = 0U; @@ -104,8 +99,7 @@ void crypto_init(void) * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. */ CLK_EnableModuleClock_S(CRPT_MODULE); - - NVIC_SetVector(CRPT_IRQn, (uint32_t) CRPT_IRQHandler); + NVIC_EnableIRQ(CRPT_IRQn); } core_util_critical_section_exit(); @@ -315,8 +309,13 @@ static bool crypto_submodule_wait(volatile uint16_t *submodule_done) return false; } -/* Crypto interrupt handler */ -void CRPT_IRQHandler() +/* Crypto interrupt handler + * + * There's inconsistency in cryptography related naming, Crpt or Crypto. For example, + * cryptography IRQ handler could be CRPT_IRQHandler or CRYPTO_IRQHandler. To override + * default cryptography IRQ handler, see device/startup_{CHIP}.c for its correct name + * or call NVIC_SetVector() in crypto_init() regardless of its name. */ +extern "C" void CRPT_IRQHandler() { uint32_t intsts; From 39262235b107b2ed1a92e7918a7d41359999d7fd Mon Sep 17 00:00:00 2001 From: ccli8 Date: Mon, 11 Feb 2019 18:10:51 +0800 Subject: [PATCH 022/109] Remove unnecessary header files in crypto-misc.cpp --- targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp | 4 ---- targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp | 4 ---- targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp | 4 ---- 3 files changed, 12 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp index 9a6df270ab..eed2603836 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp +++ b/targets/TARGET_NUVOTON/TARGET_M2351/crypto/crypto-misc.cpp @@ -19,10 +19,6 @@ #include "mbed_assert.h" #include "mbed_critical.h" #include "mbed_error.h" -#if MBED_CONF_RTOS_PRESENT -#include "cmsis_os2.h" -#endif -#include #include #include "nu_modutil.h" #include "nu_bitutil.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp index 13000985af..18f517a844 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp @@ -19,10 +19,6 @@ #include "mbed_assert.h" #include "mbed_critical.h" #include "mbed_error.h" -#if MBED_CONF_RTOS_PRESENT -#include "cmsis_os2.h" -#endif -#include #include #include "nu_modutil.h" #include "nu_bitutil.h" diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp index f771a3e510..e4fd9143c3 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp @@ -19,10 +19,6 @@ #include "mbed_assert.h" #include "mbed_critical.h" #include "mbed_error.h" -#if MBED_CONF_RTOS_PRESENT -#include "cmsis_os2.h" -#endif -#include #include #include "nu_modutil.h" #include "nu_bitutil.h" From 306943a5823da2f146c12ed8c43c2b288b83445d Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Tue, 29 Jan 2019 15:10:45 +0200 Subject: [PATCH 023/109] Cellular: Fix socket bind tests for BG96 --- .../framework/AT/AT_CellularStack.cpp | 27 +++++++++++++++---- .../cellular/framework/AT/AT_CellularStack.h | 2 ++ .../BG96/QUECTEL_BG96_CellularStack.cpp | 12 +++++++++ .../QUECTEL/BG96/QUECTEL_BG96_CellularStack.h | 1 + 4 files changed, 37 insertions(+), 5 deletions(-) diff --git a/features/cellular/framework/AT/AT_CellularStack.cpp b/features/cellular/framework/AT/AT_CellularStack.cpp index a43e2ebd89..ad4932c072 100644 --- a/features/cellular/framework/AT/AT_CellularStack.cpp +++ b/features/cellular/framework/AT/AT_CellularStack.cpp @@ -198,15 +198,21 @@ nsapi_error_t AT_CellularStack::socket_bind(nsapi_socket_t handle, const SocketA } if (addr) { - socket->localAddress.set_addr(addr.get_addr()); - } - - if (addr.get_port()) { - socket->localAddress.set_port(addr.get_port()); + return NSAPI_ERROR_UNSUPPORTED; } _at.lock(); + uint16_t port = addr.get_port(); + if (port != socket->localAddress.get_port()) { + if (port && (get_socket_index_by_port(port) == -1)) { + socket->localAddress.set_port(port); + } else { + _at.unlock(); + return NSAPI_ERROR_PARAMETER; + } + } + if (!socket->created) { create_socket_impl(socket); } @@ -340,3 +346,14 @@ void AT_CellularStack::socket_attach(nsapi_socket_t handle, void (*callback)(voi socket->_cb = callback; socket->_data = data; } + +int AT_CellularStack::get_socket_index_by_port(uint16_t port) +{ + int max_socket_count = get_max_socket_count(); + for (int i = 0; i < max_socket_count; i++) { + if (_socket[i]->localAddress.get_port() == port) { + return i; + } + } + return -1; +} diff --git a/features/cellular/framework/AT/AT_CellularStack.h b/features/cellular/framework/AT/AT_CellularStack.h index 2c25da1579..8ce5764665 100644 --- a/features/cellular/framework/AT/AT_CellularStack.h +++ b/features/cellular/framework/AT/AT_CellularStack.h @@ -184,6 +184,8 @@ protected: private: int find_socket_index(nsapi_socket_t handle); + int get_socket_index_by_port(uint16_t port); + // mutex for write/read to a _socket array, needed when multiple threads may open sockets simultaneously PlatformMutex _socket_mutex; }; diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp index 8d79fa6c74..4a71a87e0d 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp @@ -62,6 +62,10 @@ nsapi_error_t QUECTEL_BG96_CellularStack::socket_connect(nsapi_socket_t handle, handle_open_socket_response(modem_connect_id, err); if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) { + if (err == BG96_SOCKET_BIND_FAIL) { + socket->created = false; + return NSAPI_ERROR_PARAMETER; + } _at.cmd_start("AT+QICLOSE="); _at.write_int(modem_connect_id); _at.cmd_stop(); @@ -178,6 +182,10 @@ nsapi_error_t QUECTEL_BG96_CellularStack::create_socket_impl(CellularSocket *soc handle_open_socket_response(modem_connect_id, err); if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) { + if (err == BG96_SOCKET_BIND_FAIL) { + socket->created = false; + return NSAPI_ERROR_PARAMETER; + } _at.cmd_start("AT+QICLOSE="); _at.write_int(modem_connect_id); _at.cmd_stop_read_resp(); @@ -206,6 +214,10 @@ nsapi_error_t QUECTEL_BG96_CellularStack::create_socket_impl(CellularSocket *soc handle_open_socket_response(modem_connect_id, err); if ((_at.get_last_error() == NSAPI_ERROR_OK) && err) { + if (err == BG96_SOCKET_BIND_FAIL) { + socket->created = false; + return NSAPI_ERROR_PARAMETER; + } _at.cmd_start("AT+QICLOSE="); _at.write_int(modem_connect_id); _at.cmd_stop_read_resp(); diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h index 1b8e547530..f5de062ac4 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h @@ -25,6 +25,7 @@ namespace mbed { #define BG96_SOCKET_MAX 12 #define BG96_CREATE_SOCKET_TIMEOUT 150000 //150 seconds #define BG96_CLOSE_SOCKET_TIMEOUT 20000 // TCP socket max timeout is >10sec +#define BG96_SOCKET_BIND_FAIL 556 class QUECTEL_BG96_CellularStack : public AT_CellularStack { public: From 0ed5e805df5eae861b87eb7b06338a736cee6db2 Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Tue, 29 Jan 2019 15:13:04 +0200 Subject: [PATCH 024/109] Cellular: Fix socket's send and receive boundaries for BG96 --- .../QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp | 14 +++++++++++++- .../QUECTEL/BG96/QUECTEL_BG96_CellularStack.h | 2 ++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp index 4a71a87e0d..091a53fac7 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp @@ -251,6 +251,9 @@ nsapi_error_t QUECTEL_BG96_CellularStack::create_socket_impl(CellularSocket *soc nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_sendto_impl(CellularSocket *socket, const SocketAddress &address, const void *data, nsapi_size_t size) { + if (size > BG96_MAX_SEND_SIZE) { + return NSAPI_ERROR_PARAMETER; + } int sent_len = 0; int sent_len_before = 0; int sent_len_after = 0; @@ -308,6 +311,11 @@ nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_recvfrom_impl(CellularS _at.cmd_start("AT+QIRD="); _at.write_int(socket->id); + if (socket->proto == NSAPI_TCP) { + // do not read more than max size + size = size > BG96_MAX_RECV_SIZE ? BG96_MAX_RECV_SIZE : size; + _at.write_int(size); + } _at.cmd_stop(); _at.resp_start("+QIRD:"); @@ -315,11 +323,15 @@ nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_recvfrom_impl(CellularS _at.read_string(ip_address, sizeof(ip_address)); port = _at.read_int(); if (recv_len > 0) { + // do not read more than buffer size + recv_len = recv_len > size ? size : recv_len; _at.read_bytes((uint8_t *)buffer, recv_len); } _at.resp_stop(); - if (!recv_len || (_at.get_last_error() != NSAPI_ERROR_OK)) { + // We block only if 0 recv length really means no data. + // If 0 is followed by ip address and port can be an UDP 0 length packet + if (!recv_len && port < 0) { return NSAPI_ERROR_WOULD_BLOCK; } diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h index f5de062ac4..e8eb670c1c 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h @@ -25,6 +25,8 @@ namespace mbed { #define BG96_SOCKET_MAX 12 #define BG96_CREATE_SOCKET_TIMEOUT 150000 //150 seconds #define BG96_CLOSE_SOCKET_TIMEOUT 20000 // TCP socket max timeout is >10sec +#define BG96_MAX_RECV_SIZE 1500 +#define BG96_MAX_SEND_SIZE 1460 #define BG96_SOCKET_BIND_FAIL 556 class QUECTEL_BG96_CellularStack : public AT_CellularStack { From b8712b32813cf98a812a32b6d855d38f3a9171fe Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Fri, 8 Feb 2019 15:43:01 +0200 Subject: [PATCH 025/109] Cellular: Fix UDPSOCKET_SENDTO_INVALID test for BG96 --- .../targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp index 091a53fac7..59ec9487f4 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp @@ -254,6 +254,11 @@ nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_sendto_impl(CellularSoc if (size > BG96_MAX_SEND_SIZE) { return NSAPI_ERROR_PARAMETER; } + + if (!size && socket->proto == NSAPI_UDP) { + return NSAPI_ERROR_UNSUPPORTED; + } + int sent_len = 0; int sent_len_before = 0; int sent_len_after = 0; From 182f229a58a673b30e30459afa1e5881befa5a34 Mon Sep 17 00:00:00 2001 From: Aleksi Klasila Date: Mon, 11 Feb 2019 10:55:33 +0200 Subject: [PATCH 026/109] REALTEK_RTL8195AM daplink timestamp from os.environ --- tools/targets/REALTEK_RTL8195AM.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/targets/REALTEK_RTL8195AM.py b/tools/targets/REALTEK_RTL8195AM.py index 3dc1577e4e..a4eb02510f 100644 --- a/tools/targets/REALTEK_RTL8195AM.py +++ b/tools/targets/REALTEK_RTL8195AM.py @@ -147,7 +147,7 @@ def create_daplink(image_bin, ram1_bin, ram2_bin): RAM2_HEADER['tag'] = format_number(TAG, 8) RAM2_HEADER['ver'] = format_number(VER, 8) - RAM2_HEADER['timestamp'] = format_number(epoch_timestamp(), 16) + RAM2_HEADER['timestamp'] = format_number(int(os.environ.get('DAPLINK_TIMESTAMP', epoch_timestamp())), 16) RAM2_HEADER['size'] = format_number(os.stat(ram2_bin).st_size + 72, 8) RAM2_HEADER['hash'] = format_string(sha256_checksum(ram2_bin)) RAM2_HEADER['campaign'] = format_string(CAMPAIGN) From 3930d2e9973c0e0f24fd015da6f3a20b1ed97a8b Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Fri, 1 Feb 2019 14:11:55 -0600 Subject: [PATCH 027/109] targets: QUECTEL: Fix build warning Fix the following warning seen when built with GCC_ARM with mbed-cli v1.8.3 $ mbed compile -c -t GCC_ARM -m K64F [Warning] QUECTEL_M26_CellularStack.cpp@364,9: variable 'sent_acked' set but not used [-Wunused-but-set-variable] --- .../framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp index 20515438a2..0840edee8d 100644 --- a/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp @@ -361,10 +361,10 @@ nsapi_size_or_error_t QUECTEL_M26_CellularStack::socket_sendto_impl(CellularSock const void *data, nsapi_size_t size) { int sent_len = (size > M26_SENT_BYTE_MAX) ? M26_SENT_BYTE_MAX : size; - int sent_acked = 0; int sent_nacked = 0; int sent_len_before = 0; int sent_len_after = 0; + int sent_acked; nsapi_error_t error; tr_debug("QUECTEL_M26_CellularStack:%s:%u:[%d-%d]", __FUNCTION__, __LINE__, sent_len, size); From e8ce42ad83d727346fbdf51c061273fe081dbdf3 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Mon, 4 Feb 2019 15:32:15 +0100 Subject: [PATCH 028/109] STM32 GPIO: use maximum speed --- targets/TARGET_STM/pinmap.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index 5c92ad19bd..5076ef45ba 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -79,7 +79,13 @@ void pin_function(PinName pin, int data) #if defined (TARGET_STM32F1) if (mode == STM_PIN_OUTPUT) { #endif + +#if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) + LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); +#else LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); +#endif + #if defined (TARGET_STM32F1) } #endif From 46478abc6aba73664e9ba52197dc09d044dfea2b Mon Sep 17 00:00:00 2001 From: Veijo Pesonen Date: Thu, 31 Jan 2019 12:59:40 +0200 Subject: [PATCH 029/109] tests-netsocket-udp: UDPSOCKET_ECHOTEST_NONBLOCK restores non-blocking Fixes a bug where after dropping bad packets receiver doesn't restore the socket back to non-blocking state as it's supposed to. --- TESTS/netsocket/udp/udpsocket_echotest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/netsocket/udp/udpsocket_echotest.cpp b/TESTS/netsocket/udp/udpsocket_echotest.cpp index ffd3dc75e7..eb9c0c15e3 100644 --- a/TESTS/netsocket/udp/udpsocket_echotest.cpp +++ b/TESTS/netsocket/udp/udpsocket_echotest.cpp @@ -118,7 +118,7 @@ void udpsocket_echotest_nonblock_receiver(void *receive_bytes) } } - drop_bad_packets(sock, -1); // timeout equivalent to set_blocking(false) + drop_bad_packets(sock, 0); // timeout equivalent to set_blocking(false) tx_sem.release(); } From 1b5fdafce88182a5ce90257c57a3a3112d0968a7 Mon Sep 17 00:00:00 2001 From: Veijo Pesonen Date: Thu, 31 Jan 2019 14:22:47 +0200 Subject: [PATCH 030/109] tests-netsocket-udp: UDPSOCKET_ECHOTEST_NONBLOCK execution time limit Test case is allowed to take not more than a half what has been given to the whole UDP suite. UDP test cases reorganized so that the longest running ones are executed last. --- TESTS/netsocket/udp/main.cpp | 44 +++++++++++++--------- TESTS/netsocket/udp/udp_tests.h | 9 +++++ TESTS/netsocket/udp/udpsocket_echotest.cpp | 11 +++++- 3 files changed, 46 insertions(+), 18 deletions(-) diff --git a/TESTS/netsocket/udp/main.cpp b/TESTS/netsocket/udp/main.cpp index f8b87e30b7..0057aed55f 100644 --- a/TESTS/netsocket/udp/main.cpp +++ b/TESTS/netsocket/udp/main.cpp @@ -33,10 +33,26 @@ using namespace utest::v1; +namespace { +Timer tc_bucket; // Timer to limit a test cases run time +} + #if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE mbed_stats_socket_t udp_stats[MBED_CONF_NSAPI_SOCKET_STATS_MAX_COUNT]; #endif +void drop_bad_packets(UDPSocket &sock, int orig_timeout) +{ + nsapi_error_t err; + sock.set_timeout(0); + while (true) { + err = sock.recv(NULL, 0); + if (err == NSAPI_ERROR_WOULD_BLOCK) { + break; + } + } + sock.set_timeout(orig_timeout); +} static void _ifup() { NetworkInterface *net = NetworkInterface::get_default_instance(); @@ -51,18 +67,6 @@ static void _ifdown() printf("MBED: ifdown\n"); } -void drop_bad_packets(UDPSocket &sock, int orig_timeout) -{ - nsapi_error_t err; - sock.set_timeout(0); - while (true) { - err = sock.recvfrom(NULL, 0, 0); - if (err == NSAPI_ERROR_WOULD_BLOCK) { - break; - } - } - sock.set_timeout(orig_timeout); -} nsapi_version_t get_ip_version() { @@ -80,6 +84,11 @@ void fill_tx_buffer_ascii(char *buff, size_t len) } } +int split2half_rmng_udp_test_time() +{ + return (udp_global::TESTS_TIMEOUT - tc_bucket.read()) / 2; +} + #if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE int fetch_stats() { @@ -90,20 +99,20 @@ int fetch_stats() // Test setup utest::v1::status_t greentea_setup(const size_t number_of_cases) { - GREENTEA_SETUP(480, "default_auto"); + GREENTEA_SETUP(udp_global::TESTS_TIMEOUT, "default_auto"); _ifup(); + tc_bucket.start(); return greentea_test_setup_handler(number_of_cases); } void greentea_teardown(const size_t passed, const size_t failed, const failure_t failure) { + tc_bucket.stop(); _ifdown(); return greentea_test_teardown_handler(passed, failed, failure); } Case cases[] = { - Case("UDPSOCKET_ECHOTEST", UDPSOCKET_ECHOTEST), - Case("UDPSOCKET_ECHOTEST_NONBLOCK", UDPSOCKET_ECHOTEST_NONBLOCK), Case("UDPSOCKET_OPEN_CLOSE_REPEAT", UDPSOCKET_OPEN_CLOSE_REPEAT), Case("UDPSOCKET_OPEN_LIMIT", UDPSOCKET_OPEN_LIMIT), Case("UDPSOCKET_RECV_TIMEOUT", UDPSOCKET_RECV_TIMEOUT), @@ -119,10 +128,11 @@ Case cases[] = { Case("UDPSOCKET_BIND_WRONG_TYPE", UDPSOCKET_BIND_WRONG_TYPE), Case("UDPSOCKET_BIND_UNOPENED", UDPSOCKET_BIND_UNOPENED), Case("UDPSOCKET_SENDTO_INVALID", UDPSOCKET_SENDTO_INVALID), - Case("UDPSOCKET_ECHOTEST", UDPSOCKET_ECHOTEST), - Case("UDPSOCKET_ECHOTEST_BURST", UDPSOCKET_ECHOTEST_BURST), + Case("UDPSOCKET_ECHOTEST_NONBLOCK", UDPSOCKET_ECHOTEST_NONBLOCK), Case("UDPSOCKET_ECHOTEST_BURST_NONBLOCK", UDPSOCKET_ECHOTEST_BURST_NONBLOCK), Case("UDPSOCKET_SENDTO_REPEAT", UDPSOCKET_SENDTO_REPEAT), + Case("UDPSOCKET_ECHOTEST", UDPSOCKET_ECHOTEST), + Case("UDPSOCKET_ECHOTEST_BURST", UDPSOCKET_ECHOTEST_BURST), }; Specification specification(greentea_setup, cases, greentea_teardown, greentea_continue_handlers); diff --git a/TESTS/netsocket/udp/udp_tests.h b/TESTS/netsocket/udp/udp_tests.h index 34a06670a3..a6222a786d 100644 --- a/TESTS/netsocket/udp/udp_tests.h +++ b/TESTS/netsocket/udp/udp_tests.h @@ -28,6 +28,15 @@ extern mbed_stats_socket_t udp_stats[MBED_CONF_NSAPI_SOCKET_STATS_MAX_COUNT]; int fetch_stats(void); #endif +/** + * Single testcase might take only half of the remaining execution time + */ +int split2half_rmng_udp_test_time(); // [s] + +namespace udp_global { +static const int TESTS_TIMEOUT = 480; +} + /* * Test cases */ diff --git a/TESTS/netsocket/udp/udpsocket_echotest.cpp b/TESTS/netsocket/udp/udpsocket_echotest.cpp index eb9c0c15e3..1457096fce 100644 --- a/TESTS/netsocket/udp/udpsocket_echotest.cpp +++ b/TESTS/netsocket/udp/udpsocket_echotest.cpp @@ -45,6 +45,8 @@ static const int pkt_sizes[PKTS] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, \ 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, \ 1100, 1200 }; +Timer tc_exec_time; +int time_allotted; } static void _sigio_handler(osThreadId id) @@ -106,6 +108,9 @@ void udpsocket_echotest_nonblock_receiver(void *receive_bytes) for (int retry_cnt = 0; retry_cnt <= RETRIES; retry_cnt++) { recvd = sock.recvfrom(NULL, rx_buffer, expt2recv); if (recvd == NSAPI_ERROR_WOULD_BLOCK) { + if (tc_exec_time.read() >= time_allotted) { + break; + } wait_ms(WAIT2RECV_TIMEOUT); --retry_cnt; continue; @@ -132,6 +137,8 @@ void UDPSOCKET_ECHOTEST_NONBLOCK() TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); } #endif + tc_exec_time.start(); + time_allotted = split2half_rmng_udp_test_time(); // [s] SocketAddress udp_addr; NetworkInterface::get_default_instance()->gethostbyname(MBED_CONF_APP_ECHO_SERVER_ADDR, &udp_addr); @@ -166,7 +173,8 @@ void UDPSOCKET_ECHOTEST_NONBLOCK() packets_sent++; } if (sent == NSAPI_ERROR_WOULD_BLOCK) { - if (osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) { + if (tc_exec_time.read() >= time_allotted || + osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) { continue; } --retry_cnt; @@ -209,4 +217,5 @@ void UDPSOCKET_ECHOTEST_NONBLOCK() #endif } TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close()); + tc_exec_time.stop(); } From b705934b6225c1c7901e42aa12281ef3135f820a Mon Sep 17 00:00:00 2001 From: Oren Cohen Date: Tue, 12 Feb 2019 11:22:15 +0200 Subject: [PATCH 031/109] Add MBEDTLS_ENTROPY_NV_SEED to NUCLEO_F411RE to fix the build --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 8d99432812..3e7450ffd5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2435,7 +2435,7 @@ "macro_name": "CLOCK_SOURCE_USB" } }, - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "MBEDTLS_PSA_CRYPTO_C"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "MBEDTLS_PSA_CRYPTO_C", "MBEDTLS_ENTROPY_NV_SEED"], "device_has_add": [ "SERIAL_ASYNCH", "FLASH", From 3204ce5f9f98f03091b25fe42b2a954f889357c0 Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Mon, 11 Feb 2019 20:02:57 -0600 Subject: [PATCH 032/109] Prefixed string to properly be parsed as bytes --- tools/targets/__init__.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index b083f74dd7..567c6380cc 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -427,7 +427,7 @@ class LPC4088Code(object): # Pad the fist part (internal flash) with 0xFF to 512k data = partf.read() outbin.write(data) - outbin.write('\xFF' * (512*1024 - len(data))) + outbin.write(b'\xFF' * (512*1024 - len(data))) partf.close() # Read and append the second part (external flash) in chunks of fixed # size @@ -470,7 +470,7 @@ class MTSCode(object): part = open(loader, 'rb') data = part.read() outbin.write(data) - outbin.write('\xFF' * (64*1024 - len(data))) + outbin.write(b'\xFF' * (64*1024 - len(data))) part.close() part = open(binf, 'rb') data = part.read() From b63f255af8de9b7da72bb1d2a74310a7e18915b4 Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Mon, 11 Feb 2019 20:03:53 -0600 Subject: [PATCH 033/109] Removed decode since deeper tools always return strings --- tools/toolchains/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index 6595538f8d..cc1b6e21a9 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -571,7 +571,7 @@ class mbedToolchain: def compile_output(self, output=[]): _rc = output[0] - _stderr = output[1].decode("utf-8") + _stderr = output[1] command = output[2] # Parse output for Warnings and Errors From 64b263cedb53ee17f289d9a1c84648961bdbca32 Mon Sep 17 00:00:00 2001 From: Leszek Rusinowicz Date: Tue, 12 Feb 2019 12:20:01 +0100 Subject: [PATCH 034/109] FUTURE_SEQUANA: Fixed Arduino signal mappings Fixed Arduino signal mappings for production version of Sequana board. --- .../TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA/PinNames.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA/PinNames.h index 10a8f6dd41..a3b6d064d8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA/PinNames.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA/PinNames.h @@ -187,7 +187,7 @@ typedef enum { D2 = P10_6, D3 = P12_6, D4 = P12_7, - D5 = P6_2, + D5 = P5_5, D6 = P6_3, D7 = P7_2, D8 = P7_1, From c632480a25b001c79120889a12d06094050d5d91 Mon Sep 17 00:00:00 2001 From: Cai Date: Mon, 7 Jan 2019 20:26:00 +0800 Subject: [PATCH 035/109] Add WIFI support for RDA target UNO_91H --- TESTS/network/emac/main.cpp | 3 +- .../TARGET_RDA_EMAC/RdaWiFiInterface.cpp | 217 +++ .../TARGET_RDA_EMAC/RdaWiFiInterface.h | 137 ++ .../TARGET_RDA/TARGET_UNO_91H/inc/csl_mbed.h | 152 ++ .../TARGET_UNO_91H/inc/maclib_task.h | 69 + .../TARGET_UNO_91H/inc/rda5981_flash.h | 105 ++ .../TARGET_UNO_91H/inc/rda5981_ota.h | 57 + .../TARGET_UNO_91H/inc/rda5981_sniffer.h | 99 ++ .../TARGET_UNO_91H/inc/rda5991h_wland.h | 658 ++++++++ .../TARGET_UNO_91H/inc/rda_sys_wrapper.h | 216 +++ .../TARGET_RDA/TARGET_UNO_91H/inc/wland_dbg.h | 60 + .../TARGET_UNO_91H/inc/wland_flash.h | 311 ++++ .../TARGET_UNO_91H/inc/wland_flash_wp.h | 32 + .../TARGET_RDA/TARGET_UNO_91H/inc/wland_ota.h | 39 + .../TARGET_RDA/TARGET_UNO_91H/inc/wland_rf.h | 41 + .../TARGET_UNO_91H/inc/wland_types.h | 86 + .../LICENSE-permissive-binary-license-1.0.txt | 49 + .../TARGET_RDA/TARGET_UNO_91H/lib/README.md | 7 + .../lib/TOOLCHAIN_ARM_STD/libwifi_sta_ap.ar | Bin 0 -> 2534620 bytes .../lib/TOOLCHAIN_GCC_ARM/libwifi_sta_ap.a | Bin 0 -> 1179022 bytes .../lib/TOOLCHAIN_IAR/libwifi_sta_ap.a | Bin 0 -> 2519912 bytes .../TARGET_UNO_91H/src/maclib_task.c | 275 +++ .../TARGET_UNO_91H/src/rda5991h_wland.c | 509 ++++++ .../TARGET_UNO_91H/src/rda_sys_wrapper.c | 450 +++++ .../TARGET_UNO_91H/src/wland_flash.c | 1481 +++++++++++++++++ .../TARGET_UNO_91H/src/wland_flash_wp.c | 366 ++++ .../TARGET_RDA/TARGET_UNO_91H/src/wland_ota.c | 145 ++ .../TARGET_RDA_EMAC/rda5981x_emac.cpp | 293 ++++ .../TARGET_RDA_EMAC/rda5981x_emac.h | 161 ++ .../TARGET_RDA_EMAC/rda5981x_emac_config.h | 22 + .../TARGET_UNO_91H/device/RDA5991H.h | 32 +- targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c | 10 + targets/targets.json | 8 +- 33 files changed, 6066 insertions(+), 24 deletions(-) create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/RdaWiFiInterface.cpp create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/RdaWiFiInterface.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/csl_mbed.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/maclib_task.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5981_flash.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5981_ota.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5981_sniffer.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5991h_wland.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda_sys_wrapper.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_dbg.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_flash.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_flash_wp.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_ota.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_rf.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_types.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/LICENSE-permissive-binary-license-1.0.txt create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/README.md create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_ARM_STD/libwifi_sta_ap.ar create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_GCC_ARM/libwifi_sta_ap.a create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_IAR/libwifi_sta_ap.a create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/maclib_task.c create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda5991h_wland.c create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda_sys_wrapper.c create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash.c create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash_wp.c create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_ota.c create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.cpp create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.h create mode 100644 features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac_config.h diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp index 49ee3cf909..8da3492421 100644 --- a/TESTS/network/emac/main.cpp +++ b/TESTS/network/emac/main.cpp @@ -35,7 +35,8 @@ !defined(TARGET_MTB_ADV_WISE_1530) && \ !defined(TARGET_MTB_USI_WM_BN_BM_22) && \ !defined(TARGET_MTB_MXCHIP_EMW3166) && \ - !defined(TARGET_MTB_UBLOX_ODIN_W2) + !defined(TARGET_MTB_UBLOX_ODIN_W2) && \ + !defined(TARGET_UNO_91H) #error [NOT_SUPPORTED] Wifi tests are not valid for the target #endif #endif diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/RdaWiFiInterface.cpp b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/RdaWiFiInterface.cpp new file mode 100644 index 0000000000..0df8bb6fee --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/RdaWiFiInterface.cpp @@ -0,0 +1,217 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "WiFiInterface.h" +#include "RdaWiFiInterface.h" +#include "rda5991h_wland.h" +#include "nsapi_types.h" +#include "wland_types.h" +#include "rda_sys_wrapper.h" + +nsapi_error_t RDAWiFiInterface::set_channel(uint8_t channel) +{ + int ret= 0; + init(); + + if (channel > 13) + return NSAPI_ERROR_PARAMETER; + + if (channel == 0) { + _channel = 0; + return NSAPI_ERROR_OK; + } + + ret = rda5981_set_channel(channel); + if (ret == 0) { + _channel = channel; + return NSAPI_ERROR_OK; + } else { + return NSAPI_ERROR_TIMEOUT; + } +} + +int8_t RDAWiFiInterface::get_rssi() +{ + return rda5981_get_rssi(); +} + +nsapi_error_t RDAWiFiInterface::init() +{ + if (!_interface) { + if (!_emac.power_up()) { + LWIP_DEBUGF(NETIF_DEBUG,"power up failed!\n"); + } + nsapi_error_t err = _stack.add_ethernet_interface(_emac, true, &_interface); + if (err != NSAPI_ERROR_OK) { + _interface = NULL; + return err; + } + _interface->attach(_connection_status_cb); + } + return NSAPI_ERROR_OK; +} + +nsapi_error_t RDAWiFiInterface::set_credentials(const char *ssid, const char *pass, + nsapi_security_t security) +{ + if (ssid == 0 || strlen(ssid) == 0) { + return NSAPI_ERROR_PARAMETER; + } + if (security != NSAPI_SECURITY_NONE && (pass == 0 || strlen(pass) == 0)) { + return NSAPI_ERROR_PARAMETER; + } + if (strlen(ssid) > 32 || strlen(pass) > 63) { + return NSAPI_ERROR_PARAMETER; + } + memcpy((void*)_ssid, (void*)ssid, strlen(ssid)); + _ssid[strlen(ssid)] = '\0'; + memcpy((void*)_pass, (void*)pass, strlen(pass)); + _pass[strlen(pass)] = '\0'; + _security = security; + return NSAPI_ERROR_OK; +} + +nsapi_error_t RDAWiFiInterface::connect(const char *ssid, const char *pass, + nsapi_security_t security, uint8_t channel) +{ + rda_msg msg; + bool find = false; + int i = 0; + rda5981_scan_result bss; + int ret = 0; + + if (ssid == NULL || ssid[0] == 0) { + return NSAPI_ERROR_PARAMETER; + } + + init(); + + if(rda5981_check_scan_result_name(ssid) != 0) { + for (i = 0; i< 5; i++) { + rda5981_scan(NULL, 0, 0); + if(rda5981_check_scan_result_name(ssid) == 0) { + find = true; + break; + } + } + } else { + find = true; + } + + if (find == false) { + LWIP_DEBUGF(NETIF_DEBUG,"can not find the ap.\r\n"); + return NSAPI_ERROR_CONNECTION_TIMEOUT; + } + bss.channel = 15; + rda5981_get_scan_result_name(&bss, ssid); + if ((channel !=0) && (bss.channel != channel)) { + LWIP_DEBUGF(NETIF_DEBUG, "invalid channel\r\n"); + return NSAPI_ERROR_CONNECTION_TIMEOUT; + } + + memcpy(gssid, ssid, strlen(ssid)); + if (pass[0] != 0) { + memcpy(gpass, pass, strlen(pass)); + } + memset(gbssid, 0, NSAPI_MAC_BYTES); + gssid[strlen(ssid)] = gpass[strlen(pass)] = '\0'; + + msg.type = WLAND_CONNECT; + rda_mail_put(wland_msgQ, (void*)&msg, osWaitForever); + ret = rda_sem_wait(wifi_auth_sem, 10000); + if (ret) { + return NSAPI_ERROR_CONNECTION_TIMEOUT; + } + + ret = _interface->bringup(_dhcp, + _ip_address[0] ? _ip_address : 0, + _netmask[0] ? _netmask : 0, + _gateway[0] ? _gateway : 0, + DEFAULT_STACK, + _blocking); + + return ret; +} + + +nsapi_error_t RDAWiFiInterface::connect() +{ + return connect(_ssid, _pass, _security, _channel); +} + +nsapi_error_t RDAWiFiInterface::disconnect() +{ + rda_msg msg; + + if(sta_state < 2) { + return NSAPI_ERROR_NO_CONNECTION; + } + msg.type = WLAND_DISCONNECT; + rda_mail_put(wland_msgQ, (void*)&msg, osWaitForever); + if (_interface) { + return _interface->bringdown(); + } + + return NSAPI_ERROR_NO_CONNECTION; +} + +nsapi_size_or_error_t RDAWiFiInterface::scan(WiFiAccessPoint *res, nsapi_size_t count) +{ + int bss_num = 0, i; + rda5981_scan_result *bss; + nsapi_wifi_ap_t ap; + + init(); + + rda5981_scan(NULL, 0, 0); + bss_num = rda5981_get_scan_num(); + if (count != 0) { + bss_num = (bss_num < count) ? bss_num : count; + } + if (res) { + bss = (rda5981_scan_result *)malloc(bss_num * sizeof(rda5981_scan_result)); + rda5981_get_scan_result(bss, bss_num); + for (i=0; i +#ifdef __cplusplus +extern "C" { +#endif + +extern const unsigned int RDA_FW_INFO_ADDR; +extern const unsigned int RDA_UPGRADE_ADDR; + +/* + * function: start to wirte a partition. this func will erase given flash region + * @addr: partition start address, must be 4k alignment + * @img_len: length of image getted from OTA server, must be 4k alignment + * return: 0:success, else:fail + */ +int rda5981_write_partition_start(unsigned int addr, unsigned int img_len); + +/* + * function: write image to flash, without erase. + * the write region must be inside of the area given by func rda5981_write_partition_start + * the write region must be in order, otherwise the end function will return crc error. + * the maximum length could be write once time is 0x1000 + * @offset: offset from image inital position, must be 1k alignment + * @buf: data to be written + * @len: buffer len, max #0x1000, must be 1k alignment + * return: 0:success, else:fail + */ +int rda5981_write_partition(unsigned int offset, const unsigned char *buf, unsigned int len); + +/* + * function: end of writing partition + * return: 0:crc32 check success, else:fail + */ +int rda5981_write_partition_end(void); + +#ifdef __cplusplus +} +#endif + +#endif /*_RDA5981_OTA_H_*/ diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5981_sniffer.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5981_sniffer.h new file mode 100644 index 0000000000..0f0f4658e3 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5981_sniffer.h @@ -0,0 +1,99 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RDA5981_SNIFFER_H_ +#define _RDA5981_SNIFFER_H_ + +#ifdef __cplusplus +extern "C" { +#endif +#include "wland_types.h" + +/* Enable filtering ACK frames (no support)*/ +//#define RDA_RX_FILTER_DROP_ACK BIT0 + +/* Enable filtering CTS frames (no support)*/ +//#define RDA_RX_FILTER_DROP_CTS BIT1 + +/* Enable filtering RTS frames (no support)*/ +//#define RDA_RX_FILTER_DROP_RTS BIT2 + +/* Enable filtering beacon frames */ +#define RDA_RX_FILTER_DROP_BEACON BIT3 + +/* Enable filtering ATIM frames (no support)*/ +//#define RDA_RX_FILTER_DROP_ATIM BIT4 + +/* Enable filtering CF_END frames (no support)*/ +//#define RDA_RX_FILTER_DROP_CF_END BIT5 + +/* Enable filtering QCF_POLL frames (no support)*/ +//#define RDA_RX_FILTER_DROP_QCF_POLL BIT6 + +/* Filter Management frames which are not directed to current STA */ +#define RDA_RX_FILTER_DROP_ND_MGMT BIT7 + +/* Filter BC/MC MGMT frames belonging to other BSS */ +#define RDA_RX_FILTER_DROP_BC_MC_MGMT_OTHER_BSS BIT8 + +/* Enable filtering of duplicate frames */ +#define RDA_RX_FILTER_DROP_DUPLICATE BIT9 + +/* Enable filtering of frames whose FCS has failed */ +#define RDA_RX_FILTER_DROP_FCS_FAILED BIT10 + +/* Enable filtering of De-authentication frame */ +#define RDA_RX_FILTER_DROP_DEAUTH BIT11 + +/* Filter BA frames which are not received as SIFS response (no support)*/ +//#define RDA_RX_FILTER_DROP_NSIFS_RESP_BA BIT12 + +/* Filter BA frames which are received as SIFS response (no support)*/ +//#define RDA_RX_FILTER_DROP_SIFS_RESP_BA BIT13 + +/* Filter frames which are received in secondary channel (20 MHz PPDU from Secondary channel) */ +#define RDA_RX_FILTER_DROP_SEC_CHANNEL BIT14 + +/* Filter BC/MC DATA frames belonging to other BSS */ +#define RDA_RX_FILTER_DROP_BC_MC_DATA_OTHER_BSS BIT15 + +/* Filter DATA frames not directed to this station */ +#define RDA_RX_FILTER_DROP_ND_DATA BIT16 + +/* Filter Control frames which are not directed to current STA (no support)*/ +//#define RDA_RX_FILTER_DROP_ND_CONTROL BIT17 + +/* Filter Beacon frames (in IBSS mode) which are not used for adoption because the timestamp field is lower than TSF timer */ +#define RDA_RX_FILTER_DROP_IBSS_BEACON BIT18 + +typedef int (*sniffer_handler_t)(unsigned short data_len, void *data); + +int rda5981_enable_sniffer(sniffer_handler_t handler); +int rda5981_disable_sniffer(void); +//don't use this in sniffer callback handler +int rda5981_disable_sniffer_nocallback(void); +///TODO: time is no use anymore +int rda5981_start_sniffer(unsigned char channel, unsigned char to_ds, + unsigned char from_ds, unsigned char mgm_frame, unsigned short time); +int rda5981_stop_sniffer(void); +int wland_sniffer_set_channel(unsigned char channel); +int rda5981_set_filter(unsigned char to_ds, unsigned char from_ds, unsigned int mgm_filter); +int rda5981_sniffer_enable_fcs(void);//for hiflying +#ifdef __cplusplus +} +#endif + +#endif /*_RDA5981_SNIFFER_H_*/ diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5991h_wland.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5991h_wland.h new file mode 100644 index 0000000000..25ec00acbc --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda5991h_wland.h @@ -0,0 +1,658 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RDA5991H_WLAND_H_ +#define _RDA5991H_WLAND_H_ + +#include "sys_arch.h" +#include "wland_types.h" + +/* Mbed interface mac address + * if MBED_MAC_ADD_x are zero, interface uid sets mac address, + * otherwise MAC_ADD_x are used. + */ + +extern unsigned char user_mac[6];//not save in flash, need fill before wifi init every time +extern unsigned char gssid[32+1]; +extern unsigned char gpass[64+1]; +extern unsigned char gchannel; +extern unsigned char gbssid[6]; + +extern unsigned char gssid_ap[32+1]; +extern unsigned char gpass_ap[64+1]; +extern unsigned char gchannel_ap; +extern void *wland_msgQ; +extern void *wifi_auth_sem; + +extern u8 sta_state; + +typedef enum { + WLAND_CONNECT, + WLAND_RECONNECT, + WLAND_DISCONNECT, + WLAND_DISCONNECT_ERROR, + WLAND_STARTAP, + WLAND_STOPAP, + WLAND_ADD_AP_GTK, + WLAND_AP_EAPOL_3_OF_4, + WLAND_ADD_AP_PTK, + WLAND_STAJOINED, + WLAND_STAEXITED, + WLAND_STADEAUTH, + WLAND_MAC_CONNECTED, + WLAND_MAC_AP_CONNECTED, + WLAND_ADD_GTK, + WLAND_ADD_PTK, + WLAND_CON_FINISH, + WLAND_AUTO_RATE, + WLAND_ARP_OFFLOAD, + WLAND_SM_START, + WLAND_SM_STOP, + WLAND_WPS_CONNECT, + WLAND_WPS_START, + WLAND_WPS_DISCONNECT, +}WLAND_MSG; + +typedef enum { + MAIN_CONNECT, + MAIN_RECONNECT, + MAIN_DISCONNECT, + MAIN_STOP_AP, +}MAIN_MSG; + +typedef struct { + unsigned int type; + unsigned int arg1; + unsigned int arg2; + unsigned int arg3; +}rda_msg; + + +enum { + D_NONE_LEVEL = 0, + D_ERROR_LEVEL = 1, + D_INFO_LEVEL = 2, + D_DEBUG_LEVEL = 3, +}; + +#define WLAND_DBG_DUMP 0 +#define WPA_DBG_DUMP 0 +#define HUT_DBG_DUMP 0 +#define WLAND_DBG_LEVEL D_NONE_LEVEL +#define WPA_DBG_LEBEL D_NONE_LEVEL +#define WLANDLIB_DBG_LEVEL D_NONE_LEVEL + +#define ETH_ALEN 6 + +//encrypt type +#define ENCRYPT_NONE (0) +#define ENCRYPT_WPA_TKIP BIT0 +#define ENCRYPT_WPA_CCMP BIT1 +#define ENCRYPT_WPA2_TKIP BIT2 +#define ENCRYPT_WPA2_CCMP BIT3 +#define ENCRYPT_WEP BIT4 + +/* r91h driver data structure */ +typedef struct { + struct netif *netif_sta; + struct netif *netif_ap; + sys_thread_t wland_thread; + sys_thread_t maclib_thread; + sys_mbox_t maclib_mbox; + sys_mbox_t wland_mbox; +} rda_enetdata_t; + +__STATIC_INLINE int mac_is_valid(char* mac) +{ + return (mac[0] | mac[1] | mac[2] | mac[3] | mac[4] | mac[5]); +} + + +#ifdef __cplusplus +extern "C" { +#endif + +extern void wland_txip_data(void *data, unsigned int len, int mode); +extern void *wland_get_databuf(void); +extern void wland_sta_init(void); +extern void wland_reg_func(void); +extern void r91h_phy_task(void *data); +extern void wland_task(void *arg); +extern void rda_get_macaddr(u8_t *macaddr, int mode); +extern void rda5981_send_rawdata(char* data, unsigned int len); +extern int rda5981_send_nulldata(int power_save); +extern void rda5981_set_country_code(unsigned char country_code);// 0~china(1-14) 1~NA(1-11) 2~EU(1-13) +extern int rda5981_set_retrans_policy(unsigned char count); +extern int rda5981_set_channel(unsigned char channel); +/* default is 0, receive multicast packet, disable please set 1*/ +extern int rda5981_filter_multicast(unsigned char enable); +/* default is 0, 0 ~ no hidden, 1 ~ hidden zero len, 2 ~ hidden zero contents */ +extern void rda5981_set_AP_hidden_type(unsigned char mode); +extern void rda5981_set_AP_link_num(unsigned char num); +extern char* rda5981_get_ver(void); +extern int rda5981_enter_CE_MODE(unsigned char enable); +/* + * mode 0 - not 11n 1 - 11n + * + * -----------------11n(mode 1)(Mbps)----------------- + * rate HT20 HT40 + * GI(800ns) GI(400ns) GI(800ns) GI(400ns) + * 0 6.5 7.2 13.5 15 + * 1 13 14.2 27 30 + * 2 19.5 21.7 40.5 45 + * 3 26 28.9 54 60 + * 4 39 43.3 81 90 + * 5 52 57.8 108 120 + * 6 58.5 65 121.5 135 + * 7 65 72 135 150 + * + * --------------not 11n(mode 0)(Mbps)----------------- + * rate data rate rate data rate + * 0 autorate 9 9 + * 1 1 12 12 + * 2 2 18 18 + * 5 5.5 24 24 + * 11 11 36 36 + * 6 6 48 48 + * + */ +extern int rda5981_set_data_rate(unsigned char mode, unsigned char rate); +extern void rda5981_set_mode(unsigned char bgn_enable); +extern void rda5981_set_auth_timeout(unsigned char timeout_enable); +typedef struct { + char BSSID[ETH_ALEN]; + char SSID[32+1]; + signed char RSSI; + unsigned char SSID_len; + unsigned char channel; + unsigned char secure_type;//refer #define ENCRYPT_XXX + unsigned char wmm; + unsigned char *ie;//user program couldn't free(ie); + unsigned short capability; + unsigned int ie_length; +} rda5981_scan_result; + +typedef struct { + unsigned char mac[ETH_ALEN]; + unsigned int ip; +} rda5981_apsta_info; + +//scan one or all channel(if channel is 0) once +int rda5981_scan(const char *SSID, const unsigned char SSID_len, const unsigned char channel); +//0 passive mode, 1 active mode, scan time(unit is second) +int rda5981_scan_v2(const char *SSID, const unsigned char SSID_len, const unsigned char channel, const unsigned char mode, \ + const unsigned char scan_time); +int rda5981_get_scan_num(); +int rda5981_get_scan_result(rda5981_scan_result *buf, const unsigned char len); +int rda5981_get_scan_result_index(rda5981_scan_result *buf, const unsigned char index); +int rda5981_get_scan_result_name(rda5981_scan_result *buf, const char *name); +int rda5981_get_scan_result_bssid(rda5981_scan_result *buf, const unsigned char *bssid); +int rda5981_check_scan_result_name(const char *name); +int rda5981_check_scan_result(const char *ssid, const char *bssid, const unsigned channel); +int rda5981_check_scan_result_name_bssid(const unsigned char *name, const unsigned char *bssid); +int rda5981_del_scan_all_result(void); +void rda5981_set_expired_time(unsigned int expired_time); +int rda5981_get_joined_AP(rda5981_scan_result *bss); +s8 rda5981_get_rssi(); +void rda5981_set_main_queue(void* queue); + +void rda5981_set_sta_listen_interval(unsigned char interval); +void rda5981_set_sta_link_loss_time(unsigned char time); +unsigned int rda5981_get_ap_join_info(rda5981_apsta_info *buf, const unsigned char len); +void rda5981_set_AP_white_list(unsigned char flag, unsigned char *mac); +int wland_set_joined_sta_ip(char *mac, unsigned int ip); + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_mac_addr(unsigned char *mac_addr); +int rda5981_flash_write_mac_addr(unsigned char *mac_addr); + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_erase_uart(void); +int rda5981_flash_read_uart(unsigned int *uart); +int rda5981_flash_write_uart(unsigned int *uart); + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_ip_addr(unsigned char *ip_addr, unsigned char *server_addr); +int rda5981_flash_write_ip_addr(unsigned char *ip_add, unsigned char *server_addr); + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_erase_dhcp_data(void); +int rda5981_flash_read_dhcp_data(unsigned int *enable, unsigned int *ip, unsigned int *msk, unsigned int *gw); +int rda5981_flash_write_dhcp_data(unsigned int enable, unsigned int ip, unsigned int msk, unsigned int gw); + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_ap_data(char *ssid, char *passwd, unsigned char *channel); +int rda5981_flash_write_ap_data(const char *ssid, const char *passwd, unsigned char channel); +int rda5981_flash_erase_ap_data(void); + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_ap_net_data(unsigned int *ip, unsigned int *msk, unsigned int *gw, + unsigned int *dhcps, unsigned int *dhcpe); +int rda5981_flash_write_ap_net_data(unsigned int ip, unsigned int msk, unsigned int gw, + unsigned int dhcps, unsigned int dhcpe); +int rda5981_flash_erase_ap_net_data(void); + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_sta_data(char *ssid, char *passwd); +int rda5981_flash_write_sta_data(const char *ssid, const char *passwd); +int rda5981_flash_erase_sta_data(void); + + +/* + * read 3rd parter data length from flash + * return user data length + */ +int rda5981_flash_read_3rdparter_data_length(void); + +/* + * read 3rd parter data from flash + * @buf, buf to store user data + * @buf_len, length of buf + * return user data length + */ +int rda5981_flash_read_3rdparter_data(unsigned char *buf, unsigned int buf_len); + +/* + * write 3rd parter data from flash + * @buf, data to write + * @buf_len, length of buf. + * return 0:ok, else:fail + */ +int rda5981_flash_write_3rdparter_data(const unsigned char *buf, unsigned int buf_len); + +/* + * erase 3rd parter data from flash + * return 0:ok, else:fail + */ +int rda5981_flash_erase_3rdparter_data(void); + +/* + * set flash size + * @size, 1MB:0x100000, 2MB:0x200000, 4MB:0x400000. default size: 1MB + * return 0:ok, else:fail + */ +int rda5981_set_flash_size(const unsigned int size); + +/* + * set userdata location on flash + * @sys_data_addr, data to save system parameter, user can not operate this area directly. + * size:4KB. default location:0x180fb000 + * @user_data_addr, data to save user data. user can save own data in this area + * by @rda5981_flash_read_3rdparter_data + * and @rda5981_flash_write_3rdparter_data + * default location:0x180fc000 + * @user_data_len, user data length, default:4KB + * return 0:ok, else:fail + */ +int rda5981_set_user_data_addr(const unsigned int sys_data_addr, + const unsigned int user_data_addr, const unsigned int user_data_len); + +/* + * function: erase flash + * @addr: mast be 4k alignment + * @len: must be 4k alignment. (package 64KB erase and 4KB erase for different condition automatically) + * return: 0:success, else:fail + */ +int rda5981_erase_flash(unsigned int addr, unsigned int len); + +/* + * function: write flash + * @addr: mast be 256 alignment + * @buf: data to be written, best be 4 alignment + * @len: buffer len, mast be 4 alignment + * return: 0:success, else:fail + */ +int rda5981_write_flash(unsigned int addr, char *buf, unsigned int len); + +/* + * function: read flash to @buf + * @addr: best be 4 alignment + * @buf: best be 4 alignment + * @len: buffer len + * return: 0:success, else:fail + */ +int rda5981_read_flash(unsigned int addr, char *buf, unsigned int len); + +/* + * function: read user data + * @data: data to read + * @len: length of data in byte + * @flag: user data flag + * return: 0:success, else:fail + */ +int rda5981_read_user_data(unsigned char *data, unsigned short len, unsigned int flag); + +/* + * function: write user data + * @data: data to write + * @len: length of data in byte + * @flag: user data flag + * return: 0:success, else:fail + */ +int rda5981_write_user_data(unsigned char *data, unsigned short len, unsigned int flag); + +/* + * function: erase user data + * @flag: user data flag + * return: 0:success, else:fail + */ +int rda5981_erase_user_data(unsigned int flag); + +/* + * function: update tx power from efuse data, for reg 11F and 120 + * return: 0:success, else:fail + */ +int update_tx_power_from_efuse(void); + +/* + * function: update xtal calibration from efuse data, for reg DA + * return: 0:success, else:fail + */ +int update_xtal_cal_from_efuse(void); + +/* + * function: update mac addr from flash data + * return: 0:success, else:fail + */ +int update_mac_addr_from_efuse(void); + +/* + * function: update tx power from flash data, Deprecated version + * return: 0:success, else:fail + */ +int update_tx_power_from_flash(void); + +/* + * function: update tx power from flash data, for reg 8A + * return: 0:success, else:fail + */ +int update_tx_power_rf_from_flash(void); + +/* + * function: update tx power from flash data, for reg 11F and 120 + * return: 0:success, else:fail + */ +int update_tx_power_phy_from_flash(void); + +/* + * function: update xtal calibration from flash data + * return: 0:success, else:fail + */ +int update_xtal_cal_from_flash(void); + +/* + * function: update mac addr from flash data + * return: 0:success, else:fail + */ +int update_mac_addr_from_flash(void); + +/* + * function: write rf reg + * @reg: rf reg data + * @value: rf reg value + * return: 0:success, else:fail + * eg: 0x00DA:xtal calibration + */ +int wland_rf_write(unsigned short reg, unsigned short value); + +/* + * function: write rf reg + * @reg: rf reg data + * @value: rf reg value + * @len : value length + * return: 0:success, else:fail + * eg: 0x008A:tx power rf + */ +int wland_rf_write_all_channels(unsigned short reg, unsigned short *value, unsigned short len); + +/* + * function: read rf reg + * @reg: rf reg data + * @value: rf reg value + * return: 0:success, else:fail + */ +int wland_rf_read(unsigned short reg, unsigned short *value); + +/* + * function: read rf reg + * @reg: rf reg data + * @value: rf reg value + * return: 0:success, else:fail + * eg: 0x008A:tx power rf + */ +int wland_rf_read_all_channels(unsigned short reg, unsigned short *value); + +/* + * function: write phy reg + * @reg: phy reg data + * @value: phy reg value + * return: 0:success, else:fail + */ +int wland_phy_write(unsigned int reg, unsigned int value); + +/* + * function: write phy reg + * @reg: phy reg data + * @value: phy reg value + * @len : value length + * return: 0:success, else:fail + */ +int wland_phy_write_all_channels(unsigned int reg, unsigned int *value, unsigned short len); + +/* + * function: read phy reg + * @reg: phy reg data + * @value: phy reg value + * return: 0:success, else:fail + */ +int wland_phy_read(unsigned int reg, unsigned int *value); + +/* + * function: read phy reg + * @reg: phy reg data + * @value: phy reg value + * return: 0:success, else:fail + */ +int wland_phy_read_all_channels(unsigned int reg, unsigned int *value); + +/* efuse API start */ +/* Efuse CAN ONLY WRITE ONCE! DO NOT CALL THESE API IF YOU DO KNOW WHAT THEY MEANS!!! */ + +/* + * function: read all efuse + * @value: buffer to store efuse data, 28 bytes + * return: 0:success, else:fail + */ +int wland_read_efuse(unsigned char *value); + +/* + * function: read tx power from efuse + * @tx_power: 2 bytes, first is mode g/n(range 0x25~0x54), second is mode b(range 0x15~0x54). + * return: 0:success, else:fail + */ +int wland_read_tx_power_from_efuse(unsigned char *tx_power); + +/* + * function: read tx power from efuse + * @tx_power: 2 bytes, first is mode g/n(range 0x25~0x54), second is mode b(range 0x15~0x54) + * @len: must be 2 + * return: 0:success, else:fail + */ +int wland_write_tx_power_to_efuse(unsigned char *tx_power, unsigned char len); + +/* + * function: read xtal cal from efuse + * @xtal_cal: 1 byte, maximum 0x7F + * return: 0:success, else:fail + */ +int wland_read_xtal_cal_from_efuse(unsigned char *cal_val); + +/* + * function: write xtal cal to efuse + * @xtal_cal: 1 byte, maximum 0x7F + * @len : must be 1 + * return: 0:success, else:fail + */ +int wland_write_xtal_cal_to_efuse(unsigned char *xtal_cal, unsigned char len); + +/* + * function: write mac to efuse + * @xtal_cal: 6 bytes + * return: 0:success, else:fail + */ +int wland_read_mac_addr_from_efuse(unsigned char *mac_addr); + +/* + * function: write mac to efuse + * @xtal_cal: 6 bytes + * @len : must be 6 + * return: 0:success, else:fail + */ +int wland_write_mac_addr_to_efuse(unsigned char*mac_addr, unsigned char len); +/* efuse API end */ + +/* + * function: start rf test + * @argc: number of argv + * @argv: args for test, 6 elements for tx test, 4 elements for rx test + * @is_tx: 1 for tx test, 0 for rx test + * return: 0:success, else:fail + */ +int wland_start_rf_test(unsigned int argc, unsigned int *argv, unsigned int is_tx); + +/* + * function: stop rx test + * return: 0:success, else:fail + */ +int wland_stop_rx_test(void); + +/* + * function: get rf test result + * @result buffer to store rx result + * return: 0:success, else:fail + */ +int wland_get_rx_result(char *result); + +/* + * function: restart rx test, use last rx test args + * return: 0:success, else:fail + */ +int wland_restart_rx_test(void); + +/* + * function: stop tx test + * return: 0:success, else:fail + */ +int wland_stop_tx_test(void); + +/* + * function: restart tx test, use last tx test args + * return: 0:success, else:fail + */ +int wland_restart_tx_test(void); + +#define RDA5981_FIRMWARE_INFO_ADDR 0x18003000 +/* + * function: reboot to assigned addr (onece). + * reboot to rf test mode, not for OTA + * @firmware_info_addr: firmware info addr, depend on your flash layout + * @reboot_addr: reboot addr, 0x18001000-0x1840000 + * return: 0:success, else:fail + */ +int rda5981_reboot_to_addr(unsigned int firmware_info_addr, unsigned int reboot_addr); + +/* + * function: read reg and corresponding value related to test mode stored in flash + * @reg: reg to read + * @value: buffer to store value + * @flag: user data flag + * return: 0:success, else:fail + */ +int rda5981_read_user_data_regs(unsigned char *reg, unsigned char *value, unsigned int flag); + +/* + * function: write reg and corresponding value related to test mode stored in flash + * @reg: reg to write + * @value: buffer that stores value + * @flag: user data flag + * return: 0:success, else:fail + */ +int rda5981_write_user_data_regs(unsigned char *reg, unsigned char *value, unsigned int flag); + +/* + * function: erase reg and corresponding value related to test mode stored in flash + * @reg: reg to erase + * @flag: user data flag + * return: 0:success, else:fail + */ +int rda5981_erase_user_data_regs(unsigned char *reg, unsigned int flag); + +/* + * function: get flash Manufacturer ID + * @mid: + * return: 0:success, else:fail + */ +int rda5981_flash_get_mid(unsigned char *mid); + +/* + * function: get flash Device ID + * @did: + * return: 0:success, else:fail + */ +int rda5981_flash_get_did(unsigned char *did); + +/* + * function: get flash ID + * @mid: + * return: 0:success, else:fail + */ +int rda5981_flash_get_jdid(unsigned short *jdid); + +/* + * function: read mac reg + * @reg: mac reg data + * @value: mac reg value + * return: 0:success, else:fail + */ +int wland_mac_reg_read(unsigned short reg, unsigned int *value); + +/* + * function: write mac reg + * @reg: mac reg data + * @value: mac reg value + * return: 0:success, else:fail + */ +int wland_mac_reg_write(unsigned short reg, unsigned int value); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda_sys_wrapper.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda_sys_wrapper.h new file mode 100644 index 0000000000..25b80b5199 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/rda_sys_wrapper.h @@ -0,0 +1,216 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if 1 +#ifndef _RDA_SYS_WRAPPER_H_ +#define _RDA_SYS_WRAPPER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Alarm */ +/** + * @brief : get current time in units of micro second + * @param[in] : + * @param[out]: + * @return : return time value with uint32 type + */ +extern unsigned long rda_get_cur_time_ms(void); + +/** + * @brief : create an alarm with given function, return timer handle + * @param[in] : func(callback)/data(pass to func)/mode(once or periodic) + * @param[out]: + * @return : return timer handle, a pointer to the timer structure, non-zero is valid + */ +extern void * rda_alarm_create_v2(void *func, unsigned int data, unsigned int mode); +extern void * rda_alarm_create(void *func, unsigned int data); + +/** + * @brief : delete an alarm with given handle, then reset the handle + * @param[in] : *handle(pointer to the timer structure) + * @param[out]: **handle(address of the handle variable) + * @return : + */ +extern int rda_alarm_delete(void **handle); + +/** + * @brief : start an alarm, raise a function call after given timeout delay + * @param[in] : handle(pointer to the timer structure)/timeout(micro second) + * @param[out]: + * @return : + */ +extern int rda_alarm_start(void *handle, unsigned int timeout_ms); + +/** + * @brief : stop an alarm, will not raise a function call any more + * @param[in] : handle(pointer to the timer structure) + * @param[out]: + * @return : + */ +extern int rda_alarm_stop(void *handle); + + +/* Semaphore */ +/** + * @brief : create a semaphore + * @param[in] : name and initial valve of semaphore + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern void* rda_sem_create(unsigned int count); + +/** + * @brief : wait a semaphore + * @param[in] : name of semaphore + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_sem_wait(void *sem, unsigned int millisec); + +/** + * @brief : release a semaphore + * @param[in] : name of semaphore + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_sem_release(void *sem); + +/** + * @brief : delete a semaphore + * @param[in] : name of semaphore + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_sem_delete(void *sem); + + +/* Queue */ +/** + * @brief : create a message queue + * @param[in] : size of message queue + * @param[out]: + * @return : return message queue id or NULL if error + */ +extern void* rda_msgQ_create(unsigned int queuesz); + +/** + * @brief : put a message to queue + * @param[in] : message queue id, message value and wait time + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_msg_put(void *msgQId, unsigned int msg, unsigned int millisec); + +/** + * @brief : get a message from queue + * @param[in] : message queue id, message value and wait time + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_msg_get(void *msgQId, unsigned int *value, unsigned int millisec); + +/* Mail */ +/** + * @brief : create a mail + * @param[in] : mail count/size + * @param[out]: + * @return : return mail handle + */ +void* rda_mail_create(unsigned int msgcnt, unsigned int msgsize); + +/** + * @brief : get a msg from mail + * @param[in] : handler name of mail/mail/wait time + * @param[out]: + * @return : return ERR or NO_ERR + */ +int rda_mail_get(void *rdahandle, void *evt, unsigned int wait); + +/** + * @brief : put a msg to mail + * @param[in] : handler of mail/mail/wait time + * @param[out]: + * @return : return ERR or NO_ERR + */ + +int rda_mail_put(void *rdahandle, void *evt, unsigned int wait); + +/* Mutex */ +/** + * @brief : create a mutex + * @param[in] : + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern void* rda_mutex_create(void); + +/** + * @brief : wait a mutex + * @param[in] : id of mutex and wait time + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_mutex_wait(void *rdamutex, unsigned int millisec); + +/** + * @brief : release a mutex + * @param[in] : id of mutex + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_mutex_realease(void *rdamutex); + +/** + * @brief : delete a mutex + * @param[in] : id of mutex + * @param[out]: + * @return : return ERR or NO_ERR + */ +extern int rda_mutex_delete(void *rdamutex); + +/* Thread */ +/** + * @brief : creat a thread + * @param[in] : thread name/thread function/thread fuction argument/stacksize/thread priority + * @param[out]: + * @return : return thread id + */ +void* rda_thread_new(const char *pcName, void (*thread)(void *arg), void *arg, int stacksize, int priority); + +/** + * @brief : delete a thread + * @param[in] : thread id + * @param[out]: + * @return : return ERR or NO_ERR + */ +int rda_thread_delete(void* id); + +/** + * @brief : get current thread id + * @param[in] : + * @param[out]: + * @return : return thread id + */ +void* rda_thread_get_id(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _RDA_SYS_WRAPPER_H_ */ +#endif diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_dbg.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_dbg.h new file mode 100644 index 0000000000..ce418c023b --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_dbg.h @@ -0,0 +1,60 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _WLAND_DBG_H_ +#define _WLAND_DBG_H_ +#include +#include "rda5991h_wland.h" +#include "wland_types.h" + +extern int wland_dbg_dump; +extern int wland_dbg_level; + +#define RDA_WLAND_DBG + +#ifdef RDA_WLAND_DBG +#define WLAND_DBG(level, fmt, ...) do {\ + int dbg_level = D_##level##_LEVEL;\ + if((dbg_level <= wland_dbg_level)){\ + printf("%s,"fmt, __func__, ##__VA_ARGS__);\ + } \ + } while (0) + +//if frmae_len is zero, get len from frame header +static inline void wland_dump_frame(const char* msg, u8 *data, u32 frame_len) +{ + + u32 len,i; + + if(wland_dbg_dump == 1) { + if(frame_len != 0) { + len = frame_len; + } else { + len = data[0] | ((data[1]&0x0f) << 8); + } + printf("%s : ",msg); + for(i=0; i= 4) { + wait_busy_down_4(); + } else { + wait_busy_down_2(); + } +} + +static void spi_write_reset(void) +{ + if (rda_ccfg_hwver() >= 4) { + spi_write_reset_4(); + } else { + spi_write_reset_2(); + } +} + +static void spi_wip_reset(void) +{ + if (rda_ccfg_hwver() >= 4) { + spi_wip_reset_4(); + } else { + spi_wip_reset_2(); + } +} + +static inline void spi_flash_enable_cache(void) +{ + unsigned int func = spi_flash_cfg_cache_addr; + if (rda_ccfg_hwver() >= 4) { + func = spi_flash_cfg_cache_addr_4; + } + ((void(*)(void))func)(); +} + +static inline void spi_flash_disable_cache(void) +{ + unsigned int func = spi_flash_disable_cache_addr; + if (rda_ccfg_hwver() >= 4) { + func = spi_flash_disable_cache_addr_4; + } + ((void(*)(void))func)(); +} + +static inline void spi_flash_flush_cache(void) +{ + unsigned int func = spi_flash_flush_cache_addr; + if (rda_ccfg_hwver() >= 4) { + func = spi_flash_flush_cache_addr_4; + } + ((void(*)(void))func)(); +} + +static inline void rda5981_spi_flash_erase_4KB_sector(u32 addr) +{ + unsigned int func = spi_flash_erase_4KB_sector_addr; + if (rda_ccfg_hwver() >= 4) { + func = spi_flash_erase_4KB_sector_addr_4; + } + ((void(*)(u32))func)(addr); +} + +static inline void RDA5991H_ERASE_FLASH(void *addr, u32 len) +{ + unsigned int func = FLASH_ERASE_FUN_ADDR; + if (rda_ccfg_hwver() >= 4) { + func = FLASH_ERASE_FUN_ADDR_4; + } + ((void(*)(void *, u32))func)(addr, len); +} + +static inline void RDA5991H_WRITE_FLASH(u32 addr, u8 *data, u32 len) +{ + unsigned int func = FLASH_WRITE_FUN_ADDR; + if (rda_ccfg_hwver() >= 4) { + func = FLASH_WRITE_FUN_ADDR_4; + } + ((void(*)(u32, u8 *, u32))func)(addr, data, len); +} + +static inline void RDA5991H_READ_FLASH(u32 addr, u8 *buf, u32 len) +{ + unsigned int func = FLASH_READ_FUN_ADDR; + if (rda_ccfg_hwver() >= 4) { + func = FLASH_READ_FUN_ADDR_4; + } + ((void(*)(u32, u8 *, u32))func)(addr, buf, len); +} + +static inline void SPI_FLASH_READ_DATA_FOR_MBED(void *addr, void *buf, u32 len) +{ + unsigned int func = SPI_FLASH_READ_DATA_FOR_MBED_ADDR; + if (rda_ccfg_hwver() >= 4) { + func = SPI_FLASH_READ_DATA_FOR_MBED_ADDR_4; + } + ((void(*)(void *, void *, u32))func)(buf, addr, len); +} + +#endif /*_WLAND_FLASH_H_*/ + diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_flash_wp.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_flash_wp.h new file mode 100644 index 0000000000..40ee40ee59 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_flash_wp.h @@ -0,0 +1,32 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _WLAND_FLASH_WP_H_ +#define _WLAND_FLASH_WP_H_ + +#ifdef __cplusplus +extern "C" { +#endif +extern void flash_wrtie_protect_all(); +extern void flash_wrtie_protect_none(); +extern void flash_wrtie_protect(unsigned int offset); +extern void rda5981_flash_init(); +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_ota.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_ota.h new file mode 100644 index 0000000000..57b9052871 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_ota.h @@ -0,0 +1,39 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _WLAND_OTA_H_ +#define _WLAND_OTA_H_ +#include "wland_types.h" +#include "rda_ccfg_api.h" + +extern u32 flash_size; + +#define CRC32_TABLE_ADDR 0xbb5c +#define CRC32_ADDR 0x8dff//u32 crc32(const u8 *p, size_t len) + +#define CRC32_TABLE_ADDR_4 0xbbd8 +#define CRC32_ADDR_4 0x8e33//u32 crc32(const u8 *p, size_t len) + +static inline unsigned int bootrom_crc32(unsigned char *p, unsigned int len) +{ + unsigned int func = CRC32_ADDR; + if (rda_ccfg_hwver() >= 4) { + func = CRC32_ADDR_4; + } + return ((unsigned int(*)(unsigned char *, unsigned int))func)(p, len); +} + +#endif /*_WLAND_OTA_H_*/ diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_rf.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_rf.h new file mode 100644 index 0000000000..6a9ebebc98 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_rf.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _WLAND_RF_H_ +#define _WLAND_RF_H_ + +#include "wland_types.h" + +#define WLAND_TXP_NUM 2 +#define WLAND_CHANNEL_NUM 14 +#define WLAND_TX_POWER_PHY_GN_REG 0x11F +#define WLAND_TX_POWER_PHY_B_REG 0x120 +#define WLAND_TX_POWER_RF_REG 0x8A +#define WLAND_XTAL_CAL_REG 0xDA + +#define MAKE_WORD16(lsb, msb) (((u16)(msb) << 8) & 0xFF00) | (lsb) +#define MAKE_WORD32(lsw, msw) (((u32)(msw) << 16) & 0xFFFF0000) | (lsw) + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif + diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_types.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_types.h new file mode 100644 index 0000000000..3cb0e7e9e6 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/inc/wland_types.h @@ -0,0 +1,86 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*****************************************************************************/ +/* */ +/* File Name : wland_types.h */ +/* */ +/* Description : This file contains all the data type definitions for */ +/* MAC implementation. */ +/* */ +/*****************************************************************************/ + +#ifndef WLAND_TYPES_H +#define WLAND_TYPES_H + +/*****************************************************************************/ +/* Constants Definitions */ +/*****************************************************************************/ + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned long long u64; +typedef signed char s8; +typedef signed short s16; +typedef signed int s32; +typedef signed long long s64; + +typedef unsigned int size_t; + +/** Indicates Bit Value of BITx */ +#ifndef BIT +#define BIT(x) (1ul << (x)) + +/*****************************************************************************/ +/* Constant Definitions */ +/*****************************************************************************/ + +#define BIT0 (1ul << 0) +#define BIT1 (1ul << 1) +#define BIT2 (1ul << 2) +#define BIT3 (1ul << 3) +#define BIT4 (1ul << 4) +#define BIT5 (1ul << 5) +#define BIT6 (1ul << 6) +#define BIT7 (1ul << 7) +#define BIT8 (1ul << 8) +#define BIT9 (1ul << 9) +#define BIT10 (1ul << 10) +#define BIT11 (1ul << 11) +#define BIT12 (1ul << 12) +#define BIT13 (1ul << 13) +#define BIT14 (1ul << 14) +#define BIT15 (1ul << 15) +#define BIT16 (1ul << 16) +#define BIT17 (1ul << 17) +#define BIT18 (1ul << 18) +#define BIT19 (1ul << 19) +#define BIT20 (1ul << 20) +#define BIT21 (1ul << 21) +#define BIT22 (1ul << 22) +#define BIT23 (1ul << 23) +#define BIT24 (1ul << 24) +#define BIT25 (1ul << 25) +#define BIT26 (1ul << 26) +#define BIT27 (1ul << 27) +#define BIT28 (1ul << 28) +#define BIT29 (1ul << 29) +#define BIT30 (1ul << 30) +#define BIT31 (1ul << 31) +#endif + +#endif /* WLAND_TYPES_H */ diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/LICENSE-permissive-binary-license-1.0.txt b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/LICENSE-permissive-binary-license-1.0.txt new file mode 100644 index 0000000000..24e25298db --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/LICENSE-permissive-binary-license-1.0.txt @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, January 2019 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named “DEPENDENCIES” and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/README.md b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/README.md new file mode 100644 index 0000000000..5df1aa37df --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/README.md @@ -0,0 +1,7 @@ +This directory tree contains binaries build from RDA SDK modified for Mbed OS and released under Permissive Binary License. + +libhal files in the subfolders are generated with toolchains: + +Arm Compiler 5 - version 5.06u6 +GNU Arm Embedded - version 6.3.1 +IAR EWARM - version 8.32.2.178 \ No newline at end of file diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_ARM_STD/libwifi_sta_ap.ar b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_ARM_STD/libwifi_sta_ap.ar new file mode 100644 index 0000000000000000000000000000000000000000..3c5307cd7741140c9fd2ae603bc99d2991e7950c GIT binary patch literal 2534620 zcmeFa4}4rlbuT`<`fK^0>^O-@oUn4_pajR3WZ70sLM>a8rNpv?Bqsp^tCe;oZLB}* z-IXne01kD)fwY9a@TWlA4W(`1h5qc2^rbZUCF!Fjv_Ll`Kxy+{O@F+S5ZY(ADHRXe zyzlqS%-y+HyRx7p{P}r5y1MtAIrHz_GiT1soS9p9O)Nb!{`#8D5&y5z0rj){KN8u} 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0000000000..bd31ff81d2 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/maclib_task.c @@ -0,0 +1,275 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file : maclib_task.c + * @brief : WiFi MACLib task source file + * @version: V1.0 + * @date : 6. May 2017 + * + * @note + * + ******************************************************************************/ +#include +#include +#include + +#include "mbed_interface.h" +#include "cmsis_os.h" +#include "csl_mbed.h" +#include "maclib_task.h" +#include "rda5991h_wland.h" + +#include "lwip/pbuf.h" +#include "lwip/sys.h" + +/** + * Macros + */ +#define MACLIB_TASK_DEBUG (0) + +/** + * Variables + */ +static int maclib_task_run = 0; +static sys_mbox_t maclib_mbox; +static int g_event_num = 0; +static int g_event_proc_done = 1; +static sys_sem_t g_maclib_sem_sleep; +static int g_maclib_sleep_flag = 0; + +extern maclib_func_t *maclib_func_p; + +extern void rda_critical_sec_start(void); +extern void rda_critical_sec_end(void); +extern void wland_set_sta_sleep(unsigned char is_sleep); + +#define MAX_MSG_POOL_NUM (64) +maclib_msg_t msg_str_pool[MAX_MSG_POOL_NUM]; +int msg_str_pool_inited = 0; + +void init_msg_str_pool(void) +{ + int idx; + for(idx = 0; idx < MAX_MSG_POOL_NUM; idx++) { + msg_str_pool[idx].is_free = 1; + } +} + +maclib_msg_t *alloc_msg_str(void) +{ + int idx; + maclib_msg_t *ret = NULL; + rda_critical_sec_start(); + if (0 == msg_str_pool_inited) { + init_msg_str_pool(); + msg_str_pool_inited = 1; + } + rda_critical_sec_end(); + for (idx = 0; idx < MAX_MSG_POOL_NUM; idx++) { + rda_critical_sec_start(); + ret = &msg_str_pool[idx]; + if (1 == ret->is_free) { + ret->is_free = 0; + rda_critical_sec_end(); + break; + } + rda_critical_sec_end(); + } + return ret; +} + +void free_msg_str(maclib_msg_t *p_msg) +{ + rda_critical_sec_start(); + p_msg->is_free = 1; + rda_critical_sec_end(); +} + +/** + * Functions + */ +/* maybe called in isr, should not use "printf", "malloc" */ +void mbed_event_handle_cb(unsigned int event) +{ + MACLIB_EVENT_HANDLE_T type = (MACLIB_EVENT_HANDLE_T)event; + if ((maclib_task_run == 0) && (MACLIB_EVENT_CLEANUP != type)) { + mbed_error_printf("evntHndlCb_nulldata\r\n"); + return; + } + switch(type) { + case MACLIB_EVENT_PEND: + rda_critical_sec_start(); + g_event_num++; + if((1 == g_event_num) && (1 == g_event_proc_done)) { + maclib_msg_t *msg; +#if MACLIB_TASK_DEBUG + mbed_error_printf("#1-1,%d(%08X)\r\n", g_event_num, __get_xPSR()); +#endif + msg = alloc_msg_str(); + if(NULL == msg) { + mbed_error_printf("malloc err\r\n"); + return; + } + msg->type = MACLIB_MSG_EVNT_HNDL; + msg->msg = NULL; + sys_mbox_trypost(&(maclib_mbox), msg); +#if MACLIB_TASK_DEBUG + mbed_error_printf("#1-2\r\n"); +#endif + } + rda_critical_sec_end(); + break; + case MACLIB_EVENT_PROCESS: +#if 1 + rda_critical_sec_start(); + g_event_num--; + if(0 > g_event_num) { + mbed_error_printf("event handle err\r\n"); + g_event_num = 0; + } + rda_critical_sec_end(); +#if MACLIB_TASK_DEBUG + mbed_error_printf("#3,%d\r\n",g_event_num); +#endif +#endif + break; + case MACLIB_EVENT_CLEANUP: +#if MACLIB_TASK_DEBUG + mbed_error_printf("event cleanup\r\n"); +#endif + rda_critical_sec_start(); + g_event_num = 0; + rda_critical_sec_end(); + break; + default: + break; + } +} + +void mbed_mltask_sleep_cb(void) +{ + g_maclib_sleep_flag = 1; + sys_arch_sem_wait(&g_maclib_sem_sleep, 0); +} + +void mbed_mltask_wakeup_cb(void) +{ + rda_critical_sec_start(); + if (1 == g_maclib_sleep_flag) { + g_maclib_sleep_flag = 0; + sys_sem_signal(&g_maclib_sem_sleep); + } + rda_critical_sec_end(); +} + +void maclib_check_status(void) +{ + rda_critical_sec_start(); + if (1 == g_maclib_sleep_flag) { + if(*((unsigned int *)0x40020580U) & (0x01UL << 2)) { + mbed_mltask_wakeup_cb(); + } + } + rda_critical_sec_end(); +} + +int maclib_is_sleep_allowed(void) +{ + return g_maclib_sleep_flag; +} + +void maclib_task(void *pvParameters) +{ + int ret; +#if 0 + sleep_entry_t maclib_sleep_entry = { + wland_set_sta_sleep, + maclib_is_sleep_allowed, + maclib_check_status + }; +#endif + sys_sem_new(&g_maclib_sem_sleep, 0); + //sleep_entry_register(&maclib_sleep_entry); + + ret = sys_mbox_new(&(maclib_mbox), 8); + if(0 != ret) { + LWIP_DEBUGF(NETIF_DEBUG,"msgbox init err!\r\n"); + goto mac_lib_err; + } +#if MACLIB_TASK_DEBUG + LWIP_DEBUGF(NETIF_DEBUG,"#mbox new\r\n"); +#endif + maclib_task_run = 1; + while(1) { + int mem_free = 1; + maclib_msg_t *msg = NULL; + unsigned int time = sys_arch_mbox_fetch(&(maclib_mbox), (void **)&msg, 0); + if ((SYS_ARCH_TIMEOUT == time) || (NULL == msg)) { + LWIP_DEBUGF(NETIF_DEBUG, "ml_task: invalid msg\r\n"); + continue; + } + switch(msg->type) { + case MACLIB_MSG_EVNT_HNDL: { + rda_critical_sec_start(); + g_event_proc_done = 0; + rda_critical_sec_end(); +#if MACLIB_TASK_DEBUG + mbed_error_printf("#get event %d\r\n", g_event_num); +#endif + maclib_func_p->ml_tasklet(); +#if MACLIB_TASK_DEBUG + mbed_error_printf("#5\r\n"); +#endif + rda_critical_sec_start(); +#if 0 + g_event_num--; + if(0 > g_event_num) { + mbed_error_printf("event handle err\r\n"); + } else +#endif + g_event_proc_done = 1; + if(0 < g_event_num) { +#if MACLIB_TASK_DEBUG + mbed_error_printf("#2-1\r\n"); +#endif + sys_mbox_trypost(&(maclib_mbox), msg); +#if MACLIB_TASK_DEBUG + mbed_error_printf("#2-2\r\n"); +#endif + mem_free = 0; + } + rda_critical_sec_end(); +#if MACLIB_TASK_DEBUG + mbed_error_printf("#pDone\r\n"); +#endif + break; + } + default: + break; + } + if (mem_free) { + free_msg_str(msg); +#if MACLIB_TASK_DEBUG + mbed_error_printf("#4\r\n"); +#endif + } + } + +mac_lib_err: + LWIP_DEBUGF(NETIF_DEBUG,"MACLib exit!\r\n"); + osDelay(osWaitForever); +} diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda5991h_wland.c b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda5991h_wland.c new file mode 100644 index 0000000000..4c6febce9d --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda5991h_wland.c @@ -0,0 +1,509 @@ +/* Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file rda5991h_wland.c + * @brief RDA5991H wlan driver for LWIP + * @version: V1.0 + * @date: 25. July 2016 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "lwip/opt.h" +#include "lwip/sys.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/tcpip.h" +#include "netif/etharp.h" +#include "sys_arch.h" +#include "rda5991h_wland.h" +#include "cmsis.h" +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) +#include "entropy_poll.h" +#else +#include "trng_api.h" +#endif +#include "gpio_api.h" +#include "gpio_irq_api.h" +#include "maclib_task.h" +#include "rda_sys_wrapper.h" +#include +#include +#include +#include + +/* Global variables */ +rda_enetdata_t r91h_wifidata; + +int wland_dbg_dump = WLAND_DBG_DUMP; +int wland_dbg_level = WLAND_DBG_LEVEL; +int wpa_dbg_dump = WPA_DBG_DUMP; +int wpa_dbg_level = WPA_DBG_LEBEL; +int wlandlib_dbg_level = WLANDLIB_DBG_LEVEL; +int hut_dbg_dump = HUT_DBG_DUMP; + +//#define CONFIG_DISABLE_ALL_INT +#define CRI_SEC_START_PRI_LEVEL 0xF8 +#define CRI_SEC_END_PRI_LEVEL 0x00 +static unsigned int g_critical_sec_counter = 0U; +#if defined(CONFIG_DISABLE_ALL_INT) +static unsigned int g_critical_ctxt_saved = 0U; +#endif /* CONFIG_DISABLE_ALL_INT */ +void *packet_rx_queue; + +/* Function statements */ +void r91h_wifiif_input(struct netif *netif, u8_t *data, u32_t len, int idx); +void mbed_mac_address(char *mac); + +/** \brief Driver transmit and receive thread priorities + * + * Thread priorities for receive thread and TX cleanup thread. Alter + * to prioritize receive or transmit bandwidth. In a heavily loaded + * system or with LEIP_DEBUG enabled, the priorities might be better + * the same. */ +#define RX_PRIORITY (osPriorityNormal) +#define TX_PRIORITY (osPriorityNormal) +#define PHY_PRIORITY (osPriorityNormal) + +void rda_netif_down(int netif) +{ + if (netif == 0) { + netif_set_down(r91h_wifidata.netif_sta); + } else { + netif_set_down(r91h_wifidata.netif_ap); + } +} + +void rda_netif_link_down(int netif) +{ + rda_msg msg; + msg.type = 1; + msg.arg1 = 0; + rda_mail_put(packet_rx_queue, (void*)&msg, osWaitForever); +} + +void rda_netif_up(int netif) +{ + if (netif == 0) { + netif_set_up(r91h_wifidata.netif_sta); + } else { + netif_set_up(r91h_wifidata.netif_ap); + } +} + +void rda_netif_link_up(int netif) +{ + rda_msg msg; + msg.type = 1; + msg.arg1 = 1; + rda_mail_put(packet_rx_queue, (void*)&msg, osWaitForever); + return; +} + +void rda_netif_input(u8_t *data, u32_t len, int idx, int netif) +{ + if (netif == 0) { + r91h_wifiif_input(r91h_wifidata.netif_sta, data, len, idx++); + } else { + r91h_wifiif_input(r91h_wifidata.netif_ap, data, len, idx++); + } +} + +void rda_get_macaddr(u8_t *macaddr, int mode) +{ + mbed_mac_address((char *)macaddr); + if (mode == 1) { + if(macaddr[0] & 0x04) { + macaddr[0] &= 0xFB; + } else { + macaddr[0] |= 0x04; + } + } + return; +} + +void rda_critical_sec_start(void) +{ + if (__get_IPSR() == 0U) { + if (0U == g_critical_sec_counter) { +#if defined(CONFIG_DISABLE_ALL_INT) + g_critical_ctxt_saved = __disable_irq(); +#else /* CONFIG_DISABLE_ALL_INT */ + __set_BASEPRI(CRI_SEC_START_PRI_LEVEL); +#endif /* CONFIG_DISABLE_ALL_INT */ + } + g_critical_sec_counter++; + } +} + +void rda_critical_sec_end(void) +{ + if (__get_IPSR() == 0U) { + g_critical_sec_counter--; + if (0U == g_critical_sec_counter) { +#if defined(CONFIG_DISABLE_ALL_INT) + __set_PRIMASK(g_critical_ctxt_saved); +#else /* CONFIG_DISABLE_ALL_INT */ + __set_BASEPRI(CRI_SEC_END_PRI_LEVEL); +#endif /* CONFIG_DISABLE_ALL_INT */ + } + } +} + +void * rda_create_interrupt(unsigned int vec, unsigned int pri, void *isr) +{ + NVIC_SetPriority((IRQn_Type)vec, (uint32_t) pri); + NVIC_SetVector((IRQn_Type)vec, (uint32_t) isr); + + return NULL; +} + +void rda_delete_interrupt(unsigned int vec) +{ + NVIC_SetVector((IRQn_Type)vec, 0); +} + +void rda_enable_interrupt(unsigned int vec) +{ + NVIC_EnableIRQ((IRQn_Type)vec); +} + +void rda_disable_interrupt(unsigned int vec) +{ + NVIC_DisableIRQ((IRQn_Type)vec); +} + +/** \brief Allocates a pbuf and returns the data from the incoming packet. + * + * \param[in] netif the lwip network interface structure + * \param[in] idx index of packet to be read + * \return a pbuf filled with the received packet (including MAC header) + */ +static struct pbuf *r91h_low_level_input(struct netif *netif, u8_t *data, u32_t len, int idx) +{ + struct pbuf *p, *q; + u16_t index = 0; + + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input enter, rxlen:%d\n", len)); + + /* Obtain the size of the packet and put it into the "len" + variable. */ + if(!len) { + return NULL; + } + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for (q = p; q != NULL; q = q->next) { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. + * This does not necessarily have to be a memcpy, you can also preallocate + * pbufs for a DMA-enabled MAC and after receiving truncate it to the + * actually received size. In this case, ensure the tot_len member of the + * pbuf is the sum of the chained pbuf len members. + */ + /* load rx data from 96 to local mem_pool */ + MEMCPY(q->payload, &data[index], q->len); + index += q->len; + + if (index >= len) { + break; + } + } + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.recv); + } else { + /* Drop this packet */ + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input pbuf_alloc fail, rxlen:%d\n", len)); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + + return NULL; + } + + return p; +} + +/** \brief Attempt to read a packet from the EMAC interface. + * + * \param[in] netif the lwip network interface structure + * \param[in] idx index of packet to be read + */ +void *data_sem = NULL; +void r91h_wifiif_input(struct netif *netif, u8_t *data, u32_t len, int idx) +{ + if(data_sem == NULL) + data_sem = rda_sem_create(0); + rda_msg msg; + msg.type = 0; + msg.arg1 = (int)data; + msg.arg2 = len; + msg.arg3 = (int)data_sem; + rda_mail_put(packet_rx_queue, (void*)&msg, osWaitForever); + rda_sem_wait(data_sem, osWaitForever); + return; +} + +/** \brief Low level init of the MAC and PHY. + * + * \param[in] netif Pointer to LWIP netif structure + */ + +static err_t low_level_init(struct netif *netif) +{ + static int init_flag = 0; + if (init_flag == 0) { + wland_reg_func(); + init_flag = 1; + } + return ERR_OK; +} + +/** + * This function is the ethernet packet send function. It calls + * etharp_output after checking link status. + * + * \param[in] netif the lwip network interface structure for this enetif + * \param[in] q Pointer to pbug to send + * \param[in] ipaddr IP address + * \return ERR_OK or error code + */ +err_t rda91h_etharp_output(struct netif *netif, struct pbuf *q, const ip_addr_t *ipaddr) +{ + /* Only send packet is link is up */ + if (netif->flags & NETIF_FLAG_LINK_UP) + return etharp_output(netif, q, ipaddr); + + return ERR_CONN; +} + +/** \brief Low level output of a packet. Never call this from an + * interrupt context, as it may block until TX descriptors + * become available. + * + * \param[in] netif the lwip network interface structure for this netif + * \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent + */ +static err_t rda91h_low_level_output(struct netif *netif, struct pbuf *p) +{ + struct pbuf *q; + + /* rda5996 initiate transfer */ + u32_t actual_txlen = 0; + u8_t **data; + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_output enter, p:%08x\n", p)); + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + data = (void*)wland_get_databuf(); + + if(data == NULL){ + LWIP_DEBUGF(NETIF_DEBUG, ("rda91h_low_level_output, no PKT buf\r\n")); + return ERR_BUF; + } + + for(q = p; q != NULL; q = q->next) + { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + MEMCPY(&((*data)[actual_txlen+2]), q->payload, q->len);//reserve wid header length + actual_txlen += q->len; + if(actual_txlen > 1514 || actual_txlen > p->tot_len) + { + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_output err, actual_txlen:%d, tot_len%d\n", + actual_txlen, p->tot_len)); + return ERR_BUF; + } + } + + /* Signal rda5996 that packet should be sent */ + if(actual_txlen == p->tot_len) + { + if(netif->name[0] == 's' && netif->name[1] == 't') { + wland_txip_data((void*)data, actual_txlen, 0); + } else if(netif->name[0] == 'a' && netif->name[1] == 'p') { + wland_txip_data((void*)data, actual_txlen, 1); + } + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.xmit); + + return ERR_OK; + } + + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_output pkt len mismatch, actual_txlen:%d, tot_len%d\n", + actual_txlen, p->tot_len)); + + + return ERR_BUF; +} + +/** + * Should be called at the beginning of the program to set up the + * network interface. + * + * This function should be passed as a parameter to netif_add(). + * + * @param[in] netif the lwip network interface structure for this netif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t wifi_arch_enetif_init(struct netif *netif) +{ + err_t err; + static int thread_init_flag = 0; + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + if (*((int *)netif->state) == 0) { + r91h_wifidata.netif_sta = netif; + netif->name[0] = 's'; + netif->name[1] = 't'; +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + if(netif->hostname == NULL) + netif->hostname = "lwipr91h_sta"; +#endif /* LWIP_NETIF_HOSTNAME */ + rda_get_macaddr((u8_t *)(netif->hwaddr), 0); + } else if(*((int *)netif->state) == 1) { + r91h_wifidata.netif_ap = netif; + netif->name[0] = 'a'; + netif->name[1] = 'p'; +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + if(netif->hostname == NULL) + netif->hostname = "lwipr91h_ap"; +#endif /* LWIP_NETIF_HOSTNAME */ + rda_get_macaddr((u8_t *)(netif->hwaddr), 1); + } + + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* device capabilities */ + // TODOETH: check if the flags are correct below + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP; + + /* Initialize the hardware */ + netif->state = &r91h_wifidata; + err = low_level_init(netif); + if (err != ERR_OK) + return err; + + netif->output = rda91h_etharp_output; + netif->linkoutput = rda91h_low_level_output; + if(thread_init_flag == 0){ + /* PHY monitoring task */ + sys_thread_new("maclib_thread", maclib_task, netif->state, DEFAULT_THREAD_STACKSIZE*8, PHY_PRIORITY); + sys_thread_new("wland_thread", wland_task, NULL, DEFAULT_THREAD_STACKSIZE*5, PHY_PRIORITY); + /* Allow the PHY task to detect the initial link state and set up the proper flags */ + osDelay(10); + thread_init_flag = 1; + } + return ERR_OK; +} + +unsigned char rda_mac_addr[6] = "\0"; +static int is_available_mac_addr(unsigned char *mac_addr) +{ + if (mac_addr[0]==0 && mac_addr[1]==0 && mac_addr[2]==0 && + mac_addr[3]==0 && mac_addr[4]==0 && mac_addr[5]==0) + return 0; + if (mac_addr[0]&0x1) + return 0; + return 1; +} +static void rda_get_macaddr_from_flash(unsigned char *macaddr) +{ + int ret; + if (!mac_is_valid((char *)rda_mac_addr)) { + ret = rda5981_flash_read_mac_addr(rda_mac_addr); + if ((ret!=0) || (is_available_mac_addr(rda_mac_addr)==0)) { +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) + unsigned int out_len; + ret = mbedtls_hardware_poll(NULL, rda_mac_addr, 6, &out_len); + if (6 != out_len) { + LWIP_DEBUGF(NETIF_DEBUG, ("out_len err:%d\n", out_len)); + } +#else + ret = rda_trng_get_bytes(rda_mac_addr, 6); +#endif + rda_mac_addr[0] &= 0xfe; /* clear multicast bit */ + rda_mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + rda5981_flash_write_mac_addr(rda_mac_addr); + } + } + memcpy(macaddr, rda_mac_addr, 6); +} +void mbed_mac_address(char *mac) +{ + mac[0] = 0xD6; + mac[1] = 0x71; + mac[2] = 0x36; + mac[3] = 0x60; + mac[4] = 0xD8; +#if !MBED_CONF_APP_ECHO_SERVER + mac[5] = 0xF4; +#else + mac[5] = 0xF3; +#endif + return; +} diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda_sys_wrapper.c b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda_sys_wrapper.c new file mode 100644 index 0000000000..35401ef3fe --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/rda_sys_wrapper.c @@ -0,0 +1,450 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if 1 +#include "sys_arch.h" +#include "cmsis_os.h" +#include "cmsis_os2.h" +#include "lwip/sys.h" +#include "rtx_lib.h" + +#include +#include +#include "mbed_assert.h" +#define NO_ERR 0 +#define ERR -1 + +//#define RDA_SYS_DEBUG +#ifdef RDA_SYS_DEBUG +#define RDA_SYS_PRINT(fmt, ...) do {\ + printf(fmt, ##__VA_ARGS__);\ + } while (0) +#else +#define RDA_SYS_PRINT(fmt, ...) +#endif + + +/* Alarm */ +// Timer definitions +#define osTimerInvalid 0 +#define osTimerStopped 1 +#define osTimerRunning 2 +#if 0 +// Timer structures, same as os_timer_cb(rt_CMSIS.c) +typedef struct rda_ostmr_cb { + struct rda_ostmr_cb *next; // Pointer to next active Timer + uint8_t state; // Timer State + uint8_t type; // Timer Type (Periodic/One-shot) + uint16_t reserved; // Reserved + uint32_t tcnt; // Timer Delay Count + uint32_t icnt; // Timer Initial Count + void *arg; // Timer Function Argument + const osTimerDef_t *timer; // Pointer to Timer definition +} rda_ostmr_cb_t; +#endif +//#define USING_STDLIB + +#if !defined(USING_STDLIB) +typedef struct rda_tmr_node { + mbed_rtos_storage_timer_t _obj_mem; +} rda_tmr_node_t; + +typedef struct rda_tmr_ctrl { + unsigned char *buff; + unsigned char *state; + unsigned char max_node_num; + unsigned char node_size; + unsigned char node_cntr; + unsigned char last_freed_node_idx; +} rda_tmr_ctrl_t; + +#define MAX_ALARM_NUM (28) +#define WORD_ALIGN(n) (((n) + 0x03UL) & ~0x03UL) +#define MAX_ALARM_STAT_SIZE WORD_ALIGN(MAX_ALARM_NUM >> 3) +#define MAX_ALARM_MEM_SIZE (MAX_ALARM_NUM * WORD_ALIGN(sizeof(mbed_rtos_storage_timer_t)) + MAX_ALARM_STAT_SIZE) + +unsigned long g_alarm_buf[WORD_ALIGN(MAX_ALARM_MEM_SIZE) >> 2] = {0}; +rda_tmr_ctrl_t g_alarm_ctrl = { + (unsigned char *)g_alarm_buf + MAX_ALARM_STAT_SIZE, + (unsigned char *)g_alarm_buf, + MAX_ALARM_NUM, + WORD_ALIGN(sizeof(mbed_rtos_storage_timer_t)), + 0U, + 0U +}; + +__STATIC_INLINE unsigned char get_node_state(unsigned char *buf, unsigned char idx) +{ + unsigned char state, ofst; + ofst = (idx & 0x07U); + buf += (idx >> 3); + state = (*buf >> ofst) & 0x01U; + return state; +} + +__STATIC_INLINE void set_node_state(unsigned char *buf, unsigned char idx, unsigned char state) +{ + unsigned char ofst, tmp; + ofst = (idx & 0x07U); + buf += (idx >> 3); + tmp = *buf & (~(0x01U << ofst)); + *buf = tmp | (((state & 0x01U) << ofst)); +} + +static rda_tmr_node_t *get_tmr_node(void) +{ + rda_tmr_node_t *node = NULL; + unsigned char idx = g_alarm_ctrl.last_freed_node_idx; + if ((idx < g_alarm_ctrl.max_node_num) && (0U == get_node_state(g_alarm_ctrl.state, idx))) { + set_node_state(g_alarm_ctrl.state, idx, 1U); + node = (rda_tmr_node_t *)(g_alarm_ctrl.buff + idx * g_alarm_ctrl.node_size); + g_alarm_ctrl.node_cntr++; + } else { + for (idx = 0U; idx < g_alarm_ctrl.max_node_num; idx++) { + if(0U == get_node_state(g_alarm_ctrl.state, idx)) { + set_node_state(g_alarm_ctrl.state, idx, 1U); + node = (rda_tmr_node_t *)(g_alarm_ctrl.buff + idx * g_alarm_ctrl.node_size); + g_alarm_ctrl.node_cntr++; + break; + } + } + } + return node; +} + +static void put_tmr_node(rda_tmr_node_t *node) +{ + unsigned char *node_buf = (unsigned char *)node; + unsigned char idx = (node_buf - g_alarm_ctrl.buff) / g_alarm_ctrl.node_size; + if ((node_buf > g_alarm_ctrl.buff) && (idx < g_alarm_ctrl.max_node_num) && + (1U == get_node_state(g_alarm_ctrl.state, idx))) { + set_node_state(g_alarm_ctrl.state, idx, 0U); + g_alarm_ctrl.node_cntr--; + g_alarm_ctrl.last_freed_node_idx = idx; + } +} +#endif /* !USING_STDLIB */ + +/** + * @brief : get current time in units of micro second + * @param[in] : + * @param[out]: + * @return : return time value with uint32 type + */ +unsigned long rda_get_cur_time_ms(void) +{ + return sys_now(); +} + +/** + * @brief : create an alarm with given function, return timer handle + * @param[in] : func(callback)/data(pass to func)/mode(once or periodic) + * @param[out]: + * @return : return timer handle, a pointer to the timer structure, non-zero is valid + */ +void * rda_alarm_create_v2(void *func, unsigned int data, unsigned int mode) +{ + osTimerId_t handle; + mbed_rtos_storage_timer_t* _obj_mem = NULL; + MBED_ASSERT(func != NULL); + osTimerAttr_t attr = { 0 }; +#if defined(USING_STDLIB) + _obj_mem = (mbed_rtos_storage_timer_t*)malloc(sizeof(mbed_rtos_storage_timer_t)); +#else /* USING_STDLIB */ + _obj_mem = (mbed_rtos_storage_timer_t*)get_tmr_node(); +#endif /* USING_STDLIB */ + MBED_ASSERT(_obj_mem != NULL); + memset(_obj_mem, 0, sizeof(_obj_mem)); + attr.cb_mem = _obj_mem; + attr.cb_size = sizeof(mbed_rtos_storage_timer_t); + //printf("hehehehe fun %p\r\n", func); + handle = osTimerNew((osTimerFunc_t)func, mode, (void *)data, &attr); + //printf("time cb %p handle %p\r\n", _obj_mem, handle); + MBED_ASSERT(handle != NULL); + return handle; +} + +void * rda_alarm_create(void *func, unsigned int data) +{ + return rda_alarm_create_v2(func, data, osTimerOnce); +} + +/** + * @brief : delete an alarm with given handle, then reset the handle + * @param[in] : *handle(pointer to the timer structure) + * @param[out]: **handle(address of the handle variable) + * @return : + */ +int rda_alarm_delete(void **handle) +{ + if (NULL != *handle) { + osTimerId timer_id = (osTimerId)(*handle); + osStatus retval = osTimerDelete(timer_id); + if (osOK == retval) { +#if defined(USING_STDLIB) + free(timer_id); +#else /* USING_STDLIB */ + put_tmr_node((rda_tmr_node_t *)timer_id); +#endif /* USING_STDLIB */ + *handle = NULL; + } else { + RDA_SYS_PRINT("Delete alarm error: %d\r\n", retval); + return ERR; + } + return NO_ERR; + } + return ERR; +} + +/** + * @brief : start an alarm, raise a function call after given timeout delay + * @param[in] : handle(pointer to the timer structure)/timeout(micro second) + * @param[out]: + * @return : + */ +int rda_alarm_start(void *handle, unsigned int timeout_ms) +{ + if (NULL != handle) { + osTimerId timer_id = (osTimerId)handle; + osStatus retval = osTimerStart(timer_id, (uint32_t)timeout_ms); + if (osOK != retval) { + RDA_SYS_PRINT("Start alarm error: %d\r\n", retval); + return ERR; + } + return NO_ERR; + } + return ERR; +} + +/** + * @brief : stop an alarm, will not raise a function call any more + * @param[in] : handle(pointer to the timer structure) + * @param[out]: + * @return : + */ +int rda_alarm_stop(void *handle) +{ + if (NULL != handle) { + osTimerId timer_id = (osTimerId)handle; + osStatus retval = osTimerStop(timer_id); + if (osOK != retval) { + RDA_SYS_PRINT("Stop alarm error: %d\r\n", retval); + return ERR; + } + return NO_ERR; + } + return ERR; +} + + + +/* Semaphore */ +void* rda_sem_create(unsigned int count) +{ + osSemaphoreId_t sem; + mbed_rtos_storage_semaphore_t *_obj_mem = (mbed_rtos_storage_semaphore_t*)malloc(sizeof(mbed_rtos_storage_semaphore_t)); + osSemaphoreAttr_t attr = { 0 }; + attr.name = "rda_unnamed_sem"; + attr.cb_mem = _obj_mem; + attr.cb_size = sizeof(mbed_rtos_storage_semaphore_t); + sem = osSemaphoreNew(1, count, &attr); + MBED_ASSERT(sem != NULL); + + return (void*)sem; +} + +int rda_sem_wait(void* sem, unsigned int millisec) +{ + int res; + + res = osSemaphoreWait(sem, millisec); + if (res > 0) { + return NO_ERR; + } else { + RDA_SYS_PRINT("rda_sem_wait error %d\r\n", res); + return ERR; + } +} + +int rda_sem_release(void *sem) +{ + int res; + + res = osSemaphoreRelease(sem); + if (res == 0) { + return NO_ERR; + } else { + RDA_SYS_PRINT("rda_sem_release error %d\r\n", res); + return ERR; + } +} + +int rda_sem_delete(void *sem) +{ + int res; + + res = osSemaphoreDelete(sem); + free(sem); + if (res == 0) { + return NO_ERR; + } else { + RDA_SYS_PRINT("rda_sem_delete error %d\r\n", res); + return ERR; + } +} + +/* Mail */ +void* rda_mail_create(unsigned int msgcnt, unsigned int msgsize) +{ + unsigned int mq_size = msgcnt * (msgsize + sizeof(os_message_t)); + osMessageQueueId_t msgq; + mbed_rtos_storage_msg_queue_t *_obj_mem = (mbed_rtos_storage_msg_queue_t*)malloc(sizeof(mbed_rtos_storage_msg_queue_t)); + MBED_ASSERT(_obj_mem != NULL); + memset(_obj_mem, 0, sizeof(mbed_rtos_storage_msg_queue_t)); + void *_mq_mem = (void *)malloc(mq_size); + MBED_ASSERT(_mq_mem != NULL); + memset(_mq_mem, 0, mq_size); + osMessageQueueAttr_t attr = { 0 }; + attr.name = "rda_unnamed_message_queue"; + attr.cb_mem = _obj_mem; + attr.cb_size = sizeof(mbed_rtos_storage_msg_queue_t); + attr.mq_mem = _mq_mem; + attr.mq_size = mq_size; + msgq = osMessageQueueNew(msgcnt, msgsize, &attr); + MBED_ASSERT(msgq != NULL); + + return (void*)msgq; +} + +int rda_mail_get(void *msgq, void *msg, unsigned int wait) +{ + int ret; + ret = osMessageQueueGet(msgq, msg, 0, wait); + return ret; +} + +int rda_mail_put(void *msgq, void *msg, unsigned int wait) +{ + int ret; + ret = osMessageQueuePut(msgq, msg, 0, wait); + return ret; +} + +/* Mutex */ +void* rda_mutex_create(void) +{ + osMutexId_t rdamutex; + osMutexAttr_t attr = { 0 }; + mbed_rtos_storage_mutex_t *_obj_mem = (mbed_rtos_storage_mutex_t *)malloc(sizeof(mbed_rtos_storage_mutex_t)); + memset(_obj_mem, 0, sizeof(mbed_rtos_storage_mutex_t)); + attr.name = "rda_unnamed_mutex"; + attr.cb_mem = _obj_mem; + attr.cb_size = sizeof(mbed_rtos_storage_mutex_t); + attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; + rdamutex = osMutexNew(&attr); + MBED_ASSERT(rdamutex != NULL); + return (void *)rdamutex; +} + +int rda_mutex_wait(void *rdamutex, unsigned int millisec) +{ + osMutexId_t mutex = (osMutexId_t)rdamutex; + osStatus res; + res = osMutexWait(mutex, millisec); + if (res == osOK) { + return NO_ERR; + } else { + return ERR; + } +} + +int rda_mutex_realease(void *rdamutex) +{ + osMutexId_t mutex = (osMutexId_t)rdamutex; + osStatus res; + res = osMutexRelease(mutex); + if(res == osOK) { + return NO_ERR; + } else { + return ERR; + } +} + +int rda_mutex_delete(void *rdamutex) +{ + osMutexId_t mutex = (osMutexId_t)rdamutex; + osStatus res; + res = osMutexDelete(mutex); + free(mutex); + if (res == osOK) { + return NO_ERR; + } else { + return ERR; + } +} + +/* Thread */ +void* rda_thread_new(const char *pcName, + void (*thread)(void *arg), + void *arg, int stacksize, int priority) +{ + osThreadId_t id; + osThreadAttr_t _attr = { 0 }; + mbed_rtos_storage_thread_t *_obj_mem = (mbed_rtos_storage_thread_t *)malloc(sizeof(mbed_rtos_storage_thread_t)); + MBED_ASSERT(_obj_mem != NULL); + memset(_obj_mem, 0, sizeof(mbed_rtos_storage_thread_t)); + _attr.priority = priority; + _attr.stack_size = stacksize; + _attr.name = pcName ? pcName : "rda_unnamed_thread"; + _attr.stack_mem = malloc(stacksize); + MBED_ASSERT(_attr.stack_mem != NULL); + _attr.cb_size = sizeof(mbed_rtos_storage_thread_t); + _attr.cb_mem = _obj_mem; + _attr.tz_module = 0; + + //Fill the stack with a magic word for maximum usage checking + for (uint32_t i = 0; i < (_attr.stack_size / sizeof(uint32_t)); i++) { + ((uint32_t *)_attr.stack_mem)[i] = 0xE25A2EA5; + } + id = osThreadNew(thread, arg, &_attr); + if (id == NULL){ + free(_attr.stack_mem); + free(_attr.cb_mem); + RDA_SYS_PRINT("sys_thread_new create error\n"); + return NULL; + } + return (void *)id; +} + +int rda_thread_delete(void* id) +{ + osStatus ret; + unsigned int *stk = ((osRtxThread_t *)id)->stack_mem; + ret = osThreadTerminate(id); + free(id); + free(stk); + if (ret != osOK) { + return ERR; + } + return NO_ERR; +} + +void* rda_thread_get_id(void) +{ + osThreadId id = osThreadGetId(); + return (void*)id; +} +#endif diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash.c b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash.c new file mode 100644 index 0000000000..a2c0cd8ffa --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash.c @@ -0,0 +1,1481 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include "critical.h" +#include "wland_flash.h" +#include "wland_dbg.h" +#include "rda5981_flash.h" +#include "wland_flash_wp.h" + +#define MACDBG "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC2STRDBG(ea) (ea)[0], (ea)[1], (ea)[2], (ea)[3], (ea)[4], (ea)[5] + +u32 flash_size = FLASH_SIZE; +static u32 user_data_location = RDA5991H_USER_DATA_ADDR; +static u32 third_parter_data_location = RDA5991H_3RDPARTER_DATA_ADDR; +static u32 third_parter_data_len = RDA5991H_3RDPARTER_DATA_LEN; +int rda5981_read_flash(u32 addr, char *buf, u32 len) +{ + int ret = 0; + char *temp_buf = NULL, *temp_buf_aligned; + + addr &= (flash_size -1); + if (addr < RDA5991H_PARTITION_TABLE_END_ADDR-0x18000000) { + WLAND_DBG(ERROR, "couldn't read system data\n"); + return -1; + } + + if ((u32)buf % 4) { + temp_buf = malloc(len + 3); + if (temp_buf == NULL) { + ret = -1; + goto out; + } + if ((u32)temp_buf % 4) { + temp_buf_aligned = temp_buf + (4-(u32)temp_buf%4); + } else { + temp_buf_aligned = temp_buf; + } + } else { + temp_buf_aligned = buf; + } + + core_util_critical_section_enter(); + spi_flash_flush_cache(); + SPI_FLASH_READ_DATA_FOR_MBED((void *)addr, temp_buf_aligned, len); + core_util_critical_section_exit(); + + if (temp_buf_aligned != buf) { + memcpy(buf, temp_buf_aligned, len); + } + +out: + if (temp_buf) { + free(temp_buf); + } + + return ret; +} + +void rda5981_spi_flash_erase_64KB_block(u32 addr) +{ + if (rda_ccfg_hwver() < 4) { + spi_wip_reset_2(); + spi_write_reset_2(); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, CMD_64KB_BLOCK_ERASE | (addr<<8)); + wait_busy_down_2(); + spi_wip_reset_2(); + } else { + spi_wip_reset_4(); + spi_write_reset_4(); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, CMD_64KB_BLOCK_ERASE | (addr<<8)); + wait_busy_down_4(); + spi_wip_reset_4(); + } +} +void rda5981_spi_erase_partition(void *src, u32 counts) +{ + u32 a4k, a64k, a64kend, a4kend, atmp; + + if (counts > 0x00) { + a4k = ((u32)src ) & (~((0x01UL << 12) - 0x01UL)); + a64k = ((u32)src + (0x01UL << 16) - 0x01UL) & (~((0x01UL << 16) - 0x01UL)); + a64kend = ((u32)src + counts ) & (~((0x01UL << 16) - 0x01UL)); + a4kend = ((u32)src + counts + (0x01UL << 12) - 0x01UL) & (~((0x01UL << 12) - 0x01UL)); + + for (atmp = a4k; atmp < a4kend; atmp += (0x01UL << 12)) { + if (a64kend > a64k) { + if (atmp == a64k) { + for (; atmp < a64kend; atmp += (0x01UL << 16)) { + core_util_critical_section_enter(); + rda5981_spi_flash_erase_64KB_block(atmp); + core_util_critical_section_exit(); + } + if (atmp == a4kend) { + break; + } + } + } + core_util_critical_section_enter(); + rda5981_spi_flash_erase_4KB_sector(atmp); + core_util_critical_section_exit(); + } + } +} +//@len must be 4k aligment +int rda5981_erase_flash(u32 addr, u32 len) +{ + WLAND_DBG(INFO, "erase flash :%x:%x\n", addr, len); + + addr &= (flash_size - 1); + if (addr < RDA5991H_PARTITION_TABLE_END_ADDR-0x18000000) { + WLAND_DBG(ERROR, "couldn't erase system data\n"); + return -1; + } + + if (len & (SECTOR_SIZE-1)) { + len = ((len+SECTOR_SIZE) & (~(SECTOR_SIZE-1))); + } + flash_wrtie_protect(addr); + rda5981_spi_erase_partition((void*)addr, len); + flash_wrtie_protect_all(); + return 0; +} + +//@len must be 256 aligment +int rda5981_write_flash(u32 addr, char *buf, u32 len) +{ + int ret = 0; + u8 *temp_buf = NULL, *temp_buf_aligned; + u8 *check_buf = NULL; + + addr &= (flash_size -1); + if (addr < RDA5991H_PARTITION_TABLE_END_ADDR-0x18000000) { + WLAND_DBG(ERROR, "couldn't write system data\n"); + return -1; + } + + if ((u32)buf % 4) { + temp_buf = malloc(len + 3); + if (temp_buf == NULL) { + goto out; + } + if ((u32)temp_buf % 4) { + temp_buf_aligned = temp_buf + (4-(u32)temp_buf%4); + } else { + temp_buf_aligned = temp_buf; + } + memcpy(temp_buf_aligned, buf, len); + } else { + temp_buf_aligned = (u8*)buf; + } + flash_wrtie_protect(addr); + core_util_critical_section_enter(); + //RDA5991H_ERASE_FLASH(addr, len); + RDA5991H_WRITE_FLASH(addr, temp_buf_aligned, len); + core_util_critical_section_exit(); + flash_wrtie_protect_all(); + +#ifdef FLASH_READ_CHECK + if (ret == 0) { + check_buf = malloc(len); + rda5981_read_flash(addr, check_buf, len); + if (memcmp(buf, check_buf, len) == 0) { + ret = 0; + } else { + ret = -1; + } + } +#endif /*FLASH_READ_CHECK*/ + +out: + if (temp_buf) { + free(temp_buf); + } + if (check_buf) { + free(check_buf); + } + return ret; +} + +/* + * return 0:ok, else:error. + */ +rda5991h_user_data wland_user_data; +u8 read_flag = 0; +int rda5981_write_user_data(u8 *data, u16 len, u32 flag) +{ + WLAND_DBG(INFO, "Enter, flag:0x%x\r\n", flag); + + if (!read_flag) { + if (0 == rda5981_read_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data))) { + read_flag = 1; + } else { + return -1; + } + } + + if ((wland_user_data.flag & RDA5991H_USER_DATA_FLAG_UNINITIALIZED) || + strcmp((const char *)(wland_user_data.rda5981_flag), RDA5981_FLAG_FLAG)) { + memset(&wland_user_data, 0xff, sizeof(wland_user_data)); + wland_user_data.flag = flag; + strcpy((char *)(wland_user_data.rda5981_flag), RDA5981_FLAG_FLAG); + } + + wland_user_data.flag |= flag; + + switch (flag) { + case RDA5991H_USER_DATA_FLAG_STA: + memcpy(&wland_user_data.sta_data, data, + min(sizeof(wland_user_data.sta_data), len)); + break; + case RDA5991H_USER_DATA_FLAG_MAC: + memcpy(wland_user_data.mac_addr, data, + min(sizeof(wland_user_data.mac_addr), len)); + break; + case RDA5991H_USER_DATA_FLAG_PMK: + memcpy(wland_user_data.pmk, data, + min(sizeof(wland_user_data.pmk), len)); + break; + case RDA5991H_USER_DATA_FLAG_IP: + memcpy(wland_user_data.ip, data, + min(RDA5991H_USER_DATA_IP_LENGTH, len)); + break; + case RDA5991H_USER_DATA_FLAG_PARTER_DATA_LEN: + memcpy(&wland_user_data.parter_data_len, data, + min(sizeof(wland_user_data.parter_data_len), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER: + memcpy(&wland_user_data.tx_power, data, + min(sizeof(wland_user_data.tx_power), len)); + break; + case RDA5991H_USER_DATA_FLAG_XTAL_CAL: + memcpy(&wland_user_data.xtal_cal, data, + min(sizeof(wland_user_data.xtal_cal), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_RF: + memcpy(&wland_user_data.tx_power_rf, data, + min(sizeof(wland_user_data.tx_power_rf), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_PHY_GN: + memcpy(&wland_user_data.tx_power_phy_gn, data, + min(sizeof(wland_user_data.tx_power_phy_gn), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_PHY_B: + memcpy(&wland_user_data.tx_power_phy_b, data, + min(sizeof(wland_user_data.tx_power_phy_b), len)); + break; + case RDA5991H_USER_DATA_FLAG_AP: + memcpy(&wland_user_data.ap_data, data, + min(sizeof(wland_user_data.ap_data), len)); + break; + case RDA5991H_USER_DATA_FLAG_APNET: + memcpy(&wland_user_data.ap_net_data, data, + min(sizeof(wland_user_data.ap_net_data), len)); + break; + case RDA5991H_USER_DATA_FLAG_DHCP: + memcpy(&wland_user_data.dhcp, data, + min(sizeof(wland_user_data.dhcp), len)); + break; + case RDA5991H_USER_DATA_FLAG_UART: + memcpy(&wland_user_data.uart, data, + min(sizeof(wland_user_data.uart), len)); + break; + case RDA5991H_USER_DATA_FLAG_RF: + memcpy(&wland_user_data.rf, data, + min(sizeof(wland_user_data.rf), len)); + break; + case RDA5991H_USER_DATA_FLAG_RF_CHANNELS: + memcpy(&wland_user_data.rf_channels, data, + min(sizeof(wland_user_data.rf_channels), len)); + break; + case RDA5991H_USER_DATA_FLAG_PHY: + memcpy(&wland_user_data.phy, data, + min(sizeof(wland_user_data.phy), len)); + break; + case RDA5991H_USER_DATA_FLAG_PHY_CHANNELS: + memcpy(&wland_user_data.phy_channels, data, + min(sizeof(wland_user_data.phy_channels), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_OFFSET: + memcpy(&wland_user_data.tp_offset, data, + min(sizeof(wland_user_data.tp_offset), len)); + break; + default: + return -1; + } + rda5981_erase_flash(user_data_location, sizeof(wland_user_data)); + return rda5981_write_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data)); +} + +/* + * return 0:ok, else:error. + */ +int rda5981_erase_user_data(u32 flag) +{ + if (!read_flag) { + read_flag = 1; + rda5981_read_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data)); + } + + if (wland_user_data.flag & RDA5991H_USER_DATA_FLAG_UNINITIALIZED) {//flash init is 0xffffffff + return -1; + } + + if ((wland_user_data.flag & flag) == 0) { + return 0; + } + + wland_user_data.flag &= (~flag); + + if (wland_user_data.flag == 0) { + wland_user_data.flag = RDA5991H_USER_DATA_FLAG_UNINITIALIZED; + } + if (flag & RDA5991H_USER_DATA_FLAG_STA) { + memset(&wland_user_data.sta_data, 0xff, + sizeof(wland_user_data.sta_data)); + } + if (flag & RDA5991H_USER_DATA_FLAG_MAC) { + memset(wland_user_data.mac_addr, 0xff, + sizeof(wland_user_data.mac_addr)); + } + if (flag & RDA5991H_USER_DATA_FLAG_PMK) { + memset(wland_user_data.pmk, 0xff, + sizeof(wland_user_data.pmk)); + } + if (flag & RDA5991H_USER_DATA_FLAG_IP) { + memset(wland_user_data.ip, 0xff, + RDA5991H_USER_DATA_IP_LENGTH); + } + if (flag & RDA5991H_USER_DATA_FLAG_PARTER_DATA_LEN) { + memset(&wland_user_data.parter_data_len, 0xff, + sizeof(wland_user_data.parter_data_len)); + } + if (flag & RDA5991H_USER_DATA_FLAG_TX_POWER) { + memset(&wland_user_data.tx_power, 0xff, + sizeof(wland_user_data.tx_power)); + } + if (flag & RDA5991H_USER_DATA_FLAG_XTAL_CAL) { + memset(&wland_user_data.xtal_cal, 0xff, + sizeof(wland_user_data.xtal_cal)); + } + if (flag & RDA5991H_USER_DATA_FLAG_TX_POWER_RF) { + memset(&wland_user_data.tx_power_rf, 0xff, + sizeof(wland_user_data.tx_power_rf)); + } + if (flag & RDA5991H_USER_DATA_FLAG_TX_POWER_PHY_GN) { + memset(&wland_user_data.tx_power_phy_gn, 0xff, + sizeof(wland_user_data.tx_power_phy_gn)); + } + if (flag & RDA5991H_USER_DATA_FLAG_TX_POWER_PHY_B) { + memset(&wland_user_data.tx_power_phy_b, 0xff, + sizeof(wland_user_data.tx_power_phy_b)); + } + if (flag & RDA5991H_USER_DATA_FLAG_AP) { + memset(&wland_user_data.ap_data, 0xff, + sizeof(wland_user_data.ap_data)); + } + if (flag & RDA5991H_USER_DATA_FLAG_APNET) { + memset(&wland_user_data.ap_net_data, 0xff, + sizeof(wland_user_data.ap_net_data)); + } + if (flag & RDA5991H_USER_DATA_FLAG_DHCP) { + memset(&wland_user_data.dhcp, 0xff, + sizeof(wland_user_data.dhcp)); + } + if (flag & RDA5991H_USER_DATA_FLAG_UART) { + memset(&wland_user_data.uart, 0xff, + sizeof(wland_user_data.uart)); + } + if (flag & RDA5991H_USER_DATA_FLAG_RF) { + memset(&wland_user_data.rf, 0xff, + sizeof(wland_user_data.rf)); + } + if (flag & RDA5991H_USER_DATA_FLAG_RF_CHANNELS) { + memset(&wland_user_data.rf_channels, 0xff, + sizeof(wland_user_data.rf_channels)); + } + if (flag & RDA5991H_USER_DATA_FLAG_PHY) { + memset(&wland_user_data.phy, 0xff, + sizeof(wland_user_data.phy)); + } + if (flag & RDA5991H_USER_DATA_FLAG_PHY_CHANNELS) { + memset(&wland_user_data.phy_channels, 0xff, + sizeof(wland_user_data.phy_channels)); + } + if (flag & RDA5991H_USER_DATA_FLAG_TX_POWER_OFFSET) { + memset(&wland_user_data.tp_offset, 0xff, + sizeof(wland_user_data.tp_offset)); + } + rda5981_erase_flash(user_data_location, sizeof(wland_user_data)); + return rda5981_write_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data)); +} + +/* + * return 0:ok, else:error. + */ +int rda5981_read_user_data(u8 *data, u16 len, u32 flag) +{ + //rda5991h_user_data wland_user_data; + WLAND_DBG(INFO, "Enter, flag:0x%x\r\n", flag); + + if (!read_flag) { + read_flag = 1; + rda5981_read_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data)); + } + + if (wland_user_data.flag & RDA5991H_USER_DATA_FLAG_UNINITIALIZED) {//flash init is 0xffffffff + return -1; + } + if (strcmp((const char *)(wland_user_data.rda5981_flag), RDA5981_FLAG_FLAG)) { + return -2; + } + if ((wland_user_data.flag & flag) == 0) { + return -3; + } + switch (flag) { + case RDA5991H_USER_DATA_FLAG_STA: + memcpy(data, &wland_user_data.sta_data, + min(sizeof(wland_user_data.sta_data), len)); + break; + case RDA5991H_USER_DATA_FLAG_MAC: + memcpy(data, wland_user_data.mac_addr, + min(sizeof(wland_user_data.mac_addr), len)); + break; + case RDA5991H_USER_DATA_FLAG_PMK: + memcpy(data, wland_user_data.pmk, + min(sizeof(wland_user_data.pmk), len)); + break; + case RDA5991H_USER_DATA_FLAG_IP: + memcpy(data, wland_user_data.ip, + min(RDA5991H_USER_DATA_IP_LENGTH, len)); + break; + case RDA5991H_USER_DATA_FLAG_PARTER_DATA_LEN: + memcpy(data, &wland_user_data.parter_data_len, + min(sizeof(wland_user_data.parter_data_len), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER: + memcpy(data, &wland_user_data.tx_power, + min(sizeof(wland_user_data.tx_power), len)); + break; + case RDA5991H_USER_DATA_FLAG_XTAL_CAL: + memcpy(data, &wland_user_data.xtal_cal, + min(sizeof(wland_user_data.xtal_cal), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_RF: + memcpy(data, &wland_user_data.tx_power_rf, + min(sizeof(wland_user_data.tx_power_rf), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_PHY_GN: + memcpy(data, &wland_user_data.tx_power_phy_gn, + min(sizeof(wland_user_data.tx_power_phy_gn), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_PHY_B: + memcpy(data, &wland_user_data.tx_power_phy_b, + min(sizeof(wland_user_data.tx_power_phy_b), len)); + break; + case RDA5991H_USER_DATA_FLAG_AP: + memcpy(data, &wland_user_data.ap_data, + min(sizeof(wland_user_data.ap_data), len)); + break; + case RDA5991H_USER_DATA_FLAG_APNET: + memcpy(data, &wland_user_data.ap_net_data, + min(sizeof(wland_user_data.ap_net_data), len)); + break; + case RDA5991H_USER_DATA_FLAG_DHCP: + memcpy(data, &wland_user_data.dhcp, + min(sizeof(wland_user_data.dhcp), len)); + break; + case RDA5991H_USER_DATA_FLAG_UART: + memcpy(data, &wland_user_data.uart, + min(sizeof(wland_user_data.uart), len)); + break; + case RDA5991H_USER_DATA_FLAG_RF: + memcpy(data, &wland_user_data.rf, + min(sizeof(wland_user_data.rf), len)); + break; + case RDA5991H_USER_DATA_FLAG_RF_CHANNELS: + memcpy(data, &wland_user_data.rf_channels, + min(sizeof(wland_user_data.rf_channels), len)); + break; + case RDA5991H_USER_DATA_FLAG_PHY: + memcpy(data, &wland_user_data.phy, + min(sizeof(wland_user_data.phy), len)); + break; + case RDA5991H_USER_DATA_FLAG_PHY_CHANNELS: + memcpy(data, &wland_user_data.phy_channels, + min(sizeof(wland_user_data.phy_channels), len)); + break; + case RDA5991H_USER_DATA_FLAG_TX_POWER_OFFSET: + memcpy(data, &wland_user_data.tp_offset, + min(sizeof(wland_user_data.tp_offset), len)); + break; + default: + return -1; + } + return 0; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_mac_addr(u8 *mac_addr) +{ + int ret; + WLAND_DBG(DEBUG, "Enter\r\n"); + ret = rda5981_read_user_data(mac_addr, 6, RDA5991H_USER_DATA_FLAG_MAC); + if (ret) { + WLAND_DBG(ERROR, "read mac addr from flash fail\r\n"); + } else { + WLAND_DBG(INFO, "Done(ret:%d)"MACDBG"\r\n", ret, MAC2STRDBG(mac_addr)); + } + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_write_mac_addr(u8 *mac_addr) +{ + WLAND_DBG(INFO, "Enter"MACDBG"\r\n", MAC2STRDBG(mac_addr)); + return rda5981_write_user_data(mac_addr, 6, RDA5991H_USER_DATA_FLAG_MAC); +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_erase_uart(void) +{ + return rda5981_erase_user_data(RDA5991H_USER_DATA_FLAG_UART); +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_uart(u32 *uart) +{ + int ret; + WLAND_DBG(DEBUG, "Enter\r\n"); + ret = rda5981_read_user_data((u8 *)uart, 4, RDA5991H_USER_DATA_FLAG_UART); + if (ret) { + WLAND_DBG(ERROR, "read uart setting from flash fail\r\n"); + } + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_write_uart(u32 *uart) +{ + return rda5981_write_user_data((u8 *)uart, 4, RDA5991H_USER_DATA_FLAG_UART); +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_erase_sta_data(void) +{ + int ret; + ret = rda5981_erase_user_data(RDA5991H_USER_DATA_FLAG_PMK | + RDA5991H_USER_DATA_FLAG_STA); + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_sta_data(char *ssid, char *passwd) +{ + int ret; + wland_sta_data_t sta_data; + + WLAND_DBG(INFO, "Enter\r\n"); + + ret = rda5981_read_user_data((u8 *)&sta_data, sizeof(sta_data), RDA5991H_USER_DATA_FLAG_STA); + if (ret == 0) { + strcpy(ssid, sta_data.ssid); + strcpy(passwd, sta_data.key); + } + return ret; +} + +/* + * return 0:ok, else:error. + */ +extern u8 *rda_get_bssinfo_pmk(void); +extern u8 *rda_get_bssinfo_SSID(void); +int rda5981_flash_write_sta_data(const char *ssid, const char *passwd) +{ + int ret = 0, ret1; + wland_sta_data_t sta_data; + u8 *pbss_info_pmk = NULL, *pbss_info_SSID = NULL; + pbss_info_pmk = rda_get_bssinfo_pmk(); + pbss_info_SSID = rda_get_bssinfo_SSID(); + + WLAND_DBG(INFO, "Enter:ssid:%s,pw:%s, pmk:%02x %02x***\r\n", + ssid, passwd, pbss_info_pmk[0], pbss_info_SSID[1]); + if (strlen(ssid) == 0) { + WLAND_DBG(ERROR, "ssid is NULL\n"); + return -1; + } + + memset(&sta_data, 0xff, sizeof(sta_data)); + strcpy(sta_data.ssid, ssid); + strcpy(sta_data.key, passwd); + if (pbss_info_pmk[0] && memcmp(pbss_info_SSID, ssid, 6)==0) { + ret = rda5981_write_user_data(pbss_info_pmk, sizeof(pbss_info_pmk), RDA5991H_USER_DATA_FLAG_PMK); + } + ret1 = rda5981_write_user_data((u8 *)&sta_data, sizeof(sta_data), RDA5991H_USER_DATA_FLAG_STA); + return ret || ret1;; +} + + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_erase_dhcp_data(void) +{ + int ret;//, ret1; + //WLAND_DBG(INFO, "Enter\r\n"); + ret = rda5981_erase_user_data(RDA5991H_USER_DATA_FLAG_DHCP); + //ret1 = rda5981_erase_user_data(RDA5991H_USER_DATA_FLAG_PMK); + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_dhcp_data(unsigned int *fixip, unsigned int *ip, unsigned int *msk, unsigned int *gw) +{ + int ret; + wland_dhcp_t dhcp; + + WLAND_DBG(INFO, "Enter\r\n"); + + ret = rda5981_read_user_data((u8 *)&dhcp, sizeof(dhcp), RDA5991H_USER_DATA_FLAG_DHCP); + if (ret == 0) { + *fixip = dhcp.fixip; + *ip = dhcp.ip; + *msk = dhcp.msk; + *gw = dhcp.gw; + } + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_write_dhcp_data(unsigned int fixip, unsigned int ip, unsigned int msk, unsigned int gw) +{ + int ret = 0; + wland_dhcp_t dhcp; + + memset(&dhcp, 0xff, sizeof(dhcp)); + dhcp.fixip = fixip; + dhcp.ip = ip; + dhcp.msk = msk; + dhcp.gw = gw; + ret = rda5981_write_user_data((u8 *)&dhcp, sizeof(dhcp), RDA5991H_USER_DATA_FLAG_DHCP); + return ret; +} + + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_erase_ap_data(void) +{ + int ret; + ret = rda5981_erase_user_data(RDA5991H_USER_DATA_FLAG_AP); + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_write_ap_data(const char *ssid, const char *passwd, unsigned char channel) +{ + int ret = 0; + wland_ap_data_t ap_data; + + if (strlen(ssid) == 0) { + WLAND_DBG(ERROR, "ssid is NULL\n"); + return -1; + } + + memset(&ap_data, 0xff, sizeof(ap_data)); + strcpy(ap_data.ssid, ssid); + strcpy(ap_data.key, passwd); + ap_data.channel = channel; + ret = rda5981_write_user_data((u8 *)&ap_data, sizeof(ap_data), RDA5991H_USER_DATA_FLAG_AP); + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_ap_data(char *ssid, char *passwd, unsigned char *channel) +{ + int ret; + wland_ap_data_t ap_data; + + WLAND_DBG(INFO, "Enter\r\n"); + + ret = rda5981_read_user_data((u8 *)&ap_data, sizeof(ap_data), RDA5991H_USER_DATA_FLAG_AP); + if (ret == 0) { + strcpy(ssid, ap_data.ssid); + strcpy(passwd, ap_data.key); + *channel = ap_data.channel; + } + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_erase_ap_net_data(void) +{ + int ret; + ret = rda5981_erase_user_data(RDA5991H_USER_DATA_FLAG_APNET); + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_write_ap_net_data(unsigned int ip, unsigned int msk, unsigned int gw, + unsigned int dhcps, unsigned int dhcpe) +{ + int ret = 0; + wland_ap_net_data_t ap_net_data; + + WLAND_DBG(INFO, "Enter\r\n"); + + memset(&ap_net_data, 0xff, sizeof(ap_net_data)); + ap_net_data.ip = ip; + ap_net_data.msk = msk; + ap_net_data.gw = gw; + ap_net_data.dhcps = dhcps; + ap_net_data.dhcpe = dhcpe; + + ret = rda5981_write_user_data((u8 *)&ap_net_data, sizeof(ap_net_data), RDA5991H_USER_DATA_FLAG_APNET); + return ret; +} + +/* + * return 0:ok, else:error. + */ +int rda5981_flash_read_ap_net_data(unsigned int *ip, unsigned int *msk, unsigned int *gw, + unsigned int *dhcps, unsigned int *dhcpe) +{ + int ret = 0; + wland_ap_net_data_t ap_net_data; + + WLAND_DBG(INFO, "Enter\r\n"); + + ret = rda5981_read_user_data((u8 *)&ap_net_data, sizeof(ap_net_data), RDA5991H_USER_DATA_FLAG_APNET); + if (ret == 0) { + *ip = ap_net_data.ip; + *msk = ap_net_data.msk; + *gw = ap_net_data.gw; + *dhcps = ap_net_data.dhcps; + *dhcpe = ap_net_data.dhcpe; + } + return ret; +} + + +int rda5981_flash_read_pmk(u8 *pmk) +{ + WLAND_DBG(INFO, "Enter\r\n"); + return rda5981_read_user_data(pmk, 32, RDA5991H_USER_DATA_FLAG_PMK); +} + +int rda5981_flash_read_ip_addr(u8 *ip_addr, u8 *server_addr) +{ + int ret; + u8 buf[RDA5991H_USER_DATA_IP_LENGTH]; + WLAND_DBG(DEBUG, "Enter\r\n"); + ret = rda5981_read_user_data(buf, RDA5991H_USER_DATA_IP_LENGTH, RDA5991H_USER_DATA_FLAG_IP); + if (ret) { + WLAND_DBG(ERROR, "read ip addr from flash fail\r\n"); + } else { + memcpy(ip_addr, buf, 4); + memcpy(server_addr, buf+4, 4); + WLAND_DBG(INFO, "read ip:%u.%u.%u.%u\r\n", ip_addr[0], ip_addr[1], ip_addr[2], ip_addr[3]); + } + return ret; +} + +int rda5981_flash_write_ip_addr(u8 *ip_addr, u8 *server_addr) +{ + u8 buf[RDA5991H_USER_DATA_IP_LENGTH]; + WLAND_DBG(INFO, "write:%u.%u.%u.%u\r\n", ip_addr[0], ip_addr[1], ip_addr[2], ip_addr[3]); + memcpy(buf, ip_addr, 4); + memcpy(buf+4, server_addr, 4); + return rda5981_write_user_data(buf, RDA5991H_USER_DATA_IP_LENGTH, RDA5991H_USER_DATA_FLAG_IP); +} + +int rda5981_flash_read_3rdparter_data_length() +{ + int ret; + u32 data_len = 0; + + WLAND_DBG(INFO, "Enter\r\n"); + ret = rda5981_read_user_data((u8 *)(&data_len), 4, RDA5991H_USER_DATA_FLAG_PARTER_DATA_LEN); + if (ret) { + WLAND_DBG(ERROR, "read parter data length from flash fail(%d)\r\n", ret); + return -1; + } + return data_len; +} + +int rda5981_flash_read_3rdparter_data(u8 *buf, u32 buf_len) +{ + int ret; + u32 data_len = 0; + + WLAND_DBG(INFO, "Enter: %u\r\n", buf_len); + ret = rda5981_read_user_data((u8 *)(&data_len), 4, RDA5991H_USER_DATA_FLAG_PARTER_DATA_LEN); + if (ret) { + WLAND_DBG(ERROR, "read parter data length from flash fail(%d)\r\n", ret); + return -1; + } + + if (buf_len < data_len) + WLAND_DBG(ERROR, "The buf you prepared is to small(%u:%u)\r\n", buf_len, data_len); + + data_len = min(buf_len, data_len); + + ret = rda5981_read_flash(third_parter_data_location, + (char *)(buf), data_len); + if (ret) { + WLAND_DBG(ERROR, "read parter data from flash fail(%d)\r\n", ret); + return -2; + } + + return data_len; +} + +int rda5981_flash_erase_3rdparter_data() +{ + return rda5981_erase_user_data(RDA5991H_USER_DATA_FLAG_PARTER_DATA_LEN); +} + +int rda5981_flash_write_3rdparter_data(const u8 *buf, u32 buf_len) +{ + int ret; + + WLAND_DBG(INFO, "Enter: %u\r\n", buf_len); + if (buf_len > third_parter_data_len) { + WLAND_DBG(ERROR, "buf too long(%u), we have only %x flash space\r\n", + buf_len, third_parter_data_len); + return -1; + } + + rda5981_erase_flash(third_parter_data_location, buf_len); + ret = rda5981_write_flash(third_parter_data_location, + (char *)(buf), buf_len); + if (ret) { + WLAND_DBG(ERROR, "write parter data to flash fail\r\n"); + return -2; + } + + ret = rda5981_write_user_data((u8 *)(&buf_len), 4, RDA5991H_USER_DATA_FLAG_PARTER_DATA_LEN); + if (ret) { + WLAND_DBG(ERROR, "write parter data length to flash fail\r\n"); + return -3; + } + return 0; +} + +int rda5981_set_flash_size(const u32 size) +{ + + WLAND_DBG(INFO, "Enter set flash size: %x\r\n", size); + if (size == 0x100000 || + size == 0x200000 || + size == 0x400000) { + flash_size = size; + return 0; + } + + return -1; +} + +int rda5981_set_user_data_addr(const u32 sys_data_addr, + const u32 user_data_addr, const u32 user_data_len) +{ + WLAND_DBG(INFO, "Enter set userdata addr: %x:%x:%x\r\n", + sys_data_addr, user_data_addr, user_data_len); + if ((sys_data_addr&(SECTOR_SIZE-1)) || (user_data_addr&(SECTOR_SIZE-1))) { + return -1; + } + if (sys_data_addr == user_data_addr) { + return -2; + } + + if (sys_data_addr<=0x18001000 || user_data_addr<=0x18001000) { + return -3; + } + if (sys_data_addr+0x1000 > 0x18000000+flash_size) { + return -4; + } + if (user_data_addr+user_data_len > 0x18000000+flash_size) { + return -5; + } + + user_data_location = sys_data_addr; + third_parter_data_location = user_data_addr; + third_parter_data_len= user_data_len; + return 0; +} + +int rda5981_write_user_data_regs(u8 *reg, u8 *value, u32 flag) +{ + u16 reg16 = 0; + u32 reg32 = 0; + u8 idx = 0; + + if (!read_flag) { + if (0 == rda5981_read_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data))) { + read_flag = 1; + } else { + return -1; + } + } + + if ((wland_user_data.flag & RDA5991H_USER_DATA_FLAG_UNINITIALIZED) || + strcmp((const char *)(wland_user_data.rda5981_flag), RDA5981_FLAG_FLAG)) { + memset(&wland_user_data, 0xff, sizeof(wland_user_data)); + wland_user_data.flag = flag; + strcpy((char *)(wland_user_data.rda5981_flag), RDA5981_FLAG_FLAG); + } + + wland_user_data.flag |= flag; + + switch (flag) { + case RDA5991H_USER_DATA_FLAG_RF: + if (wland_user_data.rf.valid != 1) { + wland_user_data.rf.valid = 1; + wland_user_data.rf.flag = 0; + } + + reg16 = *((u16 *)reg); + if (wland_user_data.rf.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.rf.flag & BIT(idx)) && + (wland_user_data.rf.reg_val[idx][0] == reg16)) { + wland_user_data.rf.reg_val[idx][1] = *((u16 *)value); + break; + } else { + continue; + } + } + if ((8 == idx) && (0xFF == wland_user_data.rf.flag)) + return -2; + } + + if ((8 == idx) || (0 == wland_user_data.rf.flag)) { + for (idx = 0; idx < 8; idx++) { + if (!(wland_user_data.rf.flag & BIT(idx))) { + wland_user_data.rf.reg_val[idx][0] = reg16; + wland_user_data.rf.reg_val[idx][1] = *((u16 *)value); + wland_user_data.rf.flag |= BIT(idx); + break; + } else { + continue; + } + } + } + + break; + case RDA5991H_USER_DATA_FLAG_RF_CHANNELS: + if (wland_user_data.rf_channels.valid != 1) { + wland_user_data.rf_channels.valid = 1; + wland_user_data.rf_channels.flag = 0; + } + + reg16 = *((u16 *)reg); + if (wland_user_data.rf_channels.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.rf_channels.flag & BIT(idx)) && + (wland_user_data.rf_channels.reg_val[idx][0] == reg16)) { + memcpy(&wland_user_data.rf_channels.reg_val[idx][1], value, 14 * sizeof(u16)); + break; + } else { + continue; + } + } + if ((8 == idx) && (0xFF == wland_user_data.rf_channels.flag)) { + return -2; + } + } + + if ((8 == idx) || (0 == wland_user_data.rf_channels.flag)) { + for (idx = 0; idx < 8; idx++) { + if (!(wland_user_data.rf_channels.flag & BIT(idx))) { + wland_user_data.rf_channels.reg_val[idx][0] = reg16; + memcpy(&wland_user_data.rf_channels.reg_val[idx][1], value, 14 * sizeof(u16)); + wland_user_data.rf_channels.flag |= BIT(idx); + break; + } else { + continue; + } + } + } + break; + case RDA5991H_USER_DATA_FLAG_PHY: + if (wland_user_data.phy.valid != 1) { + wland_user_data.phy.valid = 1; + wland_user_data.phy.flag = 0; + } + + reg32 = *((u32 *)reg); + if (wland_user_data.phy.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.phy.flag & BIT(idx)) && + (wland_user_data.phy.reg_val[idx][0] == reg32)) { + wland_user_data.phy.reg_val[idx][1] = *((u32 *)value); + break; + } else { + continue; + } + } + if ((8 == idx) && (0xFF == wland_user_data.phy.flag)) { + return -2; + } + } + + if ((8 == idx) || (0 == wland_user_data.phy.flag)) { + for (idx = 0; idx < 8; idx++) { + if (!(wland_user_data.phy.flag & BIT(idx))) { + wland_user_data.phy.reg_val[idx][0] = reg32; + wland_user_data.phy.reg_val[idx][1] = *((u32 *)value); + wland_user_data.phy.flag |= BIT(idx); + break; + } else { + continue; + } + } + } + break; + case RDA5991H_USER_DATA_FLAG_PHY_CHANNELS: + if (wland_user_data.phy_channels.valid != 1) { + wland_user_data.phy_channels.valid = 1; + wland_user_data.phy_channels.flag = 0; + } + + reg32 = *((u32 *)reg); + if (wland_user_data.phy_channels.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.phy_channels.flag & BIT(idx)) && + (wland_user_data.phy_channels.reg_val[idx][0] == reg32)) { + memcpy(&wland_user_data.phy_channels.reg_val[idx][1], value, 14 * sizeof(u32)); + break; + } else { + continue; + } + } + if ((8 == idx) && (0xFF == wland_user_data.phy_channels.flag)) { + return -2; + } + } + + if ((8 == idx) || (0 == wland_user_data.phy_channels.flag)) { + for (idx = 0; idx < 8; idx++) { + if (!(wland_user_data.phy_channels.flag & BIT(idx))) { + wland_user_data.phy_channels.reg_val[idx][0] = reg32; + memcpy(&wland_user_data.phy_channels.reg_val[idx][1], value, 14 * sizeof(u32)); + wland_user_data.phy_channels.flag |= BIT(idx); + break; + } else { + continue; + } + } + } + break; + default: + WLAND_DBG(ERROR, "Unknown flag:0x%08x\n", flag); + return -3; + } + + rda5981_erase_flash(user_data_location, sizeof(wland_user_data)); + return rda5981_write_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data)); +} + +int rda5981_erase_user_data_regs(u8 *reg, u32 flag) +{ + u16 reg16 = 0; + u32 reg32 = 0; + u8 idx = 0; + + if (!read_flag) { + if (0 == rda5981_read_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data))) { + read_flag = 1; + } else { + return -1; + } + } + + if (wland_user_data.flag & RDA5991H_USER_DATA_FLAG_UNINITIALIZED) {//flash init is 0xffffffff + return -1; + } + if ((wland_user_data.flag & flag) == 0) { + return 0; + } + switch (flag) { + case RDA5991H_USER_DATA_FLAG_RF: + if (wland_user_data.rf.valid != 1) { + return 0; + } + + reg16 = *((u16 *)reg); + if (wland_user_data.rf.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.rf.flag & BIT(idx)) && + (wland_user_data.rf.reg_val[idx][0] == reg16)) { + memset(&wland_user_data.rf.reg_val[idx][0], 0xFF, 2 * sizeof(u16)); + wland_user_data.rf.flag &= ~BIT(idx); + break; + } else { + continue; + } + } + } + + if (0 == wland_user_data.rf.flag) { + wland_user_data.rf.valid = 0xFFFFFFFF; + wland_user_data.rf.flag = 0xFFFFFFFF; + wland_user_data.flag &= (~flag); + } + + break; + case RDA5991H_USER_DATA_FLAG_RF_CHANNELS: + if (wland_user_data.rf_channels.valid != 1) { + return 0; + } + + reg16 = *((u16 *)reg); + if (wland_user_data.rf_channels.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.rf_channels.flag & BIT(idx)) && + (wland_user_data.rf_channels.reg_val[idx][0] == reg16)) { + memset(&wland_user_data.rf_channels.reg_val[idx][0], 0xFF, 15 * sizeof(u16)); + wland_user_data.rf_channels.flag &= ~BIT(idx); + break; + } else { + continue; + } + } + } + + if (0 == wland_user_data.rf_channels.flag) { + wland_user_data.rf_channels.valid = 0xFFFFFFFF; + wland_user_data.rf_channels.flag = 0xFFFFFFFF; + wland_user_data.flag &= (~flag); + } + + break; + case RDA5991H_USER_DATA_FLAG_PHY: + if (wland_user_data.phy.valid != 1) { + return 0; + } + + reg32 = *((u32 *)reg); + if (wland_user_data.phy.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.phy.flag & BIT(idx)) && + (wland_user_data.phy.reg_val[idx][0] == reg32)) { + memset(&wland_user_data.phy.reg_val[idx][0], 0xFF, 2 * sizeof(u32)); + wland_user_data.phy.flag &= ~BIT(idx); + break; + } else { + continue; + } + } + } + + if (0 == wland_user_data.phy.flag) { + wland_user_data.phy.valid = 0xFFFFFFFF; + wland_user_data.phy.flag = 0xFFFFFFFF; + wland_user_data.flag &= (~flag); + } + + break; + case RDA5991H_USER_DATA_FLAG_PHY_CHANNELS: + if (wland_user_data.phy_channels.valid != 1) { + return 0; + } + + reg32 = *((u32 *)reg); + if (wland_user_data.phy_channels.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.phy_channels.flag & BIT(idx)) && + (wland_user_data.phy_channels.reg_val[idx][0] == reg32)) { + memset(&wland_user_data.phy_channels.reg_val[idx][0], 0xFF, 15 * sizeof(u32)); + wland_user_data.phy_channels.flag &= ~BIT(idx); + break; + } else { + continue; + } + } + } + + if (0 == wland_user_data.phy_channels.flag) { + wland_user_data.phy_channels.valid = 0xFFFFFFFF; + wland_user_data.phy_channels.flag = 0xFFFFFFFF; + wland_user_data.flag &= (~flag); + } + + break; + default: + WLAND_DBG(ERROR, "Unknown flag:0x%08x\n", flag); + return -3; + } + + rda5981_erase_flash(user_data_location, sizeof(wland_user_data)); + return rda5981_write_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data)); +} + + +int rda5981_read_user_data_regs(u8 *reg, u8 *value, u32 flag) +{ + u16 reg16 = 0; + u32 reg32 = 0; + u8 idx = 0; + + if (!read_flag) { + if(0 == rda5981_read_flash(user_data_location, + (char *)(&wland_user_data), sizeof(wland_user_data))) { + read_flag = 1; + } else { + return -1; + } + } + + if (wland_user_data.flag & RDA5991H_USER_DATA_FLAG_UNINITIALIZED) {//flash init is 0xffffffff + return -1; + } + if (strcmp((const char *)(wland_user_data.rda5981_flag), RDA5981_FLAG_FLAG)) { + return -2; + } + if ((wland_user_data.flag & flag) == 0) { + return -3; + } + switch (flag) { + case RDA5991H_USER_DATA_FLAG_RF: + if (wland_user_data.rf.valid != 1) { + return -4; + } + + reg16 = *((u16 *)reg); + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.rf.flag & BIT(idx)) && + (wland_user_data.rf.reg_val[idx][0] == reg16)) { + memcpy(value, &wland_user_data.rf.reg_val[idx][1], sizeof(u16)); + break; + } else { + continue; + } + } + + if (8 == idx) { + return -4; + } + break; + case RDA5991H_USER_DATA_FLAG_RF_CHANNELS: + if (wland_user_data.rf_channels.valid != 1) { + return -4; + } + + reg16 = *((u16 *)reg); + if (wland_user_data.rf_channels.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.rf_channels.flag & BIT(idx)) && + (wland_user_data.rf_channels.reg_val[idx][0] == reg16)) { + memcpy(value, &wland_user_data.rf_channels.reg_val[idx][1], 14 * sizeof(u16)); + break; + } else { + continue; + } + } + } + + if (8 == idx) { + return -4; + } + break; + case RDA5991H_USER_DATA_FLAG_PHY: + if (wland_user_data.phy.valid != 1) { + return -4; + } + + reg32 = *((u32 *)reg); + if (wland_user_data.phy.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.phy.flag & BIT(idx)) && + (wland_user_data.phy.reg_val[idx][0] == reg32)) { + memcpy(value, &wland_user_data.phy.reg_val[idx][1], sizeof(u32)); + break; + } else { + continue; + } + } + } + + if (8 == idx) { + return -4; + } + break; + case RDA5991H_USER_DATA_FLAG_PHY_CHANNELS: + if (wland_user_data.phy_channels.valid != 1) { + return -4; + } + + reg32 = *((u32 *)reg); + if (wland_user_data.phy_channels.flag != 0) { + for (idx = 0; idx < 8; idx++) { + if ((wland_user_data.phy_channels.flag & BIT(idx)) && + (wland_user_data.phy_channels.reg_val[idx][0] == reg32)) { + memcpy(value, &wland_user_data.phy_channels.reg_val[idx][1], 14 * sizeof(u32)); + break; + } else { + continue; + } + } + } + + if (8 == idx) { + return -4; + } + break; + default: + WLAND_DBG(ERROR, "Unknown flag:0x%08x\n", flag); + return -3; + } + + return 0; +} + +int rda5981_flash_get_mid(u8 *mid) +{ + *mid = 0xC8; + + return 0; +} + +int rda5981_flash_get_did(u8 *did) +{ + *did = 0x13; + + return 0; +} + +int rda5981_flash_get_jdid(u16 *jdid) +{ + *jdid = 0x4014; + + return 0; +} + +int rda5981_read_default_config(char *buf, u32 len, u32 flag) +{ + int ret = 0; + u32 addr; + u32 addr_offset = 0; + char *temp_buf = NULL, *temp_buf_aligned; + + switch (flag) { + case RDA5981_VBAT_CAL: + addr = 0x18000088; + break; + case RDA5981_GPADC0_CAL: + case RDA5981_GPADC1_CAL: + addr = 0x1800008C; + break; + case RDA5981_PRODUCT_ID: + addr = 0x18000084; + break; + case RDA5981_POWER_CLASS: + addr = 0x18000085; + break; + default: + WLAND_DBG(ERROR, "Unknown flag\n"); + return -1; + } + + addr_offset = addr % 4; + addr = (addr - addr_offset) & (flash_size -1); + + if (((u32)buf % 4) || (addr_offset != 0)) { + temp_buf = (char *)malloc(addr_offset + len + 4); + if (temp_buf == NULL) { + ret = -1; + goto out; + } + if ((u32)temp_buf % 4) { + temp_buf_aligned = temp_buf + (4 - (u32)temp_buf % 4); + } else { + temp_buf_aligned = temp_buf; + } + } else { + temp_buf_aligned = buf; + } + + core_util_critical_section_enter(); + spi_flash_flush_cache(); + SPI_FLASH_READ_DATA_FOR_MBED((void *)addr, temp_buf_aligned, (len + addr_offset)); + core_util_critical_section_exit(); + + if (temp_buf_aligned != buf) { + memcpy(buf, temp_buf_aligned + addr_offset, len); + } +out: + if (temp_buf) { + free(temp_buf); + } + return ret; +} + +int rda5981_flash_read_vbat_cal(float *k, float *b) +{ + int ret = 0; + u32 value = 0; + u32 x1 = 0;//y1 3.0f + u32 x2 = 0;//y2 4.2f + float k_tmp = 0; + float b_tmp = 0; + + ret = rda5981_read_default_config((char *)&value, 4, RDA5981_VBAT_CAL); + + if (ret < 0) { + WLAND_DBG(ERROR, "read vbat_cal form flash fail\n"); + return -1; + } + if ((0 == (value & 0xFFFFFUL)) || (0xFFFFFUL == (value & 0xFFFFFUL))) { + WLAND_DBG(ERROR, "invalid vbat_cal:0x%08x\n", value); + return -1; + } else { + x1 = value & 0x3FFUL; + x2 = (value >> 10) & 0x3FFUL; + } + + if (x1 == x2) { + return -1; + } + + k_tmp = (4.2f - 3.0f) / (float)(x2 - x1); + b_tmp = 4.2f - k_tmp * x2; + + *k = k_tmp; + *b = b_tmp; + + return ret; +} diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash_wp.c b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash_wp.c new file mode 100644 index 0000000000..6ff0181640 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_flash_wp.c @@ -0,0 +1,366 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_interface.h" +#include "wland_flash.h" + +//#define FLASH_PROTECT_ENABLE + +#define FLASH_CTL_REG_BASE 0x17fff000 +#define FLASH_CTL_TX_CMD_ADDR_REG (FLASH_CTL_REG_BASE + 0x00) +#define FLASH_CTL_TX_BLOCK_SIZE_REG (FLASH_CTL_REG_BASE + 0x04) +#define FLAHS_CTL_TX_FIFO_DATA_REG (FLASH_CTL_REG_BASE + 0x08) +#define FLASH_CTL_STATUS_REG (FLASH_CTL_REG_BASE + 0x0c) +#define FLAHS_CTL_RX_FIFO_DATA_REG (FLASH_CTL_REG_BASE + 0x10) + +#define WRITE_REG32(REG, VAL) ((*(volatile unsigned int*)(REG)) = (unsigned int)(VAL)) +#define WRITE_REG8(REG, VAL) ((*(volatile unsigned char*)(REG)) = (unsigned char)(VAL)) +#define MREAD_WORD(addr) *((volatile unsigned int *)(addr)) + +#define MID_GD 0xC8 +#define MID_WINBOND 0xEF + +#define FLASH_1M 0x100000 +#define FLASH_2M 0x200000 +#define FLASH_4M 0x400000 +extern unsigned int flash_size; + +#ifdef FLASH_PROTECT_ENABLE + +#define FLASH_WP_MASK 0x407c +#define FLASH_WP_NONE 0x0000 +#define FLASH_WP_ALL 0x1c + +#define FLASH_4M_WP_4K 0x0064 +#define FLASH_4M_WP_8K 0x0068 +#define FLASH_4M_WP_16K 0x006c +#define FLASH_4M_WP_32K 0x0070 +#define FLASH_4M_WP_1_64 0x0024 +#define FLASH_4M_WP_1_32 0x0028 +#define FLASH_4M_WP_1_16 0x002c +#define FLASH_4M_WP_1_8 0x0030 +#define FLASH_4M_WP_1_4 0x0034 +#define FLASH_4M_WP_1_2 0x0038 +#define FLASH_4M_WP_3_4 0x4014 +#define FLASH_4M_WP_7_8 0x4010 +#define FLASH_4M_WP_15_16 0x400c +#define FLASH_4M_WP_31_32 0x4008 +#define FLASH_4M_WP_63_64 0x4004 +#define FLASH_4M_WP_127_128 0x4058 +#define FLASH_4M_WP_255_256 0x404C +#define FLASH_4M_WP_1023_1024 0x4044 + +#define FLASH_2M_WP_4K 0x0064 +#define FLASH_2M_WP_8K 0x0068 +#define FLASH_2M_WP_16K 0x006c +#define FLASH_2M_WP_32K 0x0070 +#define FLASH_2M_WP_1_32 0x0024 +#define FLASH_2M_WP_1_16 0x0028 +#define FLASH_2M_WP_1_8 0x002c +#define FLASH_2M_WP_1_4 0x0050 +#define FLASH_2M_WP_1_2 0x0051 +#define FLASH_2M_WP_3_4 0x4010 +#define FLASH_2M_WP_7_8 0x400c +#define FLASH_2M_WP_15_16 0x4004 +#define FLASH_2M_WP_31_32 0x4000 +#define FLASH_2M_WP_63_64 0x4050 +#define FLASH_2M_WP_127_128 0x404c +#define FLASH_2M_WP_255_256 0x4048 +#define FLASH_2M_WP_511_512 0x4044 + + +#define FLASH_1M_WP_4K 0x0064 +#define FLASH_1M_WP_8K 0x0068 +#define FLASH_1M_WP_16K 0x006c +#define FLASH_1M_WP_32K 0x0070 +#define FLASH_1M_WP_1_16 0x0024 +#define FLASH_1M_WP_1_8 0x0028 +#define FLASH_1M_WP_1_4 0x002c +#define FLASH_1M_WP_1_2 0x0050 +#define FLASH_1M_WP_3_4 0x400C +#define FLASH_1M_WP_7_8 0x4008 +#define FLASH_1M_WP_15_16 0x4004 +#define FLASH_1M_WP_31_32 0x4050 +#define FLASH_1M_WP_63_64 0x404C +#define FLASH_1M_WP_127_128 0x4048 +#define FLASH_1M_WP_255_256 0x4044 + +static unsigned short flash_wrtie_protect_4M(unsigned short status, unsigned int offset) +{ + unsigned int wp = FLASH_WP_NONE; + if (offset >= flash_size - flash_size/1024) { + wp = FLASH_4M_WP_1023_1024; + } else if(offset >= flash_size - flash_size/256) { + wp = FLASH_4M_WP_255_256; + } else if(offset >= flash_size - flash_size/128) { + wp = FLASH_4M_WP_127_128; + } else if(offset >= flash_size - flash_size/64) { + wp = FLASH_4M_WP_63_64; + } else if(offset >= flash_size - flash_size/32) { + wp = FLASH_4M_WP_31_32; + } else if(offset >= flash_size - flash_size/16) { + wp = FLASH_4M_WP_15_16; + } else if(offset >= flash_size - flash_size/8) { + wp = FLASH_4M_WP_7_8; + } else if(offset >= flash_size - flash_size/4) { + wp = FLASH_4M_WP_3_4; + } else if(offset >= flash_size/2) { + wp = FLASH_4M_WP_1_2; + } else if(offset >= flash_size/4) { + wp = FLASH_4M_WP_1_4; + } else if(offset >= flash_size/8) { + wp = FLASH_4M_WP_1_8; + } else if(offset >= flash_size/16) { + wp = FLASH_4M_WP_1_16; + } else if(offset >= flash_size/32) { + wp = FLASH_4M_WP_1_32; + } else if(offset >= flash_size/64) { + wp = FLASH_4M_WP_1_64; + } else if(offset >= 32 * 1024) { + wp = FLASH_4M_WP_32K; + } else if(offset >= 16 * 1024) { + wp = FLASH_4M_WP_16K; + } else if(offset >= 8 * 1024) { + wp = FLASH_4M_WP_8K; + } else if(offset >= 4 * 1024) { + wp = FLASH_4M_WP_4K; + } + + return (status & ~FLASH_WP_MASK) | wp; + +} + +static unsigned short flash_wrtie_protect_2M(unsigned short status, unsigned int offset) +{ + unsigned int wp = FLASH_WP_NONE; + if (offset >= flash_size - flash_size/256) { + wp = FLASH_2M_WP_255_256; + } else if(offset >= flash_size - flash_size/128) { + wp = FLASH_2M_WP_127_128; + } else if(offset >= flash_size - flash_size/64) { + wp = FLASH_2M_WP_63_64; + } else if(offset >= flash_size - flash_size/32) { + wp = FLASH_2M_WP_31_32; + } else if(offset >= flash_size - flash_size/16) { + wp = FLASH_2M_WP_15_16; + } else if(offset >= flash_size - flash_size/8) { + wp = FLASH_2M_WP_7_8; + } else if(offset >= flash_size - flash_size/4) { + wp = FLASH_2M_WP_3_4; + } else if(offset >= flash_size/2) { + wp = FLASH_2M_WP_1_2; + } else if(offset >= flash_size/4) { + wp = FLASH_2M_WP_1_4; + } else if(offset >= flash_size/8) { + wp = FLASH_2M_WP_1_8; + } else if(offset >= flash_size/16) { + wp = FLASH_2M_WP_1_16; + } else if(offset >= flash_size/32) { + wp = FLASH_2M_WP_1_32; + } else if(offset >= 32 * 1024) { + wp = FLASH_2M_WP_32K; + } else if(offset >= 16 * 1024) { + wp = FLASH_2M_WP_16K; + } else if(offset >= 8 * 1024) { + wp = FLASH_2M_WP_8K; + } else if(offset >= 4 * 1024) { + wp = FLASH_2M_WP_4K; + } + + return (status & ~FLASH_WP_MASK) | wp; + +} + +static unsigned short flash_wrtie_protect_1M(unsigned short status, unsigned int offset) +{ + unsigned int wp = FLASH_WP_NONE; + + if (offset >= flash_size - flash_size/256) { + wp = FLASH_1M_WP_255_256; + } else if(offset >= flash_size - flash_size/128) { + wp = FLASH_1M_WP_127_128; + } else if(offset >= flash_size - flash_size/64) { + wp = FLASH_1M_WP_63_64; + } else if(offset >= flash_size - flash_size/32) { + wp = FLASH_1M_WP_31_32; + } else if(offset >= flash_size - flash_size/16) { + wp = FLASH_1M_WP_15_16; + } else if(offset >= flash_size - flash_size/8) { + wp = FLASH_1M_WP_7_8; + } else if(offset >= flash_size - flash_size/4) { + wp = FLASH_1M_WP_3_4; + } else if(offset >= flash_size/2) { + wp = FLASH_1M_WP_1_2; + } else if(offset >= flash_size/4) { + wp = FLASH_1M_WP_1_4; + } else if(offset >= flash_size/8) { + wp = FLASH_1M_WP_1_8; + } else if(offset >= flash_size/16) { + wp = FLASH_1M_WP_1_16; + } else if(offset >= 32 * 1024) { + wp = FLASH_1M_WP_32K; + } else if(offset >= 16 * 1024) { + wp = FLASH_1M_WP_16K; + } else if(offset >= 8 * 1024) { + wp = FLASH_1M_WP_8K; + } else if(offset >= 4 * 1024) { + wp = FLASH_1M_WP_4K; + } + + return (status & ~FLASH_WP_MASK) | wp; + +} + +void flash_wrtie_protect_all() +{ + unsigned short status; + unsigned char r1, r2; + core_util_critical_section_enter(); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x05); + wait_busy_down(); + r1 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x35); + wait_busy_down(); + r2 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + //mbed_error_printf("status %x %x\r\n", r2, r1); + + status = (r2 << 8) | r1; + status = (status & ~FLASH_WP_MASK) | FLASH_WP_ALL; + //mbed_error_printf("status %04x\r\n", status); + + spi_write_reset(); + wait_busy_down(); + WRITE_REG8(FLAHS_CTL_TX_FIFO_DATA_REG, (status&0xff)); + WRITE_REG8(FLAHS_CTL_TX_FIFO_DATA_REG, ((status>>8)&0xff)); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x01); + wait_busy_down(); + spi_wip_reset(); + core_util_critical_section_exit(); + return; +} + +void flash_wrtie_protect_none() +{ + unsigned short status; + unsigned char r1, r2; + core_util_critical_section_enter(); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x05); + wait_busy_down(); + r1 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x35); + wait_busy_down(); + r2 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + //mbed_error_printf("status %x %x\r\n", r2, r1); + + status = (r2 << 8) | r1; + status = status & ~FLASH_WP_MASK; + //mbed_error_printf("status %04x\r\n", status); + + spi_write_reset(); + wait_busy_down(); + WRITE_REG8(FLAHS_CTL_TX_FIFO_DATA_REG, (status&0xff)); + WRITE_REG8(FLAHS_CTL_TX_FIFO_DATA_REG, ((status>>8)&0xff)); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x01); + wait_busy_down(); + spi_wip_reset(); + core_util_critical_section_exit(); + return; +} + +void flash_wrtie_protect(unsigned int offset) +{ + unsigned short status; + unsigned char r1, r2; + core_util_critical_section_enter(); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x05); + wait_busy_down(); + r1 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x35); + wait_busy_down(); + r2 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + //mbed_error_printf("status %x %x\r\n", r2, r1); + + status = (r2 << 8) | r1; + if (flash_size == FLASH_4M) { + status = flash_wrtie_protect_4M(status, offset); + } else if(flash_size == FLASH_2M) { + status = flash_wrtie_protect_2M(status, offset); + } else if(flash_size == FLASH_1M) { + status = flash_wrtie_protect_1M(status, offset); + } else [ + LWIP_DEBUGF(NETIF_DEBUG,"flash_size is error\r\n"); + } + //mbed_error_printf("status %04x\r\n", status); + + spi_write_reset(); + wait_busy_down(); + WRITE_REG8(FLAHS_CTL_TX_FIFO_DATA_REG, (status&0xff)); + WRITE_REG8(FLAHS_CTL_TX_FIFO_DATA_REG, ((status>>8)&0xff)); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x01); + wait_busy_down(); + spi_wip_reset(); + core_util_critical_section_exit(); + return; +} +#else +void flash_wrtie_protect_all() +{ + return; +} + +void flash_wrtie_protect_none() +{ + return; +} + +void flash_wrtie_protect(unsigned int offset) +{ + return; +} + +#endif +void rda5981_flash_init() +{ + unsigned int status3, status4, status5; + core_util_critical_section_enter(); + WRITE_REG32(FLASH_CTL_TX_BLOCK_SIZE_REG, 3<<8); + status3 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + status4 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + status5 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + + wait_busy_down(); + spi_wip_reset(); + WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, 0x9F); + wait_busy_down(); + //WRITE_REG32(FLASH_CTL_TX_BLOCK_SIZE_REG, 3<<8); + //wait_busy_down(); + status3 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + status4 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + status5 = MREAD_WORD(FLAHS_CTL_RX_FIFO_DATA_REG); + core_util_critical_section_exit(); + + if ((status5&0xff != 0x14) && (status5&0xff != 0x15) && (status5&0xff != 0x16)) { + mbed_error_printf("flash size error\r\n"); + return; + } + flash_size = (1 << (status5&0xff)); + flash_wrtie_protect_all(); + + return; +} diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_ota.c b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_ota.c new file mode 100644 index 0000000000..05a85abc0a --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/lwip-wifi/arch/TARGET_RDA/TARGET_UNO_91H/src/wland_ota.c @@ -0,0 +1,145 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "wland_ota.h" +#include "wland_flash.h" +#include "rda5981_ota.h" +#include "wland_dbg.h" +#include "wland_types.h" +#include "critical.h" +#include +#include + +#define IMAGE_MAGIC 0xAEAE + +u32 wland_ota_partition_addr = 0; +u32 wland_ota_partition_len = 0; +u32 wland_crc_result = ~0UL; + +static u32 crc32(const u8 *p, u32 len, u32 crc) +{ + const u32 *crc32_tab = (const u32 *)CRC32_TABLE_ADDR; + + if (rda_ccfg_hwver() >= 4) { + crc32_tab = (const u32 *)CRC32_TABLE_ADDR_4; + } + /* Calculate CRC */ + while(len--) { + crc = crc32_tab[((crc & 0xFF) ^ *p++)] ^ (crc >> 8); + } + + return crc; +} + +static int rda5981_ota_erase_flash(u32 addr, u32 len) +{ + addr &= (flash_size -1); + rda5981_spi_erase_partition((void *)addr, len); + return 0; +} +//write without erase +static int rda5981_ota_write_flash(u32 addr, char *buf, u32 len) +{ + int ret = 0; + u8 *temp_buf = NULL, *temp_buf_aligned; + + addr &= (flash_size -1); + if ((u32)buf % 4) { + temp_buf = malloc(len + 3); + if (temp_buf == NULL) { + goto out; + } + if ((u32)temp_buf % 4) { + temp_buf_aligned = temp_buf + (4-(u32)temp_buf%4); + } else { + temp_buf_aligned = temp_buf; + } + memcpy(temp_buf_aligned, (unsigned char *)buf, len); + } else { + temp_buf_aligned = (u8 *)buf; + } + core_util_critical_section_enter(); + RDA5991H_WRITE_FLASH(addr, temp_buf_aligned, len); + core_util_critical_section_exit(); + +out: + if (temp_buf) { + free(temp_buf); + } + return ret; +} + +int rda5981_write_partition_start(u32 addr, u32 img_len) +{ + if (addr < 0x18001000 || addr+img_len>0x18000000+flash_size) { + WLAND_DBG(ERROR,"write partition start addr error. (0x%08x, %u)\r\n", addr, img_len); + return -1; + } + if (addr%0x1000 || img_len%0x1000) { + WLAND_DBG(ERROR,"write partition start length error.(mast be 4k alignment) (0x%08x, %u)\r\n", addr, img_len); + return -1; + } + + WLAND_DBG(INFO, "rda5981_write_partition_start:0x%08x, %u\r\n", addr, img_len); + wland_ota_partition_addr = addr; + wland_ota_partition_len = img_len; + wland_crc_result = ~0U; + + rda5981_ota_erase_flash(addr, img_len); + return 0; +} +int rda5981_write_partition(u32 offset, const u8 *buf, u32 len) +{ + if (wland_ota_partition_addr==0 || offset+len>wland_ota_partition_len) { + WLAND_DBG(ERROR,"write partition error. out of start addr(0x%08x, %u). (0x%08x, %u)\r\n", + wland_ota_partition_addr, wland_ota_partition_len, offset, len); + return -1; + } + if (len%0x400) { + WLAND_DBG(ERROR,"write partition length error.(mast be 1k alignment) (0x%08x, %u)\r\n", offset, len); + return -1; + } + WLAND_DBG(DEBUG, "rda5981_write_partition:0x%08x, %u.(%02x)\r\n", + wland_ota_partition_addr + offset, len, buf[0]); + wland_crc_result = crc32(buf, len, wland_crc_result); + + WLAND_DBG(DEBUG, "rda5981_write_partition: wland_crc_result 0x%08x\r\n", + wland_crc_result); + return rda5981_ota_write_flash(wland_ota_partition_addr + offset, (char *)buf, len); + //return rda5981_write_flash(wland_ota_partition_addr + offset, buf, len); +} +int rda5981_write_partition_end(void) +{ + WLAND_DBG(INFO, "check crc32:0x%08x, %u\r\n", wland_ota_partition_addr, wland_ota_partition_len); + if (wland_ota_partition_addr == 0) { + WLAND_DBG(ERROR,"OTA is not started\r\n"); + return -1; + } + core_util_critical_section_enter(); + spi_flash_flush_cache(); + //u32 crc32_check = crc32(wland_ota_partition_addr, wland_ota_partition_len, ~0U); + u32 crc32_check = bootrom_crc32((unsigned char *)wland_ota_partition_addr, wland_ota_partition_len); + core_util_critical_section_exit(); + WLAND_DBG(INFO, "rda5981_write_partition_end:0x%08x:0x%08x\r\n", wland_crc_result, crc32_check); + wland_ota_partition_addr = 0UL; + + if (crc32_check == wland_crc_result) { + return 0; + } else { + WLAND_DBG(ERROR,"check crc32 error\r\n"); + return -1; + } +} diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.cpp b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.cpp new file mode 100644 index 0000000000..9305f0daeb --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.cpp @@ -0,0 +1,293 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "cmsis_os.h" +#include "mbed_interface.h" +#include "mbed_assert.h" +#include "mbed_shared_queues.h" +#include "netsocket/nsapi_types.h" +#include "lwip/arch.h" +#include "lwip/pbuf.h" +#include "rda5991h_wland.h" +#include "rda5981x_emac_config.h" +#include "rda5981x_emac.h" +#include "rda_sys_wrapper.h" +#include "maclib_task.h" + +#define RDA_HWADDR_SIZE (6) +#define RDA_ETH_MTU_SIZE 1500 +#define RDA_ETH_IF_NAME "st" + +#define RX_PRIORITY (osPriorityNormal) +#define TX_PRIORITY (osPriorityNormal) +#define PHY_PRIORITY (osPriorityNormal) + +extern void *packet_rx_queue; + +RDA5981x_EMAC::RDA5981x_EMAC() +{ +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the memory buffer chain that is passed to the function. + * + * @param buf the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return true if the packet could be sent + * false value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become availale since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ +bool RDA5981x_EMAC::link_out(emac_mem_buf_t *buf) +{ + emac_mem_buf_t *q, *p = buf; + + u32_t actual_txlen = 0; + u8_t **data = NULL; + u16_t retry = 400; + + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_output enter, p:%08x\n", p)); + + while ((data == NULL) && (retry-- > 0)) { + data = (u8_t**)wland_get_databuf(); + osThreadYield(); + } + if (data == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("rda91h_low_level_output, no PKT buf\r\n")); + memory_manager->free(buf); + return false; + } + + for (q = p; q != NULL; q = memory_manager->get_next(q)) { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + memcpy(&((*data)[actual_txlen+2]), memory_manager->get_ptr(q), memory_manager->get_len(q));//reserve wid header length + actual_txlen += memory_manager->get_len(q); + if (actual_txlen > 1514 || actual_txlen > memory_manager->get_total_len(p)) { + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_output err, actual_txlen:%d, tot_len%d\n", actual_txlen, memory_manager->get_total_len(p))); + memory_manager->free(buf); + return false; + } + } + + /* Signal rda5996 that packet should be sent */ + if (actual_txlen == memory_manager->get_total_len(p)) { + wland_txip_data((void*)data, actual_txlen, 0); + memory_manager->free(buf); + return true; + } + + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_output pkt len mismatch, actual_txlen:%d, tot_len%d\n", + actual_txlen, memory_manager->get_total_len(p))); + + memory_manager->free(buf); + return false; +} + +/** + * Should allocate a contiguous memory buffer and transfer the bytes of the incoming + * packet to the buffer. + * + * @param buf If a frame was received and the memory buffer allocation was successful, a memory + * buffer filled with the received packet (including MAC header) + * @return negative value when no more frames, + * zero when frame is received + */ +emac_mem_buf_t * RDA5981x_EMAC::low_level_input(u8_t *data, int len) +{ + emac_mem_buf_t *p, *q; + u16_t index = 0; + + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input enter, rxlen:%d\n", len)); + + /* Obtain the size of the packet and put it into the "len" + variable. */ + if (!len) { + return NULL; + } + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = memory_manager->alloc_pool(len, 0); + if (p != NULL) { + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for (q = p; q != NULL; q = memory_manager->get_next(q)) { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. + * This does not necessarily have to be a memcpy, you can also preallocate + * pbufs for a DMA-enabled MAC and after receiving truncate it to the + * actually received size. In this case, ensure the tot_len member of the + * pbuf is the sum of the chained pbuf len members. + */ + /* load rx data from 96 to local mem_pool */ + memcpy(memory_manager->get_ptr(q), &data[index], memory_manager->get_len(q)); + index += memory_manager->get_len(q); + + if (index >= len) { + break; + } + } + + } else { + /* Drop this packet */ + LWIP_DEBUGF(NETIF_DEBUG, ("low_level_input pbuf_alloc fail, rxlen:%d\n", len)); + + return NULL; + } + return p; +} + + +/** \brief Attempt to read a packet from the EMAC interface. + * + */ +void RDA5981x_EMAC::packet_rx() +{ + rda_msg msg; + packet_rx_queue = rda_mail_create(10, sizeof(unsigned int)*4); + /* move received packet into a new buf */ + while (1) { + emac_mem_buf_t *p = NULL; + rda_mail_get(packet_rx_queue, (void*)&msg, osWaitForever); + switch(msg.type) { + case 0: + p = low_level_input((unsigned char*)msg.arg1, msg.arg2); + if (p == NULL) { + rda_sem_release((void*)msg.arg3); + break; + } + rda_sem_release((void*)msg.arg3); + if (p) { + emac_link_input_cb(p); + } + break; + case 1: + emac_link_state_cb(msg.arg1); + break; + default: + break; + } + } +} + +void RDA5981x_EMAC::thread_function(void *pvParameters) +{ + static struct RDA5981x_EMAC *rda5981x_enet = static_cast(pvParameters); + rda5981x_enet->packet_rx(); +} + +bool RDA5981x_EMAC::power_up() +{ + /* Initialize the hardware */ + static int init_flag = 0; + if (init_flag == 0) { + wland_reg_func(); + rda_thread_new("maclib_thread", maclib_task, NULL, DEFAULT_THREAD_STACKSIZE*8, PHY_PRIORITY); + rda_thread_new("wland_thread", wland_task, NULL, DEFAULT_THREAD_STACKSIZE*5, PHY_PRIORITY); + rda_thread_new("packet_rx", RDA5981x_EMAC::thread_function, this, DEFAULT_THREAD_STACKSIZE*5, PHY_PRIORITY); + /* Allow the PHY task to detect the initial link state and set up the proper flags */ + osDelay(100); + wland_sta_init(); + init_flag = 1; + } + + return true; +} + +uint32_t RDA5981x_EMAC::get_mtu_size() const +{ + return RDA_ETH_MTU_SIZE; +} + +uint32_t RDA5981x_EMAC::get_align_preference() const +{ + return 0; +} + +void RDA5981x_EMAC::get_ifname(char *name, uint8_t size) const +{ + memcpy(name, RDA_ETH_IF_NAME, (size < sizeof(RDA_ETH_IF_NAME)) ? size : sizeof(RDA_ETH_IF_NAME)); +} + +uint8_t RDA5981x_EMAC::get_hwaddr_size() const +{ + return RDA_HWADDR_SIZE; +} + +bool RDA5981x_EMAC::get_hwaddr(uint8_t *addr) const +{ + mbed_mac_address((char *)addr); + return true; +} + +void RDA5981x_EMAC::set_hwaddr(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +void RDA5981x_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + emac_link_input_cb = input_cb; +} + +void RDA5981x_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + emac_link_state_cb = state_cb; +} + +void RDA5981x_EMAC::add_multicast_group(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +void RDA5981x_EMAC::remove_multicast_group(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +void RDA5981x_EMAC::set_all_multicast(bool all) +{ + /* No-op at this stage */ +} + +void RDA5981x_EMAC::power_down() +{ + /* No-op at this stage */ +} + +void RDA5981x_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + memory_manager = &mem_mngr; +} + +RDA5981x_EMAC &RDA5981x_EMAC::get_instance() +{ + static RDA5981x_EMAC emac; + return emac; +} + +// Weak so a module can override +MBED_WEAK EMAC &EMAC::get_default_instance() +{ + return RDA5981x_EMAC::get_instance(); +} + diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.h new file mode 100644 index 0000000000..62fda7374d --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac.h @@ -0,0 +1,161 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef STM32_EMAC_H_ +#define STM32_EMAC_H_ + +#include "EMAC.h" +#include "rtos/Semaphore.h" +#include "rtos/Mutex.h" + +class RDA5981x_EMAC : public EMAC { +public: + RDA5981x_EMAC(); + + static RDA5981x_EMAC &get_instance(); + + /** + * Return maximum transmission unit + * + * @return MTU in bytes + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets memory buffer alignment preference + * + * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not + * align link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes + */ + virtual uint32_t get_align_preference() const; + + /** + * Return interface name + * + * @param name Pointer to where the name should be written + * @param size Maximum number of character to copy + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Return interface-supplied HW address + * + * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size + * + * HW address need not be provided if this interface does not have its own HW + * address configuration; stack will choose address from central system + * configuration if the function returns false and does not write to addr. + * + * @param addr HW address for underlying interface + * @return true if HW address is available + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for interface + * + * Provided address has to be of correct size, see @a get_hwaddr_size + * + * Called to set the MAC address to actually use - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden, eg for test + * purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success, False in case of an error. + */ + virtual bool power_up(); + + /** + * Deinitializes the HW + * + */ + virtual void power_down(); + + /** + * Sets a callback that needs to be called for packets received for that interface + * + * @param input_cb Function to be register as a callback + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that needs to be called on link status changes for given interface + * + * @param state_cb Function to be register as a callback + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Add device to a multicast group + * + * @param address A multicast group hardware address + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Remove device from a multicast group + * + * @param address A multicast group hardware address + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Request reception of all multicast packets + * + * @param all True to receive all multicasts + * False to receive only multicasts addressed to specified groups + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager that is used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + +private: + void packet_rx(); + emac_mem_buf_t * low_level_input(u8_t *data, int len); + static void thread_function(void *pvParameters); + emac_link_input_cb_t emac_link_input_cb; /**< Callback for incoming data */ + emac_link_state_change_cb_t emac_link_state_cb; /**< Link state change callback */ + EMACMemoryManager *memory_manager; /**< Memory manager */ + +}; + +#endif /* K64F_EMAC_H_ */ diff --git a/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac_config.h b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac_config.h new file mode 100644 index 0000000000..717d423bfe --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RDA_EMAC/rda5981x_emac_config.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2019 Unisoc Communications Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef STM32XX_EMAC_CONFIG_H__ +#define STM32XX_EMAC_CONFIG_H__ + +#define THREAD_STACKSIZE 512 + +#endif // #define STM32XX_EMAC_CONFIG_H__ diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h b/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h index 5427afc6a2..288faada83 100644 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h +++ b/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h @@ -1,27 +1,17 @@ -/****************************************************************************** - * @file RDA5991H.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for - * RDA RDA5991H Device Series - * @version: V1.09 - * @date: 07. June 2018 +/* Copyright (c) 2019 Unisoc Communications Inc. * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * http://www.apache.org/licenses/LICENSE-2.0 * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #ifndef __RDA5991H_H__ #define __RDA5991H_H__ diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c index 810531b86b..295db4a6bf 100644 --- a/targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c +++ b/targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c @@ -118,4 +118,14 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l return ret; } +int rda_trng_get_bytes(unsigned char *output, size_t len) +{ + size_t temp; + trng_t trng_obj; + trng_init(&trng_obj); + int ret = trng_get_bytes(&trng_obj, output, len, &temp); + trng_free(&trng_obj); + return ret; +} + #endif diff --git a/targets/targets.json b/targets/targets.json index 3e7450ffd5..d1286ffea5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8058,7 +8058,7 @@ "inherits": ["Target"], "core": "Cortex-M4F", "public": true, - "extra_labels": ["RDA", "UNO_91H", "FLASH_CMSIS_ALGO"], + "extra_labels": ["RDA", "UNO_91H", "FLASH_CMSIS_ALGO", "RDA_EMAC"], "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "macros": ["TWO_RAM_REGIONS", "CMSIS_NVIC_VIRTUAL", "CMSIS_NVIC_VIRTUAL_HEADER_FILE=\"RDA5981_nvic_virtual.h\""], "device_has": [ @@ -8067,6 +8067,7 @@ "PORTOUT", "PORTINOUT", "INTERRUPTIN", + "EMAC", "SERIAL", "STDIO_MESSAGES", "PWMOUT", @@ -8080,7 +8081,10 @@ }, "UNO_91H": { "inherits": ["RDA5981X"], - "detect_code": ["8001"] + "detect_code": ["8001"], + "overrides": { + "network-default-interface-type" : "WIFI" + } }, "GD32_Target": { "inherits": ["Target"], From c4e6275d7e12ea169a9f5499a4ddbb3f83a5a188 Mon Sep 17 00:00:00 2001 From: Hasnain Virk Date: Thu, 10 Jan 2019 12:01:30 +0200 Subject: [PATCH 036/109] Doxygen correction Adding to proper group so that the API doxygen appears into the class hierarchy group rather than data strutures. --- features/nfc/nfc/NFCController.h | 19 ++++++++----------- features/nfc/nfc/NFCEEPROM.h | 14 +++++--------- features/nfc/nfc/ndef/MessageBuilder.h | 13 +++++-------- features/nfc/nfc/ndef/MessageParser.h | 15 +++++---------- .../nfc/nfc/ndef/common/SimpleMessageParser.h | 14 ++++++-------- 5 files changed, 29 insertions(+), 46 deletions(-) diff --git a/features/nfc/nfc/NFCController.h b/features/nfc/nfc/NFCController.h index fffb5e1ab2..945d248811 100644 --- a/features/nfc/nfc/NFCController.h +++ b/features/nfc/nfc/NFCController.h @@ -1,4 +1,6 @@ -/* mbed Microcontroller Library +/** @file NFCController.h + * + * mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -31,15 +33,14 @@ namespace mbed { namespace nfc { +/** @addtogroup nfc + * @{ + */ + class NFCRemoteInitiator; class NFCRemoteTarget; class NFCControllerDriver; -/** - * @addtogroup nfc - * @{ - */ - /** * This class represents a NFC Controller. * @@ -178,11 +179,7 @@ private: bool _discovery_running; Span _ndef_buffer; }; - -/** - * @} - */ - +/** @}*/ } // namespace nfc } // namespace mbed diff --git a/features/nfc/nfc/NFCEEPROM.h b/features/nfc/nfc/NFCEEPROM.h index 1e940c745a..b06c2836a7 100644 --- a/features/nfc/nfc/NFCEEPROM.h +++ b/features/nfc/nfc/NFCEEPROM.h @@ -1,4 +1,6 @@ -/* mbed Microcontroller Library +/** @file NFCEEPROM.h + * + * mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,8 +29,7 @@ namespace mbed { namespace nfc { -/** - * @addtogroup nfc +/** @addtogroup nfc * @{ */ @@ -153,12 +154,7 @@ private: uint32_t _eeprom_address; nfc_err_t _operation_result; }; - -/** - * @} - */ - - +/** @}*/ } // namespace nfc } // namespace mbed diff --git a/features/nfc/nfc/ndef/MessageBuilder.h b/features/nfc/nfc/ndef/MessageBuilder.h index 0b2437108e..2564675897 100644 --- a/features/nfc/nfc/ndef/MessageBuilder.h +++ b/features/nfc/nfc/ndef/MessageBuilder.h @@ -1,4 +1,6 @@ -/* mbed Microcontroller Library +/** @file MessageBuilder.h + * + * mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,8 +29,7 @@ namespace mbed { namespace nfc { namespace ndef { -/** - * @addtogroup nfc +/** @addtogroup nfc * @{ */ @@ -189,11 +190,7 @@ private: bool _message_ended; bool _in_chunk; }; - -/** - * @} - */ - +/** @}*/ } // namespace ndef } // namespace nfc } // namespace mbed diff --git a/features/nfc/nfc/ndef/MessageParser.h b/features/nfc/nfc/ndef/MessageParser.h index 41c4a9e3a3..55a0e6e5fd 100644 --- a/features/nfc/nfc/ndef/MessageParser.h +++ b/features/nfc/nfc/ndef/MessageParser.h @@ -1,4 +1,6 @@ -/* mbed Microcontroller Library +/** @file MessageParser.h + * + * mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,19 +20,16 @@ #define NFC_NDEF_MESSAGEPARSER_H_ #include - #include "platform/Span.h" namespace mbed { namespace nfc { namespace ndef { -/** - * @addtogroup nfc +/** @addtogroup nfc * @{ */ - // Forward declaration class Record; @@ -165,11 +164,7 @@ private: Delegate *_delegate; }; - -/** - * @} - */ - +/** @}*/ } // namespace ndef } // namespace nfc } // namespace mbed diff --git a/features/nfc/nfc/ndef/common/SimpleMessageParser.h b/features/nfc/nfc/ndef/common/SimpleMessageParser.h index a4da0049f9..7ba7e9db91 100644 --- a/features/nfc/nfc/ndef/common/SimpleMessageParser.h +++ b/features/nfc/nfc/ndef/common/SimpleMessageParser.h @@ -1,4 +1,6 @@ -/* mbed Microcontroller Library +/** @file SimpleMessageParser.h + * + * mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,8 +32,7 @@ namespace nfc { namespace ndef { namespace common { -/** - * @addtogroup nfc +/** @addtogroup nfc * @{ */ @@ -161,14 +162,11 @@ private: MimeParser _mime_parser; Delegate *_delegate; }; - -/** - * @} - */ - +/** @}*/ } // namespace common } // namespace ndef } // namespace nfc } // namespace mbed #endif /* NFC_COMMON_SIMPLEMESSAGEPARSER_H_ */ + From 8fe844db2bd7621fab8098daadb06d0a3297ad20 Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Tue, 12 Feb 2019 16:20:25 -0600 Subject: [PATCH 037/109] platform: fix build warning in mbed_error Fix the following build warning Compile [ 83.4%]: mbed_error.c [Warning] mbed_error.c@71,21: 'compute_crc32' defined but not used [-Wunused-function] compute_crc32 usage is guraded with #define, but not the definition. Use the same #define around the definition of compute_crc32() --- platform/mbed_error.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/platform/mbed_error.c b/platform/mbed_error.c index c1ee19d6fd..b34dfb23d7 100644 --- a/platform/mbed_error.c +++ b/platform/mbed_error.c @@ -49,15 +49,14 @@ static core_util_atomic_flag halt_in_progress = CORE_UTIL_ATOMIC_FLAG_INIT; static int error_count = 0; static mbed_error_ctx first_error_ctx = {0}; +static mbed_error_ctx last_error_ctx = {0}; +static mbed_error_hook_t error_hook = NULL; +static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller); + #if MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED //Global for populating the context in exception handler static mbed_error_ctx *const report_error_ctx = (mbed_error_ctx *)(ERROR_CONTEXT_LOCATION); static bool is_reboot_error_valid = false; -#endif - -static mbed_error_ctx last_error_ctx = {0}; -static mbed_error_hook_t error_hook = NULL; -static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller); //Helper function to calculate CRC //NOTE: It would have been better to use MbedCRC implementation. But @@ -88,6 +87,7 @@ static unsigned int compute_crc32(const void *data, int datalen) return crc; } +#endif //Helper function to halt the system static MBED_NORETURN void mbed_halt_system(void) From 9891168c61f52d45b651483359a279907109cf69 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Tue, 12 Feb 2019 15:40:11 +0200 Subject: [PATCH 038/109] Greentea tests: set correct port to test against google.com --- TESTS/netsocket/tls/tlssocket_handshake_invalid.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTS/netsocket/tls/tlssocket_handshake_invalid.cpp b/TESTS/netsocket/tls/tlssocket_handshake_invalid.cpp index c5c1a187df..0417afb1c3 100644 --- a/TESTS/netsocket/tls/tlssocket_handshake_invalid.cpp +++ b/TESTS/netsocket/tls/tlssocket_handshake_invalid.cpp @@ -31,8 +31,8 @@ void TLSSOCKET_HANDSHAKE_INVALID() TLSSocket sock; TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(NetworkInterface::get_default_instance())); TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.set_root_ca_cert(tls_global::cert)); - TEST_ASSERT_EQUAL(NSAPI_ERROR_NO_CONNECTION, - sock.connect("google.com", MBED_CONF_APP_ECHO_SERVER_DISCARD_PORT_TLS)); + TEST_ASSERT_EQUAL(NSAPI_ERROR_AUTH_FAILURE, + sock.connect("google.com", 443)); // 443 is https port. TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close()); } From 88c5b8da79a58747f2cf3b42c6748df7386e2bd4 Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Tue, 12 Feb 2019 15:38:42 -0600 Subject: [PATCH 039/109] target: UBLOX: Fix build warning in UBLOX_AT_CellularNetwork.cpp Fix this build warning seen when building with ARMCC Compile [ 13.7%]: UBLOX_AT_CellularNetwork.cpp [Warning] UBLOX_AT_CellularNetwork.cpp@65,0: #111-D: statement is unreachable --- .../framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp index 1491deee60..24b6a19c72 100644 --- a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp +++ b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp @@ -38,6 +38,8 @@ AT_CellularNetwork::RegistrationMode UBLOX_AT_CellularNetwork::has_registration( nsapi_error_t UBLOX_AT_CellularNetwork::set_access_technology_impl(RadioAccessTechnology opRat) { + nsapi_error_t ret = NSAPI_ERROR_OK; + switch (opRat) { #if defined(TARGET_UBLOX_C030_U201) || defined(TARGET_UBLOX_C027) case RAT_GSM: @@ -63,9 +65,9 @@ nsapi_error_t UBLOX_AT_CellularNetwork::set_access_technology_impl(RadioAccessTe #endif default: { _op_act = RAT_UNKNOWN; - return NSAPI_ERROR_UNSUPPORTED; + ret = NSAPI_ERROR_UNSUPPORTED; } } - return NSAPI_ERROR_OK; + return(ret); } From 1b0f7afee91220fa957ab97117e24481d595c124 Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Tue, 12 Feb 2019 16:35:15 -0600 Subject: [PATCH 040/109] nanostack: icmpv6: fix build warning Fix the following build warning seen when building with GCC Compile [ 54.2%]: icmpv6.c [Warning] icmpv6.c@1091,16: this statement may fall through [-Wimplicit-fallthrough=] --- .../sal-stack-nanostack/source/Common_Protocols/icmpv6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c index 2dd17b9143..3059e68265 100644 --- a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c +++ b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c @@ -1084,7 +1084,7 @@ buffer_t *icmpv6_up(buffer_t *buf) case ICMPV6_TYPE_INFO_ECHO_REPLY: ipv6_neighbour_reachability_confirmation(buf->src_sa.address, buf->interface->id); - /* fall through */ + /* fall through */ case ICMPV6_TYPE_ERROR_DESTINATION_UNREACH: #ifdef HAVE_RPL_ROOT @@ -1092,7 +1092,7 @@ buffer_t *icmpv6_up(buffer_t *buf) buf = rpl_control_source_route_error_handler(buf, cur); } #endif - /* no break */ + /* fall through */ default: if (buf) { From 8e843163d2d59e1a851e01cd8e11f77ee60b8245 Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Tue, 12 Feb 2019 16:57:35 -0600 Subject: [PATCH 041/109] features: nanostack: fix warning in thread_extension.h Fix the following build warning seen with GCC Compile [ 51.2%]: thread_bootstrap.c [Warning] thread_extension.h@88,44: statement with no effect [-Wunused-value] --- .../source/6LoWPAN/Thread/thread_extension.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_extension.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_extension.h index b6f64d1e90..2e9fd3d41f 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_extension.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_extension.h @@ -85,7 +85,7 @@ uint8_t *thread_extension_discover_response_write(protocol_interface_info_entry_ #define thread_extension_version_check(version) (false) #define thread_extension_discover_response_read(nwk_info, discover_response_tlv, data_ptr, data_len) ((void) 0) #define thread_extension_discover_response_tlv_write(data, version, securityPolicy) ((void) 0) -#define thread_extension_service_init(cur) (0) +#define thread_extension_service_init(cur) ((void) 0) #define thread_extension_joining_enabled(interface_id) (false) #define thread_extension_discover_response_len(cur) (0) #define thread_extension_discover_response_write(cur, ptr) (ptr) From 352585420dfe33a6ceb7233b001686708b5b192a Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Tue, 12 Feb 2019 15:26:31 -0600 Subject: [PATCH 042/109] btle: fix build warning about unused clockConfiguration Fix the following build warning seen with both GCC and ARM_CC [Warning] btle.cpp@115,0: #177-D: variable "clockConfiguration" was declared but never referenced --- .../TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/btle/btle.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/btle/btle.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/btle/btle.cpp index a0ce8bbeb9..962ddef9b7 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/btle/btle.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/btle/btle.cpp @@ -112,7 +112,6 @@ static uint32_t signalEvent() error_t btle_init(void) { - nrf_clock_lf_cfg_t clockConfiguration; ret_code_t err_code; // register softdevice handler vector @@ -122,6 +121,7 @@ error_t btle_init(void) err_code = nrf_sdh_enable_request(); ASSERT_STATUS(err_code); #else + nrf_clock_lf_cfg_t clockConfiguration; // Configure the LF clock according to values provided by btle_clock.h. // It is input from the chain of the yotta configuration system. clockConfiguration.source = LFCLK_CONF_SOURCE; From 1c88e0fa11a72f9bfcca3a6390c672e797db5149 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Thu, 7 Feb 2019 18:10:02 +0200 Subject: [PATCH 043/109] ESP8266: connect() can handle ESP's errors. ESP8266Interface::connect() checks the exact return value from the underlying ESP8266::connect() call. Increased timeout for network-wifi greentea tests to 6 minutes. --- TESTS/network/wifi/main.cpp | 2 +- .../wifi/esp8266-driver/ESP8266Interface.cpp | 18 +++++++++++------- .../wifi/esp8266-driver/ESP8266Interface.h | 1 + 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/TESTS/network/wifi/main.cpp b/TESTS/network/wifi/main.cpp index aeb139137a..10d5c4c4df 100644 --- a/TESTS/network/wifi/main.cpp +++ b/TESTS/network/wifi/main.cpp @@ -52,7 +52,7 @@ using namespace utest::v1; utest::v1::status_t test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(240, "default_auto"); + GREENTEA_SETUP(360, "default_auto"); return verbose_test_setup_handler(number_of_cases); } diff --git a/components/wifi/esp8266-driver/ESP8266Interface.cpp b/components/wifi/esp8266-driver/ESP8266Interface.cpp index eea53d71a4..1f3ea4b592 100644 --- a/components/wifi/esp8266-driver/ESP8266Interface.cpp +++ b/components/wifi/esp8266-driver/ESP8266Interface.cpp @@ -58,6 +58,7 @@ ESP8266Interface::ESP8266Interface() _if_blocking(true), _if_connected(_cmutex), _initialized(false), + _connect_retval(NSAPI_ERROR_OK), _conn_stat(NSAPI_STATUS_DISCONNECTED), _conn_stat_cb(NULL), _global_event_queue(NULL), @@ -187,8 +188,12 @@ void ESP8266Interface::_connect_async() _cmutex.unlock(); return; } - - if (_esp.connect(ap_ssid, ap_pass) != NSAPI_ERROR_OK) { + _connect_retval = _esp.connect(ap_ssid, ap_pass); + if (_connect_retval == NSAPI_ERROR_OK || _connect_retval == NSAPI_ERROR_AUTH_FAILURE + || _connect_retval == NSAPI_ERROR_NO_SSID) { + _connect_event_id = 0; + _if_connected.notify_all(); + } else { // Postpone to give other stuff time to run _connect_event_id = _global_event_queue->call_in(ESP8266_CONNECT_TIMEOUT, callback(this, &ESP8266Interface::_connect_async)); @@ -196,9 +201,6 @@ void ESP8266Interface::_connect_async() MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_ENOMEM), \ "_connect_async(): unable to add event to queue"); } - } else { - _connect_event_id = 0; - _if_connected.notify_all(); } _cmutex.unlock(); } @@ -235,6 +237,7 @@ int ESP8266Interface::connect() _cmutex.lock(); + _connect_retval = NSAPI_ERROR_NO_CONNECTION; MBED_ASSERT(!_connect_event_id); _connect_event_id = _global_event_queue->call(callback(this, &ESP8266Interface::_connect_async)); @@ -243,13 +246,14 @@ int ESP8266Interface::connect() "connect(): unable to add event to queue"); } - while (_if_blocking && (_conn_status_to_error() != NSAPI_ERROR_IS_CONNECTED)) { + while (_if_blocking && (_conn_status_to_error() != NSAPI_ERROR_IS_CONNECTED) + && (_connect_retval == NSAPI_ERROR_NO_CONNECTION)) { _if_connected.wait(); } _cmutex.unlock(); - return NSAPI_ERROR_OK; + return _connect_retval; } int ESP8266Interface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) diff --git a/components/wifi/esp8266-driver/ESP8266Interface.h b/components/wifi/esp8266-driver/ESP8266Interface.h index f123cf27cd..93d455120f 100644 --- a/components/wifi/esp8266-driver/ESP8266Interface.h +++ b/components/wifi/esp8266-driver/ESP8266Interface.h @@ -368,6 +368,7 @@ private: bool _get_firmware_ok(); nsapi_error_t _init(void); void _hw_reset(); + nsapi_error_t _connect_retval; //sigio struct { From c05fca23162e044939679c93f41766f6c0a77574 Mon Sep 17 00:00:00 2001 From: Steve Cartmell Date: Mon, 11 Feb 2019 18:46:49 +0000 Subject: [PATCH 044/109] revert: "Refactor sleep tracing driver identifier to be pointer to the driver filepath." This reverts commit 9a0e8797b9b9fc32f6ce8f5fc508a43ff76b42f8. --- platform/mbed_sleep_manager.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/platform/mbed_sleep_manager.c b/platform/mbed_sleep_manager.c index c1d4c9b510..c792c783de 100644 --- a/platform/mbed_sleep_manager.c +++ b/platform/mbed_sleep_manager.c @@ -73,11 +73,14 @@ us_timestamp_t mbed_time_deepsleep(void) #ifdef MBED_SLEEP_TRACING_ENABLED +// Length of the identifier extracted from the driver name to store for logging. +#define IDENTIFIER_WIDTH 15 + // Number of drivers that can be stored in the structure #define STATISTIC_COUNT 10 typedef struct sleep_statistic { - const char *identifier; + char identifier[IDENTIFIER_WIDTH]; uint8_t count; } sleep_statistic_t; @@ -85,8 +88,13 @@ static sleep_statistic_t sleep_stats[STATISTIC_COUNT]; static sleep_statistic_t *sleep_tracker_find(const char *const filename) { + char temp[IDENTIFIER_WIDTH]; + strncpy(temp, filename, IDENTIFIER_WIDTH); + temp[IDENTIFIER_WIDTH - 1] = '\0'; + + // Search for the a driver matching the current name and return it's index for (int i = 0; i < STATISTIC_COUNT; ++i) { - if (sleep_stats[i].identifier == filename) { + if (strcmp(sleep_stats[i].identifier, temp) == 0) { return &sleep_stats[i]; } } @@ -96,9 +104,15 @@ static sleep_statistic_t *sleep_tracker_find(const char *const filename) static sleep_statistic_t *sleep_tracker_add(const char *const filename) { + char temp[IDENTIFIER_WIDTH]; + strncpy(temp, filename, IDENTIFIER_WIDTH); + temp[IDENTIFIER_WIDTH - 1] = '\0'; + for (int i = 0; i < STATISTIC_COUNT; ++i) { - if (sleep_stats[i].identifier == NULL) { - sleep_stats[i].identifier = filename; + if (sleep_stats[i].identifier[0] == '\0') { + core_util_critical_section_enter(); + strncpy(sleep_stats[i].identifier, temp, sizeof(temp)); + core_util_critical_section_exit(); return &sleep_stats[i]; } @@ -117,7 +131,7 @@ static void sleep_tracker_print_stats(void) continue; } - if (sleep_stats[i].identifier == NULL) { + if (sleep_stats[i].identifier[0] == '\0') { return; } From 14061854f1d444b57d62fe01f8220ac763e6a489 Mon Sep 17 00:00:00 2001 From: Oren Cohen Date: Wed, 13 Feb 2019 21:09:33 +0200 Subject: [PATCH 045/109] Add release notes section to PR template --- .github/pull_request_template.md | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index e3ecdd70b2..289c5740a3 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -1,15 +1,15 @@ ### Description - ### Pull request type - +### Release Notes + + From d17a5c8b5d819b0a6fca939dfe4795452971650d Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Wed, 6 Feb 2019 14:32:14 -0600 Subject: [PATCH 046/109] Do not provide a default Pelion host address. This moves the default pelion host address to be assigned by the cloud sdk. It also cleans up the logic a bit to be shorter. --- tools/device_management.py | 47 ++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 22 deletions(-) diff --git a/tools/device_management.py b/tools/device_management.py index 74a6c22edc..2ad7d26416 100644 --- a/tools/device_management.py +++ b/tools/device_management.py @@ -23,7 +23,6 @@ import logging import sys import argparse from os.path import join, abspath, dirname, basename -from os import getenv from manifesttool import create, parse, verify, cert, init, update from manifesttool.argparser import MainArgumentParser @@ -31,9 +30,6 @@ from mbed_cloud import AccountManagementAPI, CertificatesAPI import colorama colorama.init() -from utils import (generate_update_filename) - - LOG = logging.getLogger(__name__) LOG_FORMAT = '[%(levelname)s] %(asctime)s - %(name)s - %(message)s' @@ -43,6 +39,7 @@ sys.path.insert(0, ROOT) from tools.config import Config from tools.options import extract_mcus +from tools.utils import generate_update_filename class MbedExtendedArgs(MainArgumentParser): @@ -91,24 +88,30 @@ def wrap_payload(func): def wrap_init(func): def inner(options): - if getattr(options, 'api_key', None): - api_key = options.api_key - else: - api_key = getenv("MBED_CLOUD_SDK_API_KEY") - if getattr(options, 'server_address', None): - host_addr = options.server_address - else: - host_addr = getenv("MBED_CLOUD_SDK_HOST", - "https://api.us-east-1.mbedcloud.com/") - config = { - "api_key": api_key, - "host": host_addr, - } - accounts = AccountManagementAPI(config) - certs = CertificatesAPI(config) - api_key = accounts.list_api_keys(filter={ - 'key': api_key - }).next() + config = {} + if getattr(options, 'api_key'): + config["api_key"] = options.api_key + if getattr(options, 'server_address'): + config["host"] = options.server_address + + try: + accounts = AccountManagementAPI(config) + certs = CertificatesAPI(config) + except Exception as e: + LOG.error( + 'Missing api key. Set it with ' + '"mbed config -G CLOUD_SDK_API_KEY "' + ) + exit(1) + + # Get the currently in-use API key (may come from environment or + # configuration files, which is handled by the cloud SDK) + api_key_value = accounts.config.get("api_key") + api_key = accounts.list_api_keys( + filter={ + "key": api_key_value + } + ).next() certificates_owned = list(certs.list_certificates()) dev_cert_info = None for certif in certificates_owned: From bb2e41314658077f0e0c563700487252d2175edb Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Wed, 13 Feb 2019 17:56:09 -0600 Subject: [PATCH 047/109] Add .inc as a header file type. Currently, if you were to add a directory that only contained .inc files, this file would not be passed as an include path to the compiler. This ensures that .inc files are also considered header files. --- tools/resources/__init__.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/resources/__init__.py b/tools/resources/__init__.py index 243b6c0c5d..5da087fa7d 100644 --- a/tools/resources/__init__.py +++ b/tools/resources/__init__.py @@ -418,6 +418,7 @@ class Resources(object): ".h": FileType.HEADER, ".hh": FileType.HEADER, ".hpp": FileType.HEADER, + ".inc": FileType.HEADER, ".o": FileType.OBJECT, ".hex": FileType.HEX, ".bin": FileType.BIN, From ec3093b3dbcba8fbb0377563a75224f83f604d9d Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Thu, 14 Feb 2019 10:17:59 -0600 Subject: [PATCH 048/109] tools/utils: ensure default build profiles are processed first The command-line argument '--profile' looks for build profiles provided in mbed-os/tools/profiles/. If a directory name exists in the root folder with the same name as one of the profile names provided by default [e.g debug/develop/release], that directory is processed instead resulting in incorrect behavior. Fix this behavior by processing the default profiles first. --- tools/utils.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/utils.py b/tools/utils.py index ad5db06fdf..37d6c885f7 100644 --- a/tools/utils.py +++ b/tools/utils.py @@ -495,10 +495,12 @@ def argparse_profile_filestring_type(string): absolute path or a file name (expanded to mbed-os/tools/profiles/.json) of a existing file""" fpath = join(dirname(__file__), "profiles/{}.json".format(string)) - if exists(string): - return string - elif exists(fpath): + + # default profiles are searched first, local ones next. + if exists(fpath): return fpath + elif exists(string): + return string else: raise argparse.ArgumentTypeError( "{0} does not exist in the filesystem.".format(string)) From f14828e8c6bcd3c9017b2e3801e0c5b0d93daa3f Mon Sep 17 00:00:00 2001 From: Amir Cohen Date: Thu, 14 Feb 2019 17:30:51 +0200 Subject: [PATCH 049/109] Add flash sum check Check that flash size sum up to all sectors combined --- TESTS/mbed_drivers/flashiap/main.cpp | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/TESTS/mbed_drivers/flashiap/main.cpp b/TESTS/mbed_drivers/flashiap/main.cpp index 9cd3cd861b..28249eeaf2 100644 --- a/TESTS/mbed_drivers/flashiap/main.cpp +++ b/TESTS/mbed_drivers/flashiap/main.cpp @@ -29,6 +29,17 @@ #include "mbed.h" +// Debug available +#ifndef FLASHIAP_DEBUG +#define FLASHIAP_DEBUG 0 +#endif + +#if FLASHIAP_DEBUG +#define DEBUG_PRINTF(...) printf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + using namespace utest::v1; @@ -37,6 +48,21 @@ void flashiap_init_test() FlashIAP flash_device; uint32_t ret = flash_device.init(); TEST_ASSERT_EQUAL_INT32(0, ret); + + uint32_t flash_start = flash_device.get_flash_start(); + uint32_t flash_size = flash_device.get_flash_size(); + utest_printf("Flash address: 0x%08x, size: %d\n", flash_start, flash_size); + uint32_t address = flash_start; + int num = 0; + while (flash_size) { + uint32_t sector_size = flash_device.get_sector_size(address); + // Make sure all sectors sum up to the total flash size + TEST_ASSERT(flash_size >= sector_size); + DEBUG_PRINTF("\tsector %3d: address 0x%08x, size %8d\n", num++, address, sector_size); + flash_size -= sector_size; + address += sector_size; + } + ret = flash_device.deinit(); TEST_ASSERT_EQUAL_INT32(0, ret); } From 9c519c2fa3cc13e0af846a97c2bd2ef3a7b4ddeb Mon Sep 17 00:00:00 2001 From: Hasnain Virk Date: Mon, 4 Feb 2019 14:58:21 +0200 Subject: [PATCH 050/109] Including CTest explicitly enable_test() seems to include CTest framework in the CMakeLists.txt but that would result in inconsistencies and CTest framework will not be able to find DartConfiguration file or MemCheck tool. Including CTest framework explicitely in the CMakeLists.txt seems to solve the issue. --- UNITTESTS/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UNITTESTS/CMakeLists.txt b/UNITTESTS/CMakeLists.txt index 7e93bf5c68..112aa373ea 100644 --- a/UNITTESTS/CMakeLists.txt +++ b/UNITTESTS/CMakeLists.txt @@ -59,7 +59,7 @@ target_include_directories(gmock_main SYSTEM BEFORE INTERFACE # TESTING #################### -enable_testing() +include(CTest) set_property(DIRECTORY APPEND PROPERTY ADDITIONAL_MAKE_CLEAN_FILES "${CMAKE_BINARY_DIR}/Testing" From c433a144e7ae6ed7def8f150e3583742c46625bc Mon Sep 17 00:00:00 2001 From: Hasnain Virk Date: Mon, 4 Feb 2019 15:01:35 +0200 Subject: [PATCH 051/109] Proper size checking for link ADR commands In a specific branch path 'adr_settings' in link_adr_request() API, the structure adr_settings of type link_adr_params_t will be rendered uninitialized. To prevent this we initialize the construct as zero. In addition to that, to handle the case properly we should check for the command identifier and the command payload length anticipating contiguous blocks of adr commands. If we find a discrepency in size, we should abort. --- .../lorawan/lorastack/mac/LoRaMacCommand.cpp | 15 +++++++++++---- features/lorawan/lorastack/phy/LoRaPHY.cpp | 16 +++++++++++++--- features/lorawan/lorastack/phy/LoRaPHY.h | 3 ++- features/lorawan/lorastack/phy/LoRaPHYAU915.cpp | 13 +++++++++++-- features/lorawan/lorastack/phy/LoRaPHYCN470.cpp | 16 +++++++++++++--- features/lorawan/lorastack/phy/LoRaPHYUS915.cpp | 13 +++++++++++-- 6 files changed, 61 insertions(+), 15 deletions(-) diff --git a/features/lorawan/lorastack/mac/LoRaMacCommand.cpp b/features/lorawan/lorastack/mac/LoRaMacCommand.cpp index b3447cde7f..d2ebf397ff 100644 --- a/features/lorawan/lorastack/mac/LoRaMacCommand.cpp +++ b/features/lorawan/lorastack/mac/LoRaMacCommand.cpp @@ -149,7 +149,7 @@ lorawan_status_t LoRaMacCommand::process_mac_commands(const uint8_t *payload, ui int8_t link_adr_dr = DR_0; int8_t link_adr_txpower = TX_POWER_0; uint8_t link_adr_nbtrans = 0; - uint8_t link_adr_nb_bytes_pasred = 0; + uint8_t link_adr_nb_bytes_parsed = 0; // Fill parameter structure link_adr_req.payload = &payload[mac_index - 1]; @@ -165,7 +165,14 @@ lorawan_status_t LoRaMacCommand::process_mac_commands(const uint8_t *payload, ui &link_adr_dr, &link_adr_txpower, &link_adr_nbtrans, - &link_adr_nb_bytes_pasred); + &link_adr_nb_bytes_parsed); + + // If nothing was consumed, we have a malformed packet at our hand + // we bin everything and return. link_adr_nb_bytes_parsed being 0 is + // a magic identifier letting us know that there are payload inconsistencies + if (link_adr_nb_bytes_parsed == 0) { + return LORAWAN_STATUS_UNSUPPORTED; + } if ((status & 0x07) == 0x07) { mac_sys_params.channel_data_rate = link_adr_dr; @@ -174,11 +181,11 @@ lorawan_status_t LoRaMacCommand::process_mac_commands(const uint8_t *payload, ui } // Add the answers to the buffer - for (uint8_t i = 0; i < (link_adr_nb_bytes_pasred / 5); i++) { + for (uint8_t i = 0; i < (link_adr_nb_bytes_parsed / 5); i++) { ret_value = add_link_adr_ans(status); } // Update MAC index - mac_index += link_adr_nb_bytes_pasred - 1; + mac_index += link_adr_nb_bytes_parsed - 1; } break; case SRV_MAC_DUTY_CYCLE_REQ: diff --git a/features/lorawan/lorastack/phy/LoRaPHY.cpp b/features/lorawan/lorastack/phy/LoRaPHY.cpp index 1e6cc64169..dd3cba9217 100644 --- a/features/lorawan/lorastack/phy/LoRaPHY.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHY.cpp @@ -309,11 +309,12 @@ lorawan_time_t LoRaPHY::update_band_timeoff(bool joined, bool duty_cycle, } uint8_t LoRaPHY::parse_link_ADR_req(const uint8_t *payload, + uint8_t payload_size, link_adr_params_t *params) { uint8_t ret_index = 0; - if (payload[0] == SRV_MAC_LINK_ADR_REQ) { + if (payload_size >= 5) { // Parse datarate and tx power params->datarate = payload[1]; @@ -973,13 +974,17 @@ uint8_t LoRaPHY::link_ADR_request(adr_req_params_t *link_adr_req, verify_adr_params_t verify_params; - while (bytes_processed < link_adr_req->payload_size) { + while (bytes_processed < link_adr_req->payload_size && + link_adr_req->payload[bytes_processed] == SRV_MAC_LINK_ADR_REQ) { // Get ADR request parameters next_index = parse_link_ADR_req(&(link_adr_req->payload[bytes_processed]), + link_adr_req->payload_size - bytes_processed, &adr_settings); if (next_index == 0) { - break; // break loop, since no more request has been found + bytes_processed = 0; + // break loop, malformed packet + break; } // Update bytes processed @@ -1024,6 +1029,11 @@ uint8_t LoRaPHY::link_ADR_request(adr_req_params_t *link_adr_req, } } + if (bytes_processed == 0) { + *nb_bytes_processed = 0; + return status; + } + if (is_datarate_supported(adr_settings.datarate)) { verify_params.status = status; diff --git a/features/lorawan/lorastack/phy/LoRaPHY.h b/features/lorawan/lorastack/phy/LoRaPHY.h index d6be36b1dc..f68f646726 100644 --- a/features/lorawan/lorastack/phy/LoRaPHY.h +++ b/features/lorawan/lorastack/phy/LoRaPHY.h @@ -608,7 +608,8 @@ protected: /** * Parses the parameter of an LinkAdrRequest. */ - uint8_t parse_link_ADR_req(const uint8_t *payload, link_adr_params_t *adr_params); + uint8_t parse_link_ADR_req(const uint8_t *payload, uint8_t payload_size, + link_adr_params_t *adr_params); /** * Verifies and updates the datarate, the TX power and the number of repetitions diff --git a/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp b/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp index 46ea344860..b41091e8e8 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp @@ -435,12 +435,16 @@ uint8_t LoRaPHYAU915::link_ADR_request(adr_req_params_t *params, // Initialize local copy of channels mask copy_channel_mask(temp_channel_masks, channel_mask, AU915_CHANNEL_MASK_SIZE); - while (bytes_processed < params->payload_size) { + while (bytes_processed < params->payload_size && + params->payload[bytes_processed] == SRV_MAC_LINK_ADR_REQ) { next_index = parse_link_ADR_req(&(params->payload[bytes_processed]), + params->payload_size, &adr_settings); if (next_index == 0) { - break; // break loop, since no more request has been found + bytes_processed = 0; + // break loop, malformed packet + break; } // Update bytes processed @@ -471,6 +475,11 @@ uint8_t LoRaPHYAU915::link_ADR_request(adr_req_params_t *params, } } + if (bytes_processed == 0) { + *nb_bytes_parsed = 0; + return status; + } + // FCC 15.247 paragraph F mandates to hop on at least 2 125 kHz channels if ((adr_settings.datarate < DR_6) && (num_active_channels(temp_channel_masks, 0, 4) < 2)) { diff --git a/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp b/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp index 01614e34f5..da46aea6bf 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp @@ -460,13 +460,18 @@ uint8_t LoRaPHYCN470::link_ADR_request(adr_req_params_t *params, // Initialize local copy of channels mask copy_channel_mask(temp_channel_masks, channel_mask, CN470_CHANNEL_MASK_SIZE); - while (bytes_processed < params->payload_size) { + while (bytes_processed < params->payload_size && + params->payload[bytes_processed] == SRV_MAC_LINK_ADR_REQ) { // Get ADR request parameters - next_index = parse_link_ADR_req(&(params->payload[bytes_processed]), &adr_settings); + next_index = parse_link_ADR_req(&(params->payload[bytes_processed]), + params->payload_size, + &adr_settings); if (next_index == 0) { - break; // break loop, since no more request has been found + bytes_processed = 0; + // break loop, malformed packet + break; } // Update bytes processed @@ -501,6 +506,11 @@ uint8_t LoRaPHYCN470::link_ADR_request(adr_req_params_t *params, } } + if (bytes_processed == 0) { + *nb_bytes_parsed = 0; + return status; + } + verify_params.status = status; verify_params.adr_enabled = params->adr_enabled; verify_params.datarate = adr_settings.datarate; diff --git a/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp b/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp index abc496be13..d454fb24e4 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp @@ -460,12 +460,16 @@ uint8_t LoRaPHYUS915::link_ADR_request(adr_req_params_t *params, // Initialize local copy of channels mask copy_channel_mask(temp_channel_masks, channel_mask, US915_CHANNEL_MASK_SIZE); - while (bytes_processed < params->payload_size) { + while (bytes_processed < params->payload_size && + params->payload[bytes_processed] == SRV_MAC_LINK_ADR_REQ) { next_idx = parse_link_ADR_req(&(params->payload[bytes_processed]), + params->payload_size - bytes_processed, &adr_settings); if (next_idx == 0) { - break; // break loop, since no more request has been found + bytes_processed = 0; + // break loop, malformed packet + break; } // Update bytes processed @@ -501,6 +505,11 @@ uint8_t LoRaPHYUS915::link_ADR_request(adr_req_params_t *params, } } + if (bytes_processed == 0) { + *nb_bytes_parsed = 0; + return status; + } + // FCC 15.247 paragraph F mandates to hop on at least 2 125 kHz channels if ((adr_settings.datarate < DR_4) && (num_active_channels(temp_channel_masks, 0, 4) < 2)) { From 523a8cebe0fb182116ef53d6c308cd81c356c755 Mon Sep 17 00:00:00 2001 From: Hasnain Virk Date: Mon, 4 Feb 2019 16:57:53 +0200 Subject: [PATCH 052/109] Updating unit tests Updating unit test in response to the change in the link ADR related APIs. --- .../features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp | 4 ++++ .../features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp | 4 ++++ .../features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp | 9 ++++++++- .../features/lorawan/lorawanstack/Test_LoRaWANStack.cpp | 4 ++++ UNITTESTS/stubs/LoRaPHY_stub.cpp | 3 +++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp b/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp index 11a27e9d20..93ff3d29e0 100644 --- a/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp +++ b/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp @@ -181,6 +181,10 @@ TEST_F(Test_LoRaPHYAU915, link_ADR_request) uint8_t nb_rep_out = 0; uint8_t nb_bytes_parsed = 0; + uint8_t payload [] = {SRV_MAC_LINK_ADR_REQ, 1, 2, 3, 4}; + params.payload = payload; + params.payload_size = 5; + LoRaPHY_stub::uint8_value = 1; LoRaPHY_stub::ch_mask_value = 6; LoRaPHY_stub::adr_parse_count = 2; diff --git a/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp b/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp index abeefd52d6..20e8fc3be2 100644 --- a/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp +++ b/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp @@ -206,6 +206,10 @@ TEST_F(Test_LoRaPHYCN470, link_ADR_request) uint8_t nb_rep_out = 0; uint8_t nb_bytes_parsed = 0; + uint8_t payload [] = {SRV_MAC_LINK_ADR_REQ, 1, 2, 3, 4}; + params.payload = payload; + params.payload_size = 5; + LoRaPHY_stub::uint8_value = 1; LoRaPHY_stub::ch_mask_value = 6; LoRaPHY_stub::adr_parse_count = 2; diff --git a/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp b/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp index b3d921bac9..36e3a15e78 100644 --- a/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp +++ b/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp @@ -177,6 +177,7 @@ TEST_F(Test_LoRaPHYUS915, tx_config) TEST_F(Test_LoRaPHYUS915, link_ADR_request) { + uint8_t payload [] = {SRV_MAC_LINK_ADR_REQ, 1, 2, 3, 4}; adr_req_params_t params; memset(¶ms, 0, sizeof(params)); int8_t dr_out = 0; @@ -184,8 +185,14 @@ TEST_F(Test_LoRaPHYUS915, link_ADR_request) uint8_t nb_rep_out = 0; uint8_t nb_bytes_parsed = 0; - EXPECT_TRUE(0 == object->link_ADR_request(¶ms, &dr_out, &tx_power_out, &nb_rep_out, &nb_bytes_parsed)); + params.payload = payload; + params.payload_size = 4; + uint8_t status = object->link_ADR_request(¶ms, &dr_out, &tx_power_out, &nb_rep_out, &nb_bytes_parsed); + + EXPECT_TRUE(0 == nb_bytes_parsed); + + params.payload_size = 5; LoRaPHY_stub::uint8_value = 1; LoRaPHY_stub::ch_mask_value = 6; LoRaPHY_stub::adr_parse_count = 2; diff --git a/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp b/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp index 15a2942001..e91f842055 100644 --- a/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp +++ b/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp @@ -494,6 +494,10 @@ TEST_F(Test_LoRaWANStack, handle_rx) ind.buffer = ind_buf; ind.buffer_size = 150; ind.type = MCPS_UNCONFIRMED; + ind.port = 15; + ind.is_data_recvd = true; + ind.fpending_status = false; + LoRaMac_stub::dev_class_value = CLASS_A; radio._ev->rx_done(NULL, 0, 0, 0); //data == NULL || LENGTH == 0 (2 cases) diff --git a/UNITTESTS/stubs/LoRaPHY_stub.cpp b/UNITTESTS/stubs/LoRaPHY_stub.cpp index 01b7312b7c..53dce9fe4f 100644 --- a/UNITTESTS/stubs/LoRaPHY_stub.cpp +++ b/UNITTESTS/stubs/LoRaPHY_stub.cpp @@ -151,9 +151,12 @@ lorawan_time_t LoRaPHY::update_band_timeoff(bool joined, bool duty_cycle, } uint8_t LoRaPHY::parse_link_ADR_req(const uint8_t *payload, + uint8_t payload_size, link_adr_params_t *params) { params->ch_mask_ctrl = LoRaPHY_stub::ch_mask_value; + params->channel_mask = 0; + params->datarate = 0; if (LoRaPHY_stub::adr_parse_count) { return --LoRaPHY_stub::adr_parse_count; From b96ec171b5efe7476854c56305d564a7016687e9 Mon Sep 17 00:00:00 2001 From: Antti Yli-Tokola Date: Mon, 11 Feb 2019 10:37:43 +0200 Subject: [PATCH 053/109] Update mbed-coap to version 4.7.4 - Remove dependency to yotta tool - Do not remove stored (GET) blockwise message when EMPTY ACK received. When non piggybacked response mode is used original GET request must not be removed from the stored message list.Message is needed for building the next (GET) blockwise message. - Move definitions to sn_config.h --- features/frameworks/mbed-coap/.yotta_ignore | 5 - features/frameworks/mbed-coap/CHANGELOG.md | 10 ++ features/frameworks/mbed-coap/Makefile.test | 24 +++- .../mbed-coap/mbed-coap/sn_config.h | 104 +++++++++++++---- .../frameworks/mbed-coap/run_unit_tests.sh | 3 +- .../include/sn_coap_protocol_internal.h | 107 +----------------- .../mbed-coap/source/sn_coap_protocol.c | 5 +- 7 files changed, 122 insertions(+), 136 deletions(-) delete mode 100644 features/frameworks/mbed-coap/.yotta_ignore diff --git a/features/frameworks/mbed-coap/.yotta_ignore b/features/frameworks/mbed-coap/.yotta_ignore deleted file mode 100644 index 6cd3f5174f..0000000000 --- a/features/frameworks/mbed-coap/.yotta_ignore +++ /dev/null @@ -1,5 +0,0 @@ -# need unity.h: -unittest/* -test/* -doxygen/* - diff --git a/features/frameworks/mbed-coap/CHANGELOG.md b/features/frameworks/mbed-coap/CHANGELOG.md index 7da355071f..4e0355bf70 100644 --- a/features/frameworks/mbed-coap/CHANGELOG.md +++ b/features/frameworks/mbed-coap/CHANGELOG.md @@ -1,5 +1,15 @@ # Change Log +## [v4.7.4](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.7.4) + +- Remove dependency to yotta tool +- Do not remove stored (GET) blockwise message when EMPTY ACK received + When non piggybacked response mode is used original GET request must not be removed from the stored message list. + Message is needed for building the next (GET) blockwise message. +- Move definitions to sn_config.h + +-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.7.3...v4.7.4) + ## [v4.7.3](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.7.3) - Do not store EMPTY response to blockwise list diff --git a/features/frameworks/mbed-coap/Makefile.test b/features/frameworks/mbed-coap/Makefile.test index 4cc7296c5f..78cf60fbbc 100644 --- a/features/frameworks/mbed-coap/Makefile.test +++ b/features/frameworks/mbed-coap/Makefile.test @@ -11,6 +11,28 @@ TESTDIRS := $(UNITTESTS:%=build-%) CLEANTESTDIRS := $(UNITTESTS:%=clean-%) COVERAGEFILE := ./lcov/coverage.info +TEST_MODULES = ./test_modules +TEST_MODULE_MBED_TRACE = $(TEST_MODULES)/mbed-trace +TEST_MODULE_NANOSTACK = $(TEST_MODULES)/nanostack-libservice +TEST_MODULE_RANDLIB = $(TEST_MODULES)/mbed-client-randlib + +.PHONY: clone +clone: + if [ ! -d $(TEST_MODULES) ]; \ + then mkdir $(TEST_MODULES); \ + fi; + + if [ ! -d $(TEST_MODULE_MBED_TRACE) ]; \ + then git clone --depth 1 git@github.com:ARMmbed/mbed-trace.git $(TEST_MODULE_MBED_TRACE); \ + fi; + + if [ ! -d $(TEST_MODULE_NANOSTACK) ]; \ + then git clone --depth 1 git@github.com:ARMmbed/nanostack-libservice.git $(TEST_MODULE_NANOSTACK); \ + fi; + + if [ ! -d $(TEST_MODULE_RANDLIB) ]; \ + then git clone --depth 1 git@github.com:ARMmbed/mbed-client-randlib.git $(TEST_MODULE_RANDLIB); \ + fi; .PHONY: test test: $(TESTDIRS) @rm -rf ./lcov @@ -27,7 +49,7 @@ test: $(TESTDIRS) @rm -f lcov/index.xml @find ./ -name '*.gcno' | xargs cp --backup=numbered -t ./coverage/ @find ./ -name '*.gcda' | xargs cp --backup=numbered -t ./coverage/ - @gcovr --object-directory ./coverage --exclude-unreachable-branches -e '.*/builds/.*' -e '.*/test/.*' -e '.*/yotta_modules/.*' -e '.*/stubs/.*' -e '.*/mbed-coap/.*' -x -o ./lcov/gcovr.xml + @gcovr --object-directory ./coverage --exclude-unreachable-branches -e '.*/builds/.*' -e '.*/test/.*' -e '.*/stubs/.*' -e '.*/mbed-coap/.*' -x -o ./lcov/gcovr.xml @lcov -d test/. -c -o $(COVERAGEFILE) @lcov -q -r $(COVERAGEFILE) "/usr*" -o $(COVERAGEFILE) @lcov -q -r $(COVERAGEFILE) "/test*" -o $(COVERAGEFILE) diff --git a/features/frameworks/mbed-coap/mbed-coap/sn_config.h b/features/frameworks/mbed-coap/mbed-coap/sn_config.h index 5794af5cbc..63652826ed 100644 --- a/features/frameworks/mbed-coap/mbed-coap/sn_config.h +++ b/features/frameworks/mbed-coap/mbed-coap/sn_config.h @@ -17,6 +17,10 @@ #ifndef SN_CONFIG_H #define SN_CONFIG_H +#ifdef MBED_CLIENT_USER_CONFIG_FILE +#include MBED_CLIENT_USER_CONFIG_FILE +#endif + /** * \brief Configuration options (set of defines and values) * @@ -30,9 +34,15 @@ * \brief For Message duplication detection * Init value for the maximum count of messages to be stored for duplication detection * Setting of this value to 0 will disable duplication check, also reduce use of ROM memory - * Default is set to 1. + * Default is set to 0. */ -#undef SN_COAP_DUPLICATION_MAX_MSGS_COUNT /* 1 */ +#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_DUPLICATION_MAX_MSGS_COUNT +#define SN_COAP_DUPLICATION_MAX_MSGS_COUNT MBED_CONF_MBED_CLIENT_SN_COAP_DUPLICATION_MAX_MSGS_COUNT +#endif + +#ifndef SN_COAP_DUPLICATION_MAX_MSGS_COUNT +#define SN_COAP_DUPLICATION_MAX_MSGS_COUNT 0 +#endif /** * \def SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE @@ -42,7 +52,13 @@ * also reduce use of ROM memory. * Note: This define is common for both received and sent Blockwise messages */ -#undef SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE /* 0 */ // < Must be 2^x and x is at least 4. Suitable values: 0, 16, 32, 64, 128, 256, 512 and 1024 +#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE +#define SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE MBED_CONF_MBED_CLIENT_SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE +#endif + +#ifndef SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE +#define SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE 0 /**< Must be 2^x and x is at least 4. Suitable values: 0, 16, 32, 64, 128, 256, 512 and 1024 */ +#endif /** * \def SN_COAP_DISABLE_RESENDINGS @@ -50,21 +66,33 @@ * when using CoAP with TCP transport for example. By default resendings are * enabled. Set to 1 to disable. */ -#undef SN_COAP_DISABLE_RESENDINGS /* 0 */ // < Default re-sending are not disabled. Set to 1 to disable re-sendings +#ifdef SN_COAP_DISABLE_RESENDINGS +#define ENABLE_RESENDINGS 0 /** Disable resendings **/ +#else +#define ENABLE_RESENDINGS 1 /**< Enable / Disable resending from library in building */ +#endif /** * \def SN_COAP_RESENDING_QUEUE_SIZE_MSGS * \brief Sets the number of messages stored * in the resending queue. Default is 2 */ -#undef SN_COAP_RESENDING_QUEUE_SIZE_MSGS /* 2 */ // < Default re-sending queue size - defines how many messages can be stored. Setting this to 0 disables feature +#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_MSGS +#define SN_COAP_RESENDING_QUEUE_SIZE_MSGS MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_MSGS +#endif + +#ifndef SN_COAP_RESENDING_QUEUE_SIZE_MSGS +#define SN_COAP_RESENDING_QUEUE_SIZE_MSGS 2 /**< Default re-sending queue size - defines how many messages can be stored. Setting this to 0 disables feature */ +#endif /** * \def DEFAULT_RESPONSE_TIMEOUT * \brief Sets the CoAP re-send interval in seconds. * By default is 10 seconds. */ -#undef DEFAULT_RESPONSE_TIMEOUT +#ifndef DEFAULT_RESPONSE_TIMEOUT +#define DEFAULT_RESPONSE_TIMEOUT 10 /**< Default re-sending timeout as seconds */ +#endif /** * \def SN_COAP_RESENDING_QUEUE_SIZE_BYTES @@ -72,7 +100,13 @@ * Setting this to 0 disables this feature. * By default, this feature is disabled. */ -#undef SN_COAP_RESENDING_QUEUE_SIZE_BYTES /* 0 */ // Default re-sending queue size - defines size of the re-sending buffer. Setting this to 0 disables feature +#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_BYTES +#define SN_COAP_RESENDING_QUEUE_SIZE_BYTES MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_BYTES +#endif + +#ifndef SN_COAP_RESENDING_QUEUE_SIZE_BYTES +#define SN_COAP_RESENDING_QUEUE_SIZE_BYTES 0 /**< Default re-sending queue size - defines size of the re-sending buffer. Setting this to 0 disables feature */ +#endif /** * \def SN_COAP_MAX_INCOMING_MESSAGE_SIZE @@ -83,7 +117,9 @@ * available storage capability. * By default, maximum size is UINT16_MAX, 65535 bytes. */ -#undef SN_COAP_MAX_INCOMING_MESSAGE_SIZE /* UINT16_MAX */ +#ifndef SN_COAP_MAX_INCOMING_MESSAGE_SIZE +#define SN_COAP_MAX_INCOMING_MESSAGE_SIZE UINT16_MAX +#endif /** * \def SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE @@ -98,21 +134,27 @@ * Note that value should be less than transport layer maximum fragment size. * Note that value has no effect if blockwise transfer is disabled. */ -#undef SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE /* 0 */ +#ifndef SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE +#define SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE 0 +#endif /** * \def SN_COAP_BLOCKWISE_ENABLED * \brief Enables the blockwise functionality in CoAP library also when blockwise payload * size is set to '0' in SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE. */ -#undef SN_COAP_BLOCKWISE_ENABLED /* 0 */ +#ifndef SN_COAP_BLOCKWISE_ENABLED +#define SN_COAP_BLOCKWISE_ENABLED 0 /**< Enable blockwise */ +#endif /** * \def SN_COAP_RESENDING_MAX_COUNT * \brief Defines how many times CoAP library tries to re-send the CoAP packet. * By default value is 3. */ -#undef SN_COAP_RESENDING_MAX_COUNT /* 3 */ +#ifndef SN_COAP_RESENDING_MAX_COUNT +#define SN_COAP_RESENDING_MAX_COUNT 3 +#endif /** * \def SN_COAP_MAX_ALLOWED_RESENDING_COUNT @@ -120,7 +162,9 @@ * 'sn_coap_protocol_set_retransmission_parameters()' API. * By default value is 6. */ -#undef SN_COAP_MAX_ALLOWED_RESENDING_COUNT /* 6 */ +#ifndef SN_COAP_MAX_ALLOWED_RESENDING_COUNT +#define SN_COAP_MAX_ALLOWED_RESENDING_COUNT 6 /**< Maximum allowed count of re-sending */ +#endif /** * \def SN_COAP_MAX_ALLOWED_RESPONSE_TIMEOUT @@ -128,7 +172,9 @@ * 'sn_coap_protocol_set_retransmission_parameters()' API. * By default value is 40. */ -#undef SN_COAP_MAX_ALLOWED_RESPONSE_TIMEOUT /* 40 */ +#ifndef SN_COAP_MAX_ALLOWED_RESPONSE_TIMEOUT +#define SN_COAP_MAX_ALLOWED_RESPONSE_TIMEOUT 40 /**< Maximum allowed re-sending timeout */ +#endif /** * \def SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_MSGS @@ -136,7 +182,9 @@ * 'sn_coap_protocol_set_retransmission_buffer()' API. * By default value is 6. */ -#undef SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_MSGS /* 6 */ +#ifndef SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_MSGS +#define SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_MSGS 6 /**< Maximum allowed number of saved re-sending messages */ +#endif /** * \def SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_BYTES @@ -144,7 +192,9 @@ * 'sn_coap_protocol_set_retransmission_buffer()' API. * By default value is 512. */ -#undef SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_BYTES /* 512 */ +#ifndef SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_BYTES +#define SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_BYTES 512 /**< Maximum allowed size of re-sending buffer */ +#endif /** * \def SN_COAP_MAX_ALLOWED_DUPLICATION_MESSAGE_COUNT @@ -152,14 +202,18 @@ * that can be set via 'sn_coap_protocol_set_duplicate_buffer_size' API. * By default value is 6. */ -#undef SN_COAP_MAX_ALLOWED_DUPLICATION_MESSAGE_COUNT +#ifndef SN_COAP_MAX_ALLOWED_DUPLICATION_MESSAGE_COUNT +#define SN_COAP_MAX_ALLOWED_DUPLICATION_MESSAGE_COUNT 6 +#endif /** * \def SN_COAP_DUPLICATION_MAX_TIME_MSGS_STORED * \brief Maximum time in seconds howe long message is kept for duplicate detection. * By default 60 seconds. */ -#undef SN_COAP_DUPLICATION_MAX_TIME_MSGS_STORED +#ifndef SN_COAP_DUPLICATION_MAX_TIME_MSGS_STORED +#define SN_COAP_DUPLICATION_MAX_TIME_MSGS_STORED 60 /** RESPONSE_TIMEOUT * RESPONSE_RANDOM_FACTOR * (2 ^ MAX_RETRANSMIT - 1) + the expected maximum round trip time **/ +#endif /** * \def SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED @@ -167,17 +221,25 @@ * Longer time will increase the memory consumption in lossy networks. * By default 60 seconds. */ -#undef SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED +#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED +#define SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED MBED_CONF_MBED_CLIENT_SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED +#endif + +#ifndef SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED +#define SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED 60 /**< Maximum time in seconds of data (messages and payload) to be stored for blockwising */ +#endif /** * \def SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE * \brief Maximum size of blockwise message that can be received. * By default 65535 bytes. */ -#undef SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE +#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_MAX_INCOMING_MESSAGE_SIZE +#define SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE MBED_CONF_MBED_CLIENT_SN_COAP_MAX_INCOMING_MESSAGE_SIZE +#endif -#ifdef MBED_CLIENT_USER_CONFIG_FILE -#include MBED_CLIENT_USER_CONFIG_FILE +#ifndef SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE +#define SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE UINT16_MAX #endif #endif // SN_CONFIG_H diff --git a/features/frameworks/mbed-coap/run_unit_tests.sh b/features/frameworks/mbed-coap/run_unit_tests.sh index 797ca2c6ce..de190fe139 100755 --- a/features/frameworks/mbed-coap/run_unit_tests.sh +++ b/features/frameworks/mbed-coap/run_unit_tests.sh @@ -17,7 +17,6 @@ echo echo "Build mbed-coap C unit tests" echo -yt target x86-linux-native -yt up +make -f Makefile.test clone make -f Makefile.test test #make -f Makefile.test test clean diff --git a/features/frameworks/mbed-coap/source/include/sn_coap_protocol_internal.h b/features/frameworks/mbed-coap/source/include/sn_coap_protocol_internal.h index 0eff138331..3654684517 100644 --- a/features/frameworks/mbed-coap/source/include/sn_coap_protocol_internal.h +++ b/features/frameworks/mbed-coap/source/include/sn_coap_protocol_internal.h @@ -34,118 +34,13 @@ extern "C" { struct sn_coap_hdr_; -/* * * * * * * * * * * */ -/* * * * DEFINES * * * */ -/* * * * * * * * * * * */ - -/* * For Message resending * */ -#ifdef SN_COAP_DISABLE_RESENDINGS -#define ENABLE_RESENDINGS 0 /* Disable resendings */ -#else -#define ENABLE_RESENDINGS 1 /**< Enable / Disable resending from library in building */ -#endif - -#define SN_COAP_RESENDING_MAX_COUNT 3 /**< Default number of re-sendings */ - -#ifdef YOTTA_CFG_COAP_RESENDING_QUEUE_SIZE_MSGS -#define SN_COAP_RESENDING_QUEUE_SIZE_MSGS YOTTA_CFG_COAP_RESENDING_QUEUE_SIZE_MSGS -#elif defined MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_MSGS -#define SN_COAP_RESENDING_QUEUE_SIZE_MSGS MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_MSGS -#endif - -#ifndef SN_COAP_RESENDING_QUEUE_SIZE_MSGS -#define SN_COAP_RESENDING_QUEUE_SIZE_MSGS 2 /**< Default re-sending queue size - defines how many messages can be stored. Setting this to 0 disables feature */ -#endif - -#ifdef YOTTA_CFG_COAP_RESENDING_QUEUE_SIZE_BYTES -#define SN_COAP_RESENDING_QUEUE_SIZE_BYTES YOTTA_CFG_COAP_RESENDING_QUEUE_SIZE_BYTES -#elif defined MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_BYTES -#define SN_COAP_RESENDING_QUEUE_SIZE_BYTES MBED_CONF_MBED_CLIENT_SN_COAP_RESENDING_QUEUE_SIZE_BYTES -#endif - -#ifndef SN_COAP_RESENDING_QUEUE_SIZE_BYTES -#define SN_COAP_RESENDING_QUEUE_SIZE_BYTES 0 /**< Default re-sending queue size - defines size of the re-sending buffer. Setting this to 0 disables feature */ -#endif - -#define DEFAULT_RESPONSE_TIMEOUT 10 /**< Default re-sending timeout as seconds */ - -/* These parameters sets maximum values application can set with API */ -#define SN_COAP_MAX_ALLOWED_RESENDING_COUNT 6 /**< Maximum allowed count of re-sending */ -#define SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_MSGS 6 /**< Maximum allowed number of saved re-sending messages */ -#define SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_BYTES 512 /**< Maximum allowed size of re-sending buffer */ -#define SN_COAP_MAX_ALLOWED_RESPONSE_TIMEOUT 40 /**< Maximum allowed re-sending timeout */ - -#define RESPONSE_RANDOM_FACTOR 1.5 /**< Resending random factor, value is specified in IETF CoAP specification */ - -/* * For Message duplication detecting * */ - -/* Init value for the maximum count of messages to be stored for duplication detection */ -/* Setting of this value to 0 will disable duplication check, also reduce use of ROM memory */ -#ifdef YOTTA_CFG_COAP_DUPLICATION_MAX_MSGS_COUNT -#define SN_COAP_DUPLICATION_MAX_MSGS_COUNT YOTTA_CFG_COAP_DUPLICATION_MAX_MSGS_COUNT -#elif defined MBED_CONF_MBED_CLIENT_SN_COAP_DUPLICATION_MAX_MSGS_COUNT -#define SN_COAP_DUPLICATION_MAX_MSGS_COUNT MBED_CONF_MBED_CLIENT_SN_COAP_DUPLICATION_MAX_MSGS_COUNT -#endif - -// Keep the old flag to maintain backward compatibility -#ifndef SN_COAP_DUPLICATION_MAX_MSGS_COUNT -#define SN_COAP_DUPLICATION_MAX_MSGS_COUNT 0 -#endif - -/* Maximum allowed number of saved messages for duplicate searching */ -#define SN_COAP_MAX_ALLOWED_DUPLICATION_MESSAGE_COUNT 6 - -/* Maximum time in seconds of messages to be stored for duplication detection */ -#define SN_COAP_DUPLICATION_MAX_TIME_MSGS_STORED 60 /* RESPONSE_TIMEOUT * RESPONSE_RANDOM_FACTOR * (2 ^ MAX_RETRANSMIT - 1) + the expected maximum round trip time */ - -/* * For Message blockwising * */ - -/* Init value for the maximum payload size to be sent and received at one blockwise message */ -/* Setting of this value to 0 will disable this feature, and also reduce use of ROM memory */ -/* Note: This define is common for both received and sent Blockwise messages */ - -#ifdef YOTTA_CFG_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE -#define SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE YOTTA_CFG_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE -#elif defined MBED_CONF_MBED_CLIENT_SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE -#define SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE MBED_CONF_MBED_CLIENT_SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE -#endif - -#ifndef SN_COAP_BLOCKWISE_ENABLED -#define SN_COAP_BLOCKWISE_ENABLED 0 /**< Enable blockwise */ -#endif - -#ifndef SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE -#define SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE 0 /**< Must be 2^x and x is at least 4. Suitable values: 0, 16, 32, 64, 128, 256, 512 and 1024 */ -#endif - -#ifndef SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE -#define SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE 0 -#endif - -#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED -#define SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED MBED_CONF_MBED_CLIENT_SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED -#endif - -#ifndef SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED -#define SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED 60 /**< Maximum time in seconds of data (messages and payload) to be stored for blockwising */ -#endif - -#ifdef YOTTA_CFG_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE -#define SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE YOTTA_CFG_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE -#elif defined MBED_CONF_MBED_CLIENT_SN_COAP_MAX_INCOMING_MESSAGE_SIZE -#define SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE MBED_CONF_MBED_CLIENT_SN_COAP_MAX_INCOMING_MESSAGE_SIZE -#endif - -#ifndef SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE -#define SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE UINT16_MAX -#endif +#define RESPONSE_RANDOM_FACTOR 1.5 /**< Resending random factor, value is specified in IETF CoAP specification */ /* * For Option handling * */ #define COAP_OPTION_MAX_AGE_DEFAULT 60 /**< Default value of Max-Age if option not present */ #define COAP_OPTION_URI_PORT_NONE (-1) /**< Internal value to represent no Uri-Port option */ #define COAP_OPTION_BLOCK_NONE (-1) /**< Internal value to represent no Block1/2 option */ - int8_t prepare_blockwise_message(struct coap_s *handle, struct sn_coap_hdr_ *coap_hdr_ptr); /* Structure which is stored to Linked list for message sending purposes */ diff --git a/features/frameworks/mbed-coap/source/sn_coap_protocol.c b/features/frameworks/mbed-coap/source/sn_coap_protocol.c index 0a87eb3f1a..773216bf29 100644 --- a/features/frameworks/mbed-coap/source/sn_coap_protocol.c +++ b/features/frameworks/mbed-coap/source/sn_coap_protocol.c @@ -738,7 +738,10 @@ sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src (returned_dst_coap_msg_ptr->options_list_ptr->block1 != COAP_OPTION_BLOCK_NONE || returned_dst_coap_msg_ptr->options_list_ptr->block2 != COAP_OPTION_BLOCK_NONE)) { returned_dst_coap_msg_ptr = sn_coap_handle_blockwise_message(handle, src_addr_ptr, returned_dst_coap_msg_ptr, param); - } else { + } else if (returned_dst_coap_msg_ptr->msg_code != COAP_MSG_CODE_EMPTY) { + // Do not clean stored blockwise message when empty ack is received. + // Stored message is mandatory when building a next (GET) blockwise message. + // This will happen when non piggybacked response mode is selected. /* Get ... */ coap_blockwise_msg_s *stored_blockwise_msg_temp_ptr = NULL; From de35a15b058784bfba975c5a0e461454074dfdc6 Mon Sep 17 00:00:00 2001 From: Hasnain Virk Date: Wed, 13 Feb 2019 16:56:29 +0200 Subject: [PATCH 054/109] Reverting to original doxy configuration This commit essentially brings back old code. We did an attempt to resolve doxy issues with nfc durint docathlon, but it introduced more issues and yak shaving rather than being a useful exercise. Unfortunately the previous attempt got merged. This commit attempts to restore the style maintained by original developers. From here they can take over. --- features/nfc/nfc/NFCController.h | 4 +--- features/nfc/nfc/NFCEEPROM.h | 4 +--- features/nfc/nfc/ndef/MessageBuilder.h | 4 +--- features/nfc/nfc/ndef/MessageParser.h | 4 +--- features/nfc/nfc/ndef/common/SimpleMessageParser.h | 4 +--- 5 files changed, 5 insertions(+), 15 deletions(-) diff --git a/features/nfc/nfc/NFCController.h b/features/nfc/nfc/NFCController.h index 945d248811..df55292f13 100644 --- a/features/nfc/nfc/NFCController.h +++ b/features/nfc/nfc/NFCController.h @@ -1,6 +1,4 @@ -/** @file NFCController.h - * - * mbed Microcontroller Library +/* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/features/nfc/nfc/NFCEEPROM.h b/features/nfc/nfc/NFCEEPROM.h index b06c2836a7..ed0deb301d 100644 --- a/features/nfc/nfc/NFCEEPROM.h +++ b/features/nfc/nfc/NFCEEPROM.h @@ -1,6 +1,4 @@ -/** @file NFCEEPROM.h - * - * mbed Microcontroller Library +/* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/features/nfc/nfc/ndef/MessageBuilder.h b/features/nfc/nfc/ndef/MessageBuilder.h index 2564675897..1b4e38e0d4 100644 --- a/features/nfc/nfc/ndef/MessageBuilder.h +++ b/features/nfc/nfc/ndef/MessageBuilder.h @@ -1,6 +1,4 @@ -/** @file MessageBuilder.h - * - * mbed Microcontroller Library +/* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/features/nfc/nfc/ndef/MessageParser.h b/features/nfc/nfc/ndef/MessageParser.h index 55a0e6e5fd..a0ac9391ed 100644 --- a/features/nfc/nfc/ndef/MessageParser.h +++ b/features/nfc/nfc/ndef/MessageParser.h @@ -1,6 +1,4 @@ -/** @file MessageParser.h - * - * mbed Microcontroller Library +/* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/features/nfc/nfc/ndef/common/SimpleMessageParser.h b/features/nfc/nfc/ndef/common/SimpleMessageParser.h index 7ba7e9db91..2f7bbbc274 100644 --- a/features/nfc/nfc/ndef/common/SimpleMessageParser.h +++ b/features/nfc/nfc/ndef/common/SimpleMessageParser.h @@ -1,6 +1,4 @@ -/** @file SimpleMessageParser.h - * - * mbed Microcontroller Library +/* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); From c71f1d46248115d2203f5109a56c6bbdd2e346a2 Mon Sep 17 00:00:00 2001 From: Nicolas Graziano Date: Sat, 9 Feb 2019 19:23:56 +0100 Subject: [PATCH 055/109] Fix IntelliSense in VSCode export Allow to use default intelliSenseEngine in visual studio code. Add of compilerPath and forcedInclude of mbed_config header in the created c_cpp_properties.json file. --- tools/export/vscode/__init__.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tools/export/vscode/__init__.py b/tools/export/vscode/__init__.py index 9cfa1f4836..0ea77e79b5 100644 --- a/tools/export/vscode/__init__.py +++ b/tools/export/vscode/__init__.py @@ -67,16 +67,29 @@ class VSCode(Makefile): "configurations": [ { "name": "Windows", + "forcedInclude": [ + "${workspaceRoot}\\mbed_config.h" + ], + "compilerPath": self.toolchain.cppc[0], + "intelliSenseMode": "gcc-x64", "includePath": [x.replace("/", "\\") for x in all_directories], "defines": [symbol for symbol in self.toolchain.get_symbols()] }, { "name": "Mac", + "forcedInclude": [ + "${workspaceRoot}\\mbed_config.h" + ], + "compilerPath": self.toolchain.cppc[0], "includePath": all_directories, "defines": [symbol for symbol in self.toolchain.get_symbols()] }, { "name": "Linux", + "forcedInclude": [ + "${workspaceRoot}\\mbed_config.h" + ], + "compilerPath": self.toolchain.cppc[0], "includePath": all_directories, "defines": [symbol for symbol in self.toolchain.get_symbols()] } From a47683069d71e32b12f1e05b9d575c4e3f5a19e8 Mon Sep 17 00:00:00 2001 From: Nicolas Graziano Date: Mon, 11 Feb 2019 14:45:34 +0100 Subject: [PATCH 056/109] Vscode export: remove path separator conversion VSCode handle "/" and it is easier to read. --- tools/export/vscode/__init__.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/export/vscode/__init__.py b/tools/export/vscode/__init__.py index 0ea77e79b5..efa92b3c9a 100644 --- a/tools/export/vscode/__init__.py +++ b/tools/export/vscode/__init__.py @@ -68,17 +68,17 @@ class VSCode(Makefile): { "name": "Windows", "forcedInclude": [ - "${workspaceRoot}\\mbed_config.h" + "${workspaceRoot}/mbed_config.h" ], "compilerPath": self.toolchain.cppc[0], "intelliSenseMode": "gcc-x64", - "includePath": [x.replace("/", "\\") for x in all_directories], + "includePath": all_directories, "defines": [symbol for symbol in self.toolchain.get_symbols()] }, { "name": "Mac", "forcedInclude": [ - "${workspaceRoot}\\mbed_config.h" + "${workspaceRoot}/mbed_config.h" ], "compilerPath": self.toolchain.cppc[0], "includePath": all_directories, @@ -87,7 +87,7 @@ class VSCode(Makefile): { "name": "Linux", "forcedInclude": [ - "${workspaceRoot}\\mbed_config.h" + "${workspaceRoot}/mbed_config.h" ], "compilerPath": self.toolchain.cppc[0], "includePath": all_directories, From a245a177030f94959a8a8ae7fe9096ef9f3c6a0e Mon Sep 17 00:00:00 2001 From: Nicolas Graziano Date: Mon, 11 Feb 2019 14:52:02 +0100 Subject: [PATCH 057/109] Vscode export: replace obsolete ${workspaceRoot} Replace with ${workspaceFolder} --- tools/export/vscode/__init__.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/export/vscode/__init__.py b/tools/export/vscode/__init__.py index efa92b3c9a..5765adbb95 100644 --- a/tools/export/vscode/__init__.py +++ b/tools/export/vscode/__init__.py @@ -59,16 +59,16 @@ class VSCode(Makefile): continue if directory == ".": - all_directories.append("${workspaceRoot}/*") + all_directories.append("${workspaceFolder}/*") else: - all_directories.append(directory.replace("./", "${workspaceRoot}/") + "/*") + all_directories.append(directory.replace("./", "${workspaceFolder}/") + "/*") cpp_props = { "configurations": [ { "name": "Windows", "forcedInclude": [ - "${workspaceRoot}/mbed_config.h" + "${workspaceFolder}/mbed_config.h" ], "compilerPath": self.toolchain.cppc[0], "intelliSenseMode": "gcc-x64", @@ -78,7 +78,7 @@ class VSCode(Makefile): { "name": "Mac", "forcedInclude": [ - "${workspaceRoot}/mbed_config.h" + "${workspaceFolder}/mbed_config.h" ], "compilerPath": self.toolchain.cppc[0], "includePath": all_directories, @@ -87,7 +87,7 @@ class VSCode(Makefile): { "name": "Linux", "forcedInclude": [ - "${workspaceRoot}/mbed_config.h" + "${workspaceFolder}/mbed_config.h" ], "compilerPath": self.toolchain.cppc[0], "includePath": all_directories, From 0b8bcb05d539be3b3a4e82b59f9e7922680bba84 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Thu, 24 Jan 2019 18:22:32 +0000 Subject: [PATCH 058/109] readme: add list of licenses - not Apache 2.0 Name all folders containing different liceses. Any new file not Apache 2.0 should be captured here. --- README.md | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/README.md b/README.md index 59d8fcc7e3..075350c5fb 100644 --- a/README.md +++ b/README.md @@ -33,6 +33,28 @@ The software is provided under [Apache-2.0 license](LICENSE). Contributions to t This project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/latest/reference/license.html) +Folders containing files not under Apache 2.0 as listed above. The original license text is included in those source files. + +- cmsis - MIT/BSD-3-Clause +- components/802.15.4_RF/mcr20a-rf-driver - BSD-3-Clause +- features/cryptocell/FEATURE_CRYPTOCELL310 - BSD-style +- features/FEATURE_BOOTLOADER - PBL +- features/FEATURE_BLE/targets - BSD-style/PBL/MIT +- features/lorawan - Revised BSD +- features/lwipstack - BSD-3-Clause/MIT +- features/nanostack/sal-stack-nanostack - BSD-3-Clause +- features/storage/FEATURE_STORAGE - BSD-style +- features/storage/blockdevice - MIT +- features/storage/filesystem/littlefs - BSD-3-Clause +- features/storage/filesystem/fat - MIT/BSD-style +- features/netsocket/emac-drivers - BSD-3-Clause +- features/frameworks/unity/unity - MIT +- rtos - MIT +- drivers - MIT +- TESTS/mbed_hal/trng/pithy - BSD-3-Clause +- tools/data/rpc - MIT +- targets - PBL/BSD-style/MIT/Zlib + ## Getting started for developers We have a [developer website](https://os.mbed.com) for asking questions, engaging with others, finding information on boards and components, using an online IDE and compiler, reading the documentation and learning about what's new and what's coming next in Mbed OS. From fabf99f7a743636bef02626c3554900583f55ed2 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Tue, 12 Feb 2019 10:13:32 +0000 Subject: [PATCH 059/109] readme: license update Fix licenses based on latest Fossology scan. Using -style licenses for specific type licenses Add paths to the readme. --- README.md | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/README.md b/README.md index 075350c5fb..da335abb13 100644 --- a/README.md +++ b/README.md @@ -33,27 +33,28 @@ The software is provided under [Apache-2.0 license](LICENSE). Contributions to t This project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/latest/reference/license.html) -Folders containing files not under Apache 2.0 as listed above. The original license text is included in those source files. +Folders containing files not under Apache 2.0 as listed above (each folder should contain own README file with license specified for its files). The original license text is included in those source files. -- cmsis - MIT/BSD-3-Clause -- components/802.15.4_RF/mcr20a-rf-driver - BSD-3-Clause -- features/cryptocell/FEATURE_CRYPTOCELL310 - BSD-style -- features/FEATURE_BOOTLOADER - PBL -- features/FEATURE_BLE/targets - BSD-style/PBL/MIT -- features/lorawan - Revised BSD -- features/lwipstack - BSD-3-Clause/MIT -- features/nanostack/sal-stack-nanostack - BSD-3-Clause -- features/storage/FEATURE_STORAGE - BSD-style -- features/storage/blockdevice - MIT -- features/storage/filesystem/littlefs - BSD-3-Clause -- features/storage/filesystem/fat - MIT/BSD-style -- features/netsocket/emac-drivers - BSD-3-Clause -- features/frameworks/unity/unity - MIT -- rtos - MIT -- drivers - MIT -- TESTS/mbed_hal/trng/pithy - BSD-3-Clause -- tools/data/rpc - MIT -- targets - PBL/BSD-style/MIT/Zlib +- [cmsis](./cmsis) - MIT, BSD-3-Clause +- [components/802.15.4_RF/mcr20a-rf-driver](./components/802.15.4_RF/mcr20a-rf-driver) - BSD-3-Clause +- [features/cryptocell/FEATURE_CRYPTOCELL310](./features/cryptocell/FEATURE_CRYPTOCELL310) - ARM Object Code and Header Files License +- [features/FEATURE_BOOTLOADER](./features/FEATURE_BOOTLOADER) - PBL +- [features/FEATURE_BLE/targets](./features/FEATURE_BLE/targets) - BSD-style, PBL, MIT-style +- [features/lorawan](./features/lorawan) - Revised BSD +- [features/lwipstack](./features/lwipstack) - BSD-style, MIT-style +- [features/nanostack/sal-stack-nanostack](./features/nanostack/sal-stack-nanostack) - BSD-3-Clause +- [features/storage/FEATURE_STORAGE](./features/storage/FEATURE_STORAGE) - BSD-style +- [features/storage/blockdevice](./features/storage/blockdevice) - MIT +- [features/storage/filesystem/littlefs](./features/storage/filesystem/littlefs) - BSD-3-Clause +- [features/storage/filesystem/fat](./features/storage/filesystem/fat) - MIT, BSD-style +- [features/netsocket/emac-drivers](./features/netsocket/emac-drivers) - BSD-style +- [features/frameworks/unity/unity](./features/frameworks/unity/unity) - MIT +- [features/unsupported](./features/unsupported) - MIT-style, BSD-style +- [rtos](./rtos) - MIT +- [drivers](./drivers) - MIT +- [TESTS/mbed_hal/trng/pithy](./TESTS/mbed_hal/trng/pithy) - BSD-3-Clause +- [tools/data/rpc](./tools/data/rpc) - MIT +- [targets](./targets) - PBL, BSD-style, MIT-style, Zlib-style, Public-domain ## Getting started for developers From f2897a99ca0b949aa8791a62dab3e4386c76bef3 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Tue, 12 Feb 2019 10:21:55 +0000 Subject: [PATCH 060/109] readme: storage license under one folder --- README.md | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/README.md b/README.md index da335abb13..13b277e6d6 100644 --- a/README.md +++ b/README.md @@ -43,10 +43,7 @@ Folders containing files not under Apache 2.0 as listed above (each folder shoul - [features/lorawan](./features/lorawan) - Revised BSD - [features/lwipstack](./features/lwipstack) - BSD-style, MIT-style - [features/nanostack/sal-stack-nanostack](./features/nanostack/sal-stack-nanostack) - BSD-3-Clause -- [features/storage/FEATURE_STORAGE](./features/storage/FEATURE_STORAGE) - BSD-style -- [features/storage/blockdevice](./features/storage/blockdevice) - MIT -- [features/storage/filesystem/littlefs](./features/storage/filesystem/littlefs) - BSD-3-Clause -- [features/storage/filesystem/fat](./features/storage/filesystem/fat) - MIT, BSD-style +- [features/storage](./features/storage) - BSD-style, MIT - [features/netsocket/emac-drivers](./features/netsocket/emac-drivers) - BSD-style - [features/frameworks/unity/unity](./features/frameworks/unity/unity) - MIT - [features/unsupported](./features/unsupported) - MIT-style, BSD-style From 656ab6e89c3b3e017d794ea1b12bcc77fc007189 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Wed, 13 Feb 2019 11:25:59 +0000 Subject: [PATCH 061/109] license: rename to apache 2.0 txt file --- LICENSE => LICENSE-apache-2.0.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename LICENSE => LICENSE-apache-2.0.txt (100%) diff --git a/LICENSE b/LICENSE-apache-2.0.txt similarity index 100% rename from LICENSE rename to LICENSE-apache-2.0.txt From 0c104f2155232ad1cafc584dec70ebabd0669b54 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Wed, 13 Feb 2019 11:29:46 +0000 Subject: [PATCH 062/109] license: add license file containing folders with non apache license --- LICENSE | 22 ++++++++++++++++++++++ README.md | 22 ++-------------------- 2 files changed, 24 insertions(+), 20 deletions(-) create mode 100644 LICENSE diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000000..efda07b093 --- /dev/null +++ b/LICENSE @@ -0,0 +1,22 @@ +Unless specifically indicated otherwise in a file, files are licensed under the Apache 2.0 license, +as can be found in: LICENSE-apache-2.0.txt + +Folders containing files under different permissive license than Apache 2.0 are listed below. Eeach folder should contain own README file with license specified for its files. The original license text is included in those source files. + +- [cmsis](./cmsis) - MIT, BSD-3-Clause +- [components/802.15.4_RF/mcr20a-rf-driver](./components/802.15.4_RF/mcr20a-rf-driver) - BSD-3-Clause +- [features/cryptocell/FEATURE_CRYPTOCELL310](./features/cryptocell/FEATURE_CRYPTOCELL310) - ARM Object Code and Header Files License +- [features/FEATURE_BOOTLOADER](./features/FEATURE_BOOTLOADER) - PBL +- [features/FEATURE_BLE/targets](./features/FEATURE_BLE/targets) - BSD-style, PBL, MIT-style +- [features/lorawan](./features/lorawan) - Revised BSD +- [features/lwipstack](./features/lwipstack) - BSD-style, MIT-style +- [features/nanostack/sal-stack-nanostack](./features/nanostack/sal-stack-nanostack) - BSD-3-Clause +- [features/storage](./features/storage) - BSD-style, MIT +- [features/netsocket/emac-drivers](./features/netsocket/emac-drivers) - BSD-style +- [features/frameworks/unity/unity](./features/frameworks/unity/unity) - MIT +- [features/unsupported](./features/unsupported) - MIT-style, BSD-style +- [rtos](./rtos) - MIT +- [drivers](./drivers) - MIT +- [TESTS/mbed_hal/trng/pithy](./TESTS/mbed_hal/trng/pithy) - BSD-3-Clause +- [tools/data/rpc](./tools/data/rpc) - MIT +- [targets](./targets) - PBL, BSD-style, MIT-style, Zlib-style, Public-domain diff --git a/README.md b/README.md index 13b277e6d6..308b66860e 100644 --- a/README.md +++ b/README.md @@ -29,29 +29,11 @@ The [release notes](https://os.mbed.com/releases) detail the current release. Yo ## License and contributions -The software is provided under [Apache-2.0 license](LICENSE). Contributions to this project are accepted under the same license. Please see [contributing.md](CONTRIBUTING.md) for more info. +The software is provided under [Apache-2.0 license](LICENSE-apache-2.0.txt). Contributions to this project are accepted under the same license. Please see [contributing.md](CONTRIBUTING.md) for more info. This project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/latest/reference/license.html) -Folders containing files not under Apache 2.0 as listed above (each folder should contain own README file with license specified for its files). The original license text is included in those source files. - -- [cmsis](./cmsis) - MIT, BSD-3-Clause -- [components/802.15.4_RF/mcr20a-rf-driver](./components/802.15.4_RF/mcr20a-rf-driver) - BSD-3-Clause -- [features/cryptocell/FEATURE_CRYPTOCELL310](./features/cryptocell/FEATURE_CRYPTOCELL310) - ARM Object Code and Header Files License -- [features/FEATURE_BOOTLOADER](./features/FEATURE_BOOTLOADER) - PBL -- [features/FEATURE_BLE/targets](./features/FEATURE_BLE/targets) - BSD-style, PBL, MIT-style -- [features/lorawan](./features/lorawan) - Revised BSD -- [features/lwipstack](./features/lwipstack) - BSD-style, MIT-style -- [features/nanostack/sal-stack-nanostack](./features/nanostack/sal-stack-nanostack) - BSD-3-Clause -- [features/storage](./features/storage) - BSD-style, MIT -- [features/netsocket/emac-drivers](./features/netsocket/emac-drivers) - BSD-style -- [features/frameworks/unity/unity](./features/frameworks/unity/unity) - MIT -- [features/unsupported](./features/unsupported) - MIT-style, BSD-style -- [rtos](./rtos) - MIT -- [drivers](./drivers) - MIT -- [TESTS/mbed_hal/trng/pithy](./TESTS/mbed_hal/trng/pithy) - BSD-3-Clause -- [tools/data/rpc](./tools/data/rpc) - MIT -- [targets](./targets) - PBL, BSD-style, MIT-style, Zlib-style, Public-domain +Folders containing files under different permissive license than Apache 2.0 are listed in LICENSE file. ## Getting started for developers From f68aa8cd474b75f1452621cf5b0b084c8b6ff798 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Wed, 13 Feb 2019 14:06:49 +0000 Subject: [PATCH 063/109] readme: license file reference fix --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 308b66860e..970aeb1331 100644 --- a/README.md +++ b/README.md @@ -33,7 +33,7 @@ The software is provided under [Apache-2.0 license](LICENSE-apache-2.0.txt). Con This project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/latest/reference/license.html) -Folders containing files under different permissive license than Apache 2.0 are listed in LICENSE file. +Folders containing files under different permissive license than Apache 2.0 are listed in [LICENSE](LICENSE) file. ## Getting started for developers From 22a288d489b184d0816154e15833e5fcda0540f8 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Thu, 14 Feb 2019 10:39:14 +0000 Subject: [PATCH 064/109] readme: fix space and . in license --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 970aeb1331..3e3d985518 100644 --- a/README.md +++ b/README.md @@ -29,9 +29,9 @@ The [release notes](https://os.mbed.com/releases) detail the current release. Yo ## License and contributions -The software is provided under [Apache-2.0 license](LICENSE-apache-2.0.txt). Contributions to this project are accepted under the same license. Please see [contributing.md](CONTRIBUTING.md) for more info. +The software is provided under [Apache-2.0 license](LICENSE-apache-2.0.txt). Contributions to this project are accepted under the same license. Please see [contributing.md](CONTRIBUTING.md) for more info. -This project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/latest/reference/license.html) +This project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/latest/reference/license.html). Folders containing files under different permissive license than Apache 2.0 are listed in [LICENSE](LICENSE) file. From 38fa21d9d65b3c74cdf29d5e10c0156f21e0465b Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Fri, 15 Feb 2019 13:58:14 -0600 Subject: [PATCH 065/109] Fix typo in LICENSE Fix typo as requested in comments. --- LICENSE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/LICENSE b/LICENSE index efda07b093..4522260636 100644 --- a/LICENSE +++ b/LICENSE @@ -1,7 +1,7 @@ Unless specifically indicated otherwise in a file, files are licensed under the Apache 2.0 license, as can be found in: LICENSE-apache-2.0.txt -Folders containing files under different permissive license than Apache 2.0 are listed below. Eeach folder should contain own README file with license specified for its files. The original license text is included in those source files. +Folders containing files under different permissive license than Apache 2.0 are listed below. Each folder should contain its own README file with license specified for its files. The original license text is included in those source files. - [cmsis](./cmsis) - MIT, BSD-3-Clause - [components/802.15.4_RF/mcr20a-rf-driver](./components/802.15.4_RF/mcr20a-rf-driver) - BSD-3-Clause From 4a58fa1e26f8ce0b76477785db080c9c1ac39bfb Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Fri, 15 Feb 2019 14:05:29 -0600 Subject: [PATCH 066/109] Add articles to README.md Include articles for clarity. --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 3e3d985518..bed98b0caf 100644 --- a/README.md +++ b/README.md @@ -29,11 +29,11 @@ The [release notes](https://os.mbed.com/releases) detail the current release. Yo ## License and contributions -The software is provided under [Apache-2.0 license](LICENSE-apache-2.0.txt). Contributions to this project are accepted under the same license. Please see [contributing.md](CONTRIBUTING.md) for more info. +The software is provided under the [Apache-2.0 license](LICENSE-apache-2.0.txt). Contributions to this project are accepted under the same license. Please see [contributing.md](CONTRIBUTING.md) for more information. This project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/latest/reference/license.html). -Folders containing files under different permissive license than Apache 2.0 are listed in [LICENSE](LICENSE) file. +Folders containing files under different permissive license than Apache 2.0 are listed in the [LICENSE](LICENSE) file. ## Getting started for developers From 783485f3b7ff7a5f426932912cbba8f0e0d35db3 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Thu, 14 Feb 2019 14:44:51 -0600 Subject: [PATCH 067/109] Remove pyocd requirement and update icetea. Icetea depends on mbed-flasher. mbed-flasher recently released a version that drops the dependency on pyocd. Icetea released a version that uses this latest version of mbed-flasher. So now tht pyocd is no longer in our dependency tree, we can drop it here. --- requirements.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/requirements.txt b/requirements.txt index f6459351c0..de08793b17 100644 --- a/requirements.txt +++ b/requirements.txt @@ -20,5 +20,4 @@ beautifulsoup4>=4,<=4.6.3 fuzzywuzzy>=0.11,<=0.17 pyelftools>=0.24,<=0.25 git+https://github.com/armmbed/manifest-tool.git@v1.4.6 -pyocd>=0.14,<0.15 -icetea>=1.0.2,<1.1 +icetea>=1.2.1,<1.3 From da5c3a84f6fec7dc4fb03ccdcf6a02ea9263ffcb Mon Sep 17 00:00:00 2001 From: Naveen Kaje Date: Fri, 15 Feb 2019 11:02:57 -0600 Subject: [PATCH 068/109] tools: export: MCUXpresso: fix case inconsistencies in .templ file names The templ file names are both all upper case and lower case letters. The Target Names map is usually all upper case. The match could fail if the templ file, as we have case-sensitive comparison. Handle such cases by perorming a case-insensitve check. mbed export of a project to MCUXpresso could potentially always fail irrespective of what is passed in -m option since the target names map entry and the filename may not match. This commit fixes this issue. Example of the issue that this commit fixes: $ mbed export -i mcuxpresso -m lpc11u68 -v project.py: error: LPC11U68 not supported by mcuxpresso --- tools/export/mcuxpresso/__init__.py | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/tools/export/mcuxpresso/__init__.py b/tools/export/mcuxpresso/__init__.py index 52e1f77c94..54a2db4313 100644 --- a/tools/export/mcuxpresso/__init__.py +++ b/tools/export/mcuxpresso/__init__.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2016 ARM Limited +Copyright (c) 2011-2019 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -28,9 +28,10 @@ from builtins import str import copy import tempfile import shutil +import re from subprocess import Popen, PIPE -from os import getcwd, remove +from os import getcwd, remove, listdir from os.path import splitext, basename, exists from random import randint @@ -54,10 +55,19 @@ class MCUXpresso(GNUARMEclipse): MBED_CONFIG_HEADER_SUPPORTED = True + @staticmethod + def is_target_name_in_dir(path, target_name): + # toos/export/mcuxpresso/ has entries with + # both lower and upper case. Handle these inconsistencies. + for entry in listdir(path): + if(re.match(entry, target_name + '_cproject.tmpl', re.IGNORECASE)): + return True + return False + @classmethod def is_target_supported(cls, target_name): # target is supported when *_cproject.tmpl template file exists - if exists(cls.TEMPLATE_DIR + '/mcuxpresso/' + target_name + '_cproject.tmpl'): + if MCUXpresso.is_target_name_in_dir(cls.TEMPLATE_DIR + '/mcuxpresso/', target_name): target = TARGET_MAP[target_name] return apply_supported_whitelist( cls.TOOLCHAIN, POST_BINARY_WHITELIST, target) From 6be5ad09f2db83faf432d450a1660d4a80e4bab4 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Fri, 15 Feb 2019 17:33:21 +0200 Subject: [PATCH 069/109] ESP8266: connect() returns OK in non-blocking calls --- components/wifi/esp8266-driver/ESP8266Interface.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/components/wifi/esp8266-driver/ESP8266Interface.cpp b/components/wifi/esp8266-driver/ESP8266Interface.cpp index 1f3ea4b592..f3e7d4b7de 100644 --- a/components/wifi/esp8266-driver/ESP8266Interface.cpp +++ b/components/wifi/esp8266-driver/ESP8266Interface.cpp @@ -253,7 +253,11 @@ int ESP8266Interface::connect() _cmutex.unlock(); - return _connect_retval; + if (!_if_blocking) { + return NSAPI_ERROR_OK; + } else { + return _connect_retval; + } } int ESP8266Interface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) From 631acd4ac8d03cd4116fa9c13b61b3bd83e2ac27 Mon Sep 17 00:00:00 2001 From: Marcin Tomczyk Date: Wed, 9 Jan 2019 13:07:36 +0100 Subject: [PATCH 070/109] ONME-3949 Configuration options for STM_EMAC buffer counts --- .../emac-drivers/TARGET_STM_EMAC/mbed_lib.json | 13 +++++++++++++ .../TARGET_STM32F1/device/stm32f1xx_hal_conf.h | 10 ++++++++-- .../TARGET_STM32F2/device/stm32f2xx_hal_conf.h | 10 ++++++++-- .../TARGET_STM32F4/device/stm32f4xx_hal_conf.h | 10 ++++++++-- .../TARGET_STM32F7/device/stm32f7xx_hal_conf.h | 9 +++++++-- 5 files changed, 44 insertions(+), 8 deletions(-) create mode 100644 features/netsocket/emac-drivers/TARGET_STM_EMAC/mbed_lib.json diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/mbed_lib.json b/features/netsocket/emac-drivers/TARGET_STM_EMAC/mbed_lib.json new file mode 100644 index 0000000000..39ae08e4a4 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/mbed_lib.json @@ -0,0 +1,13 @@ +{ + "name": "stm32-emac", + "config": { + "eth-rxbufnb": 4, + "eth-txbufnb": 4 + }, + "target_overrides": { + "NUCLEO_F207ZG": { + "eth-rxbufnb": 1, + "eth-txbufnb": 4 + } + } +} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h index 55aad36197..3bfc9a065b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h @@ -164,8 +164,14 @@ extern "C" { /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB +#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + +#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB +#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */ +#endif /* Section 2: PHY configuration section */ diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h index 23c209ca62..2ca8e308ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h @@ -175,8 +175,14 @@ /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB +#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + +#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB +#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */ +#endif /* Section 2: PHY configuration section */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h index 44179a7e50..5d7d9caec6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h @@ -183,8 +183,14 @@ /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB +#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + +#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB +#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */ +#endif /* Section 2: PHY configuration section */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h index f484b45c73..c3c9080c3f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h @@ -189,9 +189,14 @@ /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB +#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + +#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB +#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */ +#endif /* Section 2: PHY configuration section */ /* DP83848 PHY Address*/ From 1f5fdbc43b12168c4c746cc658e031b361c54084 Mon Sep 17 00:00:00 2001 From: Desmond Chen Date: Tue, 19 Feb 2019 14:19:44 +0800 Subject: [PATCH 071/109] BLE:Cordio: ATTS setting for write cback should use bitwise or --- .../targets/TARGET_CORDIO/source/CordioGattServer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp index 8a096aab26..e553256087 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp @@ -294,7 +294,7 @@ ble_error_t GattServer::insert_characteristic_value_attribute( attribute_it->settings = ATTS_SET_READ_CBACK; } if (properties & WRITABLE_PROPERTIES) { - attribute_it->settings = ATTS_SET_WRITE_CBACK; + attribute_it->settings |= ATTS_SET_WRITE_CBACK; } if (value_attribute.getUUID().shortOrLong() == UUID::UUID_TYPE_LONG) { attribute_it->settings |= ATTS_SET_UUID_128; From dae6a757eabe510affa316e53d44e9f91063b642 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Fri, 15 Feb 2019 11:37:00 +0200 Subject: [PATCH 072/109] Greentea: Remove TLSSocket_simultaneous test The reason is that some platforms lack memory to run it. To be brought back once TLS library memory consumption is optimized. --- TESTS/netsocket/tls/main.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/TESTS/netsocket/tls/main.cpp b/TESTS/netsocket/tls/main.cpp index 0e7316a9e3..9ee0dfee56 100644 --- a/TESTS/netsocket/tls/main.cpp +++ b/TESTS/netsocket/tls/main.cpp @@ -195,9 +195,12 @@ Case cases[] = { Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT), Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT), Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT), -#ifndef __IAR_SYSTEMS_ICC__ - Case("TLSSOCKET_SIMULTANEOUS", TLSSOCKET_SIMULTANEOUS) -#endif +// Temporarily removing this test, as TLS library consumes too much memory +// and we see frequent memory allocation failures on architectures with less +// RAM such as DISCO_L475VG_IOT1A and NUCLEO_F207ZG (both have 128 kB RAM) +// This test also fails for IAR, due to wrong heap configuration in the linker +// script - see https://github.com/ARMmbed/mbed-os/issues/8306 +// Case("TLSSOCKET_SIMULTANEOUS", TLSSOCKET_SIMULTANEOUS) }; Specification specification(greentea_setup, cases, greentea_teardown, greentea_continue_handlers); From fb4441ffc05eca7833d11d3ab1283fe8fb19109c Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Tue, 19 Feb 2019 11:58:19 +0200 Subject: [PATCH 073/109] Update Nanostack_HAL licenses and copyright year -Add Apache License to files that were missing a licence -Update copyright year --- .../arm_hal_fhss_timer.cpp | 13 +++++++------ .../arm_hal_interrupt.c | 13 +++++++------ .../arm_hal_interrupt_private.h | 13 +++++++------ .../arm_hal_random.c | 13 +++++++------ .../arm_hal_timer.cpp | 13 +++++++------ .../nanostack-hal-mbed-cmsis-rtos/cs_nvm/cs_nvm.c | 13 +++++++------ .../unittest/cs_nvm/csnvmtest.cpp | 15 ++++++++++++++- .../test_cs_nvm_unit/unittest/cs_nvm/main.cpp | 15 ++++++++++++++- .../unittest/cs_nvm/test_cs_nvm.c | 15 ++++++++++++++- .../unittest/cs_nvm/test_cs_nvm.h | 15 ++++++++++++++- .../unittest/stubs/configuration_store_stub.c | 15 ++++++++++++++- .../unittest/stubs/configuration_store_stub.h | 15 ++++++++++++++- .../unittest/stubs/ns_trace_stub.c | 15 ++++++++++++++- .../unittest/stubs/nsdynmemLIB_stub.c | 15 ++++++++++++++- .../unittest/stubs/nsdynmemLIB_stub.h | 15 ++++++++++++++- .../unittest/stubs/timeout_stub.c | 15 ++++++++++++++- .../nanostack-hal-mbed-cmsis-rtos/ns_event_loop.c | 13 +++++++------ .../nanostack-hal-mbed-cmsis-rtos/ns_event_loop.h | 13 +++++++------ .../ns_event_loop_mbed.cpp | 13 +++++++------ .../ns_event_loop_mutex.c | 13 +++++++------ .../ns_event_loop_mutex.h | 13 +++++++------ .../nanostack-hal-mbed-cmsis-rtos/ns_hal_init.c | 13 +++++++------ .../nanostack-hal-mbed-cmsis-rtos/ns_hal_init.h | 13 +++++++------ .../nanostack-hal-mbed-cmsis-rtos/nvm/nvm_ram.c | 15 ++++++++++++++- 24 files changed, 245 insertions(+), 89 deletions(-) diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_fhss_timer.cpp b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_fhss_timer.cpp index ca9bc0a338..e5aa08f8f8 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_fhss_timer.cpp +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_fhss_timer.cpp @@ -1,15 +1,16 @@ /* - * Copyright (c) 2018 ARM Limited. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c index e09dd3e8bf..519e3995b9 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt.c @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016-2018 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt_private.h b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt_private.h index 586e2e9604..6bea5dcd07 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt_private.h +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_interrupt_private.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016-2018 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_random.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_random.c index 2def6c4f16..7ba0aae6f8 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_random.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_random.c @@ -1,15 +1,16 @@ /* - * Copyright (c) 2015 ARM Limited. All rights reserved. + * Copyright (c) 2015, 2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_timer.cpp b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_timer.cpp index 7aeb13f334..c7952d1be9 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_timer.cpp +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_timer.cpp @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016-2018 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/cs_nvm.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/cs_nvm.c index bdd77358f6..4b9eed9f93 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/cs_nvm.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/cs_nvm.c @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/csnvmtest.cpp b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/csnvmtest.cpp index 4393ca4ad6..ee1e1881c5 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/csnvmtest.cpp +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/csnvmtest.cpp @@ -1,5 +1,18 @@ /* - * Copyright (c) 2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "CppUTest/TestHarness.h" diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/main.cpp b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/main.cpp index cc82213e17..d6a8a5740c 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/main.cpp +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/main.cpp @@ -1,5 +1,18 @@ /* - * Copyright (c) 2015 ARM Limited. All rights reserved. + * Copyright (c) 2015, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "CppUTest/CommandLineTestRunner.h" diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.c index ced1cec5e8..915a82ea5e 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.c @@ -1,5 +1,18 @@ /* - * Copyright (c) 2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.h b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.h index 36155af9f6..b14537ddd6 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.h +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/cs_nvm/test_cs_nvm.h @@ -1,5 +1,18 @@ /* - * Copyright (c) 2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef TEST_NS_NVM_HELPER_H #define TEST_NS_NVM_HELPER_H diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.c index e00ead2cad..556c159b6c 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.c @@ -1,5 +1,18 @@ /* - * Copyright (c) 2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.h b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.h index 02d53e4294..418b230143 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.h +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/configuration_store_stub.h @@ -1,5 +1,18 @@ /* - * Copyright (c) 2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef __CONFIGURATION_STORE_STUB_H__ #define __CONFIGURATION_STORE_STUB_H__ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/ns_trace_stub.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/ns_trace_stub.c index b4b4f442b6..d58eb4c4a5 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/ns_trace_stub.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/ns_trace_stub.c @@ -1,5 +1,18 @@ /* - * Copyright (c) 2014-2016 ARM Limited. All rights reserved. + * Copyright (c) 2014-2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.c index 0b10772efc..e870047d86 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.c @@ -1,5 +1,18 @@ /* - * Copyright (c) 2014-2016 ARM Limited. All rights reserved. + * Copyright (c) 2014-2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "nsdynmemLIB_stub.h" diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.h b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.h index 3a15519876..4ab78ec9dd 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.h +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/nsdynmemLIB_stub.h @@ -1,5 +1,18 @@ /* - * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * Copyright (c) 2015-2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef __NSDYNMEMLIB_STUB_H__ #define __NSDYNMEMLIB_STUB_H__ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/timeout_stub.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/timeout_stub.c index be22af487a..4e18eb5010 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/timeout_stub.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/cs_nvm/test/test_cs_nvm_unit/unittest/stubs/timeout_stub.c @@ -1,5 +1,18 @@ /* - * Copyright (c) 2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "eventOS_event_timer.h" diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.c index ec970bdd07..9b1655c127 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.c @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016-2018 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.h b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.h index 8dc55bd737..5e38ece428 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.h +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016-2018 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mbed.cpp b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mbed.cpp index 6953cb660d..96e320884b 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mbed.cpp +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mbed.cpp @@ -1,15 +1,16 @@ /* - * Copyright (c) 2018 ARM Limited. All rights reserved. + * Copyright (c) 2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.c index b65c98617a..d6244d4757 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.c @@ -1,15 +1,16 @@ /* - * Copyright (c) 2018 ARM Limited. All rights reserved. + * Copyright (c) 2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.h b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.h index ce3ac9beb6..d8a56ca62a 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.h +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_event_loop_mutex.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2018 ARM Limited. All rights reserved. + * Copyright (c) 2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.c index 566472a0dc..0a81c9ef17 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.c @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016-2018 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.h b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.h index 10991ce4c7..a26b48cc25 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.h +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/ns_hal_init.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2016-2018 ARM Limited. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/nvm/nvm_ram.c b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/nvm/nvm_ram.c index 51ad41160c..12a6974fa9 100644 --- a/features/nanostack/nanostack-hal-mbed-cmsis-rtos/nvm/nvm_ram.c +++ b/features/nanostack/nanostack-hal-mbed-cmsis-rtos/nvm/nvm_ram.c @@ -1,5 +1,18 @@ /* - * Copyright (c) 2016, ARM Limited, All Rights Reserved. + * Copyright (c) 2016, 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifdef MBED_CONF_NANOSTACK_HAL_NVM_CFSTORE From 7824c793b7188c8f7b282a8e77817567f2086617 Mon Sep 17 00:00:00 2001 From: Netanel Gonen Date: Mon, 18 Feb 2019 13:56:50 +0200 Subject: [PATCH 074/109] support in more types then just RSA_KEYPAIR if the type is not supported the psa_crypto will return the error code for unsupported --- .../crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c index d734903874..5cc9acc2bc 100644 --- a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c +++ b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c @@ -1003,18 +1003,13 @@ psa_status_t psa_generate_key(psa_key_slot_t key, in_vec[1].base = &bits; in_vec[1].len = sizeof(size_t); - /* currently the parameter argument is used only for RSA keypair - and ignored in other cases. support for other algorithms - may be added later*/ - if (PSA_KEY_TYPE_RSA_KEYPAIR == type) { - in_vec[2].base = parameters; - /* size of parameter is unsigned integer as defined in header */ - in_vec[2].len = parameters_size; - } else { // currenty ignored for non RSA case - in_vec[2].base = NULL; - in_vec[2].len = 0; + if (((parameters == NULL) && (parameters_size != 0)) || ((parameters != NULL) && (parameters_size == 0))) { + return (PSA_ERROR_INVALID_ARGUMENT); } + in_vec[2].base = parameters; + in_vec[2].len = parameters_size; + handle = psa_connect(PSA_KEY_MNG_ID, MINOR_VER); if (handle <= 0) { return (PSA_ERROR_COMMUNICATION_FAILURE); From 31b9ce2d0be5a6fbc20ee0961b37615dad2a1c3a Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Thu, 14 Feb 2019 13:54:31 +0000 Subject: [PATCH 075/109] cmsis conf: change license to apache 2.0 --- cmsis/mbed_cmsis_conf.h | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/cmsis/mbed_cmsis_conf.h b/cmsis/mbed_cmsis_conf.h index d5ba37c8b2..d0fed8c324 100644 --- a/cmsis/mbed_cmsis_conf.h +++ b/cmsis/mbed_cmsis_conf.h @@ -1,23 +1,18 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2012 ARM Limited +/* + * Copyright (c) 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. + * http://www.apache.org/licenses/LICENSE-2.0 * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef MBED_CMSIS_CONF_H #define MBED_CMSIS_CONF_H From b6fe528a5dff3bf10bcfd3cfe31a445a61b8126f Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Thu, 14 Feb 2019 13:58:07 +0000 Subject: [PATCH 076/109] wifi test: add license info --- TESTS/network/wifi/wifi_tests.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/TESTS/network/wifi/wifi_tests.h b/TESTS/network/wifi/wifi_tests.h index b7d598b8b6..579b4d6e59 100644 --- a/TESTS/network/wifi/wifi_tests.h +++ b/TESTS/network/wifi/wifi_tests.h @@ -1,3 +1,19 @@ +/* + * Copyright (c) 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #ifndef WIFI_TESTS_H #define WIFI_TESTS_H From e3e8d490e72119ff735207a393423c82fe788943 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Thu, 14 Feb 2019 14:02:35 +0000 Subject: [PATCH 077/109] test mbedmicro: fix licenses --- TESTS/mbedmicro-mbed/attributes/attributes.c | 17 +++++++++++++++++ TESTS/mbedmicro-mbed/attributes/weak.c | 17 +++++++++++++++++ TESTS/mbedmicro-mbed/static_assert/test_c.c | 17 +++++++++++++++++ TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp | 17 +++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/TESTS/mbedmicro-mbed/attributes/attributes.c b/TESTS/mbedmicro-mbed/attributes/attributes.c index 5329b8a3c5..2f031f4f47 100644 --- a/TESTS/mbedmicro-mbed/attributes/attributes.c +++ b/TESTS/mbedmicro-mbed/attributes/attributes.c @@ -1,3 +1,20 @@ +/* +* Copyright (c) 2016-2018 ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the License); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an AS IS BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ #include "mbed_toolchain.h" #include diff --git a/TESTS/mbedmicro-mbed/attributes/weak.c b/TESTS/mbedmicro-mbed/attributes/weak.c index 7b2f862177..745cdca84c 100644 --- a/TESTS/mbedmicro-mbed/attributes/weak.c +++ b/TESTS/mbedmicro-mbed/attributes/weak.c @@ -1,3 +1,20 @@ +/* +* Copyright (c) 2016-2018 ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the License); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an AS IS BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ #include "mbed_toolchain.h" int testWeak1() diff --git a/TESTS/mbedmicro-mbed/static_assert/test_c.c b/TESTS/mbedmicro-mbed/static_assert/test_c.c index b908a2e872..ab7612eea2 100644 --- a/TESTS/mbedmicro-mbed/static_assert/test_c.c +++ b/TESTS/mbedmicro-mbed/static_assert/test_c.c @@ -1,3 +1,20 @@ +/* +* Copyright (c) 2015-2018 ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the License); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an AS IS BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ #include "mbed_assert.h" #define THE_ANSWER 42 diff --git a/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp b/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp index 2bff2780cb..55755dcee0 100644 --- a/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp +++ b/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp @@ -1,3 +1,20 @@ +/* +* Copyright (c) 2016-2018 ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the License); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an AS IS BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ #include "mbed_assert.h" #define THE_ANSWER 42 From 75ba44a6d058c826363751cf955e558994bed0d9 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Thu, 14 Feb 2019 14:06:15 +0000 Subject: [PATCH 078/109] check release: add license header --- tools/check_release.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tools/check_release.py b/tools/check_release.py index 4d940fbb2d..249945946c 100644 --- a/tools/check_release.py +++ b/tools/check_release.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + # Script to check a new mbed 2 release by compiling a set of specified test apps # for all currently supported platforms. Each test app must include an mbed library. # This can either be the pre-compiled version 'mbed' or the source version 'mbed-dev'. From aaa2b2b5dca6d63fa33451cd9197786a44cb68fc Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Fri, 15 Feb 2019 13:19:05 +0000 Subject: [PATCH 079/109] tools: add license headers --- tools/arm_pack_manager/__init__.py | 18 ++++++++++++++++++ tools/arm_pack_manager/pack_manager.py | 17 +++++++++++++++++ tools/check_release.py | 2 +- tools/dev/intel_hex_utils.py | 18 ++++++++++++++++++ tools/export/exporters.py | 18 ++++++++++++++++++ tools/host_tests/midi.py | 20 +++++++++++++++++++- tools/importer/importer.py | 18 ++++++++++++++++++ tools/memap.py | 18 ++++++++++++++++++ tools/misc/find_c_includes.py | 18 ++++++++++++++++++ tools/misc/remove-device-h.py | 18 ++++++++++++++++++ tools/project.py | 18 ++++++++++++++++++ tools/test/__init__.py | 17 +++++++++++++++++ tools/test/examples/examples.py | 18 ++++++++++++++++++ tools/test/examples/examples_lib.py | 20 +++++++++++++++++++- tools/test/memap/parse_test.py | 18 ++++++++++++++++++ tools/test/pylint.py | 18 ++++++++++++++++++ tools/test/spm/__init__.py | 17 +++++++++++++++++ tools/test/toolchains/api_test.py | 18 ++++++++++++++++++ tools/test/toolchains/arm_support_test.py | 18 ++++++++++++++++++ tools/test_configs/__init__.py | 18 ++++++++++++++++++ 20 files changed, 342 insertions(+), 3 deletions(-) diff --git a/tools/arm_pack_manager/__init__.py b/tools/arm_pack_manager/__init__.py index e33b3495d1..eac5cf4232 100644 --- a/tools/arm_pack_manager/__init__.py +++ b/tools/arm_pack_manager/__init__.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016-2018 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + try: from urllib2 import urlopen, URLError except ImportError: diff --git a/tools/arm_pack_manager/pack_manager.py b/tools/arm_pack_manager/pack_manager.py index edc492803b..6c946d87fe 100644 --- a/tools/arm_pack_manager/pack_manager.py +++ b/tools/arm_pack_manager/pack_manager.py @@ -1,3 +1,20 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" from __future__ import print_function, division, absolute_import import argparse from os.path import basename diff --git a/tools/check_release.py b/tools/check_release.py index 249945946c..e64e6d2a4f 100644 --- a/tools/check_release.py +++ b/tools/check_release.py @@ -1,5 +1,5 @@ """ -Copyright (c) 2016 ARM Limited. All rights reserved. +Copyright (c) 2016-2019 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/tools/dev/intel_hex_utils.py b/tools/dev/intel_hex_utils.py index c60e9c4e74..75ec2bfbc4 100644 --- a/tools/dev/intel_hex_utils.py +++ b/tools/dev/intel_hex_utils.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2014-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + from intelhex import IntelHex from cStringIO import StringIO diff --git a/tools/export/exporters.py b/tools/export/exporters.py index 61e91f48a0..b0db20e274 100644 --- a/tools/export/exporters.py +++ b/tools/export/exporters.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + """Just a template for subclassing""" import os from abc import abstractmethod, ABCMeta diff --git a/tools/host_tests/midi.py b/tools/host_tests/midi.py index 67f34ea6f8..3df89070b2 100644 --- a/tools/host_tests/midi.py +++ b/tools/host_tests/midi.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + from __future__ import print_function import sys import re @@ -69,4 +87,4 @@ try: test_midi_out_loopback(output_port,input_port) except KeyboardInterrupt: - pass \ No newline at end of file + pass diff --git a/tools/importer/importer.py b/tools/importer/importer.py index b093309e1d..f57de43af8 100644 --- a/tools/importer/importer.py +++ b/tools/importer/importer.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2017-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + import os import json import sys diff --git a/tools/memap.py b/tools/memap.py index 3691f89ce8..b233eab327 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + #!/usr/bin/env python """Memory Map File Analyser for ARM mbed""" diff --git a/tools/misc/find_c_includes.py b/tools/misc/find_c_includes.py index e24c6d13c8..34d1ef2712 100644 --- a/tools/misc/find_c_includes.py +++ b/tools/misc/find_c_includes.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + #!/usr/bin/env python import os diff --git a/tools/misc/remove-device-h.py b/tools/misc/remove-device-h.py index 6e71ecb2f4..a7834f3856 100644 --- a/tools/misc/remove-device-h.py +++ b/tools/misc/remove-device-h.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + import json import os import stat diff --git a/tools/project.py b/tools/project.py index 550c2eec3e..1037a6ee33 100644 --- a/tools/project.py +++ b/tools/project.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + """ The CLI entry point for exporting projects from the mbed tools to any of the supported IDEs or project structures. """ diff --git a/tools/test/__init__.py b/tools/test/__init__.py index e69de29bb2..0119582f3f 100644 --- a/tools/test/__init__.py +++ b/tools/test/__init__.py @@ -0,0 +1,17 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" diff --git a/tools/test/examples/examples.py b/tools/test/examples/examples.py index 3fbeaa3acc..bf3f2796e5 100644 --- a/tools/test/examples/examples.py +++ b/tools/test/examples/examples.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2017-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + """ import and bulid a bunch of example programs """ from argparse import ArgumentParser diff --git a/tools/test/examples/examples_lib.py b/tools/test/examples/examples_lib.py index 308fb87c75..9d607cb83b 100644 --- a/tools/test/examples/examples_lib.py +++ b/tools/test/examples/examples_lib.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2017-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + """ Import and bulid a bunch of example programs This library includes functions that are shared between the examples.py and @@ -425,4 +443,4 @@ def update_mbedos_version(config, tag, examples): return result return 0 - \ No newline at end of file + diff --git a/tools/test/memap/parse_test.py b/tools/test/memap/parse_test.py index 6ed7ecd7e5..e3bb7ed5ec 100644 --- a/tools/test/memap/parse_test.py +++ b/tools/test/memap/parse_test.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2018-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + import sys from io import open from os import sep diff --git a/tools/test/pylint.py b/tools/test/pylint.py index 9fc43ae18b..38c89705de 100644 --- a/tools/test/pylint.py +++ b/tools/test/pylint.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + """A test that all code scores above a 9.25 in pylint""" import subprocess diff --git a/tools/test/spm/__init__.py b/tools/test/spm/__init__.py index e69de29bb2..982d7317e5 100644 --- a/tools/test/spm/__init__.py +++ b/tools/test/spm/__init__.py @@ -0,0 +1,17 @@ +""" +Copyright (c) 2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" diff --git a/tools/test/toolchains/api_test.py b/tools/test/toolchains/api_test.py index f48ea1dc0d..1958afa41e 100644 --- a/tools/test/toolchains/api_test.py +++ b/tools/test/toolchains/api_test.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2017-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + """Tests for the toolchain sub-system""" import sys import os diff --git a/tools/test/toolchains/arm_support_test.py b/tools/test/toolchains/arm_support_test.py index b32bd7ab82..fdafa68a8c 100644 --- a/tools/test/toolchains/arm_support_test.py +++ b/tools/test/toolchains/arm_support_test.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2016-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + """Tests for the arm toolchain supported checks""" import sys import os diff --git a/tools/test_configs/__init__.py b/tools/test_configs/__init__.py index e397374339..5d40db4066 100644 --- a/tools/test_configs/__init__.py +++ b/tools/test_configs/__init__.py @@ -1,3 +1,21 @@ +""" +Copyright (c) 2018-2019 ARM Limited. All rights reserved. + +SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations +""" + from os.path import dirname, abspath, join, exists from tools.utils import json_file_to_dict From a43ef525d616e3cfec55e792ef61a3c28412aae5 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Fri, 15 Feb 2019 13:37:40 +0000 Subject: [PATCH 080/109] copyright 2019 fix --- TESTS/mbedmicro-mbed/attributes/attributes.c | 2 +- TESTS/mbedmicro-mbed/attributes/weak.c | 2 +- TESTS/mbedmicro-mbed/static_assert/test_c.c | 2 +- TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp | 2 +- TESTS/network/wifi/wifi_tests.h | 2 +- cmsis/mbed_cmsis_conf.h | 2 +- tools/arm_pack_manager/__init__.py | 2 +- tools/memap.py | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/TESTS/mbedmicro-mbed/attributes/attributes.c b/TESTS/mbedmicro-mbed/attributes/attributes.c index 2f031f4f47..df7ede99bb 100644 --- a/TESTS/mbedmicro-mbed/attributes/attributes.c +++ b/TESTS/mbedmicro-mbed/attributes/attributes.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2018 ARM Limited. All rights reserved. +* Copyright (c) 2016-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/TESTS/mbedmicro-mbed/attributes/weak.c b/TESTS/mbedmicro-mbed/attributes/weak.c index 745cdca84c..9a30fe77ce 100644 --- a/TESTS/mbedmicro-mbed/attributes/weak.c +++ b/TESTS/mbedmicro-mbed/attributes/weak.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2018 ARM Limited. All rights reserved. +* Copyright (c) 2016-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/TESTS/mbedmicro-mbed/static_assert/test_c.c b/TESTS/mbedmicro-mbed/static_assert/test_c.c index ab7612eea2..adcff7073a 100644 --- a/TESTS/mbedmicro-mbed/static_assert/test_c.c +++ b/TESTS/mbedmicro-mbed/static_assert/test_c.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2015-2018 ARM Limited. All rights reserved. +* Copyright (c) 2015-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp b/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp index 55755dcee0..024e4970cf 100644 --- a/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp +++ b/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2018 ARM Limited. All rights reserved. +* Copyright (c) 2016-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/TESTS/network/wifi/wifi_tests.h b/TESTS/network/wifi/wifi_tests.h index 579b4d6e59..d5f8eea39e 100644 --- a/TESTS/network/wifi/wifi_tests.h +++ b/TESTS/network/wifi/wifi_tests.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited and affiliates. + * Copyright (c) 2018-2019, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/cmsis/mbed_cmsis_conf.h b/cmsis/mbed_cmsis_conf.h index d0fed8c324..2a79698992 100644 --- a/cmsis/mbed_cmsis_conf.h +++ b/cmsis/mbed_cmsis_conf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited and affiliates. + * Copyright (c) 2018-2019, Arm Limited and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/tools/arm_pack_manager/__init__.py b/tools/arm_pack_manager/__init__.py index eac5cf4232..a16977245d 100644 --- a/tools/arm_pack_manager/__init__.py +++ b/tools/arm_pack_manager/__init__.py @@ -1,5 +1,5 @@ """ -Copyright (c) 2016-2018 ARM Limited. All rights reserved. +Copyright (c) 2016-2019 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/tools/memap.py b/tools/memap.py index b233eab327..7f3a409f09 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -1,5 +1,5 @@ """ -Copyright (c) 2016 ARM Limited. All rights reserved. +Copyright (c) 2016-2019 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 From 7049b585b56234b85872bbff57c592d63dbbc101 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Mon, 18 Feb 2019 15:45:33 +0000 Subject: [PATCH 081/109] tools: fix hashbang --- tools/memap.py | 4 ++-- tools/misc/find_c_includes.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index 7f3a409f09..99b6b561ea 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -1,3 +1,5 @@ +#!/usr/bin/env python + """ Copyright (c) 2016-2019 ARM Limited. All rights reserved. @@ -16,8 +18,6 @@ See the License for the specific language governing permissions and limitations under the License. """ -#!/usr/bin/env python - """Memory Map File Analyser for ARM mbed""" from __future__ import print_function, division, absolute_import diff --git a/tools/misc/find_c_includes.py b/tools/misc/find_c_includes.py index 34d1ef2712..292412f7d2 100644 --- a/tools/misc/find_c_includes.py +++ b/tools/misc/find_c_includes.py @@ -1,3 +1,5 @@ +#!/usr/bin/env python + """ Copyright (c) 2016-2019 ARM Limited. All rights reserved. @@ -16,8 +18,6 @@ See the License for the specific language governing permissions and limitations under the License. """ -#!/usr/bin/env python - import os import re From 81f7aa6003d3a5d267e1ef595686ae199cd3de62 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Tue, 19 Feb 2019 09:55:05 +0000 Subject: [PATCH 082/109] memap: remove not needed comment prior future import --- tools/memap.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/tools/memap.py b/tools/memap.py index 99b6b561ea..f6c4c4a81b 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -17,8 +17,6 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. """ - -"""Memory Map File Analyser for ARM mbed""" from __future__ import print_function, division, absolute_import from abc import abstractmethod, ABCMeta From 6cbe7a77597bd5be480c849f6dbbe5f3d12668bd Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Tue, 19 Feb 2019 10:38:53 +0000 Subject: [PATCH 083/109] tools: move string description after import modules --- tools/export/exporters.py | 2 +- tools/project.py | 7 ++++--- tools/test/examples/examples.py | 4 ++-- tools/test/examples/examples_lib.py | 12 ++++++------ tools/test/pylint.py | 4 ++-- tools/test/toolchains/api_test.py | 3 ++- tools/test/toolchains/arm_support_test.py | 3 ++- 7 files changed, 19 insertions(+), 16 deletions(-) diff --git a/tools/export/exporters.py b/tools/export/exporters.py index b0db20e274..960f8d15ea 100644 --- a/tools/export/exporters.py +++ b/tools/export/exporters.py @@ -16,7 +16,6 @@ See the License for the specific language governing permissions and limitations under the License. """ -"""Just a template for subclassing""" import os from abc import abstractmethod, ABCMeta import logging @@ -30,6 +29,7 @@ from tools.targets import TARGET_MAP from tools.utils import mkdir from tools.resources import FileType +"""Just a template for subclassing""" class TargetNotSupportedException(Exception): """Indicates that an IDE does not support a particular MCU""" diff --git a/tools/project.py b/tools/project.py index 1037a6ee33..8002d41704 100644 --- a/tools/project.py +++ b/tools/project.py @@ -16,9 +16,6 @@ See the License for the specific language governing permissions and limitations """ -""" The CLI entry point for exporting projects from the mbed tools to any of the -supported IDEs or project structures. -""" from __future__ import print_function, absolute_import from builtins import str @@ -57,6 +54,10 @@ from tools.utils import NotSupportedException from tools.options import extract_profile, list_profiles, extract_mcus from tools.notifier.term import TerminalNotifier +""" The CLI entry point for exporting projects from the mbed tools to any of the +supported IDEs or project structures. +""" + EXPORTER_ALIASES = { u'gcc_arm': u'make_gcc_arm', u'uvision': u'uvision5', diff --git a/tools/test/examples/examples.py b/tools/test/examples/examples.py index bf3f2796e5..d3d698152d 100644 --- a/tools/test/examples/examples.py +++ b/tools/test/examples/examples.py @@ -16,8 +16,6 @@ See the License for the specific language governing permissions and limitations """ -""" import and bulid a bunch of example programs """ - from argparse import ArgumentParser import os from os.path import dirname, abspath, basename @@ -26,6 +24,8 @@ import sys import subprocess import json +""" import and bulid a bunch of example programs """ + ROOT = abspath(dirname(dirname(dirname(dirname(__file__))))) sys.path.insert(0, ROOT) diff --git a/tools/test/examples/examples_lib.py b/tools/test/examples/examples_lib.py index 9d607cb83b..89e488a8a5 100644 --- a/tools/test/examples/examples_lib.py +++ b/tools/test/examples/examples_lib.py @@ -15,6 +15,12 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations """ +import os +from os.path import dirname, abspath, basename +import os.path +import sys +import subprocess +from shutil import rmtree """ Import and bulid a bunch of example programs @@ -22,12 +28,6 @@ limitations the update.py modules. """ -import os -from os.path import dirname, abspath, basename -import os.path -import sys -import subprocess -from shutil import rmtree ROOT = abspath(dirname(dirname(dirname(dirname(__file__))))) sys.path.insert(0, ROOT) diff --git a/tools/test/pylint.py b/tools/test/pylint.py index 38c89705de..dc986eaab3 100644 --- a/tools/test/pylint.py +++ b/tools/test/pylint.py @@ -16,12 +16,12 @@ See the License for the specific language governing permissions and limitations """ -"""A test that all code scores above a 9.25 in pylint""" - import subprocess import re import os.path +"""A test that all code scores above a 9.25 in pylint""" + SCORE_REGEXP = re.compile( r'^Your\ code\ has\ been\ rated\ at\ (\-?[0-9\.]+)/10') diff --git a/tools/test/toolchains/api_test.py b/tools/test/toolchains/api_test.py index 1958afa41e..fded2c672e 100644 --- a/tools/test/toolchains/api_test.py +++ b/tools/test/toolchains/api_test.py @@ -16,7 +16,6 @@ See the License for the specific language governing permissions and limitations """ -"""Tests for the toolchain sub-system""" import sys import os from string import printable @@ -25,6 +24,8 @@ from mock import MagicMock, patch from hypothesis import given, settings, HealthCheck from hypothesis.strategies import text, lists, fixed_dictionaries, booleans +"""Tests for the toolchain sub-system""" + ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "..")) sys.path.insert(0, ROOT) diff --git a/tools/test/toolchains/arm_support_test.py b/tools/test/toolchains/arm_support_test.py index fdafa68a8c..e0f5aa6b64 100644 --- a/tools/test/toolchains/arm_support_test.py +++ b/tools/test/toolchains/arm_support_test.py @@ -16,7 +16,6 @@ See the License for the specific language governing permissions and limitations """ -"""Tests for the arm toolchain supported checks""" import sys import os from string import printable @@ -25,6 +24,8 @@ from mock import MagicMock, patch from hypothesis import given, settings from hypothesis.strategies import text, lists, sampled_from +"""Tests for the arm toolchain supported checks""" + ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "..")) sys.path.insert(0, ROOT) From 22832744078706c674fb0019af2984b4fea59562 Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Tue, 5 Feb 2019 18:28:57 +0200 Subject: [PATCH 084/109] PSOC6: enable export to CMake The approach for the hex_files subset selection is identical to makefile exporter: https://github.com/ARMmbed/mbed-os/pull/9466 Single hex file should be passed to srec_cat when hex_filename is set in targets.json or mbed_app.json. --- tools/export/cmake/__init__.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index 5cf7caa95d..10c5de002b 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -44,7 +44,8 @@ class CMake(Exporter): "MCU_NRF51Code.binary_hook", "TEENSY3_1Code.binary_hook", "LPCTargetCode.lpc_patch", - "LPC4088Code.binary_hook" + "LPC4088Code.binary_hook", + "PSOC6Code.complete" ]) @classmethod @@ -74,6 +75,12 @@ class CMake(Exporter): # sort includes reverse, so the deepest dir comes first (ensures short includes) includes = sorted([re.sub(r'^[.]/', '', l) for l in self.resources.inc_dirs], reverse=True) + # select dependant hex files to merge into compiled hex image + hex_files = self.resources.hex_files + if hasattr(self.toolchain.target, 'hex_filename'): + hex_filename = self.toolchain.target.hex_filename + hex_files = list(f for f in hex_files if basename(f) == hex_filename) + ctx = { 'name': self.project_name, 'target': self.target, @@ -83,7 +90,7 @@ class CMake(Exporter): 'include_paths': includes, 'library_paths': sorted([re.sub(r'^[.]/', '', l) for l in self.resources.lib_dirs]), 'linker_script': self.resources.linker_script, - 'hex_files': self.resources.hex_files, + 'hex_files': hex_files, 'ar': basename(self.toolchain.ar), 'cc': basename(self.toolchain.cc[0]), 'cc_flags': " ".join(flag for flag in self.toolchain.cc[1:] if not flag == "-c"), From bb3c20695ec77324ecfa50d04d8b3dfaf978493e Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Tue, 19 Feb 2019 20:03:00 +0200 Subject: [PATCH 085/109] tools/export: move hex_files selection to base Exporter class CMake and makefile exporters share a common logic for hex file selection. Factor it as a common property in the base class to avoid code duplication. --- tools/export/cmake/__init__.py | 8 +------- tools/export/exporters.py | 9 +++++++++ tools/export/makefile/__init__.py | 7 +------ 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index 10c5de002b..67216544e1 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -75,12 +75,6 @@ class CMake(Exporter): # sort includes reverse, so the deepest dir comes first (ensures short includes) includes = sorted([re.sub(r'^[.]/', '', l) for l in self.resources.inc_dirs], reverse=True) - # select dependant hex files to merge into compiled hex image - hex_files = self.resources.hex_files - if hasattr(self.toolchain.target, 'hex_filename'): - hex_filename = self.toolchain.target.hex_filename - hex_files = list(f for f in hex_files if basename(f) == hex_filename) - ctx = { 'name': self.project_name, 'target': self.target, @@ -90,7 +84,7 @@ class CMake(Exporter): 'include_paths': includes, 'library_paths': sorted([re.sub(r'^[.]/', '', l) for l in self.resources.lib_dirs]), 'linker_script': self.resources.linker_script, - 'hex_files': hex_files, + 'hex_files': self.hex_files, 'ar': basename(self.toolchain.ar), 'cc': basename(self.toolchain.cc[0]), 'cc_flags': " ".join(flag for flag in self.toolchain.cc[1:] if not flag == "-c"), diff --git a/tools/export/exporters.py b/tools/export/exporters.py index 960f8d15ea..43504c6c13 100644 --- a/tools/export/exporters.py +++ b/tools/export/exporters.py @@ -141,6 +141,15 @@ class Exporter(object): return [l for l in self.resources.get_file_names(FileType.LIB) if l.endswith(self.toolchain.LIBRARY_EXT)] + @property + def hex_files(self): + """Returns a list of hex files to include in the exported project""" + hex_files = self.resources.hex_files + if hasattr(self.toolchain.target, 'hex_filename'): + hex_filename = self.toolchain.target.hex_filename + hex_files = [f for f in hex_files if basename(f) == hex_filename] + return hex_files + def toolchain_flags(self, toolchain): """Returns a dictionary of toolchain flags. Keys of the dictionary are: diff --git a/tools/export/makefile/__init__.py b/tools/export/makefile/__init__.py index c4d7412a0a..830c2cb252 100644 --- a/tools/export/makefile/__init__.py +++ b/tools/export/makefile/__init__.py @@ -84,11 +84,6 @@ class Makefile(Exporter): sys_libs = [self.prepare_sys_lib(lib) for lib in self.toolchain.sys_libs] - hex_files = self.resources.hex_files - if hasattr(self.toolchain.target, 'hex_filename'): - hex_filename = self.toolchain.target.hex_filename - hex_files = list(f for f in hex_files if basename(f) == hex_filename) - ctx = { 'name': self.project_name, 'to_be_compiled': to_be_compiled, @@ -98,7 +93,7 @@ class Makefile(Exporter): 'linker_script': self.resources.linker_script, 'libraries': libraries, 'ld_sys_libs': sys_libs, - 'hex_files': hex_files, + 'hex_files': self.hex_files, 'vpath': (["../../.."] if (basename(dirname(dirname(self.export_dir))) == "projectfiles") From c79e3fd10f4563748771b3e3878f2ffa0102a22f Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Fri, 15 Feb 2019 14:33:59 +0200 Subject: [PATCH 086/109] PSOC6: update PDL to the latest version --- .../psoc6pdl/drivers/include/cy_ble_clk.h | 11 +- .../psoc6pdl/drivers/include/cy_crypto.h | 313 ++-- .../drivers/include/cy_crypto_common.h | 291 +-- .../psoc6pdl/drivers/include/cy_crypto_core.h | 41 +- .../drivers/include/cy_crypto_core_aes.h | 125 +- .../drivers/include/cy_crypto_core_cmac.h | 32 +- .../drivers/include/cy_crypto_core_crc.h | 127 +- .../drivers/include/cy_crypto_core_crc_v1.h | 2 +- .../drivers/include/cy_crypto_core_crc_v2.h | 2 +- .../drivers/include/cy_crypto_core_des.h | 51 +- .../drivers/include/cy_crypto_core_ecc.h | 47 +- .../include/cy_crypto_core_ecc_nist_p.h | 59 +- .../drivers/include/cy_crypto_core_hmac.h | 27 +- .../drivers/include/cy_crypto_core_hw.h | 34 +- .../drivers/include/cy_crypto_core_hw_v2.h | 38 +- .../drivers/include/cy_crypto_core_hw_vu.h | 172 +- .../drivers/include/cy_crypto_core_mem.h | 30 +- .../drivers/include/cy_crypto_core_prng.h | 35 +- .../drivers/include/cy_crypto_core_sha.h | 110 +- .../drivers/include/cy_crypto_core_sha_v1.h | 18 +- .../drivers/include/cy_crypto_core_sha_v2.h | 2 +- .../drivers/include/cy_crypto_core_trng.h | 25 +- .../include/cy_crypto_core_trng_config_v1.h | 14 +- .../include/cy_crypto_core_trng_config_v2.h | 14 +- .../drivers/include/cy_crypto_core_trng_v1.h | 2 +- .../drivers/include/cy_crypto_core_vu.h | 62 +- .../drivers/include/cy_crypto_server.h | 8 +- .../psoc6pdl/drivers/include/cy_device.h | 2 + .../psoc6pdl/drivers/include/cy_pdl.h | 3 + .../psoc6pdl/drivers/include/cy_sysclk.h | 1 + .../psoc6pdl/drivers/source/cy_ble_clk.c | 10 +- .../psoc6pdl/drivers/source/cy_crypto.c | 4 +- .../drivers/source/cy_crypto_core_aes_v1.c | 100 +- .../drivers/source/cy_crypto_core_aes_v2.c | 109 +- .../drivers/source/cy_crypto_core_cmac_v1.c | 35 +- .../drivers/source/cy_crypto_core_cmac_v2.c | 29 +- .../drivers/source/cy_crypto_core_crc_v1.c | 102 +- .../drivers/source/cy_crypto_core_crc_v2.c | 103 +- .../drivers/source/cy_crypto_core_des_v1.c | 41 +- .../drivers/source/cy_crypto_core_des_v2.c | 46 +- .../source/cy_crypto_core_ecc_domain_params.c | 839 +++++---- .../drivers/source/cy_crypto_core_ecc_ecdsa.c | 189 +- .../source/cy_crypto_core_ecc_key_gen.c | 512 +++--- .../source/cy_crypto_core_ecc_nist_p.c | 1599 ++++++++--------- .../drivers/source/cy_crypto_core_hmac_v1.c | 126 +- .../drivers/source/cy_crypto_core_hmac_v2.c | 120 +- .../drivers/source/cy_crypto_core_hw.c | 25 +- .../drivers/source/cy_crypto_core_hw_v1.c | 18 +- .../drivers/source/cy_crypto_core_mem_v1.c | 8 +- .../drivers/source/cy_crypto_core_mem_v2.c | 8 +- .../drivers/source/cy_crypto_core_prng_v1.c | 8 +- .../drivers/source/cy_crypto_core_prng_v2.c | 8 +- .../drivers/source/cy_crypto_core_rsa.c | 248 +-- .../drivers/source/cy_crypto_core_sha_v1.c | 149 +- .../drivers/source/cy_crypto_core_sha_v2.c | 123 +- .../drivers/source/cy_crypto_core_trng_v1.c | 12 +- .../drivers/source/cy_crypto_core_trng_v2.c | 12 +- .../drivers/source/cy_crypto_core_vu.c | 52 +- .../drivers/source/cy_crypto_server.c | 14 +- 59 files changed, 3237 insertions(+), 3110 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h index 8a2beb8903..47bd9b8793 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ble_clk.h -* \version 3.0 +* \version 3.10 * * The header file of the BLE ECO clock driver. * @@ -70,7 +70,14 @@ * * * -* +* +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h index 0ee2810f3f..af3a29cd77 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h @@ -26,18 +26,51 @@ * \addtogroup group_crypto * \{ * The Crypto driver provides a public API to perform cryptographic and hash -* operations, as well as generate both true and pseudo random numbers -* (TRNG, PRNG). +* operations, as well as generate both true and pseudo random numbers. * * It uses a hardware IP block to accelerate operations. * * The functions and other declarations used in this driver are in cy_crypto.h, -* cy_crypto_core.h, and cy_crypto_server.h. You can also include cy_pdl.h +* cy_crypto_core.h, and cy_crypto_server.h. You can also include cy_pdl.h * (ModusToolbox only) to get access to all functions and declarations in the PDL. * -* The driver -* supports these standards: DES, TDES, AES (128, 192, 256 bits), CMAC-AES, SHA, -* HMAC, PRNG, TRNG, CRC, and RSA. +* The driver implements two usage models: +* * \ref group_crypto_cli_srv +* * \ref group_crypto_lld_api +* +* Mixing these usage models will result in undefined behaviour. +* +* The Crypto driver supports these standards: DES, TDES, AES (128, 192, 256 bits), CMAC-AES, SHA, +* HMAC, PRNG, TRNG, CRC, RSA, ECP, and ECDSA. +* \note ECP and ECDSA are only implemented for the \ref group_crypto_lld_api model. +* +* \section group_crypto_configuration_considerations Configuration Considerations +* +* Firmware sets up a cryptographic operation by passing in the required data as +* parameters in the function calls. +* +* All Crypto functions require a context. A context is a data +* structure that the driver uses for its operations. Firmware declares a +* context (allocates memory) but does not write or read the values in that +* context. In effect, the context is a scratch pad you provide to the driver. +* The driver uses the context to store and manipulate data during cryptographic +* operations. +* +* Several methods require an additional context unique to the particular +* cryptographic technique. +* The Crypto driver header files declare all the required structures for both +* configuration and context. +* +* Some encryption techniques require additional initialization specific to the +* technique. If there is an Init function, you must call it before using any +* other function for that technique, and re-initialize after you use a different +* encryption technique. +* +* For example, use \ref Cy_Crypto_Aes_Init to configure an AES encryption +* operation with the encryption key, and key length. +* Provide pointers to two context structures. You can then call the AES Run functions. +* If you use DES after that, you must re-initialize the AES encryption before using +* it again. * * \section group_crypto_definitions Definitions * @@ -63,16 +96,16 @@ * This function takes a fixed-size key and a block of plaintext data from * the message and encrypts it to generate ciphertext. Block ciphers are * reversible. The function performed on a block of encrypted data will -* decrypt it. +* decrypt that data. * * * * -* * * @@ -80,8 +113,8 @@ * * * * @@ -89,7 +122,7 @@ * * @@ -99,17 +132,17 @@ * * * * * * -* * -* * For more information see [Recommendation for Block Cipher Modes of Operation] * (https://nvlpubs.nist.gov/nistpubs/specialpublications/nist.sp.800-38b.pdf). @@ -144,7 +177,7 @@ * * * -* * -* * * @@ -176,15 +209,15 @@ * * * -* * *
VersionChangesReason of Change
3.0.03.10Updated the Cy_BLE_EcoConfigure() use case, when the voltageReg parameter is CY_BLE_ECO_VOLTAGE_REG_BLESSLDO +* and the Buck core regulator is enabled.Defect fixing: Before, when the Cy_BLE_EcoConfigure() function included the BLE LDO regulator option, the function returned CY_BLE_ECO_HARDWARE_ERROR if +* the Buck core regulator had been enabled.
3.0The initial version. \n The functionality of the BLE ECO clock is migrated from the BLE Middleware to the separated driver (ble_clk).Independent usage of BLE ECO clock without BLE Middleware.
Block Cipher ModeA mode of encrypting a message using block ciphers for messages of +* A mode of encrypting a message using block ciphers for messages of an * arbitrary length. The message is padded so that its length is an integer * multiple of the block size. ECB (Electronic Code Book), CBC (Cipher Block * Chaining), and CFB (Cipher Feedback) are all modes of using block ciphers -* to create an encrypted message of arbitrary length. +* to create an encrypted message of an arbitrary length. *
Data Encryption Standard (DES)The [DES standard] * (https://csrc.nist.gov/csrc/media/publications/fips/46/3/archive/1999-10-25/documents/fips46-3.pdf) -* specifies a symmetric-key algorithm for the encryption of electronic data. -* It uses a 56-bit key and a 64-bit message block size. +* specifies a symmetric-key algorithm for encryption of electronic data. +* It uses a 56-bit key. The block size is 64-bits. *
Triple DES (3DES or TDES)The [TDES standard] * (https://csrc.nist.gov/csrc/media/publications/fips/46/3/archive/1999-10-25/documents/fips46-3.pdf) -* specifies a symmetric-key block cipher, which applies the Data Encryption +* specifies a symmetric-key block cipher that applies the Data Encryption * Standard (DES) cipher algorithm three times to each data block. * It uses three 56-bit keys. The block size is 64-bits. * Advanced Encryption Standard (AES)The [AES standard] (https://nvlpubs.nist.gov/nistpubs/fips/nist.fips.197.pdf) * specifies the Rijndael algorithm, a symmetric block -* cipher that can process data blocks of 128 bits, using cipher keys with -* lengths of 128, 192, and 256 bits. Rijndael was designed to handle -* additional block sizes and key lengths, however they are not adopted in +* cipher that can process 128-bit data blocks, using cipher keys with +* 128-, 192-, and 256-bit lengths. Rijndael was designed to handle +* additional block sizes and key lengths. However, they are not adopted in * this standard. AES is also used for message authentication. *
Secure Hash Algorithm (SHA)Is a cryptographic hash function. -* This function takes a message of the arbitrary length and reduces it to a +* A cryptographic hash function. +* This function takes a message of an arbitrary length and reduces it to a * fixed-length residue or message digest after performing a series of * mathematically defined operations that practically guarantee that any * change in the message will change the hash value. It is used for message @@ -136,7 +169,7 @@ * *
Cipher-based Message Authentication Code (CMAC)This is a block cipher-based message authentication code algorithm. +* A block cipher-based message authentication code algorithm. * It computes the MAC value using the AES block cipher algorithm.
Hash Message Authentication Code (HMAC)Is a specific type of message authentication code (MAC) involving a +* A specific type of message authentication code (MAC) that involves a * cryptographic hash function and a secret cryptographic key. * It computes the MAC value using a Hash algorithm. * For more information see [The Keyed-Hash Message Authentication Code standard] @@ -154,7 +187,7 @@ * *
Pseudo Random Number Generator (PRNG)Is a Linear Feedback Shift Registers-based algorithm for generating a +* A Linear Feedback Shift Registers-based algorithm for generating a * sequence of numbers starting from a non-zero seed.
Asymmetric Key CryptographyAlso referred to as Public Key encryption. Someone who wishes to -* receive a message, publishes a very large public key (up to 4096 bits -* currently), which is one of two prime factors of a very large number. The -* other prime factor is the private key of the recipient and a secret. -* Someone wishing to send a message to the publisher of the public key -* encrypts the message with the public key. This message can now be -* decrypted only with the private key (the other prime factor held secret by +* Also referred to as Public Key encryption. To receive a message, +* you publish a very large public key (up to 4096 bits currently). +* That key is one of the two prime factors of a very large number. The +* other prime factor is the recipient's private (secret) key. +* To send a message to the publisher of the public key, you +* encrypt the message with the public key. This message can now be +* decrypted only with the private key (the other prime factor held in secret by * the recipient). The message is now sent over any channel to the recipient -* who can decrypt it with the private, secret, key. The same process is used +* who can decrypt it with the private (secret) key. The same process is used * to send messages to the sender of the original message. The asymmetric * cryptography relies on the mathematical impracticality (usually related to * the processing power available at any given time) of factoring the keys. @@ -192,7 +225,7 @@ * The public key is described by the pair (n, e) where n is a product of two * randomly chosen primes p and q. The exponent e is a random integer * 1 < e < Q where Q = (p-1) (q-1). The private key d is uniquely defined -* by the integer 1 < d < Q such that ed congruent to 1 (mod Q ). +* by the integer 1 < d < Q so that ed congruent with 1 (mod Q ). *
@@ -202,10 +235,51 @@ * RSASSA-PKCS1-v1_5 described here, page 31: * http://www.emc.com/collateral/white-papers/h11300-pkcs-1v2-2-rsa-cryptography-standard-wp.pdf * -* See the Cryptographic Function Block chapter of the Technical Reference Manual. +* See the "Cryptographic Function Block" chapter of the Technical Reference Manual. * * \section group_crypto_MISRA MISRA-C Compliance -* This driver does not contains any driver-specific MISRA violations. +* The Crypto driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
8.8AAn external object or function shall be declared in one and only +* one file.The pointer to the operation context memory can not be public +* accessible (can not be defined in the header file) but it should be +* extarnally accessed, because it is used by other Cypress software +* resources.
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type.The pointers to the context memory are void to allow handling of +* different data types for different operations. +* The cast operation is safe because the configuration is verified +* before operation is performed. +*
16.7AA pointer parameter in a function prototype should be declared as +* pointer to const if the pointer is not used to modify the addressed +* object.The objects pointed to by the base addresses of the CRYPTO are not +* always modified. While a const qualifier can be used in select +* scenarios, it brings little benefit in adding this to the affected +* functions.
* * \section group_crypto_changelog Changelog * @@ -214,15 +288,16 @@ * * * * * -* * * * * -* * * * * -* +* * * * @@ -267,7 +342,7 @@ * * * -* * @@ -278,7 +353,7 @@ * * * -* +* * * * @@ -289,15 +364,15 @@ * \ref Cy_Crypto_Trng_Generate, \ref Cy_Crypto_Des_Run, * \ref Cy_Crypto_Tdes_Run, \ref Cy_Crypto_Rsa_Proc * -* +* * * * -* +* * * * @@ -306,29 +381,24 @@ * *
2.20 *
    -*
  • Moved from pre-compiled library to Open Source under +*
  • Moved from a pre-compiled library to Open Source under * Apache 2.0 license.
    • -*
  • Added ECP and ECDSA support for NIST P curves: +*
  • Core (server) This API is now available.
    • +*
  • Added ECP and ECDSA support for the NIST P curves: * SECP192R1, SECP224R1, SECP256R1, SECP384R1, SECP521R1.
    • *
  • ECP and ECDSA only supported with direct calls to Crypto APIs, -* no client interface functions present.
    • -*
  • Added chunk mode for CRC.
    • -*
  • Added chunk mode for SHA, chunk size is limited to -* SHA block size.
    • +* no client interface functions are present. +*
  • Added Chunk mode for CRC.
    • +*
  • Added Chunk mode for SHA, the chunk size is limited to +* the SHA block size.
    • *
* 		ECC support added.
@@ -232,22 +307,22 @@ *
2.11bSame as production 2.10; only newly added Elliptic Curve point +* The same as production 2.10; only the newly-added Elliptic Curve point * multiplication functionality (NIST P256) is pre-production. * Open source under Apache version 2.0 license.
2.11Based on pre-production 2.10, except newly added Elliptic Curve point +* Based on pre-production 2.10, except the newly-added Elliptic Curve point * multiplication functionality (NIST P256). -* Does not incorporate production level documentation. +* Does not incorporate the production level documentation. * Open source under Apache version 2.0 license.ECC support.
2.10bSame as production 2.10. Open source under Apache version 2.0 license.The same as production 2.10. Open source under Apache version 2.0 license.
Added register access layer. Use register access macros instead +* Added the register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
2.0bSame as production 2.0. Open source under Apache version 2.0 license.The same as production 2.0. Open source under Apache version 2.0 license.
Documentation update and clarificationDocumentation update and clarification.
-* Changed crypto IP power control
-* Enhanced Vector Unit functionality for RSA crypto algorithm
-* Added support of the single-core devices +* Changed crypto IP power control.
+* Enhanced Vector Unit functionality for RSA crypto algorithm.
+* Added support of the single-core devices. * 		New device supportNew device support.
1.0
* -* \defgroup group_crypto_cli_srv Client-Server API +* \defgroup group_crypto_cli_srv Client-Server Model * \{ -* \defgroup group_crypto_client Client +* \defgroup group_crypto_cli_srv_macros Macros +* \defgroup group_crypto_cli_srv_functions Functions * \{ -* Client part of the Crypto. -* \defgroup group_crypto_macros Macros -* \defgroup group_crypto_cli_functions Functions -* \defgroup group_crypto_cli_data_structures Data Structures -* \defgroup group_crypto_enums Enumerated Types +* \defgroup group_crypto_cli_functions Client Functions +* \defgroup group_crypto_srv_functions Server Functions * \} -* \defgroup group_crypto_server Server +* \defgroup group_crypto_cli_srv_data_structures Data Structures * \{ -* Server part of the Crypto. -* \defgroup group_crypto_srv_functions Functions -* \defgroup group_crypto_srv_data_structures Data Structures -* \} -* \defgroup group_crypto_config_structure Configuration Structure -* \{ -* Crypto initialization configuration. -* \note Should be the same for Crypto Server and Crypto Client initializations. +* \defgroup group_crypto_config_structure Common Data Structures +* \defgroup group_crypto_cli_data_structures Client Data Structures +* \defgroup group_crypto_srv_data_structures Server Data Structures * \} * \} -* \defgroup group_crypto_lld_api Low-Level API +* \defgroup group_crypto_lld_api Direct Crypto Core Access +* \defgroup group_crypto_data_structures Common Data Structures +* \defgroup group_crypto_enums Common Enumerated Types */ /** @@ -339,23 +409,22 @@ * * The functions and other declarations used in this part of the driver are in * cy_crypto.h and cy_crypto_server.h. You can also include cy_pdl.h -* (ModusToolbox only) to get access to all functions and declarations in the +* (ModusToolbox only) to get access to all functions and declarations in the * PDL. * -* Firmware initializes and starts the Crypto server. The server can run on any +* The firmware initializes and starts the Crypto server. The server can run on any * core and works with the Crypto hardware. The Crypto server is implemented as * a secure block. It performs all cryptographic operations for the client. * Access to the server is through the Inter Process Communication (IPC) driver. * Direct access is not allowed. * -* The Crypto client can run on any core too. Firmware initializes and starts -* the client. The firmware then provides the configuration data required for -* the desired cryptographic technique, and requests that the server run the +* The Crypto client can run on any core too. The firmware initializes and starts +* the client. The firmware then provides configuration data required for +* the desired cryptographic technique and a request that the server run the * cryptographic operation. * * This document contains the following topics: * - \ref group_crypto_architecture -* - \ref group_crypto_configuration_considerations * - \ref group_crypto_configuration_structure * - \ref group_crypto_server_init * - \ref group_crypto_client_init @@ -396,23 +465,6 @@ * Using IPC for communication provides a simple synchronization mechanism to * handle concurrent requests from different cores. * -* \section group_crypto_configuration_considerations Configuration Considerations -* -* Firmware sets up a cryptographic operation by passing in required data as -* parameters in function calls. -* -* All Crypto functions require a context. A context is a data -* structure that the driver uses for its operations. Firmware declares the -* context (allocates memory) but does not write or read the values in the -* context. In effect the context is a scratch pad you provide to the driver. -* The driver uses the context to store and manipulate data during cryptographic -* operations. -* -* Several methods require an additional context unique to the particular -* cryptographic technique. -* The Crypto driver header files declare all the required structures for both -* configuration and context. -* * \section group_crypto_configuration_structure Configuration Structure * * IPC communication for the Crypto driver is handled transparently. User should @@ -527,17 +579,6 @@ * * \snippet crypto/2.10/snippet/main.c snippet_myCryptoInit * -* Some encryption techniques require additional initialization specific to the -* technique. If there is an Init function, you must call it before using any -* other function for that technique, and reinitialize after you use a different -* encryption technique. -* -* For example, use \ref Cy_Crypto_Aes_Init to configure an AES encryption -* operation with the encryption key, and key length. -* Provide pointers to two context structures. You can then call AES Run functions. -* If later on you use DES, you must re-initialize AES encryption before using -* it again. -* * \section group_crypto_common_use_cases Common Use Cases * * \subsection group_crypto_Use_CRC CRC Calculation @@ -667,9 +708,9 @@ * (2^moduloLength mod modulo). These fields are optional, and can be set to NULL. * * Calculate these coefficients with \ref Cy_Crypto_Rsa_CalcCoefs. -* Pass in the address of the key structure with the modulus and exponent values -* for the key. The function returns the coefficients for the key in the key -* structure, replacing any previous values. +* Pass them in the address of the key structure with the modulus and exponent +* values for the key. The function returns the coefficients for the key in the +* key structure, replacing any previous values. * * The RSA functionality also implements functions to decrypt a signature using * a public key. This signature must follow the RSASSA-PKCS-v1_5 standard. @@ -786,7 +827,7 @@ cy_en_crypto_status_t Cy_Crypto_GetLibraryInfo(cy_en_crypto_lib_info_t *cryptoIn * that stores the Crypto driver common context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoInit @@ -801,7 +842,7 @@ cy_en_crypto_status_t Cy_Crypto_Init(cy_stc_crypto_config_t const *config, cy_st * This function de-initializes the Crypto driver. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_DeInit(void); @@ -813,7 +854,7 @@ cy_en_crypto_status_t Cy_Crypto_DeInit(void); * This function enables (turns on) the Crypto hardware. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Enable(void); @@ -825,7 +866,7 @@ cy_en_crypto_status_t Cy_Crypto_Enable(void); * This function disables (turns off) the Crypto hardware. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Disable(void); @@ -843,7 +884,7 @@ cy_en_crypto_status_t Cy_Crypto_Disable(void); * False - is not blocking. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Sync(bool isBlocking); @@ -859,7 +900,7 @@ cy_en_crypto_status_t Cy_Crypto_Sync(bool isBlocking); * \ref cy_stc_crypto_hw_error_t. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_GetErrorStatus(cy_stc_crypto_hw_error_t *hwErrorCause); @@ -890,7 +931,7 @@ cy_en_crypto_status_t Cy_Crypto_GetErrorStatus(cy_stc_crypto_hw_error_t *hwError * the Crypto function context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoPrngUse @@ -920,7 +961,7 @@ cy_en_crypto_status_t Cy_Crypto_Prng_Init(uint32_t lfsr32InitState, * the Crypto function context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoPrngUse @@ -953,7 +994,7 @@ cy_en_crypto_status_t Cy_Crypto_Prng_Generate(uint32_t max, * internal variables the Crypto driver requires. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoAesEcbUse @@ -986,7 +1027,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Init(uint32_t *key, * that stores all AES internal variables. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoAesEcbUse @@ -1025,7 +1066,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Ecb_Run(cy_en_crypto_dir_mode_t dirMode, * internal variables the Crypto driver requires. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Aes_Cbc_Run(cy_en_crypto_dir_mode_t dirMode, @@ -1053,17 +1094,17 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Cbc_Run(cy_en_crypto_dir_mode_t dirMode, * The pointer to the initial vector. __Must be 4-byte aligned.__ * * \param dst -* The pointer to a destination cipher text. __Must be 4-byte aligned.__ +* The pointer to the destination cipher text. __Must be 4-byte aligned.__ * * \param src -* The pointer to a source plain text. __Must be 4-byte aligned.__ +* The pointer to the source plain text. __Must be 4-byte aligned.__ * * \param cfContext * The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all * internal variables the Crypto driver requires. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Aes_Cfb_Run(cy_en_crypto_dir_mode_t dirMode, @@ -1102,17 +1143,17 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Cfb_Run(cy_en_crypto_dir_mode_t dirMode, * __Must be 4-byte aligned.__ * * \param dst -* The pointer to a destination cipher text. __Must be 4-byte aligned.__ +* The pointer to the destination cipher text. __Must be 4-byte aligned.__ * * \param src -* The pointer to a source plain text. __Must be 4-byte aligned.__ +* The pointer to the source plain text. __Must be 4-byte aligned.__ * * \param cfContext * The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all * internal variables the Crypto driver requires. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_en_crypto_dir_mode_t dirMode, @@ -1134,7 +1175,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_en_crypto_dir_mode_t dirMode, * the context structure when making this function call. * * \param src -* The pointer to a source plain text. __Must be 4-byte aligned.__ +* The pointer to the source plain text. __Must be 4-byte aligned.__ * * \param srcSize * The size of a source plain text. @@ -1153,7 +1194,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_en_crypto_dir_mode_t dirMode, * internal variables the Crypto driver requires. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoCmacUse @@ -1189,7 +1230,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(uint32_t *src, * The size of a message. * * \param digest -* The pointer to the hash digest. Hash size depends to selected SHA mode +* The pointer to the hash digest. The hash size depends on the selected SHA mode * (from 20 to 64 bytes, see \ref CY_CRYPTO_SHA_MAX_DIGEST_SIZE). * __Must be 4-byte aligned.__ * @@ -1198,7 +1239,7 @@ cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(uint32_t *src, * internal variables for Crypto driver. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoSha256Use @@ -1246,7 +1287,7 @@ cy_en_crypto_status_t Cy_Crypto_Sha_Run(uint32_t *message, * internal variables for the Crypto driver. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoHmacUse @@ -1288,7 +1329,7 @@ cy_en_crypto_status_t Cy_Crypto_Hmac_Run(uint32_t *hmac, * internal variables for the Crypto driver. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Str_MemCpy(void *dst, @@ -1320,7 +1361,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemCpy(void *dst, * internal variables for the Crypto driver. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Str_MemSet(void *dst, @@ -1357,7 +1398,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemSet(void *dst, * internal variables for the Crypto driver. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Str_MemCmp(void const *src0, @@ -1395,7 +1436,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemCmp(void const *src0, * internal variables for the Crypto driver. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Str_MemXor(void const *src0, @@ -1508,7 +1549,7 @@ cy_en_crypto_status_t Cy_Crypto_Str_MemXor(void const *src0, * the Crypto driver context. * * \return -* A Crypto status \ref cy_en_crypto_status_t +* \ref cy_en_crypto_status_t * * \note * The polynomial, initial seed and remainder XOR values are always @@ -1551,7 +1592,7 @@ cy_en_crypto_status_t Cy_Crypto_Crc_Init(uint32_t polynomial, * the Crypto driver context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \note * The polynomial, initial seed and remainder XOR values are always @@ -1594,7 +1635,7 @@ cy_en_crypto_status_t Cy_Crypto_Crc_Run(void *data, * the Crypto driver context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoTrngUse @@ -1636,7 +1677,7 @@ cy_en_crypto_status_t Cy_Crypto_Trng_Generate(uint32_t GAROPol, * the Crypto driver context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Des_Run(cy_en_crypto_dir_mode_t dirMode, @@ -1673,7 +1714,7 @@ cy_en_crypto_status_t Cy_Crypto_Des_Run(cy_en_crypto_dir_mode_t dirMode, * the Crypto driver context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoTdesUse @@ -1735,7 +1776,7 @@ cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_en_crypto_dir_mode_t dirMode, * the RSA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Rsa_Proc(cy_stc_crypto_rsa_pub_key_t const *pubKey, @@ -1774,7 +1815,7 @@ cy_en_crypto_status_t Cy_Crypto_Rsa_Proc(cy_stc_crypto_rsa_pub_key_t const *pubK * the RSA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Rsa_CalcCoefs(cy_stc_crypto_rsa_pub_key_t const *pubKey, @@ -1818,7 +1859,7 @@ cy_en_crypto_status_t Cy_Crypto_Rsa_CalcCoefs(cy_stc_crypto_rsa_pub_key_t const * the RSA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Rsa_Verify(cy_en_crypto_rsa_ver_result_t *verResult, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h index 47301afbca..1fe68ef5e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h @@ -60,7 +60,7 @@ #define CY_CRYPTO_DRV_VERSION_MINOR 20 /** -* \addtogroup group_crypto_macros +* \addtogroup group_crypto_cli_srv_macros * \{ */ @@ -70,7 +70,7 @@ /** Defines Crypto_Sync non-blocking execution type parameter */ #define CY_CRYPTO_SYNC_NON_BLOCKING (false) -/** Defines the Crypto DES block size (in bytes) */ +/** Defines the Crypto DES block size (in bytes). */ #define CY_CRYPTO_DES_BLOCK_SIZE (8u) /** Defines the Crypto DES key size (in bytes) */ @@ -114,7 +114,7 @@ #define CY_CRYPTO_SHA512_224_DIGEST_SIZE (28u) /** Hash size for the SHA512_256 mode (in bytes) */ #define CY_CRYPTO_SHA512_256_DIGEST_SIZE (32u) -/** Maximal hash size for the SHA modes (in bytes) */ +/** The maximal Hash size for the SHA modes (in bytes). */ #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA512_DIGEST_SIZE) /** Block size for the SHA1 mode (in bytes) */ @@ -141,6 +141,9 @@ #define CY_CRYPTO_SHA512_ROUND_MEM_SIZE (640uL) #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (CY_CRYPTO_SHA512_ROUND_MEM_SIZE) +/* The width of the Crypto hardware registers values in bits. */ +#define CY_CRYPTO_HW_REGS_WIDTH (32UL) + /** \endcond */ #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ @@ -161,11 +164,13 @@ /** Crypto Driver PDL ID */ #define CY_CRYPTO_ID CY_PDL_DRV_ID(0x0Cu) -/** \} group_crypto_macros */ +/** \} group_crypto_cli_srv_macros */ /** * \addtogroup group_crypto_config_structure * \{ + The Crypto initialization configuration. +* \note Should be the same for the Crypto Server and Crypto Client initialization. */ /** The Crypto user callback function type. @@ -231,32 +236,37 @@ typedef struct /** \} group_crypto_config_structure */ /** -* \addtogroup group_crypto_cli_data_structures +* \addtogroup group_crypto_data_structures * \{ */ #if (CPUSS_CRYPTO_VU == 1) + /** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the RSA public key and - * additional coefficients to accelerate RSA calculation. - * - * RSA key contained from two fields: - * - n - modulus part of the key - * - e - exponent part of the key. - * - * Other fields are accelerating coefficients and can be calculated by - * \ref Cy_Crypto_Rsa_CalcCoefs. - * - * \note The modulus and exponent values in the - * \ref cy_stc_crypto_rsa_pub_key_t must also be in little-endian order.
- * Use \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from - * little-endian order. - * +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +* +* The driver uses this structure to store and manipulate the RSA public key and +* additional coefficients to accelerate RSA calculation. +* +* RSA key contained from two fields: +* - n - modulus part of the key +* - e - exponent part of the key. +* +* Other fields are accelerating coefficients and can be calculated by +* \ref Cy_Crypto_Rsa_CalcCoefs. +* +* \note The modulus and exponent values in the +* \ref cy_stc_crypto_rsa_pub_key_t must also be in little-endian order.
+* Use \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from +* little-endian order. */ typedef struct { + /** \cond INTERNAL */ /** The pointer to the modulus part of public key. */ uint8_t *moduloPtr; /** The modulus length, in bits, maximum supported size is 2048Bit */ @@ -278,10 +288,18 @@ typedef struct /** The pointer to the (2^moduloLength mod modulo). Memory for it should be allocated by user with size moduloLength */ uint8_t *rBarPtr; +/** \endcond */ } cy_stc_crypto_rsa_pub_key_t; #endif /* #if (CPUSS_CRYPTO_VU == 1) */ +/** \} group_crypto_data_structures */ + +/** +* \addtogroup group_crypto_cli_data_structures +* \{ +*/ + /** Structure for storing a description of a Crypto hardware error */ typedef struct { @@ -484,17 +502,25 @@ typedef enum /** \endcond */ /** -* \addtogroup group_crypto_cli_data_structures +* \addtogroup group_crypto_data_structures * \{ */ #if (CPUSS_CRYPTO_AES == 1) -/** Structure for storing the AES state */ + +/** The structure for storing the AES state. +* All fields for this structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** Pointer to AES key */ uint8_t *key; - /** Pointer to AES inversed key */ + /** Pointer to AES inverse key */ uint8_t *invKey; /** AES key length */ cy_en_crypto_aes_key_length_t keyLength; @@ -502,10 +528,39 @@ typedef struct uint32_t *buffers; /** AES processed block index (for CMAC, SHA operations) */ uint32_t blockIdx; + /** \endcond */ } cy_stc_crypto_aes_state_t; #endif /* #if (CPUSS_CRYPTO_AES == 1) */ -/** \} group_crypto_cli_data_structures */ +#if (CPUSS_CRYPTO_SHA == 1) + +/** The structure for storing the SHA state. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ +typedef struct +{ + /** \cond INTERNAL */ + uint32_t mode; + uint8_t *block; + uint32_t blockSize; + uint8_t *hash; + uint32_t hashSize; + uint8_t *roundMem; + uint32_t roundMemSize; + uint32_t messageSize; + uint32_t digestSize; + uint32_t blockIdx; + uint8_t const *initialHash; + /** \endcond */ +} cy_stc_crypto_sha_state_t; + +#endif /* (CPUSS_CRYPTO_SHA == 1) */ + +/** \} group_crypto_data_structures */ /************************************************************* * Structures used for communication between Client and Server @@ -516,14 +571,16 @@ typedef struct * \{ */ -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the server - * context. - */ +/** The structure for storing the crypto server context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** IPC communication channel number */ uint32_t ipcChannel; /** IPC acquire interrupt channel number */ @@ -540,6 +597,7 @@ typedef struct bool isHwErrorOccured; /** Hardware processing errors */ cy_stc_crypto_hw_error_t hwErrorStatus; + /** \endcond */ } cy_stc_crypto_server_context_t; /** \} group_crypto_srv_data_structures */ @@ -549,14 +607,16 @@ typedef struct * \{ */ -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the global - * context. - */ +/** The structure for storing the crypto client context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** Operation instruction code */ cy_en_crypto_comm_instr_t instr; /** Response from executed crypto function */ @@ -575,18 +635,21 @@ typedef struct cy_stc_sysint_t releaseNotifierConfig; /** Pointer to the crypto function specific context data */ void *xdata; + /** \endcond */ } cy_stc_crypto_context_t; #if (CPUSS_CRYPTO_DES == 1) -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the DES operational - * context. - */ +/** The structure for storing the DES context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** Operation direction (Encrypt / Decrypt) */ cy_en_crypto_dir_mode_t dirMode; /** Pointer to key data */ @@ -595,18 +658,21 @@ typedef struct uint32_t *dst; /** Pointer to data source block */ uint32_t *src; + /** \endcond */ } cy_stc_crypto_context_des_t; #endif /* #if (CPUSS_CRYPTO_DES == 1) */ #if (CPUSS_CRYPTO_AES == 1) -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the AES operational - * context. - */ +/** The structure for storing the AES context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** AES state data */ cy_stc_crypto_aes_state_t aesState; /** Operation direction (Encrypt / Decrypt) */ @@ -627,38 +693,22 @@ typedef struct uint32_t *dst; /** Pointer to data source block */ uint32_t *src; + /** \endcond */ } cy_stc_crypto_context_aes_t; #endif /* #if (CPUSS_CRYPTO_AES == 1) */ #if (CPUSS_CRYPTO_SHA == 1) -/** \cond INTERNAL */ -/* The structure for storing the SHA context */ -typedef struct -{ - uint32_t mode; - uint8_t *block; - uint32_t blockSize; - uint8_t *hash; - uint32_t hashSize; - uint8_t *roundMem; - uint32_t roundMemSize; - uint32_t messageSize; - uint32_t digestSize; - uint32_t blockIdx; - uint8_t const *initialHash; -} cy_stc_crypto_sha_state_t; - -/** \endcond */ - -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the SHA operational - * context. - */ +/** The structure for storing the SHA context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** Pointer to data source block */ uint32_t *message; /** Operation data size */ @@ -671,35 +721,41 @@ typedef struct uint32_t *key; /** Key data length (for HMAC only) */ uint32_t keyLength; + /** \endcond */ } cy_stc_crypto_context_sha_t; #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ #if (CPUSS_CRYPTO_PR == 1) -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the PRNG operational - * context. - */ +/** The structure for storing the PRNG context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ uint32_t lfsr32InitState; /**< lfsr32 initialization data */ uint32_t lfsr31InitState; /**< lfsr31 initialization data */ uint32_t lfsr29InitState; /**< lfsr29 initialization data */ uint32_t max; /**< Maximum of the generated value */ uint32_t *prngNum; /**< Pointer to generated value */ + /** \endcond */ } cy_stc_crypto_context_prng_t; #endif /* #if (CPUSS_CRYPTO_PR == 1) */ #if (CPUSS_CRYPTO_TR == 1) -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the TRNG operational - * context. - */ +/** The structure for storing the TRNG context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** The polynomial for the programmable Galois ring oscillator (TR_GARO_CTL). The polynomial is represented WITHOUT the high order bit (this bit is @@ -721,35 +777,41 @@ typedef struct uint32_t max; /** Pointer to generated value */ uint32_t *trngNum; + /** \endcond */ } cy_stc_crypto_context_trng_t; #endif /* #if (CPUSS_CRYPTO_TR == 1) */ #if (CPUSS_CRYPTO_STR == 1) -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the STR operational - * context. - */ +/** The structure for storing the string context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ void const *src0; /**< Pointer to 1-st string source */ void const *src1; /**< Pointer to 2-nd string source */ void *dst; /**< Pointer to string destination */ uint32_t dataSize; /**< Operation data size */ uint32_t data; /**< Operation data value (for memory setting) */ + /** \endcond */ } cy_stc_crypto_context_str_t; #endif /* #if (CPUSS_CRYPTO_STR == 1) */ #if (CPUSS_CRYPTO_CRC == 1) -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the CRC operational - * context. - */ +/** The structure for storing the CRC context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ void* data; /**< Pointer to data source block */ uint32_t dataSize; /**< Operation data size */ uint32_t *crc; /**< Pointer to CRC destination variable */ @@ -759,20 +821,23 @@ typedef struct uint32_t dataXor; /**< Input data XOR flag */ uint32_t remReverse; /**< Output data reverse flag */ uint32_t remXor; /**< Output data XOR flag */ + /** \endcond */ } cy_stc_crypto_context_crc_t; #endif /* #if (CPUSS_CRYPTO_CRC == 1) */ #if (CPUSS_CRYPTO_VU == 1) #if (CPUSS_CRYPTO_SHA == 1) -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the RSA verifying - * context. - */ +/** The structure for storing the RSA verification context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in the function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** Pointer to verification result /ref cy_en_crypto_rsa_ver_result_t */ cy_en_crypto_rsa_ver_result_t *verResult; /** SHA digest type, used with SHA calculation of the message */ @@ -783,17 +848,20 @@ typedef struct uint32_t const *decryptedSignature; /** Length of the decrypted RSA signature */ uint32_t decryptedSignatureLength; + /** \endcond */ } cy_stc_crypto_context_rsa_ver_t; #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ -/** - * Firmware allocates memory and provides a pointer to this structure in - * function calls. Firmware does not write or read values in this structure. - * The driver uses this structure to store and manipulate the RSA operational - * context. - */ +/** The structure for storing the RSA context. +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in function calls. Firmware must +* ensure that the defined instance of this structure remains in scope +* while the drive is in use. +*/ typedef struct { + /** \cond INTERNAL */ /** Pointer to key data */ cy_stc_crypto_rsa_pub_key_t const *key; /** Pointer to data source block */ @@ -802,6 +870,7 @@ typedef struct uint32_t messageSize; /** Pointer to data destination block */ uint32_t *result; + /** \endcond */ } cy_stc_crypto_context_rsa_t; #endif /* #if (CPUSS_CRYPTO_VU == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h index fe64336cfb..31c67a5bfb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h @@ -36,10 +36,43 @@ * provides the configuration data required for the desired cryptographic * technique. * -* \defgroup group_crypto_llc_macros Macros -* \defgroup group_crypto_llc_functions Functions -* \defgroup group_crypto_llc_data_structures Data Structures -* \defgroup group_crypto_llc_enums Enumerated Types +* \defgroup group_crypto_lld_hw Control and Status +* \{ +* \defgroup group_crypto_lld_hw_functions Functions +* \} +* \defgroup group_crypto_lld_symmetric Symmetric Key Algorithms (AES, DES, TDES) +* \{ +* \defgroup group_crypto_lld_symmetric_functions Functions +* \} +* \defgroup group_crypto_lld_asymmetric Asymmetric Key Algorithms (RSA, ECP, ECDSA) +* \{ +* \defgroup group_crypto_lld_asymmetric_functions Functions +* \defgroup group_crypto_lld_asymmetric_enums Enumerated Types +* \} +* \defgroup group_crypto_lld_sha Hash Operations (SHA) +* \{ +* \defgroup group_crypto_lld_sha_functions Functions +* \} +* \defgroup group_crypto_lld_mac Message Authentication Code (CMAC, HMAC) +* \{ +* \defgroup group_crypto_lld_mac_functions Functions +* \} +* \defgroup group_crypto_lld_crc Cyclic Redundancy Code (CRC) +* \{ +* \defgroup group_crypto_lld_crc_functions Functions +* \} +* \defgroup group_crypto_lld_rng Random Number Generation (TRNG, PRNG) +* \{ +* \defgroup group_crypto_lld_rng_functions Functions +* \} +* \defgroup group_crypto_lld_vu Vector Unit (VU) +* \{ +* \defgroup group_crypto_lld_vu_functions Functions +* \} +* \defgroup group_crypto_lld_mem Memory Streaming Functions +* \{ +* \defgroup group_crypto_lld_mem_functions Functions +* \} * \} */ #if !defined(CY_CRYPTO_CORE_H) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h index 7f93678932..0f6e960941 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h @@ -72,15 +72,19 @@ typedef cy_en_crypto_status_t (*cy_crypto_aes_ctr_func_t)(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState); +/** +* \addtogroup group_crypto_lld_symmetric_functions +* \{ +*/ /******************************************************************************* * Function Name: Cy_Crypto_Core_Aes_Init ****************************************************************************//** * -* Sets Aes mode and prepare inversed key. +* Initializes AES mode of operation and prepares an inverse key. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param key * The pointer to the encryption/decryption key. @@ -89,10 +93,11 @@ typedef cy_en_crypto_status_t (*cy_crypto_aes_ctr_func_t)(CRYPTO_Type *base, * \ref cy_en_crypto_aes_key_length_t * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Init(CRYPTO_Type *base, @@ -100,44 +105,45 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Init(CRYPTO_Type *base, cy_en_crypto_aes_key_length_t keyLength, cy_stc_crypto_aes_state_t *aesState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Aes_Init(base, key, keyLength, aesState); + tmpResult = Cy_Crypto_Core_V1_Aes_Init(base, key, keyLength, aesState); } else { - myResult = Cy_Crypto_Core_V2_Aes_Init(base, key, keyLength, aesState); + tmpResult = Cy_Crypto_Core_V2_Aes_Init(base, key, keyLength, aesState); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Aes_Ecb ****************************************************************************//** * -* Performs AES operation on one Block. +* Performs the AES operation on a single block. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT * (\ref cy_en_crypto_dir_mode_t). * * \param dst -* The pointer to a destination cipher block. +* The pointer to the destination cipher block. * * \param src -* The pointer to a source block. +* The pointer to the source block. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ecb(CRYPTO_Type *base, @@ -146,28 +152,29 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ecb(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Aes_Ecb(base, dirMode, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V1_Aes_Ecb(base, dirMode, dst, src, aesState); } else { - myResult = Cy_Crypto_Core_V2_Aes_Ecb(base, dirMode, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V2_Aes_Ecb(base, dirMode, dst, src, aesState); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Aes_Cbc ****************************************************************************//** * -* Performs AES operation on a plain text with Cipher Block Chaining (CBC). +* Performs the AES-CBC operation defined in the dirMode parameter on a plain text +* defined in the src parameter. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -180,16 +187,17 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ecb(CRYPTO_Type *base, * The pointer to the initial vector. * * \param dst -* The pointer to a destination cipher text. +* The pointer to the destination cipher text. * * \param src -* The pointer to a source plain text. +* The pointer to the source plain text. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cbc(CRYPTO_Type *base, @@ -200,28 +208,29 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cbc(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Aes_Cbc(base, dirMode, srcSize, ivPtr, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V1_Aes_Cbc(base, dirMode, srcSize, ivPtr, dst, src, aesState); } else { - myResult = Cy_Crypto_Core_V2_Aes_Cbc(base, dirMode, srcSize, ivPtr, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V2_Aes_Cbc(base, dirMode, srcSize, ivPtr, dst, src, aesState); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Aes_Cfb -******************************************************************************** +****************************************************************************//** * -* Performs AES operation on a plain text with the Cipher Feedback Block method (CFB). +* Performs the AES-CFB operation defined in the dirMode parameter on a plain text +* defined in the SRC parameter. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -234,16 +243,17 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cbc(CRYPTO_Type *base, * The pointer to the initial vector. * * \param dst -* The pointer to a destination cipher text. +* The pointer to the destination cipher text. * * \param src -* The pointer to a source plain text. +* The pointer to the source plain text. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cfb(CRYPTO_Type *base, @@ -254,31 +264,31 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cfb(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Aes_Cfb(base, dirMode, srcSize, ivPtr, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V1_Aes_Cfb(base, dirMode, srcSize, ivPtr, dst, src, aesState); } else { - myResult = Cy_Crypto_Core_V2_Aes_Cfb(base, dirMode, srcSize, ivPtr, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V2_Aes_Cfb(base, dirMode, srcSize, ivPtr, dst, src, aesState); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Aes_Ctr -******************************************************************************** +****************************************************************************//** * -* Performs AES operation on a plain text using the counter method (CTR). +* Performs the AES-CTR operation on a plain text defined in the src parameter. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcSize -* The size of a source plain text. +* The size of the source plain text. * * \param srcOffset * The size of an offset within the current block stream for resuming within the @@ -291,16 +301,17 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cfb(CRYPTO_Type *base, * The saved stream-block for resuming. Is over-written by the function. * * \param dst -* The pointer to a destination cipher text. +* The pointer to the destination cipher text. * * \param src -* The pointer to a source plain text. Must be 4-Byte aligned. +* The pointer to the source plain text. Must be 4-Byte aligned. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ctr(CRYPTO_Type *base, @@ -312,20 +323,22 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ctr(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Aes_Ctr(base, srcSize, srcOffset, ivPtr, streamBlock, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V1_Aes_Ctr(base, srcSize, srcOffset, ivPtr, streamBlock, dst, src, aesState); } else { - myResult = Cy_Crypto_Core_V2_Aes_Ctr(base, srcSize, srcOffset, ivPtr, streamBlock, dst, src, aesState); + tmpResult = Cy_Crypto_Core_V2_Aes_Ctr(base, srcSize, srcOffset, ivPtr, streamBlock, dst, src, aesState); } - return myResult; + return tmpResult; } +/** \} group_crypto_lld_symmetric_functions */ + #endif /* #if (CPUSS_CRYPTO_AES == 1) */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h index 710fe59921..c4e908c068 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h @@ -47,21 +47,26 @@ typedef cy_en_crypto_status_t (*cy_crypto_cmac_func_t)(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState); /** \endcond */ +/** +* \addtogroup group_crypto_lld_mac_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Cmac ****************************************************************************//** * -* Performs CMAC(Cipher-based Message Authentication Code) operation -* on a message to produce message authentication code using AES. +* Calculates the AES Cipher-based Message Authentication Code (CMAC) on the input +* message with the provided key. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param message -* The pointer to a source plain text. Must be 4-byte aligned. +* The pointer to the source plain text. Must be 4-byte aligned. * * \param messageSize -* The size of a source plain text. +* The size of the source plain text in bytes. * * \param key * The pointer to the encryption key. Must be 4-byte aligned. @@ -73,10 +78,11 @@ typedef cy_en_crypto_status_t (*cy_crypto_cmac_func_t)(CRYPTO_Type *base, * The pointer to the calculated CMAC. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Cmac(CRYPTO_Type *base, @@ -87,20 +93,22 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Cmac(CRYPTO_Type *base, uint8_t *cmac, cy_stc_crypto_aes_state_t *aesState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Cmac(base, message, messageSize, key, keyLength, cmac, aesState); + tmpResult = Cy_Crypto_Core_V1_Cmac(base, message, messageSize, key, keyLength, cmac, aesState); } else { - myResult = Cy_Crypto_Core_V2_Cmac(base, message, messageSize, key, keyLength, cmac, aesState); + tmpResult = Cy_Crypto_Core_V2_Cmac(base, message, messageSize, key, keyLength, cmac, aesState); } - return myResult; + return tmpResult; } +/** \} group_crypto_lld_mac_functions */ + #endif /* (CPUSS_CRYPTO_AES == 1) */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h index 921f474c90..6890e6654b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h @@ -49,14 +49,19 @@ typedef cy_en_crypto_status_t (*cy_crypto_crc_func_t)(CRYPTO_Type *base, uint32_t dataSize, uint32_t lfsrInitState); +/** +* \addtogroup group_crypto_lld_crc_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Crc_Init ****************************************************************************//** * -* Initializes CRC calculation. +* Initializes the CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param polynomial * The polynomial (specified using 32 bits) used in the computing CRC. @@ -65,16 +70,16 @@ typedef cy_en_crypto_status_t (*cy_crypto_crc_func_t)(CRYPTO_Type *base, * The order in which data bytes are processed. 0 - MSB first; 1- LSB first. * * \param dataXor -* The byte mask for XORing data +* The byte mask for XORing data. * * \param remReverse * A remainder reverse: 0 means the remainder is not reversed. 1 means reversed. * * \param remXor -* Specifies a mask with which the LFSR32 register is XORed to produce a remainder. +* Specifies the mask with which the LFSR32 register is XORed to produce a remainder. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_Init(CRYPTO_Type *base, @@ -84,28 +89,28 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_Init(CRYPTO_Type *base, uint32_t remReverse, uint32_t remXor) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Crc_Init(base, polynomial, dataReverse, dataXor, remReverse, remXor); + tmpResult = Cy_Crypto_Core_V1_Crc_Init(base, polynomial, dataReverse, dataXor, remReverse, remXor); } else { - myResult = Cy_Crypto_Core_V2_Crc_Init(base, polynomial, dataReverse, dataXor, remReverse, remXor); + tmpResult = Cy_Crypto_Core_V2_Crc_Init(base, polynomial, dataReverse, dataXor, remReverse, remXor); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Crc ****************************************************************************//** * -* Performs CRC calculation on a message. +* Performs the CRC calculation on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param crc * The pointer to a computed CRC value. Must be 4-byte aligned. @@ -120,7 +125,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_Init(CRYPTO_Type *base, * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc(CRYPTO_Type *base, @@ -129,28 +134,28 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc(CRYPTO_Type *base, uint32_t dataSize, uint32_t lfsrInitState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Crc(base, crc, data, dataSize, lfsrInitState); + tmpResult = Cy_Crypto_Core_V1_Crc(base, crc, data, dataSize, lfsrInitState); } else { - myResult = Cy_Crypto_Core_V2_Crc(base, crc, data, dataSize, lfsrInitState); + tmpResult = Cy_Crypto_Core_V2_Crc(base, crc, data, dataSize, lfsrInitState); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Crc_CalcInit ****************************************************************************//** * -* Initializes CRC calculation. +* Initializes the CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -159,7 +164,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc(CRYPTO_Type *base, * The polynomial (specified using 32 bits) used in the computing CRC. * * \param dataReverse -* The order in which data bytes are processed. 0 - MSB first; 1- LSB first. +* The order in which data bytes are processed. 0 - MSB first; 1 - LSB first. * * \param dataXor * The byte mask for XORing data @@ -168,13 +173,13 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc(CRYPTO_Type *base, * A remainder reverse: 0 means the remainder is not reversed. 1 means reversed. * * \param remXor -* Specifies a mask with which the LFSR32 register is XORed to produce a remainder. +* Specifies the mask with which the LFSR32 register is XORed to produce a remainder. * * \param lfsrInitState * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcInit(CRYPTO_Type *base, @@ -186,30 +191,30 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcInit(CRYPTO_Type *b uint32_t remXor, uint32_t lfsrInitState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Crc_CalcInit(base, width, polynomial, dataReverse, dataXor, + tmpResult = Cy_Crypto_Core_V1_Crc_CalcInit(base, width, polynomial, dataReverse, dataXor, remReverse, remXor, lfsrInitState); } else { - myResult = Cy_Crypto_Core_V2_Crc_CalcInit(base, width, polynomial, dataReverse, dataXor, + tmpResult = Cy_Crypto_Core_V2_Crc_CalcInit(base, width, polynomial, dataReverse, dataXor, remReverse, remXor, lfsrInitState); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Crc_CalcStart ****************************************************************************//** * -* Prepares CRC calculation by setting an initial seeds value. +* Prepares the CRC calculation by setting an initial seed value. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -218,34 +223,34 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcInit(CRYPTO_Type *b * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t lfsrInitState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Crc_CalcStart(base, width, lfsrInitState); + tmpResult = Cy_Crypto_Core_V1_Crc_CalcStart(base, width, lfsrInitState); } else { - myResult = Cy_Crypto_Core_V2_Crc_CalcStart(base, width, lfsrInitState); + tmpResult = Cy_Crypto_Core_V2_Crc_CalcStart(base, width, lfsrInitState); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Crc_CalcPartial ****************************************************************************//** * -* Performs CRC calculation of a message part. +* Performs the CRC calculation of a message part. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param data * The pointer to the message whose CRC is being computed. @@ -254,34 +259,34 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcStart(CRYPTO_Type * * The size of a message in bytes. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcPartial(CRYPTO_Type *base, void const *data, uint32_t dataSize) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Crc_CalcPartial(base, data, dataSize); + tmpResult = Cy_Crypto_Core_V1_Crc_CalcPartial(base, data, dataSize); } else { - myResult = Cy_Crypto_Core_V2_Crc_CalcPartial(base, data, dataSize); + tmpResult = Cy_Crypto_Core_V2_Crc_CalcPartial(base, data, dataSize); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Crc_CalcFinish ****************************************************************************//** * -* Finalizes CRC calculation. +* Finalizes the CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -290,33 +295,33 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcPartial(CRYPTO_Type * The pointer to a computed CRC value. Must be 4-byte aligned. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t *crc) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Crc_CalcFinish(base, width, crc); + tmpResult = Cy_Crypto_Core_V1_Crc_CalcFinish(base, width, crc); } else { - myResult = Cy_Crypto_Core_V2_Crc_CalcFinish(base, width, crc); + tmpResult = Cy_Crypto_Core_V2_Crc_CalcFinish(base, width, crc); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Crc_Calc ****************************************************************************//** * -* Performs CRC calculation on a message. +* Performs the CRC calculation on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -331,27 +336,29 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_CalcFinish(CRYPTO_Type * The size of a message in bytes. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Crc_Calc(CRYPTO_Type *base, uint32_t width, uint32_t *crc, void const *data, uint32_t dataSize) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Crc_Calc(base, width, crc, data, dataSize); + tmpResult = Cy_Crypto_Core_V1_Crc_Calc(base, width, crc, data, dataSize); } else { - myResult = Cy_Crypto_Core_V2_Crc_Calc(base, width, crc, data, dataSize); + tmpResult = Cy_Crypto_Core_V2_Crc_Calc(base, width, crc, data, dataSize); } - return myResult; + return tmpResult; } +/** \} group_crypto_lld_crc_functions */ + #endif /* #if (CPUSS_CRYPTO_CRC == 1) */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h index c4feeef338..f9f17ec657 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h @@ -48,7 +48,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc(CRYPTO_Type *base, uint32_t dataSize, uint32_t lfsrInitState); -/* New Partial calculation interface */ +/* The new partial calculation interface. */ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcInit(CRYPTO_Type *base, uint32_t width, uint32_t polynomial, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h index 319ce82a5d..58c4b7de92 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h @@ -48,7 +48,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc(CRYPTO_Type *base, uint32_t dataSize, uint32_t lfsrInitState); -/* New Partial calculation interface */ +/* The new partial calculation interface. */ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcInit(CRYPTO_Type *base, uint32_t width, uint32_t polynomial, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h index 14ec3290c5..4acf65c0ad 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h @@ -42,16 +42,21 @@ typedef cy_en_crypto_status_t (*cy_crypto_des_func_t)(CRYPTO_Type *base, uint8_t *dst, uint8_t const *src); +/** +* \addtogroup group_crypto_lld_symmetric_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Des ****************************************************************************//** * -* Performs DES operation on a Single Block. All addresses must be 4-Byte aligned. -* Ciphertext (dstBlock) may overlap with plaintext (srcBlock) +* Performs the DES operation on a single block. All addresses must be 4-byte aligned. +* Ciphertext (dst) may overlap with plaintext (src). * This function is independent from the previous Crypto state. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -61,13 +66,13 @@ typedef cy_en_crypto_status_t (*cy_crypto_des_func_t)(CRYPTO_Type *base, * The pointer to the encryption/decryption key. * * \param dst -* The pointer to a destination cipher block. +* The pointer to the destination cipher block. * * \param src -* The pointer to a source block. +* The pointer to the source block. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Des(CRYPTO_Type *base, @@ -76,30 +81,30 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Des(CRYPTO_Type *base, uint8_t *dst, uint8_t const *src) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Des(base, dirMode, key, dst, src); + tmpResult = Cy_Crypto_Core_V1_Des(base, dirMode, key, dst, src); } else { - myResult = Cy_Crypto_Core_V2_Des(base, dirMode, key, dst, src); + tmpResult = Cy_Crypto_Core_V2_Des(base, dirMode, key, dst, src); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Tdes ****************************************************************************//** * -* Performs TDES operation on a Single Block. All addresses must be 4-Byte aligned. -* Ciphertext (dstBlock) may overlap with plaintext (srcBlock) +* Performs the TDES operation on a single block. All addresses must be 4-byte aligned. +* Ciphertext (dst) may overlap with plaintext (src). * This function is independent from the previous Crypto state. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -109,13 +114,13 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Des(CRYPTO_Type *base, * The pointer to the encryption/decryption keys. * * \param dst -* The pointer to a destination cipher block. +* The pointer to the destination cipher block. * * \param src -* The pointer to a source data block. +* The pointer to the source data block. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Tdes(CRYPTO_Type *base, @@ -124,20 +129,22 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Tdes(CRYPTO_Type *base, uint8_t *dst, uint8_t const *src) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Tdes(base, dirMode, key, dst, src); + tmpResult = Cy_Crypto_Core_V1_Tdes(base, dirMode, key, dst, src); } else { - myResult = Cy_Crypto_Core_V2_Tdes(base, dirMode, key, dst, src); + tmpResult = Cy_Crypto_Core_V2_Tdes(base, dirMode, key, dst, src); } - return myResult; + return tmpResult; } +/** \} group_crypto_lld_symmetric_functions */ + #endif /* #if (CPUSS_CRYPTO_DES == 1) */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h index 6a68d63e9f..fb98ccb491 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h @@ -34,6 +34,12 @@ #if (CPUSS_CRYPTO_VU == 1) +/** +* \addtogroup group_crypto_lld_asymmetric_enums +* \{ +*/ + +/** List of supported elliptic curve IDs */ typedef enum { CY_CRYPTO_ECC_ECP_NONE = 0, CY_CRYPTO_ECC_ECP_SECP192R1, @@ -45,6 +51,8 @@ typedef enum { CY_CRYPTO_ECC_ECP_CURVES_CNT } cy_en_crypto_ecc_curve_id_t; +/** \} group_crypto_lld_asymmetric_enums */ + typedef enum cy_en_red_mul_algs { CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG = 0, CY_CRYPTO_NIST_P_SHIFT_MUL_RED_ALG, @@ -60,7 +68,7 @@ typedef struct { uint32_t size; /** name of curve */ - const char *name; + const char_t *name; /** ECC calculation default algorithm */ cy_en_crypto_ecc_red_mul_algs_t algo; @@ -118,7 +126,14 @@ typedef struct { } cy_stc_crypto_ecc_key; -typedef int (*cy_func_get_random_data_t)(void *, unsigned char *, size_t); +/** +* \addtogroup group_crypto_lld_asymmetric_functions +* \{ +*/ + +/** Pointer to a random number supplier function */ +typedef int (*cy_func_get_random_data_t)(void *rndInfo, uint8_t *rndData, size_t rndSize); + cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakeKeyPair(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, cy_stc_crypto_ecc_key *key, @@ -127,22 +142,24 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8_t *hash, uint32_t hashlen, uint8_t *sig, - cy_stc_crypto_ecc_key *key, - uint8_t *messageKey); + const cy_stc_crypto_ecc_key *key, + const uint8_t *messageKey); cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, - const uint8_t *sig, - const uint8_t *hash, - uint32_t hashlen, - uint8_t *status, - cy_stc_crypto_ecc_key *key); + const uint8_t *sig, + const uint8_t *hash, + uint32_t hashlen, + uint8_t *stat, + const cy_stc_crypto_ecc_key *key); cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePrivateKey(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, uint8_t *key, cy_func_get_random_data_t GetRandomDataFunc, void *randomDataInfo); cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, - uint8_t *privateKey, + const uint8_t *privateKey, cy_stc_crypto_ecc_key *publicKey); +/** \} group_crypto_lld_asymmetric_functions */ + /** Calculates the actual size in bytes of the bits value */ #define CY_CRYPTO_BYTE_SIZE_OF_BITS(x) (uint32_t)(((x) + 7u) >> 3u) @@ -166,11 +183,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, #define CY_CRYPTO_ECC_MAX_BYTE_SIZE (CY_CRYPTO_ECC_P521_BYTE_SIZE) /* "Global" vector unit registers. */ -#define VR_D 10 -#define VR_S_X 11 -#define VR_S_Y 12 -#define VR_BARRETT 13 -#define VR_P 14 /* polynomial */ +#define VR_D 10u +#define VR_S_X 11u +#define VR_S_Y 12u +#define VR_BARRETT 13u +#define VR_P 14u /* polynomial */ #endif /* #if (CPUSS_CRYPTO_VU == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h index 6fec27fa7b..33e5b3a824 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h @@ -33,38 +33,39 @@ #if (CPUSS_CRYPTO_VU == 1) -void Cy_Crypto_Core_EC_NistP_SetMode(int bitsize); +void Cy_Crypto_Core_EC_NistP_SetMode(uint32_t bitsize); void Cy_Crypto_Core_EC_NistP_SetRedAlg(cy_en_crypto_ecc_red_mul_algs_t alg); -void Cy_Crypto_Core_EC_NistP_PointMul(CRYPTO_Type *base, int p_x, int p_y, int p_d, int p_order, int bitsize); + +/** +* \addtogroup group_crypto_lld_asymmetric_functions +* \{ +*/ cy_en_crypto_status_t Cy_Crypto_Core_EC_NistP_PointMultiplication(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, - uint8_t* ecpGX, - uint8_t* ecpGY, - uint8_t* ecpD, - uint8_t* ecpQX, - uint8_t* ecpQY); -void Cy_Crypto_Core_EC_MulMod( CRYPTO_Type *base, - int z, - int a, - int b, - int size); -void Cy_Crypto_Core_EC_DivMod( CRYPTO_Type *base, - int z, - int a, - int b, - int size); -void Cy_Crypto_Core_EC_SquareMod( CRYPTO_Type *base, - int z, - int a, - int size); -void Cy_Crypto_Core_EC_Bar_MulRed(CRYPTO_Type *base, - int z, - int x, - int size -); -void Cy_Crypto_Core_EC_AddMod( CRYPTO_Type *base, int z, int a, int b); -void Cy_Crypto_Core_EC_SubMod( CRYPTO_Type *base, int z, int a, int b); -void Cy_Crypto_Core_EC_HalfMod( CRYPTO_Type *base, int z, int a); + const uint8_t *ecpGX, + const uint8_t *ecpGY, + const uint8_t *ecpD, + uint8_t *ecpQX, + uint8_t *ecpQY); +/** \} group_crypto_lld_asymmetric_functions */ + +void Cy_Crypto_Core_EC_MulMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t b, uint32_t size); +void Cy_Crypto_Core_EC_DivMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t b, uint32_t size); +void Cy_Crypto_Core_EC_SquareMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t size); +void Cy_Crypto_Core_EC_Bar_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size); + +void Cy_Crypto_Core_EC_AddMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t b); +void Cy_Crypto_Core_EC_SubMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t b); +void Cy_Crypto_Core_EC_HalfMod( CRYPTO_Type *base, uint32_t z, uint32_t a); + +void Cy_Crypto_Core_JacobianEcAdd(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t s_z, uint32_t t_x, uint32_t t_y, uint32_t size); +void Cy_Crypto_Core_JacobianEcDouble(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t s_z, uint32_t size); +void Cy_Crypto_Core_JacobianEcScalarMul(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t d, uint32_t size); + +void Cy_Crypto_Core_JacobianTransform(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t s_z); +void Cy_Crypto_Core_JacobianInvTransform(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t s_z, uint32_t size); + +void Cy_Crypto_Core_EC_NistP_PointMul(CRYPTO_Type *base, uint32_t p_x, uint32_t p_y, uint32_t p_d, uint32_t p_order, uint32_t bitsize); #endif /* #if (CPUSS_CRYPTO_VU == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h index 8dabf45ad5..d920990cf9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h @@ -44,23 +44,28 @@ typedef cy_en_crypto_status_t (*cy_crypto_hmac_func_t)(CRYPTO_Type *base, uint32_t keyLength, cy_en_crypto_sha_mode_t mode); +/** +* \addtogroup group_crypto_lld_mac_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Hmac ****************************************************************************//** * -* Performs HMAC calculation. +* Performs the HMAC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hmac * The pointer to the calculated HMAC. Must be 4-byte aligned. * * \param message -* The pointer to a message whose hash value is being computed. +* The pointer to the message whose hash value is being computed. * * \param messageSize -* The size of a message. +* The size of the message. * * \param key * The pointer to the key. @@ -72,7 +77,7 @@ typedef cy_en_crypto_status_t (*cy_crypto_hmac_func_t)(CRYPTO_Type *base, * \ref cy_en_crypto_sha_mode_t * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Hmac(CRYPTO_Type *base, @@ -83,20 +88,22 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Hmac(CRYPTO_Type *base, uint32_t keyLength, cy_en_crypto_sha_mode_t mode) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Hmac(base, hmac, message, messageSize, key, keyLength, mode); + tmpResult = Cy_Crypto_Core_V1_Hmac(base, hmac, message, messageSize, key, keyLength, mode); } else { - myResult = Cy_Crypto_Core_V2_Hmac(base, hmac, message, messageSize, key, keyLength, mode); + tmpResult = Cy_Crypto_Core_V2_Hmac(base, hmac, message, messageSize, key, keyLength, mode); } - return myResult; + return tmpResult; } +/** \} group_crypto_lld_mac_functions */ + #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h index c7df544ae8..ff2ddf9c86 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h @@ -108,9 +108,9 @@ #define REG_CRYPTO_DEV_KEY_CTL0(base) (((CRYPTO_V2_Type*)(base))->DEV_KEY_CTL0) #define REG_CRYPTO_DEV_KEY_CTL1(base) (((CRYPTO_V2_Type*)(base))->DEV_KEY_CTL1) -/* CRYPTO internal memory buffer size IN BYTES */ +/* The CRYPTO internal-memory buffer-size in bytes. */ #define CY_CRYPTO_MEM_BUFF_SIZE ((cy_device->cryptoMemSize) * 4u) -/* CRYPTO internal memory buffer size IN 32 bit WORDS */ +/* The CRYPTO internal-memory buffer-size in 32-bit words. */ #define CY_CRYPTO_MEM_BUFF_SIZE_U32 (cy_device->cryptoMemSize) /* Device Crypto IP descriptor type */ @@ -220,6 +220,11 @@ typedef enum /** \endcond */ +/** +* \addtogroup group_crypto_lld_hw_functions +* \{ +*/ + void Cy_Crypto_Core_HwInit(void); cy_en_crypto_status_t Cy_Crypto_Core_Enable(CRYPTO_Type *base); @@ -239,10 +244,10 @@ void Cy_Crypto_Core_InvertEndianness(void *inArrPtr, uint32_t byteSize); * The function checks whether the Crypto hardware is enabled. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \return -* Crypto status \ref cy_en_crypto_status_t. +* Crypto status \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE bool Cy_Crypto_Core_IsEnabled(CRYPTO_Type *base) @@ -265,7 +270,7 @@ __STATIC_INLINE bool Cy_Crypto_Core_IsEnabled(CRYPTO_Type *base) * - from 0 to 16 for MXCRYPTO_ver2 IP block * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_Crypto_Core_GetFIFODepth(CRYPTO_Type *base) @@ -281,7 +286,7 @@ __STATIC_INLINE uint8_t Cy_Crypto_Core_GetFIFODepth(CRYPTO_Type *base) * The value of this field ranges from 0 to 8 * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ __STATIC_INLINE uint8_t Cy_Crypto_Core_GetFIFOUsed(CRYPTO_Type *base) @@ -299,7 +304,7 @@ __STATIC_INLINE uint8_t Cy_Crypto_Core_GetFIFOUsed(CRYPTO_Type *base) * By default EVENT_LEVEL = 0; * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ __STATIC_INLINE void Cy_Crypto_Core_WaitForFifoAvailable(CRYPTO_Type *base) @@ -316,7 +321,7 @@ __STATIC_INLINE void Cy_Crypto_Core_WaitForFifoAvailable(CRYPTO_Type *base) * Waits until all instruction in FIFO will be completed * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ __STATIC_INLINE void Cy_Crypto_Core_WaitForReady(CRYPTO_Type *base) @@ -333,7 +338,7 @@ __STATIC_INLINE void Cy_Crypto_Core_WaitForReady(CRYPTO_Type *base) * Masks / unmasks multiple interrupt sources. * * \param base -* Pointer to Crypto instance address +* The pointer to the CRYPTO instance. * * \param interrupts * Mask bits. See definitions above. @@ -351,7 +356,7 @@ __STATIC_INLINE void Cy_Crypto_Core_SetInterruptMask(CRYPTO_Type *base, uint32_t * Reports mask / unmask multiple interrupt sources. * * \param base -* Pointer to Crypto instance address +* The pointer to the CRYPTO instance. * * \return * Mask bits. See definitions above. @@ -369,7 +374,7 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_GetInterruptMask(CRYPTO_Type const *base * Reports states of multiple enabled interrupt sources. * * \param base -* Pointer to Crypto instance address +* The pointer to the CRYPTO instance. * * \return * Source bits. See definitions above. @@ -387,7 +392,7 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_GetInterruptStatusMasked(CRYPTO_Type con * Reports states of multiple interrupt sources. * * \param base -* Pointer to Crypto instance address +* The pointer to the CRYPTO instance. * * \return * Source bits. See definitions above. @@ -405,7 +410,7 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_GetInterruptStatus(CRYPTO_Type *base) * Sets one of more interrupt sources * * \param base -* Pointer to Crypto instance address +* The pointer to the CRYPTO instance. * * \param interrupts * Source bit(s) @@ -423,7 +428,7 @@ __STATIC_INLINE void Cy_Crypto_Core_SetInterrupt(CRYPTO_Type *base, uint32_t in * Clears multiple interrupt sources. * * \param base -* Pointer to Crypto instance address +* The pointer to the CRYPTO instance. * * \param interrupts * Source bit(s). See definitions above. @@ -435,6 +440,7 @@ __STATIC_INLINE void Cy_Crypto_Core_ClearInterrupt(CRYPTO_Type *base, uint32_t (void) REG_CRYPTO_INTR(base); } +/** \} group_crypto_lld_hw_functions */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h index fb8e1b11ac..33eef6dad5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h @@ -151,8 +151,8 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_FFStart(CRYPTO_Type *base, { } - REG_CRYPTO_INSTR_FF_WR(base) = (CY_CRYPTO_V2_FF_START_OPC << CY_CRYPTO_OPCODE_POS) - | (ff_idx << CY_CRYPTO_RSRC0_SHIFT); + REG_CRYPTO_INSTR_FF_WR(base) = ((uint32_t)CY_CRYPTO_V2_FF_START_OPC << CY_CRYPTO_OPCODE_POS) | + (ff_idx << CY_CRYPTO_RSRC0_SHIFT); REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t) p_mem; REG_CRYPTO_INSTR_FF_WR(base) = size; } @@ -168,8 +168,8 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_FFContinue(CRYPTO_Type *base, /* Wait for previous loading has been completed. */ (CY_CRYPTO_V2_RB_FF_LOAD0 == ff_idx) ? Cy_Crypto_Core_V2_FFLoad0Sync(base) : Cy_Crypto_Core_V2_FFLoad1Sync(base); - REG_CRYPTO_INSTR_FF_WR(base) = (CY_CRYPTO_V2_FF_CONTINUE_OPC << CY_CRYPTO_OPCODE_POS) - | (ff_idx << CY_CRYPTO_RSRC0_SHIFT); + REG_CRYPTO_INSTR_FF_WR(base) = ((uint32_t)CY_CRYPTO_V2_FF_CONTINUE_OPC << CY_CRYPTO_OPCODE_POS) | + (ff_idx << CY_CRYPTO_RSRC0_SHIFT); REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t) p_mem; REG_CRYPTO_INSTR_FF_WR(base) = size; } @@ -181,7 +181,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_FFStop(CRYPTO_Type *base, uint32_t ff_idx { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_FF_STOP_OPC << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_FF_STOP_OPC << CY_CRYPTO_OPCODE_POS) | (ff_idx << CY_CRYPTO_RSRC0_SHIFT)); } @@ -193,7 +193,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockMov(CRYPTO_Type *base, { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_BLOCK_MOV_OPC << CY_CRYPTO_OPCODE_POS) + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_BLOCK_MOV_OPC << CY_CRYPTO_OPCODE_POS) | (size << CY_CRYPTO_RSRC16_SHIFT) | (dst_idx << CY_CRYPTO_RSRC12_SHIFT) | (src_idx << CY_CRYPTO_RSRC0_SHIFT)); @@ -207,8 +207,8 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockMov_Reflect(CRYPTO_Type *base, { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_BLOCK_MOV_OPC << CY_CRYPTO_OPCODE_POS) - | (1u << CY_CRYPTO_RSRC23_SHIFT) + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_BLOCK_MOV_OPC << CY_CRYPTO_OPCODE_POS) + | (1UL << CY_CRYPTO_RSRC23_SHIFT) | (size << CY_CRYPTO_RSRC16_SHIFT) | (dst_idx << CY_CRYPTO_RSRC12_SHIFT) | (src_idx << CY_CRYPTO_RSRC0_SHIFT)); @@ -222,7 +222,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockSet(CRYPTO_Type *base, { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_BLOCK_SET_OPC << CY_CRYPTO_OPCODE_POS) + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_BLOCK_SET_OPC << CY_CRYPTO_OPCODE_POS) | (size << CY_CRYPTO_RSRC16_SHIFT) | (dst_idx << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)(data) << CY_CRYPTO_RSRC0_SHIFT)); @@ -236,7 +236,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockCmp(CRYPTO_Type *base, { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_BLOCK_CMP_OPC << CY_CRYPTO_OPCODE_POS) + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_BLOCK_CMP_OPC << CY_CRYPTO_OPCODE_POS) | (size << CY_CRYPTO_RSRC16_SHIFT) | (src1_idx << CY_CRYPTO_RSRC4_SHIFT) | (src0_idx << CY_CRYPTO_RSRC0_SHIFT)); @@ -250,7 +250,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockXor(CRYPTO_Type *base, { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_BLOCK_XOR_OPC << CY_CRYPTO_OPCODE_POS) + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_BLOCK_XOR_OPC << CY_CRYPTO_OPCODE_POS) | (size << CY_CRYPTO_RSRC16_SHIFT) | (dst_idx << CY_CRYPTO_RSRC12_SHIFT) | (src1_idx << CY_CRYPTO_RSRC4_SHIFT) @@ -264,7 +264,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_BlockGcm(CRYPTO_Type *base) { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(CY_CRYPTO_V2_BLOCK_GCM_OPC << CY_CRYPTO_OPCODE_POS); + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((uint32_t)CY_CRYPTO_V2_BLOCK_GCM_OPC << CY_CRYPTO_OPCODE_POS); } __STATIC_INLINE void Cy_Crypto_Core_V2_Run(CRYPTO_Type *base, uint32_t opc) @@ -284,7 +284,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBClear(CRYPTO_Type *base) { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(CY_CRYPTO_V2_RB_CLEAR_OPC << CY_CRYPTO_OPCODE_POS); + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((uint32_t)CY_CRYPTO_V2_RB_CLEAR_OPC << CY_CRYPTO_OPCODE_POS); } __STATIC_INLINE void Cy_Crypto_Core_V2_RBSwap(CRYPTO_Type *base) @@ -294,7 +294,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBSwap(CRYPTO_Type *base) { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(CY_CRYPTO_V2_RB_SWAP_OPC << CY_CRYPTO_OPCODE_POS); + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((uint32_t)CY_CRYPTO_V2_RB_SWAP_OPC << CY_CRYPTO_OPCODE_POS); } __STATIC_INLINE void Cy_Crypto_Core_V2_RBXor(CRYPTO_Type *base, uint32_t offset, uint32_t size) @@ -304,7 +304,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBXor(CRYPTO_Type *base, uint32_t offset, { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_RB_XOR_OPC << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_RB_XOR_OPC << CY_CRYPTO_OPCODE_POS) | (offset << CY_CRYPTO_RSRC8_SHIFT) | (size << CY_CRYPTO_RSRC0_SHIFT)); } @@ -316,7 +316,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBStore(CRYPTO_Type *base, uint32_t offse { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_RB_STORE_OPC << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_RB_STORE_OPC << CY_CRYPTO_OPCODE_POS) | (offset << CY_CRYPTO_RSRC8_SHIFT) | (size << CY_CRYPTO_RSRC0_SHIFT));} @@ -327,7 +327,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RBSetByte(CRYPTO_Type *base, uint32_t off { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((CY_CRYPTO_V2_RB_BYTE_SET_OPC << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(((uint32_t)CY_CRYPTO_V2_RB_BYTE_SET_OPC << CY_CRYPTO_OPCODE_POS) | (offset << CY_CRYPTO_RSRC8_SHIFT) | ((uint32_t)(byte) << CY_CRYPTO_RSRC0_SHIFT)); } @@ -339,7 +339,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RunAes(CRYPTO_Type *base) { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(CY_CRYPTO_V2_AES_OPC << CY_CRYPTO_OPCODE_POS); + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((uint32_t)CY_CRYPTO_V2_AES_OPC << CY_CRYPTO_OPCODE_POS); } __STATIC_INLINE void Cy_Crypto_Core_V2_RunAesInv(CRYPTO_Type *base) @@ -349,7 +349,7 @@ __STATIC_INLINE void Cy_Crypto_Core_V2_RunAesInv(CRYPTO_Type *base) { } - REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)(CY_CRYPTO_V2_AES_INV_OPC << CY_CRYPTO_OPCODE_POS); + REG_CRYPTO_INSTR_FF_WR(base) = (uint32_t)((uint32_t)CY_CRYPTO_V2_AES_INV_OPC << CY_CRYPTO_OPCODE_POS); } __STATIC_INLINE void Cy_Crypto_Core_V2_RunChacha(CRYPTO_Type *base, uint8_t roundNum) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h index c883594c2c..7780982475 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h @@ -191,8 +191,8 @@ #define CY_CRYPTO_VU2_INV_BIT_IMM_OPC (0x2Eu) -__STATIC_INLINE void CY_CRYPTO_VU_SAVE_REG (CRYPTO_Type *base, uint32_t rsrc, uint32_t *ddata); -__STATIC_INLINE void CY_CRYPTO_VU_RESTORE_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t ddata); +__STATIC_INLINE void CY_CRYPTO_VU_SAVE_REG (CRYPTO_Type *base, uint32_t rsrc, uint32_t *data); +__STATIC_INLINE void CY_CRYPTO_VU_RESTORE_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data); __STATIC_INLINE void CY_CRYPTO_VU_SET_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data, uint32_t size); @@ -200,7 +200,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS (CRYPTO_Type *base, uin { REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | - (uint32_t)rsrc); + ((uint32_t)rsrc)); } __STATIC_INLINE void CY_CRYPTO_VU_MOV_REG_TO_STATUS (CRYPTO_Type *base, uint32_t rsrc) @@ -222,18 +222,19 @@ __STATIC_INLINE void CY_CRYPTO_VU_MOV_STATUS_TO_REG (CRYPTO_Type *base, uint32_t __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_IMM_TO_STATUS (CRYPTO_Type *base, uint32_t cc, uint32_t imm4) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******* V1 *********/ - int tmp_reg = CY_CRYPTO_VU_HW_REG14; - uint32_t tmp_data; + uint32_t tmpReg = CY_CRYPTO_VU_HW_REG14; + uint32_t tmpData; - CY_CRYPTO_VU_SAVE_REG(base, tmp_reg, &tmp_data); + CY_CRYPTO_VU_SAVE_REG(base, tmpReg, &tmpData); - CY_CRYPTO_VU_SET_REG(base, tmp_reg, imm4, 4); - CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS(base, cc, tmp_reg); + /* Load 4 bit immediate value */ + CY_CRYPTO_VU_SET_REG(base, tmpReg, imm4, 4u); + CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS(base, cc, tmpReg); - CY_CRYPTO_VU_RESTORE_REG(base, tmp_reg, tmp_data); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { @@ -255,8 +256,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_REG (CRYPTO_Type *base, uint32_t rdst, uin { REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_SET_REG_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)rdst << CY_CRYPTO_RSRC26_SHIFT) | - ((uint32_t)data << ((cy_device->cryptoVersion == 1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC13_SHIFT)) | - (((uint32_t)size - 1) << CY_CRYPTO_RSRC0_SHIFT)); + ((uint32_t)data << ((CY_CRYPTO_HW_V1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC13_SHIFT)) | + (((uint32_t)size - 1u) << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_COND_LD_REG (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) @@ -317,7 +318,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_ADD_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_ADD_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -331,7 +332,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_SUB_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_SUB_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -345,7 +346,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_OR_REG (CRYPTO_Type *base, uint32_t cc, u ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_OR_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -359,7 +360,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_AND_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_AND_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -373,7 +374,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_XOR_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_XOR_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -387,7 +388,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_NOR_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_NOR_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -401,7 +402,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_NAND_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_NAND_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -415,7 +416,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_MIN_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_MIN_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -429,7 +430,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_MAX_REG (CRYPTO_Type *base, uint32_t cc, ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_MAX_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -464,8 +465,8 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_ALLOC_MEM (CRYPTO_Type *base, uint32_t cc REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_ALLOC_MEM_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | - ((uint32_t)rdst << ((cy_device->cryptoVersion == 1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC16_SHIFT)) | - (((uint32_t)size - 1) << CY_CRYPTO_RSRC0_SHIFT)); + ((uint32_t)rdst << ((CY_CRYPTO_HW_V1) ? CY_CRYPTO_RSRC12_SHIFT : CY_CRYPTO_RSRC16_SHIFT)) | + (((uint32_t)size - 1u) << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_ALLOC_MEM (CRYPTO_Type *base, uint32_t rdst, uint32_t size) @@ -477,7 +478,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_FREE_MEM (CRYPTO_Type *base, uint32_t cc, { REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_FREE_MEM_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | - (uint32_t)reg_mask); + ((uint32_t)reg_mask)); } __STATIC_INLINE void CY_CRYPTO_VU_FREE_MEM (CRYPTO_Type *base, uint32_t reg_mask) @@ -491,7 +492,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL (CRYPTO_Type *base, uint32_t cc, uint ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_LSL (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -501,7 +502,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSL (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL1 (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******* V1 *********/ REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LSL1_OPC << CY_CRYPTO_OPCODE_POS) | @@ -527,7 +528,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSL1 (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_LSL1_WITH_CARRY (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******* V1 *********/ REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_LSL1_WITH_CARRY_OPC << CY_CRYPTO_OPCODE_POS) | @@ -553,11 +554,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSL1_WITH_CARRY (CRYPTO_Type *base, uint32_t r __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((cy_device->cryptoVersion == 1) ? CY_CRYPTO_VU1_LSR_OPC : CY_CRYPTO_VU2_LSR_OPC) << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_LSR_OPC : CY_CRYPTO_VU2_LSR_OPC) << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_LSR (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -567,7 +568,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSR (CRYPTO_Type *base, uint32_t rdst, uint32_ __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR1 (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******* V1 *********/ REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)(CY_CRYPTO_VU1_LSR1_OPC) << CY_CRYPTO_OPCODE_POS) | @@ -593,7 +594,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSR1 (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_LSR1_WITH_CARRY (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******* V1 *********/ REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)(CY_CRYPTO_VU1_LSR1_WITH_CARRY_OPC) << CY_CRYPTO_OPCODE_POS) | @@ -619,11 +620,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_LSR1_WITH_CARRY (CRYPTO_Type *base, uint32_t r __STATIC_INLINE void CY_CRYPTO_VU_COND_CLSAME (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((cy_device->cryptoVersion == 1) ? CY_CRYPTO_VU1_CLSAME_OPC : CY_CRYPTO_VU2_CLSAME_OPC) << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_CLSAME_OPC : CY_CRYPTO_VU2_CLSAME_OPC) << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_CLSAME (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -633,11 +634,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_CLSAME (CRYPTO_Type *base, uint32_t rdst, uint __STATIC_INLINE void CY_CRYPTO_VU_COND_CTSAME (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((cy_device->cryptoVersion == 1) ? CY_CRYPTO_VU1_CTSAME_OPC : CY_CRYPTO_VU2_CTSAME_OPC) << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_CTSAME_OPC : CY_CRYPTO_VU2_CTSAME_OPC) << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_CTSAME (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -647,10 +648,10 @@ __STATIC_INLINE void CY_CRYPTO_VU_CTSAME (CRYPTO_Type *base, uint32_t rdst, uint __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((cy_device->cryptoVersion == 1) ? CY_CRYPTO_VU1_SET_BIT_OPC : CY_CRYPTO_VU2_SET_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_SET_BIT_OPC : CY_CRYPTO_VU2_SET_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | - (uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_SET_BIT (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc) @@ -660,10 +661,10 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_BIT (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_CLR_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((cy_device->cryptoVersion == 1) ? CY_CRYPTO_VU1_CLR_BIT_OPC : CY_CRYPTO_VU2_CLR_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_CLR_BIT_OPC : CY_CRYPTO_VU2_CLR_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | - (uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_CLR_BIT (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc) @@ -673,10 +674,10 @@ __STATIC_INLINE void CY_CRYPTO_VU_CLR_BIT (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_INV_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((cy_device->cryptoVersion == 1) ? CY_CRYPTO_VU1_INV_BIT_OPC : CY_CRYPTO_VU2_INV_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_INV_BIT_OPC : CY_CRYPTO_VU2_INV_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | - (uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_INV_BIT (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc) @@ -686,11 +687,11 @@ __STATIC_INLINE void CY_CRYPTO_VU_INV_BIT (CRYPTO_Type *base, uint32_t rdst, uin __STATIC_INLINE void CY_CRYPTO_VU_COND_GET_BIT (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) { - REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((cy_device->cryptoVersion == 1) ? CY_CRYPTO_VU1_GET_BIT_OPC : CY_CRYPTO_VU2_GET_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | + REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)((CY_CRYPTO_HW_V1) ? CY_CRYPTO_VU1_GET_BIT_OPC : CY_CRYPTO_VU2_GET_BIT_OPC) << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_GET_BIT (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -701,17 +702,18 @@ __STATIC_INLINE void CY_CRYPTO_VU_GET_BIT (CRYPTO_Type *base, uint32_t rdst, uin /******************************************************************************/ __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_BIT_IMM (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t imm13) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******** V1 ********/ - int tmp_reg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; - uint32_t tmp_data; - CY_CRYPTO_VU_SAVE_REG(base, tmp_reg, &tmp_data); + uint32_t tmpReg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; + uint32_t tmpData; + CY_CRYPTO_VU_SAVE_REG(base, tmpReg, &tmpData); - CY_CRYPTO_VU_SET_REG(base, tmp_reg, imm13, 13); - CY_CRYPTO_VU_COND_SET_BIT(base, cc, rdst, tmp_reg); + /* Load 13 bit immediate value */ + CY_CRYPTO_VU_SET_REG(base, tmpReg, imm13, 13u); + CY_CRYPTO_VU_COND_SET_BIT(base, cc, rdst, tmpReg); - CY_CRYPTO_VU_RESTORE_REG(base, tmp_reg, tmp_data); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { @@ -719,7 +721,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_SET_BIT_IMM (CRYPTO_Type *base, uint32_t REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_SET_BIT_IMM_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC16_SHIFT) | - (uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT)); } } @@ -730,17 +732,18 @@ __STATIC_INLINE void CY_CRYPTO_VU_SET_BIT_IMM (CRYPTO_Type *base, uint32_t rdst, __STATIC_INLINE void CY_CRYPTO_VU_COND_CLR_BIT_IMM (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t imm13) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******** V1 ********/ - int tmp_reg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; - uint32_t tmp_data; - CY_CRYPTO_VU_SAVE_REG(base, tmp_reg, &tmp_data); + uint32_t tmpReg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; + uint32_t tmpData; + CY_CRYPTO_VU_SAVE_REG(base, tmpReg, &tmpData); - CY_CRYPTO_VU_SET_REG(base, tmp_reg, imm13, 13); - CY_CRYPTO_VU_COND_CLR_BIT(base, cc, rdst, tmp_reg); + /* Load 13 bit immediate value */ + CY_CRYPTO_VU_SET_REG(base, tmpReg, imm13, 13u); + CY_CRYPTO_VU_COND_CLR_BIT(base, cc, rdst, tmpReg); - CY_CRYPTO_VU_RESTORE_REG(base, tmp_reg, tmp_data); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { @@ -748,7 +751,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_CLR_BIT_IMM (CRYPTO_Type *base, uint32_t REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_CLR_BIT_IMM_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC16_SHIFT) | - (uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT)); } } @@ -759,17 +762,18 @@ __STATIC_INLINE void CY_CRYPTO_VU_CLR_BIT_IMM (CRYPTO_Type *base, uint32_t rdst, __STATIC_INLINE void CY_CRYPTO_VU_COND_INV_BIT_IMM (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t imm13) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /******** V1 ********/ - int tmp_reg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; - uint32_t tmp_data; - CY_CRYPTO_VU_SAVE_REG(base, tmp_reg, &tmp_data); + uint32_t tmpReg = (rdst != CY_CRYPTO_VU_HW_REG14) ? CY_CRYPTO_VU_HW_REG14 : CY_CRYPTO_VU_HW_REG13; + uint32_t tmpData; + CY_CRYPTO_VU_SAVE_REG(base, tmpReg, &tmpData); - CY_CRYPTO_VU_SET_REG(base, tmp_reg, imm13, 13); - CY_CRYPTO_VU_COND_INV_BIT(base, cc, rdst, tmp_reg); + /* Load 13 bit immediate value */ + CY_CRYPTO_VU_SET_REG(base, tmpReg, imm13, 13u); + CY_CRYPTO_VU_COND_INV_BIT(base, cc, rdst, tmpReg); - CY_CRYPTO_VU_RESTORE_REG(base, tmp_reg, tmp_data); + CY_CRYPTO_VU_RESTORE_REG(base, tmpReg, tmpData); } else { @@ -777,7 +781,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_INV_BIT_IMM (CRYPTO_Type *base, uint32_t REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_INV_BIT_IMM_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC16_SHIFT) | - (uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)imm13 << CY_CRYPTO_RSRC0_SHIFT)); } } @@ -791,7 +795,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_TST (CRYPTO_Type *base, uint32_t cc, uint { REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_TST_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | - (uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_TST (CRYPTO_Type *base, uint32_t rsrc) @@ -804,7 +808,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV (CRYPTO_Type *base, uint32_t cc, uint REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_MOV_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | - (uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_MOV (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc) @@ -817,7 +821,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_XSQUARE (CRYPTO_Type *base, uint32_t cc, REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_XSQUARE_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | - (uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_XSQUARE (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc) @@ -831,7 +835,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_XMUL (CRYPTO_Type *base, uint32_t cc, uin ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_XMUL (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -846,7 +850,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_UMUL (CRYPTO_Type *base, uint32_t cc, uin ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_UMUL (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -856,7 +860,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_UMUL (CRYPTO_Type *base, uint32_t rdst, uint32 __STATIC_INLINE void CY_CRYPTO_VU_COND_USQUARE (CRYPTO_Type *base, uint32_t cc, uint32_t rdst, uint32_t rsrc) { - if (cy_device->cryptoVersion == 1) + if (CY_CRYPTO_HW_V1) { /***** V1 *******/ CY_CRYPTO_VU_COND_UMUL(base, cc, rdst, rsrc, rsrc); @@ -867,7 +871,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_USQUARE (CRYPTO_Type *base, uint32_t cc, REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU2_USQUARE_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | - (uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc << CY_CRYPTO_RSRC0_SHIFT)); } } @@ -906,7 +910,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_ADD (CRYPTO_Type *base, uint32_t cc, uint ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_ADD (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -920,7 +924,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_SUB (CRYPTO_Type *base, uint32_t cc, uint ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_SUB (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -934,7 +938,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_OR (CRYPTO_Type *base, uint32_t cc, uint3 ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_OR (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -948,7 +952,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_AND (CRYPTO_Type *base, uint32_t cc, uint ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_AND (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -962,7 +966,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_XOR (CRYPTO_Type *base, uint32_t cc, uint ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_XOR (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -976,7 +980,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_NOR (CRYPTO_Type *base, uint32_t cc, uint ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_NOR (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -990,7 +994,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_NAND (CRYPTO_Type *base, uint32_t cc, uin ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rdst << CY_CRYPTO_RSRC12_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_NAND (CRYPTO_Type *base, uint32_t rdst, uint32_t rsrc1, uint32_t rsrc0) @@ -1003,7 +1007,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_CMP_SUB (CRYPTO_Type *base, uint32_t cc, REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_CMP_SUB_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_CMP_SUB (CRYPTO_Type *base, uint32_t rsrc1, uint32_t rsrc0) @@ -1016,7 +1020,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_COND_CMP_DEGREE (CRYPTO_Type *base, uint32_t c REG_CRYPTO_INSTR_FF_WR(base) = (((uint32_t)CY_CRYPTO_VU_CMP_DEGREE_OPC << CY_CRYPTO_OPCODE_POS) | ((uint32_t)cc << CY_CRYPTO_RSRC20_SHIFT) | ((uint32_t)rsrc1 << CY_CRYPTO_RSRC4_SHIFT) | - (uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT); + ((uint32_t)rsrc0 << CY_CRYPTO_RSRC0_SHIFT)); } __STATIC_INLINE void CY_CRYPTO_VU_CMP_DEGREE (CRYPTO_Type *base, uint32_t rsrc1, uint32_t rsrc0) @@ -1031,7 +1035,7 @@ __STATIC_INLINE void CY_CRYPTO_VU_SAVE_REG (CRYPTO_Type *base, uint32_t rsrc, ui __STATIC_INLINE void CY_CRYPTO_VU_RESTORE_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data) { - CY_CRYPTO_VU_SET_REG(base, rdst, CY_CRYPTO_VU_GET_REG_DATA(data), CY_CRYPTO_VU_GET_REG_SIZE(data) + 1); + CY_CRYPTO_VU_SET_REG(base, rdst, CY_CRYPTO_VU_GET_REG_DATA(data), CY_CRYPTO_VU_GET_REG_SIZE(data) + 1u); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h index 2e7f548619..f779b43e4c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h @@ -44,6 +44,11 @@ typedef uint32_t (*cy_crypto_memcmp_func_t)(CRYPTO_Type *base, typedef void (*cy_crypto_memxor_func_t)(CRYPTO_Type *base, void* dst, void const *src0, void const *src1, uint16_t size); +/** +* \addtogroup group_crypto_lld_mem_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_MemCpy ****************************************************************************//** @@ -53,7 +58,7 @@ typedef void (*cy_crypto_memxor_func_t)(CRYPTO_Type *base, void* dst, * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dst * The pointer to the destination of MemCpy. @@ -67,7 +72,7 @@ typedef void (*cy_crypto_memxor_func_t)(CRYPTO_Type *base, void* dst, *******************************************************************************/ __STATIC_INLINE void Cy_Crypto_Core_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uint16_t size) { - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { Cy_Crypto_Core_V1_MemCpy(base, dst, src, size); } @@ -85,7 +90,7 @@ __STATIC_INLINE void Cy_Crypto_Core_MemCpy(CRYPTO_Type *base, void* dst, void co * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dst * The pointer to the destination of MemSet. @@ -99,7 +104,7 @@ __STATIC_INLINE void Cy_Crypto_Core_MemCpy(CRYPTO_Type *base, void* dst, void co *******************************************************************************/ __STATIC_INLINE void Cy_Crypto_Core_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16_t size) { - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { Cy_Crypto_Core_V1_MemSet(base, dst, data, size); } @@ -117,7 +122,7 @@ __STATIC_INLINE void Cy_Crypto_Core_MemSet(CRYPTO_Type *base, void* dst, uint8_t * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param src0 * The pointer to the first source of MemCmp. @@ -134,17 +139,17 @@ __STATIC_INLINE void Cy_Crypto_Core_MemSet(CRYPTO_Type *base, void* dst, uint8_t *******************************************************************************/ __STATIC_INLINE uint32_t Cy_Crypto_Core_MemCmp(CRYPTO_Type *base, void const *src0, void const *src1, uint16_t size) { - uint32_t result; - if (cy_device->cryptoVersion == 1u) + uint32_t tmpResult; + if (CY_CRYPTO_HW_V1) { - result = Cy_Crypto_Core_V1_MemCmp(base, src0, src1, size); + tmpResult = Cy_Crypto_Core_V1_MemCmp(base, src0, src1, size); } else { - result = Cy_Crypto_Core_V2_MemCmp(base, src0, src1, size); + tmpResult = Cy_Crypto_Core_V2_MemCmp(base, src0, src1, size); } - return (result); + return (tmpResult); } /******************************************************************************* @@ -156,7 +161,7 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_MemCmp(CRYPTO_Type *base, void const *sr * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dst * The pointer to the destination of MemXor. @@ -174,7 +179,7 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_MemCmp(CRYPTO_Type *base, void const *sr __STATIC_INLINE void Cy_Crypto_Core_MemXor(CRYPTO_Type *base, void* dst, void const *src0, void const *src1, uint16_t size) { - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { Cy_Crypto_Core_V1_MemXor(base, dst, src0, src1, size); } @@ -184,6 +189,7 @@ __STATIC_INLINE void Cy_Crypto_Core_MemXor(CRYPTO_Type *base, void* dst, } } +/** \} group_crypto_lld_mem_functions */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h index cad1b88604..fcdf41a24b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h @@ -45,6 +45,11 @@ typedef cy_en_crypto_status_t (*cy_crypto_prng_func_t)(CRYPTO_Type *base, uint32_t max, uint32_t *randomNum); +/** +* \addtogroup group_crypto_lld_rng_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Prng_Init ****************************************************************************//** @@ -53,7 +58,7 @@ typedef cy_en_crypto_status_t (*cy_crypto_prng_func_t)(CRYPTO_Type *base, * Invoking this function causes a restart of the pseudo-random sequence. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param lfsr32InitState * A non-zero seed value for the first LFSR. @@ -65,7 +70,7 @@ typedef cy_en_crypto_status_t (*cy_crypto_prng_func_t)(CRYPTO_Type *base, * A non-zero seed value for the third LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Prng_Init(CRYPTO_Type *base, @@ -73,18 +78,18 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Prng_Init(CRYPTO_Type *base uint32_t lfsr31InitState, uint32_t lfsr29InitState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Prng_Init(base, lfsr32InitState, lfsr31InitState, lfsr29InitState); + tmpResult = Cy_Crypto_Core_V1_Prng_Init(base, lfsr32InitState, lfsr31InitState, lfsr29InitState); } else { - myResult = Cy_Crypto_Core_V2_Prng_Init(base, lfsr32InitState, lfsr31InitState, lfsr29InitState); + tmpResult = Cy_Crypto_Core_V2_Prng_Init(base, lfsr32InitState, lfsr31InitState, lfsr29InitState); } - return myResult; + return tmpResult; } /******************************************************************************* @@ -94,7 +99,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Prng_Init(CRYPTO_Type *base * Generates a Pseudo Random Number. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param max * The maximum value of a random number. @@ -103,27 +108,29 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Prng_Init(CRYPTO_Type *base * The pointer to a variable to store the generated pseudo random number. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Prng(CRYPTO_Type *base, uint32_t max, uint32_t *randomNum) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Prng(base, max, randomNum); + tmpResult = Cy_Crypto_Core_V1_Prng(base, max, randomNum); } else { - myResult = Cy_Crypto_Core_V2_Prng(base, max, randomNum); + tmpResult = Cy_Crypto_Core_V2_Prng(base, max, randomNum); } - return myResult; + return tmpResult; } +/** \} group_crypto_lld_rng_functions */ + #endif /* #if (CPUSS_CRYPTO_PR == 1) */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h index 783b54c06f..caf2e587fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h @@ -42,6 +42,11 @@ typedef cy_en_crypto_status_t (*cy_crypto_sha_func_t)(CRYPTO_Type *base, uint8_t *digest, cy_en_crypto_sha_mode_t mode); +/** +* \addtogroup group_crypto_lld_sha_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Sha ****************************************************************************//** @@ -49,22 +54,22 @@ typedef cy_en_crypto_status_t (*cy_crypto_sha_func_t)(CRYPTO_Type *base, * Performs the SHA Hash function. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param mode * \ref cy_en_crypto_sha_mode_t * * \param message -* The pointer to a message whose hash value is being computed. +* The pointer to the message whose hash value is being computed. * * \param messageSize -* The size of a message. +* The size of the message. * * \param digest * The pointer to the hash digest. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha(CRYPTO_Type *base, @@ -73,41 +78,41 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha(CRYPTO_Type *base, uint8_t *digest, cy_en_crypto_sha_mode_t mode) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Sha(base, message, messageSize, digest, mode); + tmpResult = Cy_Crypto_Core_V1_Sha(base, message, messageSize, digest, mode); } else { - myResult = Cy_Crypto_Core_V2_Sha(base, message, messageSize, digest, mode); + tmpResult = Cy_Crypto_Core_V2_Sha(base, message, messageSize, digest, mode); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Sha_Init ****************************************************************************//** * -* The function to initialize SHA operation. +* The function to initialize the SHA operation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param shaHashState -* The pointer to a Hash State. +* The pointer to a Hash state. * * \param mode * One of these: CY_CRYPTO_SHA256, CY_CRYPTO_SHA1, CY_CRYPTO_SHA256_224, * CY_CRYPTO_SHA512, CY_CRYPTO_SHA384, CY_CRYPTO_SHA512_224, CY_CRYPTO_SHA512_256 * * \param shaBuffers -* The pointer to memory buffers storage +* The pointer to the memory buffers storage. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Init(CRYPTO_Type *base, @@ -115,50 +120,50 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Init(CRYPTO_Type *base, cy_en_crypto_sha_mode_t mode, void *shaBuffers) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Sha_Init(base, shaHashState, mode, shaBuffers); + tmpResult = Cy_Crypto_Core_V1_Sha_Init(base, shaHashState, mode, shaBuffers); } else { - myResult = Cy_Crypto_Core_V2_Sha_Init(base, shaHashState, mode, shaBuffers); + tmpResult = Cy_Crypto_Core_V2_Sha_Init(base, shaHashState, mode, shaBuffers); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_Sha_Start ****************************************************************************//** * -* Initializes the initial hash vector. +* Initializes the initial Hash vector. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Start(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Sha_Start(base, hashState); + tmpResult = Cy_Crypto_Core_V1_Sha_Start(base, hashState); } else { - myResult = Cy_Crypto_Core_V2_Sha_Start(base, hashState); + tmpResult = Cy_Crypto_Core_V2_Sha_Start(base, hashState); } - return myResult; + return tmpResult; } /******************************************************************************* @@ -168,7 +173,7 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Start(CRYPTO_Type *base * Performs the SHA calculation on one message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. @@ -180,12 +185,12 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Start(CRYPTO_Type *base * The size of the message whose Hash is being computed. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \note * This function can be called several times only with message lengths dividable -* by block size. Only the last call to the function can process a message with -* the not dividable size. +* by the block size. Only the last call to the function can process a message with +* a not-dividable size. * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Update(CRYPTO_Type *base, @@ -193,55 +198,55 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Update(CRYPTO_Type *bas uint8_t const *message, uint32_t messageSize) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Sha_Update(base, hashState, message, messageSize); + tmpResult = Cy_Crypto_Core_V1_Sha_Update(base, hashState, message, messageSize); } else { - myResult = Cy_Crypto_Core_V2_Sha_Update(base, hashState, message, messageSize); + tmpResult = Cy_Crypto_Core_V2_Sha_Update(base, hashState, message, messageSize); } - return myResult; + return tmpResult; } /******************************************************************************* * Function Name: Cy_Crypto_Core_V1_Sha_Finish ****************************************************************************//** * -* Completes SHA calculation. +* Completes the SHA calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. * * \param digest -* The pointer to the calculated hash digest. +* The pointer to the calculated Hash digest. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Finish(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState, uint8_t *digest) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Sha_Finish(base, hashState, digest); + tmpResult = Cy_Crypto_Core_V1_Sha_Finish(base, hashState, digest); } else { - myResult = Cy_Crypto_Core_V2_Sha_Finish(base, hashState, digest); + tmpResult = Cy_Crypto_Core_V2_Sha_Finish(base, hashState, digest); } - return myResult; + return tmpResult; } /******************************************************************************* @@ -251,31 +256,32 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Finish(CRYPTO_Type *bas * Clears the used memory buffers. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Sha_Free(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState) { - cy_en_crypto_status_t myResult; + cy_en_crypto_status_t tmpResult; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { - myResult = Cy_Crypto_Core_V1_Sha_Free(base, hashState); + tmpResult = Cy_Crypto_Core_V1_Sha_Free(base, hashState); } else { - myResult = Cy_Crypto_Core_V2_Sha_Free(base, hashState); + tmpResult = Cy_Crypto_Core_V2_Sha_Free(base, hashState); } - return myResult; + return tmpResult; } +/** \} group_crypto_lld_sha_functions */ #endif /* #if (CPUSS_CRYPTO_SHA == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h index ec23625dc0..621272f47e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h @@ -38,37 +38,37 @@ typedef struct { - /* Allocate CRYPTO_MAX_BLOCK_SIZE Bytes for block */ + /* Allocates CRYPTO_MAX_BLOCK_SIZE Bytes for the block. */ uint32_t block[CY_CRYPTO_SHA1_BLOCK_SIZE / 4u]; - /* Allocate CRYPTO_MAX_HASH_SIZE Bytes for hash */ + /* Allocates CRYPTO_MAX_HASH_SIZE Bytes for the hash. */ uint32_t hash[CY_CRYPTO_SHA1_HASH_SIZE / 4u]; - /* Allocate CRYPTO_MAX_ROUND_MEM_SIZE Bytes for roundMem */ + /* Allocates CRYPTO_MAX_ROUND_MEM_SIZE Bytes for roundMem. */ uint32_t roundMem[CY_CRYPTO_SHA1_ROUND_MEM_SIZE / 4u]; } cy_stc_crypto_v1_sha1_buffers_t; typedef struct { - /* Allocate CRYPTO_MAX_BLOCK_SIZE Bytes for block */ + /* Allocates CRYPTO_MAX_BLOCK_SIZE Bytes for the block. */ uint32_t block[CY_CRYPTO_SHA256_BLOCK_SIZE / 4u]; - /* Allocate CRYPTO_MAX_HASH_SIZE Bytes for hash */ + /* Allocates CRYPTO_MAX_HASH_SIZE Bytes for the hash. */ uint32_t hash[CY_CRYPTO_SHA256_HASH_SIZE / 4u]; - /* Allocate CRYPTO_MAX_ROUND_MEM_SIZE Bytes for roundMem */ + /* Allocates CRYPTO_MAX_ROUND_MEM_SIZE Bytes for roundMem. */ uint32_t roundMem[CY_CRYPTO_SHA256_ROUND_MEM_SIZE / 4u]; } cy_stc_crypto_v1_sha256_buffers_t; typedef struct { - /* Allocate CRYPTO_MAX_BLOCK_SIZE Bytes for block */ + /* Allocates CRYPTO_MAX_BLOCK_SIZE Bytes for the block. */ uint32_t block[CY_CRYPTO_SHA512_BLOCK_SIZE / 4u]; - /* Allocate CRYPTO_MAX_HASH_SIZE Bytes for hash */ + /* Allocates CRYPTO_MAX_HASH_SIZE Bytes for the hash. */ uint32_t hash[CY_CRYPTO_SHA512_HASH_SIZE / 4u]; - /* Allocate CRYPTO_MAX_ROUND_MEM_SIZE Bytes for roundMem */ + /* Allocates CRYPTO_MAX_ROUND_MEM_SIZE Bytes for roundMem. */ uint32_t roundMem[CY_CRYPTO_SHA512_ROUND_MEM_SIZE / 4u]; } cy_stc_crypto_v1_sha512_buffers_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h index 720dd31d9d..11e842b0e0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h @@ -38,7 +38,7 @@ /** \cond INTERNAL */ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, - cy_stc_crypto_sha_state_t *shaHashState, + cy_stc_crypto_sha_state_t *hashState, cy_en_crypto_sha_mode_t mode, void *shaBuffers); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h index a9c234fd94..def797749e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h @@ -42,15 +42,19 @@ typedef cy_en_crypto_status_t (*cy_crypto_trng_func_t)(CRYPTO_Type *base, uint32_t max, uint32_t *randomNum); +/** +* \addtogroup group_crypto_lld_rng_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Trng ****************************************************************************//** * -* Generates a True Random Number and returns it in the -* cfContext->trngNumPtr. +* Generates a True Random Number. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param GAROPol * The polynomial for the programmable Galois ring oscillator. @@ -59,13 +63,13 @@ typedef cy_en_crypto_status_t (*cy_crypto_trng_func_t)(CRYPTO_Type *base, * The polynomial for the programmable Fibonacci ring oscillator. * * \param max -* The maximum length of a random number, in the range [0, 32] bits. +* The maximum length of a random number, in the range of [0, 32] bits. * * \param randomNum * The pointer to a generated true random number. Must be 4-byte aligned. * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Trng(CRYPTO_Type *base, @@ -74,18 +78,19 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Trng(CRYPTO_Type *base, uint32_t max, uint32_t *randomNum) { - cy_en_crypto_status_t result; - if (cy_device->cryptoVersion == 1u) + cy_en_crypto_status_t tmpResult; + if (CY_CRYPTO_HW_V1) { - result = Cy_Crypto_Core_V1_Trng(base, GAROPol, FIROPol, max, randomNum); + tmpResult = Cy_Crypto_Core_V1_Trng(base, GAROPol, FIROPol, max, randomNum); } else { - result = Cy_Crypto_Core_V2_Trng(base, GAROPol, FIROPol, max, randomNum); + tmpResult = Cy_Crypto_Core_V2_Trng(base, GAROPol, FIROPol, max, randomNum); } - return (result); + return (tmpResult); } +/** \} group_crypto_lld_rng_functions */ #endif /* #if (CPUSS_CRYPTO_TR == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h index 065c5672de..0eb516b9b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h @@ -182,11 +182,11 @@ #define CY_CRYPTO_V1_TR_CUTOFF_COUNT8 (1UL) /** -Cut-off count (legal range is [1, 65535]). -"0": Illegal. -"1": 1 occurrence. -... -"65535": 65535 occurrences. +* Cut-off count (legal range is [1, 65535]). +* "0": Illegal. +* "1": 1 occurrence. +* ... +* "65535": 65535 occurrences. */ #define CY_CRYPTO_V1_TR_CUTOFF_COUNT16 (1UL) @@ -196,9 +196,9 @@ Cut-off count (legal range is [1, 65535]). * ... * "65535": 65536 bits. */ -#define CY_CRYPTO_V1_TR_WINDOW_SIZE (1uL) +#define CY_CRYPTO_V1_TR_WINDOW_SIZE (1UL) -/** the composed value for the TR_CTL0 register */ +/** The composed value for the TR_CTL0 register */ #define CY_CRYPTO_V1_TR_CTL0_VAL (_VAL2FLD(CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV, CY_CRYPTO_V1_TR_SAMPLE_CLOCK_DIV) | \ _VAL2FLD(CRYPTO_TR_CTL0_RED_CLOCK_DIV, CY_CRYPTO_V1_TR_RED_CLOCK_DIV) | \ _VAL2FLD(CRYPTO_TR_CTL0_INIT_DELAY, CY_CRYPTO_V1_TR_INIT_DELAY) | \ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h index b193efdfbc..165b12aeb7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h @@ -182,11 +182,11 @@ #define CY_CRYPTO_V2_TR_CUTOFF_COUNT8 (1UL) /** -Cut-off count (legal range is [1, 65535]). -"0": Illegal. -"1": 1 occurrence. -... -"65535": 65535 occurrences. +* Cut-off count (legal range is [1, 65535]). +* "0": Illegal. +* "1": 1 occurrence. +* ... +* "65535": 65535 occurrences. */ #define CY_CRYPTO_V2_TR_CUTOFF_COUNT16 (1UL) @@ -196,9 +196,9 @@ Cut-off count (legal range is [1, 65535]). * ... * "65535": 65536 bits. */ -#define CY_CRYPTO_V2_TR_WINDOW_SIZE (1uL) +#define CY_CRYPTO_V2_TR_WINDOW_SIZE (1UL) -/** the composed value for the TR_CTL0 register */ +/** The composed value for the TR_CTL0 register */ #define CY_CRYPTO_V2_TR_CTL0_VAL (_VAL2FLD(CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV, CY_CRYPTO_V2_TR_SAMPLE_CLOCK_DIV) | \ _VAL2FLD(CRYPTO_TR_CTL0_RED_CLOCK_DIV, CY_CRYPTO_V2_TR_RED_CLOCK_DIV) | \ _VAL2FLD(CRYPTO_TR_CTL0_INIT_DELAY, CY_CRYPTO_V2_TR_INIT_DELAY) | \ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h index ad6b4b1a49..b4d79349ec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h @@ -46,7 +46,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Trng(CRYPTO_Type *base, #endif /* CY_IP_MXCRYPTO */ -#endif /* #if !defined(CY_CRYPTO_CORE_TRNG_H) */ +#endif /* #if !defined(CY_CRYPTO_CORE_TRNG_V1_H) */ /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h index 27cbdd49e9..c0741a4a27 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h @@ -41,17 +41,22 @@ #define CY_CRYPTO_VU_DATA_FLD_MASK (0x00003fffuL) #define CY_CRYPTO_VU_DATA_FLD_POS (16u) +/** +* \addtogroup group_crypto_lld_vu_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Cleanup ****************************************************************************//** * -* Cleanup the the CRYPTO block. +* Cleans up the Crypto block. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_Cleanup(CRYPTO_Type *base); @@ -60,10 +65,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_Cleanup(CRYPTO_Type *base); * Function Name: Cy_Crypto_Core_Vu_SetMemValue ****************************************************************************//** * -* Sets the value in the crypto memory allocated by destination VU register. +* Sets the value in the Crypto memory allocated by the destination VU register. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dstReg * The destination vector unit register. @@ -84,7 +89,7 @@ void Cy_Crypto_Core_Vu_SetMemValue(CRYPTO_Type *base, uint32_t dstReg, uint8_t c * Gets the value located in the crypto memory and pointed by source VU register. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dst * The pointer to the destination value. @@ -102,10 +107,10 @@ void Cy_Crypto_Core_Vu_GetMemValue(CRYPTO_Type *base, uint8_t *dst, uint32_t src * Function Name: Cy_Crypto_Core_Vu_IsRegZero ****************************************************************************//** * -* Returns TRUE if srcReg contains 0. FALSE otherwise. +* Returns TRUE if srcReg contains 0. FALSE - otherwise. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -120,10 +125,10 @@ bool Cy_Crypto_Core_Vu_IsRegZero(CRYPTO_Type *base, uint32_t srcReg); * Function Name: Cy_Crypto_Core_Vu_IsRegEqual ****************************************************************************//** * -* Returns TRUE if srcReg0 contains the same value as srcReg1. FALSE otherwise. +* Returns TRUE if srcReg0 contains the same value as srcReg1. FALSE - otherwise. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg0 * The source 0 vector unit register. @@ -142,10 +147,10 @@ bool Cy_Crypto_Core_Vu_IsRegEqual(CRYPTO_Type *base, uint32_t srcReg0, uint32_t ****************************************************************************//** * * Returns TRUE if srcReg0 contains the value less than value of srcReg1. -* FALSE otherwise. +* FALSE - otherwise. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg0 * The source 0 vector unit register. @@ -163,10 +168,10 @@ bool Cy_Crypto_Core_Vu_IsRegLess(CRYPTO_Type *base, uint32_t srcReg0, uint32_t s * Function Name: Cy_Crypto_Core_Vu_RegRead ****************************************************************************//** * -* Returns the data pointed in given register +* Returns the data pointed in a given register. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -185,7 +190,7 @@ __STATIC_INLINE uint32_t Cy_Crypto_Core_Vu_RegRead(CRYPTO_Type *base, uint32_t s * it is lower 12Bit of the 32Bit word * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -204,7 +209,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegSizeRead(CRYPTO_Type *base, uint32 * It is lower 12Bit of the 32Bit word * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -223,7 +228,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegBitSizeRead(CRYPTO_Type *base, uin * It is lower 12Bit of the 32Bit word * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -242,7 +247,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegByteSizeRead(CRYPTO_Type *base, ui * It is lower 12Bit of the 32Bit word * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -261,7 +266,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegWordSizeRead(CRYPTO_Type *base, ui * it is upper 16Bit of the 32Bir word. Pointer is in words (uint32_t). * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -269,7 +274,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegWordSizeRead(CRYPTO_Type *base, ui *******************************************************************************/ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegDataPtrRead(CRYPTO_Type *base, uint32_t srcReg) { - return ((uint16_t)(_FLD2VAL(CRYPTO_RF_DATA_DATA32, REG_CRYPTO_VU_RF_DATA(base, srcReg)) >> CY_CRYPTO_VU_DATA_FLD_POS) + return (uint16_t)((_FLD2VAL(CRYPTO_RF_DATA_DATA32, REG_CRYPTO_VU_RF_DATA(base, srcReg)) >> CY_CRYPTO_VU_DATA_FLD_POS) & CY_CRYPTO_VU_DATA_FLD_MASK); } @@ -280,7 +285,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegDataPtrRead(CRYPTO_Type *base, uin * Returns the memory address of the data pointed in given register. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcReg * The source vector unit register. @@ -288,7 +293,7 @@ __STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegDataPtrRead(CRYPTO_Type *base, uin *******************************************************************************/ __STATIC_INLINE uint32_t * Cy_Crypto_Core_Vu_RegMemPointer(CRYPTO_Type *base, uint32_t srcReg) { - return (uint32_t *)((uint32_t)REG_CRYPTO_MEM_BUFF(base) + 4u * (uint32_t)Cy_Crypto_Core_Vu_RegDataPtrRead(base, srcReg)); + return (uint32_t *)((uint32_t)REG_CRYPTO_MEM_BUFF(base) + (4u * (uint32_t)Cy_Crypto_Core_Vu_RegDataPtrRead(base, srcReg))); } /******************************************************************************* @@ -298,13 +303,13 @@ __STATIC_INLINE uint32_t * Cy_Crypto_Core_Vu_RegMemPointer(CRYPTO_Type *base, ui * Waits until VU instruction will be completed * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ __STATIC_INLINE void Cy_Crypto_Core_Vu_WaitForComplete(CRYPTO_Type *base) { /* Wait until the VU instruction is complete */ - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { while (0uL != _FLD2VAL(CRYPTO_STATUS_VU_BUSY, REG_CRYPTO_STATUS(base))) { @@ -322,19 +327,20 @@ __STATIC_INLINE void Cy_Crypto_Core_Vu_WaitForComplete(CRYPTO_Type *base) * Function Name: Cy_Crypto_Core_Vu_StatusRead ****************************************************************************//** * -* Returns value of the VU status register +* Returns the value of the VU status register. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ -__STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_StatusRead(CRYPTO_Type *base) +__STATIC_INLINE uint32_t Cy_Crypto_Core_Vu_StatusRead(CRYPTO_Type *base) { Cy_Crypto_Core_Vu_WaitForComplete(base); - return((uint16_t)REG_CRYPTO_VU_STATUS(base)); + return((uint32_t)REG_CRYPTO_VU_STATUS(base)); } +/** \} group_crypto_lld_vu_functions */ #endif /* #if (CPUSS_CRYPTO_VU == 1) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h index f25efba8d4..99d9ce5996 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h @@ -63,7 +63,7 @@ extern "C" { * the Crypto server context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \funcusage * \snippet crypto/2.10/snippet/main.c snippet_myCryptoServerStartBase @@ -94,7 +94,7 @@ cy_en_crypto_status_t Cy_Crypto_Server_Start_Base(cy_stc_crypto_config_t const * * the Crypto server context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * Refer to \ref Cy_Crypto_Server_Start_Base for the function usage example. * @@ -124,7 +124,7 @@ cy_en_crypto_status_t Cy_Crypto_Server_Start_Extra(cy_stc_crypto_config_t const * the Crypto server context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * Refer to \ref Cy_Crypto_Server_Start_Base for the function usage example. * @@ -142,7 +142,7 @@ cy_en_crypto_status_t Cy_Crypto_Server_Start_Full(cy_stc_crypto_config_t const * * This function available for Server side only. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Server_Stop(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h index 44ecd5499e..f60560f49c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h @@ -189,6 +189,8 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * Register Access Helper Macros *******************************************************************************/ +#define CY_CRYPTO_HW_V1 (1U == cy_device->cryptoVersion) /* true if the mxcrypto version is 1 */ + #define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath)) #define CY_SRSS_NUM_PLL ((uint32_t)(cy_device->srssNumPll)) #define CY_SRSS_NUM_HFROOT ((uint32_t)(cy_device->srssNumHfroot)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h index 5c1a7f182a..3ed8b87027 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h @@ -36,6 +36,7 @@ #include "cy_ctb.h" #include "cy_ctdac.h" #include "cy_dma.h" +#include "cy_dmac.h" #include "cy_efuse.h" #include "cy_flash.h" #include "cy_gpio.h" @@ -55,8 +56,10 @@ #include "cy_scb_i2c.h" #include "cy_scb_spi.h" #include "cy_scb_uart.h" +#include "cy_sd_host.h" #include "cy_smartio.h" #include "cy_smif.h" +#include "cy_smif_memslot.h" #include "cy_sysanalog.h" #include "cy_sysclk.h" #include "cy_sysint.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h index f2811c245e..3c71b78aab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h @@ -112,6 +112,7 @@ * Updated the following functions implementation: \ref Cy_SysClk_EcoEnable, \ref Cy_SysClk_EcoGetStatus, \ref Cy_SysClk_FllGetConfiguration \n * and \ref Cy_SysClk_DeepSleepCallback. \n * The \ref Cy_SysClk_DeepSleepCallback now implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. \n +* The actions that were done in \ref CY_SYSPM_CHECK_READY case are moved to \ref CY_SYSPM_BEFORE_TRANSITION. \n * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL. * Defect fixing. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c index e14ba10b10..cd2e3a1f8a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ble_clk.c -* \version 3.0 +* \version 3.10 * * \brief * This driver provides the source code for API BLE ECO clock. @@ -138,8 +138,8 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq /* Range for inputs parameters */ -#define CY_BLE_ECO_XTAL_SRART_UP_TIME_MAX ((uint8_t) (4593.75 / 31.25)) -#define CY_BLE_ECO_XTAL_SRART_UP_TIME_MIN ((uint8_t) (400 / 31.25)) +#define CY_BLE_ECO_XTAL_START_UP_TIME_MAX ((uint8_t) (4593.75 / 31.25)) +#define CY_BLE_ECO_XTAL_START_UP_TIME_MIN ((uint8_t) (400 / 31.25)) #define CY_BLE_ECO_CLOAD_MIN ((uint8_t) ((7.5 - 7.5)/0.075)) #define CY_BLE_ECO_CLOAD_MAX ((uint8_t) ((26.325 - 7.5)/0.075)) @@ -220,7 +220,7 @@ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_ uint32_t temp = 0UL; if( (freq > CY_BLE_BLESS_ECO_FREQ_32MHZ) || (sysClkDiv > CY_BLE_SYS_ECO_CLK_DIV_8) || - (xtalStartUpTime > CY_BLE_ECO_XTAL_SRART_UP_TIME_MAX) || (xtalStartUpTime < CY_BLE_ECO_XTAL_SRART_UP_TIME_MIN) || + (xtalStartUpTime > CY_BLE_ECO_XTAL_START_UP_TIME_MAX) || (xtalStartUpTime < CY_BLE_ECO_XTAL_START_UP_TIME_MIN) || (cLoad > CY_BLE_ECO_CLOAD_MAX)) { status = CY_BLE_ECO_BAD_PARAM; @@ -355,7 +355,7 @@ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_ /* Clear the BLERD_ACTIVE_INTR */ BLE_BLESS_INTR_STAT |= BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk; - if(!Cy_SysPm_SimoBuckOutputIsEnabled(CY_SYSPM_BUCK_VRF)) + if((!Cy_SysPm_SimoBuckOutputIsEnabled(CY_SYSPM_BUCK_VRF)) || (voltageReg == CY_BLE_ECO_VOLTAGE_REG_BLESSLDO)) { temp |= BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c index 0fd3c1604a..66bd2e6184 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c @@ -171,7 +171,7 @@ cy_en_crypto_status_t Cy_Crypto_Sync(bool isBlocking) * This function is internal and should not to be called directly by user software. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ static cy_en_crypto_status_t Cy_Crypto_Client_Send(void) @@ -309,7 +309,7 @@ cy_en_crypto_status_t Cy_Crypto_Enable(void) * The pointer to a variable to store gathered crypto library information. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_GetLibraryInfo(cy_en_crypto_lib_info_t *cryptoInfo) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c index 4f3e3c082e..f7a67e20b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c @@ -44,10 +44,11 @@ static void Cy_Crypto_Core_V1_Aes_InvKey(CRYPTO_Type *base, cy_stc_crypto_aes_st * Performs the AES block cipher. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \param dirMode * One of CRYPTO_ENCRYPT or CRYPTO_DECRYPT. @@ -90,10 +91,11 @@ void Cy_Crypto_Core_V1_Aes_ProcessBlock(CRYPTO_Type *base, * All addresses must be 4-Byte aligned! * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \param dstBlock * The pointer to the memory structure with the XOR results. @@ -136,10 +138,11 @@ void Cy_Crypto_Core_V1_Aes_Xor(CRYPTO_Type *base, * Calculates an inverse block cipher key from the block cipher key. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * *******************************************************************************/ static void Cy_Crypto_Core_V1_Aes_InvKey(CRYPTO_Type *base, cy_stc_crypto_aes_state_t const *aesState) @@ -162,10 +165,10 @@ static void Cy_Crypto_Core_V1_Aes_InvKey(CRYPTO_Type *base, cy_stc_crypto_aes_st * Function Name: Cy_Crypto_Core_V1_Aes_Init ****************************************************************************//** * -* Sets Aes mode and prepare inversed key. +* Sets AES mode and prepares an inverse key. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param key * The pointer to the encryption/decryption key. @@ -174,10 +177,11 @@ static void Cy_Crypto_Core_V1_Aes_InvKey(CRYPTO_Type *base, cy_stc_crypto_aes_st * \ref cy_en_crypto_aes_key_length_t * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Init(CRYPTO_Type *base, @@ -212,10 +216,10 @@ void Cy_Crypto_Core_V1_Aes_Free(CRYPTO_Type *base) * Function Name: Cy_Crypto_Core_V1_Aes_Ecb ****************************************************************************//** * -* Performs AES operation on one Block. +* Performs an AES operation on one block. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -228,10 +232,11 @@ void Cy_Crypto_Core_V1_Aes_Free(CRYPTO_Type *base) * The pointer to a source block. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ecb(CRYPTO_Type *base, @@ -258,7 +263,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ecb(CRYPTO_Type *base, * Performs AES operation on a plain text with Cipher Block Chaining (CBC). * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -277,10 +282,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ecb(CRYPTO_Type *base, * The pointer to a source plain text. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, @@ -298,17 +304,17 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, uint32_t *srcBuff = (uint32_t*)(&aesBuffers->block0); uint32_t *dstBuff = (uint32_t*)(&aesBuffers->block1); - cy_en_crypto_status_t myResult = CY_CRYPTO_SIZE_NOT_X16; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SIZE_NOT_X16; /* Check whether the data size is multiple of CY_CRYPTO_AES_BLOCK_SIZE */ - if (0uL == (uint32_t)(size & (CY_CRYPTO_AES_BLOCK_SIZE - 1u))) + if (0UL == (uint32_t)(size & (CY_CRYPTO_AES_BLOCK_SIZE - 1U))) { /* Copy the Initialization Vector to the local buffer because it changes during calculation */ Cy_Crypto_Core_V1_MemCpy(base, tempBuff, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); if (CY_CRYPTO_DECRYPT == dirMode) { - while (size > 0uL) + while (size != 0UL) { /* source message block */ Cy_Crypto_Core_V1_MemCpy(base, srcBuff, src, CY_CRYPTO_AES_BLOCK_SIZE); @@ -329,7 +335,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, } else { - while (size > 0uL) + while (size != 0UL) { /* source message block */ Cy_Crypto_Core_V1_MemCpy(base, srcBuff, src, CY_CRYPTO_AES_BLOCK_SIZE); @@ -349,10 +355,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, } } - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -362,7 +368,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, * Performs AES operation on a plain text with the Cipher Feedback Block method (CFB). * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -381,10 +387,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cbc(CRYPTO_Type *base, * The pointer to a source plain text. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user must +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, @@ -396,7 +403,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState) { uint32_t size = srcSize; - cy_en_crypto_status_t myResult = CY_CRYPTO_SIZE_NOT_X16; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SIZE_NOT_X16; cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t*)aesState->buffers; @@ -406,17 +413,17 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, uint32_t *encBuff = dstBuff; /* Default operation is ENCRYPT */ /* Check whether the data size is multiple of CY_CRYPTO_AES_BLOCK_SIZE */ - if (0uL == (size & (CY_CRYPTO_AES_BLOCK_SIZE - 1u))) + if (0UL == (size & (CY_CRYPTO_AES_BLOCK_SIZE - 1U))) { if (CY_CRYPTO_DECRYPT == dirMode) { encBuff = srcBuff; } - /* Copy the Initialization Vector to local encode buffer */ + /* Copies the Initialization Vector to the local encode buffer. */ Cy_Crypto_Core_V1_MemCpy(base, encBuff, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); - while (size > 0uL) + while (size != 0UL) { /* In this mode, (CFB) is always an encryption! */ Cy_Crypto_Core_V1_Aes_ProcessBlock(base, aesState, CY_CRYPTO_ENCRYPT, dstBuff, encBuff); @@ -435,20 +442,20 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, size -= CY_CRYPTO_AES_BLOCK_SIZE; } - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } - return (myResult); + return (tmpResult); } /******************************************************************************* * Function Name: Cy_Crypto_Core_V1_Aes_Ctr ******************************************************************************** * -* Performs AES operation on a plain text using the counter method (CTR). +* Performs an AES operation on a plain text using the counter method (CTR). * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcSize * The size of a source plain text. @@ -458,7 +465,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, * current cipher stream. * * \param ivPtr -* The 128-bit nonce and counter. +* The 128-bit initial vector and counter. * * \param streamBlock * The saved stream-block for resuming. Is over-written by the function. @@ -470,13 +477,14 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Cfb(CRYPTO_Type *base, * The pointer to a source plain text. Must be 4-Byte aligned. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user must +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ -#define CY_CRYPTO_AES_CTR_CNT_POS (0x02u) +#define CY_CRYPTO_AES_CTR_CNT_POS (0x02U) cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ctr(CRYPTO_Type *base, uint32_t srcSize, uint32_t *srcOffset, @@ -491,28 +499,28 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ctr(CRYPTO_Type *base, uint64_t counter; cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t*)aesState->buffers; - uint32_t *nonceCounter = (uint32_t*)(&aesBuffers->iv); + uint32_t *blockCounter = (uint32_t*)(&aesBuffers->iv); uint32_t *srcBuff = (uint32_t*)(&aesBuffers->block0); uint32_t *dstBuff = (uint32_t*)(&aesBuffers->block1); uint32_t *streamBuff = (uint32_t*)(&aesBuffers->block2); - Cy_Crypto_Core_V1_MemCpy(base, nonceCounter, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V1_MemCpy(base, blockCounter, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); - counter = CY_SWAP_ENDIAN64(*(uint64_t*)(nonceCounter + CY_CRYPTO_AES_CTR_CNT_POS)); + counter = CY_SWAP_ENDIAN64(*(uint64_t*)(blockCounter + CY_CRYPTO_AES_CTR_CNT_POS)); cnt = (uint32_t)(srcSize / CY_CRYPTO_AES_BLOCK_SIZE); - for (i = 0uL; i < cnt; i++) + for (i = 0UL; i < cnt; i++) { /* source message block */ Cy_Crypto_Core_V1_MemCpy(base, srcBuff, src, CY_CRYPTO_AES_BLOCK_SIZE); /* In this mode, (CTR) is always an encryption! */ - Cy_Crypto_Core_V1_Aes_ProcessBlock(base, aesState, CY_CRYPTO_ENCRYPT, streamBuff, nonceCounter); + Cy_Crypto_Core_V1_Aes_ProcessBlock(base, aesState, CY_CRYPTO_ENCRYPT, streamBuff, blockCounter); - /* Increment the nonce counter, at least 64Bits (from 128) is the counter part */ + /* Increment the block counter, at least 64Bits (from 128) is the counter part */ counter++; - *(uint64_t*)(nonceCounter + CY_CRYPTO_AES_CTR_CNT_POS) = CY_SWAP_ENDIAN64(counter); + *(uint64_t*)(blockCounter + CY_CRYPTO_AES_CTR_CNT_POS) = CY_SWAP_ENDIAN64(counter); Cy_Crypto_Core_V1_Aes_Xor(base, aesState, dstBuff, srcBuff, streamBuff); @@ -523,7 +531,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ctr(CRYPTO_Type *base, dst += CY_CRYPTO_AES_BLOCK_SIZE; } - Cy_Crypto_Core_V1_MemCpy(base, ivPtr, nonceCounter, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V1_MemCpy(base, ivPtr, blockCounter, CY_CRYPTO_AES_BLOCK_SIZE); /* Save the reminder of the last non-complete block */ *srcOffset = (uint32_t)(srcSize % CY_CRYPTO_AES_BLOCK_SIZE); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c index 54015cc8a8..173e232774 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c @@ -45,10 +45,11 @@ * Calculates an inverse block cipher key from the block cipher key. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * *******************************************************************************/ void Cy_Crypto_Core_V2_Aes_LoadEncKey(CRYPTO_Type *base, @@ -77,10 +78,11 @@ void Cy_Crypto_Core_V2_Aes_LoadEncKey(CRYPTO_Type *base, * Calculates an inverse block cipher key from the block cipher key. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * *******************************************************************************/ void Cy_Crypto_Core_V2_Aes_LoadDecKey(CRYPTO_Type *base, @@ -109,10 +111,10 @@ void Cy_Crypto_Core_V2_Aes_LoadDecKey(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V2_Aes_Init ****************************************************************************//** * -* Sets Aes mode and prepare inversed key. +* Sets AES mode and prepares inverse key. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param key * The pointer to the encryption/decryption key. @@ -121,10 +123,11 @@ void Cy_Crypto_Core_V2_Aes_LoadDecKey(CRYPTO_Type *base, * \ref cy_en_crypto_aes_key_length_t * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Init(CRYPTO_Type *base, @@ -150,10 +153,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Init(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V2_Aes_Ecb ****************************************************************************//** * -* Performs AES operation on one Block. +* Performs an AES operation on one block. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -166,10 +169,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Init(CRYPTO_Type *base, * The pointer to a source block. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ecb(CRYPTO_Type *base, @@ -202,7 +206,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ecb(CRYPTO_Type *base, * Performs AES operation on a plain text with Cipher Block Chaining (CBC). * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -221,10 +225,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ecb(CRYPTO_Type *base, * The pointer to a source plain text. Must be 4-Byte aligned. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, @@ -236,10 +241,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState) { uint32_t size = srcSize; - cy_en_crypto_status_t myResult = CY_CRYPTO_SIZE_NOT_X16; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SIZE_NOT_X16; /* Check whether the data size is multiple of CY_CRYPTO_AES_BLOCK_SIZE */ - if (0uL == (uint32_t)(srcSize & (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1u))) + if (0UL == (uint32_t)(srcSize & (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1U))) { (CY_CRYPTO_ENCRYPT == dirMode) ? \ @@ -254,7 +259,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, { Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_AES_BLOCK_SIZE); - while (size != 0u) + while (size != 0U) { Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_V2_RB_BLOCK1, CY_CRYPTO_AES_BLOCK_SIZE); @@ -268,7 +273,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, { Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK2, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_AES_BLOCK_SIZE); - while (size != 0u) + while (size != 0U) { Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_RunAesInv(base); @@ -280,12 +285,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, } } - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } Cy_Crypto_Core_WaitForReady(base); - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -295,7 +300,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, * Performs AES operation on a plain text with the Cipher Feedback Block method (CFB). * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -314,10 +319,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cbc(CRYPTO_Type *base, * The pointer to a source plain text. Must be 4-Byte aligned. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, @@ -330,10 +336,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, { uint32_t size = srcSize; - cy_en_crypto_status_t myResult = CY_CRYPTO_SIZE_NOT_X16; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SIZE_NOT_X16; /* Check whether the data size is multiple of CY_CRYPTO_AES_BLOCK_SIZE */ - if (0uL == (uint32_t)(size & (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1u))) + if (0UL == (uint32_t)(size & (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1U))) { Cy_Crypto_Core_V2_Aes_LoadEncKey(base, aesState); @@ -345,7 +351,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, if (CY_CRYPTO_ENCRYPT == dirMode) { - while (size != 0u) + while (size != 0U) { Cy_Crypto_Core_V2_RunAes(base); Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, @@ -357,7 +363,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, } else { - while (size != 0u) + while (size != 0U) { Cy_Crypto_Core_V2_RunAes(base); Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_AES_BLOCK_SIZE); @@ -368,12 +374,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, } } - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } Cy_Crypto_Core_WaitForReady(base); - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -383,7 +389,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, * Performs AES operation on a plain text using the counter method (CTR). * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param srcSize * The size of a source plain text. @@ -405,13 +411,14 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Cfb(CRYPTO_Type *base, * The pointer to a source plain text. Must be 4-Byte aligned. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ -#define CY_CRYPTO_AES_CTR_CNT_POS (2u) +#define CY_CRYPTO_AES_CTR_CNT_POS (2U) cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ctr(CRYPTO_Type *base, uint32_t srcSize, uint32_t *srcOffset, @@ -421,28 +428,28 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ctr(CRYPTO_Type *base, uint8_t const *src, cy_stc_crypto_aes_state_t *aesState) { - uint32_t nonceCounter[4]; + uint32_t blockCounter[4]; uint64_t counter; uint32_t cnt; uint32_t i; - nonceCounter[ 0] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 3], ivPtr[ 2], ivPtr[ 1], ivPtr[0]); - nonceCounter[ 1] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 7], ivPtr[ 6], ivPtr[ 5], ivPtr[4]); - nonceCounter[ 2] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[11], ivPtr[10], ivPtr[ 9], ivPtr[8]); - nonceCounter[ 3] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[15], ivPtr[14], ivPtr[13], ivPtr[12]); + blockCounter[ 0] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 3], ivPtr[ 2], ivPtr[ 1], ivPtr[0]); + blockCounter[ 1] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 7], ivPtr[ 6], ivPtr[ 5], ivPtr[4]); + blockCounter[ 2] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[11], ivPtr[10], ivPtr[ 9], ivPtr[8]); + blockCounter[ 3] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[15], ivPtr[14], ivPtr[13], ivPtr[12]); - counter = CY_SWAP_ENDIAN64(*(uint64_t*)(nonceCounter + CY_CRYPTO_AES_CTR_CNT_POS)); + counter = CY_SWAP_ENDIAN64(*(uint64_t*)(blockCounter + CY_CRYPTO_AES_CTR_CNT_POS)); Cy_Crypto_Core_V2_Aes_LoadEncKey(base, aesState); - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t *) &nonceCounter, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD1, (const uint8_t *) &blockCounter, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_BlockMov (base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD1, CY_CRYPTO_AES_BLOCK_SIZE); /* CTR counter is placed into last 4 bytes of the Nonce block */ - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 4u, (uint8_t)((counter >> 24u) & 0xffu)); - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 3u, (uint8_t)((counter >> 16u) & 0xffu)); - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 2u, (uint8_t)((counter >> 8u) & 0xffu)); - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 1u, (uint8_t)((counter) & 0xffu)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 4U, (uint8_t)((counter >> 24U) & 0xffU)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 3U, (uint8_t)((counter >> 16U) & 0xffU)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 2U, (uint8_t)((counter >> 8U) & 0xffU)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 1U, (uint8_t)((counter) & 0xffU)); Cy_Crypto_Core_V2_RunAes(base); @@ -457,19 +464,19 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ctr(CRYPTO_Type *base, /* Increment the nonce counter */ counter++; - *(uint64_t*)(nonceCounter + CY_CRYPTO_AES_CTR_CNT_POS) = CY_SWAP_ENDIAN64(counter); + *(uint64_t*)(blockCounter + CY_CRYPTO_AES_CTR_CNT_POS) = CY_SWAP_ENDIAN64(counter); /* CTR counter is placed into last 4 bytes of the Nonce block */ - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 4u, (uint8_t)((counter >> 24u) & 0xffu)); - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 3u, (uint8_t)((counter >> 16u) & 0xffu)); - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 2u, (uint8_t)((counter >> 8u) & 0xffu)); - Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 1u, (uint8_t)((counter) & 0xffu)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 4U, (uint8_t)((counter >> 24u) & 0xffU)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 3U, (uint8_t)((counter >> 16u) & 0xffU)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 2U, (uint8_t)((counter >> 8u) & 0xffU)); + Cy_Crypto_Core_V2_RBSetByte(base, CY_CRYPTO_AES_BLOCK_SIZE - 1U, (uint8_t)((counter) & 0xffU)); Cy_Crypto_Core_V2_RBXor (base, CY_CRYPTO_AES_BLOCK_SIZE, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V2_RBStore(base, CY_CRYPTO_AES_BLOCK_SIZE, CY_CRYPTO_AES_BLOCK_SIZE); } - Cy_Crypto_Core_V2_MemCpy(base, ivPtr, nonceCounter, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V2_MemCpy(base, ivPtr, blockCounter, CY_CRYPTO_AES_BLOCK_SIZE); /* Save the reminder of the last non-complete block */ *srcOffset = (uint32_t)(srcSize % CY_CRYPTO_AES_BLOCK_SIZE); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c index 2a6f130c3a..59d73f6317 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c @@ -56,20 +56,20 @@ static void Cy_Crypto_Core_V1_Cmac_CalcSubKey(uint8_t *srcDstPtr) { int32_t i; uint32_t c; - uint32_t msb = 0uL; + uint32_t msb = 0UL; - for (i = (int32_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1); i >= 0; i--) + for (i = (int32_t)((int32_t)CY_CRYPTO_AES_BLOCK_SIZE - 1); i >= 0; i--) { c = (uint32_t)srcDstPtr[i]; - c = (c << 1u) | msb; + c = (c << 1U) | msb; srcDstPtr[i] = (uint8_t) c; - msb = (c >> 8u) & 1uL; + msb = (c >> 8U) & 1UL; } - if (0uL != msb) + if (0UL != msb) { /* Just one byte is valuable, the rest are zeros */ - srcDstPtr[(uint8_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1u)] ^= CY_CRYPTO_CMAC_RB; + srcDstPtr[(uint8_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1U)] ^= CY_CRYPTO_CMAC_RB; } } @@ -110,13 +110,13 @@ void Cy_Crypto_Core_V1_Cmac_Init(cy_stc_crypto_v1_cmac_state_t* cmacState, * Starts CMAC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState * The pointer to the structure which stores the AES context. * * \param cmacState -* the pointer to the structure which stores the CMAC context. +* The pointer to the structure which stores the CMAC context. * *******************************************************************************/ void Cy_Crypto_Core_V1_Cmac_Start(CRYPTO_Type *base, @@ -127,7 +127,7 @@ void Cy_Crypto_Core_V1_Cmac_Start(CRYPTO_Type *base, uint32_t *tempTmp = cmacState->temp; /* Calculate the K1 sub-key */ - Cy_Crypto_Core_V1_MemSet(base, (void*)tempTmp, 0u, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V1_MemSet(base, (void*)tempTmp, 0U, CY_CRYPTO_AES_BLOCK_SIZE); Cy_Crypto_Core_V1_Aes_ProcessBlock(base, aesState, CY_CRYPTO_ENCRYPT, kTmp, tempTmp); @@ -141,7 +141,7 @@ void Cy_Crypto_Core_V1_Cmac_Start(CRYPTO_Type *base, * Calculates CMAC on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState * The pointer to the structure which stores the AES context. @@ -166,7 +166,7 @@ void Cy_Crypto_Core_V1_Cmac_Update(CRYPTO_Type *base, uint32_t *tempBuff = cmacState->temp; /* Clear the argument for XOR for the first block */ - Cy_Crypto_Core_V1_MemSet(base, (void* )tempBuff, 0x00u, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_V1_MemSet(base, (void* )tempBuff, 0x00U, CY_CRYPTO_AES_BLOCK_SIZE); /* Process all blocks except last */ while (messageSize > CY_CRYPTO_AES_BLOCK_SIZE) @@ -197,7 +197,7 @@ void Cy_Crypto_Core_V1_Cmac_Update(CRYPTO_Type *base, * Completes CMAC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param aesState * the pointer to the structure which stores the AES context. @@ -226,11 +226,11 @@ void Cy_Crypto_Core_V1_Cmac_Finish(CRYPTO_Type *base, Cy_Crypto_Core_V1_Cmac_CalcSubKey((uint8_t* )kPtrTmp); /* Appended '1' bit to the end of message, followed by '0' */ - *((uint8_t* )blockBuff + blockIdxTmp) = 0x80u; + *((uint8_t* )blockBuff + blockIdxTmp) = 0x80U; /* Write zeros into the rest of the message */ copySize = CY_CRYPTO_AES_BLOCK_SIZE - 1u - blockIdxTmp; - Cy_Crypto_Core_V1_MemSet(base, ((uint8_t* )blockBuff + blockIdxTmp + 1), 0x00u, (uint16_t)copySize); + Cy_Crypto_Core_V1_MemSet(base, ((uint8_t* )blockBuff + blockIdxTmp + 1), 0x00U, (uint16_t)copySize); } Cy_Crypto_Core_V1_Aes_Xor(base, aesState, blockBuff, blockBuff, tempBuff); @@ -250,7 +250,7 @@ void Cy_Crypto_Core_V1_Cmac_Finish(CRYPTO_Type *base, * on a message to produce message authentication code using AES. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param message * The pointer to a source plain text. Must be 4-byte aligned. @@ -268,10 +268,11 @@ void Cy_Crypto_Core_V1_Cmac_Finish(CRYPTO_Type *base, * The pointer to the calculated CMAC. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Cmac(CRYPTO_Type *base, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c index e144b20dce..cd10dde848 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c @@ -66,20 +66,20 @@ static void Cy_Crypto_Core_V2_Cmac_CalcSubKey(uint8_t *srcDstPtr) { int32_t i; uint32_t c; - uint32_t msb = 0uL; + uint32_t msb = 0UL; - for (i = (int32_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1); i >= 0; i--) + for (i = (int32_t)((int32_t)CY_CRYPTO_AES_BLOCK_SIZE - 1); i >= 0; i--) { c = (uint32_t)srcDstPtr[i]; - c = (c << 1u) | msb; + c = (c << 1U) | msb; srcDstPtr[i] = (uint8_t) c; - msb = (c >> 8u) & 1uL; + msb = (c >> 8U) & 1UL; } - if (0uL != msb) + if (0UL != msb) { /* Just one byte is valuable, the rest are zeros */ - srcDstPtr[(uint8_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1u)] ^= CY_CRYPTO_CMAC_RB; + srcDstPtr[(uint8_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1U)] ^= CY_CRYPTO_CMAC_RB; } } @@ -105,7 +105,7 @@ void Cy_Crypto_Core_V2_Cmac_Init(cy_stc_crypto_v2_cmac_state_t* cmacState, uint8 * Starts CMAC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param cmacState * the pointer to the structure which stores the CMAC context. @@ -114,7 +114,7 @@ void Cy_Crypto_Core_V2_Cmac_Init(cy_stc_crypto_v2_cmac_state_t* cmacState, uint8 void Cy_Crypto_Core_V2_Cmac_Start(CRYPTO_Type *base, cy_stc_crypto_v2_cmac_state_t *cmacState) { - cmacState->block_idx = 0u; + cmacState->block_idx = 0U; /* Calculate the K1 sub-key */ Cy_Crypto_Core_V2_BlockXor(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_BLOCK0, @@ -137,7 +137,7 @@ void Cy_Crypto_Core_V2_Cmac_Start(CRYPTO_Type *base, * Calculates CMAC on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param cmacState * The pointer to the structure which stores the CMAC context. @@ -177,7 +177,7 @@ void Cy_Crypto_Core_V2_Cmac_Update(CRYPTO_Type *base, * Completes CMAC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param cmacState * The pointer to the structure which stores the CMAC context. @@ -226,7 +226,7 @@ void Cy_Crypto_Core_V2_Cmac_Finish(CRYPTO_Type *base, * on a message to produce message authentication code using AES. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param message * The pointer to a source plain text. Must be 4-byte aligned. @@ -244,10 +244,11 @@ void Cy_Crypto_Core_V2_Cmac_Finish(CRYPTO_Type *base, * The pointer to the calculated CMAC. * * \param aesState -* The pointer to the aesState structure which stores the AES context. +* The pointer to the AES state structure allocated by the user. The user +* must not modify anything in this structure. * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Cmac(CRYPTO_Type *base, @@ -259,7 +260,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Cmac(CRYPTO_Type *base, cy_stc_crypto_aes_state_t *aesState) { /* Allocate space for the structure which stores the CMAC context */ - cy_stc_crypto_v2_cmac_buffers_t cmacBuffersData; + cy_stc_crypto_v2_cmac_buffers_t cmacBuffersData = { 0 }; cy_stc_crypto_v2_cmac_buffers_t *cmacBuffers = &cmacBuffersData; uint8_t *myK = cmacBuffers->k; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c index eba47c10fb..b661fd2f4b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c @@ -41,7 +41,7 @@ * Initializes CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param polynomial * The polynomial (specified using 32 bits) used in the computing CRC. @@ -59,7 +59,7 @@ * Specifies a mask with which the LFSR32 register is XORed to produce a remainder. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_Init(CRYPTO_Type *base, @@ -85,7 +85,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_Init(CRYPTO_Type *base, * (this bit is always assumed '1'). */ REG_CRYPTO_CRC_POL_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CRC_POL_CTL_POLYNOMIAL, polynomial)); - /*Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XORed to produce a remainder. + /* Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XORed to produce a remainder. * The XOR is performed before remainder reversal. */ REG_CRYPTO_CRC_REM_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CRC_REM_CTL_REM_XOR, remXor)); @@ -99,7 +99,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_Init(CRYPTO_Type *base, * Performs CRC calculation on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param crc * The pointer to a computed CRC value. Must be 4-byte aligned. @@ -114,7 +114,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_Init(CRYPTO_Type *base, * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc(CRYPTO_Type *base, @@ -148,10 +148,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V1_Crc_CalcInit ****************************************************************************//** * -* Initializes CRC calculation. +* Initializes the CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -163,19 +163,19 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc(CRYPTO_Type *base, * The order in which data bytes are processed. 0 - MSB first; 1- LSB first. * * \param dataXor -* The byte mask for XORing data +* The byte mask for XORing data. * * \param remReverse -* A remainder reverse: 0 means the remainder is not reversed. 1 means reversed. +* A remainder reverse: 0 means the remainder is not reversed. 1 means it is reversed. * * \param remXor -* Specifies a mask with which the LFSR32 register is XORed to produce a remainder. +* Specifies the mask with which the LFSR32 register is XORed to produce a remainder. * * \param lfsrInitState * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcInit(CRYPTO_Type *base, @@ -187,30 +187,33 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcInit(CRYPTO_Type *base, uint32_t remXor, uint32_t lfsrInitState) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); - /* Specifies the bit order in which a data Byte is processed + /* Specifies the bit order in which a data byte is processed * (reversal is performed after XORing): * '0': Most significant bit (bit 1) first. * '1': Least significant bit (bit 0) first. */ REG_CRYPTO_CRC_CTL(base) = (uint32_t)( (_VAL2FLD(CRYPTO_CRC_CTL_DATA_REVERSE, dataReverse)) | (_VAL2FLD(CRYPTO_CRC_CTL_REM_REVERSE, remReverse)) ); - /* Specifies a byte mask with which each data byte is XORed. + /* Specifies the byte mask with which each data byte is XORed. * The XOR is performed before data reversal. */ REG_CRYPTO_CRC_DATA_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CRC_DATA_CTL_DATA_XOR, dataXor)); - /* CRC polynomial. The polynomial is represented WITHOUT the high order bit + /* The CRC polynomial. The polynomial is represented WITHOUT the high-order bit * (this bit is always assumed '1'). * CRC_POLYNOMIAL << (32 - CRC_BITLEN) */ - REG_CRYPTO_CRC_POL_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CRC_POL_CTL_POLYNOMIAL, polynomial << (32u - width))); + REG_CRYPTO_CRC_POL_CTL(base) = + (uint32_t)(_VAL2FLD(CRYPTO_CRC_POL_CTL_POLYNOMIAL, polynomial << (CY_CRYPTO_HW_REGS_WIDTH - width))); - /*Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XORed to produce a remainder. + /*Specifies the mask with which the CRC_LFSR_CTL.LFSR32 register is XORed to produce a remainder. * The XOR is performed before remainder reversal. */ - REG_CRYPTO_CRC_REM_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CRC_REM_CTL_REM_XOR, remXor << (32u - width))); + REG_CRYPTO_CRC_REM_CTL(base) = + (uint32_t)(_VAL2FLD(CRYPTO_CRC_REM_CTL_REM_XOR, remXor << (CY_CRYPTO_HW_REGS_WIDTH - width))); - /* A state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement CRC. */ - REG_CRYPTO_CRC_LFSR_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CRC_LFSR_CTL_LFSR32, lfsrInitState << (32u - width))); + /* The state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement the CRC. */ + REG_CRYPTO_CRC_LFSR_CTL(base) = + (uint32_t)(_VAL2FLD(CRYPTO_CRC_LFSR_CTL_LFSR32, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); return (CY_CRYPTO_SUCCESS); } @@ -219,10 +222,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcInit(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V1_Crc_CalcStart ****************************************************************************//** * -* Prepare CRC calculation by setting an initial seeds value. +* Prepares the CRC calculation by setting an initial seed value. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -231,15 +234,16 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcInit(CRYPTO_Type *base, * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t lfsrInitState) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); - /* A state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement CRC. */ - REG_CRYPTO_CRC_LFSR_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CRC_LFSR_CTL_LFSR32, lfsrInitState << (32u - width))); + /* The state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement the CRC. */ + REG_CRYPTO_CRC_LFSR_CTL(base) = + (uint32_t)(_VAL2FLD(CRYPTO_CRC_LFSR_CTL_LFSR32, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); return (CY_CRYPTO_SUCCESS); } @@ -248,10 +252,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcStart(CRYPTO_Type *base, uint32_ * Function Name: Cy_Crypto_Core_V1_Crc_CalcPartial ****************************************************************************//** * -* Performs CRC calculation of a message part. +* Performs the CRC calculation of a message part. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param data * The pointer to the message whose CRC is being computed. @@ -260,19 +264,19 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcStart(CRYPTO_Type *base, uint32_ * The size of a message in bytes. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcPartial(CRYPTO_Type *base, void const *data, uint32_t dataSize) { - /* Fill the FIFO with the instruction parameters */ + /* Fills the FIFO with the instruction parameters. */ Cy_Crypto_SetReg2Instr(base, (uint32_t)data, dataSize ); - /* Issue the CRC instruction */ + /* Issues the CRC instruction. */ Cy_Crypto_Run2ParamInstr(base, CY_CRYPTO_V1_CRC_OPC, CY_CRYPTO_RSRC0_SHIFT, CY_CRYPTO_RSRC4_SHIFT); - /* Wait until CRC instruction is complete */ + /* Waits until the CRC instruction is complete. */ while(0uL != _FLD2VAL(CRYPTO_STATUS_CRC_BUSY, REG_CRYPTO_STATUS(base))) { } @@ -284,10 +288,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcPartial(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V1_Crc_CalcFinish ****************************************************************************//** * -* Finalizes CRC calculation. +* Finalizes the CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -296,22 +300,22 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcPartial(CRYPTO_Type *base, * The pointer to a computed CRC value. Must be 4-byte aligned. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t *crc) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); uint32_t calculatedCrc; - /* Copy the result from the CRC_REM_RESULT register */ + /* Copies the result from the CRC_REM_RESULT register. */ calculatedCrc = (uint32_t)_FLD2VAL(CRYPTO_CRC_REM_RESULT_REM, REG_CRYPTO_CRC_REM_RESULT(base)); - /* Note: Calculated CRC value is MSB aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ + /* NOTE The calculated CRC value is MSB-aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ if (_FLD2VAL(CRYPTO_CRC_CTL_REM_REVERSE, REG_CRYPTO_CRC_CTL(base)) == 0u) { - calculatedCrc = calculatedCrc >> (32u - width); + calculatedCrc = calculatedCrc >> (CY_CRYPTO_HW_REGS_WIDTH - width); } *crc = calculatedCrc; @@ -323,10 +327,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcFinish(CRYPTO_Type *base, uint32 * Function Name: Cy_Crypto_Core_V1_Crc_Calc ****************************************************************************//** * -* Performs CRC calculation on a message. +* Performs the CRC calculation on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -341,7 +345,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcFinish(CRYPTO_Type *base, uint32 * The size of a message in bytes. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_Calc(CRYPTO_Type *base, @@ -350,28 +354,28 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_Calc(CRYPTO_Type *base, void const *data, uint32_t dataSize) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); uint32_t calculatedCrc; - /* Fill the FIFO with the instruction parameters */ + /* Fills the FIFO with the instruction parameters. */ Cy_Crypto_SetReg2Instr(base, (uint32_t)data, dataSize ); - /* Issue the CRC instruction */ + /* Issues the CRC instruction. */ Cy_Crypto_Run2ParamInstr(base, CY_CRYPTO_V1_CRC_OPC, CY_CRYPTO_RSRC0_SHIFT, CY_CRYPTO_RSRC4_SHIFT); - /* Wait until CRC instruction is complete */ + /* Waits until the CRC instruction is complete. */ while(0uL != _FLD2VAL(CRYPTO_STATUS_CRC_BUSY, REG_CRYPTO_STATUS(base))) { } - /* Copy the result from the CRC_REM_RESULT register */ + /* Copies the result from the CRC_REM_RESULT register. */ calculatedCrc = (uint32_t)_FLD2VAL(CRYPTO_CRC_REM_RESULT_REM, REG_CRYPTO_CRC_REM_RESULT(base)); - /* Note: Calculated CRC value is MSB aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ + /* NOTE The calculated CRC value is MSB-aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ if (_FLD2VAL(CRYPTO_CRC_CTL_REM_REVERSE, REG_CRYPTO_CRC_CTL(base)) == 0u) { - calculatedCrc = calculatedCrc >> (32u - width); + calculatedCrc = calculatedCrc >> (CY_CRYPTO_HW_REGS_WIDTH - width); } *crc = calculatedCrc; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c index 5c5878384d..a27ce9b677 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c @@ -42,7 +42,7 @@ * Initializes CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param polynomial * The polynomial (specified using 32 bits) used in the computing CRC. @@ -60,7 +60,7 @@ * Specifies a mask with which the LFSR32 register is XORed to produce a remainder. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_Init(CRYPTO_Type *base, @@ -100,7 +100,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_Init(CRYPTO_Type *base, * Performs CRC calculation on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param crc * The pointer to a computed CRC value. Must be 4-byte aligned. @@ -115,7 +115,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_Init(CRYPTO_Type *base, * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc(CRYPTO_Type *base, @@ -146,10 +146,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V2_Crc_CalcInit ****************************************************************************//** * -* Initializes CRC calculation. +* Initializes the CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -161,19 +161,19 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc(CRYPTO_Type *base, * The order in which data bytes are processed. 0 - MSB first; 1- LSB first. * * \param dataXor -* The byte mask for XORing data +* The byte mask for XORing data. * * \param remReverse -* A remainder reverse: 0 means the remainder is not reversed. 1 means reversed. +* The remainder reverse: 0 means the remainder is not reversed; 1 means it is reversed. * * \param remXor -* Specifies a mask with which the LFSR32 register is XORed to produce a remainder. +* Specifies the mask with which the LFSR32 register is XORed to produce a remainder. * * \param lfsrInitState * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcInit(CRYPTO_Type *base, @@ -185,29 +185,32 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcInit(CRYPTO_Type *base, uint32_t remXor, uint32_t lfsrInitState) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); - /* Specifies the bit order in which a data Byte is processed + /* Specifies the bit order in which a data byte is processed * (reversal is performed after XORing): * '0': Most significant bit (bit 1) first. * '1': Least significant bit (bit 0) first. */ REG_CRYPTO_CRC_CTL(base) = (uint32_t)( (_VAL2FLD(CRYPTO_V2_CRC_CTL_DATA_REVERSE, dataReverse)) | (_VAL2FLD(CRYPTO_V2_CRC_CTL_REM_REVERSE, remReverse)) ); - /* Specifies a byte mask with which each data byte is XORed. + /* Specifies the byte mask with which each data byte is XORed. * The XOR is performed before data reversal. */ REG_CRYPTO_CRC_DATA_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_V2_CRC_DATA_CTL_DATA_XOR, dataXor)); - /* CRC polynomial. The polynomial is represented WITHOUT the high order bit + /* The CRC polynomial. The polynomial is represented WITHOUT the high-order bit * (this bit is always assumed '1'). */ - REG_CRYPTO_CRC_POL_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL, polynomial << (32u - width))); + REG_CRYPTO_CRC_POL_CTL(base) = + (uint32_t)(_VAL2FLD(CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL, polynomial << (CY_CRYPTO_HW_REGS_WIDTH - width))); - /*Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XORed to produce a remainder. + /*Specifies the mask with which the CRC_LFSR_CTL.LFSR32 register is XORed to produce a remainder. * The XOR is performed before remainder reversal. */ - REG_CRYPTO_CRC_REM_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_V2_CRC_REM_CTL_REM_XOR, remXor << (32u - width))); + REG_CRYPTO_CRC_REM_CTL(base) = + (uint32_t)(_VAL2FLD(CRYPTO_V2_CRC_REM_CTL_REM_XOR, remXor << (CY_CRYPTO_HW_REGS_WIDTH - width))); - /* A state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement CRC. */ - REG_CRYPTO_RESULT(base) = (uint32_t)(_VAL2FLD(CRYPTO_V2_RESULT_DATA, lfsrInitState << (32u - width))); + /* The state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement the CRC. */ + REG_CRYPTO_RESULT(base) = + (uint32_t)(_VAL2FLD(CRYPTO_V2_RESULT_DATA, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); return (CY_CRYPTO_SUCCESS); } @@ -216,10 +219,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcInit(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V2_Crc_CalcStart ****************************************************************************//** * -* Prepares CRC calculation by setting an initial seeds value. +* Prepares the CRC calculation by setting an initial seed value. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -228,15 +231,15 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcInit(CRYPTO_Type *base, * The initial state of the LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t lfsrInitState) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); - /* A state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement CRC. */ - REG_CRYPTO_RESULT(base) = (uint32_t)(_VAL2FLD(CRYPTO_V2_RESULT_DATA, lfsrInitState << (32u - width))); + /* The state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement the CRC. */ + REG_CRYPTO_RESULT(base) = (uint32_t)(_VAL2FLD(CRYPTO_V2_RESULT_DATA, lfsrInitState << (CY_CRYPTO_HW_REGS_WIDTH - width))); return (CY_CRYPTO_SUCCESS); } @@ -245,10 +248,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcStart(CRYPTO_Type *base, uint32_ * Function Name: Cy_Crypto_Core_V2_Crc_CalcPartial ****************************************************************************//** * -* Performs CRC calculation of a message part. +* Performs the CRC calculation of a message part. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param data * The pointer to the message whose CRC is being computed. @@ -257,19 +260,19 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcStart(CRYPTO_Type *base, uint32_ * The size of a message in bytes. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcPartial(CRYPTO_Type *base, void const *data, uint32_t dataSize) { - /* Fill the FIFO with the instruction parameters */ + /* Fills the FIFO with the instruction parameters. */ Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, (uint8_t const *)data, dataSize); - /* Issue the CRC instruction */ + /* Issues the CRC instruction. */ Cy_Crypto_Core_V2_Run(base, CY_CRYPTO_V2_CRC_OPC); - /* Wait until CRC instruction is complete */ + /* Waits until the CRC instruction is complete. */ Cy_Crypto_Core_V2_Sync(base); return (CY_CRYPTO_SUCCESS); @@ -279,10 +282,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcPartial(CRYPTO_Type *base, * Function Name: Cy_Crypto_Core_V2_Crc_CalcFinish ****************************************************************************//** * -* Finalizes CRC calculation. +* Finalizes the CRC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -291,22 +294,22 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcPartial(CRYPTO_Type *base, * The pointer to a computed CRC value. Must be 4-byte aligned. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t *crc) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); uint32_t calculatedCrc; - /* Copy the result from the CRC_REM_RESULT register */ + /* Copies the result from the CRC_REM_RESULT register. */ calculatedCrc = (uint32_t)_FLD2VAL(CRYPTO_V2_CRC_REM_RESULT_REM, REG_CRYPTO_CRC_REM_RESULT(base)); - /* Note: Calculated CRC value is MSB aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ - if (_FLD2VAL(CRYPTO_V2_CRC_CTL_REM_REVERSE, REG_CRYPTO_CRC_CTL(base)) == 0u) + /* NOTE The calculated CRC value is MSB-aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ + if (_FLD2VAL(CRYPTO_V2_CRC_CTL_REM_REVERSE, REG_CRYPTO_CRC_CTL(base)) == 0U) { - calculatedCrc = calculatedCrc >> (32u - width); + calculatedCrc = calculatedCrc >> (CY_CRYPTO_HW_REGS_WIDTH - width); } *crc = calculatedCrc; @@ -318,10 +321,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcFinish(CRYPTO_Type *base, uint32 * Function Name: Cy_Crypto_Core_V2_Crc_Calc ****************************************************************************//** * -* Performs CRC calculation on a message. +* Performs the CRC calculation on a message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param width * The CRC width in bits. @@ -336,7 +339,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcFinish(CRYPTO_Type *base, uint32 * The size of a message in bytes. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_Calc(CRYPTO_Type *base, @@ -345,26 +348,26 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_Calc(CRYPTO_Type *base, void const *data, uint32_t dataSize) { - CY_ASSERT_L1((width >= 1) && (width <=32u)); + CY_ASSERT_L1((width >= 1U) && (width <= CY_CRYPTO_HW_REGS_WIDTH)); uint32_t calculatedCrc; - /* Fill the FIFO with the instruction parameters */ + /* Fills the FIFO with the instruction parameters. */ Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, (uint8_t const *)data, dataSize); - /* Issue the CRC instruction */ + /* Issues the CRC instruction. */ Cy_Crypto_Core_V2_Run(base, CY_CRYPTO_V2_CRC_OPC); - /* Wait until CRC instruction is complete */ + /* Waits until the CRC instruction is complete. */ Cy_Crypto_Core_V2_Sync(base); - /* Copy the result from the CRC_REM_RESULT register */ + /* Copies the result from the CRC_REM_RESULT register. */ calculatedCrc = (uint32_t)_FLD2VAL(CRYPTO_V2_CRC_REM_RESULT_REM, REG_CRYPTO_CRC_REM_RESULT(base)); - /* Note: Calculated CRC value is MSB aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ - if (_FLD2VAL(CRYPTO_V2_CRC_CTL_REM_REVERSE, REG_CRYPTO_CRC_CTL(base)) == 0u) + /* NOTE The calculated CRC value is MSB-aligned and should be shifted WHEN CRC_DATA_REVERSE is zero. */ + if (_FLD2VAL(CRYPTO_V2_CRC_CTL_REM_REVERSE, REG_CRYPTO_CRC_CTL(base)) == 0U) { - calculatedCrc = calculatedCrc >> (32u - width); + calculatedCrc = calculatedCrc >> (CY_CRYPTO_HW_REGS_WIDTH - width); } *crc = calculatedCrc; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c index 5fe50a3f38..73c53e78c1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c @@ -91,7 +91,7 @@ static void Cy_Crypto_Core_V1_Des_ProcessBlock(CRYPTO_Type *base, * srcBlock could overlap dstBlock. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * One of CRYPTO_ENCRYPT or CRYPTO_DECRYPT. @@ -145,7 +145,7 @@ static void Cy_Crypto_Core_V1_Des_ProcessBlock(CRYPTO_Type *base, * This function is independent from the previous Crypto state. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -161,7 +161,7 @@ static void Cy_Crypto_Core_V1_Des_ProcessBlock(CRYPTO_Type *base, * The pointer to a source block. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Des(CRYPTO_Type *base, @@ -176,12 +176,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Des(CRYPTO_Type *base, cy_stc_crypto_des_buffers_t *desBuffers = (cy_stc_crypto_des_buffers_t *)REG_CRYPTO_MEM_BUFF(base); /* Check weak keys */ - for (i = 0u; i < CY_CRYPTO_DES_WEAK_KEY_COUNT; i++) + for (i = 0U; (i < CY_CRYPTO_DES_WEAK_KEY_COUNT) && (CY_CRYPTO_SUCCESS == status); i++) { - if (memcmp(key, (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) + if (Cy_Crypto_Core_V1_MemCmp(base, key, (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0U) { status = CY_CRYPTO_DES_WEAK_KEY; - break; } } @@ -205,7 +204,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Des(CRYPTO_Type *base, * This function is independent from the previous Crypto state. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -221,7 +220,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Des(CRYPTO_Type *base, * The pointer to a source data block. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Tdes(CRYPTO_Type *base, @@ -236,30 +235,18 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Tdes(CRYPTO_Type *base, cy_stc_crypto_des_buffers_t *desBuffers = (cy_stc_crypto_des_buffers_t *)REG_CRYPTO_MEM_BUFF(base); /* Check weak keys */ - for (i = 0u; i < CY_CRYPTO_DES_WEAK_KEY_COUNT; i++) + for (i = 0U; (i < CY_CRYPTO_DES_WEAK_KEY_COUNT) && (CY_CRYPTO_SUCCESS == status); i++) { - if (memcmp(key, (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) + for (uint32_t keynum=0U; (keynum < (CY_CRYPTO_TDES_KEY_SIZE / CY_CRYPTO_DES_KEY_SIZE)) && (CY_CRYPTO_SUCCESS == status); keynum++) { - status = CY_CRYPTO_DES_WEAK_KEY; - break; - } - - if (memcmp(&(key[CY_CRYPTO_DES_KEY_BYTE_LENGTH]), - (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) - { - status = CY_CRYPTO_DES_WEAK_KEY; - break; - } - - if (memcmp(&(key[2u * CY_CRYPTO_DES_KEY_BYTE_LENGTH]), - (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) - { - status = CY_CRYPTO_DES_WEAK_KEY; - break; + if (Cy_Crypto_Core_V1_MemCmp(base, &(key[keynum * CY_CRYPTO_DES_KEY_BYTE_LENGTH]), (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0U) + { + status = CY_CRYPTO_DES_WEAK_KEY; + } } } - Cy_Crypto_Core_V1_MemCpy(base, desBuffers->key, key, CY_CRYPTO_DES_KEY_BYTE_LENGTH * 3u); + Cy_Crypto_Core_V1_MemCpy(base, desBuffers->key, key, CY_CRYPTO_DES_KEY_BYTE_LENGTH * 3U); Cy_Crypto_Core_V1_MemCpy(base, desBuffers->block0, src, CY_CRYPTO_DES_KEY_BYTE_LENGTH); Cy_Crypto_Core_V1_Des_ProcessBlock(base, CY_CRYPTO_DES_MODE_TRIPLE, dirMode, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c index c0152db4e1..e1ea2b72d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c @@ -36,8 +36,8 @@ #if (CPUSS_CRYPTO_DES == 1) -#define CY_CRYPTO_DES_WEAK_KEY_COUNT (16u) -#define CY_CRYPTO_DES_KEY_BYTE_LENGTH (8u) +#define CY_CRYPTO_DES_WEAK_KEY_COUNT (16U) +#define CY_CRYPTO_DES_KEY_BYTE_LENGTH (8U) typedef enum { @@ -78,7 +78,7 @@ static uint8_t const cy_desWeakKeys[CY_CRYPTO_DES_WEAK_KEY_COUNT][CY_CRYPTO_DES_ * This function is independent from the previous Crypto state. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -94,7 +94,7 @@ static uint8_t const cy_desWeakKeys[CY_CRYPTO_DES_WEAK_KEY_COUNT][CY_CRYPTO_DES_ * The pointer to a source data block. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Des(CRYPTO_Type *base, @@ -107,9 +107,9 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Des(CRYPTO_Type *base, cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; /* Check weak keys */ - for (i = 0u; i < CY_CRYPTO_DES_WEAK_KEY_COUNT; i++) + for (i = 0U; i < CY_CRYPTO_DES_WEAK_KEY_COUNT; i++) { - if (Cy_Crypto_Core_V2_MemCmp(base, key, (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0u) + if (Cy_Crypto_Core_V2_MemCmp(base, key, (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0U) { status = CY_CRYPTO_DES_WEAK_KEY; break; @@ -139,7 +139,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Des(CRYPTO_Type *base, * This function is independent from the previous Crypto state. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dirMode * Can be \ref CY_CRYPTO_ENCRYPT or \ref CY_CRYPTO_DECRYPT @@ -155,7 +155,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Des(CRYPTO_Type *base, * The pointer to a source data block. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Tdes(CRYPTO_Type *base, @@ -168,36 +168,24 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Tdes(CRYPTO_Type *base, cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; /* Check weak keys */ - for (i = 0u; i < CY_CRYPTO_DES_WEAK_KEY_COUNT; i++) + for (i = 0U; (i < CY_CRYPTO_DES_WEAK_KEY_COUNT) && (CY_CRYPTO_SUCCESS == status); i++) { - if (Cy_Crypto_Core_V2_MemCmp(base, key, (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0u) + for (uint32_t keynum=0U; (keynum < (CY_CRYPTO_TDES_KEY_SIZE / CY_CRYPTO_DES_KEY_SIZE)) && (CY_CRYPTO_SUCCESS == status); keynum++) { - status = CY_CRYPTO_DES_WEAK_KEY; - break; - } - - if (Cy_Crypto_Core_V2_MemCmp(base, &(key[CY_CRYPTO_DES_KEY_BYTE_LENGTH]), - (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0u) - { - status = CY_CRYPTO_DES_WEAK_KEY; - break; - } - - if (Cy_Crypto_Core_V2_MemCmp(base, &(key[2u * CY_CRYPTO_DES_KEY_BYTE_LENGTH]), - (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0u) - { - status = CY_CRYPTO_DES_WEAK_KEY; - break; + if (Cy_Crypto_Core_V2_MemCmp(base, &(key[keynum * CY_CRYPTO_DES_KEY_BYTE_LENGTH]), (uint8_t const *)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0U) + { + status = CY_CRYPTO_DES_WEAK_KEY; + } } } /* Load keys */ - Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, key, CY_CRYPTO_DES_KEY_BYTE_LENGTH * 3u); - Cy_Crypto_Core_V2_BlockMov (base, CY_CRYPTO_V2_RB_KEY0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_DES_KEY_BYTE_LENGTH * 2u); + Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, key, CY_CRYPTO_DES_KEY_BYTE_LENGTH * 3U); + Cy_Crypto_Core_V2_BlockMov (base, CY_CRYPTO_V2_RB_KEY0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_DES_KEY_BYTE_LENGTH * 2U); Cy_Crypto_Core_V2_BlockMov (base, CY_CRYPTO_V2_RB_KEY1, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_DES_KEY_BYTE_LENGTH); Cy_Crypto_Core_V2_FFContinue(base, CY_CRYPTO_V2_RB_FF_LOAD0, src, CY_CRYPTO_DES_KEY_BYTE_LENGTH); - Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, dst, CY_CRYPTO_DES_KEY_BYTE_LENGTH); + Cy_Crypto_Core_V2_FFStart (base, CY_CRYPTO_V2_RB_FF_STORE, dst, CY_CRYPTO_DES_KEY_BYTE_LENGTH); Cy_Crypto_Core_V2_BlockMov(base, CY_CRYPTO_V2_RB_BLOCK0, CY_CRYPTO_V2_RB_FF_LOAD0, CY_CRYPTO_DES_KEY_BYTE_LENGTH); Cy_Crypto_Core_V2_Run(base, (uint32_t)((dirMode == CY_CRYPTO_ENCRYPT) ? (CY_CRYPTO_V2_TDES_OPC) : (CY_CRYPTO_V2_TDES_INV_OPC))); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c index 2b1f0122f6..f0c41ba4eb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c @@ -27,445 +27,444 @@ #include "cy_crypto_core_ecc.h" #include "cy_syslib.h" -const cy_stc_crypto_ecc_dp_type eccDomainParams[]; - /******************************************************************************* * Function Name: Cy_Crypto_Core_ECC_GetCurveParams ****************************************************************************//** * -* . +* Get curve domain parameters if this curve is supported. * * \param curveID * See \ref cy_en_crypto_ecc_curve_id_t. * -* \return status code. See \ref cy_stc_crypto_ecc_dp_type. +* \return +* Pointer to curve domain parameters. See \ref cy_stc_crypto_ecc_dp_type. * *******************************************************************************/ cy_stc_crypto_ecc_dp_type *Cy_Crypto_Core_ECC_GetCurveParams(cy_en_crypto_ecc_curve_id_t curveId) { - cy_stc_crypto_ecc_dp_type *result = NULL; + /* P192 CURVE PARAMETERS */ + CY_ALIGN(4) static const uint8_t eccP192Polynomial[CY_CRYPTO_ECC_P192_BYTE_SIZE] = + { + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xfeu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + }; + + CY_ALIGN(4) static const uint8_t eccP192PolyBarrett[CY_CRYPTO_ECC_P192_BYTE_SIZE + 1u] = + { /* pre-calculated */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u + }; + CY_ALIGN(4) static const uint8_t eccP192Order[CY_CRYPTO_ECC_P192_BYTE_SIZE] = + { + 0x31u, 0x28u, 0xD2u, 0xB4u, 0xB1u, 0xC9u, 0x6Bu, 0x14u, + 0x36u, 0xF8u, 0xDEu, 0x99u, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu + }; + + /* barrett_o: "1000000000000000000000000662107c9eb94364e4b2dd7cf" */ + CY_ALIGN(4) static const uint8_t eccP192OrderBarrett[CY_CRYPTO_ECC_P192_BYTE_SIZE + 1u] = + { /* pre-calculated */ + 0xcfu, 0xd7u, 0x2du, 0x4bu, 0x4eu, 0x36u, 0x94u, 0xebu, + 0xc9u, 0x07u, 0x21u, 0x66u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u + }; + + /* base point x: "188DA80EB03090F67CBF20EB43A18800F4FF0AFD82FF1012" */ + CY_ALIGN(4) static const uint8_t eccP192BasePointX[CY_CRYPTO_ECC_P192_BYTE_SIZE] = + { + 0x12u, 0x10u, 0xffu, 0x82u, 0xfdu, 0x0au, 0xffu, 0xf4u, + 0x00u, 0x88u, 0xa1u, 0x43u, 0xebu, 0x20u, 0xbfu, 0x7cu, + 0xf6u, 0x90u, 0x30u, 0xb0u, 0x0eu, 0xa8u, 0x8du, 0x18u + }; + + /* base point y: "07192B95FFC8DA78631011ED6B24CDD573F977A11E794811" */ + CY_ALIGN(4) static const uint8_t eccP192BasePointY[CY_CRYPTO_ECC_P192_BYTE_SIZE] = + { + 0x11u, 0x48u, 0x79u, 0x1eu, 0xa1u, 0x77u, 0xf9u, 0x73u, + 0xd5u, 0xcdu, 0x24u, 0x6bu, 0xedu, 0x11u, 0x10u, 0x63u, + 0x78u, 0xdau, 0xc8u, 0xffu, 0x95u, 0x2bu, 0x19u, 0x07u + }; + + /* P224 CURVE PARAMETERS */ + CY_ALIGN(4) static const uint8_t eccP224Polynomial[CY_CRYPTO_ECC_P224_BYTE_SIZE] = + { + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu + }; + + CY_ALIGN(4) static const uint8_t eccP224PolyBarrett[CY_CRYPTO_ECC_P224_BYTE_SIZE + 1u] = + { /* pre-calculated */ + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u + }; + + CY_ALIGN(4) static const uint8_t eccP224Order[CY_CRYPTO_ECC_P224_BYTE_SIZE] = + { + 0x3Du, 0x2Au, 0x5Cu, 0x5Cu, 0x45u, 0x29u, 0xDDu, 0x13u, + 0x3Eu, 0xF0u, 0xB8u, 0xE0u, 0xA2u, 0x16u, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu + }; + /* barrett_o: "10000000000000000000000000000e95d1f470fc1ec22d6baa3a3d5c3" */ + CY_ALIGN(4) static const uint8_t eccP224OrderBarrett[CY_CRYPTO_ECC_P224_BYTE_SIZE + 1u] = + { /* pre-calculated */ + 0xc3u, 0xd5u, 0xa3u, 0xa3u, 0xbau, 0xd6u, 0x22u, 0xecu, + 0xc1u, 0x0fu, 0x47u, 0x1fu, 0x5du, 0xe9u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u + }; + + /* Gx - base point x: "B70E0CBD6BB4BF7F321390B94A03C1D356C21122343280D6115C1D21" */ + CY_ALIGN(4) static const uint8_t eccP224BasePointX[CY_CRYPTO_ECC_P224_BYTE_SIZE] = + { + 0x21u, 0x1du, 0x5cu, 0x11u, 0xd6u, 0x80u, 0x32u, 0x34u, + 0x22u, 0x11u, 0xc2u, 0x56u, 0xd3u, 0xc1u, 0x03u, 0x4au, + 0xb9u, 0x90u, 0x13u, 0x32u, 0x7fu, 0xbfu, 0xb4u, 0x6bu, + 0xbdu, 0x0cu, 0x0eu, 0xb7u + }; + + /* Gy - base point y: "BD376388B5F723FB4C22DFE6CD4375A05A07476444D5819985007E34" */ + CY_ALIGN(4) static const uint8_t eccP224BasePointY[CY_CRYPTO_ECC_P224_BYTE_SIZE] = + { + 0x34u, 0x7eu, 0x00u, 0x85u, 0x99u, 0x81u, 0xd5u, 0x44u, + 0x64u, 0x47u, 0x07u, 0x5au, 0xa0u, 0x75u, 0x43u, 0xcdu, + 0xe6u, 0xdfu, 0x22u, 0x4cu, 0xfbu, 0x23u, 0xf7u, 0xb5u, + 0x88u, 0x63u, 0x37u, 0xbdu + }; + + + /* P256 CURVE PARAMETERS */ + /* prime: "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF" */ + CY_ALIGN(4) static const uint8_t eccP256Polynomial[CY_CRYPTO_ECC_P256_BYTE_SIZE] = + { + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu + }; + + /* barrett_p: "100000000fffffffffffffffefffffffefffffffeffffffff0000000000000003" */ + CY_ALIGN(4) static const uint8_t eccP256PolyBarrett[CY_CRYPTO_ECC_P256_BYTE_SIZE + 1u] = + { /* pre-calculated! */ + 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xffu, 0xffu, 0xffu, 0xffu, 0xfeu, 0xffu, 0xffu, 0xffu, + 0xfeu, 0xffu, 0xffu, 0xffu, 0xfeu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u + }; + + /* order: "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551" */ + CY_ALIGN(4) static const uint8_t eccP256Order[CY_CRYPTO_ECC_P256_BYTE_SIZE] = + { + 0x51u, 0x25u, 0x63u, 0xfcu, 0xc2u, 0xcau, 0xb9u, 0xf3u, + 0x84u, 0x9eu, 0x17u, 0xa7u, 0xadu, 0xfau, 0xe6u, 0xbcu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu + }; + + /* barrett_o: 100000000fffffffffffffffeffffffff43190552df1a6c21012ffd85eedf9bfe" */ + CY_ALIGN(4) static const uint8_t eccP256OrderBarrett[CY_CRYPTO_ECC_P256_BYTE_SIZE + 1u] = + { /* pre-calculated */ + 0xfeu, 0x9bu, 0xdfu, 0xeeu, 0x85u, 0xfdu, 0x2fu, 0x01u, + 0x21u, 0x6cu, 0x1au, 0xdfu, 0x52u, 0x05u, 0x19u, 0x43u, + 0xffu, 0xffu, 0xffu, 0xffu, 0xfeu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u + }; + + /* base point x: "6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296" */ + CY_ALIGN(4) static const uint8_t eccP256BasePointX[CY_CRYPTO_ECC_P256_BYTE_SIZE] = + { + 0x96u, 0xc2u, 0x98u, 0xd8u, 0x45u, 0x39u, 0xa1u, 0xf4u, + 0xa0u, 0x33u, 0xebu, 0x2du, 0x81u, 0x7du, 0x03u, 0x77u, + 0xf2u, 0x40u, 0xa4u, 0x63u, 0xe5u, 0xe6u, 0xbcu, 0xf8u, + 0x47u, 0x42u, 0x2cu, 0xe1u, 0xf2u, 0xd1u, 0x17u, 0x6bu + }; + + /* base point y: "4FE342E2FE1A7F9B8EE7EB4A7C0F9E162BCE33576B315ECECBB6406837BF51F5" */ + CY_ALIGN(4) static const uint8_t eccP256BasePointY[CY_CRYPTO_ECC_P256_BYTE_SIZE] = + { + 0xf5u, 0x51u, 0xbfu, 0x37u, 0x68u, 0x40u, 0xb6u, 0xcbu, + 0xceu, 0x5eu, 0x31u, 0x6bu, 0x57u, 0x33u, 0xceu, 0x2bu, + 0x16u, 0x9eu, 0x0fu, 0x7cu, 0x4au, 0xebu, 0xe7u, 0x8eu, + 0x9bu, 0x7fu, 0x1au, 0xfeu, 0xe2u, 0x42u, 0xe3u, 0x4fu, + }; + + /* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF" */ + CY_ALIGN(4) static const uint8_t eccP384Polynomial[CY_CRYPTO_ECC_P384_BYTE_SIZE] = + { + 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, + 0xfeu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu + }; + + /* barrett_p: "1000000000000000000000000000000000000000000000000000000000000000100000000ffffffffffffffff00000001" */ + CY_ALIGN(4) static const uint8_t eccP384PolyBarrett[CY_CRYPTO_ECC_P384_BYTE_SIZE + 1u] = + { /* pre-calculated */ + 0x01u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u + }; + + /* order: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973" */ + CY_ALIGN(4) static const uint8_t eccP384Order[CY_CRYPTO_ECC_P384_BYTE_SIZE] = + { + 0x73u, 0x29u, 0xC5u, 0xCCu, 0x6Au, 0x19u, 0xECu, 0xECu, + 0x7Au, 0xA7u, 0xB0u, 0x48u, 0xB2u, 0x0Du, 0x1Au, 0x58u, + 0xDFu, 0x2Du, 0x37u, 0xF4u, 0x81u, 0x4Du, 0x63u, 0xC7u, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu + }; + + /* barrett_o: "1000000000000000000000000000000000000000000000000389cb27e0bc8d220a7e5f24db74f58851313e695333ad68d" */ + CY_ALIGN(4) static const uint8_t eccP384OrderBarrett[CY_CRYPTO_ECC_P384_BYTE_SIZE + 1u] = + { /* pre-calculated */ + 0x8du, 0xd6u, 0x3au, 0x33u, 0x95u, 0xe6u, 0x13u, 0x13u, + 0x85u, 0x58u, 0x4fu, 0xb7u, 0x4du, 0xf2u, 0xe5u, 0xa7u, + 0x20u, 0xd2u, 0xc8u, 0x0bu, 0x7eu, 0xb2u, 0x9cu, 0x38u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u + }; + + /* base point x: "AA87CA22BE8B05378EB1C71EF320AD746E1D3B628BA79B9859F741E082542A385502F25DBF55296C3A545E3872760AB7" */ + CY_ALIGN(4) static const uint8_t eccP384BasePointX[CY_CRYPTO_ECC_P384_BYTE_SIZE] = + { + 0xb7u, 0x0au, 0x76u, 0x72u, 0x38u, 0x5eu, 0x54u, 0x3au, + 0x6cu, 0x29u, 0x55u, 0xbfu, 0x5du, 0xf2u, 0x02u, 0x55u, + 0x38u, 0x2au, 0x54u, 0x82u, 0xe0u, 0x41u, 0xf7u, 0x59u, + 0x98u, 0x9bu, 0xa7u, 0x8bu, 0x62u, 0x3bu, 0x1du, 0x6eu, + 0x74u, 0xadu, 0x20u, 0xf3u, 0x1eu, 0xc7u, 0xb1u, 0x8eu, + 0x37u, 0x05u, 0x8bu, 0xbeu, 0x22u, 0xcau, 0x87u, 0xaau + }; + + /* base point y: "3617DE4A96262C6F5D9E98BF9292DC29F8F41DBD289A147CE9DA3113B5F0B8C00A60B1CE1D7E819D7A431D7C90EA0E5F" */ + CY_ALIGN(4) static const uint8_t eccP384BasePointY[CY_CRYPTO_ECC_P384_BYTE_SIZE] = + { + 0x5fu, 0x0eu, 0xeau, 0x90u, 0x7cu, 0x1du, 0x43u, 0x7au, + 0x9du, 0x81u, 0x7eu, 0x1du, 0xceu, 0xb1u, 0x60u, 0x0au, + 0xc0u, 0xb8u, 0xf0u, 0xb5u, 0x13u, 0x31u, 0xdau, 0xe9u, + 0x7cu, 0x14u, 0x9au, 0x28u, 0xbdu, 0x1du, 0xf4u, 0xf8u, + 0x29u, 0xdcu, 0x92u, 0x92u, 0xbfu, 0x98u, 0x9eu, 0x5du, + 0x6fu, 0x2cu, 0x26u, 0x96u, 0x4au, 0xdeu, 0x17u, 0x36u + }; + + CY_ALIGN(4) static const uint8_t eccP521Polynomial[CY_CRYPTO_ECC_P521_BYTE_SIZE] = + { + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0x01u + }; + + CY_ALIGN(4) static const uint8_t eccP521PolyBarrett[CY_CRYPTO_ECC_P521_BYTE_SIZE] = + { /* pre-calculated */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x02u + }; + + CY_ALIGN(4) static const uint8_t eccP521Order[CY_CRYPTO_ECC_P521_BYTE_SIZE] = + { + 0x09u, 0x64u, 0x38u, 0x91u, 0x1Eu, 0xB7u, 0x6Fu, 0xBBu, + 0xAEu, 0x47u, 0x9Cu, 0x89u, 0xB8u, 0xC9u, 0xB5u, 0x3Bu, + 0xD0u, 0xA5u, 0x09u, 0xF7u, 0x48u, 0x01u, 0xCCu, 0x7Fu, + 0x6Bu, 0x96u, 0x2Fu, 0xBFu, 0x83u, 0x87u, 0x86u, 0x51u, + 0xFAu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0x01u + }; + + /* barrett_o: "2000000000000000000000000000000000000000000000000000000000000000005ae79787c40d069948033feb708f65a2fc44a36477663b851449048e16ec79bf7" */ + CY_ALIGN(4) static const uint8_t eccP521OrderBarrett[CY_CRYPTO_ECC_P521_BYTE_SIZE] = + { /* pre-calculated */ + 0xf7u, 0x9bu, 0xc7u, 0x6eu, 0xe1u, 0x48u, 0x90u, 0x44u, + 0x51u, 0xb8u, 0x63u, 0x76u, 0x47u, 0x36u, 0x4au, 0xc4u, + 0x2fu, 0x5au, 0xf6u, 0x08u, 0xb7u, 0xfeu, 0x33u, 0x80u, + 0x94u, 0x69u, 0xd0u, 0x40u, 0x7cu, 0x78u, 0x79u, 0xaeu, + 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x02u + }; + + /* base point x: "00C6858E06B70404E9CD9E3ECB662395B4429C648139053FB521F828AF606B4D3DBAA14B5E77EFE75928FE1DC127A2FFA8DE3348B3C1856A429BF97E7E31C2E5BD66" */ + CY_ALIGN(4) static const uint8_t eccP521BasePointX[CY_CRYPTO_ECC_P521_BYTE_SIZE] = + { + 0x66u, 0xbdu, 0xe5u, 0xc2u, 0x31u, 0x7eu, 0x7eu, 0xf9u, + 0x9bu, 0x42u, 0x6au, 0x85u, 0xc1u, 0xb3u, 0x48u, 0x33u, + 0xdeu, 0xa8u, 0xffu, 0xa2u, 0x27u, 0xc1u, 0x1du, 0xfeu, + 0x28u, 0x59u, 0xe7u, 0xefu, 0x77u, 0x5eu, 0x4bu, 0xa1u, + 0xbau, 0x3du, 0x4du, 0x6bu, 0x60u, 0xafu, 0x28u, 0xf8u, + 0x21u, 0xb5u, 0x3fu, 0x05u, 0x39u, 0x81u, 0x64u, 0x9cu, + 0x42u, 0xb4u, 0x95u, 0x23u, 0x66u, 0xcbu, 0x3eu, 0x9eu, + 0xcdu, 0xe9u, 0x04u, 0x04u, 0xb7u, 0x06u, 0x8eu, 0x85u, + 0xc6u, 0x00u + }; + + /* base point y: "011839296A789A3BC0045C8A5FB42C7D1BD998F54449579B446817AFBD17273E662C97EE72995EF42640C550B9013FAD0761353C7086A272C24088BE94769FD16650" */ + CY_ALIGN(4) static const uint8_t eccP521BasePointY[CY_CRYPTO_ECC_P521_BYTE_SIZE] = + { + 0x50u, 0x66u, 0xd1u, 0x9fu, 0x76u, 0x94u, 0xbeu, 0x88u, + 0x40u, 0xc2u, 0x72u, 0xa2u, 0x86u, 0x70u, 0x3cu, 0x35u, + 0x61u, 0x07u, 0xadu, 0x3fu, 0x01u, 0xb9u, 0x50u, 0xc5u, + 0x40u, 0x26u, 0xf4u, 0x5eu, 0x99u, 0x72u, 0xeeu, 0x97u, + 0x2cu, 0x66u, 0x3eu, 0x27u, 0x17u, 0xbdu, 0xafu, 0x17u, + 0x68u, 0x44u, 0x9bu, 0x57u, 0x49u, 0x44u, 0xf5u, 0x98u, + 0xd9u, 0x1bu, 0x7du, 0x2cu, 0xb4u, 0x5fu, 0x8au, 0x5cu, + 0x04u, 0xc0u, 0x3bu, 0x9au, 0x78u, 0x6au, 0x29u, 0x39u, + 0x18u, 0x01u + }; + + static const cy_stc_crypto_ecc_dp_type eccDomainParams[] = + { + { + CY_CRYPTO_ECC_ECP_NONE, + 0u, + NULL, + CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL + }, + { + CY_CRYPTO_ECC_ECP_SECP192R1, + CY_CRYPTO_ECC_P192_SIZE, + "NIST P-192", + CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG, + /* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF" */ + eccP192Polynomial, + /* barrett_p: "1000000000000000000000000000000010000000000000001" */ + eccP192PolyBarrett, + /* order: "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831" */ + eccP192Order, + /* barrett_o: "1000000000000000000000000662107c9eb94364e4b2dd7cf" */ + eccP192OrderBarrett, + /* base point x: "188DA80EB03090F67CBF20EB43A18800F4FF0AFD82FF1012" */ + eccP192BasePointX, + /* base point y: "07192B95FFC8DA78631011ED6B24CDD573F977A11E794811" */ + eccP192BasePointY + }, + { + CY_CRYPTO_ECC_ECP_SECP224R1, + CY_CRYPTO_ECC_P224_SIZE, + "NIST P-224", + CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG, + /* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001" */ + eccP224Polynomial, + /* barrett_p: "100000000000000000000000000000000ffffffffffffffffffffffff" */ + eccP224PolyBarrett, + /* order: "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D" */ + eccP224Order, + /* barrett_o: "10000000000000000000000000000e95d1f470fc1ec22d6baa3a3d5c3" */ + eccP224OrderBarrett, + /* Gx - base point x: "B70E0CBD6BB4BF7F321390B94A03C1D356C21122343280D6115C1D21" */ + eccP224BasePointX, + /* Gy - base point y: "BD376388B5F723FB4C22DFE6CD4375A05A07476444D5819985007E34" */ + eccP224BasePointY + }, + { + CY_CRYPTO_ECC_ECP_SECP256R1, + CY_CRYPTO_ECC_P256_SIZE, + "NIST P-256", + CY_CRYPTO_NIST_P_BARRETT_RED_ALG, + /* prime: "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF" */ + eccP256Polynomial, + /* barrett_p: "100000000fffffffffffffffefffffffefffffffeffffffff0000000000000003" */ + eccP256PolyBarrett, + /* order: "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551" */ + eccP256Order, + /* barrett_o: "100000000fffffffffffffffeffffffff43190552df1a6c21012ffd85eedf9bfe" */ + eccP256OrderBarrett, + /* Gx - base point x: "6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296" */ + eccP256BasePointX, + /* Gy - base point y: "4FE342E2FE1A7F9B8EE7EB4A7C0F9E162BCE33576B315ECECBB6406837BF51F5" */ + eccP256BasePointY + }, + { + CY_CRYPTO_ECC_ECP_SECP384R1, + CY_CRYPTO_ECC_P384_SIZE, + "NIST P-384", + CY_CRYPTO_NIST_P_BARRETT_RED_ALG, + /* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF" */ + eccP384Polynomial, + /* barrett_p: "1000000000000000000000000000000000000000000000000000000000000000100000000ffffffffffffffff00000001" */ + eccP384PolyBarrett, + /* order: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973" */ + eccP384Order, + /* barrett_o: "1000000000000000000000000000000000000000000000000389cb27e0bc8d220a7e5f24db74f58851313e695333ad68d" */ + eccP384OrderBarrett, + /* base point x: "AA87CA22BE8B05378EB1C71EF320AD746E1D3B628BA79B9859F741E082542A385502F25DBF55296C3A545E3872760AB7" */ + eccP384BasePointX, + /* base point y: "3617DE4A96262C6F5D9E98BF9292DC29F8F41DBD289A147CE9DA3113B5F0B8C00A60B1CE1D7E819D7A431D7C90EA0E5F" */ + eccP384BasePointY + }, + { + CY_CRYPTO_ECC_ECP_SECP521R1, + CY_CRYPTO_ECC_P521_SIZE, + "NIST P-521", + /* Currently driver uses CY_CRYPTO_NIST_P_BARRETT_RED_ALG algorithm instead of + curve specific CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG */ + CY_CRYPTO_NIST_P_BARRETT_RED_ALG, + /* prime: "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" */ + eccP521Polynomial, + /* barrett_p: "20000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001" */ + eccP521PolyBarrett, + /* order: "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409" */ + eccP521Order, + /* barrett_o: "2000000000000000000000000000000000000000000000000000000000000000005ae79787c40d069948033feb708f65a2fc44a36477663b851449048e16ec79bf7" */ + eccP521OrderBarrett, + /* base point x: "0C6858E06B70404E9CD9E3ECB662395B4429C648139053FB521F828AF606B4D3DBAA14B5E77EFE75928FE1DC127A2FFA8DE3348B3C1856A429BF97E7E31C2E5BD66" */ + eccP521BasePointX, + /* base point y: "11839296A789A3BC0045C8A5FB42C7D1BD998F54449579B446817AFBD17273E662C97EE72995EF42640C550B9013FAD0761353C7086A272C24088BE94769FD16650" */ + eccP521BasePointY + } + }; + + cy_stc_crypto_ecc_dp_type *tmpResult = NULL; if ((curveId > CY_CRYPTO_ECC_ECP_NONE) && (curveId < CY_CRYPTO_ECC_ECP_CURVES_CNT)) { - result = (cy_stc_crypto_ecc_dp_type *)&eccDomainParams[curveId]; + tmpResult = (cy_stc_crypto_ecc_dp_type *)&eccDomainParams[curveId]; } - return result; + return tmpResult; } -/* P192 CURVE PARAMETERS */ -CY_ALIGN(4) const uint8_t eccP192Polynomial[CY_CRYPTO_ECC_P192_BYTE_SIZE] = -{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -}; - -CY_ALIGN(4) const uint8_t eccP192PolyBarrett[CY_CRYPTO_ECC_P192_BYTE_SIZE + 1u] = -{ /* pre-calculated */ - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01 -}; -CY_ALIGN(4) const uint8_t eccP192Order[CY_CRYPTO_ECC_P192_BYTE_SIZE] = -{ - 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14, - 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF -}; - -/* barrett_o: "1000000000000000000000000662107c9eb94364e4b2dd7cf" */ -CY_ALIGN(4) const uint8_t eccP192OrderBarrett[CY_CRYPTO_ECC_P192_BYTE_SIZE + 1u] = -{ /* pre-calculated */ - 0xcf, 0xd7, 0x2d, 0x4b, 0x4e, 0x36, 0x94, 0xeb, - 0xc9, 0x07, 0x21, 0x66, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01 -}; - -/* base point x: "188DA80EB03090F67CBF20EB43A18800F4FF0AFD82FF1012" */ -CY_ALIGN(4) const uint8_t eccP192BasePointX[CY_CRYPTO_ECC_P192_BYTE_SIZE] = -{ - 0x12, 0x10, 0xff, 0x82, 0xfd, 0x0a, 0xff, 0xf4, - 0x00, 0x88, 0xa1, 0x43, 0xeb, 0x20, 0xbf, 0x7c, - 0xf6, 0x90, 0x30, 0xb0, 0x0e, 0xa8, 0x8d, 0x18 -}; - -/* base point y: "07192B95FFC8DA78631011ED6B24CDD573F977A11E794811" */ -CY_ALIGN(4) const uint8_t eccP192BasePointY[CY_CRYPTO_ECC_P192_BYTE_SIZE] = -{ - 0x11, 0x48, 0x79, 0x1e, 0xa1, 0x77, 0xf9, 0x73, - 0xd5, 0xcd, 0x24, 0x6b, 0xed, 0x11, 0x10, 0x63, - 0x78, 0xda, 0xc8, 0xff, 0x95, 0x2b, 0x19, 0x07 -}; - -/* P224 CURVE PARAMETERS */ -CY_ALIGN(4) const uint8_t eccP224Polynomial[CY_CRYPTO_ECC_P224_BYTE_SIZE] = -{ - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff -}; - -CY_ALIGN(4) const uint8_t eccP224PolyBarrett[CY_CRYPTO_ECC_P224_BYTE_SIZE + 1u] = -{ /* pre-calculated */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01 -}; - -CY_ALIGN(4) const uint8_t eccP224Order[CY_CRYPTO_ECC_P224_BYTE_SIZE] = -{ - 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, - 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF -}; -/* barrett_o: "10000000000000000000000000000e95d1f470fc1ec22d6baa3a3d5c3" */ -CY_ALIGN(4) const uint8_t eccP224OrderBarrett[CY_CRYPTO_ECC_P224_BYTE_SIZE + 1u] = -{ /* pre-calculated */ - 0xc3, 0xd5, 0xa3, 0xa3, 0xba, 0xd6, 0x22, 0xec, - 0xc1, 0x0f, 0x47, 0x1f, 0x5d, 0xe9, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01 -}; - -/* Gx - base point x: "B70E0CBD6BB4BF7F321390B94A03C1D356C21122343280D6115C1D21" */ -CY_ALIGN(4) const uint8_t eccP224BasePointX[CY_CRYPTO_ECC_P224_BYTE_SIZE] = -{ - 0x21, 0x1d, 0x5c, 0x11, 0xd6, 0x80, 0x32, 0x34, - 0x22, 0x11, 0xc2, 0x56, 0xd3, 0xc1, 0x03, 0x4a, - 0xb9, 0x90, 0x13, 0x32, 0x7f, 0xbf, 0xb4, 0x6b, - 0xbd, 0x0c, 0x0e, 0xb7 -}; - -/* Gy - base point y: "BD376388B5F723FB4C22DFE6CD4375A05A07476444D5819985007E34" */ -CY_ALIGN(4) const uint8_t eccP224BasePointY[CY_CRYPTO_ECC_P224_BYTE_SIZE] = -{ - 0x34, 0x7e, 0x00, 0x85, 0x99, 0x81, 0xd5, 0x44, - 0x64, 0x47, 0x07, 0x5a, 0xa0, 0x75, 0x43, 0xcd, - 0xe6, 0xdf, 0x22, 0x4c, 0xfb, 0x23, 0xf7, 0xb5, - 0x88, 0x63, 0x37, 0xbd -}; - - -/* P256 CURVE PARAMETERS */ -/* prime: "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF" */ -CY_ALIGN(4) const uint8_t eccP256Polynomial[CY_CRYPTO_ECC_P256_BYTE_SIZE] = -{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff -}; - -/* barrett_p: "100000000fffffffffffffffefffffffefffffffeffffffff0000000000000003" */ -CY_ALIGN(4) const uint8_t eccP256PolyBarrett[CY_CRYPTO_ECC_P256_BYTE_SIZE + 1u] = -{ /* pre-calculated! */ - 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x01 -}; - -/* order: "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551" */ -CY_ALIGN(4) const uint8_t eccP256Order[CY_CRYPTO_ECC_P256_BYTE_SIZE] = -{ - 0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, - 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff -}; - -/* barrett_o: 100000000fffffffffffffffeffffffff43190552df1a6c21012ffd85eedf9bfe" */ -CY_ALIGN(4) const uint8_t eccP256OrderBarrett[CY_CRYPTO_ECC_P256_BYTE_SIZE + 1u] = -{ /* pre-calculated */ - 0xfe, 0x9b, 0xdf, 0xee, 0x85, 0xfd, 0x2f, 0x01, - 0x21, 0x6c, 0x1a, 0xdf, 0x52, 0x05, 0x19, 0x43, - 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x01 -}; - -/* base point x: "6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296" */ -CY_ALIGN(4) const uint8_t eccP256BasePointX[CY_CRYPTO_ECC_P256_BYTE_SIZE] = -{ - 0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, - 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, - 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, - 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b -}; - -/* base point y: "4FE342E2FE1A7F9B8EE7EB4A7C0F9E162BCE33576B315ECECBB6406837BF51F5" */ -CY_ALIGN(4) const uint8_t eccP256BasePointY[CY_CRYPTO_ECC_P256_BYTE_SIZE] = -{ - 0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, - 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, - 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, - 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f, -}; - -/* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF" */ -CY_ALIGN(4) const uint8_t eccP384Polynomial[CY_CRYPTO_ECC_P384_BYTE_SIZE] = -{ - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -}; - -/* barrett_p: "1000000000000000000000000000000000000000000000000000000000000000100000000ffffffffffffffff00000001" */ -CY_ALIGN(4) const uint8_t eccP384PolyBarrett[CY_CRYPTO_ECC_P384_BYTE_SIZE + 1u] = -{ /* pre-calculated */ - 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01 -}; - -/* order: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973" */ -CY_ALIGN(4) const uint8_t eccP384Order[CY_CRYPTO_ECC_P384_BYTE_SIZE] = -{ - 0x73, 0x29, 0xC5, 0xCC, 0x6A, 0x19, 0xEC, 0xEC, - 0x7A, 0xA7, 0xB0, 0x48, 0xB2, 0x0D, 0x1A, 0x58, - 0xDF, 0x2D, 0x37, 0xF4, 0x81, 0x4D, 0x63, 0xC7, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF -}; - -/* barrett_o: "1000000000000000000000000000000000000000000000000389cb27e0bc8d220a7e5f24db74f58851313e695333ad68d" */ -CY_ALIGN(4) const uint8_t eccP384OrderBarrett[CY_CRYPTO_ECC_P384_BYTE_SIZE + 1u] = -{ /* pre-calculated */ - 0x8d, 0xd6, 0x3a, 0x33, 0x95, 0xe6, 0x13, 0x13, - 0x85, 0x58, 0x4f, 0xb7, 0x4d, 0xf2, 0xe5, 0xa7, - 0x20, 0xd2, 0xc8, 0x0b, 0x7e, 0xb2, 0x9c, 0x38, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01 -}; - -/* base point x: "AA87CA22BE8B05378EB1C71EF320AD746E1D3B628BA79B9859F741E082542A385502F25DBF55296C3A545E3872760AB7" */ -CY_ALIGN(4) const uint8_t eccP384BasePointX[CY_CRYPTO_ECC_P384_BYTE_SIZE] = -{ - 0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a, - 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55, - 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59, - 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e, - 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e, - 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa -}; - -/* base point y: "3617DE4A96262C6F5D9E98BF9292DC29F8F41DBD289A147CE9DA3113B5F0B8C00A60B1CE1D7E819D7A431D7C90EA0E5F" */ -CY_ALIGN(4) const uint8_t eccP384BasePointY[CY_CRYPTO_ECC_P384_BYTE_SIZE] = -{ - 0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a, - 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a, - 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9, - 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8, - 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d, - 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36 -}; - -CY_ALIGN(4) const uint8_t eccP521Polynomial[CY_CRYPTO_ECC_P521_BYTE_SIZE] = -{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x01 -}; - -CY_ALIGN(4) const uint8_t eccP521PolyBarrett[CY_CRYPTO_ECC_P521_BYTE_SIZE] = -{ /* pre-calculated */ - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02 -}; - -CY_ALIGN(4) const uint8_t eccP521Order[CY_CRYPTO_ECC_P521_BYTE_SIZE] = -{ - 0x09, 0x64, 0x38, 0x91, 0x1E, 0xB7, 0x6F, 0xBB, - 0xAE, 0x47, 0x9C, 0x89, 0xB8, 0xC9, 0xB5, 0x3B, - 0xD0, 0xA5, 0x09, 0xF7, 0x48, 0x01, 0xCC, 0x7F, - 0x6B, 0x96, 0x2F, 0xBF, 0x83, 0x87, 0x86, 0x51, - 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0x01 -}; - -/* barrett_o: "2000000000000000000000000000000000000000000000000000000000000000005ae79787c40d069948033feb708f65a2fc44a36477663b851449048e16ec79bf7" */ -CY_ALIGN(4) const uint8_t eccP521OrderBarrett[CY_CRYPTO_ECC_P521_BYTE_SIZE] = -{ /* pre-calculated */ - 0xf7, 0x9b, 0xc7, 0x6e, 0xe1, 0x48, 0x90, 0x44, - 0x51, 0xb8, 0x63, 0x76, 0x47, 0x36, 0x4a, 0xc4, - 0x2f, 0x5a, 0xf6, 0x08, 0xb7, 0xfe, 0x33, 0x80, - 0x94, 0x69, 0xd0, 0x40, 0x7c, 0x78, 0x79, 0xae, - 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02 -}; - -/* base point x: "00C6858E06B70404E9CD9E3ECB662395B4429C648139053FB521F828AF606B4D3DBAA14B5E77EFE75928FE1DC127A2FFA8DE3348B3C1856A429BF97E7E31C2E5BD66" */ -CY_ALIGN(4) const uint8_t eccP521BasePointX[CY_CRYPTO_ECC_P521_BYTE_SIZE] = -{ - 0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9, - 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33, - 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe, - 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1, - 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8, - 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c, - 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e, - 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85, - 0xc6, 0x00 -}; - -/* base point y: "011839296A789A3BC0045C8A5FB42C7D1BD998F54449579B446817AFBD17273E662C97EE72995EF42640C550B9013FAD0761353C7086A272C24088BE94769FD16650" */ -CY_ALIGN(4) const uint8_t eccP521BasePointY[CY_CRYPTO_ECC_P521_BYTE_SIZE] = -{ - 0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88, - 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35, - 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5, - 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97, - 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17, - 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98, - 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c, - 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39, - 0x18, 0x01 -}; - -const cy_stc_crypto_ecc_dp_type eccDomainParams[] = -{ - { - CY_CRYPTO_ECC_ECP_NONE, - 0, - NULL, - CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL - }, - { - CY_CRYPTO_ECC_ECP_SECP192R1, - CY_CRYPTO_ECC_P192_SIZE, - "NIST P-192", - CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG, - /* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF" */ - eccP192Polynomial, - /* barrett_p: "1000000000000000000000000000000010000000000000001" */ - eccP192PolyBarrett, - /* order: "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831" */ - eccP192Order, - /* barrett_o: "1000000000000000000000000662107c9eb94364e4b2dd7cf" */ - eccP192OrderBarrett, - /* base point x: "188DA80EB03090F67CBF20EB43A18800F4FF0AFD82FF1012" */ - eccP192BasePointX, - /* base point y: "07192B95FFC8DA78631011ED6B24CDD573F977A11E794811" */ - eccP192BasePointY - }, - { - CY_CRYPTO_ECC_ECP_SECP224R1, - CY_CRYPTO_ECC_P224_SIZE, - "NIST P-224", - CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG, - /* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001" */ - eccP224Polynomial, - /* barrett_p: "100000000000000000000000000000000ffffffffffffffffffffffff" */ - eccP224PolyBarrett, - /* order: "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D" */ - eccP224Order, - /* barrett_o: "10000000000000000000000000000e95d1f470fc1ec22d6baa3a3d5c3" */ - eccP224OrderBarrett, - /* Gx - base point x: "B70E0CBD6BB4BF7F321390B94A03C1D356C21122343280D6115C1D21" */ - eccP224BasePointX, - /* Gy - base point y: "BD376388B5F723FB4C22DFE6CD4375A05A07476444D5819985007E34" */ - eccP224BasePointY - }, - { - CY_CRYPTO_ECC_ECP_SECP256R1, - CY_CRYPTO_ECC_P256_SIZE, - "NIST P-256", - CY_CRYPTO_NIST_P_BARRETT_RED_ALG, - /* prime: "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF" */ - eccP256Polynomial, - /* barrett_p: "100000000fffffffffffffffefffffffefffffffeffffffff0000000000000003" */ - eccP256PolyBarrett, - /* order: "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551" */ - eccP256Order, - /* barrett_o: "100000000fffffffffffffffeffffffff43190552df1a6c21012ffd85eedf9bfe" */ - eccP256OrderBarrett, - /* Gx - base point x: "6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296" */ - eccP256BasePointX, - /* Gy - base point y: "4FE342E2FE1A7F9B8EE7EB4A7C0F9E162BCE33576B315ECECBB6406837BF51F5" */ - eccP256BasePointY - }, - { - CY_CRYPTO_ECC_ECP_SECP384R1, - CY_CRYPTO_ECC_P384_SIZE, - "NIST P-384", - CY_CRYPTO_NIST_P_BARRETT_RED_ALG, - /* prime: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF" */ - eccP384Polynomial, - /* barrett_p: "1000000000000000000000000000000000000000000000000000000000000000100000000ffffffffffffffff00000001" */ - eccP384PolyBarrett, - /* order: "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973" */ - eccP384Order, - /* barrett_o: "1000000000000000000000000000000000000000000000000389cb27e0bc8d220a7e5f24db74f58851313e695333ad68d" */ - eccP384OrderBarrett, - /* base point x: "AA87CA22BE8B05378EB1C71EF320AD746E1D3B628BA79B9859F741E082542A385502F25DBF55296C3A545E3872760AB7" */ - eccP384BasePointX, - /* base point y: "3617DE4A96262C6F5D9E98BF9292DC29F8F41DBD289A147CE9DA3113B5F0B8C00A60B1CE1D7E819D7A431D7C90EA0E5F" */ - eccP384BasePointY - }, - { - CY_CRYPTO_ECC_ECP_SECP521R1, - CY_CRYPTO_ECC_P521_SIZE, - "NIST P-521", - /* Currently driver uses CY_CRYPTO_NIST_P_BARRETT_RED_ALG algorithm instead of - curve specific CY_CRYPTO_NIST_P_CURVE_SPECIFIC_RED_ALG */ - CY_CRYPTO_NIST_P_BARRETT_RED_ALG, - /* prime: "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" */ - eccP521Polynomial, - /* barrett_p: "20000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001" */ - eccP521PolyBarrett, - /* order: "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409" */ - eccP521Order, - /* barrett_o: "2000000000000000000000000000000000000000000000000000000000000000005ae79787c40d069948033feb708f65a2fc44a36477663b851449048e16ec79bf7" */ - eccP521OrderBarrett, - /* base point x: "0C6858E06B70404E9CD9E3ECB662395B4429C648139053FB521F828AF606B4D3DBAA14B5E77EFE75928FE1DC127A2FFA8DE3348B3C1856A429BF97E7E31C2E5BD66" */ - eccP521BasePointX, - /* base point y: "11839296A789A3BC0045C8A5FB42C7D1BD998F54449579B446817AFBD17273E662C97EE72995EF42640C550B9013FAD0761353C7086A272C24088BE94769FD16650" */ - eccP521BasePointY - } -}; - /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c index aa7144819a..9ab6d7f46b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c @@ -31,16 +31,6 @@ #include -#define ECC_ECDSA_DEBUG 0 - -#if ECC_ECDSA_DEBUG -#include "cy_crypto_core_my_support.h" -#ifndef Tb_PrintStr -#include -#define Tb_PrintStr(s) printf("%s\n", s) -#endif -#endif - /******************************************************************************* * Function Name: Cy_Crypto_Core_ECC_SignHash @@ -70,22 +60,22 @@ * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8_t *hash, uint32_t hashlen, uint8_t *sig, - cy_stc_crypto_ecc_key *key, uint8_t *messageKey) + const cy_stc_crypto_ecc_key *key, const uint8_t *messageKey) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; cy_stc_crypto_ecc_key ephKey; uint8_t myKGX[CY_CRYPTO_ECC_MAX_BYTE_SIZE]; uint8_t myKGY[CY_CRYPTO_ECC_MAX_BYTE_SIZE]; const cy_stc_crypto_ecc_dp_type *eccDp; - uint32_t mallocMask = 0; + uint32_t mallocMask = 0U; uint32_t bitsize; /* NULL parameters checking */ if ((hash != NULL) && (sig != NULL) && (key != NULL) && (messageKey != NULL)) { - myResult = CY_CRYPTO_NOT_SUPPORTED; + tmpResult = CY_CRYPTO_NOT_SUPPORTED; eccDp = Cy_Crypto_Core_ECC_GetCurveParams(key->curveID); @@ -93,44 +83,27 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 { bitsize = eccDp->size; - #if ECC_ECDSA_DEBUG - Tb_PrintStr("\necc_sign_hash() for "); - Tb_PrintStr(eccDp->name); - Tb_PrintStr("\n"); - #endif /* ECC_ECDSA_DEBUG */ - /* make ephemeral key pair */ ephKey.pubkey.x = myKGX; ephKey.pubkey.y = myKGY; - myResult = Cy_Crypto_Core_ECC_MakePublicKey(base, key->curveID, messageKey, &ephKey); + tmpResult = Cy_Crypto_Core_ECC_MakePublicKey(base, key->curveID, messageKey, &ephKey); - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = CY_CRYPTO_BAD_PARAMS; + tmpResult = CY_CRYPTO_BAD_PARAMS; - int dividend = 0; /* for whatever reason Crypto_EC_DivMod only works if dividend is in register 0 */ - int p_temp = 8; - int p_r = 9; - int p_s = 10; - int p_d = 11; - - #if ECC_ECDSA_DEBUG - Tb_PrintStr("%10s: \t", "hash"); - Crypto_PrintNumber((uint8_t *)hash, hashlen); - - Tb_PrintStr("%10s: \t", "k"); - Crypto_PrintNumber(messageKey, CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)); - - Tb_PrintStr("%10s: \t", "x1"); - Crypto_PrintNumber((uint8_t *)ephKey.pubkey.x, CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)); - #endif /* ECC_ECDSA_DEBUG */ + uint32_t dividend = 0U; /* for whatever reason Crypto_EC_DivMod only works if dividend is in register 0 */ + uint32_t p_temp = 8U; + uint32_t p_r = 9U; + uint32_t p_s = 10U; + uint32_t p_d = 11U; /* load values needed for reduction modulo order of the base point */ CY_CRYPTO_VU_ALLOC_MEM (base, VR_P, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, (uint8_t *)eccDp->order, bitsize); - CY_CRYPTO_VU_ALLOC_MEM (base, VR_BARRETT, bitsize + 1); + CY_CRYPTO_VU_ALLOC_MEM (base, VR_BARRETT, bitsize + 1U); Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, (uint8_t *)eccDp->barrett_o, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_r, bitsize); @@ -140,7 +113,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 if (!Cy_Crypto_Core_Vu_IsRegZero(base, p_r)) { - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; CY_CRYPTO_VU_ALLOC_MEM (base, p_d, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_s, bitsize); @@ -162,15 +135,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 /* r = x1 mod n */ Cy_Crypto_Core_Vu_GetMemValue (base, sig, p_r, bitsize); - #if ECC_ECDSA_DEBUG - Tb_PrintStr("x1 after reduction modulo order: "); - Crypto_RegMemNumberPrint(p_r); - #endif /* ECC_ECDSA_DEBUG */ - if (Cy_Crypto_Core_Vu_IsRegZero(base, p_r)) { /* R is zero!!! */ - myResult = CY_CRYPTO_HW_ERROR; + tmpResult = CY_CRYPTO_HW_ERROR; } } else @@ -180,14 +148,14 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 Cy_Crypto_Core_MemCpy(base, sig, ephKey.pubkey.x, (uint16_t)CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)); } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { /* find s = (e + d*r)/k */ /* load signing private key */ Cy_Crypto_Core_Vu_SetMemValue (base, p_d, (uint8_t *)key->k, bitsize); - /* use barrett reduction algorithm for operations modulo n (order of the base point) */ + /* use Barrett reduction algorithm for operations modulo n (order of the base point) */ Cy_Crypto_Core_EC_NistP_SetRedAlg(CY_CRYPTO_NIST_P_BARRETT_RED_ALG); /* d*r mod n */ @@ -202,7 +170,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 } else { - Cy_Crypto_Core_Vu_SetMemValue (base, p_d, (uint8_t *)hash, hashlen * 8); + Cy_Crypto_Core_Vu_SetMemValue (base, p_d, (uint8_t *)hash, hashlen * 8U); } Cy_Crypto_Core_Vu_SetMemValue (base, p_r, messageKey, bitsize); @@ -226,14 +194,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 } else { - myResult = CY_CRYPTO_HW_ERROR; + tmpResult = CY_CRYPTO_HW_ERROR; } - - #if ECC_ECDSA_DEBUG - Crypto_PrintRegister(p_r, "k"); - Crypto_PrintRegister(p_s, "(e+d*r)/k"); - #endif /* ECC_ECDSA_DEBUG */ - } } @@ -243,7 +205,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 } } - return (myResult); + return (tmpResult); } @@ -276,47 +238,40 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_SignHash(CRYPTO_Type *base, const uint8 *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, const uint8_t *sig, const uint8_t *hash, uint32_t hashlen, - uint8_t *stat, cy_stc_crypto_ecc_key *key) + uint8_t *stat, const cy_stc_crypto_ecc_key *key) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; const cy_stc_crypto_ecc_dp_type *eccDp; uint32_t bitsize; - uint32_t mallocMask = 0; + uint32_t mallocMask = 0U; /* NULL parameters checking */ if ((sig != NULL) && (hash != NULL) && (stat != NULL) && (key != NULL)) { - myResult = CY_CRYPTO_NOT_SUPPORTED; + tmpResult = CY_CRYPTO_NOT_SUPPORTED; eccDp = Cy_Crypto_Core_ECC_GetCurveParams(key->curveID); if (eccDp != NULL) { - - #if ECC_ECDSA_DEBUG - Tb_PrintStr("\necc_verify_hash() for "); - Tb_PrintStr((char *)eccDp->name); - Tb_PrintStr("\n"); - #endif /* ECC_ECDSA_DEBUG */ - bitsize = eccDp->size; - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; - int dividend = 0; /* for whatever reason Crypto_EC_DivMod only works if dividend is in register 0 */ - int p_r = 4; - int p_s = 5; - int p_u1 = 6; - int p_u2 = 7; - int p_o = 8; - int p_gx = 9; - int p_gy = 10; - int p_qx = 11; - int p_qy = 12; + uint32_t dividend = 0u; /* for whatever reason Crypto_EC_DivMod only works if dividend is in register 0 */ + uint32_t p_r = 4U; + uint32_t p_s = 5U; + uint32_t p_u1 = 6U; + uint32_t p_u2 = 7U; + uint32_t p_o = 8U; + uint32_t p_gx = 9U; + uint32_t p_gy = 10U; + uint32_t p_qx = 11U; + uint32_t p_qy = 12U; - /* use barrett reduction algorithm for operations modulo n (order of the base point) */ + /* use Barrett reduction algorithm for operations modulo n (order of the base point) */ Cy_Crypto_Core_EC_NistP_SetRedAlg(CY_CRYPTO_NIST_P_BARRETT_RED_ALG); Cy_Crypto_Core_EC_NistP_SetMode(bitsize); @@ -325,13 +280,13 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, CY_CRYPTO_VU_ALLOC_MEM (base, VR_P, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, (uint8_t *)eccDp->order, bitsize); - CY_CRYPTO_VU_ALLOC_MEM (base, VR_BARRETT, bitsize + 1); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, (uint8_t *)eccDp->barrett_o, bitsize + 1); + CY_CRYPTO_VU_ALLOC_MEM (base, VR_BARRETT, bitsize + 1U); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, (uint8_t *)eccDp->barrett_o, bitsize + 1U); /*******************************************************************************/ /* check that R and S are within the valid range, i.e. 0 < R < n and 0 < S < n */ - CY_CRYPTO_VU_ALLOC_MEM (base, p_r, bitsize); - CY_CRYPTO_VU_ALLOC_MEM (base, p_s, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, p_r, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, p_s, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, p_r, (uint8_t *)sig, bitsize); Cy_Crypto_Core_Vu_SetMemValue (base, p_s, (uint8_t *)&sig[CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)], bitsize); @@ -342,28 +297,28 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, if (Cy_Crypto_Core_Vu_IsRegZero(base, p_r)) { /* R is zero!!! */ - myResult = CY_CRYPTO_BAD_PARAMS; + tmpResult = CY_CRYPTO_BAD_PARAMS; } if (!Cy_Crypto_Core_Vu_IsRegLess(base, p_r, VR_P)) { /* R is not less than n!!! */ - myResult = CY_CRYPTO_BAD_PARAMS; + tmpResult = CY_CRYPTO_BAD_PARAMS; } if (Cy_Crypto_Core_Vu_IsRegZero(base, p_s)) { /* S is zero!!! */ - myResult = CY_CRYPTO_BAD_PARAMS; + tmpResult = CY_CRYPTO_BAD_PARAMS; } if (!Cy_Crypto_Core_Vu_IsRegLess(base, p_s, VR_P)) { /* S is not less than n!!! */ - myResult = CY_CRYPTO_BAD_PARAMS; + tmpResult = CY_CRYPTO_BAD_PARAMS; } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { CY_CRYPTO_VU_ALLOC_MEM (base, dividend, bitsize); - CY_CRYPTO_VU_ALLOC_MEM (base, p_o, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, p_o, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_u1, bitsize); CY_CRYPTO_VU_ALLOC_MEM (base, p_u2, bitsize); @@ -386,41 +341,25 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, } else { - Cy_Crypto_Core_Vu_SetMemValue (base, p_u1, (uint8_t *)hash, hashlen * 8); + Cy_Crypto_Core_Vu_SetMemValue (base, p_u1, (uint8_t *)hash, hashlen * 8U); } - #if ECC_ECDSA_DEBUG - Crypto_PrintRegister(p_u1, "hash"); - Crypto_PrintRegister(p_r, "R"); - Crypto_PrintRegister(p_s, "S"); - Tb_PrintStr("\n"); - #endif /* ECC_ECDSA_DEBUG */ - /* w = s^-1 mod n */ CY_CRYPTO_VU_SET_TO_ONE(base, dividend); Cy_Crypto_Core_EC_DivMod(base, p_s, dividend, p_s, bitsize); - #if ECC_ECDSA_DEBUG - Crypto_PrintRegister(p_s, "w"); - #endif /* ECC_ECDSA_DEBUG */ - /* u1 = e*w mod n */ Cy_Crypto_Core_EC_MulMod(base, p_u1, p_u1, p_s, bitsize); /* u2 = r*w mod n */ - Cy_Crypto_Core_EC_MulMod(base, p_u2, p_r, p_s, bitsize); - - #if ECC_ECDSA_DEBUG - Crypto_PrintRegister(p_u1, "u1"); - Crypto_PrintRegister(p_u2, "u2"); - #endif /* ECC_ECDSA_DEBUG */ + Cy_Crypto_Core_EC_MulMod(base, p_u2, p_r, p_s, bitsize); /* Initialize point multiplication */ Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); - /* load prime, order and barrett coefficient */ - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, (uint8_t *)eccDp->prime, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_o, (uint8_t *)eccDp->order, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, (uint8_t *)eccDp->barrett_p, bitsize + 1); + /* load prime, order and Barrett coefficient */ + Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, (uint8_t *)eccDp->prime, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, p_o, (uint8_t *)eccDp->order, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, (uint8_t *)eccDp->barrett_p, bitsize + 1U); /* load base Point G */ Cy_Crypto_Core_Vu_SetMemValue (base, p_gx, (uint8_t *)eccDp->Gx, bitsize); @@ -439,40 +378,22 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, /* u2 * Qa */ Cy_Crypto_Core_EC_NistP_PointMul(base, p_qx, p_qy, p_u2, p_o, bitsize); - #if ECC_ECDSA_DEBUG - Tb_PrintStr("u1 * G: \n"); - Crypto_PrintRegister(p_gx, " u1*G(x)"); - Crypto_PrintRegister(p_gy, " u1*G(y)"); - Tb_PrintStr("u2 * Q: \n"); - Crypto_PrintRegister(p_qx, " u2*Q(x)"); - Crypto_PrintRegister(p_qy, " u2*Q(x)"); - #endif /* ECC_ECDSA_DEBUG */ - /* P = u1 * G + u2 * Qa. Only Px is needed */ Cy_Crypto_Core_EC_SubMod(base, dividend, p_qy, p_gy); /* (y2-y1) */ Cy_Crypto_Core_EC_SubMod(base, p_s, p_qx, p_gx); /* (x2-x1) */ Cy_Crypto_Core_EC_DivMod(base, p_s, dividend, p_s, bitsize); /* s = (y2-y1)/(x2-x1) */ - #if ECC_ECDSA_DEBUG - Tb_PrintStr("Point addition: \n"); - Crypto_PrintRegister(p_s, "s"); - #endif /* ECC_ECDSA_DEBUG */ - Cy_Crypto_Core_EC_SquareMod (base, p_s, p_s, bitsize); /* s^2 */ Cy_Crypto_Core_EC_SubMod (base, p_s, p_s, p_gx); /* s^2 - x1 */ Cy_Crypto_Core_EC_SubMod (base, p_s, p_s, p_qx); /* s^2 - x1 - x2 which is Px mod n */ - #if ECC_ECDSA_DEBUG - Crypto_PrintRegister(p_s, "px"); - #endif /* ECC_ECDSA_DEBUG */ - if (Cy_Crypto_Core_Vu_IsRegEqual(base, p_s, p_r)) { - *stat = 1; + *stat = 1u; } else { - *stat = 0; + *stat = 0u; } } @@ -481,7 +402,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_VerifyHash(CRYPTO_Type *base, } } - return (myResult); + return (tmpResult); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c index 2bc05400f4..43a8018b58 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c @@ -29,11 +29,8 @@ #include "cy_crypto_core_vu.h" #include "cy_crypto_core_trng.h" -#define CY_ECC_CONFIG_TR_GARO_CTL 0x6C740B8Du -#define CY_ECC_CONFIG_TR_FIRO_CTL 0x52D246E1u - -/* print some debug information. enabling this will render meaningless all time measurements */ -#define ECC_KEY_GEN_DEBUG 0 +#define CY_ECC_CONFIG_TR_GARO_CTL 0x6C740B8DuL +#define CY_ECC_CONFIG_TR_FIRO_CTL 0x52D246E1uL /******************************************************************************* @@ -65,152 +62,135 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakeKeyPair(CRYPTO_Type *base, cy_func_get_random_data_t GetRandomDataFunc, void *randomDataInfo) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_NOT_SUPPORTED; + cy_stc_crypto_ecc_dp_type *eccDp = Cy_Crypto_Core_ECC_GetCurveParams(curveID); - if (eccDp == NULL || key == NULL) + if ((eccDp != NULL) && (key != NULL)) { - /* NULL parameter detected in Cy_Crypto_Core_ECC_MakeKeyPair()!!! */ - return CY_CRYPTO_NOT_SUPPORTED; - } + tmpResult = CY_CRYPTO_SUCCESS; -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("\necc_make_key() for "); - Tb_PrintStr((int8_t *)eccDp->name); - Tb_PrintStr("\n"); -#endif /* ECC_KEY_GEN_DEBUG */ + uint32_t bitsize = eccDp->size; - int bitsize = eccDp->size; + /* used VU registers. Same values as in crypto_NIST_P.c */ + uint32_t p_temp = 8u; /* temporal values */ + uint32_t p_order = 9u; /* order of the curve */ + uint32_t p_d = 10u; /* private key */ + uint32_t p_x = 11u; /* x coordinate */ + uint32_t p_y = 12u; /* y coordinate */ - /* used VU registers. Same values as in crypto_NIST_P.c */ - int p_temp = 8; /* temporal values */ - int p_order = 9; /* order of the curve */ - int p_d = 10; /* private key */ - int p_x = 11; /* x coordinate */ - int p_y = 12; /* y coordinate */ + CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, p_order, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1U); + CY_CRYPTO_VU_ALLOC_MEM(base, p_x, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, p_y, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, p_order, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1); - CY_CRYPTO_VU_ALLOC_MEM(base, p_x, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, p_y, bitsize); + /*************************************************************** + * Apply domain parameters + ***************************************************************/ + /* load prime and order defining the curve as well as the Barrett coefficient. */ + /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ + Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->prime, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, p_order, eccDp->order, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_p, bitsize + 1U); - /*************************************************************** - * Apply domain parameters - ***************************************************************/ - /* load prime and order defining the curve as well as the barrett coefficient. */ + /* Base Point, G = (p_x, p_y) */ + Cy_Crypto_Core_Vu_SetMemValue (base, p_x, eccDp->Gx, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, p_y, eccDp->Gy, bitsize); - /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->prime, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_order, eccDp->order, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_p, bitsize + 1); + Cy_Crypto_Core_EC_NistP_SetMode(bitsize); + Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); - /* Base Point, G = (p_x, p_y) */ - Cy_Crypto_Core_Vu_SetMemValue (base, p_x, eccDp->Gx, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_y, eccDp->Gy, bitsize); - - Cy_Crypto_Core_EC_NistP_SetMode(bitsize); - Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); - - - /*************************************************************** - * generate random string - ***************************************************************/ - if (GetRandomDataFunc != NULL) - { - GetRandomDataFunc( randomDataInfo, key->k, (bitsize + 7u) >> 3u ); - } - else - { - for (int i = 0, randomsize = bitsize; randomsize > 0; randomsize-=32, i++) + /*************************************************************** + * generate random string + ***************************************************************/ + if (GetRandomDataFunc != NULL) { - int randombits = CY_CRYPTO_MIN(randomsize, 32); + (void)GetRandomDataFunc( randomDataInfo, (uint8_t*)key->k, ((bitsize + 7U) >> 3U) ); + } + else + { + uint32_t i = 0U; + int32_t randomsize = (int32_t)bitsize; + cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; - cy_en_crypto_status_t error = Cy_Crypto_Core_Trng(base, CY_ECC_CONFIG_TR_GARO_CTL, CY_ECC_CONFIG_TR_FIRO_CTL, - randombits, &((uint32_t *)key->k)[i]); - - if (CY_CRYPTO_SUCCESS != error) + while ((randomsize > 0) && (CY_CRYPTO_SUCCESS == status)) { - return CY_CRYPTO_HW_ERROR; + uint32_t randombits = (uint32_t)CY_CRYPTO_MIN(randomsize, 32); + + status = Cy_Crypto_Core_Trng(base, CY_ECC_CONFIG_TR_GARO_CTL, CY_ECC_CONFIG_TR_FIRO_CTL, + randombits, &((uint32_t *)key->k)[i]); + randomsize -= 32; + i++; + + if (CY_CRYPTO_SUCCESS != status) + { + tmpResult = CY_CRYPTO_HW_ERROR; + } } } + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + /*************************************************************** + * Load random data into VU + ***************************************************************/ + CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); + Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)key->k, bitsize); + + /* check that the key is smaller than the order of base point */ + CY_CRYPTO_VU_CMP_SUB (base, p_d, p_order); /* C = (a >= b) */ + uint32_t status = Cy_Crypto_Core_Vu_StatusRead(base); + + if (0u != (status & CY_CRYPTO_VU_STATUS_CARRY_BIT)) + { + /* random data >= order, needs reduction */ + + CY_CRYPTO_VU_PUSH_REG(base); + + /* load values needed for reduction modulo curve order */ + CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->order, bitsize); + + CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_o, bitsize + 1u); + + CY_CRYPTO_VU_ALLOC_MEM(base, p_temp, bitsize); + CY_CRYPTO_VU_MOV(base, p_temp, p_d); + + /* z = x % mod */ + Cy_Crypto_Core_EC_Bar_MulRed(base, p_d, p_temp, bitsize); + + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(p_temp) | CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT)); + + Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->k, p_d, bitsize); + + /* restore previous prime and Barrett values */ + CY_CRYPTO_VU_POP_REG(base); + } + + /* + * Make the public key + * EC scalar multiplication - X,Y-only co-Z arithmetic + */ + Cy_Crypto_Core_EC_NistP_PointMul(base, p_x, p_y, p_d, p_order, bitsize); + + Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->pubkey.x, p_x, bitsize); + Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->pubkey.y, p_y, bitsize); + + key->type = PK_PRIVATE; + key->curveID = curveID; + + tmpResult = CY_CRYPTO_SUCCESS; + } + + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | + CY_CRYPTO_VU_REG_BIT(p_x) | CY_CRYPTO_VU_REG_BIT(p_y) | + CY_CRYPTO_VU_REG_BIT(p_order) | CY_CRYPTO_VU_REG_BIT(p_d)); } - - /*************************************************************** - * Load random data into VU - ***************************************************************/ - CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); - Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)key->k, bitsize); - -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("random data: "); - Crypto_RegMemNumberPrint(p_d); - Tb_PrintStr("p_order: "); - Crypto_RegMemNumberPrint(p_order); -#endif /*ECC_KEY_GEN_DEBUG */ - - /* check that the key is smaller than the order of base point */ - CY_CRYPTO_VU_CMP_SUB (base, p_d, p_order); /* C = (a >= b) */ - uint16_t status = Cy_Crypto_Core_Vu_StatusRead(base); - - if (status & CY_CRYPTO_VU_STATUS_CARRY_BIT) - { - /* random data >= order, needs reduction */ - - CY_CRYPTO_VU_PUSH_REG(base); - - /* load values needed for reduction modulo curve order */ - CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->order, bitsize); - - CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_o, bitsize + 1u); - - CY_CRYPTO_VU_ALLOC_MEM(base, p_temp, bitsize); - CY_CRYPTO_VU_MOV(base, p_temp, p_d); - - /* z = x % mod */ - Cy_Crypto_Core_EC_Bar_MulRed(base, p_d, p_temp, bitsize); - - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(p_temp) | CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT)); - - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->k, p_d, bitsize); - - /* restore previous prime and barrett values */ - CY_CRYPTO_VU_POP_REG(base); - -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("random data after reduction modulo order: "); - Crypto_RegMemNumberPrint(p_d); -#endif /* ECC_KEY_GEN_DEBUG */ - - } - else - { - /* carry is clear, i. e. p_d < p_order */ - } - - /* make the public key - * EC scalar multiplication - X,Y-only co-Z arithmetic - */ -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("Doing scalar multiplication\n"); -#endif /* ECC_KEY_GEN_DEBUG */ - - Cy_Crypto_Core_EC_NistP_PointMul(base, p_x, p_y, p_d, p_order, bitsize); - - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->pubkey.x, p_x, bitsize); - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key->pubkey.y, p_y, bitsize); - - key->type = PK_PRIVATE; - key->curveID = curveID; - - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | - CY_CRYPTO_VU_REG_BIT(p_x) | CY_CRYPTO_VU_REG_BIT(p_y) | - CY_CRYPTO_VU_REG_BIT(p_order) | CY_CRYPTO_VU_REG_BIT(p_d)); - - return CY_CRYPTO_SUCCESS; + return (tmpResult); } @@ -242,105 +222,88 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePrivateKey(CRYPTO_Type *base, uint8_t *key, cy_func_get_random_data_t GetRandomDataFunc, void *randomDataInfo) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; + const cy_stc_crypto_ecc_dp_type *eccDp = Cy_Crypto_Core_ECC_GetCurveParams(curveID); - if (eccDp == NULL || key == NULL) + if ((eccDp != NULL) && (key != NULL)) { - /* NULL parameter detected in Cy_Crypto_Core_ECC_MakeKey()!!! */ - return CY_CRYPTO_NOT_SUPPORTED; - } + tmpResult = CY_CRYPTO_SUCCESS; -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("\necc_make_key() for "); - Tb_PrintStr((int8_t *)eccDp->name); - Tb_PrintStr("\n"); -#endif /* ECC_KEY_GEN_DEBUG */ + uint32_t bitsize = eccDp->size; - int bitsize = eccDp->size; + uint32_t p_temp = 8u; /* temporal values */ + uint32_t p_d = 10u; /* private key */ - int p_temp = 8; /* temporal values */ - int p_d = 10; /* private key */ - - /* generate random string */ - if (GetRandomDataFunc != NULL) - { - GetRandomDataFunc( randomDataInfo, key, (bitsize + 7u) >> 3u ); - } - else - { - for (int i = 0, randomsize = bitsize; randomsize > 0; randomsize-=32, i++) + /* generate random string */ + if (GetRandomDataFunc != NULL) { - int randombits = CY_CRYPTO_MIN(randomsize, 32); + (void)GetRandomDataFunc( randomDataInfo, key, ((bitsize + 7U) >> 3U) ); + } + else + { + uint32_t i = 0U; + int32_t randomsize = (int32_t)bitsize; + cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; - cy_en_crypto_status_t error = Cy_Crypto_Core_Trng(base, CY_ECC_CONFIG_TR_GARO_CTL, CY_ECC_CONFIG_TR_FIRO_CTL, - randombits, &((uint32_t *)key)[i]); - - if (CY_CRYPTO_SUCCESS != error) + while ((randomsize > 0) && (CY_CRYPTO_SUCCESS == status)) { - return CY_CRYPTO_HW_ERROR; + uint32_t randombits = (uint32_t)CY_CRYPTO_MIN(randomsize, 32); + + status = Cy_Crypto_Core_Trng(base, CY_ECC_CONFIG_TR_GARO_CTL, CY_ECC_CONFIG_TR_FIRO_CTL, + randombits, &((uint32_t *)key)[i]); + randomsize -= 32; + i++; + + if (CY_CRYPTO_SUCCESS != status) + { + tmpResult = CY_CRYPTO_HW_ERROR; + } } } + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + /* load prime and order defining the curve as well as the barrett coefficient. */ + /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ + CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->order, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_o, bitsize + 1u); + + /* Load random data into VU */ + CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); + Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)key, bitsize); + + CY_CRYPTO_VU_ALLOC_MEM(base, p_temp, bitsize); + CY_CRYPTO_VU_MOV(base, p_temp, p_d); + + /* check that the key is smaller than the order of base point */ + CY_CRYPTO_VU_CMP_SUB (base, p_d, VR_P); /* C = (a >= b) */ + uint32_t status = Cy_Crypto_Core_Vu_StatusRead(base); + + if (0u != (status & CY_CRYPTO_VU_STATUS_CARRY_BIT)) + { + /* private key (random data) >= order, needs reduction */ + + /* use Barrett reduction algorithm for operations modulo n (order of the base point) */ + Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); + Cy_Crypto_Core_EC_NistP_SetMode(bitsize); + + /* z = x % mod */ + Cy_Crypto_Core_EC_Bar_MulRed(base, p_d, p_temp, bitsize); + + Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key, p_d, bitsize); + } + + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | + CY_CRYPTO_VU_REG_BIT(p_d) | CY_CRYPTO_VU_REG_BIT(p_temp)); + + tmpResult = CY_CRYPTO_SUCCESS; + } } -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("private key: "); - Crypto_PrintNumber((uint8_t *)key, CY_CRYPTO_BYTE_SIZE_OF_BITS(bitsize)); -#endif /* ECC_KEY_GEN_DEBUG */ - - - /* load prime and order defining the curve as well as the barrett coefficient. */ - /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ - CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->order, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_o, bitsize + 1); - - /* Load random data into VU */ - CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); - Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)key, bitsize); - - CY_CRYPTO_VU_ALLOC_MEM(base, p_temp, bitsize); - CY_CRYPTO_VU_MOV(base, p_temp, p_d); - -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("random data: "); - Crypto_RegMemNumberPrint(p_d); - Tb_PrintStr("p_order: "); - Crypto_RegMemNumberPrint(VR_P); -#endif /* ECC_KEY_GEN_DEBUG */ - - /* check that the key is smaller than the order of base point */ - CY_CRYPTO_VU_CMP_SUB (base, p_d, VR_P); /* C = (a >= b) */ - uint16_t status = Cy_Crypto_Core_Vu_StatusRead(base); - - if (status & CY_CRYPTO_VU_STATUS_CARRY_BIT) - { - /* private key (random data) >= order, needs reduction */ - - /* use barrett reduction algorithm for operations modulo n (order of the base point) */ - Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); - Cy_Crypto_Core_EC_NistP_SetMode(bitsize); - - /* z = x % mod */ - Cy_Crypto_Core_EC_Bar_MulRed(base, p_d, p_temp, bitsize); - - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)key, p_d, bitsize); - -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("private key after reduction modulo order: "); - Crypto_RegMemNumberPrint(p_d); -#endif /* ECC_KEY_GEN_DEBUG */ - - } - else - { - /* carry is clear, i. e. p_d < p_order */ - } - - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | - CY_CRYPTO_VU_REG_BIT(p_d) | CY_CRYPTO_VU_REG_BIT(p_temp)); - - return CY_CRYPTO_SUCCESS; + return (tmpResult); } @@ -367,71 +330,66 @@ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePrivateKey(CRYPTO_Type *base, *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_ECC_MakePublicKey(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, - uint8_t *privateKey, + const uint8_t *privateKey, cy_stc_crypto_ecc_key *publicKey) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; + cy_stc_crypto_ecc_dp_type *eccDp = Cy_Crypto_Core_ECC_GetCurveParams(curveID); - if (eccDp == NULL || privateKey == NULL || publicKey == NULL) + if ((eccDp != NULL) && (privateKey != NULL) && (publicKey != NULL)) { - /* NULL parameter detected in Cy_Crypto_Core_ECC_MakeKey()!!! */ - return CY_CRYPTO_NOT_SUPPORTED; + uint32_t bitsize = eccDp->size; + + uint32_t p_order = 9u; /* order of the curve */ + uint32_t p_d = 10u; /* private key */ + uint32_t p_x = 11u; /* x coordinate */ + uint32_t p_y = 12u; /* y coordinate */ + + /* make the public key + * EC scalar multiplication - X,Y-only co-Z arithmetic + */ + CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, p_order, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1u); + CY_CRYPTO_VU_ALLOC_MEM(base, p_x, bitsize); + CY_CRYPTO_VU_ALLOC_MEM(base, p_y, bitsize); + + /* Apply domain parameters */ + + /* load prime and order defining the curve as well as the barrett coefficient. */ + + /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ + Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->prime, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, p_order, eccDp->order, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_p, bitsize + 1u); + + /*Base Point, G = (p_x, p_y) */ + Cy_Crypto_Core_Vu_SetMemValue (base, p_x, eccDp->Gx, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, p_y, eccDp->Gy, bitsize); + + Cy_Crypto_Core_EC_NistP_SetMode(bitsize); + Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); + + /* Load random data into VU */ + CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); + Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)privateKey, bitsize); + + Cy_Crypto_Core_EC_NistP_PointMul(base, p_x, p_y, p_d, p_order, bitsize); + + Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)publicKey->pubkey.x, p_x, bitsize); + Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)publicKey->pubkey.y, p_y, bitsize); + + publicKey->type = PK_PUBLIC; + publicKey->curveID = curveID; + + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(p_order) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | + CY_CRYPTO_VU_REG_BIT(p_x) | CY_CRYPTO_VU_REG_BIT(p_y) | CY_CRYPTO_VU_REG_BIT(p_d)); + + tmpResult = CY_CRYPTO_SUCCESS; } -#if ECC_KEY_GEN_DEBUG - Tb_PrintStr("\necc_make public key() for "); - Tb_PrintStr((int8_t *)eccDp->name); - Tb_PrintStr("\n"); -#endif /* ECC_KEY_GEN_DEBUG */ - - int bitsize = eccDp->size; - - int p_order = 9; /* order of the curve */ - int p_d = 10; /* private key */ - int p_x = 11; /* x coordinate */ - int p_y = 12; /* y coordinate */ - - /* make the public key - * EC scalar multiplication - X,Y-only co-Z arithmetic - */ - CY_CRYPTO_VU_ALLOC_MEM(base, VR_P, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, p_order, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, VR_BARRETT, bitsize + 1); - CY_CRYPTO_VU_ALLOC_MEM(base, p_x, bitsize); - CY_CRYPTO_VU_ALLOC_MEM(base, p_y, bitsize); - - /* Apply domain parameters */ - - /* load prime and order defining the curve as well as the barrett coefficient. */ - - /* P and BARRETT_U are "globally" defined in cy_crypto_core_ecc.h */ - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, eccDp->prime, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_order, eccDp->order, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, eccDp->barrett_p, bitsize + 1); - - /*Base Point, G = (p_x, p_y) */ - Cy_Crypto_Core_Vu_SetMemValue (base, p_x, eccDp->Gx, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, p_y, eccDp->Gy, bitsize); - - Cy_Crypto_Core_EC_NistP_SetMode(bitsize); - Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); - - /* Load random data into VU */ - CY_CRYPTO_VU_ALLOC_MEM(base, p_d, bitsize); - Cy_Crypto_Core_Vu_SetMemValue(base, p_d, (uint8_t *)privateKey, bitsize); - - Cy_Crypto_Core_EC_NistP_PointMul(base, p_x, p_y, p_d, p_order, bitsize); - - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)publicKey->pubkey.x, p_x, bitsize); - Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t *)publicKey->pubkey.y, p_y, bitsize); - - publicKey->type = PK_PUBLIC; - publicKey->curveID = curveID; - - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(VR_P) | CY_CRYPTO_VU_REG_BIT(p_order) | CY_CRYPTO_VU_REG_BIT(VR_BARRETT) | - CY_CRYPTO_VU_REG_BIT(p_x) | CY_CRYPTO_VU_REG_BIT(p_y) | CY_CRYPTO_VU_REG_BIT(p_d)); - - return CY_CRYPTO_SUCCESS; + return (tmpResult); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c index 17718cbbd6..e73f4ddf24 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c @@ -52,34 +52,32 @@ /*************************************************************** * Global Variables ***************************************************************/ -static int eccMode; +static cy_en_crypto_ecc_curve_id_t eccMode; static cy_en_crypto_ecc_red_mul_algs_t mul_red_alg_select = CY_CRYPTO_NIST_P_BARRETT_RED_ALG; -/* Pre-computed coefficients for shift-multiply modular reduction for P256 and P384 */ -const uint8_t P256_ShMul_COEFF[] = { - 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xFEu, 0xFFu, 0xFFu, 0xFFu -}; - -const uint8_t P384_ShMul_COEFF[] = { - 0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, - 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, - 0x01u -}; - - - /*************************************************************** * Collection of multiplication reduction algorithms -* Method 1 (Crypto_EC_CS_MUL_Red_Pxxx): curve specific -* reduction as proposed by NIST -* Method 2 (Crypto_EC_SM_MUL_Red_Pxxx): curve specific r -* eduction based on Mersenne prime reduction approach +* Method 1: (Crypto_EC_CS_MUL_Red_Pxxx): curve specific +* reduction as proposed by NIST +* Method 2: (Crypto_EC_SM_MUL_Red_Pxxx): curve specific r +* eduction based on Mersenne prime reduction approach * Method 3: generic Barrett reduction ***************************************************************/ +static void Cy_Crypto_Core_EC_CS_MUL_Red_P192(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_CS_MUL_Red_P224(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_CS_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_CS_MUL_Red_P384(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_SM_MUL_Red_P192(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_SM_MUL_Red_P224(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_SM_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_SM_MUL_Red_P384(CRYPTO_Type *base, uint32_t z, uint32_t x); +static void Cy_Crypto_Core_EC_SM_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uint32_t x); + +static void Cy_Crypto_Core_EC_CS_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size); +static void Cy_Crypto_Core_EC_SM_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size); +static void Cy_Crypto_Core_EC_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size); /*************************************************************** @@ -91,7 +89,7 @@ const uint8_t P384_ShMul_COEFF[] = { * Function Name: Cy_Crypto_Core_EC_CS_MUL_Red_P192 ****************************************************************************//** * -* Curve-specific multiplication modular reduction for P192 +* Curve-specific multiplication modular reduction for P192. * 0 <= a, b < P192 * a5..a0 * b5..b0 % P192 = t11..t0 % P192 * P192 = 2^192-2^64-1 @@ -108,52 +106,52 @@ const uint8_t P384_ShMul_COEFF[] = { * * \param z * Product = a*b [2*192 bits]. -* +* * \param x -* Result = x mod P = a*b mod P [192 bits] +* Result = x mod P = a*b mod P [192 bits]. * *******************************************************************************/ -void Cy_Crypto_Core_EC_CS_MUL_Red_P192(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_CS_MUL_Red_P192(CRYPTO_Type *base, uint32_t z, uint32_t x) { - int sh = 0; - int t1 = 2; /* 128 */ - int t2 = 3; /* 192 */ - int my_z = 4; - int my_x = 5; + uint32_t sh = 0u; + uint32_t t1 = 2u; /* 128 */ + uint32_t t2 = 3u; /* 192 */ + uint32_t my_z = 4u; + uint32_t my_x = 5u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, t1, 128); - CY_CRYPTO_VU_ALLOC_MEM (base, t2, 192); + CY_CRYPTO_VU_ALLOC_MEM (base, t1, 128u); + CY_CRYPTO_VU_ALLOC_MEM (base, t2, 192u); - CY_CRYPTO_VU_SET_REG (base, sh, 192, 1); - CY_CRYPTO_VU_LSR (base, my_z, my_x, sh); /* t11..t6 */ + CY_CRYPTO_VU_SET_REG (base, sh, 192u, 1u); + CY_CRYPTO_VU_LSR (base, my_z, my_x, sh); /* t11..t6 */ - CY_CRYPTO_VU_SET_REG (base, sh, 128, 1); - CY_CRYPTO_VU_LSR (base, t1, my_z, sh); /* t11..t10 */ - CY_CRYPTO_VU_SET_REG (base, sh, 64, 1); - CY_CRYPTO_VU_LSL (base, t2, my_z, sh); /* t9..t6 * 2^64 */ + CY_CRYPTO_VU_SET_REG (base, sh, 128u, 1u); + CY_CRYPTO_VU_LSR (base, t1, my_z, sh); /* t11..t10 */ + CY_CRYPTO_VU_SET_REG (base, sh, 64u, 1u); + CY_CRYPTO_VU_LSL (base, t2, my_z, sh); /* t9..t6 * 2^64 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, my_x); /* t11..t6 + t5..t0 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, my_x); /* t11..t6 + t5..t0 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* t9..t6 * 2^64 + t11..t6 + t5..t0 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* t9..t6 * 2^64 + t11..t6 + t5..t0 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); - CY_CRYPTO_VU_LSL (base, t2, t1, sh); /* t11..t10 * 2^64 */ - CY_CRYPTO_VU_OR (base, t1, t1, t2); /* t11..t10 * 2^64 + t11..t10 */ + CY_CRYPTO_VU_LSL (base, t2, t1, sh); /* t11..t10 * 2^64 */ + CY_CRYPTO_VU_OR (base, t1, t1, t2); /* t11..t10 * 2^64 + t11..t10 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* t11..t10 * 2^64 + t11..t10 + t9..t6 * 2^64 + t11..t6 + t5..t0 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* t11..t10 * 2^64 + t11..t10 + t9..t6 * 2^64 + t11..t6 + t5..t0 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); - CY_CRYPTO_VU_FREE_MEM (base, (1 << t1) | (1 << t2)); + CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t1) | CY_CRYPTO_VU_REG_BIT(t2)); CY_CRYPTO_VU_POP_REG (base); } @@ -174,57 +172,57 @@ void Cy_Crypto_Core_EC_CS_MUL_Red_P192(CRYPTO_Type *base, int z, int x) * * \param z * Result = x mod P = a*b mod P [224 bits]. -* +* * \param x * Product = a*b [2*224 bits]. * *******************************************************************************/ -void Cy_Crypto_Core_EC_CS_MUL_Red_P224(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_CS_MUL_Red_P224(CRYPTO_Type *base, uint32_t z, uint32_t x) { - int sh = 0; - int t1 = 1; /* 224 */ - int t2 = 2; /* 224 */ - int t3 = 3; /* 224 */ - int my_z = 4; - int my_x = 5; + uint32_t sh = 0u; + uint32_t t1 = 1u; /* 224 */ + uint32_t t2 = 2u; /* 224 */ + uint32_t t3 = 3u; /* 224 */ + uint32_t my_z = 4u; + uint32_t my_x = 5u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, t1, CY_CRYPTO_ECC_P224_SIZE); /* 224 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t2, CY_CRYPTO_ECC_P224_SIZE); /* 224 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t3, CY_CRYPTO_ECC_P224_SIZE); /* 224 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t1, CY_CRYPTO_ECC_P224_SIZE); /* 224 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t2, CY_CRYPTO_ECC_P224_SIZE); /* 224 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t3, CY_CRYPTO_ECC_P224_SIZE); /* 224 */ - CY_CRYPTO_VU_SET_REG (base, sh, CY_CRYPTO_ECC_P224_SIZE, 1); /* sh = 224 */ - CY_CRYPTO_VU_LSR (base, my_z, my_x, sh); /* z = t13..t7 */ + CY_CRYPTO_VU_SET_REG (base, sh, CY_CRYPTO_ECC_P224_SIZE, 1u); /* sh = 224 */ + CY_CRYPTO_VU_LSR (base, my_z, my_x, sh); /* z = t13..t7 */ - CY_CRYPTO_VU_SET_REG (base, sh, 128, 1); - CY_CRYPTO_VU_LSR (base, t1, my_z, sh); /* t1 = t13..t11 */ + CY_CRYPTO_VU_SET_REG (base, sh, 128u, 1u); + CY_CRYPTO_VU_LSR (base, t1, my_z, sh); /* t1 = t13..t11 */ - CY_CRYPTO_VU_SET_REG (base, sh, 96, 1); - CY_CRYPTO_VU_LSL (base, t2, t1, sh); /* t2 = t13..t11*2^96 */ + CY_CRYPTO_VU_SET_REG (base, sh, 96u, 1u); + CY_CRYPTO_VU_LSL (base, t2, t1, sh); /* t2 = t13..t11*2^96 */ - CY_CRYPTO_VU_SET_REG (base, sh, 96, 1); - CY_CRYPTO_VU_LSL (base, t3, my_z, sh); /* t3 = t10..t7*2^96 */ + CY_CRYPTO_VU_SET_REG (base, sh, 96u, 1u); + CY_CRYPTO_VU_LSL (base, t3, my_z, sh); /* t3 = t10..t7*2^96 */ - CY_CRYPTO_VU_ADD (base, t2, t2, my_x); /* t2 = t13..t11*2^96 + t6..t0 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, t2, VR_P); /* C = (t2 >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, t2, t2, VR_P); /* t2 = t2 - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_ADD (base, t2, t2, my_x); /* t2 = t13..t11*2^96 + t6..t0 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, t2, VR_P); /* C = (t2 >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, t2, t2, VR_P); /* t2 = t2 - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_SUB (base, t2, t2, my_z); /* t2 = (t13..t11*2^96 + t6..t0) - t13..t7 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, t2, t2, VR_P); /* t2 = t2 + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_SUB (base, t2, t2, my_z); /* t2 = (t13..t11*2^96 + t6..t0) - t13..t7 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, t2, t2, VR_P); /* t2 = t2 + p, if C==0 (Carry is clear) */ - CY_CRYPTO_VU_SUB (base, t2, t2, t1); /* t2 = (t13..t11*2^96 + t6..t0 - t13..t7) - t13..t11 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, t2, t2, VR_P); /* t2 = t2 + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_SUB (base, t2, t2, t1); /* t2 = (t13..t11*2^96 + t6..t0 - t13..t7) - t13..t11 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, t2, t2, VR_P); /* t2 = t2 + p, if C==0 (Carry is clear) */ - CY_CRYPTO_VU_ADD (base, my_z, t2, t3); /* z = (t13..t11*2^96 + t6..t0 - t13..t7 - t13..t11) + t10..t7*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_ADD (base, my_z, t2, t3); /* z = (t13..t11*2^96 + t6..t0 - t13..t7 - t13..t11) + t10..t7*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_FREE_MEM (base, (1 << t1) | (1 << t2) | (1 << t3)); + CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t1) | CY_CRYPTO_VU_REG_BIT(t2) | CY_CRYPTO_VU_REG_BIT(t3)); CY_CRYPTO_VU_POP_REG (base); } @@ -247,172 +245,172 @@ void Cy_Crypto_Core_EC_CS_MUL_Red_P224(CRYPTO_Type *base, int z, int x) * * \param z * Result = x mod P = a*b mod P [256 bits]. -* +* * \param x * Product = a*b [2*256 bits]. * *******************************************************************************/ -void Cy_Crypto_Core_EC_CS_MUL_Red_P256(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_CS_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uint32_t x) { - int sh = 0; /* Variable values */ - int sh32 = 1; - int sh96 = 2; - int sh192 = 3; - int sh224 = 4; - int t0 = 5; /* 256 */ - int t1 = 6; /* 256 */ - int t2 = 7; /* 256 */ - int t3 = 8; /* 32 */ - int t4 = 9; /* 96 */ - int my_z = 10; - int my_x = 11; + uint32_t sh = 0u; /* Variable values */ + uint32_t sh32 = 1u; + uint32_t sh96 = 2u; + uint32_t sh192 = 3u; + uint32_t sh224 = 4u; + uint32_t t0 = 5u; /* 256 */ + uint32_t t1 = 6u; /* 256 */ + uint32_t t2 = 7u; /* 256 */ + uint32_t t3 = 8u; /* 32 */ + uint32_t t4 = 9u; /* 96 */ + uint32_t my_z = 10u; + uint32_t my_x = 11u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P256_SIZE); /* 256 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t1, CY_CRYPTO_ECC_P256_SIZE); /* 256 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t2, CY_CRYPTO_ECC_P256_SIZE); /* 256 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t3, 32); /* 32 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t4, 96); /* 96 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P256_SIZE); /* 256 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t1, CY_CRYPTO_ECC_P256_SIZE); /* 256 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t2, CY_CRYPTO_ECC_P256_SIZE); /* 256 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t3, 32u); /* 32 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t4, 96u); /* 96 */ - CY_CRYPTO_VU_SET_REG (base, sh, CY_CRYPTO_ECC_P256_SIZE, 1); /* sh = 256 */ - CY_CRYPTO_VU_SET_REG (base, sh32, 32, 1); /* sh = 32 */ - CY_CRYPTO_VU_SET_REG (base, sh96, 96, 1); /* sh = 96 */ - CY_CRYPTO_VU_SET_REG (base, sh192, 192, 1); /* sh = 192 */ - CY_CRYPTO_VU_SET_REG (base, sh224, 224, 1); /* sh = 224 */ + CY_CRYPTO_VU_SET_REG (base, sh, CY_CRYPTO_ECC_P256_SIZE, 1u); /* sh = 256 */ + CY_CRYPTO_VU_SET_REG (base, sh32, 32u, 1u); /* sh = 32 */ + CY_CRYPTO_VU_SET_REG (base, sh96, 96u, 1u); /* sh = 96 */ + CY_CRYPTO_VU_SET_REG (base, sh192, 192u, 1u); /* sh = 192 */ + CY_CRYPTO_VU_SET_REG (base, sh224, 224u, 1u); /* sh = 224 */ - CY_CRYPTO_VU_LSR (base, t0, my_x, sh); /* t0 = t15..t8 */ - CY_CRYPTO_VU_LSR (base, my_z, t0, sh96); /* z = t15..t11 */ - CY_CRYPTO_VU_LSR (base, t1, my_z, sh32); /* t1 = t15..t12 */ - CY_CRYPTO_VU_LSR (base, t3, my_z, sh32); /* t3 = t12 */ + CY_CRYPTO_VU_LSR (base, t0, my_x, sh); /* t0 = t15..t8 */ + CY_CRYPTO_VU_LSR (base, my_z, t0, sh96); /* z = t15..t11 */ + CY_CRYPTO_VU_LSR (base, t1, my_z, sh32); /* t1 = t15..t12 */ + CY_CRYPTO_VU_LSR (base, t3, my_z, sh32); /* t3 = t12 */ /* 2*S1 -- 2*t15..t11*2^96 */ - CY_CRYPTO_VU_LSL (base, my_z, my_z, sh96); /* z = t15..t11*2^96 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, my_z); /* z = 2*t15..t11*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, my_z, my_z, sh96); /* z = t15..t11*2^96 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, my_z); /* z = 2*t15..t11*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D3 (a) -- t12*2^224 */ - CY_CRYPTO_VU_LSL (base, t2, t3, sh224); /* t2 = t12*2^224 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t12*2^224 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSL (base, t2, t3, sh224); /* t2 = t12*2^224 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t12*2^224 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* 2*S2 -- 2*t15..t12*2^96 */ - CY_CRYPTO_VU_LSL (base, t2, t1, sh96); /* t2 = t15..t12*2^96 */ + CY_CRYPTO_VU_LSL (base, t2, t1, sh96); /* t2 = t15..t12*2^96 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t15..t12*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t15..t12*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + 2*t15..t12*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + 2*t15..t12*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D4 (c) -- t15..t14 */ - CY_CRYPTO_VU_LSR (base, t2, t0, sh192); /* t2 = t15..t14 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t15..t14 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t2, t0, sh192); /* t2 = t15..t14 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t15..t14 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S3 (a) -- t15..t14*2^192 */ - CY_CRYPTO_VU_LSL (base, t2, t2, sh192); /* t2 = t15..t14*2^192 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t15..t14*2^192 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t2, t2, sh192); /* t2 = t15..t14*2^192 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t15..t14*2^192 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D2 (c) -- t15..t12 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t15..t12 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t15..t12 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S4 (b) -- t13*2^192 */ - CY_CRYPTO_VU_LSR (base, t3, t1, sh32); /* t3 = t13 */ - CY_CRYPTO_VU_LSL (base, t2, t3, sh192); /* t2 = t13*2^192 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t13*2^192 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSR (base, t3, t1, sh32); /* t3 = t13 */ + CY_CRYPTO_VU_LSL (base, t2, t3, sh192); /* t2 = t13*2^192 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t13*2^192 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D4 (a) -- t13*2^224 */ - CY_CRYPTO_VU_LSL (base, t2, t2, sh32); /* t2 = t13*2^224 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t13*2^224 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSL (base, t2, t2, sh32); /* t2 = t13*2^224 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t13*2^224 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* D3 (c) -- t15..t13 */ - CY_CRYPTO_VU_LSR (base, t1, t1, sh32); /* t1 = t15..t13 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t15..t13 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t1, t1, sh32); /* t1 = t15..t13 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t15..t13 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S4 (c) -- t15..t13*2^96 */ - CY_CRYPTO_VU_LSL (base, t2, t1, sh96); /* t2 = t15..t13*2^96 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t15..t13*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t2, t1, sh96); /* t2 = t15..t13*2^96 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t15..t13*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D2 (a) -- t11*2^224 */ - CY_CRYPTO_VU_LSR (base, t3, t0, sh96); /* t3 = t11 */ - CY_CRYPTO_VU_LSL (base, t2, t3, sh224); /* t2 = t11*2^224 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t11*2^224 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t3, t0, sh96); /* t3 = t11 */ + CY_CRYPTO_VU_LSL (base, t2, t3, sh224); /* t2 = t11*2^224 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t11*2^224 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* D2 (b) -- t9*2^192 */ - CY_CRYPTO_VU_LSR (base, t3, t0, sh32); /* t3 = t9 */ - CY_CRYPTO_VU_LSL (base, t2, t3, sh192); /* t2 = t9*2^192 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t9*2^192 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t3, t0, sh32); /* t3 = t9 */ + CY_CRYPTO_VU_LSL (base, t2, t3, sh192); /* t2 = t9*2^192 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t9*2^192 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* D1 (c) -- t13..t11 */ - CY_CRYPTO_VU_LSR (base, t4, t0, sh96); /* t4 = t13..t11 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t4); /* z = z - t13..t11 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t4, t0, sh96); /* t4 = t13..t11 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t4); /* z = z - t13..t11 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S4 (d) -- t11..t9 */ - CY_CRYPTO_VU_LSR (base, t4, t0, sh32); /* t4 = t11..t9 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t4); /* z = z + t11..t9 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSR (base, t4, t0, sh32); /* t4 = t11..t9 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t4); /* z = z + t11..t9 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D1 (a) -- t10*2^224 */ - CY_CRYPTO_VU_LSR (base, t3, t4, sh32); /* t3 = t10 */ - CY_CRYPTO_VU_LSL (base, t2, t3, sh224); /* t2 = t10*2^224 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t10*2^224 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t3, t4, sh32); /* t3 = t10 */ + CY_CRYPTO_VU_LSL (base, t2, t3, sh224); /* t2 = t10*2^224 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t10*2^224 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* D4 (b) -- t11..t9*2^96 */ - CY_CRYPTO_VU_LSL (base, t2, t4, sh96); /* t2 = t11..t9*2^96 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t11..t9*2^96 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSL (base, t2, t4, sh96); /* t2 = t11..t9*2^96 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t11..t9*2^96 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ - CY_CRYPTO_VU_SET_REG (base, sh, 0, 1); /* sh = 0; */ + CY_CRYPTO_VU_SET_REG (base, sh, 0u, 1u); /* sh = 0; */ /* S3 (b) -- t10..t8 */ - CY_CRYPTO_VU_LSR (base, t4, t0, sh); /* t4 = t10..t8 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t4); /* z = z + t10..t8 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSR (base, t4, t0, sh); /* t4 = t10..t8 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t4); /* z = z + t10..t8 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D3 (b) -- t10..t8*2^96 */ - CY_CRYPTO_VU_LSL (base, t2, t4, sh96); /* t4 = t10..t8*2^96 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t10..t8*2^96 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSL (base, t2, t4, sh96); /* t4 = t10..t8*2^96 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t10..t8*2^96 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S4 (a) -- t8*2^224 */ - CY_CRYPTO_VU_LSL (base, t2, t0, sh224); /* t2 = t8*2^224 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t8*2^224 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t2, t0, sh224); /* t2 = t8*2^224 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t8*2^224 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D1 (b) -- t8*2^192 */ - CY_CRYPTO_VU_LSR (base, t2, t2, sh32); /* t2 = t8*2^192 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t8*2^192 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t2, t2, sh32); /* t2 = t8*2^192 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t8*2^192 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* T -- t7..t0 */ - CY_CRYPTO_VU_LSR (base, t2, my_x, sh); /* t2 = t8*2^192 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t7..t0 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSR (base, t2, my_x, sh); /* t2 = t8*2^192 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t7..t0 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t0) | CY_CRYPTO_VU_REG_BIT(t1) | @@ -438,132 +436,132 @@ void Cy_Crypto_Core_EC_CS_MUL_Red_P256(CRYPTO_Type *base, int z, int x) * * \param z * Result = x mod P = a*b mod P [384 bits] -* +* * \param x * Product = a*b [2*384 bits] * *******************************************************************************/ -void Cy_Crypto_Core_EC_CS_MUL_Red_P384(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_CS_MUL_Red_P384(CRYPTO_Type *base, uint32_t z, uint32_t x) { - int sh32 = 0; - int sh64 = 1; - int sh96 = 2; - int sh128 = 3; - int sh256 = 4; - int sh384 = 5; - int t0 = 6; /* 384 */ - int t1 = 7; /* 384 */ - int t2 = 8; /* 32 */ - int my_z = 9; - int my_x = 10; + uint32_t sh32 = 0u; + uint32_t sh64 = 1u; + uint32_t sh96 = 2u; + uint32_t sh128 = 3u; + uint32_t sh256 = 4u; + uint32_t sh384 = 5u; + uint32_t t0 = 6u; /* 384 */ + uint32_t t1 = 7u; /* 384 */ + uint32_t t2 = 8u; /* 32 */ + uint32_t my_z = 9u; + uint32_t my_x = 10u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P384_SIZE); /* 384 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t1, CY_CRYPTO_ECC_P384_SIZE); /* 384 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t2, 32); /* 32 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P384_SIZE); /* 384 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t1, CY_CRYPTO_ECC_P384_SIZE); /* 384 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t2, 32u); /* 32 */ - CY_CRYPTO_VU_SET_REG (base, sh32, 32, 1); /* sh32 = 32 */ - CY_CRYPTO_VU_SET_REG (base, sh64, 64, 1); /* sh64 = 64 */ - CY_CRYPTO_VU_SET_REG (base, sh96, 96, 1); /* sh96 = 96 */ - CY_CRYPTO_VU_SET_REG (base, sh128, 128, 1); /* sh128 = 128 */ - CY_CRYPTO_VU_SET_REG (base, sh256, 256, 1); /* sh256 = 256 */ - CY_CRYPTO_VU_SET_REG (base, sh384, CY_CRYPTO_ECC_P384_SIZE, 1); /* sh384 = 384 */ + CY_CRYPTO_VU_SET_REG (base, sh32, 32u, 1u); /* sh32 = 32 */ + CY_CRYPTO_VU_SET_REG (base, sh64, 64u, 1u); /* sh64 = 64 */ + CY_CRYPTO_VU_SET_REG (base, sh96, 96u, 1u); /* sh96 = 96 */ + CY_CRYPTO_VU_SET_REG (base, sh128, 128u, 1u); /* sh128 = 128 */ + CY_CRYPTO_VU_SET_REG (base, sh256, 256u, 1u); /* sh256 = 256 */ + CY_CRYPTO_VU_SET_REG (base, sh384, CY_CRYPTO_ECC_P384_SIZE, 1u); /* sh384 = 384 */ - CY_CRYPTO_VU_LSR (base, t0, my_x, sh384); /* t0 = t23..t12 */ + CY_CRYPTO_VU_LSR (base, t0, my_x, sh384); /* t0 = t23..t12 */ /* T + S2 -- t11..t0 + t23..t12 */ - CY_CRYPTO_VU_ADD (base, my_z, t0, my_x); /* z = t23..t12 + t11..t0 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_ADD (base, my_z, t0, my_x); /* z = t23..t12 + t11..t0 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* S6 (b) -- t_20 */ - CY_CRYPTO_VU_LSR (base, t2, t0, sh256); /* t2 = t20 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t20 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSR (base, t2, t0, sh256); /* t2 = t20 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t2); /* z = z + t20 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* S4 (b) -- t20*2^96 */ - CY_CRYPTO_VU_LSL (base, t1, t2, sh96); /* t1 = t20*2^96 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t20*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t1, t2, sh96); /* t1 = t20*2^96 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t20*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* S5 -- t23..t20*2^128 */ - CY_CRYPTO_VU_LSR (base, t1, t0, sh256); /* t1 = t23..t20 */ - CY_CRYPTO_VU_LSL (base, t1, t1, sh128); /* t1 = t23..t20*2^128 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t20*2^128 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSR (base, t1, t0, sh256); /* t1 = t23..t20 */ + CY_CRYPTO_VU_LSL (base, t1, t1, sh128); /* t1 = t23..t20*2^128 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t20*2^128 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D2 -- t23..t20*2^32 */ - CY_CRYPTO_VU_LSR (base, t1, t1, sh96); /* t1 = t23..t20*2^32 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t23..t20*2^32 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t1, t1, sh96); /* t1 = t23..t20*2^32 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t23..t20*2^32 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S3 (b) -- t23..t21 */ - CY_CRYPTO_VU_LSR (base, t1, t1, sh64); /* t1 = t23..t21 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t21 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSR (base, t1, t1, sh64); /* t1 = t23..t21 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t21 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D1 (b) -- t23 */ - CY_CRYPTO_VU_LSR (base, t2, t1, sh64); /* t2 = t23 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t23 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSR (base, t2, t1, sh64); /* t2 = t23 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t2); /* z = z - t23 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S6 (a) -- t23..t21*2^96 */ - CY_CRYPTO_VU_LSL (base, t1, t1, sh96); /* t1 = t23..t21*2^96 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t21*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t1, t1, sh96); /* t1 = t23..t21*2^96 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t21*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* 2*S1 -- 2*t23..t21*2^128 */ - CY_CRYPTO_VU_LSL (base, t1, t1, sh32); /* t1 = t23..t21*2^128 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t21*2^128 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t20..t12*2^128 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t1, t1, sh32); /* t1 = t23..t21*2^128 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23..t21*2^128 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t20..t12*2^128 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* S4 (c) -- t23*2^32 */ - CY_CRYPTO_VU_LSL (base, t1, t2, sh32); /* t1 = t23*2^32 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23*2^32 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t1, t2, sh32); /* t1 = t23*2^32 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t23*2^32 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* D3 (b) -- t23*2^96 */ - CY_CRYPTO_VU_LSL (base, t1, t1, sh64); /* t1 = t23*2^96 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t23*2^96 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSL (base, t1, t1, sh64); /* t1 = t23*2^96 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t23*2^96 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* D3 (a) -- t23*2^128 */ - CY_CRYPTO_VU_LSL (base, t1, t1, sh32); /* t1 = t23*2^128 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t23*2^128 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSL (base, t1, t1, sh32); /* t1 = t23*2^128 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t23*2^128 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* D1 (a) -- t22..t12*2^32 */ - CY_CRYPTO_VU_LSL (base, t1, t0, sh32); /* t1 = t22..t12*2^32 */ - CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t22..t12*2^32 */ - CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ + CY_CRYPTO_VU_LSL (base, t1, t0, sh32); /* t1 = t22..t12*2^32 */ + CY_CRYPTO_VU_SUB (base, my_z, my_z, t1); /* z = z - t22..t12*2^32 */ + CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, my_z, my_z, VR_P); /* z = z + p, if C==0 (Carry is clear) */ /* S3 (a) -- t20..t12*2^96 */ - CY_CRYPTO_VU_LSL (base, t1, t1, sh64); /* t1 = t20..t12*2^96 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t20..t12*2^96 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t1, t1, sh64); /* t1 = t20..t12*2^96 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t20..t12*2^96 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ /* S4 (a) -- t19..t12*2^128 */ - CY_CRYPTO_VU_LSL (base, t1, t1, sh32); /* t1 = t19..t12*2^128 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t19..t12*2^128 */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_LSL (base, t1, t1, sh32); /* t1 = t19..t12*2^128 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, t1); /* z = z + t19..t12*2^128 */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* z = z - p, if C==1 (Carry is set) */ - CY_CRYPTO_VU_FREE_MEM (base, (1 << t0) | (1 << t1) | (1 << t2)); + CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t0) | CY_CRYPTO_VU_REG_BIT(t1) | CY_CRYPTO_VU_REG_BIT(t2)); CY_CRYPTO_VU_POP_REG (base); } @@ -585,34 +583,34 @@ void Cy_Crypto_Core_EC_CS_MUL_Red_P384(CRYPTO_Type *base, int z, int x) * * \param z * Result = x mod P = a*b mod P [521 bits] -* +* * \param x * Product = a*b [2*521 bits] * *******************************************************************************/ -void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uint32_t x) { - int sh521 = 0; - int t0 = 1; - int my_z = 2; - int my_x = 3; + uint32_t sh521 = 0u; + uint32_t t0 = 1u; + uint32_t my_z = 2u; + uint32_t my_x = 3u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P521_SIZE); /* 521 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P521_SIZE); /* 521 */ - CY_CRYPTO_VU_SET_REG (base, sh521, 521, 1); /* sh521 = 521 */ + CY_CRYPTO_VU_SET_REG (base, sh521, 521u, 1u); /* sh521 = 521 */ - CY_CRYPTO_VU_LSR (base, my_z, my_x, sh521); /* z = T1 */ + CY_CRYPTO_VU_LSR (base, my_z, my_x, sh521); /* z = T1 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, my_x); /* z = T1 + T0 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, my_x); /* z = T1 + T0 */ /* T0 + T1 mod p */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (t2 >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* t2 = t2 - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (t2 >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* t2 = t2 - p, if C==1 (Carry is set) */ CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t0)); @@ -630,7 +628,7 @@ void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, int z, int x) * * \param z * Result. -* +* * \param x * Product. * @@ -638,7 +636,7 @@ void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, int z, int x) * Size. * *******************************************************************************/ -void Cy_Crypto_Core_EC_CS_MulRed(CRYPTO_Type *base, int z, int x, int size) +static void Cy_Crypto_Core_EC_CS_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size) { switch (eccMode) { @@ -680,57 +678,57 @@ void Cy_Crypto_Core_EC_CS_MulRed(CRYPTO_Type *base, int z, int x, int size) * * \param z * Result = x mod P = a*b mod P [192 bits]. -* +* * \param x * Product = a*b [2*192 bits]. * *******************************************************************************/ -void Cy_Crypto_Core_EC_SM_MUL_Red_P192(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_SM_MUL_Red_P192(CRYPTO_Type *base, uint32_t z, uint32_t x) { /* Setup */ - int partial = 0; - int hi = 1; - int sh64 = 2; - int sh192 = 3; - int my_z = 4; - int my_x = 5; + uint32_t partial = 0u; + uint32_t hi = 1u; + uint32_t sh64 = 2u; + uint32_t sh192 = 3u; + uint32_t my_z = 4u; + uint32_t my_x = 5u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P192_SIZE + 65); - CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P192_SIZE + 64); + CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P192_SIZE + 65u); + CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P192_SIZE + 64u); - CY_CRYPTO_VU_SET_REG (base, sh64, 64, 1); - CY_CRYPTO_VU_SET_REG (base, sh192, 192, 1); + CY_CRYPTO_VU_SET_REG (base, sh64, 64u, 1u); + CY_CRYPTO_VU_SET_REG (base, sh192, 192u, 1u); /* Step 2: 1st round of shift-multiply - * (Separate hi and lo (LSR hi>>CURVE_SIZE), multiply hi (LSL hi and add 1) and add shifted hi to lo) - * hi*(2^{64} + 1) + lo - */ - CY_CRYPTO_VU_LSR (base, hi, my_x, sh192); /* hi = prod >> CURVE_SIZE = prod[383:192] */ - CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[191:0] */ + * (Separate hi and lo (LSR hi>>CURVE_SIZE), multiply hi (LSL hi and add 1) and add shifted hi to lo) + * hi * (2^{64} + 1) + lo + */ + CY_CRYPTO_VU_LSR (base, hi, my_x, sh192); /* hi = prod >> CURVE_SIZE = prod[383:192] */ + CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[191:0] */ - CY_CRYPTO_VU_ADD (base, partial, hi, my_z); /* partial = (hi*1) + lo */ + CY_CRYPTO_VU_ADD (base, partial, hi, my_z); /* partial = (hi*1) + lo */ - CY_CRYPTO_VU_LSL (base, hi, hi, sh64); /* hi = hi << 64 = hi*2^{64} */ + CY_CRYPTO_VU_LSL (base, hi, hi, sh64); /* hi = hi << 64 = hi*2^{64} */ - CY_CRYPTO_VU_ADD (base, partial, partial, hi); /* partial = hi*(2^{64}+1) + lo */ + CY_CRYPTO_VU_ADD (base, partial, partial, hi); /* partial = hi*(2^{64}+1) + lo */ /* Step 3: 2nd round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh192); /* hi = partial >> CURVE_SIZE = partial[383:192] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh192); /* hi = partial >> CURVE_SIZE = partial[383:192] */ - CY_CRYPTO_VU_ADD (base, my_z, hi, partial); /* z = (hi*1) + lo (Note: partial == lo, since it will be cut to CURVE_SIZE since z = CURVE_SIZE) */ + CY_CRYPTO_VU_ADD (base, my_z, hi, partial); /* z = (hi*1) + lo (Note: partial == lo, since it will be cut to CURVE_SIZE since z = CURVE_SIZE) */ - CY_CRYPTO_VU_LSL (base, hi, hi, sh64); /* hi = hi << 64 = hi*2^{64} */ + CY_CRYPTO_VU_LSL (base, hi, hi, sh64); /* hi = hi << 64 = hi*2^{64} */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, hi); /* z = hi*(2^{64}+1) + lo */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, hi); /* z = hi*(2^{64}+1) + lo */ /* Step 4: Final reduction (compare to P-192 and reduce if necessary, based on CARRY flag) */ - CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(partial) | CY_CRYPTO_VU_REG_BIT(hi)); @@ -750,57 +748,57 @@ void Cy_Crypto_Core_EC_SM_MUL_Red_P192(CRYPTO_Type *base, int z, int x) * * \param z * Result = x mod P = a*b mod P [224 bits]. -* +* * \param x * Product = a*b [2*224 bits]. * *******************************************************************************/ -void Cy_Crypto_Core_EC_SM_MUL_Red_P224(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_SM_MUL_Red_P224(CRYPTO_Type *base, uint32_t z, uint32_t x) { /* Setup */ - int partial = 0; - int hi = 1; - int sh96 = 2; - int sh224 = 3; - int my_z = 4; - int my_x = 5; + uint32_t partial = 0u; + uint32_t hi = 1u; + uint32_t sh96 = 2u; + uint32_t sh224 = 3u; + uint32_t my_z = 4u; + uint32_t my_x = 5u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P224_SIZE + 97); - CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P224_SIZE + 96); + CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P224_SIZE + 97u); + CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P224_SIZE + 96u); - CY_CRYPTO_VU_SET_REG (base, sh96, 96, 1); - CY_CRYPTO_VU_SET_REG (base, sh224, 224, 1); + CY_CRYPTO_VU_SET_REG (base, sh96, 96u, 1u); + CY_CRYPTO_VU_SET_REG (base, sh224, 224u, 1u); /* Step 2: 1st round of shift-multiply - * (Separate hi and lo (LSR hi>>CURVE_SIZE), multiply hi (LSL hi<<96 and subtract 1) and add shifted hi to lo) - * hi*(2^{96} + 1) + lo - */ - CY_CRYPTO_VU_LSR (base, hi, my_x, sh224); /* hi = prod >> CURVE_SIZE = prod[447:224] */ - CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[223:0] */ + * (Separate hi and lo (LSR hi>>CURVE_SIZE), multiply hi (LSL hi<<96 and subtract 1) and add shifted hi to lo) + * hi * (2^{96} + 1) + lo + */ + CY_CRYPTO_VU_LSR (base, hi, my_x, sh224); /* hi = prod >> CURVE_SIZE = prod[447:224] */ + CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[223:0] */ - CY_CRYPTO_VU_SUB (base, partial, my_z, hi); /* partial = lo - (hi*1) */ + CY_CRYPTO_VU_SUB (base, partial, my_z, hi); /* partial = lo - (hi*1) */ - CY_CRYPTO_VU_LSL (base, hi, hi, sh96); /* hi = hi << 96 = hi*2^{96} */ + CY_CRYPTO_VU_LSL (base, hi, hi, sh96); /* hi = hi << 96 = hi*2^{96} */ - CY_CRYPTO_VU_ADD (base, partial, partial, hi); /* partial = hi*(2^{96}-1) + lo */ + CY_CRYPTO_VU_ADD (base, partial, partial, hi); /* partial = hi*(2^{96}-1) + lo */ /* Step 3: 2nd round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh224); /* hi = partial>>CURVE_SIZE = partial[447:224] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh224); /* hi = partial>>CURVE_SIZE = partial[447:224] */ - CY_CRYPTO_VU_SUB (base, my_z, partial, hi); /* z = lo - (hi*1) (Note: partial == lo, since it will be cut to CURVE_SIZE since z = CURVE_SIZE) */ + CY_CRYPTO_VU_SUB (base, my_z, partial, hi); /* z = lo - (hi*1) (Note: partial == lo, since it will be cut to CURVE_SIZE since z = CURVE_SIZE) */ - CY_CRYPTO_VU_LSL (base, hi, hi, sh96); /* hi = hi<<96 = hi*2^{96} */ + CY_CRYPTO_VU_LSL (base, hi, hi, sh96); /* hi = hi<<96 = hi*2^{96} */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, hi); /* z = hi*(2^{96}-1) + lo */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, hi); /* z = hi*(2^{96}-1) + lo */ /* Step 4: Final reduction (compare to P-224 and reduce if necessary, based on CARRY flag) */ - CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(partial) | CY_CRYPTO_VU_REG_BIT(hi)); @@ -808,61 +806,6 @@ void Cy_Crypto_Core_EC_SM_MUL_Red_P224(CRYPTO_Type *base, int z, int x) } -/******************************************************************************* -* Function Name: Cy_Crypto_Core_EC_P256_ShMulRed_Coeff -****************************************************************************//** -* -* Generate multiplier for shift-multiply multiplication reduction P256. -* Multiplier coeficient = (2^{224} - 2^{192} - 2^{96} + 1) -* Multiplier coefficient = fffffffe ffffffff ffffffff ffffffff 00000000 00000000 00000001 -* -* \param base -* The pointer to a Crypto instance. -* -* \param z -* Result = x mod P = a*b mod P [224 bits]. -* -* \param x -* Product = a*b [2*224 bits]. -* -* \note Complicated swapping of t and coeff registers is to ensure coeff only -* requires 224 bits, while t requires 225 bits. Hence, the externally used -* register coeff requires one less bit. -* -*******************************************************************************/ -void Cy_Crypto_Core_EC_P256_ShMulRed_Coeff(CRYPTO_Type *base, int coeff) -{ - int sh = 0; - int t = 1; - int my_coeff = 2; - - CY_CRYPTO_VU_PUSH_REG (base); - - CY_CRYPTO_VU_LD_REG (base, my_coeff, coeff); - - CY_CRYPTO_VU_SET_REG (base, sh, 224, 1u); /* sh = 224 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t, 225u); /* t [225 bits] */ - - CY_CRYPTO_VU_SET_TO_ONE (base, t); /* t = 1 */ - CY_CRYPTO_VU_LSL (base, t, t, sh); /* t = 1<<224 */ - - CY_CRYPTO_VU_SET_REG (base, sh, 32, 1u); /* sh = 32 */ - CY_CRYPTO_VU_LSR (base, my_coeff, t, sh); /* coeff = 1<<192 */ - CY_CRYPTO_VU_SUB (base, t, t, my_coeff); /* t = 1<<224 - 1<<192 */ - - CY_CRYPTO_VU_SET_REG (base, sh, 96, 1u); /* sh = 96 */ - CY_CRYPTO_VU_LSR (base, my_coeff, my_coeff, sh); /* coeff = 1<<96 */ - CY_CRYPTO_VU_SUB (base, t, t, my_coeff); /* t = 1<<224 - 1<<192 - 1<<96 */ - - CY_CRYPTO_VU_LSR (base, my_coeff, my_coeff, sh); /* coeff = 1 */ - CY_CRYPTO_VU_ADD (base, my_coeff, my_coeff, t); /* coeff = 1<<224 - 1<<192 - 1<<96 + 1 */ - - CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t)); - CY_CRYPTO_VU_POP_REG (base); - -} - - /******************************************************************************* * Function Name: Cy_Crypto_Core_EC_SM_MUL_Red_P256 ****************************************************************************//** @@ -876,97 +819,103 @@ void Cy_Crypto_Core_EC_P256_ShMulRed_Coeff(CRYPTO_Type *base, int coeff) * * \param z * Result. -* +* * \param x * Product. * *******************************************************************************/ -void Cy_Crypto_Core_EC_SM_MUL_Red_P256(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_SM_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uint32_t x) { + /* Pre-computed coefficient for shift-multiply modular reduction for P256 */ + const uint8_t P256_ShMul_COEFF[] = { + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu + }; + /* Setup */ - int partial = 0; - int hi = 1; - int sh256 = 2; - int my_z = 3; - int my_x = 4; - int coeff = 5; + uint32_t partial = 0u; + uint32_t hi = 1u; + uint32_t sh256 = 2u; + uint32_t my_z = 3u; + uint32_t my_x = 4u; + uint32_t coeff = 5u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, coeff, 224u); - CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P256_SIZE + 224u); - CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P256_SIZE); + CY_CRYPTO_VU_ALLOC_MEM (base, coeff, 224u); + CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P256_SIZE + 224u); + CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P256_SIZE); - CY_CRYPTO_VU_SET_REG (base, sh256, 256, 1u); + CY_CRYPTO_VU_SET_REG (base, sh256, 256u, 1u); - /* Cy_Crypto_Core_EC_P256_ShMulRed_Coeff(coeff); */ - Cy_Crypto_Core_Vu_SetMemValue (base, coeff, P256_ShMul_COEFF, 224u); + Cy_Crypto_Core_Vu_SetMemValue (base, coeff, P256_ShMul_COEFF, 224u); /* Step 2: 1st round of shift-multiply - * (Separate hi and lo (LSR hi>>CURVE_SIZE), multiply hi*c and add hi*coeff + lo) - * hi*coeff + lo - */ - CY_CRYPTO_VU_LSR (base, hi, my_x, sh256); /* hi = prod >> CURVE_SIZE = prod[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[255:0] */ + * (Separate hi and lo (LSR hi>>CURVE_SIZE), multiply hi*c and add hi*coeff + lo) + * hi*coeff + lo + */ + CY_CRYPTO_VU_LSR (base, hi, my_x, sh256); /* hi = prod >> CURVE_SIZE = prod[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* partial = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* partial = hi*coeff + lo */ /* Step 3: 2nd round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ /* Step 4: 3rd round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ /* Step 5: 4th round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ /* Step 6: 5th round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ /* Step 7: 6th round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ /* Step 8: 7th round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* z = hi*coeff + lo */ /* Step 9: 8th round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh256); /* hi = partial>>CURVE_SIZE = partial[511:256] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[255:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, my_z, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, my_z, partial, my_z); /* z = hi*coeff + lo */ /* Step 11: Final reduction (compare to P-256 and reduce if necessary, based on CARRY flag) */ - CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(partial) | CY_CRYPTO_VU_REG_BIT(hi) | CY_CRYPTO_VU_REG_BIT(coeff)); @@ -974,55 +923,6 @@ void Cy_Crypto_Core_EC_SM_MUL_Red_P256(CRYPTO_Type *base, int z, int x) } -/******************************************************************************* -* Function Name: Cy_Crypto_Core_EC_P384_ShMulRed_Coeff -****************************************************************************//** -* -* Generate multiplier for shift-multiply multiplication reduction P384. -* Multiplier coeficient = (2^{128} + 2^{96} - 2^{32} + 1) -* Multiplier coefficient = 1 00000000 FFFFFFFF FFFFFFFF 00000000 -* -* \param base -* The pointer to a Crypto instance. -* -* \param coeff -* Coeffitient. -* -*******************************************************************************/ -void Cy_Crypto_Core_EC_P384_ShMulRed_Coeff(CRYPTO_Type *base, int coeff) -{ - - int sh = 0; - int t = 1; - int my_coeff = 2; - - CY_CRYPTO_VU_PUSH_REG (base); - - CY_CRYPTO_VU_LD_REG (base, my_coeff, coeff); - - CY_CRYPTO_VU_SET_REG (base, sh, 128, 1); /* sh = 128 */ - CY_CRYPTO_VU_ALLOC_MEM (base, t, 97); /* t [96 bits] */ - - CY_CRYPTO_VU_SET_TO_ONE (base, my_coeff); /* coeff = 1 */ - CY_CRYPTO_VU_LSL (base, my_coeff, my_coeff, sh); /* coeff = 1<<128 */ - - CY_CRYPTO_VU_SET_REG (base, sh, 32, 1); /* sh = 32 */ - CY_CRYPTO_VU_LSR (base, t, my_coeff, sh); /* t = 1<<96 */ - CY_CRYPTO_VU_ADD (base, my_coeff, my_coeff, t); /* coeff = 1<<128 + 1<<96 */ - - CY_CRYPTO_VU_SET_REG (base, sh, 64, 1); /* sh = 64 */ - CY_CRYPTO_VU_LSR (base, t, t, sh); /* t = 1<<32 */ - CY_CRYPTO_VU_SUB (base, my_coeff, my_coeff, t); /* coeff = 1<<128 + 1<<96 - 1<<32 */ - - CY_CRYPTO_VU_SET_REG (base, sh, 32, 1); /* sh = 32 */ - CY_CRYPTO_VU_LSR (base, t, t, sh); /* t = 1 */ - CY_CRYPTO_VU_ADD (base, my_coeff, my_coeff, t); /* coeff = 1<<128 + 1<<96 - 1<<32 + 1 */ - - CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t)); - CY_CRYPTO_VU_POP_REG (base); -} - - /******************************************************************************* * Function Name: Cy_Crypto_Core_EC_SM_MUL_Red_P384 ****************************************************************************//** @@ -1036,55 +936,62 @@ void Cy_Crypto_Core_EC_P384_ShMulRed_Coeff(CRYPTO_Type *base, int coeff) * * \param z * Result. -* +* * \param x * Product. * *******************************************************************************/ -void Cy_Crypto_Core_EC_SM_MUL_Red_P384(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_SM_MUL_Red_P384(CRYPTO_Type *base, uint32_t z, uint32_t x) { + /* Pre-computed coefficient for shift-multiply modular reduction for P384 */ + const uint8_t P384_ShMul_COEFF[] = { + 0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u + }; + /* Setup */ - int partial = 0; - int hi = 1; - int sh96 = 2; - int sh384 = 3; - int my_z = 4; - int my_x = 5; - int coeff = 6; + uint32_t partial = 0u; + uint32_t hi = 1u; + uint32_t sh96 = 2u; + uint32_t sh384 = 3u; + uint32_t my_z = 4u; + uint32_t my_x = 5u; + uint32_t coeff = 6u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P384_SIZE + 129u); - CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P384_SIZE + 96u); - CY_CRYPTO_VU_ALLOC_MEM (base, coeff, 129u); + CY_CRYPTO_VU_ALLOC_MEM (base, partial, CY_CRYPTO_ECC_P384_SIZE + 129u); + CY_CRYPTO_VU_ALLOC_MEM (base, hi, CY_CRYPTO_ECC_P384_SIZE + 96u); + CY_CRYPTO_VU_ALLOC_MEM (base, coeff, 129u); - CY_CRYPTO_VU_SET_REG (base, sh96, 96, 1u); - CY_CRYPTO_VU_SET_REG (base, sh384, 384, 1u); + CY_CRYPTO_VU_SET_REG (base, sh96, 96u, 1u); + CY_CRYPTO_VU_SET_REG (base, sh384, 384u, 1u); - Cy_Crypto_Core_Vu_SetMemValue (base, coeff, P384_ShMul_COEFF, 129u); + Cy_Crypto_Core_Vu_SetMemValue (base, coeff, P384_ShMul_COEFF, 129u); /* Step 2: 1st round of shift-multiply * (Separate hi and lo (LSR hi>>CURVE_SIZE), multiply hi*c and add hi*coeff + lo) * hi*coeff + lo */ - CY_CRYPTO_VU_LSR (base, hi, my_x, sh384); /* hi = prod >> CURVE_SIZE = prod[767:384] */ - CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[383:0] */ + CY_CRYPTO_VU_LSR (base, hi, my_x, sh384); /* hi = prod >> CURVE_SIZE = prod[767:384] */ + CY_CRYPTO_VU_MOV (base, my_z, my_x); /* z == lo = prod[383:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* partial = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, partial, partial, my_z); /* partial = hi*coeff + lo */ /* Step 3: 2nd round of shift-multiply */ - CY_CRYPTO_VU_LSR (base, hi, partial, sh384); /* hi = partial>>CURVE_SIZE = partial[767:384] */ - CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[383:0] */ + CY_CRYPTO_VU_LSR (base, hi, partial, sh384); /* hi = partial>>CURVE_SIZE = partial[767:384] */ + CY_CRYPTO_VU_MOV (base, my_z, partial); /* z == lo = partial[383:0] */ - CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ - CY_CRYPTO_VU_ADD (base, my_z, partial, my_z); /* z = hi*coeff + lo */ + CY_CRYPTO_VU_UMUL (base, partial, hi, coeff); /* partial = hi*coeff */ + CY_CRYPTO_VU_ADD (base, my_z, partial, my_z); /* z = hi*coeff + lo */ /* Step 4: Final reduction (compare to P-384 and reduce if necessary, based on CARRY flag) */ - CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ + CY_CRYPTO_VU_CMP_SUB (base, my_z, VR_P); /* C = (z >= VR_P) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(partial) | CY_CRYPTO_VU_REG_BIT(hi) | CY_CRYPTO_VU_REG_BIT(coeff)); @@ -1109,34 +1016,34 @@ void Cy_Crypto_Core_EC_SM_MUL_Red_P384(CRYPTO_Type *base, int z, int x) * * \param z * Result = x mod P = a*b mod P [521 bits]. -* +* * \param x * Product = a*b [2*521 bits]. * *******************************************************************************/ -void Cy_Crypto_Core_EC_SM_MUL_Red_P521(CRYPTO_Type *base, int z, int x) +static void Cy_Crypto_Core_EC_SM_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uint32_t x) { - int sh521 = 0; - int t0 = 1; - int my_z = 2; - int my_x = 3; + uint32_t sh521 = 0u; + uint32_t t0 = 1u; + uint32_t my_z = 2u; + uint32_t my_x = 3u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, my_x, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, my_x, x); - CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P521_SIZE); /* 521 */ + CY_CRYPTO_VU_ALLOC_MEM (base, t0, CY_CRYPTO_ECC_P521_SIZE); /* 521 */ - CY_CRYPTO_VU_SET_REG (base, sh521, 521, 1); /* sh521 = 521 */ + CY_CRYPTO_VU_SET_REG (base, sh521, 521u, 1u); /* sh521 = 521 */ - CY_CRYPTO_VU_LSR (base, my_z, my_x, sh521); /* z = T1 */ + CY_CRYPTO_VU_LSR (base, my_z, my_x, sh521); /* z = T1 */ - CY_CRYPTO_VU_ADD (base, my_z, my_z, my_x); /* z = T1 + T0 */ + CY_CRYPTO_VU_ADD (base, my_z, my_z, my_x); /* z = T1 + T0 */ /* T0 + T1 mod p */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (t2 >= VR_P) */ - CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* t2 = t2 - p, if C==1 (Carry is set) */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, my_z, VR_P); /* C = (t2 >= VR_P) */ + CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, my_z, my_z, VR_P); /* t2 = t2 - p, if C==1 (Carry is set) */ CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t0)); CY_CRYPTO_VU_POP_REG (base); @@ -1148,14 +1055,14 @@ void Cy_Crypto_Core_EC_SM_MUL_Red_P521(CRYPTO_Type *base, int z, int x) * Function Name: Cy_Crypto_Core_EC_SM_MulRed ****************************************************************************//** * -* +* * * \param base * The pointer to a Crypto instance. * * \param z * Result. -* +* * \param x * Product. * @@ -1163,7 +1070,7 @@ void Cy_Crypto_Core_EC_SM_MUL_Red_P521(CRYPTO_Type *base, int z, int x) * Size. * *******************************************************************************/ -void Cy_Crypto_Core_EC_SM_MulRed(CRYPTO_Type *base, int z, int x, int size) +static void Cy_Crypto_Core_EC_SM_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size) { switch (eccMode) { case CY_CRYPTO_ECC_ECP_SECP192R1: @@ -1198,14 +1105,14 @@ void Cy_Crypto_Core_EC_SM_MulRed(CRYPTO_Type *base, int z, int x, int size) * * Curve-specific multiplication modular reduction for P224. * t[b-1:0] = z_double >> size -* t = t * VR_BARRETT -* t = t + ((z_double >> size) << size) - for leading '1' Barrett bit. -* t = t >> size -* t = t * mod - r2 (not reduced) -* u = z_double - t - r = r1 - r2 (not reduced) +* t = t * VR_BARRETT +* t = t + ((z_double >> size) << size) - for leading '1' Barrett bit. +* t = t >> size +* t = t * mod - r2 (not reduced) +* u = z_double - t - r = r1 - r2 (not reduced) * -* u = IF (u >= mod) u = u - mod - reduce r using mod -* u = IF (u >= mod) u = u - mod +* u = IF (u >= mod) u = u - mod - reduce r using mod +* u = IF (u >= mod) u = u - mod * * z = a_double % mod * @@ -1216,7 +1123,7 @@ void Cy_Crypto_Core_EC_SM_MulRed(CRYPTO_Type *base, int z, int x, int size) * * \param z * Register index for Barrett reduced value. -* +* * \param x * Register index for non reduced value. * @@ -1225,48 +1132,48 @@ void Cy_Crypto_Core_EC_SM_MulRed(CRYPTO_Type *base, int z, int x, int size) * *******************************************************************************/ void Cy_Crypto_Core_EC_Bar_MulRed(CRYPTO_Type *base, - int z, - int x, - int size) + uint32_t z, + uint32_t x, + uint32_t size) { - int sh = 0; - int t1 = 1; - int t1_plus2 = 1; - int t2_plus2 = 0; - int t_double = 2; - int z_double = 3; - int my_z = 4; + uint32_t sh = 0u; + uint32_t t1 = 1u; + uint32_t t1_plus2 = 1u; + uint32_t t2_plus2 = 0u; + uint32_t t_double = 2u; + uint32_t z_double = 3u; + uint32_t my_z = 4u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, my_z, z); - CY_CRYPTO_VU_LD_REG (base, z_double, x); + CY_CRYPTO_VU_LD_REG (base, my_z, z); + CY_CRYPTO_VU_LD_REG (base, z_double, x); - CY_CRYPTO_VU_ALLOC_MEM (base, t_double, 2u * size); - CY_CRYPTO_VU_ALLOC_MEM (base, t1, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t_double, 2u * size); + CY_CRYPTO_VU_ALLOC_MEM (base, t1, size); - CY_CRYPTO_VU_SET_REG (base, sh, size, 1u); /* sh = k (k \equiv size) */ - CY_CRYPTO_VU_LSR (base, my_z, z_double, sh); /* a/b^{k} (q1*b) */ + CY_CRYPTO_VU_SET_REG (base, sh, size, 1u); /* sh = k (k \equiv size) */ + CY_CRYPTO_VU_LSR (base, my_z, z_double, sh); /* a/b^{k} (q1*b) */ - CY_CRYPTO_VU_UMUL (base, t_double, my_z, VR_BARRETT); /* a/b^{k}*VR_BARRETT (q2*b) */ - CY_CRYPTO_VU_LSR (base, t1, t_double, sh); /* q2*b/b^{k} = q2/b^{k-1} */ + CY_CRYPTO_VU_UMUL (base, t_double, my_z, VR_BARRETT); /* a/b^{k}*VR_BARRETT (q2*b) */ + CY_CRYPTO_VU_LSR (base, t1, t_double, sh); /* q2*b/b^{k} = q2/b^{k-1} */ - CY_CRYPTO_VU_UMUL (base, t_double, t1, VR_P); + CY_CRYPTO_VU_UMUL (base, t_double, t1, VR_P); CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t1)); - CY_CRYPTO_VU_ALLOC_MEM (base, t1_plus2, size + 2u); - CY_CRYPTO_VU_ALLOC_MEM (base, t2_plus2, size + 2u); + CY_CRYPTO_VU_ALLOC_MEM (base, t1_plus2, size + 2u); + CY_CRYPTO_VU_ALLOC_MEM (base, t2_plus2, size + 2u); - CY_CRYPTO_VU_SUB (base, t2_plus2, z_double, t_double); + CY_CRYPTO_VU_SUB (base, t2_plus2, z_double, t_double); - CY_CRYPTO_VU_SUB (base, t1_plus2, t2_plus2, VR_P); - CY_CRYPTO_VU_COND_SWAP_REG (base, CY_CRYPTO_VU_COND_CC, t1_plus2, t2_plus2); + CY_CRYPTO_VU_SUB (base, t1_plus2, t2_plus2, VR_P); + CY_CRYPTO_VU_COND_SWAP_REG (base, CY_CRYPTO_VU_COND_CC, t1_plus2, t2_plus2); - CY_CRYPTO_VU_SUB (base, t2_plus2, t1_plus2, VR_P); - CY_CRYPTO_VU_COND_MOV (base, CY_CRYPTO_VU_COND_CC, my_z, t1_plus2); - CY_CRYPTO_VU_COND_MOV (base, CY_CRYPTO_VU_COND_CS, my_z, t2_plus2); + CY_CRYPTO_VU_SUB (base, t2_plus2, t1_plus2, VR_P); + CY_CRYPTO_VU_COND_MOV (base, CY_CRYPTO_VU_COND_CC, my_z, t1_plus2); + CY_CRYPTO_VU_COND_MOV (base, CY_CRYPTO_VU_COND_CS, my_z, t2_plus2); CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t2_plus2) | CY_CRYPTO_VU_REG_BIT(t1_plus2) | @@ -1291,7 +1198,7 @@ void Cy_Crypto_Core_EC_Bar_MulRed(CRYPTO_Type *base, * * \param z * Result = x mod P = a*b mod P [224 bits]. -* +* * \param x * Product = a*b [2*224 bits]. * @@ -1299,10 +1206,7 @@ void Cy_Crypto_Core_EC_Bar_MulRed(CRYPTO_Type *base, * Bit size. * *******************************************************************************/ -void Cy_Crypto_Core_EC_MulRed(CRYPTO_Type *base, - int z, - int x, - int size) +static void Cy_Crypto_Core_EC_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size) { switch (mul_red_alg_select) { @@ -1334,7 +1238,7 @@ void Cy_Crypto_Core_EC_MulRed(CRYPTO_Type *base, * * \param z * Result = a * b % mod. Register index for product value. -* +* * \param a * Register index for multiplicand value. * @@ -1346,15 +1250,15 @@ void Cy_Crypto_Core_EC_MulRed(CRYPTO_Type *base, * *******************************************************************************/ void Cy_Crypto_Core_EC_MulMod( CRYPTO_Type *base, - int z, - int a, - int b, - int size) + uint32_t z, + uint32_t a, + uint32_t b, + uint32_t size) { - int ab_double = 0; - int my_z = 1; - int my_a = 2; - int my_b = 3; + uint32_t ab_double = 0u; + uint32_t my_z = 1u; + uint32_t my_a = 2u; + uint32_t my_b = 3u; CY_CRYPTO_VU_PUSH_REG (base); @@ -1362,12 +1266,12 @@ void Cy_Crypto_Core_EC_MulMod( CRYPTO_Type *base, CY_CRYPTO_VU_LD_REG(base, my_a, a); CY_CRYPTO_VU_LD_REG(base, my_b, b); - CY_CRYPTO_VU_ALLOC_MEM (base, ab_double, 2 * size); + CY_CRYPTO_VU_ALLOC_MEM (base, ab_double, 2u * size); - CY_CRYPTO_VU_UMUL (base, ab_double, my_a, my_b); + CY_CRYPTO_VU_UMUL (base, ab_double, my_a, my_b); /* Modular Reduction: Barrett reduction or curve-specific or shift-multiply */ - Cy_Crypto_Core_EC_MulRed(base, my_z, ab_double, size); + Cy_Crypto_Core_EC_MulRed(base, my_z, ab_double, size); CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(ab_double)); @@ -1387,7 +1291,7 @@ void Cy_Crypto_Core_EC_MulMod( CRYPTO_Type *base, * * \param z * Result = a + b % mod. Register index for sum value -* +* * \param a * Register index for augend a value. * @@ -1395,10 +1299,10 @@ void Cy_Crypto_Core_EC_MulMod( CRYPTO_Type *base, * Register index for addend b value. * *******************************************************************************/ -void Cy_Crypto_Core_EC_AddMod( CRYPTO_Type *base, int z, int a, int b) +void Cy_Crypto_Core_EC_AddMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t b) { - CY_CRYPTO_VU_ADD (base, z, a, b); /* C = (sum >= 2^n) */ - CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, z, VR_P); /* C = (sum >= mod) */ + CY_CRYPTO_VU_ADD (base, z, a, b); /* C = (sum >= 2^n) */ + CY_CRYPTO_VU_COND_CMP_SUB (base, CY_CRYPTO_VU_COND_CC, z, VR_P); /* C = (sum >= mod) */ CY_CRYPTO_VU_COND_SUB (base, CY_CRYPTO_VU_COND_CS, z, z, VR_P); } @@ -1414,7 +1318,7 @@ void Cy_Crypto_Core_EC_AddMod( CRYPTO_Type *base, int z, int a, int b) * * \param z * Result = a - b % mod. Register index for difference value. -* +* * \param a * Register index for minuend a value. * @@ -1422,7 +1326,7 @@ void Cy_Crypto_Core_EC_AddMod( CRYPTO_Type *base, int z, int a, int b) * RRegister index for subtrahend b value. * *******************************************************************************/ -void Cy_Crypto_Core_EC_SubMod( CRYPTO_Type *base, int z, int a, int b) +void Cy_Crypto_Core_EC_SubMod( CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t b) { CY_CRYPTO_VU_SUB (base, z, a, b); /* C = (a >= b) */ CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_CC, z, z, VR_P); @@ -1442,12 +1346,12 @@ void Cy_Crypto_Core_EC_SubMod( CRYPTO_Type *base, int z, int a, int b) * * \param z * Result = a / 2 % mod.Register index for result value. -* +* * \param a * Register index for value to be halved. * *******************************************************************************/ -void Cy_Crypto_Core_EC_HalfMod( CRYPTO_Type *base, int z, int a) +void Cy_Crypto_Core_EC_HalfMod( CRYPTO_Type *base, uint32_t z, uint32_t a) { CY_CRYPTO_VU_TST (base, a); CY_CRYPTO_VU_COND_ADD (base, CY_CRYPTO_VU_COND_ODD, a, a, VR_P); @@ -1466,7 +1370,7 @@ void Cy_Crypto_Core_EC_HalfMod( CRYPTO_Type *base, int z, int a) * * \param z * Result = a * a % mod. Register index for product value. -* +* * \param a * Register index for multiplicand and multiplier value. * @@ -1475,9 +1379,9 @@ void Cy_Crypto_Core_EC_HalfMod( CRYPTO_Type *base, int z, int a) * *******************************************************************************/ void Cy_Crypto_Core_EC_SquareMod( CRYPTO_Type *base, - int z, - int a, - int size) + uint32_t z, + uint32_t a, + uint32_t size) { Cy_Crypto_Core_EC_MulMod( base, z, a, a, size); } @@ -1489,14 +1393,15 @@ void Cy_Crypto_Core_EC_SquareMod( CRYPTO_Type *base, * * Modular division in GF(VR_P). * This algorithm works when "dividend" and "divisor" are relatively prime, -* Reference: "From Euclid's GCD to Montgomery Multiplication to the Great Divide", S.C. Schantz +* Reference: "From Euclid's GCD to Montgomery Multiplication to the Great Divide", +* S.C. Schantz * * \param base * The pointer to a Crypto instance. * * \param z * Result = a / b % mod. Register index for quotient value. -* +* * \param a * Register index for dividend value. * @@ -1508,40 +1413,40 @@ void Cy_Crypto_Core_EC_SquareMod( CRYPTO_Type *base, * *******************************************************************************/ void Cy_Crypto_Core_EC_DivMod( CRYPTO_Type *base, - int z, - int a, - int b, - int size) + uint32_t z, + uint32_t a, + uint32_t b, + uint32_t size) { - int my_dividend = 7; - int my_divisor = 8; - int my_a = 9; - int my_b = 10; - int my_u = 11; - int my_v = 12; + uint32_t my_dividend = 7u; + uint32_t my_divisor = 8u; + uint32_t my_a = 9u; + uint32_t my_b = 10u; + uint32_t my_u = 11u; + uint32_t my_v = 12u; - uint16_t zero; - uint16_t carry; - uint16_t a_even; - uint16_t b_even; + uint32_t zero; + uint32_t carry; + uint32_t a_even; + uint32_t b_even; - volatile uint16_t status0; - volatile uint16_t status1; - volatile uint16_t status2; + uint32_t status0; + uint32_t status1; + uint32_t status2; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG(base, my_dividend, a); - CY_CRYPTO_VU_LD_REG(base, my_divisor, b); - CY_CRYPTO_VU_LD_REG(base, my_u, z); + CY_CRYPTO_VU_LD_REG(base, my_dividend, a); + CY_CRYPTO_VU_LD_REG(base, my_divisor, b); + CY_CRYPTO_VU_LD_REG(base, my_u, z); - CY_CRYPTO_VU_ALLOC_MEM (base, my_a, size); - CY_CRYPTO_VU_ALLOC_MEM (base, my_b, size); - CY_CRYPTO_VU_ALLOC_MEM (base, my_v, size); + CY_CRYPTO_VU_ALLOC_MEM (base, my_a, size); + CY_CRYPTO_VU_ALLOC_MEM (base, my_b, size); + CY_CRYPTO_VU_ALLOC_MEM (base, my_v, size); - CY_CRYPTO_VU_MOV (base, my_a, my_divisor); - CY_CRYPTO_VU_MOV (base, my_b, VR_P); - CY_CRYPTO_VU_MOV (base, my_u, my_dividend); + CY_CRYPTO_VU_MOV (base, my_a, my_divisor); + CY_CRYPTO_VU_MOV (base, my_b, VR_P); + CY_CRYPTO_VU_MOV (base, my_u, my_dividend); CY_CRYPTO_VU_SET_TO_ZERO (base, my_v); @@ -1558,41 +1463,41 @@ void Cy_Crypto_Core_EC_DivMod( CRYPTO_Type *base, Cy_Crypto_Core_WaitForReady(base); - zero = status0 & (1 << CY_CRYPTO_VU_STATUS_ZERO); /* a == b */ - carry = status0 & (1 << CY_CRYPTO_VU_STATUS_CARRY); /* a >= b */ - a_even = status1 & (1 << CY_CRYPTO_VU_STATUS_EVEN); - b_even = status2 & (1 << CY_CRYPTO_VU_STATUS_EVEN); + zero = status0 & CY_CRYPTO_VU_STATUS_ZERO_BIT; /* a == b */ + carry = status0 & CY_CRYPTO_VU_STATUS_CARRY_BIT; /* a >= b */ + a_even = status1 & CY_CRYPTO_VU_STATUS_EVEN_BIT; + b_even = status2 & CY_CRYPTO_VU_STATUS_EVEN_BIT; - if (zero) + if (0u != zero) { break; } - if (a_even) + if (0u != a_even) { - CY_CRYPTO_VU_LSR1 (base, my_a, my_a); - Cy_Crypto_Core_EC_HalfMod( base, my_u, my_u); + CY_CRYPTO_VU_LSR1 (base, my_a, my_a); + Cy_Crypto_Core_EC_HalfMod( base, my_u, my_u); } - else if (b_even) + else if (0u != b_even) { - CY_CRYPTO_VU_LSR1 (base, my_b, my_b); - Cy_Crypto_Core_EC_HalfMod( base, my_v, my_v); + CY_CRYPTO_VU_LSR1 (base, my_b, my_b); + Cy_Crypto_Core_EC_HalfMod( base, my_v, my_v); } - else if (carry) + else if (0u != carry) { /* (a >= b) */ - CY_CRYPTO_VU_SUB (base, my_a, my_a, my_b); - CY_CRYPTO_VU_LSR1 (base, my_a, my_a); + CY_CRYPTO_VU_SUB (base, my_a, my_a, my_b); + CY_CRYPTO_VU_LSR1 (base, my_a, my_a); - Cy_Crypto_Core_EC_SubMod( base, my_u, my_u, my_v); - Cy_Crypto_Core_EC_HalfMod( base, my_u, my_u); + Cy_Crypto_Core_EC_SubMod( base, my_u, my_u, my_v); + Cy_Crypto_Core_EC_HalfMod( base, my_u, my_u); } else { - CY_CRYPTO_VU_SUB (base, my_b, my_b, my_a); - CY_CRYPTO_VU_LSR1 (base, my_b, my_b); + CY_CRYPTO_VU_SUB (base, my_b, my_b, my_a); + CY_CRYPTO_VU_LSR1 (base, my_b, my_b); - Cy_Crypto_Core_EC_SubMod( base, my_v, my_v, my_u); - Cy_Crypto_Core_EC_HalfMod( base, my_v, my_v); + Cy_Crypto_Core_EC_SubMod( base, my_v, my_v, my_u); + Cy_Crypto_Core_EC_HalfMod( base, my_v, my_v); } } @@ -1613,7 +1518,7 @@ void Cy_Crypto_Core_EC_DivMod( CRYPTO_Type *base, * * \param s_x * Register index for affine X coordinate and Jacobian projective X coordinate. -* +* * \param s_y * Register index for affine Y coordinate and Jacobian projective Y coordinate. * @@ -1621,12 +1526,8 @@ void Cy_Crypto_Core_EC_DivMod( CRYPTO_Type *base, * Register index for Jacobian projective Z coordinate. * *******************************************************************************/ -void Cy_Crypto_Core_JacobianTransform(CRYPTO_Type *base, - int s_x, - int s_y, - int s_z) +void Cy_Crypto_Core_JacobianTransform(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t s_z) { - CY_CRYPTO_VU_SET_TO_ONE (base, s_z); } @@ -1643,7 +1544,7 @@ void Cy_Crypto_Core_JacobianTransform(CRYPTO_Type *base, * * \param s_x * Register index for affine X coordinate and Jacobian projective X coordinate. -* +* * \param s_y * Register index for affine Y coordinate and Jacobian projective Y coordinate. * @@ -1654,38 +1555,34 @@ void Cy_Crypto_Core_JacobianTransform(CRYPTO_Type *base, * Bit size. * *******************************************************************************/ -void Cy_Crypto_Core_JacobianInvTransform(CRYPTO_Type *base, - int s_x, - int s_y, - int s_z, - int size) +void Cy_Crypto_Core_JacobianInvTransform(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t s_z, uint32_t size) { - int t1 = 7; - int t2 = 8; - int t3 = 9; - int my_s_x = 10; - int my_s_y = 11; - int my_s_z = 12; + uint32_t t1 = 7u; + uint32_t t2 = 8u; + uint32_t t3 = 9u; + uint32_t my_s_x = 10u; + uint32_t my_s_y = 11u; + uint32_t my_s_z = 12u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); - CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); - CY_CRYPTO_VU_LD_REG(base, my_s_z, s_z); + CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); + CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); + CY_CRYPTO_VU_LD_REG(base, my_s_z, s_z); - CY_CRYPTO_VU_ALLOC_MEM (base, t1, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t2, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t3, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t1, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t2, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t3, size); - CY_CRYPTO_VU_SET_TO_ONE (base, t1); /* t1 = 1 */ - Cy_Crypto_Core_EC_DivMod( base, t2, t1, my_s_z, size); /* t2 = 1/Z */ + CY_CRYPTO_VU_SET_TO_ONE (base, t1); /* t1 = 1 */ + Cy_Crypto_Core_EC_DivMod( base, t2, t1, my_s_z, size); /* t2 = 1/Z */ - Cy_Crypto_Core_EC_SquareMod( base, t1, t2, size); /* t1 = 1/Z^2 */ - Cy_Crypto_Core_EC_MulMod( base, my_s_x, my_s_x, t1, size); /* my_s_x = X/Z^2 */ + Cy_Crypto_Core_EC_SquareMod( base, t1, t2, size); /* t1 = 1/Z^2 */ + Cy_Crypto_Core_EC_MulMod( base, my_s_x, my_s_x, t1, size); /* my_s_x = X/Z^2 */ - Cy_Crypto_Core_EC_MulMod( base, t3, my_s_y, t1, size); /* t3 = Y/Z^2 */ - Cy_Crypto_Core_EC_MulMod( base, my_s_y, t3, t2, size); /* my_s_y = Y/Z^3 */ + Cy_Crypto_Core_EC_MulMod( base, t3, my_s_y, t1, size); /* t3 = Y/Z^2 */ + Cy_Crypto_Core_EC_MulMod( base, my_s_y, t3, t2, size); /* my_s_y = Y/Z^3 */ CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t1) | CY_CRYPTO_VU_REG_BIT(t2) | CY_CRYPTO_VU_REG_BIT(t3)); @@ -1694,7 +1591,7 @@ void Cy_Crypto_Core_JacobianInvTransform(CRYPTO_Type *base, /******************************************************************************* -* Function Name: Cy_Crypto_Core_JacobianInvTransform +* Function Name: Cy_Crypto_Core_JacobianEcAdd ****************************************************************************//** * * Elliptic curve point addition on mixed Jacobian projective (s) / affine (t) coordinates in GF(VR_P). @@ -1707,7 +1604,7 @@ void Cy_Crypto_Core_JacobianInvTransform(CRYPTO_Type *base, * * \param s_x * Register index for Jacobian projective X coordinate. -* +* * \param s_y * Register index for Jacobian projective Y coordinate. * @@ -1716,7 +1613,7 @@ void Cy_Crypto_Core_JacobianInvTransform(CRYPTO_Type *base, * * \param t_x * Register index for affine X coordinate. -* +* * \param t_y * Register index for affine Y coordinate. * @@ -1725,58 +1622,58 @@ void Cy_Crypto_Core_JacobianInvTransform(CRYPTO_Type *base, * *******************************************************************************/ void Cy_Crypto_Core_JacobianEcAdd(CRYPTO_Type *base, - int s_x, - int s_y, - int s_z, - int t_x, - int t_y, - int size + uint32_t s_x, + uint32_t s_y, + uint32_t s_z, + uint32_t t_x, + uint32_t t_y, + uint32_t size ) { - int t6 = 4; - int t7 = 5; - int t8 = 6; - int t9 = 7; - int my_s_x = 8; - int my_s_y = 9; - int my_s_z = 10; - int my_t_x = 11; - int my_t_y = 12; + uint32_t t6 = 4u; + uint32_t t7 = 5u; + uint32_t t8 = 6u; + uint32_t t9 = 7u; + uint32_t my_s_x = 8u; + uint32_t my_s_y = 9u; + uint32_t my_s_z = 10u; + uint32_t my_t_x = 11u; + uint32_t my_t_y = 12u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); - CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); - CY_CRYPTO_VU_LD_REG(base, my_s_z, s_z); - CY_CRYPTO_VU_LD_REG(base, my_t_x, t_x); - CY_CRYPTO_VU_LD_REG(base, my_t_y, t_y); + CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); + CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); + CY_CRYPTO_VU_LD_REG(base, my_s_z, s_z); + CY_CRYPTO_VU_LD_REG(base, my_t_x, t_x); + CY_CRYPTO_VU_LD_REG(base, my_t_y, t_y); - CY_CRYPTO_VU_ALLOC_MEM (base, t6, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t7, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t8, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t9, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t6, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t7, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t8, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t9, size); - Cy_Crypto_Core_EC_SquareMod( base, t6, my_s_z, size); /* t6 = ZZ */ - Cy_Crypto_Core_EC_MulMod( base, t8, my_t_x, t6, size); /* t8 = xZZ = B */ - Cy_Crypto_Core_EC_MulMod( base, t7, my_t_y, my_s_z, size); /* t7 = yZ */ - Cy_Crypto_Core_EC_SubMod( base, my_s_x, my_s_x, t8); /* my_s_x = X - B = E */ + Cy_Crypto_Core_EC_SquareMod( base, t6, my_s_z, size); /* t6 = ZZ */ + Cy_Crypto_Core_EC_MulMod( base, t8, my_t_x, t6, size); /* t8 = xZZ = B */ + Cy_Crypto_Core_EC_MulMod( base, t7, my_t_y, my_s_z, size); /* t7 = yZ */ + Cy_Crypto_Core_EC_SubMod( base, my_s_x, my_s_x, t8); /* my_s_x = X - B = E */ - Cy_Crypto_Core_EC_MulMod( base, my_s_z, my_s_x, my_s_z, size); /* my_s_z = E*Z = Z3 */ - Cy_Crypto_Core_EC_MulMod( base, t9, t7, t6, size); /* t9 = yZZZ = D */ - Cy_Crypto_Core_EC_SubMod( base, my_s_y, my_s_y, t9); /* my_s_y = Y - D = F */ - Cy_Crypto_Core_EC_SquareMod( base, t6, my_s_x, size); /* t6 = EE */ + Cy_Crypto_Core_EC_MulMod( base, my_s_z, my_s_x, my_s_z, size); /* my_s_z = E*Z = Z3 */ + Cy_Crypto_Core_EC_MulMod( base, t9, t7, t6, size); /* t9 = yZZZ = D */ + Cy_Crypto_Core_EC_SubMod( base, my_s_y, my_s_y, t9); /* my_s_y = Y - D = F */ + Cy_Crypto_Core_EC_SquareMod( base, t6, my_s_x, size); /* t6 = EE */ - Cy_Crypto_Core_EC_MulMod( base, t7, t8, t6, size); /* t7 = B*EE */ - Cy_Crypto_Core_EC_MulMod( base, t8, t6, my_s_x, size); /* t8 = EEE */ - Cy_Crypto_Core_EC_MulMod( base, t6, t9, t8, size); /* t6 = D*EEE */ - Cy_Crypto_Core_EC_SquareMod( base, my_s_x, my_s_y, size); /* my_s_x = FF */ - Cy_Crypto_Core_EC_SubMod( base, my_s_x, my_s_x, t8); /* my_s_x = FF - EEE */ - Cy_Crypto_Core_EC_AddMod( base, t9, t7, t7); /* t9 = 2*B*EE */ - Cy_Crypto_Core_EC_SubMod( base, my_s_x, my_s_x, t9); /* my_s_x = FF - EEE - 2*B*EE = X3 */ - Cy_Crypto_Core_EC_SubMod( base, t7, t7, my_s_x); /* t7 = B*EE - X3 */ - Cy_Crypto_Core_EC_MulMod( base, my_s_y, my_s_y, t7, size); /* my_s_y = F*(B*EE - X3) */ - Cy_Crypto_Core_EC_SubMod( base, my_s_y, my_s_y, t6); /* my_s_y = F*(3*B*EE - FF + EEE) - D*EEE = Y3 */ + Cy_Crypto_Core_EC_MulMod( base, t7, t8, t6, size); /* t7 = B*EE */ + Cy_Crypto_Core_EC_MulMod( base, t8, t6, my_s_x, size); /* t8 = EEE */ + Cy_Crypto_Core_EC_MulMod( base, t6, t9, t8, size); /* t6 = D*EEE */ + Cy_Crypto_Core_EC_SquareMod( base, my_s_x, my_s_y, size); /* my_s_x = FF */ + Cy_Crypto_Core_EC_SubMod( base, my_s_x, my_s_x, t8); /* my_s_x = FF - EEE */ + Cy_Crypto_Core_EC_AddMod( base, t9, t7, t7); /* t9 = 2*B*EE */ + Cy_Crypto_Core_EC_SubMod( base, my_s_x, my_s_x, t9); /* my_s_x = FF - EEE - 2*B*EE = X3 */ + Cy_Crypto_Core_EC_SubMod( base, t7, t7, my_s_x); /* t7 = B*EE - X3 */ + Cy_Crypto_Core_EC_MulMod( base, my_s_y, my_s_y, t7, size); /* my_s_y = F*(B*EE - X3) */ + Cy_Crypto_Core_EC_SubMod( base, my_s_y, my_s_y, t6); /* my_s_y = F*(3*B*EE - FF + EEE) - D*EEE = Y3 */ CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t6) | CY_CRYPTO_VU_REG_BIT(t7) | CY_CRYPTO_VU_REG_BIT(t8) | CY_CRYPTO_VU_REG_BIT(t9)); @@ -1796,7 +1693,7 @@ void Cy_Crypto_Core_JacobianEcAdd(CRYPTO_Type *base, * * \param s_x * Register index for Jacobian projective X coordinate. -* +* * \param s_y * Register index for Jacobian projective Y coordinate. * @@ -1808,80 +1705,58 @@ void Cy_Crypto_Core_JacobianEcAdd(CRYPTO_Type *base, * *******************************************************************************/ void Cy_Crypto_Core_JacobianEcDouble(CRYPTO_Type *base, - int s_x, - int s_y, - int s_z, - int size + uint32_t s_x, + uint32_t s_y, + uint32_t s_z, + uint32_t size ) /* 4M + 4S + 10A */ { - - int t1 = 1; - int t2 = 2; - int t3 = 3; - int t4 = 4; - int my_s_x = 5; - int my_s_y = 6; - int my_s_z = 7; + uint32_t t1 = 1u; + uint32_t t2 = 2u; + uint32_t t3 = 3u; + uint32_t t4 = 4u; + uint32_t my_s_x = 5u; + uint32_t my_s_y = 6u; + uint32_t my_s_z = 7u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); - CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); - CY_CRYPTO_VU_LD_REG(base, my_s_z, s_z); + CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); + CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); + CY_CRYPTO_VU_LD_REG(base, my_s_z, s_z); - CY_CRYPTO_VU_ALLOC_MEM (base, t1, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t2, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t3, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t4, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t1, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t2, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t3, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t4, size); - Cy_Crypto_Core_EC_SquareMod( base, t4, my_s_y, size); /* t4 = Y^2 */ + Cy_Crypto_Core_EC_SquareMod( base, t4, my_s_y, size); /* t4 = Y^2 */ + Cy_Crypto_Core_EC_SquareMod( base, t3, my_s_z, size); /* t3 = Z^2 */ + Cy_Crypto_Core_EC_MulMod( base, my_s_z, my_s_y, my_s_z, size); /* my_s_z = Y*Z */ - Cy_Crypto_Core_EC_SquareMod( base, t3, my_s_z, size); /* t3 = Z^2 */ + Cy_Crypto_Core_EC_MulMod( base, my_s_y, my_s_x, t4, size); /* my_s_y = X*Y^2 = A */ + Cy_Crypto_Core_EC_AddMod( base, my_s_x, my_s_x, t3); /* my_s_x = X + Z^2 */ + Cy_Crypto_Core_EC_AddMod( base, t3, t3, t3); /* t3 = 2*Z^2 */ + Cy_Crypto_Core_EC_SubMod( base, t3, my_s_x, t3); /* t3 = (X + Z^2) - 2*Z^2 = X - Z^2 */ + Cy_Crypto_Core_EC_MulMod( base, t1, my_s_x, t3, size); /* t1 = (X + Z^2) * (X - Z^2) = X^2 - Z^4 */ - Cy_Crypto_Core_EC_MulMod( base, my_s_z, my_s_y, my_s_z, size); /* my_s_z = Y*Z */ + Cy_Crypto_Core_EC_AddMod( base, t3, t1, t1); /* t3 = 2*(X^2 - Z^4) */ + Cy_Crypto_Core_EC_AddMod( base, t1, t1, t3); /* t1 = 3*(X^2 - Z^4) */ + Cy_Crypto_Core_EC_HalfMod( base, t1, t1); /* t1 = 3/2*(X^2 - Z^4) = B */ + Cy_Crypto_Core_EC_SquareMod( base, t3, t1, size); /* t3 = 9/4*(X^2 - Z^4) = B^2 */ + Cy_Crypto_Core_EC_SubMod( base, t3, t3, my_s_y); /* t3 = B^2 - A */ + Cy_Crypto_Core_EC_SubMod( base, my_s_x, t3, my_s_y); /* my_s_x = B^2 - 2*A */ + Cy_Crypto_Core_EC_SubMod( base, my_s_y, my_s_y, my_s_x); /* my_s_y = A - (B^2 - 2*A) = 3*A - B^2 */ + Cy_Crypto_Core_EC_MulMod( base, t2, t1, my_s_y, size); /* t2 = B*(3*A - B^2) */ - Cy_Crypto_Core_EC_MulMod( base, my_s_y, my_s_x, t4, size); /* my_s_y = X*Y^2 = A */ - - Cy_Crypto_Core_EC_AddMod( base, my_s_x, my_s_x, t3); /* my_s_x = X + Z^2 */ - - Cy_Crypto_Core_EC_AddMod( base, t3, t3, t3); /* t3 = 2*Z^2 */ - - Cy_Crypto_Core_EC_SubMod( base, t3, my_s_x, t3); /* t3 = (X + Z^2) - 2*Z^2 = X - Z^2 */ - - Cy_Crypto_Core_EC_MulMod( base, t1, my_s_x, t3, size); /* t1 = (X + Z^2) * (X - Z^2) = X^2 - Z^4 */ - - - Cy_Crypto_Core_EC_AddMod( base, t3, t1, t1); /* t3 = 2*(X^2 - Z^4) */ - - Cy_Crypto_Core_EC_AddMod( base, t1, t1, t3); /* t1 = 3*(X^2 - Z^4) */ - - Cy_Crypto_Core_EC_HalfMod( base, t1, t1); /* t1 = 3/2*(X^2 - Z^4) = B */ - - Cy_Crypto_Core_EC_SquareMod( base, t3, t1, size); /* t3 = 9/4*(X^2 - Z^4) = B^2 */ - - - Cy_Crypto_Core_EC_SubMod( base, t3, t3, my_s_y); /* t3 = B^2 - A */ - - Cy_Crypto_Core_EC_SubMod( base, my_s_x, t3, my_s_y); /* my_s_x = B^2 - 2*A */ - - Cy_Crypto_Core_EC_SubMod( base, my_s_y, my_s_y, my_s_x); /* my_s_y = A - (B^2 - 2*A) = 3*A - B^2 */ - - Cy_Crypto_Core_EC_MulMod( base, t2, t1, my_s_y, size); /* t2 = B*(3*A - B^2) */ - - - Cy_Crypto_Core_EC_SquareMod( base, t1, t4, size); /* t1 = Y^4 */ - - Cy_Crypto_Core_EC_SubMod( base, my_s_y, t2, t1); /* my_s_y = B*(3*A - B^2) - Y^4 */ - + Cy_Crypto_Core_EC_SquareMod( base, t1, t4, size); /* t1 = Y^4 */ + Cy_Crypto_Core_EC_SubMod( base, my_s_y, t2, t1); /* my_s_y = B*(3*A - B^2) - Y^4 */ CY_CRYPTO_VU_FREE_MEM (base, CY_CRYPTO_VU_REG_BIT(t1) | CY_CRYPTO_VU_REG_BIT(t2) | CY_CRYPTO_VU_REG_BIT(t3) | CY_CRYPTO_VU_REG_BIT(t4)); - CY_CRYPTO_VU_POP_REG (base); - - } @@ -1896,7 +1771,7 @@ void Cy_Crypto_Core_JacobianEcDouble(CRYPTO_Type *base, * * \param s_x * Register index for affine X coordinate. -* +* * \param s_y * Register index for affine Y coordinate. * @@ -1907,46 +1782,41 @@ void Cy_Crypto_Core_JacobianEcDouble(CRYPTO_Type *base, * Bit size. * *******************************************************************************/ -void Cy_Crypto_Core_JacobianEcScalarMul(CRYPTO_Type *base, - int s_x, - int s_y, - int d, - int size -) +void Cy_Crypto_Core_JacobianEcScalarMul(CRYPTO_Type *base, uint32_t s_x, uint32_t s_y, uint32_t d, uint32_t size) { - - int i; - uint16_t status; - uint16_t carry; + uint32_t i; + uint32_t status; + uint32_t carry; uint16_t clsame; - int clr = 5; - int t = 6; - int my_s_x = 7; - int my_s_y = 8; - int my_s_z = 9; - int my_t_x = 10; - int my_t_y = 11; - int my_d = 12; + uint32_t clr = 5u; + uint32_t t = 6u; + uint32_t my_s_x = 7u; + uint32_t my_s_y = 8u; + uint32_t my_s_z = 9u; + uint32_t my_t_x = 10u; + uint32_t my_t_y = 11u; + uint32_t my_d = 12u; CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); - CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); - CY_CRYPTO_VU_LD_REG(base, my_d, d); + CY_CRYPTO_VU_LD_REG(base, my_s_x, s_x); + CY_CRYPTO_VU_LD_REG(base, my_s_y, s_y); + CY_CRYPTO_VU_LD_REG(base, my_d, d); - CY_CRYPTO_VU_ALLOC_MEM (base, clr, size); - CY_CRYPTO_VU_ALLOC_MEM (base, t, size); - CY_CRYPTO_VU_ALLOC_MEM (base, my_s_z, size); - CY_CRYPTO_VU_ALLOC_MEM (base, my_t_x, size); - CY_CRYPTO_VU_ALLOC_MEM (base, my_t_y, size); + CY_CRYPTO_VU_ALLOC_MEM (base, clr, size); + CY_CRYPTO_VU_ALLOC_MEM (base, t, size); + CY_CRYPTO_VU_ALLOC_MEM (base, my_s_z, size); + CY_CRYPTO_VU_ALLOC_MEM (base, my_t_x, size); + CY_CRYPTO_VU_ALLOC_MEM (base, my_t_y, size); /* my_t_x has the same initial value of my_s_x, but does not point to the * same address in memory as my_s_x, i.e. different value after point doubling - * my_t_x and my_t_y do not change from (original Jacobian projective coordinates of) original base point + * my_t_x and my_t_y do not change from (original Jacobian projective coordinates of) + * original base point */ - CY_CRYPTO_VU_MOV (base, my_t_x, my_s_x); - CY_CRYPTO_VU_MOV (base, my_t_y, my_s_y); + CY_CRYPTO_VU_MOV (base, my_t_x, my_s_x); + CY_CRYPTO_VU_MOV (base, my_t_y, my_s_y); /* Affine-to-Jacobian Transform. */ CY_CRYPTO_VU_SET_TO_ONE (base, my_s_z); @@ -1964,12 +1834,16 @@ void Cy_Crypto_Core_JacobianEcScalarMul(CRYPTO_Type *base, /* Binary left-to-right algorithm * Perform point addition and point doubling to implement scalar multiplication - * Scan the bits of the scalar from left to right; perform point doubling for each bit, and perform point addition when the bit is set. - * Carry set if current bit is equal to 1 (hence, perform point addition - point doubling is always performed) + * Scan the bits of the scalar from left to right; perform point doubling for each bit, + * and perform point addition when the bit is set. + * Carry set if current bit is equal to 1 (hence, perform point addition - point + * doubling is always performed) */ - for (i = 0; i < (size - clsame - 1); i++) + for (i = 0u; i < (size - clsame - 1u); i++) { - /* Carry set if current bit is equal to 1 (hence, perform point addition - point doubling is always performed) */ + /* Carry set if current bit is equal to 1 (hence, perform point addition - point + * doubling is always performed) + */ CY_CRYPTO_VU_LSL1 (base, my_d, my_d); status = Cy_Crypto_Core_Vu_StatusRead(base); @@ -1977,11 +1851,10 @@ void Cy_Crypto_Core_JacobianEcScalarMul(CRYPTO_Type *base, Cy_Crypto_Core_JacobianEcDouble (base, my_s_x, my_s_y, my_s_z, size); - if (carry) + if (carry != 0U) { Cy_Crypto_Core_JacobianEcAdd (base, my_s_x, my_s_y, my_s_z, my_t_x, my_t_y, size); } - } /* Inverse transform */ @@ -2009,7 +1882,7 @@ void Cy_Crypto_Core_JacobianEcScalarMul(CRYPTO_Type *base, * bitsize of the used NIST P curve. * *******************************************************************************/ -void Cy_Crypto_Core_EC_NistP_SetMode(int bitsize) +void Cy_Crypto_Core_EC_NistP_SetMode(uint32_t bitsize) { switch (bitsize) { @@ -2042,7 +1915,8 @@ void Cy_Crypto_Core_EC_NistP_SetMode(int bitsize) * Select which reduction algorithm has to be used. * * \param alg -* one of {CURVE_SPECIFIC_RED_ALG, SHIFT_MUL_RED_ALG, BARRETT_RED_ALG}. See \ref cy_en_crypto_ecc_red_mul_algs_t. +* one of {CURVE_SPECIFIC_RED_ALG, SHIFT_MUL_RED_ALG, BARRETT_RED_ALG}. +* See \ref cy_en_crypto_ecc_red_mul_algs_t. * *******************************************************************************/ void Cy_Crypto_Core_EC_NistP_SetRedAlg(cy_en_crypto_ecc_red_mul_algs_t alg) @@ -2062,13 +1936,13 @@ void Cy_Crypto_Core_EC_NistP_SetRedAlg(cy_en_crypto_ecc_red_mul_algs_t alg) * * \param p_x * Register index for affine X coordinate of base point. -* +* * \param p_y * Register index for affine Y coordinate of base point. * * \param p_d * Register index for multiplication value. -* +* * \param p_order * Register index for order value.. * @@ -2076,14 +1950,13 @@ void Cy_Crypto_Core_EC_NistP_SetRedAlg(cy_en_crypto_ecc_red_mul_algs_t alg) * Bit size of the used curve. * *******************************************************************************/ -void Cy_Crypto_Core_EC_NistP_PointMul(CRYPTO_Type *base, int p_x, int p_y, int p_d, int p_order, int bitsize) +void Cy_Crypto_Core_EC_NistP_PointMul(CRYPTO_Type *base, uint32_t p_x, uint32_t p_y, uint32_t p_d, uint32_t p_order, uint32_t bitsize) { Cy_Crypto_Core_JacobianEcScalarMul (base, p_x, p_y, p_d, bitsize); Cy_Crypto_Core_Vu_WaitForComplete(base); } - /******************************************************************************* * Function Name: Cy_Crypto_Core_EC_NistP_PointMultiplication ****************************************************************************//** @@ -2095,13 +1968,13 @@ void Cy_Crypto_Core_EC_NistP_PointMul(CRYPTO_Type *base, int p_x, int p_y, int p * * \param curveID * Register index for affine X coordinate of base point. -* +* * \param ecpGX * Register index for affine Y coordinate of base point. * * \param ecpGY * Register index for multiplication value. -* +* * \param ecpD * Register index for order value. * @@ -2116,37 +1989,39 @@ void Cy_Crypto_Core_EC_NistP_PointMul(CRYPTO_Type *base, int p_x, int p_y, int p *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_EC_NistP_PointMultiplication(CRYPTO_Type *base, cy_en_crypto_ecc_curve_id_t curveID, - uint8_t* ecpGX, - uint8_t* ecpGY, - uint8_t* ecpD, - uint8_t* ecpQX, - uint8_t* ecpQY) + const uint8_t *ecpGX, + const uint8_t *ecpGY, + const uint8_t *ecpD, + uint8_t *ecpQX, + uint8_t *ecpQY) { /* N.b. If using test vectors from "http://point-at-infinity.org/ecc/nisttv", - * the 'k' values on the website are in decimal form, while the (x,y) result coordinates are in hexadecimal form - * Input format for 'd' scalar multiplier in this test is in hexademical form. - * Hence, convert k_{dec} to d_{hex} for comparison of test values - */ + * the 'k' values on the website are in decimal form, while the (x,y) result + * coordinates are in hexadecimal form + * Input format for 'd' scalar multiplier in this test is in hexadecimal form. + * Hence, convert k_{dec} to d_{hex} for comparison of test values + */ + /* Setup additional registers */ - int VR_ORDER = 9; + uint32_t VR_ORDER = 9u; const uint8_t *p_polynomial = NULL; const uint8_t *p_barrett = NULL; - cy_stc_crypto_ecc_dp_type *eccDp = Cy_Crypto_Core_ECC_GetCurveParams(curveID); + cy_stc_crypto_ecc_dp_type *eccDp = Cy_Crypto_Core_ECC_GetCurveParams(curveID); cy_en_crypto_status_t myStatus = CY_CRYPTO_NOT_SUPPORTED; if (eccDp != NULL) { /* Setup curve specific parameters depending on mode */ - uint32_t size; + uint32_t bitsize; p_polynomial = eccDp->prime; p_barrett = eccDp->barrett_p; - size = eccDp->size; + bitsize = eccDp->size; - /* use barrett reduction algorithm for operations modulo n (order of the base point) */ + /* use Barrett reduction algorithm for operations modulo n (order of the base point) */ Cy_Crypto_Core_EC_NistP_SetRedAlg(eccDp->algo); Cy_Crypto_Core_EC_NistP_SetMode(eccDp->size); @@ -2155,28 +2030,28 @@ cy_en_crypto_status_t Cy_Crypto_Core_EC_NistP_PointMultiplication(CRYPTO_Type *b if ((NULL != ecpGX) && (NULL != ecpGY) && (NULL != ecpD) && (NULL != ecpQX) && (NULL != ecpQY)) { /* Public parameters and characteristics of elliptic curve */ - CY_CRYPTO_VU_ALLOC_MEM (base, VR_D, size); /* Scalar factor */ - CY_CRYPTO_VU_ALLOC_MEM (base, VR_S_X, size); - CY_CRYPTO_VU_ALLOC_MEM (base, VR_S_Y, size); - CY_CRYPTO_VU_ALLOC_MEM (base, VR_P, size); - CY_CRYPTO_VU_ALLOC_MEM (base, VR_BARRETT, size + 1u); - CY_CRYPTO_VU_ALLOC_MEM (base, VR_ORDER, size); + CY_CRYPTO_VU_ALLOC_MEM (base, VR_D, bitsize); /* Scalar factor */ + CY_CRYPTO_VU_ALLOC_MEM (base, VR_S_X, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, VR_S_Y, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, VR_P, bitsize); + CY_CRYPTO_VU_ALLOC_MEM (base, VR_BARRETT, bitsize + 1u); + CY_CRYPTO_VU_ALLOC_MEM (base, VR_ORDER, bitsize); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, p_polynomial, size); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_P, p_polynomial, bitsize); /* Preparation (either use precalculated or calculated). */ - Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, p_barrett, size + 1u); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_BARRETT, p_barrett, bitsize + 1u); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_S_X, ecpGX, size); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_S_Y, ecpGY, size); - Cy_Crypto_Core_Vu_SetMemValue (base, VR_D, ecpD, size); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_S_X, ecpGX, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_S_Y, ecpGY, bitsize); + Cy_Crypto_Core_Vu_SetMemValue (base, VR_D, ecpD, bitsize); /* ECC calculation: d * G mod p */ - Cy_Crypto_Core_EC_NistP_PointMul(base, VR_S_X, VR_S_Y, VR_D, VR_ORDER, size); + Cy_Crypto_Core_EC_NistP_PointMul(base, VR_S_X, VR_S_Y, VR_D, VR_ORDER, bitsize); /* Get result P = (X,Y) = d.G from EC scalar multiplication */ - Cy_Crypto_Core_Vu_GetMemValue (base, ecpQX, VR_S_X, size); - Cy_Crypto_Core_Vu_GetMemValue (base, ecpQY, VR_S_Y, size); + Cy_Crypto_Core_Vu_GetMemValue (base, ecpQX, VR_S_X, bitsize); + Cy_Crypto_Core_Vu_GetMemValue (base, ecpQY, VR_S_Y, bitsize); /* Free memory */ CY_CRYPTO_VU_FREE_MEM (base, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c index c504700b53..d5a6d3c1ea 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c @@ -65,7 +65,7 @@ static void Cy_Crypto_Core_V1_Hmac_Init(cy_stc_crypto_v1_hmac_state_t *hmacState uint8_t *opad, uint8_t *m0Key); -static void Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, +static cy_en_crypto_status_t Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, cy_stc_crypto_v1_hmac_state_t *hmacState, cy_stc_crypto_sha_state_t *hashState, uint8_t const *key, @@ -118,7 +118,7 @@ static void Cy_Crypto_Core_V1_Hmac_Init(cy_stc_crypto_v1_hmac_state_t *hmacState * Starts HMAC (Hash-based Message Authentication Code) calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hmacState * The pointer to the hmacState structure which stores internal variables @@ -144,7 +144,7 @@ static void Cy_Crypto_Core_V1_Hmac_Init(cy_stc_crypto_v1_hmac_state_t *hmacState * The pointer to the calculated HMAC. * *******************************************************************************/ -static void Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, +static cy_en_crypto_status_t Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, cy_stc_crypto_v1_hmac_state_t *hmacState, cy_stc_crypto_sha_state_t *hashState, uint8_t const *key, @@ -153,6 +153,8 @@ static void Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, uint32_t messageSize, uint8_t *hmac) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; + uint32_t i = 0uL; uint8_t *ipadPtrTmp = (uint8_t*)hmacState->ipad; uint8_t *opadPtrTmp = (uint8_t*)hmacState->opad; @@ -162,13 +164,22 @@ static void Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, if (keyLength > hashState->blockSize) { /* The key is larger than the block size. Do a hash on the key. */ - Cy_Crypto_Core_V1_Sha_Start (base, hashState); - Cy_Crypto_Core_V1_Sha_Update (base, hashState, key, keyLength); - Cy_Crypto_Core_V1_Sha_Finish (base, hashState, (uint8_t*)m0KeyPtrTmp/*, keyLength*/); + tmpResult = Cy_Crypto_Core_V1_Sha_Start(base, hashState); + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V1_Sha_Update(base, hashState, key, keyLength); + } + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V1_Sha_Finish(base, hashState, (uint8_t*)m0KeyPtrTmp); + } - /* Append zeros */ - Cy_Crypto_Core_V1_MemSet(base, (m0KeyPtrTmp + hashState->digestSize), 0x00u, - (uint16_t)(hashState->blockSize - hashState->digestSize)); + if (CY_CRYPTO_SUCCESS == tmpResult) + { + /* Append zeros */ + Cy_Crypto_Core_V1_MemSet(base, (m0KeyPtrTmp + hashState->digestSize), 0x00u, + (uint16_t)(hashState->blockSize - hashState->digestSize)); + } } else if (keyLength < hashState->blockSize) { @@ -181,31 +192,59 @@ static void Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, Cy_Crypto_Core_V1_MemCpy(base, m0KeyPtrTmp, key, (uint16_t)keyLength); } - /* Steps 4 and 7 according to FIPS 198-1 */ - while (i < hashState->blockSize) + if (CY_CRYPTO_SUCCESS == tmpResult) { - ipadPtrTmp[i] = CY_CRYPTO_HMAC_IPAD ^ m0KeyPtrTmp[i]; - opadPtrTmp[i] = CY_CRYPTO_HMAC_0PAD ^ m0KeyPtrTmp[i]; - i++; + /* Steps 4 and 7 according to FIPS 198-1 */ + while (i < hashState->blockSize) + { + ipadPtrTmp[i] = CY_CRYPTO_HMAC_IPAD ^ m0KeyPtrTmp[i]; + opadPtrTmp[i] = CY_CRYPTO_HMAC_0PAD ^ m0KeyPtrTmp[i]; + i++; + } + + /* Step 6 according to FIPS 198-1 */ + tmpResult = Cy_Crypto_Core_V1_Sha_Start(base, hashState); + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V1_Sha_Update(base, hashState, ipadPtrTmp, hashState->blockSize); + } + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + /* Append a message */ + tmpResult = Cy_Crypto_Core_V1_Sha_Update (base, hashState, message, messageSize); + } + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V1_Sha_Finish (base, hashState, ipadPtrTmp); + } + + /* Here is the ready part of HASH: Hash((Key^ipad)||text) */ + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + /* Steps 8, 9 according to FIPS 198-1 */ + tmpResult = Cy_Crypto_Core_V1_Sha_Start(base, hashState); + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V1_Sha_Update(base, hashState, opadPtrTmp, hashState->blockSize); + } + + /* Append HASH from Step 6 */ + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V1_Sha_Update(base, hashState, (uint8_t*)ipadPtrTmp, hashState->digestSize); + } + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V1_Sha_Finish(base, hashState, hmac); + } + } } - /* Step 6 according to FIPS 198-1 */ - Cy_Crypto_Core_V1_Sha_Start (base, hashState); - Cy_Crypto_Core_V1_Sha_Update(base, hashState, ipadPtrTmp, hashState->blockSize); - - /* Append a message */ - Cy_Crypto_Core_V1_Sha_Update (base, hashState, message, messageSize); - Cy_Crypto_Core_V1_Sha_Finish (base, hashState, ipadPtrTmp); - - /* Here is the ready part of HASH: Hash((Key^ipad)||text) */ - - /* Steps 8, 9 according to FIPS 198-1 */ - Cy_Crypto_Core_V1_Sha_Start (base, hashState); - Cy_Crypto_Core_V1_Sha_Update(base, hashState, opadPtrTmp, hashState->blockSize); - - /* Append HASH from Step 6 */ - Cy_Crypto_Core_V1_Sha_Update (base, hashState, (uint8_t*)ipadPtrTmp, hashState->digestSize); - Cy_Crypto_Core_V1_Sha_Finish (base, hashState, hmac); + return (tmpResult); } /******************************************************************************* @@ -215,7 +254,7 @@ static void Cy_Crypto_Core_V1_Hmac_Calculate(CRYPTO_Type *base, * Clears the used memory buffers. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hmacState * The pointer to the HMAC context. @@ -236,7 +275,7 @@ static void Cy_Crypto_Core_V1_Hmac_Free(CRYPTO_Type *base, cy_stc_crypto_v1_hmac * Performs HMAC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hmac * The pointer to the calculated HMAC. Must be 4-byte aligned. @@ -257,7 +296,7 @@ static void Cy_Crypto_Core_V1_Hmac_Free(CRYPTO_Type *base, cy_stc_crypto_v1_hmac * \ref cy_en_crypto_sha_mode_t * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Hmac(CRYPTO_Type *base, @@ -268,25 +307,30 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Hmac(CRYPTO_Type *base, uint32_t keyLength, cy_en_crypto_sha_mode_t mode) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; + /* Allocating internal variables into the CRYPTO SRAM Buffer */ cy_stc_crypto_hmac_buffers_t *hmacBuffers = (cy_stc_crypto_hmac_buffers_t *)(REG_CRYPTO_MEM_BUFF(base)); cy_stc_crypto_v1_hmac_state_t *hmacStateTmp = &hmacBuffers->hmacState; - cy_stc_crypto_sha_state_t hashState; + cy_stc_crypto_sha_state_t hashStateLoc = { 0 }; uint8_t *ipadTmp = (uint8_t*)(&hmacBuffers->ipad); uint8_t *opadTmp = (uint8_t*)(&hmacBuffers->opad); uint8_t *m0KeyTmp = (uint8_t*)(&hmacBuffers->m0Key); - Cy_Crypto_Core_V1_Sha_Init (base, &hashState, mode, &hmacBuffers->shaBuffers); + tmpResult = Cy_Crypto_Core_V1_Sha_Init(base, &hashStateLoc, mode, &hmacBuffers->shaBuffers); - Cy_Crypto_Core_V1_Hmac_Init (hmacStateTmp, ipadTmp, opadTmp, m0KeyTmp); - Cy_Crypto_Core_V1_Hmac_Calculate (base, hmacStateTmp, &hashState, key, keyLength, message, messageSize, hmac); - Cy_Crypto_Core_V1_Hmac_Free (base, hmacStateTmp); + if (CY_CRYPTO_SUCCESS == tmpResult) + { + Cy_Crypto_Core_V1_Hmac_Init(hmacStateTmp, ipadTmp, opadTmp, m0KeyTmp); + tmpResult = Cy_Crypto_Core_V1_Hmac_Calculate (base, hmacStateTmp, &hashStateLoc, key, keyLength, message, messageSize, hmac); + Cy_Crypto_Core_V1_Hmac_Free(base, hmacStateTmp); + } - Cy_Crypto_Core_V1_Sha_Free (base, &hashState); + (void)Cy_Crypto_Core_V1_Sha_Free(base, &hashStateLoc); - return (CY_CRYPTO_SUCCESS); + return (tmpResult); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c index 5800252bfe..d00d3a4100 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c @@ -64,7 +64,7 @@ static void Cy_Crypto_Core_V2_Hmac_Init(cy_stc_crypto_v2_hmac_state_t *hmacState uint8_t *ipad, uint8_t *opad, uint8_t *m0Key); -static void Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, +static cy_en_crypto_status_t Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, cy_stc_crypto_v2_hmac_state_t *hmacState, cy_stc_crypto_sha_state_t *hashState, uint8_t const *key, @@ -116,7 +116,7 @@ static void Cy_Crypto_Core_V2_Hmac_Init(cy_stc_crypto_v2_hmac_state_t *hmacState * Starts HMAC (Hash-based Message Authentication Code) calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hmacState * The pointer to the hmacState structure which stores internal variables @@ -142,7 +142,7 @@ static void Cy_Crypto_Core_V2_Hmac_Init(cy_stc_crypto_v2_hmac_state_t *hmacState * The pointer to the calculated HMAC. * *******************************************************************************/ -static void Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, +static cy_en_crypto_status_t Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, cy_stc_crypto_v2_hmac_state_t *hmacState, cy_stc_crypto_sha_state_t *hashState, uint8_t const *key, @@ -151,6 +151,8 @@ static void Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, uint32_t messageSize, uint8_t *hmac) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; + uint32_t i = 0uL; uint32_t blockSizeTmp = hashState->blockSize; uint32_t digestSizeTmp = hashState->digestSize; @@ -164,9 +166,16 @@ static void Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, if (keyLength > blockSizeTmp) { /* The key is larger than the block size. Do a hash on the key. */ - Cy_Crypto_Core_V2_Sha_Start (base, hashState); - Cy_Crypto_Core_V2_Sha_Update (base, hashState, key, keyLength); - Cy_Crypto_Core_V2_Sha_Finish (base, hashState, m0KeyPtrTmp); + tmpResult = Cy_Crypto_Core_V2_Sha_Start (base, hashState); + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V2_Sha_Update (base, hashState, key, keyLength); + } + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V2_Sha_Finish (base, hashState, m0KeyPtrTmp); + } /* Append zeros */ Cy_Crypto_Core_V2_MemSet(base, (m0KeyPtrTmp + digestSizeTmp), 0x00u, (uint16_t)(blockSizeTmp - digestSizeTmp)); @@ -182,31 +191,59 @@ static void Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, Cy_Crypto_Core_V2_MemCpy(base, m0KeyPtrTmp, key, (uint16_t)keyLength); } - /* Steps 4 and 7 according to FIPS 198-1 */ - while (i < blockSizeTmp) + if (CY_CRYPTO_SUCCESS == tmpResult) { - ipadPtrTmp[i] = CY_CRYPTO_HMAC_IPAD ^ m0KeyPtrTmp[i]; - opadPtrTmp[i] = CY_CRYPTO_HMAC_0PAD ^ m0KeyPtrTmp[i]; - i++; + /* Steps 4 and 7 according to FIPS 198-1 */ + while (i < blockSizeTmp) + { + ipadPtrTmp[i] = CY_CRYPTO_HMAC_IPAD ^ m0KeyPtrTmp[i]; + opadPtrTmp[i] = CY_CRYPTO_HMAC_0PAD ^ m0KeyPtrTmp[i]; + i++; + } + + /* Step 6 according to FIPS 198-1 */ + tmpResult = Cy_Crypto_Core_V2_Sha_Start (base, hashState); + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V2_Sha_Update(base, hashState, ipadPtrTmp, blockSizeTmp); + } + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + /* Append a message */ + tmpResult = Cy_Crypto_Core_V2_Sha_Update(base, hashState, message, messageSize); + } + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V2_Sha_Finish(base, hashState, ipadPtrTmp); + } + + /* Here is the ready part of HASH: Hash((Key^ipad)||text) */ + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + /* Steps 8, 9 according to FIPS 198-1 */ + tmpResult = Cy_Crypto_Core_V2_Sha_Start(base, hashState); + + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V2_Sha_Update(base, hashState, opadPtrTmp, blockSizeTmp); + } + + /* Append HASH from Step 6 */ + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V2_Sha_Update(base, hashState, ipadPtrTmp, digestSizeTmp); + } + if (CY_CRYPTO_SUCCESS == tmpResult) + { + tmpResult = Cy_Crypto_Core_V2_Sha_Finish(base, hashState, hmac); + } + } } - /* Step 6 according to FIPS 198-1 */ - Cy_Crypto_Core_V2_Sha_Start (base, hashState); - Cy_Crypto_Core_V2_Sha_Update(base, hashState, ipadPtrTmp, blockSizeTmp); - - /* Append a message */ - Cy_Crypto_Core_V2_Sha_Update(base, hashState, message, messageSize); - Cy_Crypto_Core_V2_Sha_Finish(base, hashState, ipadPtrTmp); - - /* Here is the ready part of HASH: Hash((Key^ipad)||text) */ - - /* Steps 8, 9 according to FIPS 198-1 */ - Cy_Crypto_Core_V2_Sha_Start(base, hashState); - Cy_Crypto_Core_V2_Sha_Update(base, hashState, opadPtrTmp, blockSizeTmp); - - /* Append HASH from Step 6 */ - Cy_Crypto_Core_V2_Sha_Update(base, hashState, ipadPtrTmp, digestSizeTmp); - Cy_Crypto_Core_V2_Sha_Finish(base, hashState, hmac); + return (tmpResult); } /******************************************************************************* @@ -216,7 +253,7 @@ static void Cy_Crypto_Core_V2_Hmac_Calculate(CRYPTO_Type *base, * Clears the used memory buffers. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hmacState * The pointer to the HMAC context. @@ -235,7 +272,7 @@ static void Cy_Crypto_Core_V2_Hmac_Free(CRYPTO_Type *base, cy_stc_crypto_v2_hmac * Performs HMAC calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hmac * The pointer to the calculated HMAC. Must be 4-byte aligned. @@ -256,7 +293,7 @@ static void Cy_Crypto_Core_V2_Hmac_Free(CRYPTO_Type *base, cy_stc_crypto_v2_hmac * \ref cy_en_crypto_sha_mode_t * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Hmac(CRYPTO_Type *base, @@ -267,27 +304,32 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Hmac(CRYPTO_Type *base, uint32_t keyLength, cy_en_crypto_sha_mode_t mode) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; + /* Allocating internal variables into the CRYPTO SRAM Buffer */ - cy_stc_crypto_v2_hmac_buffers_t hmacBuffersData; + cy_stc_crypto_v2_hmac_buffers_t hmacBuffersData = { 0 }; cy_stc_crypto_v2_hmac_buffers_t *hmacBuffers = &hmacBuffersData; cy_stc_crypto_v2_hmac_state_t *hmacStateTmp = &hmacBuffers->hmacState; - cy_stc_crypto_sha_state_t hashState; + cy_stc_crypto_sha_state_t hashStateLoc = { 0 }; uint8_t *ipadTmp = (uint8_t*)&hmacBuffers->ipad; uint8_t *opadTmp = (uint8_t*)&hmacBuffers->opad; uint8_t *m0KeyTmp = (uint8_t*)&hmacBuffers->m0Key; /* No any buffers needed for Crypto_ver2 IP block */ - Cy_Crypto_Core_V2_Sha_Init (base, &hashState, mode, NULL); + tmpResult = Cy_Crypto_Core_V2_Sha_Init(base, &hashStateLoc, mode, NULL); - Cy_Crypto_Core_V2_Hmac_Init (hmacStateTmp, ipadTmp, opadTmp, m0KeyTmp); - Cy_Crypto_Core_V2_Hmac_Calculate (base, hmacStateTmp, &hashState, key, keyLength, message, messageSize, hmac); - Cy_Crypto_Core_V2_Hmac_Free (base, hmacStateTmp); + if (CY_CRYPTO_SUCCESS == tmpResult) + { + Cy_Crypto_Core_V2_Hmac_Init(hmacStateTmp, ipadTmp, opadTmp, m0KeyTmp); + tmpResult = Cy_Crypto_Core_V2_Hmac_Calculate(base, hmacStateTmp, &hashStateLoc, key, keyLength, message, messageSize, hmac); + Cy_Crypto_Core_V2_Hmac_Free(base, hmacStateTmp); + } - Cy_Crypto_Core_V2_Sha_Free (base, &hashState); + (void)Cy_Crypto_Core_V2_Sha_Free(base, &hashStateLoc); - return (CY_CRYPTO_SUCCESS); + return (tmpResult); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c index 7e4309d88d..f8fb5f5fbb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c @@ -104,6 +104,12 @@ const cy_stc_cryptoIP_t cy_cryptoIpBlockCfgPSoC6_02 = #define CY_CRYPTO_PWR_MODE_RETAINED (2UL) #define CY_CRYPTO_PWR_MODE_ENABLED (3UL) + +/** +* \addtogroup group_crypto_lld_hw_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_ClearVuRegisters ****************************************************************************//** @@ -111,7 +117,7 @@ const cy_stc_cryptoIP_t cy_cryptoIpBlockCfgPSoC6_02 = * The function to initialize the Crypto VU registers. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ void Cy_Crypto_Core_ClearVuRegisters(CRYPTO_Type *base) @@ -140,8 +146,6 @@ void Cy_Crypto_Core_ClearVuRegisters(CRYPTO_Type *base) * * The function to initialize the Crypto hardware. * -* This function is internal and should not to be called directly by user software -* *******************************************************************************/ void Cy_Crypto_Core_HwInit(void) { @@ -155,17 +159,17 @@ void Cy_Crypto_Core_HwInit(void) * The function to enable the Crypto hardware. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \return -* Crypto status \ref cy_en_crypto_status_t. +* Crypto status \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_Enable(CRYPTO_Type *base) { Cy_Crypto_Core_HwInit(); - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { /* Enable Crypto HW */ REG_CRYPTO_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CTL_PWR_MODE, CY_CRYPTO_PWR_MODE_ENABLED) | @@ -232,7 +236,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Enable(CRYPTO_Type *base) * The pointer to a variable to store gathered crypto library information. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_GetLibInfo(cy_en_crypto_lib_info_t *libInfo) @@ -249,15 +253,15 @@ cy_en_crypto_status_t Cy_Crypto_Core_GetLibInfo(cy_en_crypto_lib_info_t *libInfo * Disables the operation of the CRYPTO block. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_Disable(CRYPTO_Type *base) { - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { /* Disable Crypto HW */ REG_CRYPTO_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_CTL_PWR_MODE, CY_CRYPTO_PWR_MODE_OFF) | @@ -322,6 +326,7 @@ void Cy_Crypto_Core_InvertEndianness(void *inArrPtr, uint32_t byteSize) } } +/** \} group_crypto_lld_hw_functions */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c index 94a661fcc7..b6b6946779 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c @@ -39,7 +39,7 @@ * Writes one 32-Bit data word into Crypto FIFO. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param data0 * The address of data to be placed into Crypto FIFO @@ -66,7 +66,7 @@ void Cy_Crypto_SetReg1Instr(CRYPTO_Type *base, uint32_t data0) * Writes two 32-Bit data words into Crypto FIFO. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param data0 * The address of data to be placed into Crypto FIFO @@ -99,7 +99,7 @@ void Cy_Crypto_SetReg2Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1) * Writes three 32-Bit data words into Crypto FIFO. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param data0 * The address of data to be placed into Crypto FIFO @@ -138,7 +138,7 @@ void Cy_Crypto_SetReg3Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, u * Writes four 32-Bit data words into Crypto FIFO. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param data0 * The address of data to be placed into Crypto FIFO @@ -183,7 +183,7 @@ void Cy_Crypto_SetReg4Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, u * Run the Crypto instruction without parameters. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param instr * The Opcode of the called instruction. @@ -207,7 +207,7 @@ void Cy_Crypto_Run0ParamInstr(CRYPTO_Type *base, uint8_t instr) * The parameter must be placed into register 0 * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param instr * The Opcode of the called instruction. @@ -236,7 +236,7 @@ void Cy_Crypto_Run1ParamInstr(CRYPTO_Type *base, uint8_t instr, uint32_t rdst0Sh * the first parameter must be placed into register 1. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param instr * The Opcode of the called instruction. @@ -273,7 +273,7 @@ void Cy_Crypto_Run2ParamInstr(CRYPTO_Type *base, * the second parameter must be placed into register 2. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param instr * The Opcode of the called instruction. @@ -316,7 +316,7 @@ void Cy_Crypto_Run3ParamInstr(CRYPTO_Type *base, * the third parameter must be placed into register 3. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param instr * The Opcode of the called instruction. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c index 07e1fb5b74..90c5e07ed4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c @@ -44,7 +44,7 @@ * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param src * The pointer to the source of MemCpy. @@ -85,7 +85,7 @@ void Cy_Crypto_Core_V1_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uin * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dst * The pointer to the destination of MemSet. @@ -125,7 +125,7 @@ void Cy_Crypto_Core_V1_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16 * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param src0 * The pointer to the first source of MemCmp. @@ -171,7 +171,7 @@ uint32_t Cy_Crypto_Core_V1_MemCmp(CRYPTO_Type *base, void const *src0, void cons * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param src0 * The pointer to the first source of MemXor. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c index 5e241ca106..487f912de8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c @@ -42,7 +42,7 @@ * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param src * The pointer to the source of MemCpy. @@ -81,7 +81,7 @@ void Cy_Crypto_Core_V2_MemCpy(CRYPTO_Type *base, void* dst, void const *src, uin * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param dst * The pointer to the destination of MemSet. @@ -119,7 +119,7 @@ void Cy_Crypto_Core_V2_MemSet(CRYPTO_Type *base, void* dst, uint8_t data, uint16 * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param src0 * The pointer to the first source of MemCmp. @@ -166,7 +166,7 @@ uint32_t Cy_Crypto_Core_V2_MemCmp(CRYPTO_Type *base, void const *src0, void cons * There is no alignment restriction. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param src0 * The pointer to the first source of MemXor. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c index 12771a9af7..53a1a90ea1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c @@ -43,7 +43,7 @@ * Invoking this function causes a restart of the pseudo-random sequence. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param lfsr32InitState * A non-zero seed value for the first LFSR. @@ -55,7 +55,7 @@ * A non-zero seed value for the third LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Prng_Init(CRYPTO_Type *base, @@ -79,7 +79,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Prng_Init(CRYPTO_Type *base, * Generates a Pseudo Random Number. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param max * The maximum value of a random number. @@ -88,7 +88,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Prng_Init(CRYPTO_Type *base, * The pointer to a variable to store the generated pseudo random number. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Prng(CRYPTO_Type *base, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c index 4873ecb714..867fcb0f46 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c @@ -43,7 +43,7 @@ * Invoking this function causes a restart of the pseudo-random sequence. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param lfsr32InitState * A non-zero seed value for the first LFSR. @@ -55,7 +55,7 @@ * A non-zero seed value for the third LFSR. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Prng_Init(CRYPTO_Type *base, @@ -79,7 +79,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Prng_Init(CRYPTO_Type *base, * Generates a Pseudo Random Number. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param max * The maximum value of a random number. @@ -88,7 +88,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Prng_Init(CRYPTO_Type *base, * The pointer to a variable to store the generated pseudo random number. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Prng(CRYPTO_Type *base, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c index 6bcf766be6..73578a6e85 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c @@ -57,61 +57,10 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, #endif /* #if (CPUSS_CRYPTO_VU == 1) */ -/* Encodings for hash functions */ - -#if (CPUSS_CRYPTO_SHA1 == 1) -static const uint8_t sha1EncStr[CY_CRYPTO_SHA1_PADDING_SIZE] = -{ - 0x30u, 0x21u, 0x30u, 0x09u, 0x06u, 0x05u, 0x2Bu, 0x0Eu, - 0x03u, 0x02u, 0x1Au, 0x05u, 0x00u, 0x04u, 0x14u -}; -#endif /* #if (CPUSS_CRYPTO_SHA1 == 1) */ - -#if (CPUSS_CRYPTO_SHA256 == 1) -static const uint8_t sha224EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = -{ - 0x30u, 0x2Du, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, - 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x04u, 0x05u, - 0x00u, 0x04u, 0x1Cu -}; - -static const uint8_t sha256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = -{ - 0x30u, 0x31u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, - 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x01u, 0x05u, - 0x00u, 0x04u, 0x20u -}; -#endif /* #if (CPUSS_CRYPTO_SHA256 == 1) */ - -#if (CPUSS_CRYPTO_SHA512 == 1) -static const uint8_t sha384EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = -{ - 0x30u, 0x41u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, - 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x02u, 0x05u, - 0x00u, 0x04u, 0x30u -}; - -static const uint8_t sha512EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = -{ - 0x30u, 0x51u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, - 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x03u, 0x05u, - 0x00u, 0x04u, 0x40u -}; - -static const uint8_t sha512_224EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = -{ - 0x30u, 0x2Du, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, - 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x05u, 0x05u, - 0x00u, 0x04u, 0x1Cu -}; - -static const uint8_t sha512_256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = -{ - 0x30u, 0x31u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, - 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x06u, 0x05u, - 0x00u, 0x04u, 0x20u -}; -#endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ +/** +* \addtogroup group_crypto_lld_asymmetric_functions +* \{ +*/ /******************************************************************************* * Function Name: Cy_Crypto_Core_Rsa_Verify @@ -127,7 +76,7 @@ static const uint8_t sha512_256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = * Returns the verification result \ref cy_en_crypto_rsa_ver_result_t. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param verResult * The pointer to the verification result \ref cy_en_crypto_rsa_ver_result_t. @@ -145,7 +94,7 @@ static const uint8_t sha512_256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = * The length of the decrypted signature to be verified (in bytes) * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, @@ -155,11 +104,67 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, uint8_t const *decryptedSignature, uint32_t decryptedSignatureLength) { - cy_en_crypto_status_t myResult = CY_CRYPTO_SUCCESS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; + + /* Encodings for hash functions */ + + #if (CPUSS_CRYPTO_SHA1 == 1) + static const uint8_t sha1EncStr[CY_CRYPTO_SHA1_PADDING_SIZE] = + { + 0x30u, 0x21u, 0x30u, 0x09u, 0x06u, 0x05u, 0x2Bu, 0x0Eu, + 0x03u, 0x02u, 0x1Au, 0x05u, 0x00u, 0x04u, 0x14u + }; + #endif /* #if (CPUSS_CRYPTO_SHA1 == 1) */ + + #if (CPUSS_CRYPTO_SHA256 == 1) + static const uint8_t sha224EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = + { + 0x30u, 0x2Du, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, + 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x04u, 0x05u, + 0x00u, 0x04u, 0x1Cu + }; + + static const uint8_t sha256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = + { + 0x30u, 0x31u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, + 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x01u, 0x05u, + 0x00u, 0x04u, 0x20u + }; + #endif /* #if (CPUSS_CRYPTO_SHA256 == 1) */ + + #if (CPUSS_CRYPTO_SHA512 == 1) + static const uint8_t sha384EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = + { + 0x30u, 0x41u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, + 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x02u, 0x05u, + 0x00u, 0x04u, 0x30u + }; + + static const uint8_t sha512EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = + { + 0x30u, 0x51u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, + 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x03u, 0x05u, + 0x00u, 0x04u, 0x40u + }; + + static const uint8_t sha512_224EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = + { + 0x30u, 0x2Du, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, + 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x05u, 0x05u, + 0x00u, 0x04u, 0x1Cu + }; + + static const uint8_t sha512_256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = + { + 0x30u, 0x31u, 0x30u, 0x0Du, 0x06u, 0x09u, 0x60u, 0x86u, + 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x06u, 0x05u, + 0x00u, 0x04u, 0x20u + }; + #endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ uint8_t const *encodingArr = NULL; uint32_t encodingArrSize = 0u; - uint32_t digestSize = 0u; + uint32_t locDigestSize = 0u; uint32_t i; uint32_t psLength; uint32_t cmpRes = 0u; @@ -172,7 +177,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, case CY_CRYPTO_MODE_SHA1: encodingArr = sha1EncStr; encodingArrSize = sizeof(sha1EncStr); - digestSize = CY_CRYPTO_SHA1_DIGEST_SIZE; + locDigestSize = CY_CRYPTO_SHA1_DIGEST_SIZE; break; #endif /* #if (CPUSS_CRYPTO_SHA1 == 1) */ @@ -180,13 +185,13 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, case CY_CRYPTO_MODE_SHA224: encodingArr = sha224EncStr; encodingArrSize = sizeof(sha224EncStr); - digestSize = CY_CRYPTO_SHA224_DIGEST_SIZE; + locDigestSize = CY_CRYPTO_SHA224_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA256: encodingArr = sha256EncStr; encodingArrSize = sizeof(sha256EncStr); - digestSize = CY_CRYPTO_SHA256_DIGEST_SIZE; + locDigestSize = CY_CRYPTO_SHA256_DIGEST_SIZE; break; #endif /* #if (CPUSS_CRYPTO_SHA256 == 1) */ @@ -194,25 +199,25 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, case CY_CRYPTO_MODE_SHA384: encodingArr = sha384EncStr; encodingArrSize = sizeof(sha384EncStr); - digestSize = CY_CRYPTO_SHA384_DIGEST_SIZE; + locDigestSize = CY_CRYPTO_SHA384_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA512: encodingArr = sha512EncStr; encodingArrSize = sizeof(sha512EncStr); - digestSize = CY_CRYPTO_SHA512_DIGEST_SIZE; + locDigestSize = CY_CRYPTO_SHA512_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA512_224: encodingArr = sha512_224EncStr; encodingArrSize = sizeof(sha512_224EncStr); - digestSize = CY_CRYPTO_SHA512_224_DIGEST_SIZE; + locDigestSize = CY_CRYPTO_SHA512_224_DIGEST_SIZE; break; case CY_CRYPTO_MODE_SHA512_256: encodingArr = sha512_256EncStr; encodingArrSize = sizeof(sha512_256EncStr); - digestSize = CY_CRYPTO_SHA512_256_DIGEST_SIZE; + locDigestSize = CY_CRYPTO_SHA512_256_DIGEST_SIZE; break; #endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ @@ -224,12 +229,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, *verResult = CY_CRYPTO_RSA_VERIFY_FAIL; /* Check size of decrypted message */ - if (decryptedSignatureLength < (encodingArrSize + digestSize + 11u)) + if (decryptedSignatureLength < (encodingArrSize + locDigestSize + 11u)) { cmpRes = 1u; /* further checking is not needed */ } - psLength = decryptedSignatureLength - digestSize - encodingArrSize - 3u; + psLength = decryptedSignatureLength - locDigestSize - encodingArrSize - 3u; /* Check whether the begin of message is 0x00, 0x01 and after PS string (before T string) is 0x00 byte.*/ if ( (0u != cmpRes) || @@ -265,8 +270,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, if (0u == cmpRes) { cmpRes = Cy_Crypto_Core_MemCmp(base, digest, - (decryptedSignature + (decryptedSignatureLength - digestSize)), - (uint16_t)digestSize); + (decryptedSignature + (decryptedSignatureLength - locDigestSize)), + (uint16_t)locDigestSize); } if (0u == cmpRes ) @@ -274,9 +279,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, *verResult = CY_CRYPTO_RSA_VERIFY_SUCCESS; } - return (myResult); + return (tmpResult); } +/** \} group_crypto_lld_asymmetric_functions */ #if (CPUSS_CRYPTO_VU == 1) @@ -297,7 +303,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, * where R = 1 << size. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param modDerReg * Register index for Montgomery coefficient value. @@ -306,17 +312,17 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, * Register index for modulo value. * * \param size -* Size of modulo, in Bits. +* Modulo size in bits. * *******************************************************************************/ static void Cy_Crypto_Core_Rsa_MontCoeff(CRYPTO_Type *base, uint32_t modDerReg, uint32_t modReg, uint32_t size) { uint32_t myMod = 9u; uint32_t tmp = 10u; - uint32_t a = 11u; - uint32_t b = 12u; - uint32_t u = 13u; - uint32_t v = 14u; + uint32_t ra = 11u; + uint32_t rb = 12u; + uint32_t ru = 13u; + uint32_t rv = 14u; uint32_t status; uint32_t aZero; @@ -324,27 +330,27 @@ static void Cy_Crypto_Core_Rsa_MontCoeff(CRYPTO_Type *base, uint32_t modDerReg, CY_CRYPTO_VU_PUSH_REG (base); - CY_CRYPTO_VU_LD_REG (base, v, modDerReg); + CY_CRYPTO_VU_LD_REG (base, rv, modDerReg); CY_CRYPTO_VU_LD_REG (base, myMod, modReg); - CY_CRYPTO_VU_ALLOC_MEM (base, a, size); - CY_CRYPTO_VU_ALLOC_MEM (base, b, size); - CY_CRYPTO_VU_ALLOC_MEM (base, u, size); + CY_CRYPTO_VU_ALLOC_MEM (base, ra, size); + CY_CRYPTO_VU_ALLOC_MEM (base, rb, size); + CY_CRYPTO_VU_ALLOC_MEM (base, ru, size); - CY_CRYPTO_VU_SET_TO_ONE (base, u); - CY_CRYPTO_VU_SET_TO_ZERO (base, v); + CY_CRYPTO_VU_SET_TO_ONE (base, ru); + CY_CRYPTO_VU_SET_TO_ZERO (base, rv); - CY_CRYPTO_VU_SET_TO_ZERO (base, a); + CY_CRYPTO_VU_SET_TO_ZERO (base, ra); CY_CRYPTO_VU_SET_REG (base, tmp, (size - 1u), 1u); - CY_CRYPTO_VU_SET_BIT (base, a, tmp); - CY_CRYPTO_VU_MOV (base, b, myMod); + CY_CRYPTO_VU_SET_BIT (base, ra, tmp); + CY_CRYPTO_VU_MOV (base, rb, myMod); while (1) { Cy_Crypto_Core_WaitForReady(base); - CY_CRYPTO_VU_TST(base, a); + CY_CRYPTO_VU_TST(base, ra); status = Cy_Crypto_Core_Vu_StatusRead(base); aZero = status & CY_CRYPTO_VU_STATUS_ZERO_BIT; @@ -354,27 +360,27 @@ static void Cy_Crypto_Core_Rsa_MontCoeff(CRYPTO_Type *base, uint32_t modDerReg, break; } - CY_CRYPTO_VU_LSR1(base, a, a); + CY_CRYPTO_VU_LSR1(base, ra, ra); - CY_CRYPTO_VU_TST(base, u); + CY_CRYPTO_VU_TST(base, ru); status = Cy_Crypto_Core_Vu_StatusRead(base); uEven = status & CY_CRYPTO_VU_STATUS_EVEN_BIT; if (uEven != 0u) { - CY_CRYPTO_VU_LSR1(base, u, u); - CY_CRYPTO_VU_LSR1(base, v, v); + CY_CRYPTO_VU_LSR1(base, ru, ru); + CY_CRYPTO_VU_LSR1(base, rv, rv); } else { - CY_CRYPTO_VU_ADD(base, u, u, b); - CY_CRYPTO_VU_LSR1_WITH_CARRY(base, u, u); - CY_CRYPTO_VU_LSR1(base, v, v); - CY_CRYPTO_VU_SET_BIT(base, v, tmp); + CY_CRYPTO_VU_ADD(base, ru, ru, rb); + CY_CRYPTO_VU_LSR1_WITH_CARRY(base, ru, ru); + CY_CRYPTO_VU_LSR1(base, rv, rv); + CY_CRYPTO_VU_SET_BIT(base, rv, tmp); } } - CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(a) | CY_CRYPTO_VU_REG_BIT(b) | CY_CRYPTO_VU_REG_BIT(u)); + CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(ra) | CY_CRYPTO_VU_REG_BIT(rb) | CY_CRYPTO_VU_REG_BIT(ru)); CY_CRYPTO_VU_POP_REG(base); } @@ -392,7 +398,7 @@ static void Cy_Crypto_Core_Rsa_MontCoeff(CRYPTO_Type *base, uint32_t modDerReg, * barrett = (1 << (2 * size)) / mod NO!!! leading '1' Barrett bit. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param barrettUReg * Register index for Barrett reduction value. @@ -400,8 +406,8 @@ static void Cy_Crypto_Core_Rsa_MontCoeff(CRYPTO_Type *base, uint32_t modDerReg, * \param modReg * Register index for modulo value. * -* \param -* Size modulo size in Bits. +* \param size +* The modulo size in bits. * *******************************************************************************/ static void Cy_Crypto_Core_Rsa_BarrettGetU(CRYPTO_Type *base, uint32_t barrettUReg, uint32_t modReg, uint32_t size) @@ -447,7 +453,7 @@ static void Cy_Crypto_Core_Rsa_BarrettGetU(CRYPTO_Type *base, uint32_t barrettUR * z = (a << size) % mod * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param z * Register index for Montgomery representation value. @@ -521,7 +527,7 @@ static void Cy_Crypto_Core_Rsa_MontTransform(CRYPTO_Type *base, uint32_t z, uint * u = IF (u >= mod) u = u - mod * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param z * Register index for product value. @@ -561,7 +567,7 @@ static void Cy_Crypto_Core_Rsa_MontMul(CRYPTO_Type *base, CY_CRYPTO_VU_UMUL (base, tDouble, a, b); - /* Only lower 32 bits are needed */ + /* Only the lower 32 bits are needed. */ CY_CRYPTO_VU_UMUL (base, t, tDouble, montModDer); /* Clear the MSB bit (cut to size length) */ @@ -605,7 +611,7 @@ static void Cy_Crypto_Core_Rsa_MontMul(CRYPTO_Type *base, * calculation. Suitable for cases with short e. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param y * Register index for calculated value. @@ -619,8 +625,17 @@ static void Cy_Crypto_Core_Rsa_MontMul(CRYPTO_Type *base, * \param n * Register index for modulo value. * +* \param barretCoef +* Barrett coefficient. +* +* \param inverseModulo +* Binary inverse of the modulo. +* +* \param rBar +* Values of (2^moduloLength mod modulo). +* * \param size -* modulo size, in Bits +* The modulo size in bits. * *******************************************************************************/ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, @@ -720,6 +735,11 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, CY_CRYPTO_VU_POP_REG(base); } +/** +* \addtogroup group_crypto_lld_asymmetric_functions +* \{ +*/ + /******************************************************************************* * Function Name: Cy_Crypto_Core_Rsa_Proc ****************************************************************************//** @@ -730,7 +750,7 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, * https://en.wikipedia.org/wiki/RSA_%28cryptosystem%29 * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param key * The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure that stores @@ -746,7 +766,7 @@ static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base, * The pointer to processed message. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, @@ -755,7 +775,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, uint32_t messageSize, uint8_t *processedMessage) { - cy_en_crypto_status_t myResult = CY_CRYPTO_SUCCESS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; uint8_t *expPtr = key->pubExpPtr; uint32_t expBitLength = key->pubExpLength; @@ -834,7 +854,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, Cy_Crypto_Core_Vu_WaitForComplete(base); - /* Copy the myResult to output buffer */ + /* Copy the tmpResult to output buffer */ Cy_Crypto_Core_Vu_GetMemValue(base, (uint8_t*)processedMessage, yReg, nBitLength); CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(yReg) | CY_CRYPTO_VU_REG_BIT(xReg) | @@ -842,7 +862,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, CY_CRYPTO_VU_REG_BIT(inverseModuloReg) | CY_CRYPTO_VU_REG_BIT(barrettReg) | CY_CRYPTO_VU_REG_BIT(rBarReg)); - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -856,20 +876,20 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(CRYPTO_Type *base, * result of (2^moduloLength mod modulo) * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param key * The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure that stores a * public key. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Coef(CRYPTO_Type *base, cy_stc_crypto_rsa_pub_key_t const *key) { - cy_en_crypto_status_t myResult = CY_CRYPTO_SUCCESS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; uint8_t *nPtr = key->moduloPtr; uint32_t nBitLength = key->moduloLength; @@ -916,9 +936,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Coef(CRYPTO_Type *base, CY_CRYPTO_VU_FREE_MEM(base, CY_CRYPTO_VU_REG_BIT(modReg) | CY_CRYPTO_VU_REG_BIT(inverseModuloReg) | CY_CRYPTO_VU_REG_BIT(barrettReg) | CY_CRYPTO_VU_REG_BIT(rBarReg)); - return (myResult); + return (tmpResult); } +/** \} group_crypto_lld_asymmetric_functions */ + #endif /* #if (CPUSS_CRYPTO_VU == 1) */ #endif /* CY_IP_MXCRYPTO */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c index 4cff247c87..6a185c0785 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c @@ -39,15 +39,15 @@ typedef enum { #if (CPUSS_CRYPTO_SHA1 == 1) - CY_CRYPTO_V1_SHA_CTL_MODE_SHA1 = 0u, + CY_CRYPTO_V1_SHA_CTL_MODE_SHA1 = 0U, #endif /* #if (CPUSS_CRYPTO_SHA1 == 1) */ #if (CPUSS_CRYPTO_SHA256 == 1) - CY_CRYPTO_V1_SHA_CTL_MODE_SHA256 = 1u, + CY_CRYPTO_V1_SHA_CTL_MODE_SHA256 = 1U, #endif /* #if (CPUSS_CRYPTO_SHA256 == 1) */ #if (CPUSS_CRYPTO_SHA512 == 1) - CY_CRYPTO_V1_SHA_CTL_MODE_SHA512 = 2u, + CY_CRYPTO_V1_SHA_CTL_MODE_SHA512 = 2U, #endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ } cy_en_crypto_v1_sha_hw_mode_t; @@ -60,7 +60,7 @@ typedef enum * All addresses must be 4-Byte aligned! * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to a Hash State. @@ -99,7 +99,7 @@ void Cy_Crypto_Core_V1_Sha_ProcessBlock(CRYPTO_Type *base, * The function to initialize SHA operation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to a Hash State. @@ -109,10 +109,10 @@ void Cy_Crypto_Core_V1_Sha_ProcessBlock(CRYPTO_Type *base, * CY_CRYPTO_SHA512, CY_CRYPTO_SHA384, CY_CRYPTO_SHA512_224, CY_CRYPTO_SHA512_256 * * \param shaBuffers -* The pointer to memory buffers storage +* The pointer to the memory buffers storage. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, @@ -120,6 +120,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, cy_en_crypto_sha_mode_t mode, void *shaBuffers) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; + /* Initialization vectors for different modes of the SHA algorithm */ #if (CPUSS_CRYPTO_SHA1 == 1) static const uint32_t sha1InitHash[] = @@ -190,7 +192,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, #if (CPUSS_CRYPTO_SHA1 == 1) case CY_CRYPTO_MODE_SHA1: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00u, sizeof(cy_stc_crypto_v1_sha1_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha1_buffers_t)); hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->block; hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha1_buffers_t*)shaBuffers)->hash; @@ -208,7 +210,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, #if (CPUSS_CRYPTO_SHA256 == 1) case CY_CRYPTO_MODE_SHA224: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00u, sizeof(cy_stc_crypto_v1_sha256_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha256_buffers_t)); hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->block; hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->hash; @@ -223,7 +225,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA256: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00u, sizeof(cy_stc_crypto_v1_sha256_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha256_buffers_t)); hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->block; hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha256_buffers_t*)shaBuffers)->hash; @@ -241,7 +243,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, #if (CPUSS_CRYPTO_SHA512 == 1) case CY_CRYPTO_MODE_SHA384: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00u, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; @@ -255,7 +257,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA512: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00u, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; @@ -269,7 +271,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA512_224: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00u, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; @@ -283,7 +285,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, break; case CY_CRYPTO_MODE_SHA512_256: - Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00u, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); + Cy_Crypto_Core_V1_MemSet(base, shaBuffers, 0x00U, sizeof(cy_stc_crypto_v1_sha512_buffers_t)); hashState->block = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->block; hashState->hash = (uint8_t*)((cy_stc_crypto_v1_sha512_buffers_t*)shaBuffers)->hash; @@ -298,13 +300,14 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, #endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ default: + tmpResult = CY_CRYPTO_BAD_PARAMS; break; } /* Set the SHA mode */ REG_CRYPTO_SHA_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_SHA_CTL_MODE, (uint32_t)shaHwMode)); - return (CY_CRYPTO_SUCCESS); + return (tmpResult); } /******************************************************************************* @@ -314,33 +317,33 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, * Initializes the initial hash vector. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Start(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState) { - hashState->blockIdx = 0u; - hashState->messageSize = 0u; - - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if (hashState != NULL) { - if (hashState->hashSize != 0) + hashState->blockIdx = 0U; + hashState->messageSize = 0U; + + if (hashState->hashSize != 0U) { Cy_Crypto_Core_V1_MemCpy(base, hashState->hash, hashState->initialHash, (uint16_t)hashState->hashSize); - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } } - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -350,7 +353,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Start(CRYPTO_Type *base, cy_stc_cryp * Performs the SHA calculation on one message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. @@ -362,12 +365,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Start(CRYPTO_Type *base, cy_stc_cryp * The size of the message whose Hash is being computed. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \note * This function can be called several times only with message lengths dividable -* by block size. Only the last call to the function can process a message with -* the not dividable size. +* by the block size. Only the last call to the function can process a message with +* a not-dividable size. * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Update(CRYPTO_Type *base, @@ -375,13 +378,13 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Update(CRYPTO_Type *base, uint8_t const *message, uint32_t messageSize) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if ((hashState != NULL) && (message != NULL)) { - if (hashState->blockSize != 0) + if (hashState->blockSize != 0U) { - if (messageSize > 0) + if (messageSize != 0U) { uint32_t blockSizeTmp = hashState->blockSize; hashState->messageSize += messageSize; @@ -394,28 +397,28 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Update(CRYPTO_Type *base, messageSize -= blockSizeTmp; } - /* Remaining block will be calculated in Finish function */ + /* The remaining block will be calculated in the Finish function. */ hashState->blockIdx = messageSize; /* Copy the end of the message to the block */ Cy_Crypto_Core_V1_MemCpy(base, hashState->block, message, (uint16_t)(messageSize & (blockSizeTmp - 1u))); } - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } } - return (myResult); + return (tmpResult); } /******************************************************************************* * Function Name: Cy_Crypto_Core_V1_Sha_Finish ****************************************************************************//** * -* Completes SHA calculation. +* Completes the SHA calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. @@ -424,14 +427,14 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Update(CRYPTO_Type *base, * The pointer to the calculated hash digest. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Finish(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState, uint8_t *digest) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if ((hashState != NULL) && (digest != NULL)) { @@ -439,7 +442,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Finish(CRYPTO_Type *base, uint8_t *blockTmp = hashState->block; uint32_t blockSizeTmp = hashState->blockSize; uint32_t blockIdxTmp = hashState->blockIdx; - uint64_t finalMessageSizeInBits = (uint64_t)hashState->messageSize * 8u; + uint64_t finalMessageSizeInBits = (uint64_t)hashState->messageSize * 8U; uint32_t size; if (CY_CRYPTO_SHA512_BLOCK_SIZE == blockSizeTmp) @@ -452,10 +455,10 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Finish(CRYPTO_Type *base, } /* Append 1 bit to the end of the message */ - blockTmp[blockIdxTmp] = 0x80u; + blockTmp[blockIdxTmp] = 0x80U; /* Clear the rest of the block */ - Cy_Crypto_Core_V1_MemSet(base, (void* )&blockTmp[blockIdxTmp + 1u], 0x00u, (uint16_t)(blockSizeTmp - blockIdxTmp - 1u)); + Cy_Crypto_Core_V1_MemSet(base, (void* )&blockTmp[blockIdxTmp + 1U], 0x00U, (uint16_t)(blockSizeTmp - blockIdxTmp - 1U)); if (blockIdxTmp >= size) { @@ -466,32 +469,32 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Finish(CRYPTO_Type *base, Cy_Crypto_Core_V1_MemSet(base, blockTmp, 0x00u, (uint16_t)blockSizeTmp); } - blockTmp[blockSizeTmp - 4u] = (uint8_t)((finalMessageSizeInBits) >> 24u); - blockTmp[blockSizeTmp - 3u] = (uint8_t)((finalMessageSizeInBits) >> 16u); - blockTmp[blockSizeTmp - 2u] = (uint8_t)((finalMessageSizeInBits) >> 8u); - blockTmp[blockSizeTmp - 1u] = (uint8_t)(finalMessageSizeInBits); + blockTmp[blockSizeTmp - 4U] = (uint8_t)((finalMessageSizeInBits) >> 24U); + blockTmp[blockSizeTmp - 3U] = (uint8_t)((finalMessageSizeInBits) >> 16U); + blockTmp[blockSizeTmp - 2U] = (uint8_t)((finalMessageSizeInBits) >> 8U); + blockTmp[blockSizeTmp - 1U] = (uint8_t)(finalMessageSizeInBits); /* Process the last block */ Cy_Crypto_Core_V1_Sha_ProcessBlock(base, hashState, (uint8_t*)blockTmp); /* Invert endians of the hash and copy it to digest, re-use the size variable */ - size = (uint32_t)(hashState->digestSize / 4u); + size = (uint32_t)(hashState->digestSize / 4U); - for(; size != 0u; size--) + for(; size != 0U; size--) { *(digest) = *(hashTmp+3); *(digest+1) = *(hashTmp+2); *(digest+2) = *(hashTmp+1); *(digest+3) = *(hashTmp); - digest += 4; - hashTmp += 4; + digest += 4U; + hashTmp += 4U; } - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -501,30 +504,30 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Finish(CRYPTO_Type *base, * Clears the used memory buffers. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Free(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if (hashState != NULL) { /* Clears the memory buffer. */ - Cy_Crypto_Core_V1_MemSet(base, hashState->block, 0x00u, (uint16_t)hashState->blockSize); - Cy_Crypto_Core_V1_MemSet(base, hashState->hash, 0x00u, (uint16_t)hashState->hashSize); - Cy_Crypto_Core_V1_MemSet(base, hashState->roundMem, 0x00u, (uint16_t)hashState->roundMemSize); + Cy_Crypto_Core_V1_MemSet(base, hashState->block, 0x00U, (uint16_t)hashState->blockSize); + Cy_Crypto_Core_V1_MemSet(base, hashState->hash, 0x00U, (uint16_t)hashState->hashSize); + Cy_Crypto_Core_V1_MemSet(base, hashState->roundMem, 0x00U, (uint16_t)hashState->roundMemSize); - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } - return (myResult); + return (tmpResult); } @@ -535,7 +538,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Free(CRYPTO_Type *base, cy_stc_crypt * Performs the SHA Hash function. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param mode * \ref cy_en_crypto_sha_mode_t @@ -550,7 +553,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Free(CRYPTO_Type *base, cy_stc_crypt * The pointer to the hash digest. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha(CRYPTO_Type *base, @@ -559,31 +562,31 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha(CRYPTO_Type *base, uint8_t *digest, cy_en_crypto_sha_mode_t mode) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; void *shaBuffers = (void *)REG_CRYPTO_MEM_BUFF(base); - cy_stc_crypto_sha_state_t myHashState; + cy_stc_crypto_sha_state_t myHashState = { 0 }; - myResult = Cy_Crypto_Core_V1_Sha_Init (base, &myHashState, mode, shaBuffers); + tmpResult = Cy_Crypto_Core_V1_Sha_Init (base, &myHashState, mode, shaBuffers); - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V1_Sha_Start (base, &myHashState); + tmpResult = Cy_Crypto_Core_V1_Sha_Start (base, &myHashState); } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V1_Sha_Update (base, &myHashState, message, messageSize); + tmpResult = Cy_Crypto_Core_V1_Sha_Update (base, &myHashState, message, messageSize); } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V1_Sha_Finish (base, &myHashState, digest); + tmpResult = Cy_Crypto_Core_V1_Sha_Finish (base, &myHashState, digest); } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V1_Sha_Free (base, &myHashState); + tmpResult = Cy_Crypto_Core_V1_Sha_Free (base, &myHashState); } - return (myResult); + return (tmpResult); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c index 4c32c915be..aced0299ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c @@ -42,7 +42,7 @@ * The function to initialize SHA operation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to a Hash State. @@ -52,10 +52,10 @@ * CY_CRYPTO_SHA512, CY_CRYPTO_SHA384, CY_CRYPTO_SHA512_224, CY_CRYPTO_SHA512_256 * * \param shaBuffers -* The pointer to memory buffers storage +* The pointer to the memory buffers storage. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, @@ -63,6 +63,8 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, cy_en_crypto_sha_mode_t mode, void *shaBuffers) { + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; + /* Initialization vectors for different modes of the SHA algorithm */ #if (CPUSS_CRYPTO_SHA1 == 1) static const uint8_t sha1InitHash[] = @@ -149,7 +151,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, CY_ASSERT_L1(hashState != NULL); - Cy_Crypto_Core_V2_MemSet(base, hashState, 0x00u, sizeof(cy_stc_crypto_sha_state_t)); + Cy_Crypto_Core_V2_MemSet(base, hashState, 0x00U, sizeof(cy_stc_crypto_sha_state_t)); switch (mode) { @@ -209,10 +211,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, break; #endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ default: + tmpResult = CY_CRYPTO_BAD_PARAMS; break; } - return (CY_CRYPTO_SUCCESS); + return (tmpResult); } /******************************************************************************* @@ -222,39 +225,39 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, * Initializes the initial hash vector. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Start(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState) { - hashState->blockIdx = 0u; - hashState->messageSize = 0u; - - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if (hashState != NULL) { - if (hashState->hashSize != 0) + hashState->blockIdx = 0U; + hashState->messageSize = 0U; + + if (hashState->hashSize != 0U) { Cy_Crypto_Core_V2_RBClear(base); Cy_Crypto_Core_V2_Sync(base); Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_LOAD0, hashState->initialHash, hashState->hashSize); - Cy_Crypto_Core_V2_RBXor(base, 0u, hashState->hashSize); + Cy_Crypto_Core_V2_RBXor(base, 0U, hashState->hashSize); Cy_Crypto_Core_V2_Sync(base); Cy_Crypto_Core_V2_RBSwap(base); - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } } - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -264,7 +267,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Start(CRYPTO_Type *base, cy_stc_cryp * Performs the SHA calculation on one message. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. @@ -276,12 +279,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Start(CRYPTO_Type *base, cy_stc_cryp * The size of the message whose Hash is being computed. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * \note * This function can be called several times only with message lengths dividable -* by block size. Only the last call to the function can process a message with -* the not dividable size. +* by the block size. Only the last call to the function can process a message with +* a not-dividable size. * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Update(CRYPTO_Type *base, @@ -289,13 +292,13 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Update(CRYPTO_Type *base, uint8_t const *message, uint32_t messageSize) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if ((hashState != NULL) && (message != NULL)) { - if (hashState->blockSize != 0) + if (hashState->blockSize != 0U) { - if (messageSize > 0) + if (messageSize != 0U) { hashState->messageSize += messageSize; @@ -303,7 +306,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Update(CRYPTO_Type *base, while (messageSize >= hashState->blockSize) { - Cy_Crypto_Core_V2_RBXor(base, 0u, hashState->blockSize); + Cy_Crypto_Core_V2_RBXor(base, 0U, hashState->blockSize); messageSize -= hashState->blockSize; @@ -314,11 +317,11 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Update(CRYPTO_Type *base, hashState->blockIdx = messageSize; } - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } } - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -328,7 +331,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Update(CRYPTO_Type *base, * Completes SHA calculation. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. @@ -337,21 +340,21 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Update(CRYPTO_Type *base, * The pointer to the calculated hash digest. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Finish(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState, uint8_t *digest) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if ((hashState != NULL) && (digest != NULL)) { uint32_t myBlockSize = hashState->blockSize; uint32_t myBlockIdx = hashState->blockIdx; - uint64_t finalMessageSizeInBits = (uint64_t)hashState->messageSize * 8u; + uint64_t finalMessageSizeInBits = (uint64_t)hashState->messageSize * 8U; uint32_t size; if (CY_CRYPTO_SHA512_BLOCK_SIZE == myBlockSize) @@ -364,13 +367,13 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Finish(CRYPTO_Type *base, } /* Load the end of the message (tail that less then block size) to the register buffer */ - Cy_Crypto_Core_V2_RBXor(base, 0u, myBlockIdx); + Cy_Crypto_Core_V2_RBXor(base, 0U, myBlockIdx); /* Sync until XOR operation is completed */ Cy_Crypto_Core_V2_Sync(base); /* Append 1 bit to the end of the message */ - Cy_Crypto_Core_V2_RBSetByte(base, myBlockIdx, 0x80u); + Cy_Crypto_Core_V2_RBSetByte(base, myBlockIdx, 0x80U); if (myBlockIdx >= size) { @@ -381,12 +384,12 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Finish(CRYPTO_Type *base, /* Append message size into last of the block */ /* In case of u32SizeInByte * 8 > u32Max */ - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 5u, (uint8_t)(finalMessageSizeInBits >> 32u)); + Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 5U, (uint8_t)(finalMessageSizeInBits >> 32U)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 4u, (uint8_t)(finalMessageSizeInBits >> 24u)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 3u, (uint8_t)(finalMessageSizeInBits >> 16u)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 2u, (uint8_t)(finalMessageSizeInBits >> 8u)); - Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 1u, (uint8_t)(finalMessageSizeInBits)); + Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 4U, (uint8_t)(finalMessageSizeInBits >> 24U)); + Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 3U, (uint8_t)(finalMessageSizeInBits >> 16U)); + Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 2U, (uint8_t)(finalMessageSizeInBits >> 8U)); + Cy_Crypto_Core_V2_RBSetByte(base, myBlockSize - 1U, (uint8_t)(finalMessageSizeInBits)); Cy_Crypto_Core_V2_Run(base, hashState->mode); Cy_Crypto_Core_V2_Sync(base); @@ -394,14 +397,14 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Finish(CRYPTO_Type *base, /* Write digest. */ Cy_Crypto_Core_V2_FFStart(base, CY_CRYPTO_V2_RB_FF_STORE, digest, hashState->digestSize); Cy_Crypto_Core_V2_RBSwap(base); - Cy_Crypto_Core_V2_RBStore(base, 0u, hashState->digestSize); + Cy_Crypto_Core_V2_RBStore(base, 0U, hashState->digestSize); Cy_Crypto_Core_V2_FFStoreSync(base); - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -411,31 +414,31 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Finish(CRYPTO_Type *base, * Clears the used memory buffers. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param hashState * The pointer to the SHA context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Free(CRYPTO_Type *base, cy_stc_crypto_sha_state_t *hashState) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; if (hashState != NULL) { - Cy_Crypto_Core_V2_MemSet(base, hashState, 0x00u, sizeof(cy_stc_crypto_sha_state_t)); + Cy_Crypto_Core_V2_MemSet(base, hashState, 0x00U, sizeof(cy_stc_crypto_sha_state_t)); /* Clears the memory buffer. */ Cy_Crypto_Core_V2_RBClear(base); Cy_Crypto_Core_V2_Sync(base); - myResult = CY_CRYPTO_SUCCESS; + tmpResult = CY_CRYPTO_SUCCESS; } - return (myResult); + return (tmpResult); } /******************************************************************************* @@ -445,7 +448,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Free(CRYPTO_Type *base, cy_stc_crypt * Performs the SHA Hash function. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param mode * \ref cy_en_crypto_sha_mode_t @@ -460,7 +463,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Free(CRYPTO_Type *base, cy_stc_crypt * The pointer to the hash digest. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha(CRYPTO_Type *base, @@ -469,32 +472,32 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha(CRYPTO_Type *base, uint8_t *digest, cy_en_crypto_sha_mode_t mode) { - cy_en_crypto_status_t myResult = CY_CRYPTO_BAD_PARAMS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_BAD_PARAMS; /* Allocate space for the structure which stores the SHA context */ - cy_stc_crypto_sha_state_t hashState; + cy_stc_crypto_sha_state_t hashState = { 0 }; - /* No any buffers needed for Crypto_ver2 IP block */ - myResult = Cy_Crypto_Core_V2_Sha_Init (base, &hashState, mode, NULL); + /* No buffers are needed for the Crypto_ver2 IP block. */ + tmpResult = Cy_Crypto_Core_V2_Sha_Init (base, &hashState, mode, NULL); - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V2_Sha_Start (base, &hashState); + tmpResult = Cy_Crypto_Core_V2_Sha_Start (base, &hashState); } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V2_Sha_Update (base, &hashState, message, messageSize); + tmpResult = Cy_Crypto_Core_V2_Sha_Update (base, &hashState, message, messageSize); } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V2_Sha_Finish (base, &hashState, digest); + tmpResult = Cy_Crypto_Core_V2_Sha_Finish (base, &hashState, digest); } - if (CY_CRYPTO_SUCCESS == myResult) + if (CY_CRYPTO_SUCCESS == tmpResult) { - myResult = Cy_Crypto_Core_V2_Sha_Free (base, &hashState); + tmpResult = Cy_Crypto_Core_V2_Sha_Free (base, &hashState); } - return (myResult); + return (tmpResult); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c index 3a43c91bb2..5275864895 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c @@ -41,10 +41,10 @@ static void Cy_Crypto_Core_V1_Trng_Init(CRYPTO_Type *base); * Function Name: Cy_Crypto_Core_V1_Trng_Init ****************************************************************************//** * -* Initializes the TRND parameters. +* Initializes the TRNG parameters. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ static void Cy_Crypto_Core_V1_Trng_Init(CRYPTO_Type *base) @@ -57,15 +57,15 @@ static void Cy_Crypto_Core_V1_Trng_Init(CRYPTO_Type *base) REG_CRYPTO_TR_MON_AP_CTL(base) = CY_CRYPTO_V1_TR_AC_CUTOFF; } + /******************************************************************************* * Function Name: Cy_Crypto_Core_V1_Trng ****************************************************************************//** * -* Generates a True Random Number and returns it in the -* cfContext->trngNumPtr. +* Generates a True Random Number. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param GAROPol * The polynomial for the programmable Galois ring oscillator. @@ -80,7 +80,7 @@ static void Cy_Crypto_Core_V1_Trng_Init(CRYPTO_Type *base) * The pointer to a generated true random number. Must be 4-byte aligned. * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V1_Trng(CRYPTO_Type *base, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c index e6d184a225..3c83ff2fae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c @@ -40,10 +40,10 @@ static void Cy_Crypto_Core_V2_Trng_Init(CRYPTO_Type *base); * Function Name: Cy_Crypto_Core_V2_Trng_Init ****************************************************************************//** * -* Initializes the TRND parameters. +* Initializes the TRNG parameters. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * *******************************************************************************/ static void Cy_Crypto_Core_V2_Trng_Init(CRYPTO_Type *base) @@ -56,15 +56,15 @@ static void Cy_Crypto_Core_V2_Trng_Init(CRYPTO_Type *base) REG_CRYPTO_TR_MON_AP_CTL(base) = CY_CRYPTO_V2_TR_AC_CUTOFF; } + /******************************************************************************* * Function Name: Cy_Crypto_Core_V2_Trng ****************************************************************************//** * -* Generates a True Random Number and returns it in the -* cfContext->trngNumPtr. +* Generates a True Random Number. * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param GAROPol * The polynomial for the programmable Galois ring oscillator. @@ -79,7 +79,7 @@ static void Cy_Crypto_Core_V2_Trng_Init(CRYPTO_Type *base) * The pointer to a generated true random number. Must be 4-byte aligned. * * \return -* A Crypto status \ref en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ cy_en_crypto_status_t Cy_Crypto_Core_V2_Trng(CRYPTO_Type *base, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c index ec5df3c749..f1750927c1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c @@ -46,7 +46,7 @@ void Cy_Crypto_Core_Vu_SetMemValue(CRYPTO_Type *base, uint32_t dstReg, uint8_t c Cy_Crypto_Core_Vu_WaitForComplete(base); - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG0, ®0_data); CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG1, ®1_data); @@ -61,10 +61,10 @@ void Cy_Crypto_Core_Vu_SetMemValue(CRYPTO_Type *base, uint32_t dstReg, uint8_t c CY_ASSERT_L1(size <= Cy_Crypto_Core_Vu_RegBitSizeRead(base, dstReg)); - CY_ASSERT_L1(((uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, dstReg) + byteSize - 1) < ((uint32_t)REG_CRYPTO_MEM_BUFF(base) + CY_CRYPTO_MEM_BUFF_SIZE) ); + CY_ASSERT_L1( (((uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, dstReg) + byteSize) - 1u) < ((uint32_t)REG_CRYPTO_MEM_BUFF(base) + CY_CRYPTO_MEM_BUFF_SIZE)); Cy_Crypto_Core_MemCpy(base, (void*)Cy_Crypto_Core_Vu_RegMemPointer(base, dstReg), (const void*)src, byteSize); - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG0, reg0_data); CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG1, reg1_data); @@ -78,7 +78,7 @@ void Cy_Crypto_Core_Vu_GetMemValue(CRYPTO_Type *base, uint8_t *dst, uint32_t src Cy_Crypto_Core_Vu_WaitForComplete(base); - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG0, ®0_data); CY_CRYPTO_VU_SAVE_REG(base, CY_CRYPTO_VU_HW_REG1, ®1_data); @@ -92,11 +92,11 @@ void Cy_Crypto_Core_Vu_GetMemValue(CRYPTO_Type *base, uint8_t *dst, uint32_t src } CY_ASSERT_L1(size <= Cy_Crypto_Core_Vu_RegBitSizeRead(base, srcReg)); - CY_ASSERT_L1(((uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, srcReg) + byteSize - 1) < ((uint32_t)REG_CRYPTO_MEM_BUFF(base) + CY_CRYPTO_MEM_BUFF_SIZE) ); + CY_ASSERT_L1((((uint32_t)Cy_Crypto_Core_Vu_RegMemPointer(base, srcReg) + byteSize) - 1u) < ((uint32_t)REG_CRYPTO_MEM_BUFF(base) + CY_CRYPTO_MEM_BUFF_SIZE) ); Cy_Crypto_Core_MemCpy(base, (void*)dst, (void*)Cy_Crypto_Core_Vu_RegMemPointer(base, srcReg), byteSize); - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG0, reg0_data); CY_CRYPTO_VU_RESTORE_REG(base, CY_CRYPTO_VU_HW_REG1, reg1_data); @@ -129,7 +129,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_Cleanup(CRYPTO_Type *base) /* AES */ REG_CRYPTO_AES_CTL(base) = 0u; - if (cy_device->cryptoVersion == 1u) + if (CY_CRYPTO_HW_V1) { REG_CRYPTO_CRC_LFSR_CTL(base) = 0u; REG_CRYPTO_SHA_CTL(base) = 0u; @@ -145,69 +145,69 @@ cy_en_crypto_status_t Cy_Crypto_Core_Cleanup(CRYPTO_Type *base) Cy_Crypto_Core_V2_RBClear(base); } - Cy_Crypto_Core_MemSet(base, (void *)REG_CRYPTO_MEM_BUFF(base), 0u, CY_CRYPTO_MEM_BUFF_SIZE); + Cy_Crypto_Core_MemSet(base, (void *)REG_CRYPTO_MEM_BUFF(base), 0u, (uint16_t)CY_CRYPTO_MEM_BUFF_SIZE); return (CY_CRYPTO_SUCCESS); } bool Cy_Crypto_Core_Vu_IsRegZero(CRYPTO_Type *base, uint32_t srcReg) { - bool result; - uint16_t status; + bool tmpResult; + uint32_t status; CY_CRYPTO_VU_TST(base, srcReg); status = Cy_Crypto_Core_Vu_StatusRead(base); - if (status & CY_CRYPTO_VU_STATUS_ZERO_BIT) + if (0u != (status & CY_CRYPTO_VU_STATUS_ZERO_BIT)) { - result = true; + tmpResult = true; } else { - result = false; + tmpResult = false; } - return result; + return tmpResult; } bool Cy_Crypto_Core_Vu_IsRegEqual(CRYPTO_Type *base, uint32_t srcReg0, uint32_t srcReg1) { - bool result; - uint16_t status; + bool tmpResult; + uint32_t status; CY_CRYPTO_VU_CMP_SUB (base, srcReg1, srcReg0); /* C = (a >= b) */ status = Cy_Crypto_Core_Vu_StatusRead(base); - if (status & CY_CRYPTO_VU_STATUS_ZERO_BIT) + if (0u != (status & CY_CRYPTO_VU_STATUS_ZERO_BIT)) { - result = true; + tmpResult = true; } else { - result = false; + tmpResult = false; } - return result; + return tmpResult; } bool Cy_Crypto_Core_Vu_IsRegLess(CRYPTO_Type *base, uint32_t srcReg0, uint32_t srcReg1) { - bool result; - uint16_t status; + bool tmpResult; + uint32_t status; CY_CRYPTO_VU_CMP_SUB (base, srcReg1, srcReg0); /* C = (a >= b) */ status = Cy_Crypto_Core_Vu_StatusRead(base); - if (status & CY_CRYPTO_VU_STATUS_CARRY_BIT) + if (0u != (status & CY_CRYPTO_VU_STATUS_CARRY_BIT)) { - result = true; + tmpResult = true; } else { - result = false; + tmpResult = false; } - return result; + return tmpResult; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c index e3da49876d..fda6402e14 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c @@ -46,7 +46,7 @@ #if defined(CY_IP_MXCRYPTO) -/* The pointer to the CRYPTO instance address. */ +/* The pointer to the CRYPTO instance. */ #define CY_CRYPTO_BASE ((CRYPTO_Type *)cy_device->cryptoBase) typedef struct @@ -724,19 +724,19 @@ void Cy_Crypto_Server_GetDataHandler(void) * This function is internal and should not to be called directly by user software * * \param base -* The pointer to the CRYPTO instance address. +* The pointer to the CRYPTO instance. * * \param cryptoContext * The pointer to cy_stc_crypto_context_t structure which stores * the Crypto driver context. * * \return -* A Crypto status \ref cy_en_crypto_status_t. +* \ref cy_en_crypto_status_t * *******************************************************************************/ static cy_en_crypto_status_t Cy_Crypto_Core_CheckHwForErrors(cy_stc_crypto_context_t *cryptoContext) { - cy_en_crypto_status_t myResult = CY_CRYPTO_SUCCESS; + cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; uint32_t myErrorStatus0; uint32_t myErrorStatus1; @@ -750,7 +750,7 @@ static cy_en_crypto_status_t Cy_Crypto_Core_CheckHwForErrors(cy_stc_crypto_conte if (_FLD2VAL(CRYPTO_ERROR_STATUS1_VALID, myErrorStatus1) == 1u) { - myResult = CY_CRYPTO_HW_ERROR; + tmpResult = CY_CRYPTO_HW_ERROR; cy_crypto_serverContext->isHwErrorOccured = true; } @@ -763,7 +763,7 @@ static cy_en_crypto_status_t Cy_Crypto_Core_CheckHwForErrors(cy_stc_crypto_conte if (_FLD2VAL(CRYPTO_ERROR_STATUS1_VALID, myErrorStatus1) == 1u) { - myResult = CY_CRYPTO_HW_ERROR; + tmpResult = CY_CRYPTO_HW_ERROR; } cy_crypto_serverContext->isHwErrorOccured = false; @@ -772,7 +772,7 @@ static cy_en_crypto_status_t Cy_Crypto_Core_CheckHwForErrors(cy_stc_crypto_conte cryptoContext->hwErrorStatus.errorStatus0 = myErrorStatus0; cryptoContext->hwErrorStatus.errorStatus1 = myErrorStatus1; - return (myResult); + return (tmpResult); } #endif /* CY_IP_MXCRYPTO */ From 42376c0d853ce89ca8924bc273877064681c9280 Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Fri, 15 Feb 2019 14:34:39 +0200 Subject: [PATCH 087/109] PSOC6: minor updates to Cypress HAL --- .../TARGET_PSOC6/analogin_api.c | 14 ++++---- targets/TARGET_Cypress/TARGET_PSOC6/crc_api.c | 33 +++++++++---------- .../TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c | 31 +++++++---------- .../TARGET_Cypress/TARGET_PSOC6/psoc6_utils.h | 3 +- .../TARGET_Cypress/TARGET_PSOC6/pwmout_api.c | 4 +-- .../TARGET_Cypress/TARGET_PSOC6/serial_api.c | 22 ++++++++----- targets/TARGET_Cypress/TARGET_PSOC6/spi_api.c | 12 +++---- .../TARGET_Cypress/TARGET_PSOC6/trng_api.c | 12 +++---- 8 files changed, 61 insertions(+), 70 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c index 9133e88d4c..93df2f04c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c @@ -44,7 +44,7 @@ const uint32_t SAR_BASE_CLOCK_HZ = 18000000; // 18 MHz or less CY_SAR_CHAN_SAMPLE_TIME_0 \ ) -#define CY_SAR_PORT_9 (9uL) +#define CY_SAR_PORT_9 (9uL) /** Global SAR configuration data, modified as channels are configured. */ @@ -173,11 +173,10 @@ uint16_t analogin_read_u16(analogin_t *obj) if (CY_SAR_PORT_9 != port) { /* Connect the SAR Vplus input to the pin directly */ Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_CLOSE); - } - else { + } else { /* Connect the SAR Vplus input to the AMUXA bus */ Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk, CY_SAR_SWITCH_CLOSE); - + /* Connect the AMUXA bus to the pin */ Cy_GPIO_SetHSIOM(portPrt, CY_PIN(obj->pin), HSIOM_SEL_AMUXA); } @@ -188,15 +187,14 @@ uint16_t analogin_read_u16(analogin_t *obj) } else { error("ANALOG IN: measurement failed!"); } - + if (CY_SAR_PORT_9 != port) { /* Disconnect the SAR Vplus input from the pin */ Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_OPEN); - } - else { + } else { /* Disconnect the AMUXA bus from the pin */ Cy_GPIO_SetHSIOM(portPrt, CY_PIN(obj->pin), HSIOM_SEL_GPIO); - + /* Disconnect the SAR Vplus input from the AMUXA bus */ Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk, CY_SAR_SWITCH_OPEN); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/crc_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/crc_api.c index 9b8fba9a26..0f713984ed 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/crc_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/crc_api.c @@ -26,11 +26,11 @@ #include "cy_crypto_core_crc.h" -static uint32_t crcWidth = 0; -static uint32_t crcShift = 0; +static uint32_t crcWidth = 0UL; +static uint32_t crcShift = 0UL; static uint32_t crcXorMask; -/* Cypress CRYPTO HW supports ANY CRC algorithms from CRC-3 to CRC-32 */ +/* Cypress CRYPTO hardware supports any CRC algorithms from CRC-3 to CRC-32 */ bool hal_crc_is_supported(const crc_mbed_config_t *config) { return (config != NULL); @@ -38,20 +38,19 @@ bool hal_crc_is_supported(const crc_mbed_config_t *config) void hal_crc_compute_partial_start(const crc_mbed_config_t *config) { - uint32_t myMask = 0; + uint32_t myMask = 0UL; - if (!hal_crc_is_supported(config) || (cy_reserve_crypto(CY_CRYPTO_CRC_HW) != 0)) - { + if (!hal_crc_is_supported(config) || (cy_reserve_crypto(CY_CRYPTO_CRC_HW) != 0U)) { return; } crcWidth = config->width; - crcShift = (uint32_t)(!config->reflect_out) * (crcWidth & 7u); - if (crcShift) { - crcShift = 8u - crcShift; - for (uint32_t i = 0; i < crcShift; i++) { - myMask |= 1 << i; + crcShift = (uint32_t)(!config->reflect_out) * (crcWidth & 7U); + if (0U != crcShift) { + crcShift = 8U - crcShift; + for (uint32_t i = 0U; i < crcShift; i++) { + myMask |= 1U << i; } crcXorMask = config->final_xor & myMask; } @@ -59,7 +58,7 @@ void hal_crc_compute_partial_start(const crc_mbed_config_t *config) Cy_Crypto_Core_Crc_CalcInit(CRYPTO, config->width, config->polynomial, config->reflect_in, - 0, + 0U, config->reflect_out, config->final_xor >> crcShift, config->initial_xor); @@ -67,7 +66,7 @@ void hal_crc_compute_partial_start(const crc_mbed_config_t *config) void hal_crc_compute_partial(const uint8_t *data, const size_t size) { - if ((data == NULL) || (size <= 0) || (crcWidth == 0)) { + if ((data == NULL) || (size <= 0U) || (crcWidth == 0U)) { return; } @@ -76,10 +75,10 @@ void hal_crc_compute_partial(const uint8_t *data, const size_t size) uint32_t hal_crc_get_result(void) { - uint32_t result = 0; + uint32_t result = 0UL; - if (crcWidth == 0) { - return 0xffffffffu; + if (crcWidth == 0UL) { + return 0xFFFFFFFFUL; } Cy_Crypto_Core_Crc_CalcFinish(CRYPTO, crcWidth, &result); @@ -89,7 +88,7 @@ uint32_t hal_crc_get_result(void) result = result ^ crcXorMask; } - crcWidth = 0; + crcWidth = 0UL; cy_free_crypto(CY_CRYPTO_CRC_HW); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c index dc88242ee3..84af989a07 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c @@ -360,9 +360,9 @@ static uint8_t crypto_reservations[NUM_CRYPTO_HW] = { 0u }; static int cy_crypto_reserved_status(void) { return ((int)(crypto_reservations[CY_CRYPTO_TRNG_HW] | - crypto_reservations[CY_CRYPTO_CRC_HW] | - crypto_reservations[CY_CRYPTO_VU_HW] | - crypto_reservations[CY_CRYPTO_COMMON_HW])); + crypto_reservations[CY_CRYPTO_CRC_HW] | + crypto_reservations[CY_CRYPTO_VU_HW] | + crypto_reservations[CY_CRYPTO_COMMON_HW])); } @@ -370,26 +370,20 @@ int cy_reserve_crypto(cy_en_crypto_submodule_t module_num) { int result = (-1); - if (module_num < NUM_CRYPTO_HW) - { + if (module_num < NUM_CRYPTO_HW) { core_util_critical_section_enter(); - if (cy_crypto_reserved_status() == 0) - { + if (cy_crypto_reserved_status() == 0) { /* Enable Crypto IP on demand */ Cy_Crypto_Core_Enable(CRYPTO); } - if (module_num == CY_CRYPTO_COMMON_HW) - { - if (crypto_reservations[module_num] != 1) - { + if (module_num == CY_CRYPTO_COMMON_HW) { + if (crypto_reservations[module_num] != 1) { crypto_reservations[module_num] = 1; result = 0; } - } - else - { + } else { crypto_reservations[module_num] = 1; result = 0; } @@ -405,16 +399,13 @@ void cy_free_crypto(cy_en_crypto_submodule_t module_num) { int result = (-1); - if (module_num < NUM_CRYPTO_HW) - { + if (module_num < NUM_CRYPTO_HW) { core_util_critical_section_enter(); - if (crypto_reservations[module_num] == 1) - { + if (crypto_reservations[module_num] == 1) { crypto_reservations[module_num] = 0; - if (cy_crypto_reserved_status() == 0) - { + if (cy_crypto_reserved_status() == 0) { /* Crypto hardware is still in enabled state; to disable: Cy_Crypto_Core_Disable(CRYPTO) */ } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.h index b9adf938d9..452940542a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.h @@ -215,8 +215,7 @@ static inline uint32_t gpio_get_cy_drive_mode(PinDirection dir, PinMode mode) return cymode; } -typedef enum -{ +typedef enum { CY_CRYPTO_TRNG_HW, CY_CRYPTO_CRC_HW, CY_CRYPTO_VU_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/pwmout_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/pwmout_api.c index 1f39903179..915d267df9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/pwmout_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/pwmout_api.c @@ -73,7 +73,7 @@ static void pwm_start_32b(pwmout_t *obj, uint32_t new_period, uint32_t new_width Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->counter_id, obj->period - 1); Cy_TCPWM_PWM_SetCompare0(obj->base, obj->counter_id, obj->pulse_width); Cy_TCPWM_PWM_Enable(obj->base, obj->counter_id); - Cy_TCPWM_TriggerStart(obj->base, 1UL << obj->counter_id); + Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1UL << obj->counter_id); } static void pwm_start_16b(pwmout_t *obj, uint32_t period, uint32_t width) @@ -101,7 +101,7 @@ static void pwm_start_16b(pwmout_t *obj, uint32_t period, uint32_t width) Cy_TCPWM_PWM_SetPrescaler(obj->base, obj->counter_id, prescaler); Cy_TCPWM_PWM_SetCompare0(obj->base, obj->counter_id, width); Cy_TCPWM_PWM_Enable(obj->base, obj->counter_id); - Cy_TCPWM_TriggerStart(obj->base, 1UL << obj->counter_id); + Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1UL << obj->counter_id); } static void pwm_start(pwmout_t *obj, uint32_t new_period, uint32_t new_pulse_width) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c index dc01883ce8..9f7c686ec1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c @@ -383,13 +383,16 @@ static void serial_init_peripheral(serial_obj_t *obj) } +/* + * Callback function to handle into and out of deep sleep state transitions. + */ #if DEVICE_SLEEP && DEVICE_LPTICKER && SERIAL_PM_CALLBACK_ENABLED -static cy_en_syspm_status_t serial_pm_callback(cy_stc_syspm_callback_params_t *params) +static cy_en_syspm_status_t serial_pm_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode) { - serial_obj_t *obj = (serial_obj_t *)params->context; + serial_obj_t *obj = (serial_obj_t *) callbackParams->context; cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (params->mode) { + switch (mode) { case CY_SYSPM_CHECK_READY: /* If all data elements are transmitted from the TX FIFO and * shifter and the RX FIFO is empty: the UART is ready to enter @@ -432,7 +435,7 @@ static cy_en_syspm_status_t serial_pm_callback(cy_stc_syspm_callback_params_t *p return status; } -#endif /* (DEVICE_SLEEP && DEVICE_LPTICKER && SERIAL_PM_CALLBACK_ENABLED) */ +#endif /* DEVICE_SLEEP && DEVICE_LPTICKER && SERIAL_PM_CALLBACK_ENABLED */ void serial_init(serial_t *obj_in, PinName tx, PinName rx) @@ -492,16 +495,16 @@ void serial_init(serial_t *obj_in, PinName tx, PinName rx) #if DEVICE_SLEEP && DEVICE_LPTICKER && SERIAL_PM_CALLBACK_ENABLED /* Register callback once */ obj->pm_callback_handler.callback = serial_pm_callback; - obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP; + obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP; obj->pm_callback_handler.skipMode = 0; obj->pm_callback_handler.callbackParams = &obj->pm_callback_params; - obj->pm_callback_params.base = obj->base; + obj->pm_callback_params.base = obj->base; obj->pm_callback_params.context = obj; if (!Cy_SysPm_RegisterCallback(&obj->pm_callback_handler)) { error("PM callback registration failed!"); } -#endif /* (DEVICE_SLEEP && DEVICE_LPTICKER && SERIAL_PM_CALLBACK_ENABLED) */ +#endif /* DEVICE_SLEEP && DEVICE_LPTICKER && SERIAL_PM_CALLBACK_ENABLED */ } /* Configure hardware resources */ @@ -666,9 +669,10 @@ void serial_set_flow_control(serial_t *obj_in, FlowControl type, PinName rxflow, { serial_obj_t *obj = OBJ_P(obj_in); - /* Do not perform pins reservation second time for the same pins */ - if ((obj->pin_rts == rxflow) && (obj->pin_cts == txflow)) + /* Do not perform pins reservation second time for the same pins */ + if ((obj->pin_rts == rxflow) && (obj->pin_cts == txflow)) { return; + } Cy_SCB_UART_Disable(obj->base, NULL); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/spi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/spi_api.c index fb4a50bbfa..8bb5b4336d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/spi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/spi_api.c @@ -237,16 +237,16 @@ static void spi_init_peripheral(spi_obj_t *obj) /* Callback function to handle into and out of deep sleep state transitions. * */ -#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER -static cy_en_syspm_status_t spi_pm_callback(cy_stc_syspm_callback_params_t *callback_params) +#if DEVICE_SLEEP && DEVICE_LPTICKER +static cy_en_syspm_status_t spi_pm_callback(cy_stc_syspm_callback_params_t *callback_params, cy_en_syspm_callback_mode_t mode) { cy_stc_syspm_callback_params_t params = *callback_params; spi_obj_t *obj = (spi_obj_t *)params.context; params.context = &obj->context; - return Cy_SCB_SPI_DeepSleepCallback(¶ms); + return Cy_SCB_SPI_DeepSleepCallback(¶ms, mode); } -#endif /* DEVICE_SLEEP && DEVICE_LOWPOWERTIMER */ +#endif /* DEVICE_SLEEP && DEVICE_LPTICKER */ void spi_init(spi_t *obj_in, PinName mosi, PinName miso, PinName sclk, PinName ssel) @@ -314,7 +314,7 @@ void spi_init(spi_t *obj_in, PinName mosi, PinName miso, PinName sclk, PinName s obj->div_num = _FLD2VAL(CY_PERI_CLOCK_CTL_DIV_SEL, map); obj->div_type = (cy_en_divider_types_t) _FLD2VAL(CY_PERI_CLOCK_CTL_TYPE_SEL, map); } else { -#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER +#if DEVICE_SLEEP && DEVICE_LPTICKER /* Register callback once */ obj->pm_callback_handler.callback = spi_pm_callback; obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP; @@ -326,7 +326,7 @@ void spi_init(spi_t *obj_in, PinName mosi, PinName miso, PinName sclk, PinName s if (!Cy_SysPm_RegisterCallback(&obj->pm_callback_handler)) { error("PM callback registration failed!"); } -#endif /* DEVICE_SLEEP && DEVICE_LOWPOWERTIMER */ +#endif /* DEVICE_SLEEP && DEVICE_LPTICKER */ } /* Configure hardware resources */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/trng_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/trng_api.c index 49bb1ae26a..92f751670d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/trng_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/trng_api.c @@ -24,8 +24,8 @@ #include "cy_crypto_core_trng.h" /* Initialization polynomial values fro True Random Generator */ -#define GARO31_INITSTATE (0x04c11db7u) -#define FIRO31_INITSTATE (0x04c11db7u) +#define GARO31_INITSTATE (0x04c11db7UL) +#define FIRO31_INITSTATE (0x04c11db7UL) #define MAX_TRNG_BIT_SIZE (32UL) @@ -47,7 +47,7 @@ void trng_free(trng_t *obj) int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) { int ret = 0; - *output_length = 0; + *output_length = 0U; /* temporary random data buffer */ uint32_t random; @@ -59,13 +59,13 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l if (Cy_Crypto_Core_Trng(CRYPTO, GARO31_INITSTATE, FIRO31_INITSTATE, MAX_TRNG_BIT_SIZE, &random) != CY_CRYPTO_SUCCESS) { ret = -1; } else { - for (uint8_t i = 0; (i < 4) && (*output_length < length) ; i++) { + for (uint8_t i = 0; (i < 4U) && (*output_length < length) ; i++) { *output++ = ((uint8_t *)&random)[i]; - *output_length += 1; + *output_length += 1U; } } } - random = 0uL; + random = 0UL; return (ret); } From 91df4c9187e4de64b2b536c5d570a7adb04af65a Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Fri, 15 Feb 2019 14:35:52 +0200 Subject: [PATCH 088/109] PSOC6: do not reconfigure BT GPIO pins in CYW43XXX HCIDriver --- .../targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp index 3b5bf8ef50..3288b568e0 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp @@ -75,11 +75,10 @@ public: virtual void do_initialize() { - - Cy_GPIO_Clr(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN); + bt_device_wake = 0; wait_ms(500); - Cy_GPIO_Set(BT_POWER_PORT, BT_POWER_PIN); + bt_power = 1; wait_ms(500); } From cd4165bae8948f553a0424320e4af26f90d72d89 Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Fri, 15 Feb 2019 19:48:29 +0200 Subject: [PATCH 089/109] PSOC6: update BSP generated sources with latest configurator Use ModusToolbox Device Configurator 1.1.0.284 to generate the BSP low-level initialization code. Compatible version of Device Configurator to be released with ModusToolbox 1.1. Notable changes: * rename cycfg_connectivity -> cycfg_routing * switch LF_CLK clock source from ILO to WCO on CY8CPROTO-062-4343W and CYW943012P6EVB-01 --- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.h | 2 +- .../{cycfg_connectivity.c => cycfg_routing.c} | 6 ++-- .../{cycfg_connectivity.h => cycfg_routing.h} | 12 +++---- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg_pins.h | 2 +- .../GeneratedSource/cycfg_platform.c | 2 +- .../GeneratedSource/cycfg_platform.h | 2 +- .../{cycfg_connectivity.c => cycfg_routing.c} | 6 ++-- .../{cycfg_connectivity.h => cycfg_routing.h} | 34 +++++++++---------- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.h | 2 +- .../GeneratedSource/cycfg_platform.c | 2 +- .../GeneratedSource/cycfg_platform.h | 2 +- .../{cycfg_connectivity.c => cycfg_routing.c} | 22 ++++++------ .../{cycfg_connectivity.h => cycfg_routing.h} | 20 +++++------ .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.h | 2 +- .../GeneratedSource/cycfg_platform.c | 14 ++------ .../GeneratedSource/cycfg_platform.h | 2 +- .../{cycfg_connectivity.c => cycfg_routing.c} | 6 ++-- .../{cycfg_connectivity.h => cycfg_routing.h} | 12 +++---- .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 2 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.h | 2 +- .../GeneratedSource/cycfg_platform.c | 4 +-- .../GeneratedSource/cycfg_platform.h | 2 +- .../{cycfg_connectivity.c => cycfg_routing.c} | 6 ++-- .../{cycfg_connectivity.h => cycfg_routing.h} | 12 +++---- 37 files changed, 98 insertions(+), 106 deletions(-) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/{cycfg_connectivity.c => cycfg_routing.c} (93%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/{cycfg_connectivity.h => cycfg_routing.h} (93%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/{cycfg_connectivity.c => cycfg_routing.c} (93%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/{cycfg_connectivity.h => cycfg_routing.h} (70%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/{cycfg_connectivity.c => cycfg_routing.c} (86%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/{cycfg_connectivity.h => cycfg_routing.h} (88%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/{cycfg_connectivity.c => cycfg_routing.c} (93%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/{cycfg_connectivity.h => cycfg_routing.h} (93%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/{cycfg_connectivity.c => cycfg_routing.c} (95%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/{cycfg_connectivity.h => cycfg_routing.h} (95%) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c index cf7ac0229a..74c28aba2c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c @@ -30,5 +30,5 @@ void init_cycfg_all(void) init_cycfg_peripherals(); init_cycfg_pins(); init_cycfg_platform(); - init_cycfg_connectivity(); + init_cycfg_routing(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h index 68bb40bf09..ac6033d2bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h @@ -34,7 +34,7 @@ extern "C" { #include "cycfg_peripherals.h" #include "cycfg_pins.h" #include "cycfg_platform.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h index 558a12aade..d3b2015e80 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h @@ -35,7 +35,7 @@ #include "cy_mcwdt.h" #include "cy_rtc.h" #include "cy_tcpwm_pwm.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h index c2f019c59e..edfb6d7fce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h @@ -27,7 +27,7 @@ #include "cycfg_notices.h" #include "cy_gpio.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.c similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.c index c389562da2..ae79008829 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.c @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.c +* File Name: cycfg_routing.c * * Description: * Establishes all necessary connections between hardware elements. @@ -22,11 +22,11 @@ * limitations under the License. ********************************************************************************/ -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_device_headers.h" -void init_cycfg_connectivity(void) +void init_cycfg_routing(void) { HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.h similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.h index a8554f2843..76a886ce97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.h @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.h +* File Name: cycfg_routing.h * * Description: * Establishes all necessary connections between hardware elements. @@ -22,16 +22,16 @@ * limitations under the License. ********************************************************************************/ -#if !defined(CYCFG_CONNECTIVITY_H) -#define CYCFG_CONNECTIVITY_H +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H #if defined(__cplusplus) extern "C" { #endif #include "cycfg_notices.h" -void init_cycfg_connectivity(void); - +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 @@ -73,4 +73,4 @@ void init_cycfg_connectivity(void); #endif -#endif /* CYCFG_CONNECTIVITY_H */ +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c index cf7ac0229a..74c28aba2c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c @@ -30,5 +30,5 @@ void init_cycfg_all(void) init_cycfg_peripherals(); init_cycfg_pins(); init_cycfg_platform(); - init_cycfg_connectivity(); + init_cycfg_routing(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h index 68bb40bf09..ac6033d2bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h @@ -34,7 +34,7 @@ extern "C" { #include "cycfg_peripherals.h" #include "cycfg_pins.h" #include "cycfg_platform.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h index 39f5ff9f5e..874eac99dc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h @@ -27,7 +27,7 @@ #include "cycfg_notices.h" #include "cy_gpio.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c index 9e81fbf418..9cd3f7692b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c @@ -119,7 +119,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit() { /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); } __STATIC_INLINE void Cy_SysClk_ClkPath0Init() { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h index 8db1d577b5..391f01a0be 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h @@ -35,7 +35,7 @@ extern "C" { #endif -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.c similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.c index d4beee5fd1..a1dadb2d0b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.c @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.c +* File Name: cycfg_routing.c * * Description: * Establishes all necessary connections between hardware elements. @@ -22,11 +22,11 @@ * limitations under the License. ********************************************************************************/ -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_device_headers.h" -void init_cycfg_connectivity(void) +void init_cycfg_routing(void) { HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h similarity index 70% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h index ad5cb15c79..92fbc92d25 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.h +* File Name: cycfg_routing.h * * Description: * Establishes all necessary connections between hardware elements. @@ -22,43 +22,43 @@ * limitations under the License. ********************************************************************************/ -#if !defined(CYCFG_CONNECTIVITY_H) -#define CYCFG_CONNECTIVITY_H +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H #if defined(__cplusplus) extern "C" { #endif #include "cycfg_notices.h" -void init_cycfg_connectivity(void); - +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 #define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK -#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA #if defined(__cplusplus) } #endif -#endif /* CYCFG_CONNECTIVITY_H */ +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c index cf7ac0229a..74c28aba2c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c @@ -30,5 +30,5 @@ void init_cycfg_all(void) init_cycfg_peripherals(); init_cycfg_pins(); init_cycfg_platform(); - init_cycfg_connectivity(); + init_cycfg_routing(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h index faa061e3c2..1709481df2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h @@ -35,7 +35,7 @@ extern "C" { #include "cycfg_peripherals.h" #include "cycfg_pins.h" #include "cycfg_platform.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h index 2170ac28c6..beadadac39 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h @@ -34,7 +34,7 @@ #include "cy_mcwdt.h" #include "cy_rtc.h" #include "cy_tcpwm_pwm.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h index 776325ec01..7496d6069e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h @@ -27,7 +27,7 @@ #include "cycfg_notices.h" #include "cy_gpio.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c index 8f247b0267..306a16a389 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c @@ -152,7 +152,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit() { /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); } __STATIC_INLINE void Cy_SysClk_ClkPath0Init() { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h index 4feda6f95f..76dfbef7bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h @@ -35,7 +35,7 @@ extern "C" { #endif -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c similarity index 86% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c index 12ffa2a389..8a1e655157 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.c +* File Name: cycfg_routing.c * * Description: * Establishes all necessary connections between hardware elements. @@ -22,7 +22,7 @@ * limitations under the License. ********************************************************************************/ -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_trigmux.h" @@ -30,16 +30,16 @@ #include "cy_device_headers.h" -void init_cycfg_connectivity(void) +void init_cycfg_routing(void) { - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT43, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT49, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT4, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT6, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h similarity index 88% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h index cf3efa8aa3..9d9b019eae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.h +* File Name: cycfg_routing.h * * Description: * Establishes all necessary connections between hardware elements. @@ -22,16 +22,16 @@ * limitations under the License. ********************************************************************************/ -#if !defined(CYCFG_CONNECTIVITY_H) -#define CYCFG_CONNECTIVITY_H +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H #if defined(__cplusplus) extern "C" { #endif #include "cycfg_notices.h" -void init_cycfg_connectivity(void); - +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 @@ -73,17 +73,17 @@ void init_cycfg_connectivity(void); #define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1 #define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3 #define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0 -#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT4 -#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3 +#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1 +#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4 #define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1 -#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT0 +#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3 #define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3 #define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7 -#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT6 +#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0 #if defined(__cplusplus) } #endif -#endif /* CYCFG_CONNECTIVITY_H */ +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c index cf7ac0229a..74c28aba2c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c @@ -30,5 +30,5 @@ void init_cycfg_all(void) init_cycfg_peripherals(); init_cycfg_pins(); init_cycfg_platform(); - init_cycfg_connectivity(); + init_cycfg_routing(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h index 68bb40bf09..ac6033d2bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h @@ -34,7 +34,7 @@ extern "C" { #include "cycfg_peripherals.h" #include "cycfg_pins.h" #include "cycfg_platform.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h index 9ab7fdc86c..2a1bfa380e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h @@ -35,7 +35,7 @@ #include "cy_mcwdt.h" #include "cy_rtc.h" #include "cy_tcpwm_pwm.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h index b8b6546bfb..d0709a2adc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h @@ -27,7 +27,7 @@ #include "cycfg_notices.h" #include "cy_gpio.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c index 9c14fabc8c..f0edc010bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c @@ -86,7 +86,7 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) } __STATIC_INLINE void Cy_SysClk_ClkBakInit() { - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); } __STATIC_INLINE void Cy_SysClk_ClkFastInit() { @@ -129,7 +129,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit() { /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); } __STATIC_INLINE void Cy_SysClk_ClkPath0Init() { @@ -175,12 +175,7 @@ void init_cycfg_platform(void) /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ Cy_SysLib_SetWaitStates(false, 150UL); #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) - if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) - { - Cy_SysLib_ResetBackupDomain(); - Cy_SysClk_IloDisable(); - Cy_SysClk_IloInit(); - } + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */){ Cy_SysLib_ResetBackupDomain(); } #endif #ifdef CY_CFG_PWR_ENABLED /* Configure power mode */ @@ -215,9 +210,6 @@ void init_cycfg_platform(void) Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); - #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); - #endif #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h index 9778631b74..aa4aeb6159 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h @@ -34,7 +34,7 @@ extern "C" { #endif -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.c similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.c index c389562da2..ae79008829 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.c @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.c +* File Name: cycfg_routing.c * * Description: * Establishes all necessary connections between hardware elements. @@ -22,11 +22,11 @@ * limitations under the License. ********************************************************************************/ -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_device_headers.h" -void init_cycfg_connectivity(void) +void init_cycfg_routing(void) { HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h index ff31e17f1e..191672e599 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.h +* File Name: cycfg_routing.h * * Description: * Establishes all necessary connections between hardware elements. @@ -22,16 +22,16 @@ * limitations under the License. ********************************************************************************/ -#if !defined(CYCFG_CONNECTIVITY_H) -#define CYCFG_CONNECTIVITY_H +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H #if defined(__cplusplus) extern "C" { #endif #include "cycfg_notices.h" -void init_cycfg_connectivity(void); - +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM0_LINE_COMPL1 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 @@ -72,4 +72,4 @@ void init_cycfg_connectivity(void); #endif -#endif /* CYCFG_CONNECTIVITY_H */ +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c index cf7ac0229a..74c28aba2c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c @@ -30,5 +30,5 @@ void init_cycfg_all(void) init_cycfg_peripherals(); init_cycfg_pins(); init_cycfg_platform(); - init_cycfg_connectivity(); + init_cycfg_routing(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h index faa061e3c2..1709481df2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h @@ -35,7 +35,7 @@ extern "C" { #include "cycfg_peripherals.h" #include "cycfg_pins.h" #include "cycfg_platform.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h index 6104f938c3..404b85be4a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h @@ -34,7 +34,7 @@ #include "cy_mcwdt.h" #include "cy_rtc.h" #include "cy_tcpwm_pwm.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h index 68fce9d2dd..f5e0b37d47 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h @@ -27,7 +27,7 @@ #include "cycfg_notices.h" #include "cy_gpio.h" -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #if defined(__cplusplus) extern "C" { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c index 341b5d7da8..877af05d9c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c @@ -104,7 +104,7 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() } __STATIC_INLINE void Cy_SysClk_ClkBakInit() { - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); } __STATIC_INLINE void Cy_SysClk_EcoInit() { @@ -166,7 +166,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit() { /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); } __STATIC_INLINE void Cy_SysClk_ClkPath0Init() { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h index 4feda6f95f..76dfbef7bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h @@ -35,7 +35,7 @@ extern "C" { #endif -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c index daf39a82a4..ce54f0f125 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.c +* File Name: cycfg_routing.c * * Description: * Establishes all necessary connections between hardware elements. @@ -22,7 +22,7 @@ * limitations under the License. ********************************************************************************/ -#include "cycfg_connectivity.h" +#include "cycfg_routing.h" #include "cy_trigmux.h" @@ -30,7 +30,7 @@ #include "cy_device_headers.h" -void init_cycfg_connectivity(void) +void init_cycfg_routing(void) { Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT5, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h index cc92c76813..8b3a102733 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h @@ -1,5 +1,5 @@ /******************************************************************************* -* File Name: cycfg_connectivity.h +* File Name: cycfg_routing.h * * Description: * Establishes all necessary connections between hardware elements. @@ -22,16 +22,16 @@ * limitations under the License. ********************************************************************************/ -#if !defined(CYCFG_CONNECTIVITY_H) -#define CYCFG_CONNECTIVITY_H +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H #if defined(__cplusplus) extern "C" { #endif #include "cycfg_notices.h" -void init_cycfg_connectivity(void); - +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 #define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 @@ -90,4 +90,4 @@ void init_cycfg_connectivity(void); #endif -#endif /* CYCFG_CONNECTIVITY_H */ +#endif /* CYCFG_ROUTING_H */ From c0a6e9588ada0ce22a276d0f4c2027badbb9334d Mon Sep 17 00:00:00 2001 From: Oren Cohen Date: Tue, 19 Feb 2019 20:45:36 +0200 Subject: [PATCH 090/109] Add config header to assembly compilation ARMC6 was not including mbed_config.h when compiling assembly files --- tools/toolchains/arm.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index dd87038aa0..874f488dc0 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -481,14 +481,13 @@ class ARMC6(ARM_STD): def get_compile_options(self, defines, includes, for_asm=False): opts = ['-D%s' % d for d in defines] opts.extend(["-I%s" % i for i in includes if i]) + config_header = self.get_config_header() + if config_header: + opts.extend(self.get_config_option(config_header)) if for_asm: return ["--cpreproc", "--cpreproc_opts=%s" % ",".join(self.flags['common'] + opts)] - else: - config_header = self.get_config_header() - if config_header: - opts.extend(self.get_config_option(config_header)) - return opts + return opts @hook_tool def assemble(self, source, object, includes): From 2a7f5e21afe93b6ca395a6e69aa78bf6bf0cac27 Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Tue, 5 Feb 2019 11:49:34 +0200 Subject: [PATCH 091/109] nRF52 serial: Tighten/simplify atomics Use new atomics (exchange, load, store and bool types) to simplify and improve the atomics in the nRF52 serial HAL. * Ensure mutexes are released last and atomically when done done inside a critical section. * Compare-and-swap is not required for the spinlock - exchange is sufficient. (Not clear a spinlock is needed anyway, but left in). * Remove unneeded volatile, and make mutexes bool. --- .../TARGET_NRF5x/TARGET_NRF52/serial_api.c | 40 +++++++++---------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c index dbfd41f749..4ac70d7e03 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c @@ -138,8 +138,8 @@ typedef struct { uint8_t buffer[NUMBER_OF_BANKS][DMA_BUFFER_SIZE]; uint32_t usage_counter; uint8_t tx_data; - volatile uint8_t tx_in_progress; - volatile uint8_t rx_in_progress; + bool tx_in_progress; + bool rx_in_progress; bool tx_asynch; bool rx_asynch; bool callback_posted; @@ -252,7 +252,7 @@ static void nordic_nrf5_uart_callback_handler(uint32_t instance) static void nordic_nrf5_uart_event_handler_endtx(int instance) { /* Release mutex. As the owner this call is safe. */ - nordic_nrf5_uart_state[instance].tx_in_progress = 0; + core_util_atomic_store_bool(&nordic_nrf5_uart_state[instance].tx_in_progress, false); /* Check if callback handler and Tx event mask is set. */ uart_irq_handler callback = (uart_irq_handler) nordic_nrf5_uart_state[instance].owner->handler; @@ -275,8 +275,8 @@ static void nordic_nrf5_uart_event_handler_endtx(int instance) static void nordic_nrf5_uart_event_handler_endtx_asynch(int instance) { /* Set Tx done and reset Tx mode to be not asynchronous. */ - nordic_nrf5_uart_state[instance].tx_in_progress = 0; nordic_nrf5_uart_state[instance].tx_asynch = false; + core_util_atomic_store_bool(&nordic_nrf5_uart_state[instance].tx_in_progress, false); /* Cast handler to callback function pointer. */ void (*callback)(void) = (void (*)(void)) nordic_nrf5_uart_state[instance].owner->tx_handler; @@ -482,8 +482,8 @@ static void nordic_nrf5_uart_event_handler_rxstarted(int instance) static void nordic_nrf5_uart_event_handler_endrx_asynch(int instance) { /* Set Rx done and reset Rx mode to be not asynchronous. */ - nordic_nrf5_uart_state[instance].rx_in_progress = 0; nordic_nrf5_uart_state[instance].rx_asynch = false; + core_util_atomic_store_bool(&nordic_nrf5_uart_state[instance].rx_in_progress, false); /* Cast handler to callback function pointer. */ void (*callback)(void) = (void (*)(void)) nordic_nrf5_uart_state[instance].owner->rx_handler; @@ -1410,7 +1410,7 @@ int serial_writable(serial_t *obj) int instance = uart_object->instance; - return ((nordic_nrf5_uart_state[instance].tx_in_progress == 0) && + return (!core_util_atomic_load_bool(&nordic_nrf5_uart_state[instance].tx_in_progress) && (nrf_uarte_event_extra_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY))); } @@ -1449,16 +1449,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx /** * tx_in_progress acts like a mutex to ensure only one transmission can be active at a time. - * The flag is modified using the atomic compare-and-set function. + * The flag is modified using the atomic exchange function - only proceed when we see the + * flag clear and we set it to true. */ - bool mutex = false; + bool old_mutex; do { - uint8_t expected = 0; - uint8_t desired = 1; - - mutex = core_util_atomic_cas_u8((uint8_t *) &nordic_nrf5_uart_state[instance].tx_in_progress, &expected, desired); - } while (mutex == false); + old_mutex = core_util_atomic_exchange_bool(&nordic_nrf5_uart_state[instance].tx_in_progress, true); + } while (old_mutex == true); /* State variables. */ int result = 0; @@ -1575,16 +1573,14 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /** * rx_in_progress acts like a mutex to ensure only one asynchronous reception can be active at a time. - * The flag is modified using the atomic compare-and-set function. + * The flag is modified using the atomic exchange function - only proceed when we see the + * flag clear and we set it to true. */ - bool mutex = false; + bool old_mutex; do { - uint8_t expected = 0; - uint8_t desired = 1; - - mutex = core_util_atomic_cas_u8((uint8_t *) &nordic_nrf5_uart_state[instance].rx_in_progress, &expected, desired); - } while (mutex == false); + old_mutex = core_util_atomic_exchange_bool(&nordic_nrf5_uart_state[instance].rx_in_progress, true); + } while (old_mutex == true); /* Store callback handler, mask and reset event value. */ obj->serial.rx_handler = handler; @@ -1663,8 +1659,8 @@ void serial_tx_abort_asynch(serial_t *obj) nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDTX); /* Reset Tx flags. */ - nordic_nrf5_uart_state[instance].tx_in_progress = 0; nordic_nrf5_uart_state[instance].tx_asynch = false; + nordic_nrf5_uart_state[instance].tx_in_progress = false; /* Force reconfiguration. */ obj->serial.update = true; @@ -1691,8 +1687,8 @@ void serial_rx_abort_asynch(serial_t *obj) core_util_critical_section_enter(); /* Reset Rx flags. */ - nordic_nrf5_uart_state[obj->serial.instance].rx_in_progress = 0; nordic_nrf5_uart_state[obj->serial.instance].rx_asynch = false; + nordic_nrf5_uart_state[obj->serial.instance].rx_in_progress = false; obj->serial.rx_asynch = false; /* Force reconfiguration. */ From 79d8b3a9c2c9625a1876066443818d681aa4fa95 Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Wed, 20 Feb 2019 12:29:23 +0200 Subject: [PATCH 092/109] PSOC6: fix port_write API Fix port_write API to correctly shift the passed value. This allows the reference application provided in PortOut docs to work corectly with arbitrary LED_MASK. https://os.mbed.com/docs/mbed-os/v5.11/apis/portout.html The fix applies to both PSOC6 and PSOC6_FUTURE HAL implementations. --- targets/TARGET_Cypress/TARGET_PSOC6/port_api.c | 2 +- targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/port_api.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/port_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/port_api.c index b1d849fd9c..ddcc0bc5d5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/port_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/port_api.c @@ -109,8 +109,8 @@ void port_write(port_t *obj, int value) for (pin = 0; pin < 8; ++pin) { if (obj->mask & (1 << pin)) { Cy_GPIO_Write(obj->port, pin, value & 0x1); - value >>= 1; } + value >>= 1; } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/port_api.c b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/port_api.c index 5e124dd5b4..9fce69a494 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/port_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/port_api.c @@ -105,8 +105,8 @@ void port_write(port_t *obj, int value) for (pin = 0; pin < 8; ++pin) { if (obj->mask & (1 << pin)) { Cy_GPIO_Write(obj->port, pin, value & 0x1); - value >>= 1; } + value >>= 1; } } } From f329c7bf709922c5829b1cac42c068390ff2a1d4 Mon Sep 17 00:00:00 2001 From: Conrad Braam Date: Wed, 20 Feb 2019 13:54:38 +0000 Subject: [PATCH 093/109] adv builder helper now returns an object --- features/FEATURE_BLE/ble/gap/AdvertisingDataSimpleBuilder.h | 1 + 1 file changed, 1 insertion(+) diff --git a/features/FEATURE_BLE/ble/gap/AdvertisingDataSimpleBuilder.h b/features/FEATURE_BLE/ble/gap/AdvertisingDataSimpleBuilder.h index 9c529f4a09..0358672e5b 100644 --- a/features/FEATURE_BLE/ble/gap/AdvertisingDataSimpleBuilder.h +++ b/features/FEATURE_BLE/ble/gap/AdvertisingDataSimpleBuilder.h @@ -158,6 +158,7 @@ public: AdvertisingDataSimpleBuilder &setAdvertisingInterval(adv_interval_t interval) { MBED_ASSERT(_builder.setAdvertisingInterval(interval) == BLE_ERROR_NONE); + return *this; } /** From 8fa17b8f3f8ad51de8cf558c0cf061ed550e3f43 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Wed, 20 Feb 2019 09:24:12 +0000 Subject: [PATCH 094/109] license: use .md extension Using Github feature to show markdown documents. --- LICENSE => LICENSE.md | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename LICENSE => LICENSE.md (100%) diff --git a/LICENSE b/LICENSE.md similarity index 100% rename from LICENSE rename to LICENSE.md From 9f049138be1ee4cfa3a34eb76c3d77cb5d7bb893 Mon Sep 17 00:00:00 2001 From: kegilbert Date: Wed, 20 Feb 2019 17:52:28 -0600 Subject: [PATCH 095/109] Change EventFlag timeout paramter Matches rest of RTOS class timeout parameters by using the unit name. Remove ambigious statement in reference to 0 ms being no-timeout as a timeout of 0 causes the function to not block and return immediately (osWaitForever is used as no timeout as it will wait forever) --- rtos/EventFlags.cpp | 12 ++++++------ rtos/EventFlags.h | 14 +++++++------- rtos/Mail.h | 2 +- rtos/Mutex.h | 4 ++-- rtos/Queue.h | 2 +- rtos/Semaphore.h | 2 +- rtos/ThisThread.h | 4 ++-- rtos/Thread.h | 2 +- 8 files changed, 21 insertions(+), 21 deletions(-) diff --git a/rtos/EventFlags.cpp b/rtos/EventFlags.cpp index 3d6b79321f..faa3057e3b 100644 --- a/rtos/EventFlags.cpp +++ b/rtos/EventFlags.cpp @@ -62,14 +62,14 @@ uint32_t EventFlags::get() const return osEventFlagsGet(_id); } -uint32_t EventFlags::wait_all(uint32_t flags, uint32_t timeout, bool clear) +uint32_t EventFlags::wait_all(uint32_t flags, uint32_t millisec, bool clear) { - return wait(flags, osFlagsWaitAll, timeout, clear); + return wait(flags, osFlagsWaitAll, millisec, clear); } -uint32_t EventFlags::wait_any(uint32_t flags, uint32_t timeout, bool clear) +uint32_t EventFlags::wait_any(uint32_t flags, uint32_t millisec, bool clear) { - return wait(flags, osFlagsWaitAny, timeout, clear); + return wait(flags, osFlagsWaitAny, millisec, clear); } EventFlags::~EventFlags() @@ -77,13 +77,13 @@ EventFlags::~EventFlags() osEventFlagsDelete(_id); } -uint32_t EventFlags::wait(uint32_t flags, uint32_t opt, uint32_t timeout, bool clear) +uint32_t EventFlags::wait(uint32_t flags, uint32_t opt, uint32_t millisec, bool clear) { if (clear == false) { opt |= osFlagsNoClear; } - return osEventFlagsWait(_id, flags, opt, timeout); + return osEventFlagsWait(_id, flags, opt, millisec); } } diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index a448807459..bac58ea588 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -87,23 +87,23 @@ public: /** Wait for all of the specified event flags to become signaled. @param flags the flags to wait for (default: 0 -- no flags). - @param timeout timeout value or 0 in case of no time-out (default: osWaitForever). + @param millisec timeout value (default: osWaitForever). @param clear clear specified event flags after waiting for them (default: true). @return event flags before clearing or error code if highest bit set (see @a osFlagsError for details). - @note You may call this function from ISR context if the timeout parameter is set to 0. + @note You may call this function from ISR context if the millisec parameter is set to 0. */ - uint32_t wait_all(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true); + uint32_t wait_all(uint32_t flags = 0, uint32_t millisec = osWaitForever, bool clear = true); /** Wait for any of the specified event flags to become signaled. @param flags the flags to wait for (default: 0 -- no flags). - @param timeout timeout value or 0 in case of no timeout (default: osWaitForever). + @param millisec timeout value (default: osWaitForever). @param clear clear specified event flags after waiting for them (default: true). @return event flags before clearing or error code if highest bit set (see @a osFlagsError for details). - @note This function may be called from ISR context if the timeout parameter is set to 0. + @note This function may be called from ISR context if the millisec parameter is set to 0. */ - uint32_t wait_any(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true); + uint32_t wait_any(uint32_t flags = 0, uint32_t millisec = osWaitForever, bool clear = true); /** EventFlags destructor. @@ -113,7 +113,7 @@ public: private: void constructor(const char *name = NULL); - uint32_t wait(uint32_t flags, uint32_t opt, uint32_t timeout, bool clear); + uint32_t wait(uint32_t flags, uint32_t opt, uint32_t millisec, bool clear); osEventFlagsId_t _id; mbed_rtos_storage_event_flags_t _obj_mem; }; diff --git a/rtos/Mail.h b/rtos/Mail.h index 4f8cc7cac1..70f6380d98 100644 --- a/rtos/Mail.h +++ b/rtos/Mail.h @@ -131,7 +131,7 @@ public: /** Get a mail from the queue. * - * @param millisec Timeout value or 0 in case of no timeout (default: osWaitForever). + * @param millisec Timeout value (default: osWaitForever). * * @return Event that contains mail information or error code. * @retval osEventMessage Message received. diff --git a/rtos/Mutex.h b/rtos/Mutex.h index a364b1c8dc..a4955a54c6 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -95,7 +95,7 @@ public: @deprecated Do not use this function. This function has been replaced with lock(), trylock() and trylock_for() functions. - @param millisec timeout value or 0 in case of no time-out. + @param millisec timeout value. @return status code that indicates the execution status of the function: @a osOK the mutex has been obtained. @a osErrorTimeout the mutex could not be obtained in the given time. @@ -117,7 +117,7 @@ public: bool trylock(); /** Try to lock the mutex for a specified time - @param millisec timeout value or 0 in case of no time-out. + @param millisec timeout value. @return true if the mutex was acquired, false otherwise. @note the underlying RTOS may have a limit to the maximum wait time due to internal 32-bit computations, but this is guaranteed to work if the diff --git a/rtos/Queue.h b/rtos/Queue.h index d204a75696..ff258915bf 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -167,7 +167,7 @@ public: * share the same priority level, they are retrieved in first-in, first-out * (FIFO) order. * - * @param millisec Timeout value or 0 in case of no time-out. + * @param millisec Timeout value. * (default: osWaitForever). * * @return Event information that includes the message in event. Message diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index 0bcd788de9..49e0f1e833 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -60,7 +60,7 @@ public: Semaphore(int32_t count, uint16_t max_count); /** Wait until a Semaphore resource becomes available. - @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). + @param millisec timeout value. (default: osWaitForever). @return number of available tokens, before taking one; or -1 in case of incorrect parameters @note You may call this function from ISR context if the millisec parameter is set to 0. diff --git a/rtos/ThisThread.h b/rtos/ThisThread.h index c0104fc1e0..ed12fd406c 100644 --- a/rtos/ThisThread.h +++ b/rtos/ThisThread.h @@ -105,7 +105,7 @@ uint32_t flags_wait_any(uint32_t flags, bool clear = true); /** Wait for all of the specified Thread Flags to become signaled for the current thread. @param flags specifies the flags to wait for - @param millisec timeout value or 0 in case of no time-out. + @param millisec timeout value. @param clear whether to clear the specified flags after waiting for them. (default: true) @return actual thread flags before clearing, which may not satisfy the wait @note You cannot call this function from ISR context. @@ -129,7 +129,7 @@ uint32_t flags_wait_all_until(uint32_t flags, uint64_t millisec, bool clear = tr /** Wait for any of the specified Thread Flags to become signaled for the current thread. @param flags specifies the flags to wait for - @param millisec timeout value or 0 in case of no time-out. + @param millisec timeout value. @param clear whether to clear the specified flags after waiting for them. (default: true) @return actual thread flags before clearing, which may not satisfy the wait @note You cannot call this function from ISR context. diff --git a/rtos/Thread.h b/rtos/Thread.h index 34933e8bc2..34da08aa24 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -414,7 +414,7 @@ public: /** Wait for one or more Thread Flags to become signaled for the current RUNNING thread. @param signals wait until all specified signal flags are set or 0 for any single signal flag. - @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). + @param millisec timeout value. (default: osWaitForever). @return event flag information or error code. @note if @a millisec is set to 0 and flag is no set the event carries osOK value. @note You cannot call this function from ISR context. From b87ee6ca73ccb5ee582951fc33b7adf2ab755fe0 Mon Sep 17 00:00:00 2001 From: Guillermo Alonso Date: Wed, 20 Feb 2019 12:10:53 +0100 Subject: [PATCH 096/109] Added new target RHOMBIO_L476DMW1K --- .../PeripheralNames.h | 98 +++++ .../TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c | 380 ++++++++++++++++++ .../TARGET_RHOMBIO_L476DMW1K/PinNames.h | 373 +++++++++++++++++ .../TARGET_RHOMBIO_L476DMW1K/system_clock.c | 370 +++++++++++++++++ targets/targets.json | 35 ++ 5 files changed, 1256 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h new file mode 100644 index 0000000000..a68464b809 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +//#define STDIO_UART_TX PA_2 +//#define STDIO_UART_RX PA_3 +//#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE +} CANName; + +typedef enum { + QSPI_1 = (int)QSPI_R_BASE, +} QSPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c new file mode 100644 index 0000000000..06eb43ccaa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c @@ -0,0 +1,380 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // rhomb.io AD0 + {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // rhomb.io AD0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // rhomb.io AD1 + {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // rhomb.io AD1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // rhomb.io UART-A_TXD + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // rhomb.io UART-A_TXD + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // rhomb.io UART-A_RXD + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // rhomb.io UART-A_RXD + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // rhomb.io AD2 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // rhomb.io AD2 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // rhomb.io SPIA_CLK + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // rhomb.io SPIA_CLK + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // rhomb.io SPIA_MISO + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // rhomb.io SPIA_MISO + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // rhomb.io SPIA_MOSI + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // rhomb.io SPIA_MOSI + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // rhomb.io AD3 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // rhomb.io AD3 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 // rhomb.io NMI + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 // rhomb.io NMI + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // rhomb.io AD5 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // rhomb.io AD5 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // rhomb.io AD5 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // rhomb.io AD4 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // rhomb.io AD4 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // rhomb.io AD4 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // rhomb.io CAPT1 (R19 must be populated) + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // rhomb.io CAPT1 (R19 must be populated) + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // rhomb.io CAPT1 (R19 must be populated) + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // rhomb.io CAPT0 (R18 must be populated) + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // rhomb.io CAPT0 (R18 must be populated) + {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 // rhomb.io CAPT0 (R18 must be populated) + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // rhomb.io AD8 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // rhomb.io AD8 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // rhomb.io AD7 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // rhomb.io AD7 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // rhomb.io AD2 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // rhomb.io SPIA_CLK + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io INT1 + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io I2C-A_SDA // Connected to ATECC608A + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io QSPI_CS0 / + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io SPI-A_CS1 + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // rhomb.io AD4 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io SPI-A_CS0 + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io I2C-A_SCL // Connected to ATECC608A + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io IO2 + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io SPI-A_CS2 + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // rhomb.io AD5 + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io AD0 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // rhomb.io AD0 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // rhomb.io AD1 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // rhomb.io AD1 + {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // rhomb.io AD1 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // rhomb.io UART-A_TXD +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // rhomb.io UART-A_TXD + {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // rhomb.io UART-A_TXD + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // rhomb.io UART-A_RXD +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // rhomb.io UART-A_RXD + {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // rhomb.io UART-A_RXD + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io SPI-A_CLK + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // rhomb.io SPI-A_CLK + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io SPI-A_MISO + {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io SPI-A_MISO + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io SPI-A_MOSI + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io SPI-A_MOSI + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // rhomb.io SPI-A_MOSI + {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io SPI-A_MOSI + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // rhomb.io IO3 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // rhomb.io IO4 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // rhomb.io OTG_ID + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // rhomb.io OTG_N + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io INT2 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io AD3 + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io AD3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // rhomb.io AD3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io NMI + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io NMI + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // rhomb.io NMI + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // rhomb.io INT0 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io IO1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io IO0 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // rhomb.io SPI-A_CS0 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // rhomb.io SPI-A_CS0 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // rhomb.io INT1 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // rhomb.io INT1 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // rhomb.io I2C-A_SCL + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io I2C-A_SCL + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // rhomb.io I2C-A_SDA + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io I2C-A_SDA + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // rhomb.io IO2 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // rhomb.io QSPI_CS0 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io SPI-A_CS2 + {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // rhomb.io SPI-A_CS2 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io SPI-A_CS1 + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // rhomb.io SPI-A_CS1 + {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // rhomb.io SPI-A_CS1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io IO7 + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // rhomb.io IO7 + {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // rhomb.io IO7 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io PWM3 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // rhomb.io PWM3 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io PWM0 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // rhomb.io PWM0 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io SDIO_DATA0 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // rhomb.io SDIO_DATA0 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io SDIO_DATA1 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // rhomb.io SDIO_DATA1 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // rhomb.io IO12 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // rhomb.io IO13 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // rhomb.io PWM2 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // rhomb.io SDIO_CDN + {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io RESET_OUT + {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io USB_SWITCH + {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io SAI-A_SDO + {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io SAI-A_LRCLK + {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io SAI-A_BCLK + {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io SAI-A_SDI + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io IO5 + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // rhomb.io PWM1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io QSPI_CLK + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // rhomb.io QSPI_MEM_CS + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io QSPI_IO0 + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // rhomb.io QSPI_IO1 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // rhomb.io QSPI_IO2 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io AD0 + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_TXD + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io IO4 + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io SPI-A_CS0 + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO2 + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io QSPI_CS0 + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io AD4 + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io COMP-A_N + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_DATA2 + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io SDIO_DATA2 + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io SDIO_CLK + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-B_TXD + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io UART-C_TXD + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io AD1 + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_RXD + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_ID + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io INT1 + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io IO2 + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI_CS0 + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io AD5 + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io COMP-A_P + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_DATA3 + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io SDIO_DATA3 + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io SDIO_CMD + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-B_RXD + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io UART-C_RXD + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io AD1 + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_P + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io INT2 + {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io NMI + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io INT0 + {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io IO1 + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io 1WIRE // Connected to DS28E05X + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_CS1 + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_CMD + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_RTS + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO12 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io AD0 + {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_MISO + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_N + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io IO1 + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io IO0 + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io INT1 + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_CS2 + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io SPI-A_CS2 + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_CTS + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO11 + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_MOSI + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io IO0 + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io IO0 + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO7 + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO14 + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_CLK + {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io UART-A_RTS + {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_MISO + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io IO1 + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io IO1 + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io SPI-A_CS1 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO15 + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_DATA3 + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io UART-A_CTS + {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_CLK + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io INT0 + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io INT0 + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO2 + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io SPI-A_CS2 + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_DATA2 + {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io CAN-A_TX + {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io AD2 + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io AD2 + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io INT2 + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io INT2 + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io I2C-A_SDA + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io 1WIRE // Connected to DS28E05X + {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io CAN-A_RX + {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO0 + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io OTG_N + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io I2C-A_SCL + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io CAN-A_RX + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io OTG_P + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io I2C-A_SDA + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io CAN-A_TX + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io NMI + {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io QSPI_IO0 // Connected to W25Q128JVPIQ + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io AD3 + {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io QSPI_IO1 // Connected to W25Q128JVPIQ + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io SPI_A_MOSI + {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io QSPI_IO2 // Connected to W25Q128JVPIQ + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io SPI_A_MISO + {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io QSPI_IO3 // Connected to W25Q128JVPIQ + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io IO2 + {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io QSPI_CLK // Connected to W25Q128JVPIQ + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_CS0 + {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_MEM_CS // Connected to W25Q128JVPIQ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h new file mode 100644 index 0000000000..a245841779 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h @@ -0,0 +1,373 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0_ALT0 = PA_0 | ALT0, + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13 | ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, + + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, + PC_2 = 0x22, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, + PC_3 = 0x23, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // STDIO for console print +/*#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PC_4, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PC_5, +#endif*/ + + STDIO_UART_TX = PC_4, + STDIO_UART_RX = PC_5, + + // Generic signals namings + LED1 = PC_7, // LED Green + LED2 = PC_7, // LED Green + + USER_BUTTON = PB_1, + // Standardized button names + BUTTON1 = USER_BUTTON, + + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, + + I2C_SCL = PB_8, + I2C_SDA = PB_9, + SPI_MOSI = PA_7, + SPI_MISO = PA_6, + SPI_SCK = PA_5, + SPI_CS = PB_6, + PWM_OUT = PC_7, + + /**** USB pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, +/* SYS_PVD_IN = PB_7, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED1 = PE_4, + SYS_TRACED2 = PE_5, + SYS_TRACED3 = PE_6, + SYS_WKUP1 = PA_0, + SYS_WKUP2 = PC_13, + SYS_WKUP3 = PE_6, + SYS_WKUP4 = PA_2, + SYS_WKUP5 = PC_5,*/ + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = PE_12, + QSPI_FLASH1_IO1 = PE_13, + QSPI_FLASH1_IO2 = PE_14, + QSPI_FLASH1_IO3 = PE_15, + QSPI_FLASH1_SCK = PE_10, + QSPI_FLASH1_CSN = PE_11, + + // rhomb.io system namings //......................... + NMI = PB_1, + INT0 = PB_3, + INT1 = PB_7, + INT2 = PA_15, + + IO0 = PB_5, + IO1 = PB_4, + IO2 = PB_10, + IO3 = PA_8, + IO4 = PA_9, + IO5 = PE_8, + IO6 = PE_7, + IO7 = PB_15, + + IO8 = PC_13, + IO9 = PD_7, + IO10 = PD_10, + IO11 = PD_11, + IO12 = PD_12, + IO13 = PD_13, + IO14 = PC_3, + IO15 = PC_2, + + //LED0 = PC_7, + + PWM0 = PC_7, + PWM1 = PE_9, + PWM2 = PD_14, + PWM3 = PC_6, + PWM4 = PB_2, + + UART_A_RXD = PA_3, + UART_A_TXD = PA_2, + UART_A_CTS = PD_3, + UART_A_RTS = PD_4, + + UART_B_RXD = PD_6, + UART_B_TXD = PD_5, + + UART_C_RXD = PD_9, + UART_C_TXD = PD_8, + + I2C_A_SDA = PB_9, + I2C_A_SCL = PB_8, + I2C_B_SDA = PB_14, // R14 must be populated/closed (default is open) + I2C_B_SCL = PB_13, // R15 must be populated/closed (default is open) + + SPI_A_MOSI = PA_7, + SPI_A_MISO = PA_6, + SPI_A_CLK = PA_5, + SPI_A_CS0 = PB_6, + SPI_A_CS1 = PB_14, + SPI_A_CS2 = PB_13, + + QSPI_IO0 = PE_12, + QSPI_IO1 = PE_13, + QSPI_IO2 = PE_14, + QSPI_IO3 = PE_15, + QSPI_CLK = PE_10, + QSPI_CS0 = PB_11, + QSPI_MEM_CS = PE_11, + + _1WIRE = PB_12, + CAN_A_RX = PD_0, + CAN_A_TX = PD_1, + + SDIO_DATAO = PC_8, + SDIO_DATA1 = PC_9, + SDIO_DATA2 = PC_10, + SDIO_DATA3 = PC_11, + SDIO_CLK = PC_12, + SDIO_CMD = PD_2, + SDIO_CDN = PD_15, + + SAI_A_BCLK = PE_5, + SAI_A_LRCLK = PE_4, + SAI_A_SDI = PE_6, + SAI_A_SDO = PE_3, + SAI_A_MCLK = PE_2, + + OTG_P = PA_12, + OTG_N = PA_11, + OTG_ID = PA_10, + + AD0 = PA_0, + AD1 = PA_1, + AD2 = PA_4, + AD3 = PB_0, + AD4 = PC_1, + AD5 = PC_0, + //AD6 not used + AD7 = PC_5, + AD8 = PC_4, + + COMP_A_P = PC_5, + COMP_A_N = PC_4, + + CAPT0 = PC_3, // R18 must be populated/closed (default is open) + CAPT1 = PC_2, // R19 must be populated/closed (default is open) + + SWDIO = PA_13, + SWCLK = PA_14, + + RSTOUT = PE_0, + + // Not connected + NC = (int)0xFFFFFFFF + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c new file mode 100644 index 0000000000..585c434d34 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c @@ -0,0 +1,370 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32l4xx.h" +#include "nvic_addr.h" +#include "mbed_error.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock +#define USE_PLL_MSI 0x1 // Use MSI internal clock + +#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +uint8_t SetSysClock_PLL_MSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + /* 4- If fail start with MSI clock */ + if (SetSysClock_PLL_MSI() == 0) +#endif + { + { + error("SetSysClock failed\n"); + } + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + +#if MBED_CONF_TARGET_LSE_AVAILABLE + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ + HAL_RCCEx_DisableLSECSS(); +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ + RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ + RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ + RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ + RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + +#if MBED_CONF_TARGET_LSE_AVAILABLE + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ \ No newline at end of file diff --git a/targets/targets.json b/targets/targets.json index d1286ffea5..f39d40bce2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3950,6 +3950,41 @@ "device_name": "STM32L476VG", "bootloader_supported": true }, + "RHOMBIO_L476DMW1K": { + "components_add": ["FLASHIAP"], + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_MSI", + "macro_name": "CLOCK_SOURCE" + }, + "lpticker_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", + "value": 1 + } + }, + "overrides": { "lpticker_delay_ticks": 4 }, + "detect_code": ["1500"], + "macros_add": [ + "MBED_TICKLESS", + "USBHOST_OTHER", + "TWO_RAM_REGIONS" + ], + "device_has_add": [ + "ANALOGOUT", + "CAN", + "SERIAL_FC", + "TRNG", + "FLASH", + "MPU" + ], + "release_versions": ["2", "5"], + "device_name": "STM32L476VG", + "bootloader_supported": true + }, "MTS_MDOT_F405RG": { "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", From 3c223d95baf86c7c00833c688f77abced4e01932 Mon Sep 17 00:00:00 2001 From: Guillermo Alonso Date: Wed, 20 Feb 2019 17:48:07 +0100 Subject: [PATCH 097/109] added licence identifier texts --- .../TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h | 2 ++ .../TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c | 2 ++ .../TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h index a68464b809..a98f3bfbdd 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h @@ -1,4 +1,6 @@ /* mbed Microcontroller Library + +* SPDX-License-Identifier: Apache-2.0 ******************************************************************************* * Copyright (c) 2015, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c index 06eb43ccaa..da79b829ad 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c @@ -1,4 +1,6 @@ /* mbed Microcontroller Library + +* SPDX-License-Identifier: Apache-2.0 ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h index a245841779..d6c784fdaa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h @@ -1,4 +1,6 @@ /* mbed Microcontroller Library + +* SPDX-License-Identifier: Apache-2.0 ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. From c31635fa059b79c3d0433f8d7e5bf87d4cfff8d9 Mon Sep 17 00:00:00 2001 From: Guillermo Alonso Date: Thu, 21 Feb 2019 11:55:41 +0100 Subject: [PATCH 098/109] Change in license identifier, removed commented dead code Change in license identifier Removed commented dead code Removed some tab space --- .../PeripheralNames.h | 10 ++---- .../TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c | 4 +-- .../TARGET_RHOMBIO_L476DMW1K/PinNames.h | 34 +++---------------- .../TARGET_RHOMBIO_L476DMW1K/system_clock.c | 4 ++- 4 files changed, 13 insertions(+), 39 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h index a98f3bfbdd..7d462c0ffe 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralNames.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library - -* SPDX-License-Identifier: Apache-2.0 - ******************************************************************************* + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************1*********************** * Copyright (c) 2015, STMicroelectronics * All rights reserved. * @@ -57,10 +57,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -//#define STDIO_UART_TX PA_2 -//#define STDIO_UART_RX PA_3 -//#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c index da79b829ad..982c0e2afa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - -* SPDX-License-Identifier: Apache-2.0 + * + * SPDX-License-Identifier: BSD-3-Clause ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h index d6c784fdaa..f7266a20da 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PinNames.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - -* SPDX-License-Identifier: Apache-2.0 + * + * SPDX-License-Identifier: BSD-3-Clause ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. @@ -185,24 +185,13 @@ typedef enum { ADC_VBAT = 0xF2, // STDIO for console print -/*#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PC_4, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PC_5, -#endif*/ - STDIO_UART_TX = PC_4, STDIO_UART_RX = PC_5, // Generic signals namings LED1 = PC_7, // LED Green LED2 = PC_7, // LED Green - + USER_BUTTON = PB_1, // Standardized button names BUTTON1 = USER_BUTTON, @@ -237,17 +226,6 @@ typedef enum { SYS_JTDO_SWO = PB_3, SYS_JTMS_SWDIO = PA_13, SYS_JTRST = PB_4, -/* SYS_PVD_IN = PB_7, - SYS_TRACECLK = PE_2, - SYS_TRACED0 = PE_3, - SYS_TRACED1 = PE_4, - SYS_TRACED2 = PE_5, - SYS_TRACED3 = PE_6, - SYS_WKUP1 = PA_0, - SYS_WKUP2 = PC_13, - SYS_WKUP3 = PE_6, - SYS_WKUP4 = PA_2, - SYS_WKUP5 = PC_5,*/ /**** QSPI FLASH pins ****/ QSPI_FLASH1_IO0 = PE_12, @@ -280,8 +258,6 @@ typedef enum { IO13 = PD_13, IO14 = PC_3, IO15 = PC_2, - - //LED0 = PC_7, PWM0 = PC_7, PWM1 = PE_9, @@ -348,11 +324,11 @@ typedef enum { AD3 = PB_0, AD4 = PC_1, AD5 = PC_0, - //AD6 not used + // AD6 not used AD7 = PC_5, AD8 = PC_4, - COMP_A_P = PC_5, + COMP_A_P = PC_5, COMP_A_N = PC_4, CAPT0 = PC_3, // R18 must be populated/closed (default is open) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c index 585c434d34..c5daf4963e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited +* Copyright (c) 2006-2019 ARM Limited +* +* SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. From 49d5a4a57fd756641323d622daaad16c8c568bd3 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Wed, 20 Feb 2019 14:40:39 +0000 Subject: [PATCH 099/109] Adding STM32_L475 as a new MTB target --- .../TARGET_MTB_STM_L475/PeripheralNames.h | 94 +++++ .../TARGET_MTB_STM_L475/PeripheralPins.c | 368 +++++++++++++++++ .../TARGET_MTB_STM_L475/PinNames.h | 321 +++++++++++++++ .../TARGET_MTB_STM_L475/system_clock.c | 370 ++++++++++++++++++ targets/targets.json | 29 ++ 5 files changed, 1182 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h new file mode 100644 index 0000000000..04b09f6539 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h @@ -0,0 +1,94 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE +} CANName; + +typedef enum { + QSPI_1 = (int)QSPI_R_BASE, +} QSPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c new file mode 100644 index 0000000000..31119421e5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c @@ -0,0 +1,368 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to ARD_D1 [UART4_TX] + {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // Connected to ARD_D1 [UART4_TX] + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to ARD_D0 [UART4_RX] + {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // Connected to ARD_D0 [UART4_RX] + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to ARD_D10 [SPI_SSN] + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to ARD_D10 [SPI_SSN] + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to ARD_D4 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to ARD_D4 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to ARD_D7 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // Connected to ARD_D7 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to ARD_D13 [SPI1_SCK] + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to ARD_D13 [SPI1_SCK] + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to ARD_D12 [SPI1_MISO] + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to ARD_D12 [SPI1_MISO] + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to ARD_D11 [SPI1_MOSI] + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to ARD_D11 [SPI1_MOSI] + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to ARD_D3 [INT_EXT10] + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to ARD_D3 [INT_EXT10] + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 // Connected to ARD_D6 [ADC1_IN6] + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 // Connected to ARD_D6 [ADC1_IN6] + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to ARD_A5 [ADC] + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to ARD_A5 [ADC] + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to ARD_A5 [ADC] + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to ARD_A4 [ADC] + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to ARD_A4 [ADC] + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to ARD_A4 [ADC] + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to ARD_A3 [ADC] + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // Connected to ARD_A3 [ADC] + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // Connected to ARD_A3 [ADC] + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to ARD_A2 [ADC] + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to ARD_A2 [ADC] + {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 // Connected to ARD_A2 [ADC] + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to ARD_A1 [ADC] + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // Connected to ARD_A1 [ADC] + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to ARD_A0 [ADC] + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to ARD_A0 [ADC] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 0, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // Connected to ARD_D7 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to ARD_D13 [SPI1_SCK] + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to ARD_D14 [I2C1_SDA] + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED2 [LED_GREEN] + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to ARD_A4 [ADC] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_TX + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to ARD_D15 [I2C1_SCL] + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to ARD_A5 [ADC] + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ARD_D1 [UART4_TX] +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to ARD_D1 [UART4_TX] + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ARD_D0 [UART4_RX] +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ARD_D0 [UART4_RX] + {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ARD_D0 [UART4_RX] + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ARD_D10 [SPI_SSN] +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ARD_D10 [SPI_SSN] + {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ARD_D10 [SPI_SSN] + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ARD_D4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ARD_D4 + {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // Connected to ARD_D4 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ARD_D13 [SPI1_SCK] + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ARD_D13 [SPI1_SCK] + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to ARD_D12 [SPI1_MISO] + {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to ARD_D12 [SPI1_MISO] + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ARD_D11 [SPI1_MOSI] + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ARD_D11 [SPI1_MOSI] + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ARD_D11 [SPI1_MOSI] + {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to ARD_D11 [SPI1_MOSI] + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to SPBTLE_RF_RST + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_OTG_FS_VBUS [STMPS2141STR_OUT] + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_OTG_FS_ID + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_OTG_FS_DM + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to ARD_D3 [INT_EXT10] + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to ARD_D3 [INT_EXT10] + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ARD_D3 [INT_EXT10] + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to ARD_D6 [ADC1_IN6] + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to ARD_D6 [ADC1_IN6] + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to ARD_D6 [ADC1_IN6] + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] +// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to STDIO_UART_TX +// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // Connected to STDIO_UART_TX +// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to STDIO_UART_RX +// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // Connected to STDIO_UART_RX + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to ARD_D15 [I2C1_SCL] + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to ARD_D15 [I2C1_SCL] + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to ARD_D14 [I2C1_SDA] + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to ARD_D14 [I2C1_SDA] + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ISM43362_WAKEUP [ISM43362_WKUP] + {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ISM43362_WAKEUP [ISM43362_WKUP] + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LED2 [LED_GREEN] + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LED2 [LED_GREEN] + {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to LED2 [LED_GREEN] + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to SPSGRF_915_SDN [SPSGRF_SDN] + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to SPSGRF_915_SDN [SPSGRF_SDN] + {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // Connected to SPSGRF_915_SDN [SPSGRF_SDN] + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to VL53L0X_XSHUT [Read_XSHUT] + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to VL53L0X_XSHUT [Read_XSHUT] + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to VL53L0X_GPIO1_EXTI7 [VL53L0X_GPIO1] + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to VL53L0X_GPIO1_EXTI7 [VL53L0X_GPIO1] + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LSM3MDL_DRDY_EXTI8 [LIS3MDL_DRDY] + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to LSM3MDL_DRDY_EXTI8 [LIS3MDL_DRDY] + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to LED3_WIFI_ LED4_BLE + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to LED3_WIFI_ LED4_BLE + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to USB_OTG_FS_PWR_EN [STMPS2141STR_EN] + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to SPBTLE_RF_SPI3_CSN [BT module_SPI_CS] + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to ARD_D2 [INT0_EXTI14] + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to HTS221_DRDY_EXTI15 [HTS221_DRDY] + {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to ISM43362_SPI3_CSN [ISM43362_SSN] + {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to ISM43362_DRDY_EXTI1 [ISM43362_DATARDY] + {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to USB_OTG_FS_OVRCR_EXTI3 [STMPS2141STR_FAULT] + {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to M24SR64_Y_GPO [M24SR64_GPO] + {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SPSGRF_915_GPIO3_EXTI5 [SPSGRF_GPIO_3] + {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to SPBTLE_RF_IRQ_EXTI6 [BT module_SPI_IRQ] + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ISM43362_RST [ISM43362_RSTN] + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to DFSDM1_CKOUT [MP34DT01_CLK] + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to QUADSPI_CLK [MX25R6435F_SCLK] + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to QUADSPI_NCS [MX25R6435F_SCLK] + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to OQUADSPI_BK1_IO0 [MX25R6435F_IO0] + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to QUADSPI_BK1_IO1 [MX25R6435F_IO1] + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to QUAD_SPI_BK1_IO2 [MX25R6435F_IO2] + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ARD_D1 [UART4_TX] + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D10 [SPI_SSN] + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_VBUS [STMPS2141STR_OUT] + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A4 [ADC] + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A1 [ADC] + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to INTERNAL_SPI3_MOSI [BT module_SPI_MOSI] + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_TX + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_UART3_TX [ISM43362_RX] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ARD_D0 [UART4_RX] + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D4 + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_ID + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A5 [ADC] + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A0 [ADC] + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to PMOD_IRQ_EXTI12 + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_RX + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_UART3_RX [ISM43362_TX] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D0 [UART4_RX] + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DP + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_D6 [ADC1_IN6] + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_BOOT0 [ISM43362_BOOT] + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED2 [LED_GREEN] + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD_IRQ_EXTI12 + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_RTS + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to USB_OTG_FS_PWR_EN [STMPS2141STR_EN] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D1 [UART4_TX] + {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_D12 [SPI1_MISO] + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DM + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to STDIO_UART_RX + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_CTS + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LSM6DSL_INT1_EXTI11 [LSM6DSL_INT1] + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D11 [SPI1_MOSI] + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPSGRF_915_SDN [SPSGRF_SDN] + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_A2 [ADC] + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to INTERNAL_SPI3_MOSI [BT module_SPI_MOSI] + {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_UART2_RTS + {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QUAD_SPI_BK1_IO3 [MX25R6435F_IO3] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D12 [SPI1_MISO] + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LED2 [LED_GREEN] + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_A3 [ADC] + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_UART2_CTS + {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QUAD_SPI_BK1_IO2 [MX25R6435F_IO2] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D13 [SPI1_SCK] + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] + {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_SPI2_SCK + {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QUADSPI_BK1_IO1 [MX25R6435F_IO1] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D7 + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D7 + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_D14 [I2C1_SDA] + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ISM43362_BOOT0 [ISM43362_BOOT] + {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_RESET + {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to OQUADSPI_BK1_IO0 [MX25R6435F_IO0] + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_OTG_FS_DM + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D15 [I2C1_SCL] + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to PMOD_RESET + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_OTG_FS_DP + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D14 [I2C1_SDA] + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to PMOD_SPI2_SCK + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { + {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D12 [SPI1_MISO] + {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D11 [SPI1_MOSI] + {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to ARD_D3 [INT_EXT10] + {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to ARD_D6 [ADC1_IN6] + {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to OQUADSPI_BK1_IO0 [MX25R6435F_IO0] + {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QUADSPI_BK1_IO1 [MX25R6435F_IO1] + {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QUAD_SPI_BK1_IO2 [MX25R6435F_IO2] + {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QUAD_SPI_BK1_IO3 [MX25R6435F_IO3] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] + {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to QUADSPI_CLK [MX25R6435F_SCLK] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] + {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to QUADSPI_NCS [MX25R6435F_SCLK] + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h new file mode 100644 index 0000000000..9d89ae5467 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h @@ -0,0 +1,321 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0_ALT0 = PA_0 | ALT0, + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13 | ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, + + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, + PC_2 = 0x22, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, + PC_3 = 0x23, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Not connected + NC = (int)0xFFFFFFFF, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + + // Generic signals namings + LED1 = PE_2, // Red LED (LD1) + LED2 = PE_3, // Blue LED (LD2) + LED3 = PE_4, // Green LED (LD3) + + LED_RED = LED1, + LED_BLUE = LED2, + LED_GREEN = LED3, + + USER_BUTTON = PD_4, + BUTTON1 = USER_BUTTON, + + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, + + UART1_TX = PA_2, + UART1_RX = PA_3, + UART1_CTS = PA_0, + UART1_RTS = PA_1, + + SERIAL_TX = UART1_TX, + SERIAL_RX = UART1_RX, + SERIAL_CTS = UART1_CTS, + SERIAL_RTS = UART1_RTS, + + UART2_TX = PC_4, + UART2_RX = PC_5, + + I2C0_SCL = PB_6, + I2C0_SDA = PB_7, + + I2C1_SCL = PC_0, + I2C1_SDA = PC_1, + + SPI0_MOSI = PB_5, + SPI0_MISO = PA_6, + SPI0_SCK = PA_5, + SPI0_CS = PA_15, + + SPI1_MOSI = PB_15, + SPI1_MISO = PB_14, + SPI1_SCK = PD_3, + SPI1_CS = PB_9, + + SPI2_MOSI = PC_12, + SPI2_MISO = PC_11, + SPI2_SCK = PC_10, + SPI2_CS = PA_4, + + //Default SPI + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + /**************** + //IMPORTANT NOTE: The default CS for SPI is marked as the CS line for the SPI Flash + //on the MCB reference hardware. Please change as appropriate. + ****************/ + SPI_CS = PD_2, + + CAN1_RX = PD_0, //Test point on MCB + CAN1_TX = PD_1, //Test point on MCB + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_PVD_IN = PB_7, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED1 = PE_4, + SYS_TRACED2 = PE_5, + SYS_TRACED3 = PE_6, + SYS_WKUP1 = PA_0, + SYS_WKUP2 = PC_13, + SYS_WKUP3 = PE_6, + SYS_WKUP4 = PA_2, + SYS_WKUP5 = PC_5, + + //MTB aliases + TX1 = PA_2, + RX1 = PA_3, + SDA1 = PB_7, + SCL1 = PB_6, + MOSI1 = PB_5, + MISO1 = PA_6, + SCK1 = PA_5, + GP0 = PD_4, + GP1 = PC_10, + AIN0 = PA_0, //CTS + AIN1 = PA_1, // RTS + AIN2 = PB_0, + + GP2 = PE_5, //SD card CS + GP3 = PE_6, + SCK2 = PD_3, + MISO2 = PB_14, + MOSI2 = PB_15, + SCL2 = PC_1, + SDA2 = PC_0, + RX2 = PC_5, + TX2 = PC_4, + GP4 = PE_9, + GP5 = PE_10, //A0 for LCD on MTB + GP6 = PE_13, //RESET for LCD on MTB + GP7 = PE_14, //LCD CS + GP8 = PE_15 + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c new file mode 100644 index 0000000000..d71a36fb67 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c @@ -0,0 +1,370 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32l4xx.h" +#include "nvic_addr.h" +#include "mbed_error.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock +#define USE_PLL_MSI 0x1 // Use MSI internal clock + +#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +uint8_t SetSysClock_PLL_MSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + /* 4- If fail start with MSI clock */ + if (SetSysClock_PLL_MSI() == 0) +#endif + { + { + error("SetSysClock failed\n"); + } + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + +#if MBED_CONF_TARGET_LSE_AVAILABLE + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ + HAL_RCCEx_DisableLSECSS(); +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ + RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ + RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ + RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ + RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + +#if MBED_CONF_TARGET_LSE_AVAILABLE + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ diff --git a/targets/targets.json b/targets/targets.json index f39d40bce2..03a01ce1ac 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3915,6 +3915,35 @@ "device_name": "STM32L475VG", "bootloader_supported": true }, + "MTB_STM_L475": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (8MHz) | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_HSE_XTAL", + "macro_name": "CLOCK_SOURCE" + }, + "lpticker_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", + "value": 0 + } + }, + "detect_code": ["0468"], + "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], + "device_has_add": [ + "ANALOGOUT", + "CAN", + "SERIAL_FC", + "TRNG", + "FLASH", + "MPU" + ], + "release_versions": ["5"], + "device_name": "STM32L475VG", + "bootloader_supported": true + }, "DISCO_L476VG": { "components_add": ["QSPIF", "FLASHIAP"], "inherits": ["FAMILY_STM32"], From f4fc79e2cd440f3097d415638821ff2e50f0cfb3 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Wed, 20 Feb 2019 15:02:59 +0000 Subject: [PATCH 100/109] Adding SPDX license identifier --- .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c index d71a36fb67..77a37b4662 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2017 ARM Limited + +* SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. From a3007f6ffefa63d4c55929470c00533ecd26c6e3 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Wed, 20 Feb 2019 15:07:03 +0000 Subject: [PATCH 101/109] Adding SPDX license identifer for all new files --- .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h | 2 ++ .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c | 2 ++ .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h index 04b09f6539..39836c1495 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h @@ -1,4 +1,6 @@ /* mbed Microcontroller Library + +* SPDX-License-Identifier: Apache-2.0 ******************************************************************************* * Copyright (c) 2017, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c index 31119421e5..b29079934a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c @@ -1,4 +1,6 @@ /* mbed Microcontroller Library + +* SPDX-License-Identifier: Apache-2.0 ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h index 9d89ae5467..3946fdaab1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h @@ -1,4 +1,6 @@ /* mbed Microcontroller Library + +* SPDX-License-Identifier: Apache-2.0 ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. From ceb5c6e01e781a849cd3d42452e3c8e1b1fe22d7 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Wed, 20 Feb 2019 15:22:11 +0000 Subject: [PATCH 102/109] Removing redundant code comments --- .../TARGET_MTB_STM_L475/PeripheralPins.c | 416 +++++++++--------- 1 file changed, 208 insertions(+), 208 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c index b29079934a..d1c9c39723 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c @@ -55,42 +55,42 @@ //*** ADC *** MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to ARD_D1 [UART4_TX] - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // Connected to ARD_D1 [UART4_TX] - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to ARD_D0 [UART4_RX] - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // Connected to ARD_D0 [UART4_RX] - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to ARD_D10 [SPI_SSN] - {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to ARD_D10 [SPI_SSN] - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to ARD_D4 - {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to ARD_D4 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to ARD_D7 - {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // Connected to ARD_D7 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to ARD_D13 [SPI1_SCK] - {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to ARD_D13 [SPI1_SCK] - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to ARD_D12 [SPI1_MISO] - {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to ARD_D12 [SPI1_MISO] - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to ARD_D11 [SPI1_MOSI] - {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to ARD_D11 [SPI1_MOSI] - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to ARD_D3 [INT_EXT10] - {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to ARD_D3 [INT_EXT10] - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 // Connected to ARD_D6 [ADC1_IN6] - {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 // Connected to ARD_D6 [ADC1_IN6] - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to ARD_A5 [ADC] - {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to ARD_A5 [ADC] - {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to ARD_A5 [ADC] - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to ARD_A4 [ADC] - {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to ARD_A4 [ADC] - {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to ARD_A4 [ADC] - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to ARD_A3 [ADC] - {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // Connected to ARD_A3 [ADC] - {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // Connected to ARD_A3 [ADC] - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to ARD_A2 [ADC] - {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to ARD_A2 [ADC] - {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 // Connected to ARD_A2 [ADC] - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to ARD_A1 [ADC] - {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // Connected to ARD_A1 [ADC] - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to ARD_A0 [ADC] - {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to ARD_A0 [ADC] + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 {NC, NC, 0} }; @@ -104,28 +104,28 @@ MBED_WEAK const PinMap PinMap_ADC_Internal[] = { //*** DAC *** MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // Connected to ARD_D7 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to ARD_D13 [SPI1_SCK] + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // {NC, NC, 0} }; //*** I2C *** MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to ARD_D14 [I2C1_SDA] - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] - {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED2 [LED_GREEN] - {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to ARD_A4 [ADC] + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_TX - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to ARD_D15 [I2C1_SCL] - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] - {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] - {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to ARD_A5 [ADC] + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, {NC, NC, 0} }; @@ -133,238 +133,238 @@ MBED_WEAK const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ARD_D1 [UART4_TX] -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to ARD_D1 [UART4_TX] - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ARD_D0 [UART4_RX] -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ARD_D0 [UART4_RX] - {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ARD_D0 [UART4_RX] - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ARD_D10 [SPI_SSN] -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ARD_D10 [SPI_SSN] - {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ARD_D10 [SPI_SSN] - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ARD_D4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ARD_D4 - {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // Connected to ARD_D4 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ARD_D13 [SPI1_SCK] - {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ARD_D13 [SPI1_SCK] - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to ARD_D12 [SPI1_MISO] - {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to ARD_D12 [SPI1_MISO] - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ARD_D11 [SPI1_MOSI] - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ARD_D11 [SPI1_MOSI] - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ARD_D11 [SPI1_MOSI] - {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to ARD_D11 [SPI1_MOSI] - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to SPBTLE_RF_RST - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_OTG_FS_VBUS [STMPS2141STR_OUT] - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_OTG_FS_ID - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_OTG_FS_DM + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to ARD_D3 [INT_EXT10] - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to ARD_D3 [INT_EXT10] - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ARD_D3 [INT_EXT10] - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to ARD_D6 [ADC1_IN6] - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to ARD_D6 [ADC1_IN6] - {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to ARD_D6 [ADC1_IN6] + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] -// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to STDIO_UART_TX -// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // Connected to STDIO_UART_TX -// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to STDIO_UART_RX -// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // Connected to STDIO_UART_RX - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to ARD_D15 [I2C1_SCL] - {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to ARD_D15 [I2C1_SCL] - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to ARD_D14 [I2C1_SDA] - {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to ARD_D14 [I2C1_SDA] - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ISM43362_WAKEUP [ISM43362_WKUP] - {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ISM43362_WAKEUP [ISM43362_WKUP] - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LED2 [LED_GREEN] - {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LED2 [LED_GREEN] - {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to LED2 [LED_GREEN] - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to SPSGRF_915_SDN [SPSGRF_SDN] - {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to SPSGRF_915_SDN [SPSGRF_SDN] - {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // Connected to SPSGRF_915_SDN [SPSGRF_SDN] - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to VL53L0X_XSHUT [Read_XSHUT] - {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to VL53L0X_XSHUT [Read_XSHUT] - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to VL53L0X_GPIO1_EXTI7 [VL53L0X_GPIO1] - {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to VL53L0X_GPIO1_EXTI7 [VL53L0X_GPIO1] - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LSM3MDL_DRDY_EXTI8 [LIS3MDL_DRDY] - {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to LSM3MDL_DRDY_EXTI8 [LIS3MDL_DRDY] - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to LED3_WIFI_ LED4_BLE - {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to LED3_WIFI_ LED4_BLE - {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to USB_OTG_FS_PWR_EN [STMPS2141STR_EN] - {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to SPBTLE_RF_SPI3_CSN [BT module_SPI_CS] - {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to ARD_D2 [INT0_EXTI14] - {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to HTS221_DRDY_EXTI15 [HTS221_DRDY] - {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to ISM43362_SPI3_CSN [ISM43362_SSN] - {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to ISM43362_DRDY_EXTI1 [ISM43362_DATARDY] - {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to USB_OTG_FS_OVRCR_EXTI3 [STMPS2141STR_FAULT] - {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to M24SR64_Y_GPO [M24SR64_GPO] - {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SPSGRF_915_GPIO3_EXTI5 [SPSGRF_GPIO_3] - {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to SPBTLE_RF_IRQ_EXTI6 [BT module_SPI_IRQ] - {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ISM43362_RST [ISM43362_RSTN] - {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to DFSDM1_CKOUT [MP34DT01_CLK] - {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to QUADSPI_CLK [MX25R6435F_SCLK] - {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to QUADSPI_NCS [MX25R6435F_SCLK] - {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to OQUADSPI_BK1_IO0 [MX25R6435F_IO0] - {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to QUADSPI_BK1_IO1 [MX25R6435F_IO1] - {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to QUAD_SPI_BK1_IO2 [MX25R6435F_IO2] + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 +// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N +// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 +// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 {NC, NC, 0} }; //*** SERIAL *** MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ARD_D1 [UART4_TX] - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D10 [SPI_SSN] - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_VBUS [STMPS2141STR_OUT] - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] - {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] - {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A4 [ADC] - {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A1 [ADC] - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to INTERNAL_SPI3_MOSI [BT module_SPI_MOSI] - {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_TX - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_UART3_TX [ISM43362_RX] + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ARD_D0 [UART4_RX] - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D4 - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_ID - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX - {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] - {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A5 [ADC] - {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A0 [ADC] - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to PMOD_IRQ_EXTI12 - {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_RX - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_UART3_RX [ISM43362_TX] + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D0 [UART4_RX] - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DP + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_D6 [ADC1_IN6] + {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_BOOT0 [ISM43362_BOOT] - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED2 [LED_GREEN] - {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD_IRQ_EXTI12 - {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_RTS - {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to USB_OTG_FS_PWR_EN [STMPS2141STR_EN] + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D1 [UART4_TX] - {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_D12 [SPI1_MISO] - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DM + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] - {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to STDIO_UART_RX - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] - {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] - {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_CTS - {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LSM6DSL_INT1_EXTI11 [LSM6DSL_INT1] + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; //*** SPI *** MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D11 [SPI1_MOSI] - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPSGRF_915_SDN [SPSGRF_SDN] - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_A2 [ADC] - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to INTERNAL_SPI3_MOSI [BT module_SPI_MOSI] - {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_UART2_RTS - {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QUAD_SPI_BK1_IO3 [MX25R6435F_IO3] + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D12 [SPI1_MISO] + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LED2 [LED_GREEN] - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_A3 [ADC] - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] - {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_UART2_CTS - {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QUAD_SPI_BK1_IO2 [MX25R6435F_IO2] + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D13 [SPI1_SCK] + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] - {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_SPI2_SCK - {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QUADSPI_BK1_IO1 [MX25R6435F_IO1] + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D7 - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D7 + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_D14 [I2C1_SDA] - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ISM43362_BOOT0 [ISM43362_BOOT] - {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD_RESET - {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to OQUADSPI_BK1_IO0 [MX25R6435F_IO0] + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {NC, NC, 0} }; //*** CAN *** MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_OTG_FS_DM - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D15 [I2C1_SCL] - {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to PMOD_RESET + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_OTG_FS_DP - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D14 [I2C1_SDA] - {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to PMOD_SPI2_SCK + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; //*** QUADSPI *** MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { - {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D12 [SPI1_MISO] - {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D11 [SPI1_MOSI] - {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to ARD_D3 [INT_EXT10] - {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to ARD_D6 [ADC1_IN6] - {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to OQUADSPI_BK1_IO0 [MX25R6435F_IO0] - {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QUADSPI_BK1_IO1 [MX25R6435F_IO1] - {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QUAD_SPI_BK1_IO2 [MX25R6435F_IO2] - {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QUAD_SPI_BK1_IO3 [MX25R6435F_IO3] + {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 + {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 + {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 + {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { - {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to QUADSPI_CLK [MX25R6435F_SCLK] + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK + {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { - {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] - {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to QUADSPI_NCS [MX25R6435F_SCLK] + {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS + {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS {NC, NC, 0} }; From 7a716b591c4e9c83154255e06628c2dadeaad388 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Thu, 21 Feb 2019 10:35:25 +0000 Subject: [PATCH 103/109] Changing SPDX license identifier to BSD-3-Clause --- .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h | 2 +- .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c | 2 +- .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h | 2 +- .../TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h index 39836c1495..1985df72fd 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library -* SPDX-License-Identifier: Apache-2.0 +* SPDX-License-Identifier: BSD-3-Clause ******************************************************************************* * Copyright (c) 2017, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c index d1c9c39723..0b79f9eed3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library -* SPDX-License-Identifier: Apache-2.0 +* SPDX-License-Identifier: BSD-3-Clause ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h index 3946fdaab1..c9f7aca3a5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library -* SPDX-License-Identifier: Apache-2.0 +* SPDX-License-Identifier: BSD-3-Clause ******************************************************************************* * Copyright (c) 2018, STMicroelectronics * All rights reserved. diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c index 77a37b4662..39c066d940 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited +* Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 * From 7309bd9c3277c0959baa257bceaada823474b5be Mon Sep 17 00:00:00 2001 From: RFulchiero Date: Tue, 19 Feb 2019 15:20:36 -0600 Subject: [PATCH 104/109] Remove ITM from NRF52_DK and DELTA_DFBM_NQ620 targets The NRF52_DK and DELTA_DFBM_NQ620 have the SWO pin (p0_18) mapped to LED2. This means that on startup LED2 turns on after the ITM is initialized which is confusing. Since most users want LED2 usage instead of SWO we remove the ITM for these targets. The nRF52 readme is updated to instruct users how to get SWO support if they need it. --- targets/TARGET_NORDIC/TARGET_NRF5x/README.md | 10 ++++++++++ targets/targets.json | 6 ++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/README.md b/targets/TARGET_NORDIC/TARGET_NRF5x/README.md index bea26442f8..7e093ea90e 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/README.md +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/README.md @@ -153,6 +153,16 @@ The assert handler is defined in mbed-os/features/FEATURE_BLE/targets/TARGET_NOR * It is not possible to do an asynchronous write from flash and receive non-asynchronously at the same time since the non-asynchronous receive buffer is being used as the temporary transmission buffer. * The driver will flush the DMA buffer after a configurable timeout. During this process the UART will be halted and therefor unable to receive data. Hardware flow control should be enabled to avoid missing any data during this window. +#### Serial Wire Output (SWO) + +On the nRF52832 pin 18 (p18 or p0_18) is the SWO pin and a GPIO pin. On the nRF52_DK and DELTA_DFBM_NQ620 targets p18 is also mapped to LED2, so the ITM has been removed from these targets to avoid contention. If you need SWO capability instead of LED2, add the ITM through ```mbed_app.json```: +``` + "target_overrides": { + "*": { + "target.device_has_add": ["ITM"] + } + } +``` ## SoftDevice diff --git a/targets/targets.json b/targets/targets.json index 03a01ce1ac..624516df7b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6848,7 +6848,8 @@ "device_name": "nRF52832_xxAA", "macros_add": [ "WSF_MAX_HANDLERS=10" - ] + ], + "device_has_remove": ["ITM"] }, "SDT52832B": { "inherits": ["MCU_NRF52832"], @@ -6892,7 +6893,8 @@ "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52832"], "release_versions": ["5"], - "device_name": "nRF52832_xxAA" + "device_name": "nRF52832_xxAA", + "device_has_remove": ["ITM"] }, "MCU_NRF52840": { "inherits": ["Target"], From 774ee684760ac7178f6a164412c6e056f18c8d83 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 21 Feb 2019 16:25:20 +0100 Subject: [PATCH 105/109] STM32 LPTICKER (LPTIM): correct init execution after bootloader --- targets/TARGET_STM/lp_ticker.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index d8704faa56..fa16a27f6e 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -59,16 +59,19 @@ const ticker_info_t *lp_ticker_get_info() volatile uint8_t lp_Fired = 0; +static int LPTICKER_inited = 0; + static void LPTIM1_IRQHandler(void); static void (*irq_handler)(void); void lp_ticker_init(void) { /* Check if LPTIM is already configured */ - if (__HAL_RCC_LPTIM1_IS_CLK_ENABLED()) { + if (LPTICKER_inited) { lp_ticker_disable_interrupt(); return; } + LPTICKER_inited = 1; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; From f5eb87c62d71c7d8974a5b9648a251238575bb57 Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Thu, 21 Feb 2019 15:08:59 -0600 Subject: [PATCH 106/109] Revert "nRF52 serial: Tighten/simplify atomics" This reverts commit 2a7f5e21afe93b6ca395a6e69aa78bf6bf0cac27. --- .../TARGET_NRF5x/TARGET_NRF52/serial_api.c | 40 ++++++++++--------- 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c index 4ac70d7e03..dbfd41f749 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c @@ -138,8 +138,8 @@ typedef struct { uint8_t buffer[NUMBER_OF_BANKS][DMA_BUFFER_SIZE]; uint32_t usage_counter; uint8_t tx_data; - bool tx_in_progress; - bool rx_in_progress; + volatile uint8_t tx_in_progress; + volatile uint8_t rx_in_progress; bool tx_asynch; bool rx_asynch; bool callback_posted; @@ -252,7 +252,7 @@ static void nordic_nrf5_uart_callback_handler(uint32_t instance) static void nordic_nrf5_uart_event_handler_endtx(int instance) { /* Release mutex. As the owner this call is safe. */ - core_util_atomic_store_bool(&nordic_nrf5_uart_state[instance].tx_in_progress, false); + nordic_nrf5_uart_state[instance].tx_in_progress = 0; /* Check if callback handler and Tx event mask is set. */ uart_irq_handler callback = (uart_irq_handler) nordic_nrf5_uart_state[instance].owner->handler; @@ -275,8 +275,8 @@ static void nordic_nrf5_uart_event_handler_endtx(int instance) static void nordic_nrf5_uart_event_handler_endtx_asynch(int instance) { /* Set Tx done and reset Tx mode to be not asynchronous. */ + nordic_nrf5_uart_state[instance].tx_in_progress = 0; nordic_nrf5_uart_state[instance].tx_asynch = false; - core_util_atomic_store_bool(&nordic_nrf5_uart_state[instance].tx_in_progress, false); /* Cast handler to callback function pointer. */ void (*callback)(void) = (void (*)(void)) nordic_nrf5_uart_state[instance].owner->tx_handler; @@ -482,8 +482,8 @@ static void nordic_nrf5_uart_event_handler_rxstarted(int instance) static void nordic_nrf5_uart_event_handler_endrx_asynch(int instance) { /* Set Rx done and reset Rx mode to be not asynchronous. */ + nordic_nrf5_uart_state[instance].rx_in_progress = 0; nordic_nrf5_uart_state[instance].rx_asynch = false; - core_util_atomic_store_bool(&nordic_nrf5_uart_state[instance].rx_in_progress, false); /* Cast handler to callback function pointer. */ void (*callback)(void) = (void (*)(void)) nordic_nrf5_uart_state[instance].owner->rx_handler; @@ -1410,7 +1410,7 @@ int serial_writable(serial_t *obj) int instance = uart_object->instance; - return (!core_util_atomic_load_bool(&nordic_nrf5_uart_state[instance].tx_in_progress) && + return ((nordic_nrf5_uart_state[instance].tx_in_progress == 0) && (nrf_uarte_event_extra_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY))); } @@ -1449,14 +1449,16 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx /** * tx_in_progress acts like a mutex to ensure only one transmission can be active at a time. - * The flag is modified using the atomic exchange function - only proceed when we see the - * flag clear and we set it to true. + * The flag is modified using the atomic compare-and-set function. */ - bool old_mutex; + bool mutex = false; do { - old_mutex = core_util_atomic_exchange_bool(&nordic_nrf5_uart_state[instance].tx_in_progress, true); - } while (old_mutex == true); + uint8_t expected = 0; + uint8_t desired = 1; + + mutex = core_util_atomic_cas_u8((uint8_t *) &nordic_nrf5_uart_state[instance].tx_in_progress, &expected, desired); + } while (mutex == false); /* State variables. */ int result = 0; @@ -1573,14 +1575,16 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /** * rx_in_progress acts like a mutex to ensure only one asynchronous reception can be active at a time. - * The flag is modified using the atomic exchange function - only proceed when we see the - * flag clear and we set it to true. + * The flag is modified using the atomic compare-and-set function. */ - bool old_mutex; + bool mutex = false; do { - old_mutex = core_util_atomic_exchange_bool(&nordic_nrf5_uart_state[instance].rx_in_progress, true); - } while (old_mutex == true); + uint8_t expected = 0; + uint8_t desired = 1; + + mutex = core_util_atomic_cas_u8((uint8_t *) &nordic_nrf5_uart_state[instance].rx_in_progress, &expected, desired); + } while (mutex == false); /* Store callback handler, mask and reset event value. */ obj->serial.rx_handler = handler; @@ -1659,8 +1663,8 @@ void serial_tx_abort_asynch(serial_t *obj) nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDTX); /* Reset Tx flags. */ + nordic_nrf5_uart_state[instance].tx_in_progress = 0; nordic_nrf5_uart_state[instance].tx_asynch = false; - nordic_nrf5_uart_state[instance].tx_in_progress = false; /* Force reconfiguration. */ obj->serial.update = true; @@ -1687,8 +1691,8 @@ void serial_rx_abort_asynch(serial_t *obj) core_util_critical_section_enter(); /* Reset Rx flags. */ + nordic_nrf5_uart_state[obj->serial.instance].rx_in_progress = 0; nordic_nrf5_uart_state[obj->serial.instance].rx_asynch = false; - nordic_nrf5_uart_state[obj->serial.instance].rx_in_progress = false; obj->serial.rx_asynch = false; /* Force reconfiguration. */ From 42b1afa534dcc5f82bb0977fa1fd0b40ed0e3059 Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Thu, 21 Feb 2019 22:02:23 -0600 Subject: [PATCH 107/109] Revert "support in more types then just RSA_KEYPAIR" This reverts commit 7824c793b7188c8f7b282a8e77817567f2086617. --- .../crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c index 5cc9acc2bc..d734903874 100644 --- a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c +++ b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c @@ -1003,13 +1003,18 @@ psa_status_t psa_generate_key(psa_key_slot_t key, in_vec[1].base = &bits; in_vec[1].len = sizeof(size_t); - if (((parameters == NULL) && (parameters_size != 0)) || ((parameters != NULL) && (parameters_size == 0))) { - return (PSA_ERROR_INVALID_ARGUMENT); + /* currently the parameter argument is used only for RSA keypair + and ignored in other cases. support for other algorithms + may be added later*/ + if (PSA_KEY_TYPE_RSA_KEYPAIR == type) { + in_vec[2].base = parameters; + /* size of parameter is unsigned integer as defined in header */ + in_vec[2].len = parameters_size; + } else { // currenty ignored for non RSA case + in_vec[2].base = NULL; + in_vec[2].len = 0; } - in_vec[2].base = parameters; - in_vec[2].len = parameters_size; - handle = psa_connect(PSA_KEY_MNG_ID, MINOR_VER); if (handle <= 0) { return (PSA_ERROR_COMMUNICATION_FAILURE); From 71ebf820819c5f6e7ee19b13ba8760f6ae56d56d Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Thu, 21 Feb 2019 22:14:23 -0600 Subject: [PATCH 108/109] Revert "Add MBEDTLS_ENTROPY_NV_SEED to NUCLEO_F411RE to fix the build" This reverts commit b705934b6225c1c7901e42aa12281ef3135f820a. --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 624516df7b..723f14848d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2435,7 +2435,7 @@ "macro_name": "CLOCK_SOURCE_USB" } }, - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "MBEDTLS_PSA_CRYPTO_C", "MBEDTLS_ENTROPY_NV_SEED"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "MBEDTLS_PSA_CRYPTO_C"], "device_has_add": [ "SERIAL_ASYNCH", "FLASH", From b83fb2b7387298649102d3042b54063349cff371 Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Thu, 21 Feb 2019 22:15:49 -0600 Subject: [PATCH 109/109] Revert "Restore MBEDTLS_PSA_CRYPTO_C for PSA targets" This reverts commit 035ecc15d633763ab8d3d60ab0869dee210e2472. --- targets/targets.json | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 723f14848d..832cfa4355 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1743,7 +1743,7 @@ "PSA" ], "is_disk_virtual": true, - "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED", "MBEDTLS_PSA_CRYPTO_C"], + "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"], "inherits": ["Target"], "detect_code": ["0311"], "device_has": [ @@ -2435,7 +2435,7 @@ "macro_name": "CLOCK_SOURCE_USB" } }, - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "MBEDTLS_PSA_CRYPTO_C"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], "device_has_add": [ "SERIAL_ASYNCH", "FLASH", @@ -2684,8 +2684,7 @@ "components_add": ["FLASHIAP"], "macros_add": [ "USB_STM_HAL", - "USBHOST_OTHER", - "MBEDTLS_PSA_CRYPTO_C" + "USBHOST_OTHER" ], "device_has_add": [ "ANALOGOUT", @@ -4296,9 +4295,6 @@ "device_has_remove": [], "extra_labels_add": ["PSA"], "components_add": ["FLASHIAP"], - "macros_add": [ - "MBEDTLS_PSA_CRYPTO_C" - ], "config": { "stdio_uart_tx_help": { "help": "Value: D8(default) or D1"

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