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standardise QSPI pin names

pull/7817/head
Maciej Bocianski 2018-08-17 15:09:13 +02:00
parent 582b414ea2
commit 5195c820e6
17 changed files with 149 additions and 18 deletions
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21
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h
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@ -227,12 +227,21 @@ typedef enum {
A4 = p30,
A5 = p31,
QSPI_FLASH_IO0 = P0_20,
QSPI_FLASH_IO1 = P0_21,
QSPI_FLASH_IO2 = P0_22,
QSPI_FLASH_IO3 = P0_23,
QSPI_FLASH_SCK = P0_19,
QSPI_FLASH_CSN = P0_17,
/**** QSPI pins ****/
QSPI1_IO0 = P0_20,
QSPI1_IO1 = P0_21,
QSPI1_IO2 = P0_22,
QSPI1_IO3 = P0_23,
QSPI1_SCK = P0_19,
QSPI1_CSN = P0_17,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = QSPI1_IO0,
QSPI_FLASH1_IO1 = QSPI1_IO1,
QSPI_FLASH1_IO2 = QSPI1_IO2,
QSPI_FLASH1_IO3 = QSPI1_IO3,
QSPI_FLASH1_SCK = QSPI1_SCK,
QSPI_FLASH1_CSN = QSPI1_CSN,
// Not connected
NC = (int)0xFFFFFFFF

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h
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@ -307,6 +307,14 @@ typedef enum {
SYS_WKUP2 = PC_0,
SYS_WKUP3 = PC_1,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,
QSPI1_IO1 = PD_12,
QSPI1_IO2 = PE_2,
QSPI1_IO3 = PD_13,
QSPI1_SCK = PB_2,
QSPI1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

12
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h
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@ -304,12 +304,12 @@ typedef enum {
SYS_WKUP3 = PC_1,
/**** QSPI FLASH pins ****/
QSPI_PIN_IO0 = PF_8,
QSPI_PIN_IO1 = PF_9,
QSPI_PIN_IO2 = PE_2,
QSPI_PIN_IO3 = PD_13,
QSPI_PIN_SCK = PB_2,
QSPI_PIN_CSN = PG_6,
QSPI_FLASH1_IO0 = PF_8,
QSPI_FLASH1_IO1 = PF_9,
QSPI_FLASH1_IO2 = PE_2,
QSPI_FLASH1_IO3 = PD_13,
QSPI_FLASH1_SCK = PB_2,
QSPI_FLASH1_CSN = PG_6,
// Not connected
NC = (int)0xFFFFFFFF

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h
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@ -306,6 +306,14 @@ typedef enum {
SYS_WKUP2 = PC_0,
SYS_WKUP3 = PC_1,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,
QSPI1_IO1 = PD_12,
QSPI1_IO2 = PE_2,
QSPI1_IO3 = PD_13,
QSPI1_SCK = PB_2,
QSPI1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h
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@ -325,6 +325,14 @@ typedef enum {
SYS_WKUP0 = PA_0,
SYS_WKUP1 = PC_13,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,
QSPI1_IO1 = PD_12,
QSPI1_IO2 = PE_2,
QSPI1_IO3 = PD_13,
QSPI1_SCK = PB_2,
QSPI1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

13
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h
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@ -406,12 +406,13 @@ typedef enum {
SYS_TRACED3_ALT0 = PE_6,
SYS_WKUP = PA_0,
QSPI_FLASH_IO0 = PF_8,
QSPI_FLASH_IO1 = PF_9,
QSPI_FLASH_IO2 = PF_7,
QSPI_FLASH_IO3 = PF_6,
QSPI_FLASH_SCK = PF_10,
QSPI_FLASH_CSN = PB_6,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = PF_8,
QSPI_FLASH1_IO1 = PF_9,
QSPI_FLASH1_IO2 = PF_7,
QSPI_FLASH1_IO3 = PF_6,
QSPI_FLASH1_SCK = PF_10,
QSPI_FLASH1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF

8
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h
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@ -420,6 +420,14 @@ typedef enum {
SYS_WKUP5 = PI_8,
SYS_WKUP6 = PI_11,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = PD_11,
QSPI_FLASH1_IO1 = PD_12,
QSPI_FLASH1_IO2 = PE_2,
QSPI_FLASH1_IO3 = PD_13,
QSPI_FLASH1_SCK = PB_2,
QSPI_FLASH1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h
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@ -354,6 +354,14 @@ typedef enum {
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
/**** QSPI pins ****/
QSPI_FLASH1_IO0 = PD_11,
QSPI_FLASH1_IO1 = PD_12,
QSPI_FLASH1_IO2 = PE_2,
QSPI_FLASH1_IO3 = PD_13,
QSPI_FLASH1_SCK = PB_2,
QSPI_FLASH1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h
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@ -354,6 +354,14 @@ typedef enum {
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,
QSPI1_IO1 = PD_12,
QSPI1_IO2 = PE_2,
QSPI1_IO3 = PD_13,
QSPI1_SCK = PB_2,
QSPI1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h
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@ -359,6 +359,14 @@ typedef enum {
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,
QSPI1_IO1 = PD_12,
QSPI1_IO2 = PE_2,
QSPI1_IO3 = PD_13,
QSPI1_SCK = PB_2,
QSPI1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h
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@ -427,6 +427,14 @@ typedef enum {
SYS_WKUP5 = PI_8,
SYS_WKUP6 = PI_11,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = PC_9,
QSPI_FLASH1_IO1 = PC_10,
QSPI_FLASH1_IO2 = PE_2,
QSPI_FLASH1_IO3 = PD_13,
QSPI_FLASH1_SCK = PB_2,
QSPI_FLASH1_CSN = PB_6,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

9
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h
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@ -159,6 +159,15 @@ typedef enum {
SYS_WKUP1 = PA_0,
SYS_WKUP4 = PA_2,
/**** QSPI pins ****/
QSPI1_IO0 = PB_1,
QSPI1_IO1 = PB_0,
QSPI1_IO2 = PA_7,
QSPI1_IO3 = PA_6,
QSPI1_SCK = PA_3,
QSPI1_CSN = PA_2,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h
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@ -236,6 +236,14 @@ typedef enum {
SYS_WKUP2 = PC_13,
SYS_WKUP4 = PA_2,
/**** QSPI pins ****/
QSPI1_IO0 = PB_1,
QSPI1_IO1 = PB_0,
QSPI1_IO2 = PA_7,
QSPI1_IO3 = PA_6,
QSPI1_SCK = PB_10,
QSPI1_CSN = PB_11,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h
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@ -282,6 +282,14 @@ typedef enum {
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = PE_12,
QSPI_FLASH1_IO1 = PE_13,
QSPI_FLASH1_IO2 = PE_14,
QSPI_FLASH1_IO3 = PE_15,
QSPI_FLASH1_SCK = PE_10,
QSPI_FLASH1_CSN = PE_11,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

16
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h
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@ -258,6 +258,22 @@ typedef enum {
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
/**** QSPI pins ****/
QSPI1_IO0 = PE_12,
QSPI1_IO1 = PE_13,
QSPI1_IO2 = PE_14,
QSPI1_IO3 = PE_15,
QSPI1_SCK = PE_10,
QSPI1_CSN = PE_11,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = QSPI1_IO0,
QSPI_FLASH1_IO1 = QSPI1_IO1,
QSPI_FLASH1_IO2 = QSPI1_IO2,
QSPI_FLASH1_IO3 = QSPI1_IO3,
QSPI_FLASH1_SCK = QSPI1_SCK,
QSPI_FLASH1_CSN = QSPI1_CSN,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h
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@ -341,6 +341,14 @@ typedef enum {
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = PB_1,
QSPI_FLASH1_IO1 = PB_0,
QSPI_FLASH1_IO2 = PA_7,
QSPI_FLASH1_IO3 = PA_6,
QSPI_FLASH1_SCK = PB_11,
QSPI_FLASH1_CSN = PA_3,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

8
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h
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@ -317,6 +317,14 @@ typedef enum {
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
/**** QSPI pins ****/
QSPI1_IO0 = PE_12,
QSPI1_IO1 = PB_0,
QSPI1_IO2 = PE_14,
QSPI1_IO3 = PE_15,
QSPI1_SCK = PB_10,
QSPI1_CSN = PA_2,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;