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[NUC472/M453] Fix greentea lp_ticker failed tests

pull/2861/head
ccli8 2016-09-07 14:53:53 +08:00
parent dee2f276ef
commit 516efa371e
2 changed files with 67 additions and 61 deletions
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65
targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
View File

@ -24,16 +24,13 @@
#include "critical.h"
// lp_ticker tick = us = timestamp
// clock of timer peripheral = ms
#define US_PER_TICK (1)
#define US_PER_TICK (1)
#define US_PER_SEC (1000 * 1000)
#define MS_PER_TMR2_INT (1000 * 10)
#define TMR2_FIRE_FREQ (1000 / MS_PER_TMR2_INT)
#define MS_PER_TMR2_CLK 1
#define TMR2_CLK_FREQ (1000 / MS_PER_TMR2_CLK)
#define MS_PER_TMR3_CLK 1
#define TMR3_CLK_FREQ (1000 / MS_PER_TMR3_CLK)
#define US_PER_TMR2_INT (US_PER_SEC * 10)
#define TMR2_CLK_PER_SEC (__LXT)
#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
#define TMR3_CLK_PER_SEC (__LXT)
static void tmr2_vec(void);
static void tmr3_vec(void);
@ -41,8 +38,8 @@ static void lp_ticker_arm_cd(void);
static int lp_ticker_inited = 0;
static volatile uint32_t counter_major = 0;
static volatile int cd_major_minor_ms = 0;
static volatile int cd_minor_ms = 0;
static volatile int cd_major_minor_clks = 0;
static volatile int cd_minor_clks = 0;
static volatile uint32_t wakeup_tick = (uint32_t) -1;
// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
@ -61,8 +58,8 @@ void lp_ticker_init(void)
lp_ticker_inited = 1;
counter_major = 0;
cd_major_minor_ms = 0;
cd_minor_ms = 0;
cd_major_minor_clks = 0;
cd_minor_clks = 0;
wakeup_tick = (uint32_t) -1;
// Reset module
@ -78,9 +75,10 @@ void lp_ticker_init(void)
// Configure clock
uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1;
uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK;
MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
// Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
@ -113,8 +111,8 @@ timestamp_t lp_ticker_read()
TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
do {
uint64_t major_minor_ms;
uint32_t minor_ms;
uint64_t major_minor_clks;
uint32_t minor_clks;
// NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
// NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
@ -122,22 +120,22 @@ timestamp_t lp_ticker_read()
core_util_critical_section_enter();
// NOTE: Order of reading minor_us/carry here is significant.
minor_ms = TIMER_GetCounter(timer2_base) * MS_PER_TMR2_CLK;
minor_clks = TIMER_GetCounter(timer2_base);
uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
// When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
if (carry && minor_ms > (MS_PER_TMR2_INT / 2)) {
major_minor_ms = (counter_major + 1) * MS_PER_TMR2_INT;
if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
}
else {
major_minor_ms = (counter_major + carry) * MS_PER_TMR2_INT + minor_ms;
major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
}
core_util_critical_section_exit();
}
while (minor_ms == 0 || minor_ms == MS_PER_TMR2_INT);
while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
// Add power-down compensation
return (major_minor_ms * 1000 / US_PER_TICK);
return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
}
while (0);
}
@ -151,8 +149,8 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
// NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
cd_major_minor_ms = delta * US_PER_TICK / 1000;
cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
lp_ticker_arm_cd();
}
@ -177,8 +175,12 @@ static void tmr3_vec(void)
{
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
cd_major_minor_ms -= cd_minor_ms;
if (cd_major_minor_ms > 0) {
cd_major_minor_clks -= cd_minor_clks;
if (cd_major_minor_clks <= 0) {
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
lp_ticker_irq_handler();
}
else {
lp_ticker_arm_cd();
}
}
@ -191,15 +193,16 @@ static void lp_ticker_arm_cd(void)
timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
// One-shot mode, Clock = 1 KHz
uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_FREQ - 1;
uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
cd_minor_ms = cd_major_minor_ms;
cd_minor_ms = NU_CLAMP(cd_minor_ms, TMR_CMP_MIN * MS_PER_TMR3_CLK, TMR_CMP_MAX * MS_PER_TMR3_CLK);
timer3_base->CMP = cd_minor_ms / MS_PER_TMR3_CLK;
cd_minor_clks = cd_major_minor_clks;
cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
timer3_base->CMP = cd_minor_clks;
TIMER_EnableInt(timer3_base);
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));

63
targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
View File

@ -24,16 +24,13 @@
#include "critical.h"
// lp_ticker tick = us = timestamp
// clock of timer peripheral = ms
#define US_PER_TICK (1)
#define US_PER_TICK (1)
#define US_PER_SEC (1000 * 1000)
#define MS_PER_TMR2_INT (1000 * 10)
#define TMR2_FIRE_FREQ (1000 / MS_PER_TMR2_INT)
#define MS_PER_TMR2_CLK 1
#define TMR2_CLK_FREQ (1000 / MS_PER_TMR2_CLK)
#define MS_PER_TMR3_CLK 1
#define TMR3_CLK_FREQ (1000 / MS_PER_TMR3_CLK)
#define US_PER_TMR2_INT (US_PER_SEC * 10)
#define TMR2_CLK_PER_SEC (__LXT)
#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
#define TMR3_CLK_PER_SEC (__LXT)
static void tmr2_vec(void);
static void tmr3_vec(void);
@ -41,8 +38,8 @@ static void lp_ticker_arm_cd(void);
static int lp_ticker_inited = 0;
static volatile uint32_t counter_major = 0;
static volatile int cd_major_minor_ms = 0;
static volatile int cd_minor_ms = 0;
static volatile int cd_major_minor_clks = 0;
static volatile int cd_minor_clks = 0;
static volatile uint32_t wakeup_tick = (uint32_t) -1;
// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
@ -61,8 +58,8 @@ void lp_ticker_init(void)
lp_ticker_inited = 1;
counter_major = 0;
cd_major_minor_ms = 0;
cd_minor_ms = 0;
cd_major_minor_clks = 0;
cd_minor_clks = 0;
wakeup_tick = (uint32_t) -1;
// Reset module
@ -78,9 +75,10 @@ void lp_ticker_init(void)
// Configure clock
uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1;
uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK;
MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
// Continuous mode
((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk;
@ -112,8 +110,8 @@ timestamp_t lp_ticker_read()
TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
do {
uint64_t major_minor_ms;
uint32_t minor_ms;
uint64_t major_minor_clks;
uint32_t minor_clks;
// NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
// NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
@ -121,22 +119,22 @@ timestamp_t lp_ticker_read()
core_util_critical_section_enter();
// NOTE: Order of reading minor_us/carry here is significant.
minor_ms = TIMER_GetCounter(timer2_base) * MS_PER_TMR2_CLK;
minor_clks = TIMER_GetCounter(timer2_base);
uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
// When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
if (carry && minor_ms > (MS_PER_TMR2_INT / 2)) {
major_minor_ms = (counter_major + 1) * MS_PER_TMR2_INT;
if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
}
else {
major_minor_ms = (counter_major + carry) * MS_PER_TMR2_INT + minor_ms;
major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
}
core_util_critical_section_exit();
}
while (minor_ms == 0 || minor_ms == MS_PER_TMR2_INT);
while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
// Add power-down compensation
return (major_minor_ms * 1000 / US_PER_TICK);
return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
}
while (0);
}
@ -150,7 +148,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
// NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
cd_major_minor_ms = delta * US_PER_TICK / 1000;
cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
lp_ticker_arm_cd();
}
@ -176,8 +174,12 @@ static void tmr3_vec(void)
{
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
cd_major_minor_ms -= cd_minor_ms;
if (cd_major_minor_ms > 0) {
cd_major_minor_clks -= cd_minor_clks;
if (cd_major_minor_clks <= 0) {
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
lp_ticker_irq_handler();
}
else {
lp_ticker_arm_cd();
}
}
@ -190,14 +192,15 @@ static void lp_ticker_arm_cd(void)
timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
// One-shot mode, Clock = 1 KHz
uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_FREQ - 1;
uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3 | TIMER_CTL_CNTDATEN_Msk;
cd_minor_ms = cd_major_minor_ms;
cd_minor_ms = NU_CLAMP(cd_minor_ms, TMR_CMP_MIN * MS_PER_TMR3_CLK, TMR_CMP_MAX * MS_PER_TMR3_CLK);
timer3_base->CMP = cd_minor_ms / MS_PER_TMR3_CLK;
cd_minor_clks = cd_major_minor_clks;
cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
timer3_base->CMP = cd_minor_clks;
TIMER_EnableInt(timer3_base);
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));