mirror of https://github.com/ARMmbed/mbed-os.git
K22F support added
And that is a bit of an overstatement. But mbed blinky works :D. And nothing else works atm. Still more than before today. Every option in device.h is disabled (and won't work), but now they can slowly be enabled (they will need pinouts and most some will need some changes in the mbed api files). One of the major issues was that the KSDK is intended to only compile relevant peripherals, but the mbed build system does not support this. So now for the affected peripherals (with the K22F and K64F) instead of throwing an error when no valid CPU is found for them, it sets a define, and the relevant .h and .c files have an #ifndef for that define. This way it doesn't need to be manually set for each mbed target.pull/476/head
Sissors
parent
fc5473216a
commit
50ce80b7d2
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@ -38,6 +38,7 @@
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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__initial_sp EQU 0x20003FFF ; Top of RAM
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PRESERVE8
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@ -50,9 +51,8 @@
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ;NMI Handler
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DCD HardFault_Handler ;Hard Fault Handler
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@ -460,48 +460,24 @@ FSEC EQU 0xFE
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; </h>
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA FlashConfig, DATA, READONLY
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__FlashConfig
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AREA |.ARM.__at_0x400|, CODE, READONLY
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0, FPROT1, FPROT2, FPROT3
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DCB FSEC, FOPT, FEPROT, FDPROT
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ENDIF
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_NVIC_ICER0 EQU 0xE000E180
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_NVIC_ICPR0 EQU 0xE000E280
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT init_data_bss
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IMPORT __main
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IF :LNOT::DEF:RAM_TARGET
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LDR R0, =FlashConfig ; dummy read, workaround for flashConfig
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ENDIF
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CPSID I ; Mask interrupts
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LDR R0, =_NVIC_ICER0 ; Disable interrupts and clear pending flags
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LDR R1, =_NVIC_ICPR0
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LDR R2, =0xFFFFFFFF
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MOV R3, #8
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_irq_clear
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CBZ R3, _irq_clear_end
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STR R2, [R0], #4 ; NVIC_ICERx - clear enable IRQ register
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STR R2, [R1], #4 ; NVIC_ICPRx - clear pending IRQ register
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SUB R3, R3, #1
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B _irq_clear
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_irq_clear_end
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =init_data_bss
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BLX R0
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CPSIE i ; Unmask interrupts
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LDR R0, =__main
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BX R0
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ENDP
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@ -73,7 +73,7 @@
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*/
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#include <stdint.h>
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#include "device/fsl_device_registers.h"
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#include "cmsis.h"
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@ -0,0 +1,443 @@
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/*
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* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "fsl_device_registers.h"
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#include "fsl_sim_hal.h"
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#include "fsl_clock_manager.h"
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#include "fsl_osc_hal.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Table of base addresses for instances. */
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extern const uint32_t g_simBaseAddr[];
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extern const uint32_t g_mcgBaseAddr[];
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const uint32_t g_oscBaseAddr[] = OSC_BASE_ADDRS;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetDmaFreq
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* Description : Gets the clock frequency for DMA module
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* This function gets the clock frequency for DMA moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kSystemClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetDmamuxFreq
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* Description : Gets the clock frequency for DMAMUX module
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* This function gets the clock frequency for DMAMUX moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kBusClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetPortFreq
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* Description : Gets the clock frequency for PORT module
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* This function gets the clock frequency for PORT moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kLpoClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetEwmFreq
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* Description : Gets the clock frequency for Ewm module
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* This function gets the clock frequency for Ewm moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kLpoClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetFtfFreq
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* Description : Gets the clock frequency for FTF module. (Flash Memory)
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* This function gets the clock frequency for FTF moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kFlashClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetCrcFreq
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* Description : Gets the clock frequency for CRC module
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* This function gets the clock frequency for CRC moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kBusClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetAdcFreq
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* Description : Gets the clock frequency for ADC module
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* This function gets the clock frequency for ADC moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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uint32_t divider;
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CLOCK_SYS_GetFreq(kOsc0ErClock, &freq);
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divider = OSC_HAL_GetExternalRefClkDivCmd(g_oscBaseAddr[0]);
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freq = freq >> divider; /* 2 bits divider, divide by 1/2/4/8 */
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetCmpFreq
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* Description : Gets the clock frequency for CMP module
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* This function gets the clock frequency for CMP moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kBusClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetVrefFreq
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* Description : Gets the clock frequency for VREF module
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* This function gets the clock frequency for VREF moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kBusClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetPdbFreq
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* Description : Gets the clock frequency for PDB module
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* This function gets the clock frequency for PDB moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kBusClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetFtmFreq
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* Description : Gets the clock frequency for FTM module. (FlexTimers)
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* This function gets the clock frequency for FTM moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetFtmFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kMcgFfClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetPitFreq
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* Description : Gets the clock frequency for Pit module.
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* This function gets the clock frequency for Pit moudle.
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*
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*END**************************************************************************/
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uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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CLOCK_SYS_GetFreq(kBusClock, &freq);
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return freq;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_SYS_GetUsbFreq
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* Description : Gets the clock frequency for USB FS OTG module.
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* This function gets the clock frequency for USB FS OTG moudle.
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*
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||||
*END**************************************************************************/
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||||
uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance)
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{
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uint32_t freq = 0;
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uint8_t setting;
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clock_names_t clockName;
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uint32_t frac = 0;
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uint32_t divider = 0;
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/* get the sim clock source setting*/
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if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockUsbSrc, &setting) != kSimHalSuccess)
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{
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return freq;
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}
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||||
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||||
switch ((sim_usb_clock_source_t)setting)
|
||||
{
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case kSimUsbSrcClkIn: /* Core/system clock */
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clockName = kUSB_CLKIN;
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||||
break;
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case kSimUsbSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */
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/* get the sim clock source setting*/
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if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting) != kSimHalSuccess)
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||||
{
|
||||
return freq;
|
||||
}
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||||
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||||
switch ((sim_pllfll_clock_sel_t)setting)
|
||||
{
|
||||
case kSimPllFllSelFll: /* Fll clock */
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||||
clockName = kMcgFllClock;
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||||
break;
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case kSimPllFllSelIrc: /* Irc 48Mhz clock */
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clockName = kIrc48mClock;
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||||
break;
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||||
default:
|
||||
clockName = kReserved;
|
||||
break;
|
||||
}
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break;
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default:
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||||
clockName = kReserved;
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||||
break;
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}
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||||
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||||
/* Get ref clock freq */
|
||||
CLOCK_SYS_GetFreq(clockName, &freq);
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||||
|
||||
/* Get divider and frac */
|
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CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbDiv, ÷r);
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CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbFrac, &frac);
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||||
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/* Divider output clock = Divider input clock × [ (FRAC+1) / (DIV+1) ]*/
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freq = (freq) * (frac + 1) / (divider + 1);
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||||
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||||
return freq;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_SYS_GetSpiFreq
|
||||
* Description : Gets the clock frequency for SPI module.
|
||||
* This function gets the clock frequency for SPI moudle.
|
||||
*
|
||||
*END**************************************************************************/
|
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uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance)
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||||
{
|
||||
uint32_t freq = 0;
|
||||
CLOCK_SYS_GetFreq(kBusClock, &freq);
|
||||
return freq;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_SYS_GetI2cFreq
|
||||
* Description : Gets the clock frequency for I2C module.
|
||||
* This function gets the clock frequency for I2C moudle.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance)
|
||||
{
|
||||
uint32_t freq = 0;
|
||||
CLOCK_SYS_GetFreq(kBusClock, &freq);
|
||||
return freq;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_SYS_GetUartFreq
|
||||
* Description : Gets the clock frequency for UART module.
|
||||
* This function gets the clock frequency for UART moudle.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance)
|
||||
{
|
||||
uint32_t freq = 0;
|
||||
|
||||
switch (instance)
|
||||
{
|
||||
case 0:
|
||||
case 1:
|
||||
CLOCK_SYS_GetFreq(kSystemClock, &freq);
|
||||
break;
|
||||
case 2:
|
||||
CLOCK_SYS_GetFreq(kBusClock, &freq);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_SYS_GetLpuartFreq
|
||||
* Description : Gets the clock frequency for LPUART module.
|
||||
* This function gets the clock frequency for LPUART moudle.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
|
||||
{
|
||||
uint32_t freq = 0;
|
||||
uint8_t setting;
|
||||
uint8_t setting1;
|
||||
clock_names_t clockName;
|
||||
uint32_t divider = 0;
|
||||
|
||||
/* get the sim clock source setting*/
|
||||
if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockLpuartSrc, &setting) != kSimHalSuccess)
|
||||
{
|
||||
return freq;
|
||||
}
|
||||
|
||||
switch ((sim_lpuart_clock_source_t)setting)
|
||||
{
|
||||
case kSimLpuartSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */
|
||||
/* get the sim clock source setting*/
|
||||
if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting1) != kSimHalSuccess)
|
||||
{
|
||||
return freq;
|
||||
}
|
||||
|
||||
switch ((sim_pllfll_clock_sel_t)setting1)
|
||||
{
|
||||
case kSimPllFllSelFll: /* Fll clock */
|
||||
clockName = kMcgFllClock;
|
||||
break;
|
||||
case kSimPllFllSelIrc: /* Irc 48Mhz clock */
|
||||
clockName = kIrc48mClock;
|
||||
break;
|
||||
default:
|
||||
clockName = kReserved;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case kSimLpuartSrcOscErclk: /* OscErClk with divider */
|
||||
clockName = kOsc0ErClock;
|
||||
break;
|
||||
case kSimLpuartSrcMcgIrclk: /* MCGIRCLK */
|
||||
clockName = kMcgIrClock;
|
||||
break;
|
||||
default:
|
||||
clockName = kReserved;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Get ref clock freq */
|
||||
CLOCK_SYS_GetFreq(clockName, &freq);
|
||||
|
||||
if ((sim_lpuart_clock_source_t)setting == kSimLpuartSrcOscErclk)
|
||||
{
|
||||
divider = OSC_HAL_GetExternalRefClkDivCmd(g_oscBaseAddr[0]);
|
||||
freq = freq >> divider; /* 2 bits divider, divide by 1/2/4/8 */
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_SYS_GetSaiFreq
|
||||
* Description : Gets the clock frequency for I2S module
|
||||
* This function gets the clock frequency for I2S moudle.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance)
|
||||
{
|
||||
uint32_t freq = 0;
|
||||
CLOCK_SYS_GetFreq(kBusClock, &freq);
|
||||
return freq;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_SYS_GetGpioFreq
|
||||
* Description : Gets the clock frequency for GPIO module.
|
||||
* This function gets the clock frequency for GPIO moudle.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance)
|
||||
{
|
||||
uint32_t freq = 0;
|
||||
|
||||
CLOCK_SYS_GetFreq(kPlatformClock, &freq);
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
@ -0,0 +1,947 @@
|
|||
/*
|
||||
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#if !defined(__FSL_CLOCK_K22F12810_H__)
|
||||
#define __FSL_CLOCK_K22F12810_H__
|
||||
|
||||
/*! @addtogroup clock_manager*/
|
||||
/*! @{*/
|
||||
|
||||
/*! @file*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for DMA module.
|
||||
*
|
||||
* This function gets the clock frequence for DMA moudle.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for DMAMUX module.
|
||||
*
|
||||
* This function gets the clock frequence for DMAMUX moudle.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for PORT module.
|
||||
*
|
||||
* This function gets the clock frequence for PORT moudle.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for EWM module.
|
||||
*
|
||||
* This function gets the clock frequence for EWM moudle.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for FTF module. (Flash Memory)
|
||||
*
|
||||
* This function gets the clock frequence for FTF module. (Flash Memory)
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for CRC module.
|
||||
*
|
||||
* This function gets the clock frequence for CRC module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for ADC module.
|
||||
*
|
||||
* This function gets the clock frequence for ADC module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for CMP module.
|
||||
*
|
||||
* This function gets the clock frequence for CMP module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for VREF module.
|
||||
*
|
||||
* This function gets the clock frequence for VREF module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for PDB module.
|
||||
*
|
||||
* This function gets the clock frequence for PDB module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for FTM module. (FlexTimer)
|
||||
*
|
||||
* This function gets the clock frequence for FTM module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetFtmFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for PIT module.
|
||||
*
|
||||
* This function gets the clock frequence for PIT module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for USB FS OTG module
|
||||
*
|
||||
* This function gets the clock frequence for USB FS OTG module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for SPI module
|
||||
*
|
||||
* This function gets the clock frequence for SPI module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for I2C module
|
||||
*
|
||||
* This function gets the clock frequence for I2C module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for UART module
|
||||
*
|
||||
* This function gets the clock frequence for UART module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for LPUART module
|
||||
*
|
||||
* This function gets the clock frequence for LPUART module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for I2S module.
|
||||
*
|
||||
* This function gets the clock frequence for I2S module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Gets the clock frequency for GPIO module
|
||||
*
|
||||
* This function gets the clock frequence for GPIO module.
|
||||
* @param instance module device instance
|
||||
* @return freq clock frequence for this module
|
||||
*/
|
||||
uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for DMA module.
|
||||
*
|
||||
* This function enables the clock for DMA moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableDmaClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for DMA module.
|
||||
*
|
||||
* This function disables the clock for DMA moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableDmaClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for DMA module.
|
||||
*
|
||||
* This function will get the clock gate state for DMA moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetDmaGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for DMAMUX module.
|
||||
*
|
||||
* This function enables the clock for DMAMUX moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableDmamuxClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for DMAMUX module.
|
||||
*
|
||||
* This function disables the clock for DMAMUX moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableDmamuxClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for DMAMUX module.
|
||||
*
|
||||
* This function will get the clock gate state for DMAMUX moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetDmamuxGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for PORT module.
|
||||
*
|
||||
* This function enables the clock for PORT moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnablePortClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnablePortClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for PORT module.
|
||||
*
|
||||
* This function disables the clock for PORT moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisablePortClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisablePortClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for PORT module.
|
||||
*
|
||||
* This function will get the clock gate state for PORT moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetPortGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetPortGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for EWM module.
|
||||
*
|
||||
* This function enables the clock for EWM moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableEwmClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for EWM module.
|
||||
*
|
||||
* This function disables the clock for EWM moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableEwmClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for EWM module.
|
||||
*
|
||||
* This function will get the clock gate state for EWM moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetEwmGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for FTF module.
|
||||
*
|
||||
* This function enables the clock for FTF moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableFtfClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for FTF module.
|
||||
*
|
||||
* This function disables the clock for FTF moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableFtfClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for FTF module.
|
||||
*
|
||||
* This function will get the clock gate state for FTF moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetFtfGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for CRC module.
|
||||
*
|
||||
* This function enables the clock for CRC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableCrcClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for CRC module.
|
||||
*
|
||||
* This function disables the clock for CRC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableCrcClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for CRC module.
|
||||
*
|
||||
* This function will get the clock gate state for CRC moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetCrcGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for ADC module.
|
||||
*
|
||||
* This function enables the clock for ADC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableAdcClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for ADC module.
|
||||
*
|
||||
* This function disables the clock for ADC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableAdcClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for ADC module.
|
||||
*
|
||||
* This function will get the clock gate state for ADC moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetAdcGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for CMP module.
|
||||
*
|
||||
* This function enables the clock for CMP moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableCmpClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for CMP module.
|
||||
*
|
||||
* This function disables the clock for CMP moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableCmpClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for CMP module.
|
||||
*
|
||||
* This function will get the clock gate state for CMP moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetCmpGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for DAC module.
|
||||
*
|
||||
* This function enables the clock for DAC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableDacClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableDacClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for DAC module.
|
||||
*
|
||||
* This function disables the clock for DAC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableDacClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableDacClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for DAC module.
|
||||
*
|
||||
* This function will get the clock gate state for DAC moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetDacGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for VREF module.
|
||||
*
|
||||
* This function enables the clock for VREF moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableVrefClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for VREF module.
|
||||
*
|
||||
* This function disables the clock for VREF moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableVrefClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for VREF module.
|
||||
*
|
||||
* This function will get the clock gate state for VREF moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetVrefGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for SAI module.
|
||||
*
|
||||
* This function enables the clock for SAI moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableSaiClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for SAI module.
|
||||
*
|
||||
* This function disables the clock for SAI moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableSaiClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for SAI module.
|
||||
*
|
||||
* This function will get the clock gate state for SAI moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetSaiGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for PDB module.
|
||||
*
|
||||
* This function enables the clock for PDB moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnablePdbClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for PDB module.
|
||||
*
|
||||
* This function disables the clock for PDB moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisablePdbClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for PDB module.
|
||||
*
|
||||
* This function will get the clock gate state for PDB moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetPdbGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for FTM module.
|
||||
*
|
||||
* This function enables the clock for FTM moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableFtmClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for FTM module.
|
||||
*
|
||||
* This function disables the clock for FTM moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableFtmClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for FTM module.
|
||||
*
|
||||
* This function will get the clock gate state for FTM moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetFtmGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for PIT module.
|
||||
*
|
||||
* This function enables the clock for PIT moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnablePitClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnablePitClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for PIT module.
|
||||
*
|
||||
* This function disables the clock for PIT moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisablePitClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisablePitClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for PIT module.
|
||||
*
|
||||
* This function will get the clock gate state for PIT moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetPitGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for LPTIMER module.
|
||||
*
|
||||
* This function enables the clock for LPTIMER moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableLptimerClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableLptimerClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for LPTIMER module.
|
||||
*
|
||||
* This function disables the clock for LPTIMER moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableLptimerClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableLptimerClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for LPTIMER module.
|
||||
*
|
||||
* This function will get the clock gate state for LPTIMER moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetLptimerGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetLptimerGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for RTC module.
|
||||
*
|
||||
* This function enables the clock for RTC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableRtcClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for RTC module.
|
||||
*
|
||||
* This function disables the clock for RTC moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableRtcClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for RTC module.
|
||||
*
|
||||
* This function will get the clock gate state for RTC moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetRtcGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for USBFS module.
|
||||
*
|
||||
* This function enables the clock for USBFS moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableUsbClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableUsbClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for USBFS module.
|
||||
*
|
||||
* This function disables the clock for USBFS moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableUsbClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableUsbClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for USB module.
|
||||
*
|
||||
* This function will get the clock gate state for USB moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetUsbGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetUsbGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for SPI module.
|
||||
*
|
||||
* This function enables the clock for SPI moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableSpiClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for SPI module.
|
||||
*
|
||||
* This function disables the clock for SPI moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableSpiClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for SPI module.
|
||||
*
|
||||
* This function will get the clock gate state for SPI moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetSpiGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for I2C module.
|
||||
*
|
||||
* This function enables the clock for I2C moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableI2cClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for I2C module.
|
||||
*
|
||||
* This function disables the clock for I2C moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableI2cClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for I2C module.
|
||||
*
|
||||
* This function will get the clock gate state for I2C moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetI2cGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for UART module.
|
||||
*
|
||||
* This function enables the clock for UART moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableUartClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableUartClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for UART module.
|
||||
*
|
||||
* This function disables the clock for UART moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableUartClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableUartClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for UART module.
|
||||
*
|
||||
* This function will get the clock gate state for UART moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetUartGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for LPUART module.
|
||||
*
|
||||
* This function enables the clock for LPUART moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_EnableLpuartClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for LPUART module.
|
||||
*
|
||||
* This function disables the clock for LPUART moudle.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance)
|
||||
{
|
||||
SIM_HAL_DisableLpuartClock(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for LPUART module.
|
||||
*
|
||||
* This function will get the clock gate state for LPUART moudle.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
|
||||
{
|
||||
return SIM_HAL_GetLpuartGateCmd(g_simBaseAddr[0], instance);
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* __FSL_CLOCK_K22F12810_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,779 @@
|
|||
/*
|
||||
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#if !defined(__FSL_SIM_HAL_K22F12810_H__)
|
||||
#define __FSL_SIM_HAL_K22F12810_H__
|
||||
|
||||
/*! @addtogroup sim_hal*/
|
||||
/*! @{*/
|
||||
|
||||
/*! @file*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief SIM USB clock source */
|
||||
typedef enum _sim_usb_clock_source
|
||||
{
|
||||
kSimUsbSrcClkIn, /* USB CLKIN Clock */
|
||||
kSimUsbSrcPllFllSel /* clock as selected by SOPT2[PLLFLLSEL] */
|
||||
} sim_usb_clock_source_t;
|
||||
|
||||
/*! @brief SIM LPUART clock source */
|
||||
typedef enum _sim_lpuart_clock_source
|
||||
{
|
||||
kSimLpuartSrcNone, /* Clock disabled */
|
||||
kSimLpuartSrcPllFllSel, /* Clock as selected by SOPT2[PLLFLLSEL] */
|
||||
kSimLpuartSrcOscErclk, /* OscErClk with special divider */
|
||||
kSimLpuartSrcMcgIrclk /* MCGIRCLK */
|
||||
} sim_lpuart_clock_source_t;
|
||||
|
||||
/*! @brief SIM PLLFLLSEL clock source select */
|
||||
typedef enum _sim_pllfll_clock_sel
|
||||
{
|
||||
kSimPllFllSelFll, /* Fll clock */
|
||||
kSimPllFllSelRsvd, /* reserved */
|
||||
kSimPllFllSelRsvd1, /* reserved */
|
||||
kSimPllFllSelIrc /* IRC 48Mhz */
|
||||
} sim_pllfll_clock_sel_t;
|
||||
|
||||
/*! @brief SIM OSC32KSEL clock source select */
|
||||
typedef enum _sim_osc32k_clock_sel
|
||||
{
|
||||
kSimOsc32kSelOsc32k, /* OSC 32k clock */
|
||||
kSimOsc32kSelReserved, /* Reserved */
|
||||
kSimOsc32kSelRtc32k, /* RTC 32k clock */
|
||||
kSimOsc32kSelLpo /* LPO clock */
|
||||
} sim_osc32k_clock_sel_t;
|
||||
|
||||
/*! @brief SIM TRACESEL clock source select */
|
||||
typedef enum _sim_trace_clock_sel
|
||||
{
|
||||
kSimTraceMcgoutClk, /* MCG out clock */
|
||||
kSimTraceCoreClk /* core clock */
|
||||
} sim_trace_clock_sel_t;
|
||||
|
||||
/*! @brief SIM CLKOUT_SEL clock source select */
|
||||
typedef enum _sim_clkout_clock_sel
|
||||
{
|
||||
kSimClkoutReserved, /* Reserved */
|
||||
kSimClkoutReserved1, /* Reserved */
|
||||
kSimClkoutFlashClk, /* Flash clock */
|
||||
kSimClkoutLpoClk, /* LPO clock */
|
||||
kSimClkoutMcgIrcClk, /* MCG out clock */
|
||||
kSimClkoutRtc32kClk, /* RTC 32k clock */
|
||||
kSimClkoutOscErClk,
|
||||
KsimClkoutIrcClk
|
||||
} sim_clkout_clock_sel_t;
|
||||
|
||||
/*! @brief SIM RTCCLKOUTSEL clock source select */
|
||||
typedef enum _sim_rtcclkout_clock_sel
|
||||
{
|
||||
kSimRtcClkout1hzClk, /* 1Hz clock */
|
||||
kSimRtcClkout32kClk /* 32KHz clock */
|
||||
} sim_rtcclkout_clock_sel_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*! @name IP related clock feature APIs*/
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for DMA module.
|
||||
*
|
||||
* This function enables the clock for DMA moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for DMA module.
|
||||
*
|
||||
* This function disables the clock for DMA moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableDmaClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for DMA module.
|
||||
*
|
||||
* This function will get the clock gate state for DMA moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetDmaGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for DMAMUX module.
|
||||
*
|
||||
* This function enables the clock for DMAMUX moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableDmamuxClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for DMAMUX module.
|
||||
*
|
||||
* This function disables the clock for DMAMUX moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableDmamuxClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for DMAMUX module.
|
||||
*
|
||||
* This function will get the clock gate state for DMAMUX moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetDmamuxGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for PORT module.
|
||||
*
|
||||
* This function enables the clock for PORT moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnablePortClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for PORT module.
|
||||
*
|
||||
* This function disables the clock for PORT moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisablePortClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for PORT module.
|
||||
*
|
||||
* This function will get the clock gate state for PORT moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetPortGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for EWM module.
|
||||
*
|
||||
* This function enables the clock for EWM moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableEwmClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for EWM module.
|
||||
*
|
||||
* This function disables the clock for EWM moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for EWM module.
|
||||
*
|
||||
* This function will get the clock gate state for EWM moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for FTF module.
|
||||
*
|
||||
* This function enables the clock for FTF moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableFtfClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for FTF module.
|
||||
*
|
||||
* This function disables the clock for FTF moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableFtfClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for FTF module.
|
||||
*
|
||||
* This function will get the clock gate state for FTF moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetFtfGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for CRC module.
|
||||
*
|
||||
* This function enables the clock for CRC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableCrcClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for CRC module.
|
||||
*
|
||||
* This function disables the clock for CRC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for CRC module.
|
||||
*
|
||||
* This function will get the clock gate state for CRC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for ADC module.
|
||||
*
|
||||
* This function enables the clock for ADC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableAdcClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for ADC module.
|
||||
*
|
||||
* This function disables the clock for ADC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableAdcClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for ADC module.
|
||||
*
|
||||
* This function will get the clock gate state for ADC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetAdcGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for CMP module.
|
||||
*
|
||||
* This function enables the clock for CMP moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableCmpClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for CMP module.
|
||||
*
|
||||
* This function disables the clock for CMP moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableCmpClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for CMP module.
|
||||
*
|
||||
* This function will get the clock gate state for CMP moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetCmpGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for DAC module.
|
||||
*
|
||||
* This function enables the clock for DAC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for DAC module.
|
||||
*
|
||||
* This function disables the clock for DAC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for DAC module.
|
||||
*
|
||||
* This function will get the clock gate state for DAC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for VREF module.
|
||||
*
|
||||
* This function enables the clock for VREF moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableVrefClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for VREF module.
|
||||
*
|
||||
* This function disables the clock for VREF moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableVrefClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for VREF module.
|
||||
*
|
||||
* This function will get the clock gate state for VREF moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetVrefGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for SAI module.
|
||||
*
|
||||
* This function enables the clock for SAI moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableSaiClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for SAI module.
|
||||
*
|
||||
* This function disables the clock for SAI moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableSaiClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for SAI module.
|
||||
*
|
||||
* This function will get the clock gate state for SAI moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetSaiGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for PDB module.
|
||||
*
|
||||
* This function enables the clock for PDB moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnablePdbClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for PDB module.
|
||||
*
|
||||
* This function disables the clock for PDB moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisablePdbClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for PDB module.
|
||||
*
|
||||
* This function will get the clock gate state for PDB moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetPdbGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for FTM module.
|
||||
*
|
||||
* This function enables the clock for FTM moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for FTM module.
|
||||
*
|
||||
* This function disables the clock for FTM moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for FTM module.
|
||||
*
|
||||
* This function will get the clock gate state for FTM moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for PIT module.
|
||||
*
|
||||
* This function enables the clock for PIT moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnablePitClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for PIT module.
|
||||
*
|
||||
* This function disables the clock for PIT moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisablePitClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for PIT module.
|
||||
*
|
||||
* This function will get the clock gate state for PIT moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetPitGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for LPTIMER module.
|
||||
*
|
||||
* This function enables the clock for LPTIMER moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableLptimerClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for LPTIMER module.
|
||||
*
|
||||
* This function disables the clock for LPTIMER moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableLptimerClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for LPTIMER module.
|
||||
*
|
||||
* This function will get the clock gate state for LPTIMER moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetLptimerGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for RTC module.
|
||||
*
|
||||
* This function enables the clock for RTC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableRtcClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for RTC module.
|
||||
*
|
||||
* This function disables the clock for RTC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableRtcClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for RTC module.
|
||||
*
|
||||
* This function will get the clock gate state for RTC moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetRtcGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for USBFS module.
|
||||
*
|
||||
* This function enables the clock for USBFS moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableUsbClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for USBFS module.
|
||||
*
|
||||
* This function disables the clock for USBFS moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableUsbClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for USB module.
|
||||
*
|
||||
* This function will get the clock gate state for USB moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetUsbGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for SPI module.
|
||||
*
|
||||
* This function enables the clock for SPI moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableSpiClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for SPI module.
|
||||
*
|
||||
* This function disables the clock for SPI moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableSpiClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for SPI module.
|
||||
*
|
||||
* This function will get the clock gate state for SPI moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetSpiGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for I2C module.
|
||||
*
|
||||
* This function enables the clock for I2C moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableI2cClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for I2C module.
|
||||
*
|
||||
* This function disables the clock for I2C moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableI2cClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for I2C module.
|
||||
*
|
||||
* This function will get the clock gate state for I2C moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetI2cGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for UART module.
|
||||
*
|
||||
* This function enables the clock for UART moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableUartClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for UART module.
|
||||
*
|
||||
* This function disables the clock for UART moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableUartClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for UART module.
|
||||
*
|
||||
* This function will get the clock gate state for UART moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetUartGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Enable the clock for LPUART module.
|
||||
*
|
||||
* This function enables the clock for LPUART moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_EnableLpuartClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Disable the clock for LPUART module.
|
||||
*
|
||||
* This function disables the clock for LPUART moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
*/
|
||||
void SIM_HAL_DisableLpuartClock(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*!
|
||||
* @brief Get the the clock gate state for LPUART module.
|
||||
*
|
||||
* This function will get the clock gate state for LPUART moudle.
|
||||
*
|
||||
* @param baseAddr Base address for current SIM instance.
|
||||
* @param instance module device instance
|
||||
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||
*/
|
||||
bool SIM_HAL_GetLpuartGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* __FSL_SIM_HAL_K22F12810_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
OSC32KCLK = 0,
|
||||
} RTCName;
|
||||
|
||||
typedef enum {
|
||||
UART_0 = 0,
|
||||
UART_1 = 1,
|
||||
UART_2 = 2,
|
||||
UART_3 = 3,
|
||||
UART_4 = 4,
|
||||
} UARTName;
|
||||
|
||||
#define STDIO_UART_TX USBTX
|
||||
#define STDIO_UART_RX USBRX
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = 0,
|
||||
I2C_1 = 1,
|
||||
I2C_2 = 2,
|
||||
} I2CName;
|
||||
|
||||
#define TPM_SHIFT 8
|
||||
typedef enum {
|
||||
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
|
||||
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
|
||||
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
|
||||
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
|
||||
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
|
||||
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
|
||||
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
|
||||
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
|
||||
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
|
||||
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
|
||||
PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
|
||||
PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
|
||||
PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
|
||||
PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
|
||||
PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
|
||||
PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
|
||||
PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
|
||||
PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
|
||||
PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
|
||||
PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
|
||||
PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
|
||||
PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
|
||||
PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
|
||||
PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
|
||||
// could be 4 or could be 3... not sure what register
|
||||
// this is for... too much abstraction
|
||||
PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
|
||||
PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
|
||||
PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
|
||||
PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
|
||||
PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
|
||||
PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
|
||||
PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
|
||||
PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
|
||||
} PWMName;
|
||||
|
||||
#define ADC_INSTANCE_SHIFT 8
|
||||
#define ADC_B_CHANNEL_SHIFT 5
|
||||
typedef enum {
|
||||
ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
|
||||
ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
|
||||
ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
|
||||
ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
|
||||
ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
|
||||
ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
|
||||
ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
|
||||
ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
|
||||
ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
|
||||
ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
|
||||
ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
|
||||
ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
|
||||
ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
|
||||
ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4,
|
||||
ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5,
|
||||
ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6,
|
||||
ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7,
|
||||
ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
|
||||
ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
|
||||
ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
|
||||
ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
|
||||
ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
|
||||
ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
|
||||
ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
|
||||
ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
|
||||
ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
DAC_0 = 0
|
||||
} DACName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = 0,
|
||||
SPI_1 = 1,
|
||||
SPI_2 = 2,
|
||||
} SPIName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/************RTC***************/
|
||||
const PinMap PinMap_RTC[] = {
|
||||
{NC, OSC32KCLK, 0},
|
||||
};
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************DAC***************/
|
||||
const PinMap PinMap_DAC[] = {
|
||||
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{PTE0, UART_1, 3},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{PTE1, UART_1, 3},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define GPIO_PORT_SHIFT 12
|
||||
|
||||
typedef enum {
|
||||
PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTA10 = (0 << GPIO_PORT_SHIFT | 10),
|
||||
PTA11 = (0 << GPIO_PORT_SHIFT | 11),
|
||||
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
|
||||
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
|
||||
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
|
||||
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
|
||||
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
|
||||
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
|
||||
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
|
||||
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
|
||||
PTA20 = (0 << GPIO_PORT_SHIFT | 20),
|
||||
PTA21 = (0 << GPIO_PORT_SHIFT | 21),
|
||||
PTA22 = (0 << GPIO_PORT_SHIFT | 22),
|
||||
PTA23 = (0 << GPIO_PORT_SHIFT | 23),
|
||||
PTA24 = (0 << GPIO_PORT_SHIFT | 24),
|
||||
PTA25 = (0 << GPIO_PORT_SHIFT | 25),
|
||||
PTA26 = (0 << GPIO_PORT_SHIFT | 26),
|
||||
PTA27 = (0 << GPIO_PORT_SHIFT | 27),
|
||||
PTA28 = (0 << GPIO_PORT_SHIFT | 28),
|
||||
PTA29 = (0 << GPIO_PORT_SHIFT | 29),
|
||||
PTA30 = (0 << GPIO_PORT_SHIFT | 30),
|
||||
PTA31 = (0 << GPIO_PORT_SHIFT | 31),
|
||||
PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
|
||||
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
|
||||
PTB12 = (1 << GPIO_PORT_SHIFT | 12),
|
||||
PTB13 = (1 << GPIO_PORT_SHIFT | 13),
|
||||
PTB14 = (1 << GPIO_PORT_SHIFT | 14),
|
||||
PTB15 = (1 << GPIO_PORT_SHIFT | 15),
|
||||
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
|
||||
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
|
||||
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
|
||||
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
|
||||
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
|
||||
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
|
||||
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
|
||||
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
|
||||
PTB24 = (1 << GPIO_PORT_SHIFT | 24),
|
||||
PTB25 = (1 << GPIO_PORT_SHIFT | 25),
|
||||
PTB26 = (1 << GPIO_PORT_SHIFT | 26),
|
||||
PTB27 = (1 << GPIO_PORT_SHIFT | 27),
|
||||
PTB28 = (1 << GPIO_PORT_SHIFT | 28),
|
||||
PTB29 = (1 << GPIO_PORT_SHIFT | 29),
|
||||
PTB30 = (1 << GPIO_PORT_SHIFT | 30),
|
||||
PTB31 = (1 << GPIO_PORT_SHIFT | 31),
|
||||
PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
|
||||
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
|
||||
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
|
||||
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
|
||||
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
|
||||
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
|
||||
PTC16 = (2 << GPIO_PORT_SHIFT | 16),
|
||||
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
|
||||
PTC18 = (2 << GPIO_PORT_SHIFT | 18),
|
||||
PTC19 = (2 << GPIO_PORT_SHIFT | 19),
|
||||
PTC20 = (2 << GPIO_PORT_SHIFT | 20),
|
||||
PTC21 = (2 << GPIO_PORT_SHIFT | 21),
|
||||
PTC22 = (2 << GPIO_PORT_SHIFT | 22),
|
||||
PTC23 = (2 << GPIO_PORT_SHIFT | 23),
|
||||
PTC24 = (2 << GPIO_PORT_SHIFT | 24),
|
||||
PTC25 = (2 << GPIO_PORT_SHIFT | 25),
|
||||
PTC26 = (2 << GPIO_PORT_SHIFT | 26),
|
||||
PTC27 = (2 << GPIO_PORT_SHIFT | 27),
|
||||
PTC28 = (2 << GPIO_PORT_SHIFT | 28),
|
||||
PTC29 = (2 << GPIO_PORT_SHIFT | 29),
|
||||
PTC30 = (2 << GPIO_PORT_SHIFT | 30),
|
||||
PTC31 = (2 << GPIO_PORT_SHIFT | 31),
|
||||
PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTD10 = (3 << GPIO_PORT_SHIFT | 10),
|
||||
PTD11 = (3 << GPIO_PORT_SHIFT | 11),
|
||||
PTD12 = (3 << GPIO_PORT_SHIFT | 12),
|
||||
PTD13 = (3 << GPIO_PORT_SHIFT | 13),
|
||||
PTD14 = (3 << GPIO_PORT_SHIFT | 14),
|
||||
PTD15 = (3 << GPIO_PORT_SHIFT | 15),
|
||||
PTD16 = (3 << GPIO_PORT_SHIFT | 16),
|
||||
PTD17 = (3 << GPIO_PORT_SHIFT | 17),
|
||||
PTD18 = (3 << GPIO_PORT_SHIFT | 18),
|
||||
PTD19 = (3 << GPIO_PORT_SHIFT | 19),
|
||||
PTD20 = (3 << GPIO_PORT_SHIFT | 20),
|
||||
PTD21 = (3 << GPIO_PORT_SHIFT | 21),
|
||||
PTD22 = (3 << GPIO_PORT_SHIFT | 22),
|
||||
PTD23 = (3 << GPIO_PORT_SHIFT | 23),
|
||||
PTD24 = (3 << GPIO_PORT_SHIFT | 24),
|
||||
PTD25 = (3 << GPIO_PORT_SHIFT | 25),
|
||||
PTD26 = (3 << GPIO_PORT_SHIFT | 26),
|
||||
PTD27 = (3 << GPIO_PORT_SHIFT | 27),
|
||||
PTD28 = (3 << GPIO_PORT_SHIFT | 28),
|
||||
PTD29 = (3 << GPIO_PORT_SHIFT | 29),
|
||||
PTD30 = (3 << GPIO_PORT_SHIFT | 30),
|
||||
PTD31 = (3 << GPIO_PORT_SHIFT | 31),
|
||||
PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
|
||||
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
|
||||
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
|
||||
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
|
||||
PTE14 = (4 << GPIO_PORT_SHIFT | 14),
|
||||
PTE15 = (4 << GPIO_PORT_SHIFT | 15),
|
||||
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
|
||||
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
|
||||
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
|
||||
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
|
||||
PTE20 = (4 << GPIO_PORT_SHIFT | 20),
|
||||
PTE21 = (4 << GPIO_PORT_SHIFT | 21),
|
||||
PTE22 = (4 << GPIO_PORT_SHIFT | 22),
|
||||
PTE23 = (4 << GPIO_PORT_SHIFT | 23),
|
||||
PTE24 = (4 << GPIO_PORT_SHIFT | 24),
|
||||
PTE25 = (4 << GPIO_PORT_SHIFT | 25),
|
||||
PTE26 = (4 << GPIO_PORT_SHIFT | 26),
|
||||
PTE27 = (4 << GPIO_PORT_SHIFT | 27),
|
||||
PTE28 = (4 << GPIO_PORT_SHIFT | 28),
|
||||
PTE29 = (4 << GPIO_PORT_SHIFT | 29),
|
||||
PTE30 = (4 << GPIO_PORT_SHIFT | 30),
|
||||
PTE31 = (4 << GPIO_PORT_SHIFT | 31),
|
||||
|
||||
LED_RED = PTA1,
|
||||
LED_GREEN = PTA2,
|
||||
LED_BLUE = PTD5,
|
||||
|
||||
// mbed original LED naming
|
||||
LED1 = LED_RED,
|
||||
LED2 = LED_GREEN,
|
||||
LED3 = LED_BLUE,
|
||||
LED4 = LED_RED,
|
||||
|
||||
//Push buttons
|
||||
SW2 = PTC1,
|
||||
SW3 = PTB17,
|
||||
|
||||
// USB Pins
|
||||
USBTX = PTE0,
|
||||
USBRX = PTE1,
|
||||
|
||||
// Arduino Headers
|
||||
/*
|
||||
D0 = PTC16,
|
||||
D1 = PTC17,
|
||||
D2 = PTB9,
|
||||
D3 = PTA1,
|
||||
D4 = PTB23,
|
||||
D5 = PTA2,
|
||||
D6 = PTC2,
|
||||
D7 = PTC3,
|
||||
D8 = PTA0,
|
||||
D9 = PTC4,
|
||||
D10 = PTD0,
|
||||
D11 = PTD2,
|
||||
D12 = PTD3,
|
||||
D13 = PTD1,
|
||||
D14 = PTE25,
|
||||
D15 = PTE24,
|
||||
|
||||
I2C_SCL = D15,
|
||||
I2C_SDA = D14,
|
||||
|
||||
A0 = PTB2,
|
||||
A1 = PTB3,
|
||||
A2 = PTB10,
|
||||
A3 = PTB11,
|
||||
A4 = PTC10,
|
||||
A5 = PTC11,
|
||||
*/
|
||||
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 2,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 0
|
||||
#define DEVICE_PORTOUT 0
|
||||
#define DEVICE_PORTINOUT 0
|
||||
|
||||
#define DEVICE_INTERRUPTIN 0
|
||||
|
||||
#define DEVICE_ANALOGIN 0
|
||||
#define DEVICE_ANALOGOUT 0
|
||||
|
||||
#define DEVICE_SERIAL 0
|
||||
|
||||
#define DEVICE_I2C 0
|
||||
#define DEVICE_I2CSLAVE 0
|
||||
|
||||
#define DEVICE_SPI 0
|
||||
#define DEVICE_SPISLAVE 0
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 0
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 0
|
||||
|
||||
#define DEVICE_SEMIHOST 0
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
#define DEVICE_ID_LENGTH 24
|
||||
|
||||
#define DEVICE_SLEEP 0
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 0
|
||||
|
||||
#define DEVICE_ERROR_RED 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,929 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_CMP_REGISTERS_H__
|
||||
#define __HW_CMP_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 CMP
|
||||
*
|
||||
* High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_CMP_CR0 - CMP Control Register 0
|
||||
* - HW_CMP_CR1 - CMP Control Register 1
|
||||
* - HW_CMP_FPR - CMP Filter Period Register
|
||||
* - HW_CMP_SCR - CMP Status and Control Register
|
||||
* - HW_CMP_DACCR - DAC Control Register
|
||||
* - HW_CMP_MUXCR - MUX Control Register
|
||||
*
|
||||
* - hw_cmp_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_CMP_INSTANCE_COUNT (2U) /*!< Number of instances of the CMP module. */
|
||||
#define HW_CMP0 (0U) /*!< Instance number for CMP0. */
|
||||
#define HW_CMP1 (1U) /*!< Instance number for CMP1. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_CMP_CR0 - CMP Control Register 0
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_cmp_cr0
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_cmp_cr0_bitfields
|
||||
{
|
||||
uint8_t HYSTCTR : 2; /*!< [1:0] Comparator hard block hysteresis
|
||||
* control */
|
||||
uint8_t RESERVED0 : 2; /*!< [3:2] */
|
||||
uint8_t FILTER_CNT : 3; /*!< [6:4] Filter Sample Count */
|
||||
uint8_t RESERVED1 : 1; /*!< [7] */
|
||||
} B;
|
||||
} hw_cmp_cr0_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire CMP_CR0 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_CMP_CR0_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
|
||||
#define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U)
|
||||
#define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v))
|
||||
#define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v)))
|
||||
#define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
|
||||
#define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual CMP_CR0 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
|
||||
*
|
||||
* Defines the programmable hysteresis level. The hysteresis values associated
|
||||
* with each level are device-specific. See the Data Sheet of the device for the
|
||||
* exact values.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Level 0
|
||||
* - 01 - Level 1
|
||||
* - 10 - Level 2
|
||||
* - 11 - Level 3
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR0_HYSTCTR (0U) /*!< Bit position for CMP_CR0_HYSTCTR. */
|
||||
#define BM_CMP_CR0_HYSTCTR (0x03U) /*!< Bit mask for CMP_CR0_HYSTCTR. */
|
||||
#define BS_CMP_CR0_HYSTCTR (2U) /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
|
||||
#define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */
|
||||
#define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR)
|
||||
|
||||
/*! @brief Set the HYSTCTR field to a new value. */
|
||||
#define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
|
||||
*
|
||||
* Represents the number of consecutive samples that must agree prior to the
|
||||
* comparator ouput filter accepting a new output state. For information regarding
|
||||
* filter programming and latency, see the Functional descriptionThe CMP module
|
||||
* can be used to compare two analog input voltages applied to INP and INM. .
|
||||
*
|
||||
* Values:
|
||||
* - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
|
||||
* legal state, and is not recommended. If SE = 0, COUT = COUTA.
|
||||
* - 001 - One sample must agree. The comparator output is simply sampled.
|
||||
* - 010 - 2 consecutive samples must agree.
|
||||
* - 011 - 3 consecutive samples must agree.
|
||||
* - 100 - 4 consecutive samples must agree.
|
||||
* - 101 - 5 consecutive samples must agree.
|
||||
* - 110 - 6 consecutive samples must agree.
|
||||
* - 111 - 7 consecutive samples must agree.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR0_FILTER_CNT (4U) /*!< Bit position for CMP_CR0_FILTER_CNT. */
|
||||
#define BM_CMP_CR0_FILTER_CNT (0x70U) /*!< Bit mask for CMP_CR0_FILTER_CNT. */
|
||||
#define BS_CMP_CR0_FILTER_CNT (3U) /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
|
||||
#define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */
|
||||
#define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT)
|
||||
|
||||
/*! @brief Set the FILTER_CNT field to a new value. */
|
||||
#define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_CMP_CR1 - CMP Control Register 1
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_cmp_cr1
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_cmp_cr1_bitfields
|
||||
{
|
||||
uint8_t EN : 1; /*!< [0] Comparator Module Enable */
|
||||
uint8_t OPE : 1; /*!< [1] Comparator Output Pin Enable */
|
||||
uint8_t COS : 1; /*!< [2] Comparator Output Select */
|
||||
uint8_t INV : 1; /*!< [3] Comparator INVERT */
|
||||
uint8_t PMODE : 1; /*!< [4] Power Mode Select */
|
||||
uint8_t TRIGM : 1; /*!< [5] Trigger Mode Enable */
|
||||
uint8_t WE : 1; /*!< [6] Windowing Enable */
|
||||
uint8_t SE : 1; /*!< [7] Sample Enable */
|
||||
} B;
|
||||
} hw_cmp_cr1_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire CMP_CR1 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_CMP_CR1_ADDR(x) ((x) + 0x1U)
|
||||
|
||||
#define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
|
||||
#define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U)
|
||||
#define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v))
|
||||
#define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v)))
|
||||
#define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
|
||||
#define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual CMP_CR1 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field EN[0] (RW)
|
||||
*
|
||||
* Enables the Analog Comparator module. When the module is not enabled, it
|
||||
* remains in the off state, and consumes no power. When the user selects the same
|
||||
* input from analog mux to the positive and negative port, the comparator is
|
||||
* disabled automatically.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Analog Comparator is disabled.
|
||||
* - 1 - Analog Comparator is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_EN (0U) /*!< Bit position for CMP_CR1_EN. */
|
||||
#define BM_CMP_CR1_EN (0x01U) /*!< Bit mask for CMP_CR1_EN. */
|
||||
#define BS_CMP_CR1_EN (1U) /*!< Bit field size in bits for CMP_CR1_EN. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_EN field. */
|
||||
#define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_EN. */
|
||||
#define BF_CMP_CR1_EN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN)
|
||||
|
||||
/*! @brief Set the EN field to a new value. */
|
||||
#define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field OPE[1] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - CMPO is not available on the associated CMPO output pin. If the
|
||||
* comparator does not own the pin, this field has no effect.
|
||||
* - 1 - CMPO is available on the associated CMPO output pin. The comparator
|
||||
* output (CMPO) is driven out on the associated CMPO output pin if the
|
||||
* comparator owns the pin. If the comparator does not own the field, this bit has no
|
||||
* effect.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_OPE (1U) /*!< Bit position for CMP_CR1_OPE. */
|
||||
#define BM_CMP_CR1_OPE (0x02U) /*!< Bit mask for CMP_CR1_OPE. */
|
||||
#define BS_CMP_CR1_OPE (1U) /*!< Bit field size in bits for CMP_CR1_OPE. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_OPE field. */
|
||||
#define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_OPE. */
|
||||
#define BF_CMP_CR1_OPE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE)
|
||||
|
||||
/*! @brief Set the OPE field to a new value. */
|
||||
#define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field COS[2] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Set the filtered comparator output (CMPO) to equal COUT.
|
||||
* - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_COS (2U) /*!< Bit position for CMP_CR1_COS. */
|
||||
#define BM_CMP_CR1_COS (0x04U) /*!< Bit mask for CMP_CR1_COS. */
|
||||
#define BS_CMP_CR1_COS (1U) /*!< Bit field size in bits for CMP_CR1_COS. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_COS field. */
|
||||
#define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_COS. */
|
||||
#define BF_CMP_CR1_COS(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS)
|
||||
|
||||
/*! @brief Set the COS field to a new value. */
|
||||
#define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field INV[3] (RW)
|
||||
*
|
||||
* Allows selection of the polarity of the analog comparator function. It is
|
||||
* also driven to the COUT output, on both the device pin and as SCR[COUT], when
|
||||
* OPE=0.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Does not invert the comparator output.
|
||||
* - 1 - Inverts the comparator output.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_INV (3U) /*!< Bit position for CMP_CR1_INV. */
|
||||
#define BM_CMP_CR1_INV (0x08U) /*!< Bit mask for CMP_CR1_INV. */
|
||||
#define BS_CMP_CR1_INV (1U) /*!< Bit field size in bits for CMP_CR1_INV. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_INV field. */
|
||||
#define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_INV. */
|
||||
#define BF_CMP_CR1_INV(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV)
|
||||
|
||||
/*! @brief Set the INV field to a new value. */
|
||||
#define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field PMODE[4] (RW)
|
||||
*
|
||||
* See the electrical specifications table in the device Data Sheet for details.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
|
||||
* output propagation delay and lower current consumption.
|
||||
* - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
|
||||
* output propagation delay and higher current consumption.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_PMODE (4U) /*!< Bit position for CMP_CR1_PMODE. */
|
||||
#define BM_CMP_CR1_PMODE (0x10U) /*!< Bit mask for CMP_CR1_PMODE. */
|
||||
#define BS_CMP_CR1_PMODE (1U) /*!< Bit field size in bits for CMP_CR1_PMODE. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_PMODE field. */
|
||||
#define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_PMODE. */
|
||||
#define BF_CMP_CR1_PMODE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE)
|
||||
|
||||
/*! @brief Set the PMODE field to a new value. */
|
||||
#define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field TRIGM[5] (RW)
|
||||
*
|
||||
* CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
|
||||
* 1. In addition, the CMP should be enabled. If the DAC is to be used as a
|
||||
* reference to the CMP, it should also be enabled. CMP Trigger mode depends on an
|
||||
* external timer resource to periodically enable the CMP and 6-bit DAC in order to
|
||||
* generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed
|
||||
* in a standby state until an external timer resource trigger is received. See
|
||||
* the chip configuration for details about the external timer resource.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Trigger mode is disabled.
|
||||
* - 1 - Trigger mode is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_TRIGM (5U) /*!< Bit position for CMP_CR1_TRIGM. */
|
||||
#define BM_CMP_CR1_TRIGM (0x20U) /*!< Bit mask for CMP_CR1_TRIGM. */
|
||||
#define BS_CMP_CR1_TRIGM (1U) /*!< Bit field size in bits for CMP_CR1_TRIGM. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_TRIGM field. */
|
||||
#define BR_CMP_CR1_TRIGM(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_TRIGM. */
|
||||
#define BF_CMP_CR1_TRIGM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_TRIGM) & BM_CMP_CR1_TRIGM)
|
||||
|
||||
/*! @brief Set the TRIGM field to a new value. */
|
||||
#define BW_CMP_CR1_TRIGM(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field WE[6] (RW)
|
||||
*
|
||||
* At any given time, either SE or WE can be set. If a write to this register
|
||||
* attempts to set both, then SE is set and WE is cleared. However, avoid writing
|
||||
* 1s to both field locations because this "11" case is reserved and may change in
|
||||
* future implementations.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Windowing mode is not selected.
|
||||
* - 1 - Windowing mode is selected.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_WE (6U) /*!< Bit position for CMP_CR1_WE. */
|
||||
#define BM_CMP_CR1_WE (0x40U) /*!< Bit mask for CMP_CR1_WE. */
|
||||
#define BS_CMP_CR1_WE (1U) /*!< Bit field size in bits for CMP_CR1_WE. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_WE field. */
|
||||
#define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_WE. */
|
||||
#define BF_CMP_CR1_WE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE)
|
||||
|
||||
/*! @brief Set the WE field to a new value. */
|
||||
#define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_CR1, field SE[7] (RW)
|
||||
*
|
||||
* At any given time, either SE or WE can be set. If a write to this register
|
||||
* attempts to set both, then SE is set and WE is cleared. However, avoid writing
|
||||
* 1s to both field locations because this "11" case is reserved and may change in
|
||||
* future implementations.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Sampling mode is not selected.
|
||||
* - 1 - Sampling mode is selected.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_CR1_SE (7U) /*!< Bit position for CMP_CR1_SE. */
|
||||
#define BM_CMP_CR1_SE (0x80U) /*!< Bit mask for CMP_CR1_SE. */
|
||||
#define BS_CMP_CR1_SE (1U) /*!< Bit field size in bits for CMP_CR1_SE. */
|
||||
|
||||
/*! @brief Read current value of the CMP_CR1_SE field. */
|
||||
#define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_CR1_SE. */
|
||||
#define BF_CMP_CR1_SE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE)
|
||||
|
||||
/*! @brief Set the SE field to a new value. */
|
||||
#define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_CMP_FPR - CMP Filter Period Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_CMP_FPR - CMP Filter Period Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_cmp_fpr
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_cmp_fpr_bitfields
|
||||
{
|
||||
uint8_t FILT_PER : 8; /*!< [7:0] Filter Sample Period */
|
||||
} B;
|
||||
} hw_cmp_fpr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire CMP_FPR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_CMP_FPR_ADDR(x) ((x) + 0x2U)
|
||||
|
||||
#define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
|
||||
#define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U)
|
||||
#define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v))
|
||||
#define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v)))
|
||||
#define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
|
||||
#define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual CMP_FPR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_FPR, field FILT_PER[7:0] (RW)
|
||||
*
|
||||
* Specifies the sampling period, in bus clock cycles, of the comparator output
|
||||
* filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
|
||||
* programming and latency details appear in the Functional descriptionThe CMP
|
||||
* module can be used to compare two analog input voltages applied to INP and INM. .
|
||||
* This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
|
||||
* signal is used to determine the sampling period.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_FPR_FILT_PER (0U) /*!< Bit position for CMP_FPR_FILT_PER. */
|
||||
#define BM_CMP_FPR_FILT_PER (0xFFU) /*!< Bit mask for CMP_FPR_FILT_PER. */
|
||||
#define BS_CMP_FPR_FILT_PER (8U) /*!< Bit field size in bits for CMP_FPR_FILT_PER. */
|
||||
|
||||
/*! @brief Read current value of the CMP_FPR_FILT_PER field. */
|
||||
#define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield CMP_FPR_FILT_PER. */
|
||||
#define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER)
|
||||
|
||||
/*! @brief Set the FILT_PER field to a new value. */
|
||||
#define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_CMP_SCR - CMP Status and Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_CMP_SCR - CMP Status and Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_cmp_scr
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_cmp_scr_bitfields
|
||||
{
|
||||
uint8_t COUT : 1; /*!< [0] Analog Comparator Output */
|
||||
uint8_t CFF : 1; /*!< [1] Analog Comparator Flag Falling */
|
||||
uint8_t CFR : 1; /*!< [2] Analog Comparator Flag Rising */
|
||||
uint8_t IEF : 1; /*!< [3] Comparator Interrupt Enable Falling */
|
||||
uint8_t IER : 1; /*!< [4] Comparator Interrupt Enable Rising */
|
||||
uint8_t RESERVED0 : 1; /*!< [5] */
|
||||
uint8_t DMAEN : 1; /*!< [6] DMA Enable Control */
|
||||
uint8_t RESERVED1 : 1; /*!< [7] */
|
||||
} B;
|
||||
} hw_cmp_scr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire CMP_SCR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_CMP_SCR_ADDR(x) ((x) + 0x3U)
|
||||
|
||||
#define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
|
||||
#define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U)
|
||||
#define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v))
|
||||
#define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v)))
|
||||
#define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
|
||||
#define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual CMP_SCR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_SCR, field COUT[0] (RO)
|
||||
*
|
||||
* Returns the current value of the Analog Comparator output, when read. The
|
||||
* field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
|
||||
* is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_SCR_COUT (0U) /*!< Bit position for CMP_SCR_COUT. */
|
||||
#define BM_CMP_SCR_COUT (0x01U) /*!< Bit mask for CMP_SCR_COUT. */
|
||||
#define BS_CMP_SCR_COUT (1U) /*!< Bit field size in bits for CMP_SCR_COUT. */
|
||||
|
||||
/*! @brief Read current value of the CMP_SCR_COUT field. */
|
||||
#define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_SCR, field CFF[1] (W1C)
|
||||
*
|
||||
* Detects a falling-edge on COUT, when set, during normal operation. CFF is
|
||||
* cleared by writing 1 to it. During Stop modes, CFF is level sensitive .
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Falling-edge on COUT has not been detected.
|
||||
* - 1 - Falling-edge on COUT has occurred.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_SCR_CFF (1U) /*!< Bit position for CMP_SCR_CFF. */
|
||||
#define BM_CMP_SCR_CFF (0x02U) /*!< Bit mask for CMP_SCR_CFF. */
|
||||
#define BS_CMP_SCR_CFF (1U) /*!< Bit field size in bits for CMP_SCR_CFF. */
|
||||
|
||||
/*! @brief Read current value of the CMP_SCR_CFF field. */
|
||||
#define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_SCR_CFF. */
|
||||
#define BF_CMP_SCR_CFF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF)
|
||||
|
||||
/*! @brief Set the CFF field to a new value. */
|
||||
#define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_SCR, field CFR[2] (W1C)
|
||||
*
|
||||
* Detects a rising-edge on COUT, when set, during normal operation. CFR is
|
||||
* cleared by writing 1 to it. During Stop modes, CFR is level sensitive .
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Rising-edge on COUT has not been detected.
|
||||
* - 1 - Rising-edge on COUT has occurred.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_SCR_CFR (2U) /*!< Bit position for CMP_SCR_CFR. */
|
||||
#define BM_CMP_SCR_CFR (0x04U) /*!< Bit mask for CMP_SCR_CFR. */
|
||||
#define BS_CMP_SCR_CFR (1U) /*!< Bit field size in bits for CMP_SCR_CFR. */
|
||||
|
||||
/*! @brief Read current value of the CMP_SCR_CFR field. */
|
||||
#define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_SCR_CFR. */
|
||||
#define BF_CMP_SCR_CFR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR)
|
||||
|
||||
/*! @brief Set the CFR field to a new value. */
|
||||
#define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_SCR, field IEF[3] (RW)
|
||||
*
|
||||
* Enables the CFF interrupt from the CMP. When this field is set, an interrupt
|
||||
* will be asserted when CFF is set.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Interrupt is disabled.
|
||||
* - 1 - Interrupt is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_SCR_IEF (3U) /*!< Bit position for CMP_SCR_IEF. */
|
||||
#define BM_CMP_SCR_IEF (0x08U) /*!< Bit mask for CMP_SCR_IEF. */
|
||||
#define BS_CMP_SCR_IEF (1U) /*!< Bit field size in bits for CMP_SCR_IEF. */
|
||||
|
||||
/*! @brief Read current value of the CMP_SCR_IEF field. */
|
||||
#define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_SCR_IEF. */
|
||||
#define BF_CMP_SCR_IEF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF)
|
||||
|
||||
/*! @brief Set the IEF field to a new value. */
|
||||
#define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_SCR, field IER[4] (RW)
|
||||
*
|
||||
* Enables the CFR interrupt from the CMP. When this field is set, an interrupt
|
||||
* will be asserted when CFR is set.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Interrupt is disabled.
|
||||
* - 1 - Interrupt is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_SCR_IER (4U) /*!< Bit position for CMP_SCR_IER. */
|
||||
#define BM_CMP_SCR_IER (0x10U) /*!< Bit mask for CMP_SCR_IER. */
|
||||
#define BS_CMP_SCR_IER (1U) /*!< Bit field size in bits for CMP_SCR_IER. */
|
||||
|
||||
/*! @brief Read current value of the CMP_SCR_IER field. */
|
||||
#define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_SCR_IER. */
|
||||
#define BF_CMP_SCR_IER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER)
|
||||
|
||||
/*! @brief Set the IER field to a new value. */
|
||||
#define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_SCR, field DMAEN[6] (RW)
|
||||
*
|
||||
* Enables the DMA transfer triggered from the CMP module. When this field is
|
||||
* set, a DMA request is asserted when CFR or CFF is set.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - DMA is disabled.
|
||||
* - 1 - DMA is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_SCR_DMAEN (6U) /*!< Bit position for CMP_SCR_DMAEN. */
|
||||
#define BM_CMP_SCR_DMAEN (0x40U) /*!< Bit mask for CMP_SCR_DMAEN. */
|
||||
#define BS_CMP_SCR_DMAEN (1U) /*!< Bit field size in bits for CMP_SCR_DMAEN. */
|
||||
|
||||
/*! @brief Read current value of the CMP_SCR_DMAEN field. */
|
||||
#define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_SCR_DMAEN. */
|
||||
#define BF_CMP_SCR_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN)
|
||||
|
||||
/*! @brief Set the DMAEN field to a new value. */
|
||||
#define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_CMP_DACCR - DAC Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_CMP_DACCR - DAC Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_cmp_daccr
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_cmp_daccr_bitfields
|
||||
{
|
||||
uint8_t VOSEL : 6; /*!< [5:0] DAC Output Voltage Select */
|
||||
uint8_t VRSEL : 1; /*!< [6] Supply Voltage Reference Source Select */
|
||||
uint8_t DACEN : 1; /*!< [7] DAC Enable */
|
||||
} B;
|
||||
} hw_cmp_daccr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire CMP_DACCR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_CMP_DACCR_ADDR(x) ((x) + 0x4U)
|
||||
|
||||
#define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
|
||||
#define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U)
|
||||
#define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v))
|
||||
#define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v)))
|
||||
#define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
|
||||
#define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual CMP_DACCR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_DACCR, field VOSEL[5:0] (RW)
|
||||
*
|
||||
* Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
|
||||
* (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_DACCR_VOSEL (0U) /*!< Bit position for CMP_DACCR_VOSEL. */
|
||||
#define BM_CMP_DACCR_VOSEL (0x3FU) /*!< Bit mask for CMP_DACCR_VOSEL. */
|
||||
#define BS_CMP_DACCR_VOSEL (6U) /*!< Bit field size in bits for CMP_DACCR_VOSEL. */
|
||||
|
||||
/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
|
||||
#define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
|
||||
|
||||
/*! @brief Format value for bitfield CMP_DACCR_VOSEL. */
|
||||
#define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL)
|
||||
|
||||
/*! @brief Set the VOSEL field to a new value. */
|
||||
#define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_DACCR, field VRSEL[6] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Vin1 is selected as resistor ladder network supply reference.
|
||||
* - 1 - Vin2 is selected as resistor ladder network supply reference.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */
|
||||
#define BM_CMP_DACCR_VRSEL (0x40U) /*!< Bit mask for CMP_DACCR_VRSEL. */
|
||||
#define BS_CMP_DACCR_VRSEL (1U) /*!< Bit field size in bits for CMP_DACCR_VRSEL. */
|
||||
|
||||
/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
|
||||
#define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_DACCR_VRSEL. */
|
||||
#define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL)
|
||||
|
||||
/*! @brief Set the VRSEL field to a new value. */
|
||||
#define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_DACCR, field DACEN[7] (RW)
|
||||
*
|
||||
* Enables the DAC. When the DAC is disabled, it is powered down to conserve
|
||||
* power.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - DAC is disabled.
|
||||
* - 1 - DAC is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_DACCR_DACEN (7U) /*!< Bit position for CMP_DACCR_DACEN. */
|
||||
#define BM_CMP_DACCR_DACEN (0x80U) /*!< Bit mask for CMP_DACCR_DACEN. */
|
||||
#define BS_CMP_DACCR_DACEN (1U) /*!< Bit field size in bits for CMP_DACCR_DACEN. */
|
||||
|
||||
/*! @brief Read current value of the CMP_DACCR_DACEN field. */
|
||||
#define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
|
||||
|
||||
/*! @brief Format value for bitfield CMP_DACCR_DACEN. */
|
||||
#define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN)
|
||||
|
||||
/*! @brief Set the DACEN field to a new value. */
|
||||
#define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_CMP_MUXCR - MUX Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_CMP_MUXCR - MUX Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_cmp_muxcr
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_cmp_muxcr_bitfields
|
||||
{
|
||||
uint8_t MSEL : 3; /*!< [2:0] Minus Input Mux Control */
|
||||
uint8_t PSEL : 3; /*!< [5:3] Plus Input Mux Control */
|
||||
uint8_t RESERVED0 : 2; /*!< [7:6] Bit can be programmed to zero only
|
||||
* . */
|
||||
} B;
|
||||
} hw_cmp_muxcr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire CMP_MUXCR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_CMP_MUXCR_ADDR(x) ((x) + 0x5U)
|
||||
|
||||
#define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
|
||||
#define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U)
|
||||
#define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v))
|
||||
#define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v)))
|
||||
#define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
|
||||
#define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual CMP_MUXCR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_MUXCR, field MSEL[2:0] (RW)
|
||||
*
|
||||
* Determines which input is selected for the minus input of the comparator. For
|
||||
* INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
|
||||
* operation selects the same input for both muxes, the comparator automatically
|
||||
* shuts down to prevent itself from becoming a noise generator.
|
||||
*
|
||||
* Values:
|
||||
* - 000 - IN0
|
||||
* - 001 - IN1
|
||||
* - 010 - IN2
|
||||
* - 011 - IN3
|
||||
* - 100 - IN4
|
||||
* - 101 - IN5
|
||||
* - 110 - IN6
|
||||
* - 111 - IN7
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_MUXCR_MSEL (0U) /*!< Bit position for CMP_MUXCR_MSEL. */
|
||||
#define BM_CMP_MUXCR_MSEL (0x07U) /*!< Bit mask for CMP_MUXCR_MSEL. */
|
||||
#define BS_CMP_MUXCR_MSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_MSEL. */
|
||||
|
||||
/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
|
||||
#define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
|
||||
|
||||
/*! @brief Format value for bitfield CMP_MUXCR_MSEL. */
|
||||
#define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL)
|
||||
|
||||
/*! @brief Set the MSEL field to a new value. */
|
||||
#define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register CMP_MUXCR, field PSEL[5:3] (RW)
|
||||
*
|
||||
* Determines which input is selected for the plus input of the comparator. For
|
||||
* INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
|
||||
* operation selects the same input for both muxes, the comparator automatically
|
||||
* shuts down to prevent itself from becoming a noise generator.
|
||||
*
|
||||
* Values:
|
||||
* - 000 - IN0
|
||||
* - 001 - IN1
|
||||
* - 010 - IN2
|
||||
* - 011 - IN3
|
||||
* - 100 - IN4
|
||||
* - 101 - IN5
|
||||
* - 110 - IN6
|
||||
* - 111 - IN7
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_CMP_MUXCR_PSEL (3U) /*!< Bit position for CMP_MUXCR_PSEL. */
|
||||
#define BM_CMP_MUXCR_PSEL (0x38U) /*!< Bit mask for CMP_MUXCR_PSEL. */
|
||||
#define BS_CMP_MUXCR_PSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_PSEL. */
|
||||
|
||||
/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
|
||||
#define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
|
||||
|
||||
/*! @brief Format value for bitfield CMP_MUXCR_PSEL. */
|
||||
#define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL)
|
||||
|
||||
/*! @brief Set the PSEL field to a new value. */
|
||||
#define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_cmp_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All CMP module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_cmp
|
||||
{
|
||||
__IO hw_cmp_cr0_t CR0; /*!< [0x0] CMP Control Register 0 */
|
||||
__IO hw_cmp_cr1_t CR1; /*!< [0x1] CMP Control Register 1 */
|
||||
__IO hw_cmp_fpr_t FPR; /*!< [0x2] CMP Filter Period Register */
|
||||
__IO hw_cmp_scr_t SCR; /*!< [0x3] CMP Status and Control Register */
|
||||
__IO hw_cmp_daccr_t DACCR; /*!< [0x4] DAC Control Register */
|
||||
__IO hw_cmp_muxcr_t MUXCR; /*!< [0x5] MUX Control Register */
|
||||
} hw_cmp_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all CMP registers. */
|
||||
/*! @param x CMP module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */
|
||||
#define HW_CMP(x) (*(hw_cmp_t *)(x))
|
||||
|
||||
#endif /* __HW_CMP_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,824 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_DAC_REGISTERS_H__
|
||||
#define __HW_DAC_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 DAC
|
||||
*
|
||||
* 12-Bit Digital-to-Analog Converter
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_DAC_DATnL - DAC Data Low Register
|
||||
* - HW_DAC_DATnH - DAC Data High Register
|
||||
* - HW_DAC_SR - DAC Status Register
|
||||
* - HW_DAC_C0 - DAC Control Register
|
||||
* - HW_DAC_C1 - DAC Control Register 1
|
||||
* - HW_DAC_C2 - DAC Control Register 2
|
||||
*
|
||||
* - hw_dac_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_DAC_INSTANCE_COUNT (1U) /*!< Number of instances of the DAC module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_DAC_DATnL - DAC Data Low Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_DAC_DATnL - DAC Data Low Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_dac_datnl
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dac_datnl_bitfields
|
||||
{
|
||||
uint8_t DATA0 : 8; /*!< [7:0] */
|
||||
} B;
|
||||
} hw_dac_datnl_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DAC_DATnL register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_DAC_DATnL_COUNT (16U)
|
||||
|
||||
#define HW_DAC_DATnL_ADDR(x, n) ((x) + 0x0U + (0x2U * (n)))
|
||||
|
||||
#define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
|
||||
#define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
|
||||
#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
|
||||
#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
|
||||
#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
|
||||
#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DAC_DATnL bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_DATnL, field DATA0[7:0] (RW)
|
||||
*
|
||||
* When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
|
||||
* based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
|
||||
* DAC buffer is enabled, DATA is mapped to the 16-word buffer.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_DATnL_DATA0 (0U) /*!< Bit position for DAC_DATnL_DATA0. */
|
||||
#define BM_DAC_DATnL_DATA0 (0xFFU) /*!< Bit mask for DAC_DATnL_DATA0. */
|
||||
#define BS_DAC_DATnL_DATA0 (8U) /*!< Bit field size in bits for DAC_DATnL_DATA0. */
|
||||
|
||||
/*! @brief Read current value of the DAC_DATnL_DATA0 field. */
|
||||
#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
|
||||
|
||||
/*! @brief Format value for bitfield DAC_DATnL_DATA0. */
|
||||
#define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0)
|
||||
|
||||
/*! @brief Set the DATA0 field to a new value. */
|
||||
#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
|
||||
/*@}*/
|
||||
/*******************************************************************************
|
||||
* HW_DAC_DATnH - DAC Data High Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_DAC_DATnH - DAC Data High Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_dac_datnh
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dac_datnh_bitfields
|
||||
{
|
||||
uint8_t DATA1 : 4; /*!< [3:0] */
|
||||
uint8_t RESERVED0 : 4; /*!< [7:4] */
|
||||
} B;
|
||||
} hw_dac_datnh_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DAC_DATnH register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_DAC_DATnH_COUNT (16U)
|
||||
|
||||
#define HW_DAC_DATnH_ADDR(x, n) ((x) + 0x1U + (0x2U * (n)))
|
||||
|
||||
#define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
|
||||
#define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
|
||||
#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
|
||||
#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
|
||||
#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
|
||||
#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DAC_DATnH bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_DATnH, field DATA1[3:0] (RW)
|
||||
*
|
||||
* When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
|
||||
* based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
|
||||
* DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_DATnH_DATA1 (0U) /*!< Bit position for DAC_DATnH_DATA1. */
|
||||
#define BM_DAC_DATnH_DATA1 (0x0FU) /*!< Bit mask for DAC_DATnH_DATA1. */
|
||||
#define BS_DAC_DATnH_DATA1 (4U) /*!< Bit field size in bits for DAC_DATnH_DATA1. */
|
||||
|
||||
/*! @brief Read current value of the DAC_DATnH_DATA1 field. */
|
||||
#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
|
||||
|
||||
/*! @brief Format value for bitfield DAC_DATnH_DATA1. */
|
||||
#define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1)
|
||||
|
||||
/*! @brief Set the DATA1 field to a new value. */
|
||||
#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_DAC_SR - DAC Status Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_DAC_SR - DAC Status Register (RW)
|
||||
*
|
||||
* Reset value: 0x02U
|
||||
*
|
||||
* If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
|
||||
* request is done. Writing 0 to a field clears it whereas writing 1 has no
|
||||
* effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
|
||||
* The flags are set only when the data buffer status is changed.
|
||||
*/
|
||||
typedef union _hw_dac_sr
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dac_sr_bitfields
|
||||
{
|
||||
uint8_t DACBFRPBF : 1; /*!< [0] DAC Buffer Read Pointer Bottom
|
||||
* Position Flag */
|
||||
uint8_t DACBFRPTF : 1; /*!< [1] DAC Buffer Read Pointer Top Position
|
||||
* Flag */
|
||||
uint8_t DACBFWMF : 1; /*!< [2] DAC Buffer Watermark Flag */
|
||||
uint8_t RESERVED0 : 5; /*!< [7:3] */
|
||||
} B;
|
||||
} hw_dac_sr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DAC_SR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_DAC_SR_ADDR(x) ((x) + 0x20U)
|
||||
|
||||
#define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
|
||||
#define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
|
||||
#define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
|
||||
#define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
|
||||
#define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
|
||||
#define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DAC_SR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_SR, field DACBFRPBF[0] (RW)
|
||||
*
|
||||
* In FIFO mode, it is FIFO FULL status bit. It means FIFO read pointer equals
|
||||
* Write Pointer because of Write Pointer increase. If this bit is set, any write
|
||||
* to FIFO from either DMA or CPU is ignored by DAC. It is cleared if there is
|
||||
* any DAC trigger making the DAC read pointer increase. Write to this bit is
|
||||
* ignored in FIFO mode.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
|
||||
* - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_SR_DACBFRPBF (0U) /*!< Bit position for DAC_SR_DACBFRPBF. */
|
||||
#define BM_DAC_SR_DACBFRPBF (0x01U) /*!< Bit mask for DAC_SR_DACBFRPBF. */
|
||||
#define BS_DAC_SR_DACBFRPBF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */
|
||||
|
||||
/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
|
||||
#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */
|
||||
#define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF)
|
||||
|
||||
/*! @brief Set the DACBFRPBF field to a new value. */
|
||||
#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_SR, field DACBFRPTF[1] (RW)
|
||||
*
|
||||
* In FIFO mode, it is FIFO nearly empty flag. It is set when only one data
|
||||
* remains in FIFO. Any DAC trigger does not increase the Read Pointer if this bit is
|
||||
* set to avoid any possible glitch or abrupt change at DAC output. It is
|
||||
* cleared automatically if FIFO is not empty.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC buffer read pointer is not zero.
|
||||
* - 1 - The DAC buffer read pointer is zero.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_SR_DACBFRPTF (1U) /*!< Bit position for DAC_SR_DACBFRPTF. */
|
||||
#define BM_DAC_SR_DACBFRPTF (0x02U) /*!< Bit mask for DAC_SR_DACBFRPTF. */
|
||||
#define BS_DAC_SR_DACBFRPTF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */
|
||||
|
||||
/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
|
||||
#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */
|
||||
#define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF)
|
||||
|
||||
/*! @brief Set the DACBFRPTF field to a new value. */
|
||||
#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_SR, field DACBFWMF[2] (RW)
|
||||
*
|
||||
* This bit is set if the remaining FIFO data is less than the watermark
|
||||
* setting. It is cleared automatically by writing data into FIFO by DMA or CPU. Write
|
||||
* to this bit is ignored in FIFO mode.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC buffer read pointer has not reached the watermark level.
|
||||
* - 1 - The DAC buffer read pointer has reached the watermark level.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_SR_DACBFWMF (2U) /*!< Bit position for DAC_SR_DACBFWMF. */
|
||||
#define BM_DAC_SR_DACBFWMF (0x04U) /*!< Bit mask for DAC_SR_DACBFWMF. */
|
||||
#define BS_DAC_SR_DACBFWMF (1U) /*!< Bit field size in bits for DAC_SR_DACBFWMF. */
|
||||
|
||||
/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
|
||||
#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_SR_DACBFWMF. */
|
||||
#define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF)
|
||||
|
||||
/*! @brief Set the DACBFWMF field to a new value. */
|
||||
#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_DAC_C0 - DAC Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_DAC_C0 - DAC Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_dac_c0
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dac_c0_bitfields
|
||||
{
|
||||
uint8_t DACBBIEN : 1; /*!< [0] DAC Buffer Read Pointer Bottom Flag
|
||||
* Interrupt Enable */
|
||||
uint8_t DACBTIEN : 1; /*!< [1] DAC Buffer Read Pointer Top Flag
|
||||
* Interrupt Enable */
|
||||
uint8_t DACBWIEN : 1; /*!< [2] DAC Buffer Watermark Interrupt Enable
|
||||
* */
|
||||
uint8_t LPEN : 1; /*!< [3] DAC Low Power Control */
|
||||
uint8_t DACSWTRG : 1; /*!< [4] DAC Software Trigger */
|
||||
uint8_t DACTRGSEL : 1; /*!< [5] DAC Trigger Select */
|
||||
uint8_t DACRFS : 1; /*!< [6] DAC Reference Select */
|
||||
uint8_t DACEN : 1; /*!< [7] DAC Enable */
|
||||
} B;
|
||||
} hw_dac_c0_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DAC_C0 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_DAC_C0_ADDR(x) ((x) + 0x21U)
|
||||
|
||||
#define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
|
||||
#define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
|
||||
#define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
|
||||
#define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
|
||||
#define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
|
||||
#define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DAC_C0 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field DACBBIEN[0] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
|
||||
* - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_DACBBIEN (0U) /*!< Bit position for DAC_C0_DACBBIEN. */
|
||||
#define BM_DAC_C0_DACBBIEN (0x01U) /*!< Bit mask for DAC_C0_DACBBIEN. */
|
||||
#define BS_DAC_C0_DACBBIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBBIEN. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
|
||||
#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_DACBBIEN. */
|
||||
#define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN)
|
||||
|
||||
/*! @brief Set the DACBBIEN field to a new value. */
|
||||
#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field DACBTIEN[1] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC buffer read pointer top flag interrupt is disabled.
|
||||
* - 1 - The DAC buffer read pointer top flag interrupt is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_DACBTIEN (1U) /*!< Bit position for DAC_C0_DACBTIEN. */
|
||||
#define BM_DAC_C0_DACBTIEN (0x02U) /*!< Bit mask for DAC_C0_DACBTIEN. */
|
||||
#define BS_DAC_C0_DACBTIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBTIEN. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
|
||||
#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_DACBTIEN. */
|
||||
#define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN)
|
||||
|
||||
/*! @brief Set the DACBTIEN field to a new value. */
|
||||
#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field DACBWIEN[2] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC buffer watermark interrupt is disabled.
|
||||
* - 1 - The DAC buffer watermark interrupt is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_DACBWIEN (2U) /*!< Bit position for DAC_C0_DACBWIEN. */
|
||||
#define BM_DAC_C0_DACBWIEN (0x04U) /*!< Bit mask for DAC_C0_DACBWIEN. */
|
||||
#define BS_DAC_C0_DACBWIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBWIEN. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
|
||||
#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_DACBWIEN. */
|
||||
#define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN)
|
||||
|
||||
/*! @brief Set the DACBWIEN field to a new value. */
|
||||
#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field LPEN[3] (RW)
|
||||
*
|
||||
* See the 12-bit DAC electrical characteristics of the device data sheet for
|
||||
* details on the impact of the modes below.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - High-Power mode
|
||||
* - 1 - Low-Power mode
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_LPEN (3U) /*!< Bit position for DAC_C0_LPEN. */
|
||||
#define BM_DAC_C0_LPEN (0x08U) /*!< Bit mask for DAC_C0_LPEN. */
|
||||
#define BS_DAC_C0_LPEN (1U) /*!< Bit field size in bits for DAC_C0_LPEN. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C0_LPEN field. */
|
||||
#define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_LPEN. */
|
||||
#define BF_DAC_C0_LPEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN)
|
||||
|
||||
/*! @brief Set the LPEN field to a new value. */
|
||||
#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field DACSWTRG[4] (WORZ)
|
||||
*
|
||||
* Active high. This is a write-only field, which always reads 0. If DAC
|
||||
* software trigger is selected and buffer is enabled, writing 1 to this field will
|
||||
* advance the buffer read pointer once.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC soft trigger is not valid.
|
||||
* - 1 - The DAC soft trigger is valid.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_DACSWTRG (4U) /*!< Bit position for DAC_C0_DACSWTRG. */
|
||||
#define BM_DAC_C0_DACSWTRG (0x10U) /*!< Bit mask for DAC_C0_DACSWTRG. */
|
||||
#define BS_DAC_C0_DACSWTRG (1U) /*!< Bit field size in bits for DAC_C0_DACSWTRG. */
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_DACSWTRG. */
|
||||
#define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG)
|
||||
|
||||
/*! @brief Set the DACSWTRG field to a new value. */
|
||||
#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field DACTRGSEL[5] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC hardware trigger is selected.
|
||||
* - 1 - The DAC software trigger is selected.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_DACTRGSEL (5U) /*!< Bit position for DAC_C0_DACTRGSEL. */
|
||||
#define BM_DAC_C0_DACTRGSEL (0x20U) /*!< Bit mask for DAC_C0_DACTRGSEL. */
|
||||
#define BS_DAC_C0_DACTRGSEL (1U) /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
|
||||
#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */
|
||||
#define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL)
|
||||
|
||||
/*! @brief Set the DACTRGSEL field to a new value. */
|
||||
#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field DACRFS[6] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC selects DACREF_1 as the reference voltage.
|
||||
* - 1 - The DAC selects DACREF_2 as the reference voltage.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_DACRFS (6U) /*!< Bit position for DAC_C0_DACRFS. */
|
||||
#define BM_DAC_C0_DACRFS (0x40U) /*!< Bit mask for DAC_C0_DACRFS. */
|
||||
#define BS_DAC_C0_DACRFS (1U) /*!< Bit field size in bits for DAC_C0_DACRFS. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C0_DACRFS field. */
|
||||
#define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_DACRFS. */
|
||||
#define BF_DAC_C0_DACRFS(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS)
|
||||
|
||||
/*! @brief Set the DACRFS field to a new value. */
|
||||
#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C0, field DACEN[7] (RW)
|
||||
*
|
||||
* Starts the Programmable Reference Generator operation.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The DAC system is disabled.
|
||||
* - 1 - The DAC system is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C0_DACEN (7U) /*!< Bit position for DAC_C0_DACEN. */
|
||||
#define BM_DAC_C0_DACEN (0x80U) /*!< Bit mask for DAC_C0_DACEN. */
|
||||
#define BS_DAC_C0_DACEN (1U) /*!< Bit field size in bits for DAC_C0_DACEN. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C0_DACEN field. */
|
||||
#define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C0_DACEN. */
|
||||
#define BF_DAC_C0_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN)
|
||||
|
||||
/*! @brief Set the DACEN field to a new value. */
|
||||
#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_DAC_C1 - DAC Control Register 1
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_DAC_C1 - DAC Control Register 1 (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*/
|
||||
typedef union _hw_dac_c1
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dac_c1_bitfields
|
||||
{
|
||||
uint8_t DACBFEN : 1; /*!< [0] DAC Buffer Enable */
|
||||
uint8_t DACBFMD : 2; /*!< [2:1] DAC Buffer Work Mode Select */
|
||||
uint8_t DACBFWM : 2; /*!< [4:3] DAC Buffer Watermark Select */
|
||||
uint8_t RESERVED0 : 2; /*!< [6:5] */
|
||||
uint8_t DMAEN : 1; /*!< [7] DMA Enable Select */
|
||||
} B;
|
||||
} hw_dac_c1_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DAC_C1 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_DAC_C1_ADDR(x) ((x) + 0x22U)
|
||||
|
||||
#define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
|
||||
#define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
|
||||
#define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
|
||||
#define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
|
||||
#define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
|
||||
#define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DAC_C1 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C1, field DACBFEN[0] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Buffer read pointer is disabled. The converted data is always the first
|
||||
* word of the buffer.
|
||||
* - 1 - Buffer read pointer is enabled. The converted data is the word that the
|
||||
* read pointer points to. It means converted data can be from any word of
|
||||
* the buffer.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C1_DACBFEN (0U) /*!< Bit position for DAC_C1_DACBFEN. */
|
||||
#define BM_DAC_C1_DACBFEN (0x01U) /*!< Bit mask for DAC_C1_DACBFEN. */
|
||||
#define BS_DAC_C1_DACBFEN (1U) /*!< Bit field size in bits for DAC_C1_DACBFEN. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C1_DACBFEN field. */
|
||||
#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C1_DACBFEN. */
|
||||
#define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN)
|
||||
|
||||
/*! @brief Set the DACBFEN field to a new value. */
|
||||
#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C1, field DACBFMD[2:1] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Normal mode
|
||||
* - 01 - Swing mode
|
||||
* - 10 - One-Time Scan mode
|
||||
* - 11 - FIFO mode
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C1_DACBFMD (1U) /*!< Bit position for DAC_C1_DACBFMD. */
|
||||
#define BM_DAC_C1_DACBFMD (0x06U) /*!< Bit mask for DAC_C1_DACBFMD. */
|
||||
#define BS_DAC_C1_DACBFMD (2U) /*!< Bit field size in bits for DAC_C1_DACBFMD. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C1_DACBFMD field. */
|
||||
#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C1_DACBFMD. */
|
||||
#define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD)
|
||||
|
||||
/*! @brief Set the DACBFMD field to a new value. */
|
||||
#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C1, field DACBFWM[4:3] (RW)
|
||||
*
|
||||
* In normal mode it controls when SR[DACBFWMF] is set. When the DAC buffer read
|
||||
* pointer reaches the word defined by this field, which is 1-4 words away from
|
||||
* the upper limit (DACBUP), SR[DACBFWMF] will be set. This allows user
|
||||
* configuration of the watermark interrupt. In FIFO mode, it is FIFO watermark select
|
||||
* field.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining
|
||||
* in FIFO will set watermark status bit.
|
||||
* - 01 - In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data
|
||||
* remaining in FIFO will set watermark status bit.
|
||||
* - 10 - In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data
|
||||
* remaining in FIFO will set watermark status bit.
|
||||
* - 11 - In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data
|
||||
* remaining in FIFO will set watermark status bit.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C1_DACBFWM (3U) /*!< Bit position for DAC_C1_DACBFWM. */
|
||||
#define BM_DAC_C1_DACBFWM (0x18U) /*!< Bit mask for DAC_C1_DACBFWM. */
|
||||
#define BS_DAC_C1_DACBFWM (2U) /*!< Bit field size in bits for DAC_C1_DACBFWM. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C1_DACBFWM field. */
|
||||
#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C1_DACBFWM. */
|
||||
#define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM)
|
||||
|
||||
/*! @brief Set the DACBFWM field to a new value. */
|
||||
#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C1, field DMAEN[7] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - DMA is disabled.
|
||||
* - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
|
||||
* by original interrupts. The interrupts will not be presented on this
|
||||
* module at the same time.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C1_DMAEN (7U) /*!< Bit position for DAC_C1_DMAEN. */
|
||||
#define BM_DAC_C1_DMAEN (0x80U) /*!< Bit mask for DAC_C1_DMAEN. */
|
||||
#define BS_DAC_C1_DMAEN (1U) /*!< Bit field size in bits for DAC_C1_DMAEN. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C1_DMAEN field. */
|
||||
#define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C1_DMAEN. */
|
||||
#define BF_DAC_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN)
|
||||
|
||||
/*! @brief Set the DMAEN field to a new value. */
|
||||
#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_DAC_C2 - DAC Control Register 2
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_DAC_C2 - DAC Control Register 2 (RW)
|
||||
*
|
||||
* Reset value: 0x0FU
|
||||
*/
|
||||
typedef union _hw_dac_c2
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dac_c2_bitfields
|
||||
{
|
||||
uint8_t DACBFUP : 4; /*!< [3:0] DAC Buffer Upper Limit */
|
||||
uint8_t DACBFRP : 4; /*!< [7:4] DAC Buffer Read Pointer */
|
||||
} B;
|
||||
} hw_dac_c2_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DAC_C2 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_DAC_C2_ADDR(x) ((x) + 0x23U)
|
||||
|
||||
#define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
|
||||
#define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
|
||||
#define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
|
||||
#define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
|
||||
#define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
|
||||
#define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DAC_C2 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C2, field DACBFUP[3:0] (RW)
|
||||
*
|
||||
* In normal mode it selects the upper limit of the DAC buffer. The buffer read
|
||||
* pointer cannot exceed it. In FIFO mode it is the FIFO write pointer. User
|
||||
* cannot set Buffer Up limit in FIFO mode. In Normal mode its reset value is MAX.
|
||||
* When IP is configured to FIFO mode, this register becomes Write_Pointer, and its
|
||||
* value is initially set to equal READ_POINTER automatically, and the FIFO
|
||||
* status is empty. It is writable and user can configure it to the same address to
|
||||
* reset FIFO as empty.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C2_DACBFUP (0U) /*!< Bit position for DAC_C2_DACBFUP. */
|
||||
#define BM_DAC_C2_DACBFUP (0x0FU) /*!< Bit mask for DAC_C2_DACBFUP. */
|
||||
#define BS_DAC_C2_DACBFUP (4U) /*!< Bit field size in bits for DAC_C2_DACBFUP. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C2_DACBFUP field. */
|
||||
#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C2_DACBFUP. */
|
||||
#define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP)
|
||||
|
||||
/*! @brief Set the DACBFUP field to a new value. */
|
||||
#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DAC_C2, field DACBFRP[7:4] (RW)
|
||||
*
|
||||
* In normal mode it keeps the current value of the buffer read pointer. FIFO
|
||||
* mode, it is the FIFO read pointer. It is writable in FIFO mode. User can
|
||||
* configure it to same address to reset FIFO as empty.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DAC_C2_DACBFRP (4U) /*!< Bit position for DAC_C2_DACBFRP. */
|
||||
#define BM_DAC_C2_DACBFRP (0xF0U) /*!< Bit mask for DAC_C2_DACBFRP. */
|
||||
#define BS_DAC_C2_DACBFRP (4U) /*!< Bit field size in bits for DAC_C2_DACBFRP. */
|
||||
|
||||
/*! @brief Read current value of the DAC_C2_DACBFRP field. */
|
||||
#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
|
||||
|
||||
/*! @brief Format value for bitfield DAC_C2_DACBFRP. */
|
||||
#define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP)
|
||||
|
||||
/*! @brief Set the DACBFRP field to a new value. */
|
||||
#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_dac_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All DAC module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_dac
|
||||
{
|
||||
struct {
|
||||
__IO hw_dac_datnl_t DATnL; /*!< [0x0] DAC Data Low Register */
|
||||
__IO hw_dac_datnh_t DATnH; /*!< [0x1] DAC Data High Register */
|
||||
} DAT[16];
|
||||
__IO hw_dac_sr_t SR; /*!< [0x20] DAC Status Register */
|
||||
__IO hw_dac_c0_t C0; /*!< [0x21] DAC Control Register */
|
||||
__IO hw_dac_c1_t C1; /*!< [0x22] DAC Control Register 1 */
|
||||
__IO hw_dac_c2_t C2; /*!< [0x23] DAC Control Register 2 */
|
||||
} hw_dac_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all DAC registers. */
|
||||
/*! @param x DAC module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_DAC(DAC0_BASE)</code>. */
|
||||
#define HW_DAC(x) (*(hw_dac_t *)(x))
|
||||
|
||||
#endif /* __HW_DAC_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_DMAMUX_REGISTERS_H__
|
||||
#define __HW_DMAMUX_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 DMAMUX
|
||||
*
|
||||
* DMA channel multiplexor
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_DMAMUX_CHCFGn - Channel Configuration register
|
||||
*
|
||||
* - hw_dmamux_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_DMAMUX_CHCFGn - Channel Configuration register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* Each of the DMA channels can be independently enabled/disabled and associated
|
||||
* with one of the DMA slots (peripheral slots or always-on slots) in the
|
||||
* system. Setting multiple CHCFG registers with the same source value will result in
|
||||
* unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
|
||||
* Before changing the trigger or source settings, a DMA channel must be disabled
|
||||
* via CHCFGn[ENBL].
|
||||
*/
|
||||
typedef union _hw_dmamux_chcfgn
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dmamux_chcfgn_bitfields
|
||||
{
|
||||
uint8_t SOURCE : 6; /*!< [5:0] DMA Channel Source (Slot) */
|
||||
uint8_t TRIG : 1; /*!< [6] DMA Channel Trigger Enable */
|
||||
uint8_t ENBL : 1; /*!< [7] DMA Channel Enable */
|
||||
} B;
|
||||
} hw_dmamux_chcfgn_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DMAMUX_CHCFGn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_DMAMUX_CHCFGn_COUNT (4U)
|
||||
|
||||
#define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
|
||||
|
||||
#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
|
||||
#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
|
||||
#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
|
||||
#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
|
||||
#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
|
||||
#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DMAMUX_CHCFGn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
|
||||
*
|
||||
* Specifies which DMA source, if any, is routed to a particular DMA channel.
|
||||
* See the chip-specific DMAMUX information for details about the peripherals and
|
||||
* their slot numbers.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
|
||||
#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */
|
||||
#define BS_DMAMUX_CHCFGn_SOURCE (6U) /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */
|
||||
|
||||
/*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */
|
||||
#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
|
||||
|
||||
/*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */
|
||||
#define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE)
|
||||
|
||||
/*! @brief Set the SOURCE field to a new value. */
|
||||
#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
|
||||
*
|
||||
* Enables the periodic trigger capability for the triggered DMA channel.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
|
||||
* DMA Channel will simply route the specified source to the DMA channel.
|
||||
* (Normal mode)
|
||||
* - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
|
||||
* DMAMUX is in Periodic Trigger mode.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DMAMUX_CHCFGn_TRIG (6U) /*!< Bit position for DMAMUX_CHCFGn_TRIG. */
|
||||
#define BM_DMAMUX_CHCFGn_TRIG (0x40U) /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */
|
||||
#define BS_DMAMUX_CHCFGn_TRIG (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */
|
||||
|
||||
/*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */
|
||||
#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
|
||||
|
||||
/*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */
|
||||
#define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG)
|
||||
|
||||
/*! @brief Set the TRIG field to a new value. */
|
||||
#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
|
||||
*
|
||||
* Enables the DMA channel.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - DMA channel is disabled. This mode is primarily used during
|
||||
* configuration of the DMAMux. The DMA has separate channel enables/disables, which
|
||||
* should be used to disable or reconfigure a DMA channel.
|
||||
* - 1 - DMA channel is enabled
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_DMAMUX_CHCFGn_ENBL (7U) /*!< Bit position for DMAMUX_CHCFGn_ENBL. */
|
||||
#define BM_DMAMUX_CHCFGn_ENBL (0x80U) /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */
|
||||
#define BS_DMAMUX_CHCFGn_ENBL (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */
|
||||
|
||||
/*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */
|
||||
#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
|
||||
|
||||
/*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */
|
||||
#define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL)
|
||||
|
||||
/*! @brief Set the ENBL field to a new value. */
|
||||
#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_dmamux_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All DMAMUX module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_dmamux
|
||||
{
|
||||
__IO hw_dmamux_chcfgn_t CHCFGn[4]; /*!< [0x0] Channel Configuration register */
|
||||
} hw_dmamux_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all DMAMUX registers. */
|
||||
/*! @param x DMAMUX module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_DMAMUX(DMAMUX_BASE)</code>. */
|
||||
#define HW_DMAMUX(x) (*(hw_dmamux_t *)(x))
|
||||
|
||||
#endif /* __HW_DMAMUX_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
|
|
@ -0,0 +1,493 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_EWM_REGISTERS_H__
|
||||
#define __HW_EWM_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 EWM
|
||||
*
|
||||
* External Watchdog Monitor
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_EWM_CTRL - Control Register
|
||||
* - HW_EWM_SERV - Service Register
|
||||
* - HW_EWM_CMPL - Compare Low Register
|
||||
* - HW_EWM_CMPH - Compare High Register
|
||||
* - HW_EWM_CLKPRESCALER - Clock Prescaler Register
|
||||
*
|
||||
* - hw_ewm_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_EWM_CTRL - Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_EWM_CTRL - Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
|
||||
* written once after a CPU reset. Modifying these bits more than once, generates
|
||||
* a bus transfer error.
|
||||
*/
|
||||
typedef union _hw_ewm_ctrl
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_ctrl_bitfields
|
||||
{
|
||||
uint8_t EWMEN : 1; /*!< [0] EWM enable. */
|
||||
uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */
|
||||
uint8_t INEN : 1; /*!< [2] Input Enable. */
|
||||
uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */
|
||||
uint8_t RESERVED0 : 4; /*!< [7:4] */
|
||||
} B;
|
||||
} hw_ewm_ctrl_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_CTRL register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x))
|
||||
#define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U)
|
||||
#define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v))
|
||||
#define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v)))
|
||||
#define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v)))
|
||||
#define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_CTRL bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field EWMEN[0] (RW)
|
||||
*
|
||||
* This bit when set, enables the EWM module. This resets the EWM counter to
|
||||
* zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
|
||||
* therefore it cannot be enabled until a reset occurs, due to the write-once
|
||||
* nature of this bit.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */
|
||||
#define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */
|
||||
#define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */
|
||||
|
||||
/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
|
||||
#define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN))
|
||||
|
||||
/*! @brief Format value for bitfield EWM_CTRL_EWMEN. */
|
||||
#define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN)
|
||||
|
||||
/*! @brief Set the EWMEN field to a new value. */
|
||||
#define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field ASSIN[1] (RW)
|
||||
*
|
||||
* Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
|
||||
* inverts the assert state to a logic one.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */
|
||||
#define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */
|
||||
#define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */
|
||||
|
||||
/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
|
||||
#define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN))
|
||||
|
||||
/*! @brief Format value for bitfield EWM_CTRL_ASSIN. */
|
||||
#define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN)
|
||||
|
||||
/*! @brief Set the ASSIN field to a new value. */
|
||||
#define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field INEN[2] (RW)
|
||||
*
|
||||
* This bit when set, enables the EWM_in port.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */
|
||||
#define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */
|
||||
#define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */
|
||||
|
||||
/*! @brief Read current value of the EWM_CTRL_INEN field. */
|
||||
#define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN))
|
||||
|
||||
/*! @brief Format value for bitfield EWM_CTRL_INEN. */
|
||||
#define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN)
|
||||
|
||||
/*! @brief Set the INEN field to a new value. */
|
||||
#define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field INTEN[3] (RW)
|
||||
*
|
||||
* This bit when set and EWM_out is asserted, an interrupt request is generated.
|
||||
* To de-assert interrupt request, user should clear this bit by writing 0.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */
|
||||
#define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */
|
||||
#define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */
|
||||
|
||||
/*! @brief Read current value of the EWM_CTRL_INTEN field. */
|
||||
#define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN))
|
||||
|
||||
/*! @brief Format value for bitfield EWM_CTRL_INTEN. */
|
||||
#define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN)
|
||||
|
||||
/*! @brief Set the INTEN field to a new value. */
|
||||
#define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_EWM_SERV - Service Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_EWM_SERV - Service Register (WORZ)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* The SERV register provides the interface from the CPU to the EWM module. It
|
||||
* is write-only and reads of this register return zero.
|
||||
*/
|
||||
typedef union _hw_ewm_serv
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_serv_bitfields
|
||||
{
|
||||
uint8_t SERVICE : 8; /*!< [7:0] */
|
||||
} B;
|
||||
} hw_ewm_serv_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_SERV register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_EWM_SERV_ADDR(x) ((x) + 0x1U)
|
||||
|
||||
#define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x))
|
||||
#define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U)
|
||||
#define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_SERV bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
|
||||
*
|
||||
* The EWM service mechanism requires the CPU to write two values to the SERV
|
||||
* register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
|
||||
* EWM service is illegal if either of the following conditions is true. The
|
||||
* first or second data byte is not written correctly. The second data byte is not
|
||||
* written within a fixed number of peripheral bus cycles of the first data byte.
|
||||
* This fixed number of cycles is called EWM_service_time.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */
|
||||
#define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */
|
||||
#define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */
|
||||
|
||||
/*! @brief Format value for bitfield EWM_SERV_SERVICE. */
|
||||
#define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE)
|
||||
|
||||
/*! @brief Set the SERVICE field to a new value. */
|
||||
#define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_EWM_CMPL - Compare Low Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_EWM_CMPL - Compare Low Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* The CMPL register is reset to zero after a CPU reset. This provides no
|
||||
* minimum time for the CPU to service the EWM counter. This register can be written
|
||||
* only once after a CPU reset. Writing this register more than once generates a
|
||||
* bus transfer error.
|
||||
*/
|
||||
typedef union _hw_ewm_cmpl
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_cmpl_bitfields
|
||||
{
|
||||
uint8_t COMPAREL : 8; /*!< [7:0] */
|
||||
} B;
|
||||
} hw_ewm_cmpl_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_CMPL register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U)
|
||||
|
||||
#define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x))
|
||||
#define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U)
|
||||
#define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v))
|
||||
#define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v)))
|
||||
#define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v)))
|
||||
#define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_CMPL bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
|
||||
*
|
||||
* To prevent runaway code from changing this field, software should write to
|
||||
* this field after a CPU reset even if the (default) minimum service time is
|
||||
* required.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */
|
||||
#define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */
|
||||
#define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */
|
||||
|
||||
/*! @brief Read current value of the EWM_CMPL_COMPAREL field. */
|
||||
#define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */
|
||||
#define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL)
|
||||
|
||||
/*! @brief Set the COMPAREL field to a new value. */
|
||||
#define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_EWM_CMPH - Compare High Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_EWM_CMPH - Compare High Register (RW)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*
|
||||
* The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
|
||||
* of 256 clocks time, for the CPU to service the EWM counter. This register can
|
||||
* be written only once after a CPU reset. Writing this register more than once
|
||||
* generates a bus transfer error. The valid values for CMPH are up to 0xFE
|
||||
* because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
|
||||
* if EWM counter is greater than CMPH.
|
||||
*/
|
||||
typedef union _hw_ewm_cmph
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_cmph_bitfields
|
||||
{
|
||||
uint8_t COMPAREH : 8; /*!< [7:0] */
|
||||
} B;
|
||||
} hw_ewm_cmph_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_CMPH register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U)
|
||||
|
||||
#define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x))
|
||||
#define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U)
|
||||
#define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v))
|
||||
#define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v)))
|
||||
#define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v)))
|
||||
#define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_CMPH bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
|
||||
*
|
||||
* To prevent runaway code from changing this field, software should write to
|
||||
* this field after a CPU reset even if the (default) maximum service time is
|
||||
* required.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */
|
||||
#define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */
|
||||
#define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */
|
||||
|
||||
/*! @brief Read current value of the EWM_CMPH_COMPAREH field. */
|
||||
#define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */
|
||||
#define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH)
|
||||
|
||||
/*! @brief Set the COMPAREH field to a new value. */
|
||||
#define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_EWM_CLKPRESCALER - Clock Prescaler Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_EWM_CLKPRESCALER - Clock Prescaler Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* This CLKPRESCALER register is reset to 0x00 after a CPU reset. This register
|
||||
* can be written only once after a CPU reset. Writing this register more than
|
||||
* once generates a bus transfer error. Write the required prescaler value before
|
||||
* enabling the EWM. The implementation of this register is chip-specific. See the
|
||||
* Chip Configuration details.
|
||||
*/
|
||||
typedef union _hw_ewm_clkprescaler
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_clkprescaler_bitfields
|
||||
{
|
||||
uint8_t CLK_DIV : 8; /*!< [7:0] */
|
||||
} B;
|
||||
} hw_ewm_clkprescaler_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_CLKPRESCALER register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_EWM_CLKPRESCALER_ADDR(x) ((x) + 0x5U)
|
||||
|
||||
#define HW_EWM_CLKPRESCALER(x) (*(__IO hw_ewm_clkprescaler_t *) HW_EWM_CLKPRESCALER_ADDR(x))
|
||||
#define HW_EWM_CLKPRESCALER_RD(x) (HW_EWM_CLKPRESCALER(x).U)
|
||||
#define HW_EWM_CLKPRESCALER_WR(x, v) (HW_EWM_CLKPRESCALER(x).U = (v))
|
||||
#define HW_EWM_CLKPRESCALER_SET(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) | (v)))
|
||||
#define HW_EWM_CLKPRESCALER_CLR(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) & ~(v)))
|
||||
#define HW_EWM_CLKPRESCALER_TOG(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_CLKPRESCALER bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CLKPRESCALER, field CLK_DIV[7:0] (RW)
|
||||
*
|
||||
* Selected low power source for running the EWM counter can be prescaled as
|
||||
* below. Prescaled clock frequency = low power clock source frequency/ ( 1+ CLK_DIV
|
||||
* )
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_EWM_CLKPRESCALER_CLK_DIV (0U) /*!< Bit position for EWM_CLKPRESCALER_CLK_DIV. */
|
||||
#define BM_EWM_CLKPRESCALER_CLK_DIV (0xFFU) /*!< Bit mask for EWM_CLKPRESCALER_CLK_DIV. */
|
||||
#define BS_EWM_CLKPRESCALER_CLK_DIV (8U) /*!< Bit field size in bits for EWM_CLKPRESCALER_CLK_DIV. */
|
||||
|
||||
/*! @brief Read current value of the EWM_CLKPRESCALER_CLK_DIV field. */
|
||||
#define BR_EWM_CLKPRESCALER_CLK_DIV(x) (HW_EWM_CLKPRESCALER(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield EWM_CLKPRESCALER_CLK_DIV. */
|
||||
#define BF_EWM_CLKPRESCALER_CLK_DIV(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CLKPRESCALER_CLK_DIV) & BM_EWM_CLKPRESCALER_CLK_DIV)
|
||||
|
||||
/*! @brief Set the CLK_DIV field to a new value. */
|
||||
#define BW_EWM_CLKPRESCALER_CLK_DIV(x, v) (HW_EWM_CLKPRESCALER_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_ewm_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All EWM module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_ewm
|
||||
{
|
||||
__IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */
|
||||
__O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */
|
||||
__IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */
|
||||
__IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */
|
||||
uint8_t _reserved0[1];
|
||||
__IO hw_ewm_clkprescaler_t CLKPRESCALER; /*!< [0x5] Clock Prescaler Register */
|
||||
} hw_ewm_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all EWM registers. */
|
||||
/*! @param x EWM module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */
|
||||
#define HW_EWM(x) (*(hw_ewm_t *)(x))
|
||||
|
||||
#endif /* __HW_EWM_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,476 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_GPIO_REGISTERS_H__
|
||||
#define __HW_GPIO_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 GPIO
|
||||
*
|
||||
* General Purpose Input/Output
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_GPIO_PDOR - Port Data Output Register
|
||||
* - HW_GPIO_PSOR - Port Set Output Register
|
||||
* - HW_GPIO_PCOR - Port Clear Output Register
|
||||
* - HW_GPIO_PTOR - Port Toggle Output Register
|
||||
* - HW_GPIO_PDIR - Port Data Input Register
|
||||
* - HW_GPIO_PDDR - Port Data Direction Register
|
||||
*
|
||||
* - hw_gpio_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
|
||||
#define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
|
||||
#define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
|
||||
#define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
|
||||
#define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
|
||||
#define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_GPIO_PDOR - Port Data Output Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_GPIO_PDOR - Port Data Output Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* This register configures the logic levels that are driven on each
|
||||
* general-purpose output pins. Do not modify pin configuration registers associated with
|
||||
* pins not available in your selected package. All unbonded pins not available in
|
||||
* your package will default to DISABLE state for lowest power consumption.
|
||||
*/
|
||||
typedef union _hw_gpio_pdor
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_gpio_pdor_bitfields
|
||||
{
|
||||
uint32_t PDO : 32; /*!< [31:0] Port Data Output */
|
||||
} B;
|
||||
} hw_gpio_pdor_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPIO_PDOR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_GPIO_PDOR_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
|
||||
#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
|
||||
#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
|
||||
#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
|
||||
#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
|
||||
#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual GPIO_PDOR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register GPIO_PDOR, field PDO[31:0] (RW)
|
||||
*
|
||||
* Register bits for unbonded pins return a undefined value when read.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Logic level 0 is driven on pin, provided pin is configured for
|
||||
* general-purpose output.
|
||||
* - 1 - Logic level 1 is driven on pin, provided pin is configured for
|
||||
* general-purpose output.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_GPIO_PDOR_PDO (0U) /*!< Bit position for GPIO_PDOR_PDO. */
|
||||
#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
|
||||
#define BS_GPIO_PDOR_PDO (32U) /*!< Bit field size in bits for GPIO_PDOR_PDO. */
|
||||
|
||||
/*! @brief Read current value of the GPIO_PDOR_PDO field. */
|
||||
#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield GPIO_PDOR_PDO. */
|
||||
#define BF_GPIO_PDOR_PDO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
|
||||
|
||||
/*! @brief Set the PDO field to a new value. */
|
||||
#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_GPIO_PSOR - Port Set Output Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* This register configures whether to set the fields of the PDOR.
|
||||
*/
|
||||
typedef union _hw_gpio_psor
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_gpio_psor_bitfields
|
||||
{
|
||||
uint32_t PTSO : 32; /*!< [31:0] Port Set Output */
|
||||
} B;
|
||||
} hw_gpio_psor_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPIO_PSOR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_GPIO_PSOR_ADDR(x) ((x) + 0x4U)
|
||||
|
||||
#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
|
||||
#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
|
||||
#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual GPIO_PSOR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
|
||||
*
|
||||
* Writing to this register will update the contents of the corresponding bit in
|
||||
* the PDOR as follows:
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Corresponding bit in PDORn does not change.
|
||||
* - 1 - Corresponding bit in PDORn is set to logic 1.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_GPIO_PSOR_PTSO (0U) /*!< Bit position for GPIO_PSOR_PTSO. */
|
||||
#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
|
||||
#define BS_GPIO_PSOR_PTSO (32U) /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
|
||||
|
||||
/*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
|
||||
#define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
|
||||
|
||||
/*! @brief Set the PTSO field to a new value. */
|
||||
#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_GPIO_PCOR - Port Clear Output Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* This register configures whether to clear the fields of PDOR.
|
||||
*/
|
||||
typedef union _hw_gpio_pcor
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_gpio_pcor_bitfields
|
||||
{
|
||||
uint32_t PTCO : 32; /*!< [31:0] Port Clear Output */
|
||||
} B;
|
||||
} hw_gpio_pcor_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPIO_PCOR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_GPIO_PCOR_ADDR(x) ((x) + 0x8U)
|
||||
|
||||
#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
|
||||
#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
|
||||
#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual GPIO_PCOR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
|
||||
*
|
||||
* Writing to this register will update the contents of the corresponding bit in
|
||||
* the Port Data Output Register (PDOR) as follows:
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Corresponding bit in PDORn does not change.
|
||||
* - 1 - Corresponding bit in PDORn is cleared to logic 0.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_GPIO_PCOR_PTCO (0U) /*!< Bit position for GPIO_PCOR_PTCO. */
|
||||
#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
|
||||
#define BS_GPIO_PCOR_PTCO (32U) /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
|
||||
|
||||
/*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
|
||||
#define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
|
||||
|
||||
/*! @brief Set the PTCO field to a new value. */
|
||||
#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_GPIO_PTOR - Port Toggle Output Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*/
|
||||
typedef union _hw_gpio_ptor
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_gpio_ptor_bitfields
|
||||
{
|
||||
uint32_t PTTO : 32; /*!< [31:0] Port Toggle Output */
|
||||
} B;
|
||||
} hw_gpio_ptor_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPIO_PTOR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_GPIO_PTOR_ADDR(x) ((x) + 0xCU)
|
||||
|
||||
#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
|
||||
#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
|
||||
#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual GPIO_PTOR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
|
||||
*
|
||||
* Writing to this register will update the contents of the corresponding bit in
|
||||
* the PDOR as follows:
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Corresponding bit in PDORn does not change.
|
||||
* - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
|
||||
* state.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_GPIO_PTOR_PTTO (0U) /*!< Bit position for GPIO_PTOR_PTTO. */
|
||||
#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
|
||||
#define BS_GPIO_PTOR_PTTO (32U) /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
|
||||
|
||||
/*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
|
||||
#define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
|
||||
|
||||
/*! @brief Set the PTTO field to a new value. */
|
||||
#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_GPIO_PDIR - Port Data Input Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_GPIO_PDIR - Port Data Input Register (RO)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* Do not modify pin configuration registers associated with pins not available
|
||||
* in your selected package. All unbonded pins not available in your package will
|
||||
* default to DISABLE state for lowest power consumption.
|
||||
*/
|
||||
typedef union _hw_gpio_pdir
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_gpio_pdir_bitfields
|
||||
{
|
||||
uint32_t PDI : 32; /*!< [31:0] Port Data Input */
|
||||
} B;
|
||||
} hw_gpio_pdir_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPIO_PDIR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_GPIO_PDIR_ADDR(x) ((x) + 0x10U)
|
||||
|
||||
#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
|
||||
#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual GPIO_PDIR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register GPIO_PDIR, field PDI[31:0] (RO)
|
||||
*
|
||||
* Reads 0 at the unimplemented pins for a particular device. Pins that are not
|
||||
* configured for a digital function read 0. If the Port Control and Interrupt
|
||||
* module is disabled, then the corresponding bit in PDIR does not update.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Pin logic level is logic 0, or is not configured for use by digital
|
||||
* function.
|
||||
* - 1 - Pin logic level is logic 1.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_GPIO_PDIR_PDI (0U) /*!< Bit position for GPIO_PDIR_PDI. */
|
||||
#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
|
||||
#define BS_GPIO_PDIR_PDI (32U) /*!< Bit field size in bits for GPIO_PDIR_PDI. */
|
||||
|
||||
/*! @brief Read current value of the GPIO_PDIR_PDI field. */
|
||||
#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_GPIO_PDDR - Port Data Direction Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* The PDDR configures the individual port pins for input or output.
|
||||
*/
|
||||
typedef union _hw_gpio_pddr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_gpio_pddr_bitfields
|
||||
{
|
||||
uint32_t PDD : 32; /*!< [31:0] Port Data Direction */
|
||||
} B;
|
||||
} hw_gpio_pddr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire GPIO_PDDR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_GPIO_PDDR_ADDR(x) ((x) + 0x14U)
|
||||
|
||||
#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
|
||||
#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
|
||||
#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
|
||||
#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
|
||||
#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
|
||||
#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual GPIO_PDDR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register GPIO_PDDR, field PDD[31:0] (RW)
|
||||
*
|
||||
* Configures individual port pins for input or output.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Pin is configured as general-purpose input, for the GPIO function.
|
||||
* - 1 - Pin is configured as general-purpose output, for the GPIO function.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_GPIO_PDDR_PDD (0U) /*!< Bit position for GPIO_PDDR_PDD. */
|
||||
#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
|
||||
#define BS_GPIO_PDDR_PDD (32U) /*!< Bit field size in bits for GPIO_PDDR_PDD. */
|
||||
|
||||
/*! @brief Read current value of the GPIO_PDDR_PDD field. */
|
||||
#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield GPIO_PDDR_PDD. */
|
||||
#define BF_GPIO_PDDR_PDD(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
|
||||
|
||||
/*! @brief Set the PDD field to a new value. */
|
||||
#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_gpio_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All GPIO module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_gpio
|
||||
{
|
||||
__IO hw_gpio_pdor_t PDOR; /*!< [0x0] Port Data Output Register */
|
||||
__O hw_gpio_psor_t PSOR; /*!< [0x4] Port Set Output Register */
|
||||
__O hw_gpio_pcor_t PCOR; /*!< [0x8] Port Clear Output Register */
|
||||
__O hw_gpio_ptor_t PTOR; /*!< [0xC] Port Toggle Output Register */
|
||||
__I hw_gpio_pdir_t PDIR; /*!< [0x10] Port Data Input Register */
|
||||
__IO hw_gpio_pddr_t PDDR; /*!< [0x14] Port Data Direction Register */
|
||||
} hw_gpio_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all GPIO registers. */
|
||||
/*! @param x GPIO module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
|
||||
#define HW_GPIO(x) (*(hw_gpio_t *)(x))
|
||||
|
||||
#endif /* __HW_GPIO_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,603 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_LPTMR_REGISTERS_H__
|
||||
#define __HW_LPTMR_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 LPTMR
|
||||
*
|
||||
* Low Power Timer
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_LPTMR_CSR - Low Power Timer Control Status Register
|
||||
* - HW_LPTMR_PSR - Low Power Timer Prescale Register
|
||||
* - HW_LPTMR_CMR - Low Power Timer Compare Register
|
||||
* - HW_LPTMR_CNR - Low Power Timer Counter Register
|
||||
*
|
||||
* - hw_lptmr_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_LPTMR_CSR - Low Power Timer Control Status Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*/
|
||||
typedef union _hw_lptmr_csr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_lptmr_csr_bitfields
|
||||
{
|
||||
uint32_t TEN : 1; /*!< [0] Timer Enable */
|
||||
uint32_t TMS : 1; /*!< [1] Timer Mode Select */
|
||||
uint32_t TFC : 1; /*!< [2] Timer Free-Running Counter */
|
||||
uint32_t TPP : 1; /*!< [3] Timer Pin Polarity */
|
||||
uint32_t TPS : 2; /*!< [5:4] Timer Pin Select */
|
||||
uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */
|
||||
uint32_t TCF : 1; /*!< [7] Timer Compare Flag */
|
||||
uint32_t RESERVED0 : 24; /*!< [31:8] */
|
||||
} B;
|
||||
} hw_lptmr_csr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire LPTMR_CSR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_LPTMR_CSR_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_LPTMR_CSR(x) (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x))
|
||||
#define HW_LPTMR_CSR_RD(x) (HW_LPTMR_CSR(x).U)
|
||||
#define HW_LPTMR_CSR_WR(x, v) (HW_LPTMR_CSR(x).U = (v))
|
||||
#define HW_LPTMR_CSR_SET(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) | (v)))
|
||||
#define HW_LPTMR_CSR_CLR(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v)))
|
||||
#define HW_LPTMR_CSR_TOG(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual LPTMR_CSR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CSR, field TEN[0] (RW)
|
||||
*
|
||||
* When TEN is clear, it resets the LPTMR internal logic, including the CNR and
|
||||
* TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
|
||||
* CSR[5:1] must not be altered.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - LPTMR is disabled and internal logic is reset.
|
||||
* - 1 - LPTMR is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CSR_TEN (0U) /*!< Bit position for LPTMR_CSR_TEN. */
|
||||
#define BM_LPTMR_CSR_TEN (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */
|
||||
#define BS_LPTMR_CSR_TEN (1U) /*!< Bit field size in bits for LPTMR_CSR_TEN. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CSR_TEN field. */
|
||||
#define BR_LPTMR_CSR_TEN(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN))
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CSR_TEN. */
|
||||
#define BF_LPTMR_CSR_TEN(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN)
|
||||
|
||||
/*! @brief Set the TEN field to a new value. */
|
||||
#define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CSR, field TMS[1] (RW)
|
||||
*
|
||||
* Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
|
||||
* disabled.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Time Counter mode.
|
||||
* - 1 - Pulse Counter mode.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CSR_TMS (1U) /*!< Bit position for LPTMR_CSR_TMS. */
|
||||
#define BM_LPTMR_CSR_TMS (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */
|
||||
#define BS_LPTMR_CSR_TMS (1U) /*!< Bit field size in bits for LPTMR_CSR_TMS. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CSR_TMS field. */
|
||||
#define BR_LPTMR_CSR_TMS(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS))
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CSR_TMS. */
|
||||
#define BF_LPTMR_CSR_TMS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS)
|
||||
|
||||
/*! @brief Set the TMS field to a new value. */
|
||||
#define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CSR, field TFC[2] (RW)
|
||||
*
|
||||
* When clear, TFC configures the CNR to reset whenever TCF is set. When set,
|
||||
* TFC configures the CNR to reset on overflow. TFC must be altered only when the
|
||||
* LPTMR is disabled.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - CNR is reset whenever TCF is set.
|
||||
* - 1 - CNR is reset on overflow.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CSR_TFC (2U) /*!< Bit position for LPTMR_CSR_TFC. */
|
||||
#define BM_LPTMR_CSR_TFC (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */
|
||||
#define BS_LPTMR_CSR_TFC (1U) /*!< Bit field size in bits for LPTMR_CSR_TFC. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CSR_TFC field. */
|
||||
#define BR_LPTMR_CSR_TFC(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC))
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CSR_TFC. */
|
||||
#define BF_LPTMR_CSR_TFC(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC)
|
||||
|
||||
/*! @brief Set the TFC field to a new value. */
|
||||
#define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CSR, field TPP[3] (RW)
|
||||
*
|
||||
* Configures the polarity of the input source in Pulse Counter mode. TPP must
|
||||
* be changed only when the LPTMR is disabled.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Pulse Counter input source is active-high, and the CNR will increment
|
||||
* on the rising-edge.
|
||||
* - 1 - Pulse Counter input source is active-low, and the CNR will increment on
|
||||
* the falling-edge.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CSR_TPP (3U) /*!< Bit position for LPTMR_CSR_TPP. */
|
||||
#define BM_LPTMR_CSR_TPP (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */
|
||||
#define BS_LPTMR_CSR_TPP (1U) /*!< Bit field size in bits for LPTMR_CSR_TPP. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CSR_TPP field. */
|
||||
#define BR_LPTMR_CSR_TPP(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP))
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CSR_TPP. */
|
||||
#define BF_LPTMR_CSR_TPP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP)
|
||||
|
||||
/*! @brief Set the TPP field to a new value. */
|
||||
#define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CSR, field TPS[5:4] (RW)
|
||||
*
|
||||
* Configures the input source to be used in Pulse Counter mode. TPS must be
|
||||
* altered only when the LPTMR is disabled. The input connections vary by device.
|
||||
* See the chip configuration details for information on the connections to these
|
||||
* inputs.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Pulse counter input 0 is selected.
|
||||
* - 01 - Pulse counter input 1 is selected.
|
||||
* - 10 - Pulse counter input 2 is selected.
|
||||
* - 11 - Pulse counter input 3 is selected.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CSR_TPS (4U) /*!< Bit position for LPTMR_CSR_TPS. */
|
||||
#define BM_LPTMR_CSR_TPS (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */
|
||||
#define BS_LPTMR_CSR_TPS (2U) /*!< Bit field size in bits for LPTMR_CSR_TPS. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CSR_TPS field. */
|
||||
#define BR_LPTMR_CSR_TPS(x) (HW_LPTMR_CSR(x).B.TPS)
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CSR_TPS. */
|
||||
#define BF_LPTMR_CSR_TPS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS)
|
||||
|
||||
/*! @brief Set the TPS field to a new value. */
|
||||
#define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CSR, field TIE[6] (RW)
|
||||
*
|
||||
* When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Timer interrupt disabled.
|
||||
* - 1 - Timer interrupt enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CSR_TIE (6U) /*!< Bit position for LPTMR_CSR_TIE. */
|
||||
#define BM_LPTMR_CSR_TIE (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */
|
||||
#define BS_LPTMR_CSR_TIE (1U) /*!< Bit field size in bits for LPTMR_CSR_TIE. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CSR_TIE field. */
|
||||
#define BR_LPTMR_CSR_TIE(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE))
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CSR_TIE. */
|
||||
#define BF_LPTMR_CSR_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE)
|
||||
|
||||
/*! @brief Set the TIE field to a new value. */
|
||||
#define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CSR, field TCF[7] (W1C)
|
||||
*
|
||||
* TCF is set when the LPTMR is enabled and the CNR equals the CMR and
|
||||
* increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The value of CNR is not equal to CMR and increments.
|
||||
* - 1 - The value of CNR is equal to CMR and increments.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CSR_TCF (7U) /*!< Bit position for LPTMR_CSR_TCF. */
|
||||
#define BM_LPTMR_CSR_TCF (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */
|
||||
#define BS_LPTMR_CSR_TCF (1U) /*!< Bit field size in bits for LPTMR_CSR_TCF. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CSR_TCF field. */
|
||||
#define BR_LPTMR_CSR_TCF(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF))
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CSR_TCF. */
|
||||
#define BF_LPTMR_CSR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF)
|
||||
|
||||
/*! @brief Set the TCF field to a new value. */
|
||||
#define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_LPTMR_PSR - Low Power Timer Prescale Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*/
|
||||
typedef union _hw_lptmr_psr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_lptmr_psr_bitfields
|
||||
{
|
||||
uint32_t PCS : 2; /*!< [1:0] Prescaler Clock Select */
|
||||
uint32_t PBYP : 1; /*!< [2] Prescaler Bypass */
|
||||
uint32_t PRESCALE : 4; /*!< [6:3] Prescale Value */
|
||||
uint32_t RESERVED0 : 25; /*!< [31:7] */
|
||||
} B;
|
||||
} hw_lptmr_psr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire LPTMR_PSR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_LPTMR_PSR_ADDR(x) ((x) + 0x4U)
|
||||
|
||||
#define HW_LPTMR_PSR(x) (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x))
|
||||
#define HW_LPTMR_PSR_RD(x) (HW_LPTMR_PSR(x).U)
|
||||
#define HW_LPTMR_PSR_WR(x, v) (HW_LPTMR_PSR(x).U = (v))
|
||||
#define HW_LPTMR_PSR_SET(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) | (v)))
|
||||
#define HW_LPTMR_PSR_CLR(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v)))
|
||||
#define HW_LPTMR_PSR_TOG(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual LPTMR_PSR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_PSR, field PCS[1:0] (RW)
|
||||
*
|
||||
* Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
|
||||
* be altered only when the LPTMR is disabled. The clock connections vary by
|
||||
* device. See the chip configuration details for information on the connections to
|
||||
* these inputs.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Prescaler/glitch filter clock 0 selected.
|
||||
* - 01 - Prescaler/glitch filter clock 1 selected.
|
||||
* - 10 - Prescaler/glitch filter clock 2 selected.
|
||||
* - 11 - Prescaler/glitch filter clock 3 selected.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_PSR_PCS (0U) /*!< Bit position for LPTMR_PSR_PCS. */
|
||||
#define BM_LPTMR_PSR_PCS (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */
|
||||
#define BS_LPTMR_PSR_PCS (2U) /*!< Bit field size in bits for LPTMR_PSR_PCS. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_PSR_PCS field. */
|
||||
#define BR_LPTMR_PSR_PCS(x) (HW_LPTMR_PSR(x).B.PCS)
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_PSR_PCS. */
|
||||
#define BF_LPTMR_PSR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS)
|
||||
|
||||
/*! @brief Set the PCS field to a new value. */
|
||||
#define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_PSR, field PBYP[2] (RW)
|
||||
*
|
||||
* When PBYP is set, the selected prescaler clock in Time Counter mode or
|
||||
* selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
|
||||
* clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
|
||||
* must be altered only when the LPTMR is disabled.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Prescaler/glitch filter is enabled.
|
||||
* - 1 - Prescaler/glitch filter is bypassed.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_PSR_PBYP (2U) /*!< Bit position for LPTMR_PSR_PBYP. */
|
||||
#define BM_LPTMR_PSR_PBYP (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */
|
||||
#define BS_LPTMR_PSR_PBYP (1U) /*!< Bit field size in bits for LPTMR_PSR_PBYP. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
|
||||
#define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP))
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_PSR_PBYP. */
|
||||
#define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP)
|
||||
|
||||
/*! @brief Set the PBYP field to a new value. */
|
||||
#define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
|
||||
*
|
||||
* Configures the size of the Prescaler in Time Counter mode or width of the
|
||||
* glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
|
||||
* is disabled.
|
||||
*
|
||||
* Values:
|
||||
* - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
|
||||
* support this configuration.
|
||||
* - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
|
||||
* change on input pin after 2 rising clock edges.
|
||||
* - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
|
||||
* change on input pin after 4 rising clock edges.
|
||||
* - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
|
||||
* recognizes change on input pin after 8 rising clock edges.
|
||||
* - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
|
||||
* recognizes change on input pin after 16 rising clock edges.
|
||||
* - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
|
||||
* recognizes change on input pin after 32 rising clock edges.
|
||||
* - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
|
||||
* recognizes change on input pin after 64 rising clock edges.
|
||||
* - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
|
||||
* recognizes change on input pin after 128 rising clock edges.
|
||||
* - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
|
||||
* recognizes change on input pin after 256 rising clock edges.
|
||||
* - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
|
||||
* recognizes change on input pin after 512 rising clock edges.
|
||||
* - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
|
||||
* recognizes change on input pin after 1024 rising clock edges.
|
||||
* - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
|
||||
* recognizes change on input pin after 2048 rising clock edges.
|
||||
* - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
|
||||
* recognizes change on input pin after 4096 rising clock edges.
|
||||
* - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
|
||||
* recognizes change on input pin after 8192 rising clock edges.
|
||||
* - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
|
||||
* recognizes change on input pin after 16,384 rising clock edges.
|
||||
* - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
|
||||
* recognizes change on input pin after 32,768 rising clock edges.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_PSR_PRESCALE (3U) /*!< Bit position for LPTMR_PSR_PRESCALE. */
|
||||
#define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */
|
||||
#define BS_LPTMR_PSR_PRESCALE (4U) /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
|
||||
#define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE)
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */
|
||||
#define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE)
|
||||
|
||||
/*! @brief Set the PRESCALE field to a new value. */
|
||||
#define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_LPTMR_CMR - Low Power Timer Compare Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*/
|
||||
typedef union _hw_lptmr_cmr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_lptmr_cmr_bitfields
|
||||
{
|
||||
uint32_t COMPARE : 16; /*!< [15:0] Compare Value */
|
||||
uint32_t RESERVED0 : 16; /*!< [31:16] */
|
||||
} B;
|
||||
} hw_lptmr_cmr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire LPTMR_CMR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_LPTMR_CMR_ADDR(x) ((x) + 0x8U)
|
||||
|
||||
#define HW_LPTMR_CMR(x) (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x))
|
||||
#define HW_LPTMR_CMR_RD(x) (HW_LPTMR_CMR(x).U)
|
||||
#define HW_LPTMR_CMR_WR(x, v) (HW_LPTMR_CMR(x).U = (v))
|
||||
#define HW_LPTMR_CMR_SET(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) | (v)))
|
||||
#define HW_LPTMR_CMR_CLR(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v)))
|
||||
#define HW_LPTMR_CMR_TOG(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual LPTMR_CMR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
|
||||
*
|
||||
* When the LPTMR is enabled and the CNR equals the value in the CMR and
|
||||
* increments, TCF is set and the hardware trigger asserts until the next time the CNR
|
||||
* increments. If the CMR is 0, the hardware trigger will remain asserted until
|
||||
* the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
|
||||
* when TCF is set.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CMR_COMPARE (0U) /*!< Bit position for LPTMR_CMR_COMPARE. */
|
||||
#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */
|
||||
#define BS_LPTMR_CMR_COMPARE (16U) /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
|
||||
#define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE)
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */
|
||||
#define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE)
|
||||
|
||||
/*! @brief Set the COMPARE field to a new value. */
|
||||
#define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_LPTMR_CNR - Low Power Timer Counter Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*/
|
||||
typedef union _hw_lptmr_cnr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_lptmr_cnr_bitfields
|
||||
{
|
||||
uint32_t COUNTER : 16; /*!< [15:0] Counter Value */
|
||||
uint32_t RESERVED0 : 16; /*!< [31:16] */
|
||||
} B;
|
||||
} hw_lptmr_cnr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire LPTMR_CNR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_LPTMR_CNR_ADDR(x) ((x) + 0xCU)
|
||||
|
||||
#define HW_LPTMR_CNR(x) (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x))
|
||||
#define HW_LPTMR_CNR_RD(x) (HW_LPTMR_CNR(x).U)
|
||||
#define HW_LPTMR_CNR_WR(x, v) (HW_LPTMR_CNR(x).U = (v))
|
||||
#define HW_LPTMR_CNR_SET(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) | (v)))
|
||||
#define HW_LPTMR_CNR_CLR(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v)))
|
||||
#define HW_LPTMR_CNR_TOG(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual LPTMR_CNR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_LPTMR_CNR_COUNTER (0U) /*!< Bit position for LPTMR_CNR_COUNTER. */
|
||||
#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */
|
||||
#define BS_LPTMR_CNR_COUNTER (16U) /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */
|
||||
|
||||
/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
|
||||
#define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER)
|
||||
|
||||
/*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */
|
||||
#define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER)
|
||||
|
||||
/*! @brief Set the COUNTER field to a new value. */
|
||||
#define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_lptmr_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All LPTMR module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_lptmr
|
||||
{
|
||||
__IO hw_lptmr_csr_t CSR; /*!< [0x0] Low Power Timer Control Status Register */
|
||||
__IO hw_lptmr_psr_t PSR; /*!< [0x4] Low Power Timer Prescale Register */
|
||||
__IO hw_lptmr_cmr_t CMR; /*!< [0x8] Low Power Timer Compare Register */
|
||||
__IO hw_lptmr_cnr_t CNR; /*!< [0xC] Low Power Timer Counter Register */
|
||||
} hw_lptmr_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all LPTMR registers. */
|
||||
/*! @param x LPTMR module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_LPTMR(LPTMR0_BASE)</code>. */
|
||||
#define HW_LPTMR(x) (*(hw_lptmr_t *)(x))
|
||||
|
||||
#endif /* __HW_LPTMR_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,702 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_MCM_REGISTERS_H__
|
||||
#define __HW_MCM_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 MCM
|
||||
*
|
||||
* Core Platform Miscellaneous Control Module
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
|
||||
* - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
|
||||
* - HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register
|
||||
* - HW_MCM_ISCR - Interrupt Status and Control Register
|
||||
* - HW_MCM_CPO - Compute Operation Control Register
|
||||
*
|
||||
* - hw_mcm_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
|
||||
*
|
||||
* Reset value: 0x000FU
|
||||
*
|
||||
* PLASC is a 16-bit read-only register identifying the presence/absence of bus
|
||||
* slave connections to the device's crossbar switch.
|
||||
*/
|
||||
typedef union _hw_mcm_plasc
|
||||
{
|
||||
uint16_t U;
|
||||
struct _hw_mcm_plasc_bitfields
|
||||
{
|
||||
uint16_t ASC : 8; /*!< [7:0] Each bit in the ASC field indicates
|
||||
* whether there is a corresponding connection to the crossbar switch's slave
|
||||
* input port. */
|
||||
uint16_t RESERVED0 : 8; /*!< [15:8] */
|
||||
} B;
|
||||
} hw_mcm_plasc_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire MCM_PLASC register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_MCM_PLASC_ADDR(x) ((x) + 0x8U)
|
||||
|
||||
#define HW_MCM_PLASC(x) (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x))
|
||||
#define HW_MCM_PLASC_RD(x) (HW_MCM_PLASC(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual MCM_PLASC bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_PLASC, field ASC[7:0] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - A bus slave connection to AXBS input port n is absent
|
||||
* - 1 - A bus slave connection to AXBS input port n is present
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_PLASC_ASC (0U) /*!< Bit position for MCM_PLASC_ASC. */
|
||||
#define BM_MCM_PLASC_ASC (0x00FFU) /*!< Bit mask for MCM_PLASC_ASC. */
|
||||
#define BS_MCM_PLASC_ASC (8U) /*!< Bit field size in bits for MCM_PLASC_ASC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_PLASC_ASC field. */
|
||||
#define BR_MCM_PLASC_ASC(x) (HW_MCM_PLASC(x).B.ASC)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
|
||||
*
|
||||
* Reset value: 0x0017U
|
||||
*
|
||||
* PLAMC is a 16-bit read-only register identifying the presence/absence of bus
|
||||
* master connections to the device's crossbar switch.
|
||||
*/
|
||||
typedef union _hw_mcm_plamc
|
||||
{
|
||||
uint16_t U;
|
||||
struct _hw_mcm_plamc_bitfields
|
||||
{
|
||||
uint16_t AMC : 8; /*!< [7:0] Each bit in the AMC field indicates
|
||||
* whether there is a corresponding connection to the AXBS master input port. */
|
||||
uint16_t RESERVED0 : 8; /*!< [15:8] */
|
||||
} B;
|
||||
} hw_mcm_plamc_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire MCM_PLAMC register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_MCM_PLAMC_ADDR(x) ((x) + 0xAU)
|
||||
|
||||
#define HW_MCM_PLAMC(x) (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x))
|
||||
#define HW_MCM_PLAMC_RD(x) (HW_MCM_PLAMC(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual MCM_PLAMC bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_PLAMC, field AMC[7:0] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - A bus master connection to AXBS input port n is absent
|
||||
* - 1 - A bus master connection to AXBS input port n is present
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_PLAMC_AMC (0U) /*!< Bit position for MCM_PLAMC_AMC. */
|
||||
#define BM_MCM_PLAMC_AMC (0x00FFU) /*!< Bit mask for MCM_PLAMC_AMC. */
|
||||
#define BS_MCM_PLAMC_AMC (8U) /*!< Bit field size in bits for MCM_PLAMC_AMC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_PLAMC_AMC field. */
|
||||
#define BR_MCM_PLAMC_AMC(x) (HW_MCM_PLAMC(x).B.AMC)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* The PLACR register selects the arbitration policy for the crossbar masters.
|
||||
*/
|
||||
typedef union _hw_mcm_placr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_mcm_placr_bitfields
|
||||
{
|
||||
uint32_t RESERVED0 : 9; /*!< [8:0] */
|
||||
uint32_t ARB : 1; /*!< [9] Arbitration select */
|
||||
uint32_t RESERVED1 : 22; /*!< [31:10] */
|
||||
} B;
|
||||
} hw_mcm_placr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire MCM_PLACR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_MCM_PLACR_ADDR(x) ((x) + 0xCU)
|
||||
|
||||
#define HW_MCM_PLACR(x) (*(__IO hw_mcm_placr_t *) HW_MCM_PLACR_ADDR(x))
|
||||
#define HW_MCM_PLACR_RD(x) (HW_MCM_PLACR(x).U)
|
||||
#define HW_MCM_PLACR_WR(x, v) (HW_MCM_PLACR(x).U = (v))
|
||||
#define HW_MCM_PLACR_SET(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) | (v)))
|
||||
#define HW_MCM_PLACR_CLR(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) & ~(v)))
|
||||
#define HW_MCM_PLACR_TOG(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual MCM_PLACR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_PLACR, field ARB[9] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Fixed-priority arbitration for the crossbar masters
|
||||
* - 1 - Round-robin arbitration for the crossbar masters
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_PLACR_ARB (9U) /*!< Bit position for MCM_PLACR_ARB. */
|
||||
#define BM_MCM_PLACR_ARB (0x00000200U) /*!< Bit mask for MCM_PLACR_ARB. */
|
||||
#define BS_MCM_PLACR_ARB (1U) /*!< Bit field size in bits for MCM_PLACR_ARB. */
|
||||
|
||||
/*! @brief Read current value of the MCM_PLACR_ARB field. */
|
||||
#define BR_MCM_PLACR_ARB(x) (HW_MCM_PLACR(x).B.ARB)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_PLACR_ARB. */
|
||||
#define BF_MCM_PLACR_ARB(v) ((uint32_t)((uint32_t)(v) << BP_MCM_PLACR_ARB) & BM_MCM_PLACR_ARB)
|
||||
|
||||
/*! @brief Set the ARB field to a new value. */
|
||||
#define BW_MCM_PLACR_ARB(x, v) (HW_MCM_PLACR_WR(x, (HW_MCM_PLACR_RD(x) & ~BM_MCM_PLACR_ARB) | BF_MCM_PLACR_ARB(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_MCM_ISCR - Interrupt Status and Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_MCM_ISCR - Interrupt Status and Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00020000U
|
||||
*
|
||||
* The MCM_ISCR register includes the enable and status bits associated with the
|
||||
* core's floating-point exceptions. The individual event indicators are first
|
||||
* qualified with their exception enables and then logically summed to form an
|
||||
* interrupt request sent to the core's NVIC. Bits 15-8 are read-only indicator
|
||||
* flags based on the processor's FPSCR register. Attempted writes to these bits are
|
||||
* ignored. Once set, the flags remain asserted until software clears the
|
||||
* corresponding FPSCR bit.
|
||||
*/
|
||||
typedef union _hw_mcm_iscr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_mcm_iscr_bitfields
|
||||
{
|
||||
uint32_t RESERVED0 : 8; /*!< [7:0] */
|
||||
uint32_t FIOC : 1; /*!< [8] FPU invalid operation interrupt status */
|
||||
uint32_t FDZC : 1; /*!< [9] FPU divide-by-zero interrupt status */
|
||||
uint32_t FOFC : 1; /*!< [10] FPU overflow interrupt status */
|
||||
uint32_t FUFC : 1; /*!< [11] FPU underflow interrupt status */
|
||||
uint32_t FIXC : 1; /*!< [12] FPU inexact interrupt status */
|
||||
uint32_t RESERVED1 : 2; /*!< [14:13] */
|
||||
uint32_t FIDC : 1; /*!< [15] FPU input denormal interrupt status */
|
||||
uint32_t RESERVED2 : 8; /*!< [23:16] */
|
||||
uint32_t FIOCE : 1; /*!< [24] FPU invalid operation interrupt enable
|
||||
* */
|
||||
uint32_t FDZCE : 1; /*!< [25] FPU divide-by-zero interrupt enable */
|
||||
uint32_t FOFCE : 1; /*!< [26] FPU overflow interrupt enable */
|
||||
uint32_t FUFCE : 1; /*!< [27] FPU underflow interrupt enable */
|
||||
uint32_t FIXCE : 1; /*!< [28] FPU inexact interrupt enable */
|
||||
uint32_t RESERVED3 : 2; /*!< [30:29] */
|
||||
uint32_t FIDCE : 1; /*!< [31] FPU input denormal interrupt enable */
|
||||
} B;
|
||||
} hw_mcm_iscr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire MCM_ISCR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_MCM_ISCR_ADDR(x) ((x) + 0x10U)
|
||||
|
||||
#define HW_MCM_ISCR(x) (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x))
|
||||
#define HW_MCM_ISCR_RD(x) (HW_MCM_ISCR(x).U)
|
||||
#define HW_MCM_ISCR_WR(x, v) (HW_MCM_ISCR(x).U = (v))
|
||||
#define HW_MCM_ISCR_SET(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) | (v)))
|
||||
#define HW_MCM_ISCR_CLR(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v)))
|
||||
#define HW_MCM_ISCR_TOG(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual MCM_ISCR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FIOC[8] (RO)
|
||||
*
|
||||
* This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
|
||||
* illegal operation has been detected in the processor's FPU. Once set, this bit
|
||||
* remains set until software clears the FPSCR[IOC] bit.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - No interrupt
|
||||
* - 1 - Interrupt occurred
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FIOC (8U) /*!< Bit position for MCM_ISCR_FIOC. */
|
||||
#define BM_MCM_ISCR_FIOC (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */
|
||||
#define BS_MCM_ISCR_FIOC (1U) /*!< Bit field size in bits for MCM_ISCR_FIOC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FIOC field. */
|
||||
#define BR_MCM_ISCR_FIOC(x) (HW_MCM_ISCR(x).B.FIOC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FDZC[9] (RO)
|
||||
*
|
||||
* This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
|
||||
* divide by zero has been detected in the processor's FPU. Once set, this bit remains
|
||||
* set until software clears the FPSCR[DZC] bit.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - No interrupt
|
||||
* - 1 - Interrupt occurred
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FDZC (9U) /*!< Bit position for MCM_ISCR_FDZC. */
|
||||
#define BM_MCM_ISCR_FDZC (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */
|
||||
#define BS_MCM_ISCR_FDZC (1U) /*!< Bit field size in bits for MCM_ISCR_FDZC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FDZC field. */
|
||||
#define BR_MCM_ISCR_FDZC(x) (HW_MCM_ISCR(x).B.FDZC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FOFC[10] (RO)
|
||||
*
|
||||
* This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
|
||||
* overflow has been detected in the processor's FPU. Once set, this bit remains set
|
||||
* until software clears the FPSCR[OFC] bit.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - No interrupt
|
||||
* - 1 - Interrupt occurred
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FOFC (10U) /*!< Bit position for MCM_ISCR_FOFC. */
|
||||
#define BM_MCM_ISCR_FOFC (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */
|
||||
#define BS_MCM_ISCR_FOFC (1U) /*!< Bit field size in bits for MCM_ISCR_FOFC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FOFC field. */
|
||||
#define BR_MCM_ISCR_FOFC(x) (HW_MCM_ISCR(x).B.FOFC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FUFC[11] (RO)
|
||||
*
|
||||
* This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
|
||||
* underflow has been detected in the processor's FPU. Once set, this bit remains set
|
||||
* until software clears the FPSCR[UFC] bit.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - No interrupt
|
||||
* - 1 - Interrupt occurred
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FUFC (11U) /*!< Bit position for MCM_ISCR_FUFC. */
|
||||
#define BM_MCM_ISCR_FUFC (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */
|
||||
#define BS_MCM_ISCR_FUFC (1U) /*!< Bit field size in bits for MCM_ISCR_FUFC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FUFC field. */
|
||||
#define BR_MCM_ISCR_FUFC(x) (HW_MCM_ISCR(x).B.FUFC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FIXC[12] (RO)
|
||||
*
|
||||
* This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
|
||||
* inexact number has been detected in the processor's FPU. Once set, this bit
|
||||
* remains set until software clears the FPSCR[IXC] bit.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - No interrupt
|
||||
* - 1 - Interrupt occurred
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FIXC (12U) /*!< Bit position for MCM_ISCR_FIXC. */
|
||||
#define BM_MCM_ISCR_FIXC (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */
|
||||
#define BS_MCM_ISCR_FIXC (1U) /*!< Bit field size in bits for MCM_ISCR_FIXC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FIXC field. */
|
||||
#define BR_MCM_ISCR_FIXC(x) (HW_MCM_ISCR(x).B.FIXC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FIDC[15] (RO)
|
||||
*
|
||||
* This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
|
||||
* denormalized number has been detected in the processor's FPU. Once set, this
|
||||
* bit remains set until software clears the FPSCR[IDC] bit.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - No interrupt
|
||||
* - 1 - Interrupt occurred
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FIDC (15U) /*!< Bit position for MCM_ISCR_FIDC. */
|
||||
#define BM_MCM_ISCR_FIDC (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */
|
||||
#define BS_MCM_ISCR_FIDC (1U) /*!< Bit field size in bits for MCM_ISCR_FIDC. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FIDC field. */
|
||||
#define BR_MCM_ISCR_FIDC(x) (HW_MCM_ISCR(x).B.FIDC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FIOCE[24] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable interrupt
|
||||
* - 1 - Enable interrupt
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FIOCE (24U) /*!< Bit position for MCM_ISCR_FIOCE. */
|
||||
#define BM_MCM_ISCR_FIOCE (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */
|
||||
#define BS_MCM_ISCR_FIOCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIOCE. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
|
||||
#define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_ISCR_FIOCE. */
|
||||
#define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE)
|
||||
|
||||
/*! @brief Set the FIOCE field to a new value. */
|
||||
#define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FDZCE[25] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable interrupt
|
||||
* - 1 - Enable interrupt
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FDZCE (25U) /*!< Bit position for MCM_ISCR_FDZCE. */
|
||||
#define BM_MCM_ISCR_FDZCE (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */
|
||||
#define BS_MCM_ISCR_FDZCE (1U) /*!< Bit field size in bits for MCM_ISCR_FDZCE. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
|
||||
#define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_ISCR_FDZCE. */
|
||||
#define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE)
|
||||
|
||||
/*! @brief Set the FDZCE field to a new value. */
|
||||
#define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FOFCE[26] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable interrupt
|
||||
* - 1 - Enable interrupt
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FOFCE (26U) /*!< Bit position for MCM_ISCR_FOFCE. */
|
||||
#define BM_MCM_ISCR_FOFCE (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */
|
||||
#define BS_MCM_ISCR_FOFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FOFCE. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
|
||||
#define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_ISCR_FOFCE. */
|
||||
#define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE)
|
||||
|
||||
/*! @brief Set the FOFCE field to a new value. */
|
||||
#define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FUFCE[27] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable interrupt
|
||||
* - 1 - Enable interrupt
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FUFCE (27U) /*!< Bit position for MCM_ISCR_FUFCE. */
|
||||
#define BM_MCM_ISCR_FUFCE (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */
|
||||
#define BS_MCM_ISCR_FUFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FUFCE. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
|
||||
#define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_ISCR_FUFCE. */
|
||||
#define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE)
|
||||
|
||||
/*! @brief Set the FUFCE field to a new value. */
|
||||
#define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FIXCE[28] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable interrupt
|
||||
* - 1 - Enable interrupt
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FIXCE (28U) /*!< Bit position for MCM_ISCR_FIXCE. */
|
||||
#define BM_MCM_ISCR_FIXCE (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */
|
||||
#define BS_MCM_ISCR_FIXCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIXCE. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
|
||||
#define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_ISCR_FIXCE. */
|
||||
#define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE)
|
||||
|
||||
/*! @brief Set the FIXCE field to a new value. */
|
||||
#define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_ISCR, field FIDCE[31] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable interrupt
|
||||
* - 1 - Enable interrupt
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_ISCR_FIDCE (31U) /*!< Bit position for MCM_ISCR_FIDCE. */
|
||||
#define BM_MCM_ISCR_FIDCE (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */
|
||||
#define BS_MCM_ISCR_FIDCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIDCE. */
|
||||
|
||||
/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
|
||||
#define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_ISCR_FIDCE. */
|
||||
#define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE)
|
||||
|
||||
/*! @brief Set the FIDCE field to a new value. */
|
||||
#define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_MCM_CPO - Compute Operation Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_MCM_CPO - Compute Operation Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* This register controls the Compute Operation.
|
||||
*/
|
||||
typedef union _hw_mcm_cpo
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_mcm_cpo_bitfields
|
||||
{
|
||||
uint32_t CPOREQ : 1; /*!< [0] Compute Operation request */
|
||||
uint32_t CPOACK : 1; /*!< [1] Compute Operation acknowledge */
|
||||
uint32_t CPOWOI : 1; /*!< [2] Compute Operation wakeup on interrupt */
|
||||
uint32_t RESERVED0 : 29; /*!< [31:3] */
|
||||
} B;
|
||||
} hw_mcm_cpo_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire MCM_CPO register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_MCM_CPO_ADDR(x) ((x) + 0x40U)
|
||||
|
||||
#define HW_MCM_CPO(x) (*(__IO hw_mcm_cpo_t *) HW_MCM_CPO_ADDR(x))
|
||||
#define HW_MCM_CPO_RD(x) (HW_MCM_CPO(x).U)
|
||||
#define HW_MCM_CPO_WR(x, v) (HW_MCM_CPO(x).U = (v))
|
||||
#define HW_MCM_CPO_SET(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) | (v)))
|
||||
#define HW_MCM_CPO_CLR(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) & ~(v)))
|
||||
#define HW_MCM_CPO_TOG(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual MCM_CPO bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_CPO, field CPOREQ[0] (RW)
|
||||
*
|
||||
* This bit is auto-cleared by vector fetching if CPOWOI = 1.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Request is cleared.
|
||||
* - 1 - Request Compute Operation.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_CPO_CPOREQ (0U) /*!< Bit position for MCM_CPO_CPOREQ. */
|
||||
#define BM_MCM_CPO_CPOREQ (0x00000001U) /*!< Bit mask for MCM_CPO_CPOREQ. */
|
||||
#define BS_MCM_CPO_CPOREQ (1U) /*!< Bit field size in bits for MCM_CPO_CPOREQ. */
|
||||
|
||||
/*! @brief Read current value of the MCM_CPO_CPOREQ field. */
|
||||
#define BR_MCM_CPO_CPOREQ(x) (HW_MCM_CPO(x).B.CPOREQ)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_CPO_CPOREQ. */
|
||||
#define BF_MCM_CPO_CPOREQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOREQ) & BM_MCM_CPO_CPOREQ)
|
||||
|
||||
/*! @brief Set the CPOREQ field to a new value. */
|
||||
#define BW_MCM_CPO_CPOREQ(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOREQ) | BF_MCM_CPO_CPOREQ(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_CPO, field CPOACK[1] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Compute operation entry has not completed or compute operation exit has
|
||||
* completed.
|
||||
* - 1 - Compute operation entry has completed or compute operation exit has not
|
||||
* completed.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_CPO_CPOACK (1U) /*!< Bit position for MCM_CPO_CPOACK. */
|
||||
#define BM_MCM_CPO_CPOACK (0x00000002U) /*!< Bit mask for MCM_CPO_CPOACK. */
|
||||
#define BS_MCM_CPO_CPOACK (1U) /*!< Bit field size in bits for MCM_CPO_CPOACK. */
|
||||
|
||||
/*! @brief Read current value of the MCM_CPO_CPOACK field. */
|
||||
#define BR_MCM_CPO_CPOACK(x) (HW_MCM_CPO(x).B.CPOACK)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register MCM_CPO, field CPOWOI[2] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - No effect.
|
||||
* - 1 - When set, the CPOREQ is cleared on any interrupt or exception vector
|
||||
* fetch.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_MCM_CPO_CPOWOI (2U) /*!< Bit position for MCM_CPO_CPOWOI. */
|
||||
#define BM_MCM_CPO_CPOWOI (0x00000004U) /*!< Bit mask for MCM_CPO_CPOWOI. */
|
||||
#define BS_MCM_CPO_CPOWOI (1U) /*!< Bit field size in bits for MCM_CPO_CPOWOI. */
|
||||
|
||||
/*! @brief Read current value of the MCM_CPO_CPOWOI field. */
|
||||
#define BR_MCM_CPO_CPOWOI(x) (HW_MCM_CPO(x).B.CPOWOI)
|
||||
|
||||
/*! @brief Format value for bitfield MCM_CPO_CPOWOI. */
|
||||
#define BF_MCM_CPO_CPOWOI(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOWOI) & BM_MCM_CPO_CPOWOI)
|
||||
|
||||
/*! @brief Set the CPOWOI field to a new value. */
|
||||
#define BW_MCM_CPO_CPOWOI(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOWOI) | BF_MCM_CPO_CPOWOI(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_mcm_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All MCM module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_mcm
|
||||
{
|
||||
uint8_t _reserved0[8];
|
||||
__I hw_mcm_plasc_t PLASC; /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */
|
||||
__I hw_mcm_plamc_t PLAMC; /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */
|
||||
__IO hw_mcm_placr_t PLACR; /*!< [0xC] Crossbar Switch (AXBS) Control Register */
|
||||
__IO hw_mcm_iscr_t ISCR; /*!< [0x10] Interrupt Status and Control Register */
|
||||
uint8_t _reserved1[44];
|
||||
__IO hw_mcm_cpo_t CPO; /*!< [0x40] Compute Operation Control Register */
|
||||
} hw_mcm_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all MCM registers. */
|
||||
/*! @param x MCM module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */
|
||||
#define HW_MCM(x) (*(hw_mcm_t *)(x))
|
||||
|
||||
#endif /* __HW_MCM_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
|
|
@ -0,0 +1,858 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_NV_REGISTERS_H__
|
||||
#define __HW_NV_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 NV
|
||||
*
|
||||
* Flash configuration field
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
|
||||
* - HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
|
||||
* - HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
|
||||
* - HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
|
||||
* - HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
|
||||
* - HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
|
||||
* - HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
|
||||
* - HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
|
||||
* - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
|
||||
* - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
|
||||
* - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
|
||||
* - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
|
||||
* - HW_NV_FSEC - Non-volatile Flash Security Register
|
||||
* - HW_NV_FOPT - Non-volatile Flash Option Register
|
||||
*
|
||||
* - hw_nv_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey3
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey3_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey3_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY3 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY3_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_NV_BACKKEY3(x) (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR(x))
|
||||
#define HW_NV_BACKKEY3_RD(x) (HW_NV_BACKKEY3(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY3 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY3, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY3_KEY (0U) /*!< Bit position for NV_BACKKEY3_KEY. */
|
||||
#define BM_NV_BACKKEY3_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY3_KEY. */
|
||||
#define BS_NV_BACKKEY3_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY3_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY3_KEY field. */
|
||||
#define BR_NV_BACKKEY3_KEY(x) (HW_NV_BACKKEY3(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey2
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey2_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey2_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY2 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY2_ADDR(x) ((x) + 0x1U)
|
||||
|
||||
#define HW_NV_BACKKEY2(x) (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR(x))
|
||||
#define HW_NV_BACKKEY2_RD(x) (HW_NV_BACKKEY2(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY2 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY2, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY2_KEY (0U) /*!< Bit position for NV_BACKKEY2_KEY. */
|
||||
#define BM_NV_BACKKEY2_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY2_KEY. */
|
||||
#define BS_NV_BACKKEY2_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY2_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY2_KEY field. */
|
||||
#define BR_NV_BACKKEY2_KEY(x) (HW_NV_BACKKEY2(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey1
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey1_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey1_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY1 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY1_ADDR(x) ((x) + 0x2U)
|
||||
|
||||
#define HW_NV_BACKKEY1(x) (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR(x))
|
||||
#define HW_NV_BACKKEY1_RD(x) (HW_NV_BACKKEY1(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY1 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY1, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY1_KEY (0U) /*!< Bit position for NV_BACKKEY1_KEY. */
|
||||
#define BM_NV_BACKKEY1_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY1_KEY. */
|
||||
#define BS_NV_BACKKEY1_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY1_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY1_KEY field. */
|
||||
#define BR_NV_BACKKEY1_KEY(x) (HW_NV_BACKKEY1(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey0
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey0_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey0_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY0 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY0_ADDR(x) ((x) + 0x3U)
|
||||
|
||||
#define HW_NV_BACKKEY0(x) (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR(x))
|
||||
#define HW_NV_BACKKEY0_RD(x) (HW_NV_BACKKEY0(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY0 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY0, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY0_KEY (0U) /*!< Bit position for NV_BACKKEY0_KEY. */
|
||||
#define BM_NV_BACKKEY0_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY0_KEY. */
|
||||
#define BS_NV_BACKKEY0_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY0_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY0_KEY field. */
|
||||
#define BR_NV_BACKKEY0_KEY(x) (HW_NV_BACKKEY0(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey7
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey7_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey7_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY7 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY7_ADDR(x) ((x) + 0x4U)
|
||||
|
||||
#define HW_NV_BACKKEY7(x) (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR(x))
|
||||
#define HW_NV_BACKKEY7_RD(x) (HW_NV_BACKKEY7(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY7 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY7, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY7_KEY (0U) /*!< Bit position for NV_BACKKEY7_KEY. */
|
||||
#define BM_NV_BACKKEY7_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY7_KEY. */
|
||||
#define BS_NV_BACKKEY7_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY7_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY7_KEY field. */
|
||||
#define BR_NV_BACKKEY7_KEY(x) (HW_NV_BACKKEY7(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey6
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey6_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey6_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY6 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY6_ADDR(x) ((x) + 0x5U)
|
||||
|
||||
#define HW_NV_BACKKEY6(x) (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR(x))
|
||||
#define HW_NV_BACKKEY6_RD(x) (HW_NV_BACKKEY6(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY6 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY6, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY6_KEY (0U) /*!< Bit position for NV_BACKKEY6_KEY. */
|
||||
#define BM_NV_BACKKEY6_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY6_KEY. */
|
||||
#define BS_NV_BACKKEY6_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY6_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY6_KEY field. */
|
||||
#define BR_NV_BACKKEY6_KEY(x) (HW_NV_BACKKEY6(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey5
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey5_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey5_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY5 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY5_ADDR(x) ((x) + 0x6U)
|
||||
|
||||
#define HW_NV_BACKKEY5(x) (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR(x))
|
||||
#define HW_NV_BACKKEY5_RD(x) (HW_NV_BACKKEY5(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY5 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY5, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY5_KEY (0U) /*!< Bit position for NV_BACKKEY5_KEY. */
|
||||
#define BM_NV_BACKKEY5_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY5_KEY. */
|
||||
#define BS_NV_BACKKEY5_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY5_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY5_KEY field. */
|
||||
#define BR_NV_BACKKEY5_KEY(x) (HW_NV_BACKKEY5(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_backkey4
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_backkey4_bitfields
|
||||
{
|
||||
uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */
|
||||
} B;
|
||||
} hw_nv_backkey4_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_BACKKEY4 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_BACKKEY4_ADDR(x) ((x) + 0x7U)
|
||||
|
||||
#define HW_NV_BACKKEY4(x) (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR(x))
|
||||
#define HW_NV_BACKKEY4_RD(x) (HW_NV_BACKKEY4(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_BACKKEY4 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_BACKKEY4, field KEY[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_BACKKEY4_KEY (0U) /*!< Bit position for NV_BACKKEY4_KEY. */
|
||||
#define BM_NV_BACKKEY4_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY4_KEY. */
|
||||
#define BS_NV_BACKKEY4_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY4_KEY. */
|
||||
|
||||
/*! @brief Read current value of the NV_BACKKEY4_KEY field. */
|
||||
#define BR_NV_BACKKEY4_KEY(x) (HW_NV_BACKKEY4(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_fprot3
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_fprot3_bitfields
|
||||
{
|
||||
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
|
||||
} B;
|
||||
} hw_nv_fprot3_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_FPROT3 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_FPROT3_ADDR(x) ((x) + 0x8U)
|
||||
|
||||
#define HW_NV_FPROT3(x) (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR(x))
|
||||
#define HW_NV_FPROT3_RD(x) (HW_NV_FPROT3(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_FPROT3 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FPROT3, field PROT[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FPROT3_PROT (0U) /*!< Bit position for NV_FPROT3_PROT. */
|
||||
#define BM_NV_FPROT3_PROT (0xFFU) /*!< Bit mask for NV_FPROT3_PROT. */
|
||||
#define BS_NV_FPROT3_PROT (8U) /*!< Bit field size in bits for NV_FPROT3_PROT. */
|
||||
|
||||
/*! @brief Read current value of the NV_FPROT3_PROT field. */
|
||||
#define BR_NV_FPROT3_PROT(x) (HW_NV_FPROT3(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_fprot2
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_fprot2_bitfields
|
||||
{
|
||||
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
|
||||
} B;
|
||||
} hw_nv_fprot2_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_FPROT2 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_FPROT2_ADDR(x) ((x) + 0x9U)
|
||||
|
||||
#define HW_NV_FPROT2(x) (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR(x))
|
||||
#define HW_NV_FPROT2_RD(x) (HW_NV_FPROT2(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_FPROT2 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FPROT2, field PROT[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FPROT2_PROT (0U) /*!< Bit position for NV_FPROT2_PROT. */
|
||||
#define BM_NV_FPROT2_PROT (0xFFU) /*!< Bit mask for NV_FPROT2_PROT. */
|
||||
#define BS_NV_FPROT2_PROT (8U) /*!< Bit field size in bits for NV_FPROT2_PROT. */
|
||||
|
||||
/*! @brief Read current value of the NV_FPROT2_PROT field. */
|
||||
#define BR_NV_FPROT2_PROT(x) (HW_NV_FPROT2(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_fprot1
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_fprot1_bitfields
|
||||
{
|
||||
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
|
||||
} B;
|
||||
} hw_nv_fprot1_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_FPROT1 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_FPROT1_ADDR(x) ((x) + 0xAU)
|
||||
|
||||
#define HW_NV_FPROT1(x) (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR(x))
|
||||
#define HW_NV_FPROT1_RD(x) (HW_NV_FPROT1(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_FPROT1 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FPROT1, field PROT[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FPROT1_PROT (0U) /*!< Bit position for NV_FPROT1_PROT. */
|
||||
#define BM_NV_FPROT1_PROT (0xFFU) /*!< Bit mask for NV_FPROT1_PROT. */
|
||||
#define BS_NV_FPROT1_PROT (8U) /*!< Bit field size in bits for NV_FPROT1_PROT. */
|
||||
|
||||
/*! @brief Read current value of the NV_FPROT1_PROT field. */
|
||||
#define BR_NV_FPROT1_PROT(x) (HW_NV_FPROT1(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_fprot0
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_fprot0_bitfields
|
||||
{
|
||||
uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */
|
||||
} B;
|
||||
} hw_nv_fprot0_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_FPROT0 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_FPROT0_ADDR(x) ((x) + 0xBU)
|
||||
|
||||
#define HW_NV_FPROT0(x) (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR(x))
|
||||
#define HW_NV_FPROT0_RD(x) (HW_NV_FPROT0(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_FPROT0 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FPROT0, field PROT[7:0] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FPROT0_PROT (0U) /*!< Bit position for NV_FPROT0_PROT. */
|
||||
#define BM_NV_FPROT0_PROT (0xFFU) /*!< Bit mask for NV_FPROT0_PROT. */
|
||||
#define BS_NV_FPROT0_PROT (8U) /*!< Bit field size in bits for NV_FPROT0_PROT. */
|
||||
|
||||
/*! @brief Read current value of the NV_FPROT0_PROT field. */
|
||||
#define BR_NV_FPROT0_PROT(x) (HW_NV_FPROT0(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_FSEC - Non-volatile Flash Security Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*
|
||||
* Allows the user to customize the operation of the MCU at boot time
|
||||
*/
|
||||
typedef union _hw_nv_fsec
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_fsec_bitfields
|
||||
{
|
||||
uint8_t SEC : 2; /*!< [1:0] Flash Security */
|
||||
uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code
|
||||
* */
|
||||
uint8_t MEEN : 2; /*!< [5:4] */
|
||||
uint8_t KEYEN : 2; /*!< [7:6] Backdoor Key Security Enable */
|
||||
} B;
|
||||
} hw_nv_fsec_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_FSEC register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_FSEC_ADDR(x) ((x) + 0xCU)
|
||||
|
||||
#define HW_NV_FSEC(x) (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR(x))
|
||||
#define HW_NV_FSEC_RD(x) (HW_NV_FSEC(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_FSEC bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FSEC, field SEC[1:0] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 10 - MCU security status is unsecure
|
||||
* - 11 - MCU security status is secure
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FSEC_SEC (0U) /*!< Bit position for NV_FSEC_SEC. */
|
||||
#define BM_NV_FSEC_SEC (0x03U) /*!< Bit mask for NV_FSEC_SEC. */
|
||||
#define BS_NV_FSEC_SEC (2U) /*!< Bit field size in bits for NV_FSEC_SEC. */
|
||||
|
||||
/*! @brief Read current value of the NV_FSEC_SEC field. */
|
||||
#define BR_NV_FSEC_SEC(x) (HW_NV_FSEC(x).B.SEC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FSEC, field FSLACC[3:2] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 10 - Freescale factory access denied
|
||||
* - 11 - Freescale factory access granted
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FSEC_FSLACC (2U) /*!< Bit position for NV_FSEC_FSLACC. */
|
||||
#define BM_NV_FSEC_FSLACC (0x0CU) /*!< Bit mask for NV_FSEC_FSLACC. */
|
||||
#define BS_NV_FSEC_FSLACC (2U) /*!< Bit field size in bits for NV_FSEC_FSLACC. */
|
||||
|
||||
/*! @brief Read current value of the NV_FSEC_FSLACC field. */
|
||||
#define BR_NV_FSEC_FSLACC(x) (HW_NV_FSEC(x).B.FSLACC)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FSEC, field MEEN[5:4] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 10 - Mass erase is disabled
|
||||
* - 11 - Mass erase is enabled
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FSEC_MEEN (4U) /*!< Bit position for NV_FSEC_MEEN. */
|
||||
#define BM_NV_FSEC_MEEN (0x30U) /*!< Bit mask for NV_FSEC_MEEN. */
|
||||
#define BS_NV_FSEC_MEEN (2U) /*!< Bit field size in bits for NV_FSEC_MEEN. */
|
||||
|
||||
/*! @brief Read current value of the NV_FSEC_MEEN field. */
|
||||
#define BR_NV_FSEC_MEEN(x) (HW_NV_FSEC(x).B.MEEN)
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FSEC, field KEYEN[7:6] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 10 - Backdoor key access enabled
|
||||
* - 11 - Backdoor key access disabled
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FSEC_KEYEN (6U) /*!< Bit position for NV_FSEC_KEYEN. */
|
||||
#define BM_NV_FSEC_KEYEN (0xC0U) /*!< Bit mask for NV_FSEC_KEYEN. */
|
||||
#define BS_NV_FSEC_KEYEN (2U) /*!< Bit field size in bits for NV_FSEC_KEYEN. */
|
||||
|
||||
/*! @brief Read current value of the NV_FSEC_KEYEN field. */
|
||||
#define BR_NV_FSEC_KEYEN(x) (HW_NV_FSEC(x).B.KEYEN)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_NV_FOPT - Non-volatile Flash Option Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*/
|
||||
typedef union _hw_nv_fopt
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_nv_fopt_bitfields
|
||||
{
|
||||
uint8_t LPBOOT : 1; /*!< [0] */
|
||||
uint8_t EZPORT_DIS : 1; /*!< [1] */
|
||||
uint8_t NMI_DIS : 1; /*!< [2] */
|
||||
uint8_t RESERVED0 : 2; /*!< [4:3] */
|
||||
uint8_t FAST_INIT : 1; /*!< [5] */
|
||||
uint8_t RESERVED1 : 2; /*!< [7:6] */
|
||||
} B;
|
||||
} hw_nv_fopt_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire NV_FOPT register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_NV_FOPT_ADDR(x) ((x) + 0xDU)
|
||||
|
||||
#define HW_NV_FOPT(x) (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR(x))
|
||||
#define HW_NV_FOPT_RD(x) (HW_NV_FOPT(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual NV_FOPT bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FOPT, field LPBOOT[0] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Low-power boot
|
||||
* - 01 - Normal boot
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FOPT_LPBOOT (0U) /*!< Bit position for NV_FOPT_LPBOOT. */
|
||||
#define BM_NV_FOPT_LPBOOT (0x01U) /*!< Bit mask for NV_FOPT_LPBOOT. */
|
||||
#define BS_NV_FOPT_LPBOOT (1U) /*!< Bit field size in bits for NV_FOPT_LPBOOT. */
|
||||
|
||||
/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
|
||||
#define BR_NV_FOPT_LPBOOT(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_LPBOOT))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FOPT_EZPORT_DIS (1U) /*!< Bit position for NV_FOPT_EZPORT_DIS. */
|
||||
#define BM_NV_FOPT_EZPORT_DIS (0x02U) /*!< Bit mask for NV_FOPT_EZPORT_DIS. */
|
||||
#define BS_NV_FOPT_EZPORT_DIS (1U) /*!< Bit field size in bits for NV_FOPT_EZPORT_DIS. */
|
||||
|
||||
/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
|
||||
#define BR_NV_FOPT_EZPORT_DIS(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_EZPORT_DIS))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FOPT, field NMI_DIS[2] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 00 - NMI interrupts are always blocked
|
||||
* - 01 - NMI_b pin/interrupts reset default to enabled
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FOPT_NMI_DIS (2U) /*!< Bit position for NV_FOPT_NMI_DIS. */
|
||||
#define BM_NV_FOPT_NMI_DIS (0x04U) /*!< Bit mask for NV_FOPT_NMI_DIS. */
|
||||
#define BS_NV_FOPT_NMI_DIS (1U) /*!< Bit field size in bits for NV_FOPT_NMI_DIS. */
|
||||
|
||||
/*! @brief Read current value of the NV_FOPT_NMI_DIS field. */
|
||||
#define BR_NV_FOPT_NMI_DIS(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_NMI_DIS))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register NV_FOPT, field FAST_INIT[5] (RO)
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Slower initialization
|
||||
* - 01 - Fast Initialization
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_NV_FOPT_FAST_INIT (5U) /*!< Bit position for NV_FOPT_FAST_INIT. */
|
||||
#define BM_NV_FOPT_FAST_INIT (0x20U) /*!< Bit mask for NV_FOPT_FAST_INIT. */
|
||||
#define BS_NV_FOPT_FAST_INIT (1U) /*!< Bit field size in bits for NV_FOPT_FAST_INIT. */
|
||||
|
||||
/*! @brief Read current value of the NV_FOPT_FAST_INIT field. */
|
||||
#define BR_NV_FOPT_FAST_INIT(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_FAST_INIT))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_nv_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All NV module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_nv
|
||||
{
|
||||
__I hw_nv_backkey3_t BACKKEY3; /*!< [0x0] Backdoor Comparison Key 3. */
|
||||
__I hw_nv_backkey2_t BACKKEY2; /*!< [0x1] Backdoor Comparison Key 2. */
|
||||
__I hw_nv_backkey1_t BACKKEY1; /*!< [0x2] Backdoor Comparison Key 1. */
|
||||
__I hw_nv_backkey0_t BACKKEY0; /*!< [0x3] Backdoor Comparison Key 0. */
|
||||
__I hw_nv_backkey7_t BACKKEY7; /*!< [0x4] Backdoor Comparison Key 7. */
|
||||
__I hw_nv_backkey6_t BACKKEY6; /*!< [0x5] Backdoor Comparison Key 6. */
|
||||
__I hw_nv_backkey5_t BACKKEY5; /*!< [0x6] Backdoor Comparison Key 5. */
|
||||
__I hw_nv_backkey4_t BACKKEY4; /*!< [0x7] Backdoor Comparison Key 4. */
|
||||
__I hw_nv_fprot3_t FPROT3; /*!< [0x8] Non-volatile P-Flash Protection 1 - Low Register */
|
||||
__I hw_nv_fprot2_t FPROT2; /*!< [0x9] Non-volatile P-Flash Protection 1 - High Register */
|
||||
__I hw_nv_fprot1_t FPROT1; /*!< [0xA] Non-volatile P-Flash Protection 0 - Low Register */
|
||||
__I hw_nv_fprot0_t FPROT0; /*!< [0xB] Non-volatile P-Flash Protection 0 - High Register */
|
||||
__I hw_nv_fsec_t FSEC; /*!< [0xC] Non-volatile Flash Security Register */
|
||||
__I hw_nv_fopt_t FOPT; /*!< [0xD] Non-volatile Flash Option Register */
|
||||
} hw_nv_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all NV registers. */
|
||||
/*! @param x NV module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_NV(FTFA_FlashConfig_BASE)</code>. */
|
||||
#define HW_NV(x) (*(hw_nv_t *)(x))
|
||||
|
||||
#endif /* __HW_NV_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
|
|
@ -0,0 +1,367 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_OSC_REGISTERS_H__
|
||||
#define __HW_OSC_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 OSC
|
||||
*
|
||||
* Oscillator
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_OSC_CR - OSC Control Register
|
||||
* - HW_OSC_DIV - OSC_DIV
|
||||
*
|
||||
* - hw_osc_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_OSC_CR - OSC Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_OSC_CR - OSC Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* After OSC is enabled and starts generating the clocks, the configurations
|
||||
* such as low power and frequency range, must not be changed.
|
||||
*/
|
||||
typedef union _hw_osc_cr
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_osc_cr_bitfields
|
||||
{
|
||||
uint8_t SC16P : 1; /*!< [0] Oscillator 16 pF Capacitor Load Configure
|
||||
* */
|
||||
uint8_t SC8P : 1; /*!< [1] Oscillator 8 pF Capacitor Load Configure */
|
||||
uint8_t SC4P : 1; /*!< [2] Oscillator 4 pF Capacitor Load Configure */
|
||||
uint8_t SC2P : 1; /*!< [3] Oscillator 2 pF Capacitor Load Configure */
|
||||
uint8_t RESERVED0 : 1; /*!< [4] */
|
||||
uint8_t EREFSTEN : 1; /*!< [5] External Reference Stop Enable */
|
||||
uint8_t RESERVED1 : 1; /*!< [6] */
|
||||
uint8_t ERCLKEN : 1; /*!< [7] External Reference Enable */
|
||||
} B;
|
||||
} hw_osc_cr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire OSC_CR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_OSC_CR_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
|
||||
#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
|
||||
#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
|
||||
#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
|
||||
#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
|
||||
#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual OSC_CR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC16P[0] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 16 pF capacitor to the oscillator load.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_OSC_CR_SC16P (0U) /*!< Bit position for OSC_CR_SC16P. */
|
||||
#define BM_OSC_CR_SC16P (0x01U) /*!< Bit mask for OSC_CR_SC16P. */
|
||||
#define BS_OSC_CR_SC16P (1U) /*!< Bit field size in bits for OSC_CR_SC16P. */
|
||||
|
||||
/*! @brief Read current value of the OSC_CR_SC16P field. */
|
||||
#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
|
||||
|
||||
/*! @brief Format value for bitfield OSC_CR_SC16P. */
|
||||
#define BF_OSC_CR_SC16P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC16P) & BM_OSC_CR_SC16P)
|
||||
|
||||
/*! @brief Set the SC16P field to a new value. */
|
||||
#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC8P[1] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 8 pF capacitor to the oscillator load.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_OSC_CR_SC8P (1U) /*!< Bit position for OSC_CR_SC8P. */
|
||||
#define BM_OSC_CR_SC8P (0x02U) /*!< Bit mask for OSC_CR_SC8P. */
|
||||
#define BS_OSC_CR_SC8P (1U) /*!< Bit field size in bits for OSC_CR_SC8P. */
|
||||
|
||||
/*! @brief Read current value of the OSC_CR_SC8P field. */
|
||||
#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
|
||||
|
||||
/*! @brief Format value for bitfield OSC_CR_SC8P. */
|
||||
#define BF_OSC_CR_SC8P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC8P) & BM_OSC_CR_SC8P)
|
||||
|
||||
/*! @brief Set the SC8P field to a new value. */
|
||||
#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC4P[2] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 4 pF capacitor to the oscillator load.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_OSC_CR_SC4P (2U) /*!< Bit position for OSC_CR_SC4P. */
|
||||
#define BM_OSC_CR_SC4P (0x04U) /*!< Bit mask for OSC_CR_SC4P. */
|
||||
#define BS_OSC_CR_SC4P (1U) /*!< Bit field size in bits for OSC_CR_SC4P. */
|
||||
|
||||
/*! @brief Read current value of the OSC_CR_SC4P field. */
|
||||
#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
|
||||
|
||||
/*! @brief Format value for bitfield OSC_CR_SC4P. */
|
||||
#define BF_OSC_CR_SC4P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC4P) & BM_OSC_CR_SC4P)
|
||||
|
||||
/*! @brief Set the SC4P field to a new value. */
|
||||
#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC2P[3] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 2 pF capacitor to the oscillator load.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_OSC_CR_SC2P (3U) /*!< Bit position for OSC_CR_SC2P. */
|
||||
#define BM_OSC_CR_SC2P (0x08U) /*!< Bit mask for OSC_CR_SC2P. */
|
||||
#define BS_OSC_CR_SC2P (1U) /*!< Bit field size in bits for OSC_CR_SC2P. */
|
||||
|
||||
/*! @brief Read current value of the OSC_CR_SC2P field. */
|
||||
#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
|
||||
|
||||
/*! @brief Format value for bitfield OSC_CR_SC2P. */
|
||||
#define BF_OSC_CR_SC2P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC2P) & BM_OSC_CR_SC2P)
|
||||
|
||||
/*! @brief Set the SC2P field to a new value. */
|
||||
#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field EREFSTEN[5] (RW)
|
||||
*
|
||||
* Controls whether or not the external reference clock (OSCERCLK) remains
|
||||
* enabled when MCU enters Stop mode.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - External reference clock is disabled in Stop mode.
|
||||
* - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
|
||||
* before entering Stop mode.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_OSC_CR_EREFSTEN (5U) /*!< Bit position for OSC_CR_EREFSTEN. */
|
||||
#define BM_OSC_CR_EREFSTEN (0x20U) /*!< Bit mask for OSC_CR_EREFSTEN. */
|
||||
#define BS_OSC_CR_EREFSTEN (1U) /*!< Bit field size in bits for OSC_CR_EREFSTEN. */
|
||||
|
||||
/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
|
||||
#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
|
||||
|
||||
/*! @brief Format value for bitfield OSC_CR_EREFSTEN. */
|
||||
#define BF_OSC_CR_EREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_EREFSTEN) & BM_OSC_CR_EREFSTEN)
|
||||
|
||||
/*! @brief Set the EREFSTEN field to a new value. */
|
||||
#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field ERCLKEN[7] (RW)
|
||||
*
|
||||
* Enables external reference clock (OSCERCLK).
|
||||
*
|
||||
* Values:
|
||||
* - 0 - External reference clock is inactive.
|
||||
* - 1 - External reference clock is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_OSC_CR_ERCLKEN (7U) /*!< Bit position for OSC_CR_ERCLKEN. */
|
||||
#define BM_OSC_CR_ERCLKEN (0x80U) /*!< Bit mask for OSC_CR_ERCLKEN. */
|
||||
#define BS_OSC_CR_ERCLKEN (1U) /*!< Bit field size in bits for OSC_CR_ERCLKEN. */
|
||||
|
||||
/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
|
||||
#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
|
||||
|
||||
/*! @brief Format value for bitfield OSC_CR_ERCLKEN. */
|
||||
#define BF_OSC_CR_ERCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_ERCLKEN) & BM_OSC_CR_ERCLKEN)
|
||||
|
||||
/*! @brief Set the ERCLKEN field to a new value. */
|
||||
#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_OSC_DIV - OSC_DIV
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_OSC_DIV - OSC_DIV (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* OSC CLock divider register.
|
||||
*/
|
||||
typedef union _hw_osc_div
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_osc_div_bitfields
|
||||
{
|
||||
uint8_t RESERVED0 : 6; /*!< [5:0] */
|
||||
uint8_t ERPS : 2; /*!< [7:6] */
|
||||
} B;
|
||||
} hw_osc_div_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire OSC_DIV register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_OSC_DIV_ADDR(x) ((x) + 0x2U)
|
||||
|
||||
#define HW_OSC_DIV(x) (*(__IO hw_osc_div_t *) HW_OSC_DIV_ADDR(x))
|
||||
#define HW_OSC_DIV_RD(x) (HW_OSC_DIV(x).U)
|
||||
#define HW_OSC_DIV_WR(x, v) (HW_OSC_DIV(x).U = (v))
|
||||
#define HW_OSC_DIV_SET(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) | (v)))
|
||||
#define HW_OSC_DIV_CLR(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) & ~(v)))
|
||||
#define HW_OSC_DIV_TOG(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual OSC_DIV bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_DIV, field ERPS[7:6] (RW)
|
||||
*
|
||||
* ERCLK prescaler. These two bits are used to divide the ERCLK output. The
|
||||
* un-divided ERCLK output is not affected by these two bits.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - The divisor ratio is 1.
|
||||
* - 01 - The divisor ratio is 2.
|
||||
* - 10 - The divisor ratio is 4.
|
||||
* - 11 - The divisor ratio is 8.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_OSC_DIV_ERPS (6U) /*!< Bit position for OSC_DIV_ERPS. */
|
||||
#define BM_OSC_DIV_ERPS (0xC0U) /*!< Bit mask for OSC_DIV_ERPS. */
|
||||
#define BS_OSC_DIV_ERPS (2U) /*!< Bit field size in bits for OSC_DIV_ERPS. */
|
||||
|
||||
/*! @brief Read current value of the OSC_DIV_ERPS field. */
|
||||
#define BR_OSC_DIV_ERPS(x) (HW_OSC_DIV(x).B.ERPS)
|
||||
|
||||
/*! @brief Format value for bitfield OSC_DIV_ERPS. */
|
||||
#define BF_OSC_DIV_ERPS(v) ((uint8_t)((uint8_t)(v) << BP_OSC_DIV_ERPS) & BM_OSC_DIV_ERPS)
|
||||
|
||||
/*! @brief Set the ERPS field to a new value. */
|
||||
#define BW_OSC_DIV_ERPS(x, v) (HW_OSC_DIV_WR(x, (HW_OSC_DIV_RD(x) & ~BM_OSC_DIV_ERPS) | BF_OSC_DIV_ERPS(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_osc_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All OSC module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_osc
|
||||
{
|
||||
__IO hw_osc_cr_t CR; /*!< [0x0] OSC Control Register */
|
||||
uint8_t _reserved0[1];
|
||||
__IO hw_osc_div_t DIV; /*!< [0x2] OSC_DIV */
|
||||
} hw_osc_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all OSC registers. */
|
||||
/*! @param x OSC module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_OSC(OSC_BASE)</code>. */
|
||||
#define HW_OSC(x) (*(hw_osc_t *)(x))
|
||||
|
||||
#endif /* __HW_OSC_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,505 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_PIT_REGISTERS_H__
|
||||
#define __HW_PIT_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 PIT
|
||||
*
|
||||
* Periodic Interrupt Timer
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_PIT_MCR - PIT Module Control Register
|
||||
* - HW_PIT_LDVALn - Timer Load Value Register
|
||||
* - HW_PIT_CVALn - Current Timer Value Register
|
||||
* - HW_PIT_TCTRLn - Timer Control Register
|
||||
* - HW_PIT_TFLGn - Timer Flag Register
|
||||
*
|
||||
* - hw_pit_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PIT_MCR - PIT Module Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PIT_MCR - PIT Module Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000006U
|
||||
*
|
||||
* This register enables or disables the PIT timer clocks and controls the
|
||||
* timers when the PIT enters the Debug mode.
|
||||
*/
|
||||
typedef union _hw_pit_mcr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_pit_mcr_bitfields
|
||||
{
|
||||
uint32_t FRZ : 1; /*!< [0] Freeze */
|
||||
uint32_t MDIS : 1; /*!< [1] Module Disable - (PIT section) */
|
||||
uint32_t RESERVED0 : 30; /*!< [31:2] */
|
||||
} B;
|
||||
} hw_pit_mcr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PIT_MCR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PIT_MCR_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_PIT_MCR(x) (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x))
|
||||
#define HW_PIT_MCR_RD(x) (HW_PIT_MCR(x).U)
|
||||
#define HW_PIT_MCR_WR(x, v) (HW_PIT_MCR(x).U = (v))
|
||||
#define HW_PIT_MCR_SET(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) | (v)))
|
||||
#define HW_PIT_MCR_CLR(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v)))
|
||||
#define HW_PIT_MCR_TOG(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PIT_MCR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_MCR, field FRZ[0] (RW)
|
||||
*
|
||||
* Allows the timers to be stopped when the device enters the Debug mode.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Timers continue to run in Debug mode.
|
||||
* - 1 - Timers are stopped in Debug mode.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_MCR_FRZ (0U) /*!< Bit position for PIT_MCR_FRZ. */
|
||||
#define BM_PIT_MCR_FRZ (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */
|
||||
#define BS_PIT_MCR_FRZ (1U) /*!< Bit field size in bits for PIT_MCR_FRZ. */
|
||||
|
||||
/*! @brief Read current value of the PIT_MCR_FRZ field. */
|
||||
#define BR_PIT_MCR_FRZ(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ))
|
||||
|
||||
/*! @brief Format value for bitfield PIT_MCR_FRZ. */
|
||||
#define BF_PIT_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ)
|
||||
|
||||
/*! @brief Set the FRZ field to a new value. */
|
||||
#define BW_PIT_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_MCR, field MDIS[1] (RW)
|
||||
*
|
||||
* Disables the standard timers. This field must be enabled before any other
|
||||
* setup is done.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Clock for standard PIT timers is enabled.
|
||||
* - 1 - Clock for standard PIT timers is disabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_MCR_MDIS (1U) /*!< Bit position for PIT_MCR_MDIS. */
|
||||
#define BM_PIT_MCR_MDIS (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */
|
||||
#define BS_PIT_MCR_MDIS (1U) /*!< Bit field size in bits for PIT_MCR_MDIS. */
|
||||
|
||||
/*! @brief Read current value of the PIT_MCR_MDIS field. */
|
||||
#define BR_PIT_MCR_MDIS(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS))
|
||||
|
||||
/*! @brief Format value for bitfield PIT_MCR_MDIS. */
|
||||
#define BF_PIT_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS)
|
||||
|
||||
/*! @brief Set the MDIS field to a new value. */
|
||||
#define BW_PIT_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PIT_LDVALn - Timer Load Value Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* These registers select the timeout period for the timer interrupts.
|
||||
*/
|
||||
typedef union _hw_pit_ldvaln
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_pit_ldvaln_bitfields
|
||||
{
|
||||
uint32_t TSV : 32; /*!< [31:0] Timer Start Value */
|
||||
} B;
|
||||
} hw_pit_ldvaln_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PIT_LDVALn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PIT_LDVALn_COUNT (4U)
|
||||
|
||||
#define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n)))
|
||||
|
||||
#define HW_PIT_LDVALn(x, n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n))
|
||||
#define HW_PIT_LDVALn_RD(x, n) (HW_PIT_LDVALn(x, n).U)
|
||||
#define HW_PIT_LDVALn_WR(x, n, v) (HW_PIT_LDVALn(x, n).U = (v))
|
||||
#define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) | (v)))
|
||||
#define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v)))
|
||||
#define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PIT_LDVALn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_LDVALn, field TSV[31:0] (RW)
|
||||
*
|
||||
* Sets the timer start value. The timer will count down until it reaches 0,
|
||||
* then it will generate an interrupt and load this register value again. Writing a
|
||||
* new value to this register will not restart the timer; instead the value will
|
||||
* be loaded after the timer expires. To abort the current cycle and start a
|
||||
* timer period with the new value, the timer must be disabled and enabled again.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_LDVALn_TSV (0U) /*!< Bit position for PIT_LDVALn_TSV. */
|
||||
#define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */
|
||||
#define BS_PIT_LDVALn_TSV (32U) /*!< Bit field size in bits for PIT_LDVALn_TSV. */
|
||||
|
||||
/*! @brief Read current value of the PIT_LDVALn_TSV field. */
|
||||
#define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U)
|
||||
|
||||
/*! @brief Format value for bitfield PIT_LDVALn_TSV. */
|
||||
#define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV)
|
||||
|
||||
/*! @brief Set the TSV field to a new value. */
|
||||
#define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v))
|
||||
/*@}*/
|
||||
/*******************************************************************************
|
||||
* HW_PIT_CVALn - Current Timer Value Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PIT_CVALn - Current Timer Value Register (RO)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* These registers indicate the current timer position.
|
||||
*/
|
||||
typedef union _hw_pit_cvaln
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_pit_cvaln_bitfields
|
||||
{
|
||||
uint32_t TVL : 32; /*!< [31:0] Current Timer Value */
|
||||
} B;
|
||||
} hw_pit_cvaln_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PIT_CVALn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PIT_CVALn_COUNT (4U)
|
||||
|
||||
#define HW_PIT_CVALn_ADDR(x, n) ((x) + 0x104U + (0x10U * (n)))
|
||||
|
||||
#define HW_PIT_CVALn(x, n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n))
|
||||
#define HW_PIT_CVALn_RD(x, n) (HW_PIT_CVALn(x, n).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PIT_CVALn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_CVALn, field TVL[31:0] (RO)
|
||||
*
|
||||
* Represents the current timer value, if the timer is enabled. If the timer is
|
||||
* disabled, do not use this field as its value is unreliable. The timer uses a
|
||||
* downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_CVALn_TVL (0U) /*!< Bit position for PIT_CVALn_TVL. */
|
||||
#define BM_PIT_CVALn_TVL (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */
|
||||
#define BS_PIT_CVALn_TVL (32U) /*!< Bit field size in bits for PIT_CVALn_TVL. */
|
||||
|
||||
/*! @brief Read current value of the PIT_CVALn_TVL field. */
|
||||
#define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U)
|
||||
/*@}*/
|
||||
/*******************************************************************************
|
||||
* HW_PIT_TCTRLn - Timer Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PIT_TCTRLn - Timer Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* These registers contain the control bits for each timer.
|
||||
*/
|
||||
typedef union _hw_pit_tctrln
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_pit_tctrln_bitfields
|
||||
{
|
||||
uint32_t TEN : 1; /*!< [0] Timer Enable */
|
||||
uint32_t TIE : 1; /*!< [1] Timer Interrupt Enable */
|
||||
uint32_t CHN : 1; /*!< [2] Chain Mode */
|
||||
uint32_t RESERVED0 : 29; /*!< [31:3] */
|
||||
} B;
|
||||
} hw_pit_tctrln_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PIT_TCTRLn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PIT_TCTRLn_COUNT (4U)
|
||||
|
||||
#define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n)))
|
||||
|
||||
#define HW_PIT_TCTRLn(x, n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n))
|
||||
#define HW_PIT_TCTRLn_RD(x, n) (HW_PIT_TCTRLn(x, n).U)
|
||||
#define HW_PIT_TCTRLn_WR(x, n, v) (HW_PIT_TCTRLn(x, n).U = (v))
|
||||
#define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) | (v)))
|
||||
#define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v)))
|
||||
#define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PIT_TCTRLn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_TCTRLn, field TEN[0] (RW)
|
||||
*
|
||||
* Enables or disables the timer.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Timer n is disabled.
|
||||
* - 1 - Timer n is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_TCTRLn_TEN (0U) /*!< Bit position for PIT_TCTRLn_TEN. */
|
||||
#define BM_PIT_TCTRLn_TEN (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */
|
||||
#define BS_PIT_TCTRLn_TEN (1U) /*!< Bit field size in bits for PIT_TCTRLn_TEN. */
|
||||
|
||||
/*! @brief Read current value of the PIT_TCTRLn_TEN field. */
|
||||
#define BR_PIT_TCTRLn_TEN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN))
|
||||
|
||||
/*! @brief Format value for bitfield PIT_TCTRLn_TEN. */
|
||||
#define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN)
|
||||
|
||||
/*! @brief Set the TEN field to a new value. */
|
||||
#define BW_PIT_TCTRLn_TEN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_TCTRLn, field TIE[1] (RW)
|
||||
*
|
||||
* When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
|
||||
* will immediately cause an interrupt event. To avoid this, the associated
|
||||
* TFLGn[TIF] must be cleared first.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Interrupt requests from Timer n are disabled.
|
||||
* - 1 - Interrupt will be requested whenever TIF is set.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_TCTRLn_TIE (1U) /*!< Bit position for PIT_TCTRLn_TIE. */
|
||||
#define BM_PIT_TCTRLn_TIE (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */
|
||||
#define BS_PIT_TCTRLn_TIE (1U) /*!< Bit field size in bits for PIT_TCTRLn_TIE. */
|
||||
|
||||
/*! @brief Read current value of the PIT_TCTRLn_TIE field. */
|
||||
#define BR_PIT_TCTRLn_TIE(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE))
|
||||
|
||||
/*! @brief Format value for bitfield PIT_TCTRLn_TIE. */
|
||||
#define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE)
|
||||
|
||||
/*! @brief Set the TIE field to a new value. */
|
||||
#define BW_PIT_TCTRLn_TIE(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_TCTRLn, field CHN[2] (RW)
|
||||
*
|
||||
* When activated, Timer n-1 needs to expire before timer n can decrement by 1.
|
||||
* Timer 0 cannot be chained.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Timer is not chained.
|
||||
* - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
|
||||
* field is set, Timer 2 is chained to Timer 1.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_TCTRLn_CHN (2U) /*!< Bit position for PIT_TCTRLn_CHN. */
|
||||
#define BM_PIT_TCTRLn_CHN (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */
|
||||
#define BS_PIT_TCTRLn_CHN (1U) /*!< Bit field size in bits for PIT_TCTRLn_CHN. */
|
||||
|
||||
/*! @brief Read current value of the PIT_TCTRLn_CHN field. */
|
||||
#define BR_PIT_TCTRLn_CHN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN))
|
||||
|
||||
/*! @brief Format value for bitfield PIT_TCTRLn_CHN. */
|
||||
#define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN)
|
||||
|
||||
/*! @brief Set the CHN field to a new value. */
|
||||
#define BW_PIT_TCTRLn_CHN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN) = (v))
|
||||
/*@}*/
|
||||
/*******************************************************************************
|
||||
* HW_PIT_TFLGn - Timer Flag Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PIT_TFLGn - Timer Flag Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* These registers hold the PIT interrupt flags.
|
||||
*/
|
||||
typedef union _hw_pit_tflgn
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_pit_tflgn_bitfields
|
||||
{
|
||||
uint32_t TIF : 1; /*!< [0] Timer Interrupt Flag */
|
||||
uint32_t RESERVED0 : 31; /*!< [31:1] */
|
||||
} B;
|
||||
} hw_pit_tflgn_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PIT_TFLGn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PIT_TFLGn_COUNT (4U)
|
||||
|
||||
#define HW_PIT_TFLGn_ADDR(x, n) ((x) + 0x10CU + (0x10U * (n)))
|
||||
|
||||
#define HW_PIT_TFLGn(x, n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n))
|
||||
#define HW_PIT_TFLGn_RD(x, n) (HW_PIT_TFLGn(x, n).U)
|
||||
#define HW_PIT_TFLGn_WR(x, n, v) (HW_PIT_TFLGn(x, n).U = (v))
|
||||
#define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) | (v)))
|
||||
#define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v)))
|
||||
#define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PIT_TFLGn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PIT_TFLGn, field TIF[0] (W1C)
|
||||
*
|
||||
* Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
|
||||
* Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
|
||||
* interrupt request.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Timeout has not yet occurred.
|
||||
* - 1 - Timeout has occurred.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PIT_TFLGn_TIF (0U) /*!< Bit position for PIT_TFLGn_TIF. */
|
||||
#define BM_PIT_TFLGn_TIF (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */
|
||||
#define BS_PIT_TFLGn_TIF (1U) /*!< Bit field size in bits for PIT_TFLGn_TIF. */
|
||||
|
||||
/*! @brief Read current value of the PIT_TFLGn_TIF field. */
|
||||
#define BR_PIT_TFLGn_TIF(x, n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF))
|
||||
|
||||
/*! @brief Format value for bitfield PIT_TFLGn_TIF. */
|
||||
#define BF_PIT_TFLGn_TIF(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF)
|
||||
|
||||
/*! @brief Set the TIF field to a new value. */
|
||||
#define BW_PIT_TFLGn_TIF(x, n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_pit_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All PIT module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_pit
|
||||
{
|
||||
__IO hw_pit_mcr_t MCR; /*!< [0x0] PIT Module Control Register */
|
||||
uint8_t _reserved0[252];
|
||||
struct {
|
||||
__IO hw_pit_ldvaln_t LDVALn; /*!< [0x100] Timer Load Value Register */
|
||||
__I hw_pit_cvaln_t CVALn; /*!< [0x104] Current Timer Value Register */
|
||||
__IO hw_pit_tctrln_t TCTRLn; /*!< [0x108] Timer Control Register */
|
||||
__IO hw_pit_tflgn_t TFLGn; /*!< [0x10C] Timer Flag Register */
|
||||
} CHANNEL[4];
|
||||
} hw_pit_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all PIT registers. */
|
||||
/*! @param x PIT module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_PIT(PIT_BASE)</code>. */
|
||||
#define HW_PIT(x) (*(hw_pit_t *)(x))
|
||||
|
||||
#endif /* __HW_PIT_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
|
|
@ -0,0 +1,561 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_PMC_REGISTERS_H__
|
||||
#define __HW_PMC_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 PMC
|
||||
*
|
||||
* Power Management Controller
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
|
||||
* - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
|
||||
* - HW_PMC_REGSC - Regulator Status And Control register
|
||||
*
|
||||
* - hw_pmc_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
|
||||
*
|
||||
* Reset value: 0x10U
|
||||
*
|
||||
* This register contains status and control bits to support the low voltage
|
||||
* detect function. This register should be written during the reset initialization
|
||||
* program to set the desired controls even if the desired settings are the same
|
||||
* as the reset settings. While the device is in the very low power or low
|
||||
* leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
|
||||
* systems that must have LVD always on, configure the Power Mode Protection
|
||||
* (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
|
||||
* low leakage modes from being enabled. See the device's data sheet for the
|
||||
* exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
|
||||
* register's other bits are reset on Chip Reset Not VLLS. For more information
|
||||
* about these reset types, refer to the Reset section details.
|
||||
*/
|
||||
typedef union _hw_pmc_lvdsc1
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_pmc_lvdsc1_bitfields
|
||||
{
|
||||
uint8_t LVDV : 2; /*!< [1:0] Low-Voltage Detect Voltage Select */
|
||||
uint8_t RESERVED0 : 2; /*!< [3:2] */
|
||||
uint8_t LVDRE : 1; /*!< [4] Low-Voltage Detect Reset Enable */
|
||||
uint8_t LVDIE : 1; /*!< [5] Low-Voltage Detect Interrupt Enable */
|
||||
uint8_t LVDACK : 1; /*!< [6] Low-Voltage Detect Acknowledge */
|
||||
uint8_t LVDF : 1; /*!< [7] Low-Voltage Detect Flag */
|
||||
} B;
|
||||
} hw_pmc_lvdsc1_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PMC_LVDSC1 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PMC_LVDSC1_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_PMC_LVDSC1(x) (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
|
||||
#define HW_PMC_LVDSC1_RD(x) (HW_PMC_LVDSC1(x).U)
|
||||
#define HW_PMC_LVDSC1_WR(x, v) (HW_PMC_LVDSC1(x).U = (v))
|
||||
#define HW_PMC_LVDSC1_SET(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) | (v)))
|
||||
#define HW_PMC_LVDSC1_CLR(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
|
||||
#define HW_PMC_LVDSC1_TOG(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PMC_LVDSC1 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
|
||||
*
|
||||
* Selects the LVD trip point voltage (V LVD ).
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Low trip point selected (V LVD = V LVDL )
|
||||
* - 01 - High trip point selected (V LVD = V LVDH )
|
||||
* - 10 - Reserved
|
||||
* - 11 - Reserved
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC1_LVDV (0U) /*!< Bit position for PMC_LVDSC1_LVDV. */
|
||||
#define BM_PMC_LVDSC1_LVDV (0x03U) /*!< Bit mask for PMC_LVDSC1_LVDV. */
|
||||
#define BS_PMC_LVDSC1_LVDV (2U) /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
|
||||
|
||||
/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
|
||||
#define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
|
||||
|
||||
/*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
|
||||
#define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
|
||||
|
||||
/*! @brief Set the LVDV field to a new value. */
|
||||
#define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC1, field LVDRE[4] (RW)
|
||||
*
|
||||
* This write-once bit enables LVDF events to generate a hardware reset.
|
||||
* Additional writes are ignored.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - LVDF does not generate hardware resets
|
||||
* - 1 - Force an MCU reset when LVDF = 1
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC1_LVDRE (4U) /*!< Bit position for PMC_LVDSC1_LVDRE. */
|
||||
#define BM_PMC_LVDSC1_LVDRE (0x10U) /*!< Bit mask for PMC_LVDSC1_LVDRE. */
|
||||
#define BS_PMC_LVDSC1_LVDRE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
|
||||
|
||||
/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
|
||||
#define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
|
||||
|
||||
/*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
|
||||
#define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
|
||||
|
||||
/*! @brief Set the LVDRE field to a new value. */
|
||||
#define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC1, field LVDIE[5] (RW)
|
||||
*
|
||||
* Enables hardware interrupt requests for LVDF.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Hardware interrupt disabled (use polling)
|
||||
* - 1 - Request a hardware interrupt when LVDF = 1
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC1_LVDIE (5U) /*!< Bit position for PMC_LVDSC1_LVDIE. */
|
||||
#define BM_PMC_LVDSC1_LVDIE (0x20U) /*!< Bit mask for PMC_LVDSC1_LVDIE. */
|
||||
#define BS_PMC_LVDSC1_LVDIE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
|
||||
|
||||
/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
|
||||
#define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
|
||||
|
||||
/*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
|
||||
#define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
|
||||
|
||||
/*! @brief Set the LVDIE field to a new value. */
|
||||
#define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
|
||||
*
|
||||
* This write-only field is used to acknowledge low voltage detection errors.
|
||||
* Write 1 to clear LVDF. Reads always return 0.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC1_LVDACK (6U) /*!< Bit position for PMC_LVDSC1_LVDACK. */
|
||||
#define BM_PMC_LVDSC1_LVDACK (0x40U) /*!< Bit mask for PMC_LVDSC1_LVDACK. */
|
||||
#define BS_PMC_LVDSC1_LVDACK (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
|
||||
|
||||
/*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
|
||||
#define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
|
||||
|
||||
/*! @brief Set the LVDACK field to a new value. */
|
||||
#define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC1, field LVDF[7] (RO)
|
||||
*
|
||||
* This read-only status field indicates a low-voltage detect event.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Low-voltage event not detected
|
||||
* - 1 - Low-voltage event detected
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC1_LVDF (7U) /*!< Bit position for PMC_LVDSC1_LVDF. */
|
||||
#define BM_PMC_LVDSC1_LVDF (0x80U) /*!< Bit mask for PMC_LVDSC1_LVDF. */
|
||||
#define BS_PMC_LVDSC1_LVDF (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
|
||||
|
||||
/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
|
||||
#define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* This register contains status and control bits to support the low voltage
|
||||
* warning function. While the device is in the very low power or low leakage modes,
|
||||
* the LVD system is disabled regardless of LVDSC2 settings. See the device's
|
||||
* data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
|
||||
* and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
|
||||
* register are reset on Chip Reset Not VLLS. For more information about these
|
||||
* reset types, refer to the Reset section details.
|
||||
*/
|
||||
typedef union _hw_pmc_lvdsc2
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_pmc_lvdsc2_bitfields
|
||||
{
|
||||
uint8_t LVWV : 2; /*!< [1:0] Low-Voltage Warning Voltage Select */
|
||||
uint8_t RESERVED0 : 3; /*!< [4:2] */
|
||||
uint8_t LVWIE : 1; /*!< [5] Low-Voltage Warning Interrupt Enable */
|
||||
uint8_t LVWACK : 1; /*!< [6] Low-Voltage Warning Acknowledge */
|
||||
uint8_t LVWF : 1; /*!< [7] Low-Voltage Warning Flag */
|
||||
} B;
|
||||
} hw_pmc_lvdsc2_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PMC_LVDSC2 register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PMC_LVDSC2_ADDR(x) ((x) + 0x1U)
|
||||
|
||||
#define HW_PMC_LVDSC2(x) (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
|
||||
#define HW_PMC_LVDSC2_RD(x) (HW_PMC_LVDSC2(x).U)
|
||||
#define HW_PMC_LVDSC2_WR(x, v) (HW_PMC_LVDSC2(x).U = (v))
|
||||
#define HW_PMC_LVDSC2_SET(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) | (v)))
|
||||
#define HW_PMC_LVDSC2_CLR(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
|
||||
#define HW_PMC_LVDSC2_TOG(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PMC_LVDSC2 bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
|
||||
*
|
||||
* Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
|
||||
* depends on LVDSC1[LVDV].
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Low trip point selected (VLVW = VLVW1)
|
||||
* - 01 - Mid 1 trip point selected (VLVW = VLVW2)
|
||||
* - 10 - Mid 2 trip point selected (VLVW = VLVW3)
|
||||
* - 11 - High trip point selected (VLVW = VLVW4)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC2_LVWV (0U) /*!< Bit position for PMC_LVDSC2_LVWV. */
|
||||
#define BM_PMC_LVDSC2_LVWV (0x03U) /*!< Bit mask for PMC_LVDSC2_LVWV. */
|
||||
#define BS_PMC_LVDSC2_LVWV (2U) /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
|
||||
|
||||
/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
|
||||
#define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
|
||||
|
||||
/*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
|
||||
#define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
|
||||
|
||||
/*! @brief Set the LVWV field to a new value. */
|
||||
#define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC2, field LVWIE[5] (RW)
|
||||
*
|
||||
* Enables hardware interrupt requests for LVWF.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Hardware interrupt disabled (use polling)
|
||||
* - 1 - Request a hardware interrupt when LVWF = 1
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC2_LVWIE (5U) /*!< Bit position for PMC_LVDSC2_LVWIE. */
|
||||
#define BM_PMC_LVDSC2_LVWIE (0x20U) /*!< Bit mask for PMC_LVDSC2_LVWIE. */
|
||||
#define BS_PMC_LVDSC2_LVWIE (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
|
||||
|
||||
/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
|
||||
#define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
|
||||
|
||||
/*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
|
||||
#define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
|
||||
|
||||
/*! @brief Set the LVWIE field to a new value. */
|
||||
#define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
|
||||
*
|
||||
* This write-only field is used to acknowledge low voltage warning errors.
|
||||
* Write 1 to clear LVWF. Reads always return 0.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC2_LVWACK (6U) /*!< Bit position for PMC_LVDSC2_LVWACK. */
|
||||
#define BM_PMC_LVDSC2_LVWACK (0x40U) /*!< Bit mask for PMC_LVDSC2_LVWACK. */
|
||||
#define BS_PMC_LVDSC2_LVWACK (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
|
||||
|
||||
/*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
|
||||
#define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
|
||||
|
||||
/*! @brief Set the LVWACK field to a new value. */
|
||||
#define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_LVDSC2, field LVWF[7] (RO)
|
||||
*
|
||||
* This read-only status field indicates a low-voltage warning event. LVWF is
|
||||
* set when VSupply transitions below the trip point, or after reset and VSupply is
|
||||
* already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
|
||||
* interrupt function, before enabling LVWIE, LVWF must be cleared by writing
|
||||
* LVWACK first.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Low-voltage warning event not detected
|
||||
* - 1 - Low-voltage warning event detected
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_LVDSC2_LVWF (7U) /*!< Bit position for PMC_LVDSC2_LVWF. */
|
||||
#define BM_PMC_LVDSC2_LVWF (0x80U) /*!< Bit mask for PMC_LVDSC2_LVWF. */
|
||||
#define BS_PMC_LVDSC2_LVWF (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
|
||||
|
||||
/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
|
||||
#define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PMC_REGSC - Regulator Status And Control register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
|
||||
*
|
||||
* Reset value: 0x04U
|
||||
*
|
||||
* The PMC contains an internal voltage regulator. The voltage regulator design
|
||||
* uses a bandgap reference that is also available through a buffer as input to
|
||||
* certain internal peripherals, such as the CMP and ADC. The internal regulator
|
||||
* provides a status bit (REGONS) indicating the regulator is in run regulation.
|
||||
* This register is reset on Chip Reset Not VLLS and by reset types that trigger
|
||||
* Chip Reset not VLLS. See the Reset section details for more information.
|
||||
*/
|
||||
typedef union _hw_pmc_regsc
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_pmc_regsc_bitfields
|
||||
{
|
||||
uint8_t BGBE : 1; /*!< [0] Bandgap Buffer Enable */
|
||||
uint8_t RESERVED0 : 1; /*!< [1] */
|
||||
uint8_t REGONS : 1; /*!< [2] Regulator In Run Regulation Status */
|
||||
uint8_t ACKISO : 1; /*!< [3] Acknowledge Isolation */
|
||||
uint8_t BGEN : 1; /*!< [4] Bandgap Enable In VLPx Operation */
|
||||
uint8_t RESERVED1 : 3; /*!< [7:5] */
|
||||
} B;
|
||||
} hw_pmc_regsc_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PMC_REGSC register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PMC_REGSC_ADDR(x) ((x) + 0x2U)
|
||||
|
||||
#define HW_PMC_REGSC(x) (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
|
||||
#define HW_PMC_REGSC_RD(x) (HW_PMC_REGSC(x).U)
|
||||
#define HW_PMC_REGSC_WR(x, v) (HW_PMC_REGSC(x).U = (v))
|
||||
#define HW_PMC_REGSC_SET(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) | (v)))
|
||||
#define HW_PMC_REGSC_CLR(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
|
||||
#define HW_PMC_REGSC_TOG(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PMC_REGSC bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_REGSC, field BGBE[0] (RW)
|
||||
*
|
||||
* Enables the bandgap buffer.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Bandgap buffer not enabled
|
||||
* - 1 - Bandgap buffer enabled
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_REGSC_BGBE (0U) /*!< Bit position for PMC_REGSC_BGBE. */
|
||||
#define BM_PMC_REGSC_BGBE (0x01U) /*!< Bit mask for PMC_REGSC_BGBE. */
|
||||
#define BS_PMC_REGSC_BGBE (1U) /*!< Bit field size in bits for PMC_REGSC_BGBE. */
|
||||
|
||||
/*! @brief Read current value of the PMC_REGSC_BGBE field. */
|
||||
#define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
|
||||
|
||||
/*! @brief Format value for bitfield PMC_REGSC_BGBE. */
|
||||
#define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
|
||||
|
||||
/*! @brief Set the BGBE field to a new value. */
|
||||
#define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_REGSC, field REGONS[2] (RO)
|
||||
*
|
||||
* This read-only field provides the current status of the internal voltage
|
||||
* regulator.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Regulator is in stop regulation or in transition to/from it
|
||||
* - 1 - Regulator is in run regulation
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_REGSC_REGONS (2U) /*!< Bit position for PMC_REGSC_REGONS. */
|
||||
#define BM_PMC_REGSC_REGONS (0x04U) /*!< Bit mask for PMC_REGSC_REGONS. */
|
||||
#define BS_PMC_REGSC_REGONS (1U) /*!< Bit field size in bits for PMC_REGSC_REGONS. */
|
||||
|
||||
/*! @brief Read current value of the PMC_REGSC_REGONS field. */
|
||||
#define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_REGSC, field ACKISO[3] (W1C)
|
||||
*
|
||||
* Reading this field indicates whether certain peripherals and the I/O pads are
|
||||
* in a latched state as a result of having been in a VLLS mode. Writing 1 to
|
||||
* this field when it is set releases the I/O pads and certain peripherals to their
|
||||
* normal run mode state. After recovering from a VLLS mode, user should restore
|
||||
* chip configuration before clearing ACKISO. In particular, pin configuration
|
||||
* for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
|
||||
* being falsely set when ACKISO is cleared.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Peripherals and I/O pads are in normal run state.
|
||||
* - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_REGSC_ACKISO (3U) /*!< Bit position for PMC_REGSC_ACKISO. */
|
||||
#define BM_PMC_REGSC_ACKISO (0x08U) /*!< Bit mask for PMC_REGSC_ACKISO. */
|
||||
#define BS_PMC_REGSC_ACKISO (1U) /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
|
||||
|
||||
/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
|
||||
#define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
|
||||
|
||||
/*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
|
||||
#define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
|
||||
|
||||
/*! @brief Set the ACKISO field to a new value. */
|
||||
#define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PMC_REGSC, field BGEN[4] (RW)
|
||||
*
|
||||
* BGEN controls whether the bandgap is enabled in lower power modes of
|
||||
* operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
|
||||
* reference in low power modes of operation, set BGEN to continue to enable the
|
||||
* bandgap operation. When the bandgap voltage reference is not needed in low
|
||||
* power modes, clear BGEN to avoid excess power consumption.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
|
||||
* - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PMC_REGSC_BGEN (4U) /*!< Bit position for PMC_REGSC_BGEN. */
|
||||
#define BM_PMC_REGSC_BGEN (0x10U) /*!< Bit mask for PMC_REGSC_BGEN. */
|
||||
#define BS_PMC_REGSC_BGEN (1U) /*!< Bit field size in bits for PMC_REGSC_BGEN. */
|
||||
|
||||
/*! @brief Read current value of the PMC_REGSC_BGEN field. */
|
||||
#define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
|
||||
|
||||
/*! @brief Format value for bitfield PMC_REGSC_BGEN. */
|
||||
#define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
|
||||
|
||||
/*! @brief Set the BGEN field to a new value. */
|
||||
#define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_pmc_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All PMC module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_pmc
|
||||
{
|
||||
__IO hw_pmc_lvdsc1_t LVDSC1; /*!< [0x0] Low Voltage Detect Status And Control 1 register */
|
||||
__IO hw_pmc_lvdsc2_t LVDSC2; /*!< [0x1] Low Voltage Detect Status And Control 2 register */
|
||||
__IO hw_pmc_regsc_t REGSC; /*!< [0x2] Regulator Status And Control register */
|
||||
} hw_pmc_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all PMC registers. */
|
||||
/*! @param x PMC module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
|
||||
#define HW_PMC(x) (*(hw_pmc_t *)(x))
|
||||
|
||||
#endif /* __HW_PMC_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
|
|
@ -0,0 +1,881 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_PORT_REGISTERS_H__
|
||||
#define __HW_PORT_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 PORT
|
||||
*
|
||||
* Pin Control and Interrupts
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_PORT_PCRn - Pin Control Register n
|
||||
* - HW_PORT_GPCLR - Global Pin Control Low Register
|
||||
* - HW_PORT_GPCHR - Global Pin Control High Register
|
||||
* - HW_PORT_ISFR - Interrupt Status Flag Register
|
||||
* - HW_PORT_DFER - Digital Filter Enable Register
|
||||
* - HW_PORT_DFCR - Digital Filter Clock Register
|
||||
* - HW_PORT_DFWR - Digital Filter Width Register
|
||||
*
|
||||
* - hw_port_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
|
||||
#define HW_PORTA (0U) /*!< Instance number for PORTA. */
|
||||
#define HW_PORTB (1U) /*!< Instance number for PORTB. */
|
||||
#define HW_PORTC (2U) /*!< Instance number for PORTC. */
|
||||
#define HW_PORTD (3U) /*!< Instance number for PORTD. */
|
||||
#define HW_PORTE (4U) /*!< Instance number for PORTE. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PORT_PCRn - Pin Control Register n
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PORT_PCRn - Pin Control Register n (RW)
|
||||
*
|
||||
* Reset value: 0x00000702U
|
||||
*
|
||||
* See the Signal Multiplexing and Pin Assignment chapter for the reset value of
|
||||
* this device. See the GPIO Configuration section for details on the available
|
||||
* functions for each pin. Do not modify pin configuration registers associated
|
||||
* with pins not available in your selected package. All unbonded pins not
|
||||
* available in your package will default to DISABLE state for lowest power consumption.
|
||||
*/
|
||||
typedef union _hw_port_pcrn
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_port_pcrn_bitfields
|
||||
{
|
||||
uint32_t PS : 1; /*!< [0] Pull Select */
|
||||
uint32_t PE : 1; /*!< [1] Pull Enable */
|
||||
uint32_t SRE : 1; /*!< [2] Slew Rate Enable */
|
||||
uint32_t RESERVED0 : 1; /*!< [3] */
|
||||
uint32_t PFE : 1; /*!< [4] Passive Filter Enable */
|
||||
uint32_t ODE : 1; /*!< [5] Open Drain Enable */
|
||||
uint32_t DSE : 1; /*!< [6] Drive Strength Enable */
|
||||
uint32_t RESERVED1 : 1; /*!< [7] */
|
||||
uint32_t MUX : 3; /*!< [10:8] Pin Mux Control */
|
||||
uint32_t RESERVED2 : 4; /*!< [14:11] */
|
||||
uint32_t LK : 1; /*!< [15] Lock Register */
|
||||
uint32_t IRQC : 4; /*!< [19:16] Interrupt Configuration */
|
||||
uint32_t RESERVED3 : 4; /*!< [23:20] */
|
||||
uint32_t ISF : 1; /*!< [24] Interrupt Status Flag */
|
||||
uint32_t RESERVED4 : 7; /*!< [31:25] */
|
||||
} B;
|
||||
} hw_port_pcrn_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PORT_PCRn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PORT_PCRn_COUNT (32U)
|
||||
|
||||
#define HW_PORT_PCRn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
|
||||
|
||||
#define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
|
||||
#define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
|
||||
#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
|
||||
#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
|
||||
#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
|
||||
#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PORT_PCRn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field PS[0] (RW)
|
||||
*
|
||||
* Pull configuration is valid in all digital pin muxing modes.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
|
||||
* corresponding PE field is set.
|
||||
* - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
|
||||
* corresponding PE field is set.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_PS (0U) /*!< Bit position for PORT_PCRn_PS. */
|
||||
#define BM_PORT_PCRn_PS (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
|
||||
#define BS_PORT_PCRn_PS (1U) /*!< Bit field size in bits for PORT_PCRn_PS. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_PS field. */
|
||||
#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_PS. */
|
||||
#define BF_PORT_PCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
|
||||
|
||||
/*! @brief Set the PS field to a new value. */
|
||||
#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field PE[1] (RW)
|
||||
*
|
||||
* Pull configuration is valid in all digital pin muxing modes.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Internal pullup or pulldown resistor is not enabled on the
|
||||
* corresponding pin.
|
||||
* - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
|
||||
* pin, if the pin is configured as a digital input.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_PE (1U) /*!< Bit position for PORT_PCRn_PE. */
|
||||
#define BM_PORT_PCRn_PE (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
|
||||
#define BS_PORT_PCRn_PE (1U) /*!< Bit field size in bits for PORT_PCRn_PE. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_PE field. */
|
||||
#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_PE. */
|
||||
#define BF_PORT_PCRn_PE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
|
||||
|
||||
/*! @brief Set the PE field to a new value. */
|
||||
#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field SRE[2] (RW)
|
||||
*
|
||||
* Slew rate configuration is valid in all digital pin muxing modes.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
|
||||
* configured as a digital output.
|
||||
* - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
|
||||
* configured as a digital output.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_SRE (2U) /*!< Bit position for PORT_PCRn_SRE. */
|
||||
#define BM_PORT_PCRn_SRE (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
|
||||
#define BS_PORT_PCRn_SRE (1U) /*!< Bit field size in bits for PORT_PCRn_SRE. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_SRE field. */
|
||||
#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_SRE. */
|
||||
#define BF_PORT_PCRn_SRE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
|
||||
|
||||
/*! @brief Set the SRE field to a new value. */
|
||||
#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field PFE[4] (RW)
|
||||
*
|
||||
* Passive filter configuration is valid in all digital pin muxing modes.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Passive input filter is disabled on the corresponding pin.
|
||||
* - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
|
||||
* configured as a digital input. Refer to the device data sheet for filter
|
||||
* characteristics.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_PFE (4U) /*!< Bit position for PORT_PCRn_PFE. */
|
||||
#define BM_PORT_PCRn_PFE (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
|
||||
#define BS_PORT_PCRn_PFE (1U) /*!< Bit field size in bits for PORT_PCRn_PFE. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_PFE field. */
|
||||
#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_PFE. */
|
||||
#define BF_PORT_PCRn_PFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
|
||||
|
||||
/*! @brief Set the PFE field to a new value. */
|
||||
#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field ODE[5] (RW)
|
||||
*
|
||||
* Open drain configuration is valid in all digital pin muxing modes.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Open drain output is disabled on the corresponding pin.
|
||||
* - 1 - Open drain output is enabled on the corresponding pin, if the pin is
|
||||
* configured as a digital output.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_ODE (5U) /*!< Bit position for PORT_PCRn_ODE. */
|
||||
#define BM_PORT_PCRn_ODE (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
|
||||
#define BS_PORT_PCRn_ODE (1U) /*!< Bit field size in bits for PORT_PCRn_ODE. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_ODE field. */
|
||||
#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_ODE. */
|
||||
#define BF_PORT_PCRn_ODE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
|
||||
|
||||
/*! @brief Set the ODE field to a new value. */
|
||||
#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field DSE[6] (RW)
|
||||
*
|
||||
* Drive strength configuration is valid in all digital pin muxing modes.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Low drive strength is configured on the corresponding pin, if pin is
|
||||
* configured as a digital output.
|
||||
* - 1 - High drive strength is configured on the corresponding pin, if pin is
|
||||
* configured as a digital output.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_DSE (6U) /*!< Bit position for PORT_PCRn_DSE. */
|
||||
#define BM_PORT_PCRn_DSE (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
|
||||
#define BS_PORT_PCRn_DSE (1U) /*!< Bit field size in bits for PORT_PCRn_DSE. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_DSE field. */
|
||||
#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_DSE. */
|
||||
#define BF_PORT_PCRn_DSE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
|
||||
|
||||
/*! @brief Set the DSE field to a new value. */
|
||||
#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field MUX[10:8] (RW)
|
||||
*
|
||||
* Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
|
||||
* reserved and may result in configuring the pin for a different pin muxing
|
||||
* slot. The corresponding pin is configured in the following pin muxing slot as
|
||||
* follows:
|
||||
*
|
||||
* Values:
|
||||
* - 000 - Pin disabled (analog).
|
||||
* - 001 - Alternative 1 (GPIO).
|
||||
* - 010 - Alternative 2 (chip-specific).
|
||||
* - 011 - Alternative 3 (chip-specific).
|
||||
* - 100 - Alternative 4 (chip-specific).
|
||||
* - 101 - Alternative 5 (chip-specific).
|
||||
* - 110 - Alternative 6 (chip-specific).
|
||||
* - 111 - Alternative 7 (chip-specific).
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_MUX (8U) /*!< Bit position for PORT_PCRn_MUX. */
|
||||
#define BM_PORT_PCRn_MUX (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
|
||||
#define BS_PORT_PCRn_MUX (3U) /*!< Bit field size in bits for PORT_PCRn_MUX. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_MUX field. */
|
||||
#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_MUX. */
|
||||
#define BF_PORT_PCRn_MUX(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
|
||||
|
||||
/*! @brief Set the MUX field to a new value. */
|
||||
#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field LK[15] (RW)
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Pin Control Register fields [15:0] are not locked.
|
||||
* - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
|
||||
* until the next system reset.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_LK (15U) /*!< Bit position for PORT_PCRn_LK. */
|
||||
#define BM_PORT_PCRn_LK (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
|
||||
#define BS_PORT_PCRn_LK (1U) /*!< Bit field size in bits for PORT_PCRn_LK. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_LK field. */
|
||||
#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_LK. */
|
||||
#define BF_PORT_PCRn_LK(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
|
||||
|
||||
/*! @brief Set the LK field to a new value. */
|
||||
#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field IRQC[19:16] (RW)
|
||||
*
|
||||
* The pin interrupt configuration is valid in all digital pin muxing modes. The
|
||||
* corresponding pin is configured to generate interrupt/DMA request as follows:
|
||||
*
|
||||
* Values:
|
||||
* - 0000 - Interrupt/DMA request disabled.
|
||||
* - 0001 - DMA request on rising edge.
|
||||
* - 0010 - DMA request on falling edge.
|
||||
* - 0011 - DMA request on either edge.
|
||||
* - 1000 - Interrupt when logic 0.
|
||||
* - 1001 - Interrupt on rising-edge.
|
||||
* - 1010 - Interrupt on falling-edge.
|
||||
* - 1011 - Interrupt on either edge.
|
||||
* - 1100 - Interrupt when logic 1.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_IRQC (16U) /*!< Bit position for PORT_PCRn_IRQC. */
|
||||
#define BM_PORT_PCRn_IRQC (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
|
||||
#define BS_PORT_PCRn_IRQC (4U) /*!< Bit field size in bits for PORT_PCRn_IRQC. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_IRQC field. */
|
||||
#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_IRQC. */
|
||||
#define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
|
||||
|
||||
/*! @brief Set the IRQC field to a new value. */
|
||||
#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_PCRn, field ISF[24] (W1C)
|
||||
*
|
||||
* The pin interrupt configuration is valid in all digital pin muxing modes.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Configured interrupt is not detected.
|
||||
* - 1 - Configured interrupt is detected. If the pin is configured to generate
|
||||
* a DMA request, then the corresponding flag will be cleared automatically
|
||||
* at the completion of the requested DMA transfer. Otherwise, the flag
|
||||
* remains set until a logic 1 is written to the flag. If the pin is configured for
|
||||
* a level sensitive interrupt and the pin remains asserted, then the flag
|
||||
* is set again immediately after it is cleared.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_PCRn_ISF (24U) /*!< Bit position for PORT_PCRn_ISF. */
|
||||
#define BM_PORT_PCRn_ISF (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
|
||||
#define BS_PORT_PCRn_ISF (1U) /*!< Bit field size in bits for PORT_PCRn_ISF. */
|
||||
|
||||
/*! @brief Read current value of the PORT_PCRn_ISF field. */
|
||||
#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_PCRn_ISF. */
|
||||
#define BF_PORT_PCRn_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
|
||||
|
||||
/*! @brief Set the ISF field to a new value. */
|
||||
#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PORT_GPCLR - Global Pin Control Low Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* Only 32-bit writes are supported to this register.
|
||||
*/
|
||||
typedef union _hw_port_gpclr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_port_gpclr_bitfields
|
||||
{
|
||||
uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
|
||||
uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
|
||||
} B;
|
||||
} hw_port_gpclr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PORT_GPCLR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PORT_GPCLR_ADDR(x) ((x) + 0x80U)
|
||||
|
||||
#define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
|
||||
#define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
|
||||
#define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PORT_GPCLR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
|
||||
*
|
||||
* Write value that is written to all Pin Control Registers bits [15:0] that are
|
||||
* selected by GPWE.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_GPCLR_GPWD (0U) /*!< Bit position for PORT_GPCLR_GPWD. */
|
||||
#define BM_PORT_GPCLR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
|
||||
#define BS_PORT_GPCLR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
|
||||
|
||||
/*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
|
||||
#define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
|
||||
|
||||
/*! @brief Set the GPWD field to a new value. */
|
||||
#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
|
||||
*
|
||||
* Selects which Pin Control Registers (15 through 0) bits [15:0] update with
|
||||
* the value in GPWD. If a selected Pin Control Register is locked then the write
|
||||
* to that register is ignored.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Corresponding Pin Control Register is not updated with the value in
|
||||
* GPWD.
|
||||
* - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_GPCLR_GPWE (16U) /*!< Bit position for PORT_GPCLR_GPWE. */
|
||||
#define BM_PORT_GPCLR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
|
||||
#define BS_PORT_GPCLR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
|
||||
|
||||
/*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
|
||||
#define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
|
||||
|
||||
/*! @brief Set the GPWE field to a new value. */
|
||||
#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PORT_GPCHR - Global Pin Control High Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* Only 32-bit writes are supported to this register.
|
||||
*/
|
||||
typedef union _hw_port_gpchr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_port_gpchr_bitfields
|
||||
{
|
||||
uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
|
||||
uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
|
||||
} B;
|
||||
} hw_port_gpchr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PORT_GPCHR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PORT_GPCHR_ADDR(x) ((x) + 0x84U)
|
||||
|
||||
#define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
|
||||
#define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
|
||||
#define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PORT_GPCHR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
|
||||
*
|
||||
* Write value that is written to all Pin Control Registers bits [15:0] that are
|
||||
* selected by GPWE.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_GPCHR_GPWD (0U) /*!< Bit position for PORT_GPCHR_GPWD. */
|
||||
#define BM_PORT_GPCHR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
|
||||
#define BS_PORT_GPCHR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
|
||||
|
||||
/*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
|
||||
#define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
|
||||
|
||||
/*! @brief Set the GPWD field to a new value. */
|
||||
#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
|
||||
*
|
||||
* Selects which Pin Control Registers (31 through 16) bits [15:0] update with
|
||||
* the value in GPWD. If a selected Pin Control Register is locked then the write
|
||||
* to that register is ignored.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Corresponding Pin Control Register is not updated with the value in
|
||||
* GPWD.
|
||||
* - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_GPCHR_GPWE (16U) /*!< Bit position for PORT_GPCHR_GPWE. */
|
||||
#define BM_PORT_GPCHR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
|
||||
#define BS_PORT_GPCHR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
|
||||
|
||||
/*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
|
||||
#define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
|
||||
|
||||
/*! @brief Set the GPWE field to a new value. */
|
||||
#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PORT_ISFR - Interrupt Status Flag Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* The pin interrupt configuration is valid in all digital pin muxing modes. The
|
||||
* Interrupt Status Flag for each pin is also visible in the corresponding Pin
|
||||
* Control Register, and each flag can be cleared in either location.
|
||||
*/
|
||||
typedef union _hw_port_isfr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_port_isfr_bitfields
|
||||
{
|
||||
uint32_t ISF : 32; /*!< [31:0] Interrupt Status Flag */
|
||||
} B;
|
||||
} hw_port_isfr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PORT_ISFR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PORT_ISFR_ADDR(x) ((x) + 0xA0U)
|
||||
|
||||
#define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
|
||||
#define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
|
||||
#define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
|
||||
#define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
|
||||
#define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
|
||||
#define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PORT_ISFR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_ISFR, field ISF[31:0] (W1C)
|
||||
*
|
||||
* Each bit in the field indicates the detection of the configured interrupt of
|
||||
* the same number as the field.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Configured interrupt is not detected.
|
||||
* - 1 - Configured interrupt is detected. If the pin is configured to generate
|
||||
* a DMA request, then the corresponding flag will be cleared automatically
|
||||
* at the completion of the requested DMA transfer. Otherwise, the flag
|
||||
* remains set until a logic 1 is written to the flag. If the pin is configured for
|
||||
* a level sensitive interrupt and the pin remains asserted, then the flag
|
||||
* is set again immediately after it is cleared.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_ISFR_ISF (0U) /*!< Bit position for PORT_ISFR_ISF. */
|
||||
#define BM_PORT_ISFR_ISF (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
|
||||
#define BS_PORT_ISFR_ISF (32U) /*!< Bit field size in bits for PORT_ISFR_ISF. */
|
||||
|
||||
/*! @brief Read current value of the PORT_ISFR_ISF field. */
|
||||
#define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield PORT_ISFR_ISF. */
|
||||
#define BF_PORT_ISFR_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
|
||||
|
||||
/*! @brief Set the ISF field to a new value. */
|
||||
#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PORT_DFER - Digital Filter Enable Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* The corresponding bit is read only for pins that do not support a digital
|
||||
* filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
|
||||
* the pins that support digital filter. The digital filter configuration is valid
|
||||
* in all digital pin muxing modes.
|
||||
*/
|
||||
typedef union _hw_port_dfer
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_port_dfer_bitfields
|
||||
{
|
||||
uint32_t DFE : 32; /*!< [31:0] Digital Filter Enable */
|
||||
} B;
|
||||
} hw_port_dfer_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PORT_DFER register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PORT_DFER_ADDR(x) ((x) + 0xC0U)
|
||||
|
||||
#define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
|
||||
#define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
|
||||
#define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
|
||||
#define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
|
||||
#define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
|
||||
#define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PORT_DFER bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_DFER, field DFE[31:0] (RW)
|
||||
*
|
||||
* The digital filter configuration is valid in all digital pin muxing modes.
|
||||
* The output of each digital filter is reset to zero at system reset and whenever
|
||||
* the digital filter is disabled. Each bit in the field enables the digital
|
||||
* filter of the same number as the field.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Digital filter is disabled on the corresponding pin and output of the
|
||||
* digital filter is reset to zero.
|
||||
* - 1 - Digital filter is enabled on the corresponding pin, if the pin is
|
||||
* configured as a digital input.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_DFER_DFE (0U) /*!< Bit position for PORT_DFER_DFE. */
|
||||
#define BM_PORT_DFER_DFE (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
|
||||
#define BS_PORT_DFER_DFE (32U) /*!< Bit field size in bits for PORT_DFER_DFE. */
|
||||
|
||||
/*! @brief Read current value of the PORT_DFER_DFE field. */
|
||||
#define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
|
||||
|
||||
/*! @brief Format value for bitfield PORT_DFER_DFE. */
|
||||
#define BF_PORT_DFER_DFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
|
||||
|
||||
/*! @brief Set the DFE field to a new value. */
|
||||
#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PORT_DFCR - Digital Filter Clock Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* This register is read only for ports that do not support a digital filter.
|
||||
* The digital filter configuration is valid in all digital pin muxing modes.
|
||||
*/
|
||||
typedef union _hw_port_dfcr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_port_dfcr_bitfields
|
||||
{
|
||||
uint32_t CS : 1; /*!< [0] Clock Source */
|
||||
uint32_t RESERVED0 : 31; /*!< [31:1] */
|
||||
} B;
|
||||
} hw_port_dfcr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PORT_DFCR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PORT_DFCR_ADDR(x) ((x) + 0xC4U)
|
||||
|
||||
#define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
|
||||
#define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
|
||||
#define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
|
||||
#define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
|
||||
#define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
|
||||
#define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PORT_DFCR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_DFCR, field CS[0] (RW)
|
||||
*
|
||||
* The digital filter configuration is valid in all digital pin muxing modes.
|
||||
* Configures the clock source for the digital input filters. Changing the filter
|
||||
* clock source must be done only when all digital filters are disabled.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Digital filters are clocked by the bus clock.
|
||||
* - 1 - Digital filters are clocked by the 1 kHz LPO clock.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_DFCR_CS (0U) /*!< Bit position for PORT_DFCR_CS. */
|
||||
#define BM_PORT_DFCR_CS (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
|
||||
#define BS_PORT_DFCR_CS (1U) /*!< Bit field size in bits for PORT_DFCR_CS. */
|
||||
|
||||
/*! @brief Read current value of the PORT_DFCR_CS field. */
|
||||
#define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
|
||||
|
||||
/*! @brief Format value for bitfield PORT_DFCR_CS. */
|
||||
#define BF_PORT_DFCR_CS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
|
||||
|
||||
/*! @brief Set the CS field to a new value. */
|
||||
#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_PORT_DFWR - Digital Filter Width Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* This register is read only for ports that do not support a digital filter.
|
||||
* The digital filter configuration is valid in all digital pin muxing modes.
|
||||
*/
|
||||
typedef union _hw_port_dfwr
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_port_dfwr_bitfields
|
||||
{
|
||||
uint32_t FILT : 5; /*!< [4:0] Filter Length */
|
||||
uint32_t RESERVED0 : 27; /*!< [31:5] */
|
||||
} B;
|
||||
} hw_port_dfwr_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire PORT_DFWR register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_PORT_DFWR_ADDR(x) ((x) + 0xC8U)
|
||||
|
||||
#define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
|
||||
#define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
|
||||
#define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
|
||||
#define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
|
||||
#define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
|
||||
#define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual PORT_DFWR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register PORT_DFWR, field FILT[4:0] (RW)
|
||||
*
|
||||
* The digital filter configuration is valid in all digital pin muxing modes.
|
||||
* Configures the maximum size of the glitches, in clock cycles, that the digital
|
||||
* filter absorbs for the enabled digital filters. Glitches that are longer than
|
||||
* this register setting will pass through the digital filter, and glitches that
|
||||
* are equal to or less than this register setting are filtered. Changing the
|
||||
* filter length must be done only after all filters are disabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_PORT_DFWR_FILT (0U) /*!< Bit position for PORT_DFWR_FILT. */
|
||||
#define BM_PORT_DFWR_FILT (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
|
||||
#define BS_PORT_DFWR_FILT (5U) /*!< Bit field size in bits for PORT_DFWR_FILT. */
|
||||
|
||||
/*! @brief Read current value of the PORT_DFWR_FILT field. */
|
||||
#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
|
||||
|
||||
/*! @brief Format value for bitfield PORT_DFWR_FILT. */
|
||||
#define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
|
||||
|
||||
/*! @brief Set the FILT field to a new value. */
|
||||
#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_port_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All PORT module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_port
|
||||
{
|
||||
__IO hw_port_pcrn_t PCRn[32]; /*!< [0x0] Pin Control Register n */
|
||||
__O hw_port_gpclr_t GPCLR; /*!< [0x80] Global Pin Control Low Register */
|
||||
__O hw_port_gpchr_t GPCHR; /*!< [0x84] Global Pin Control High Register */
|
||||
uint8_t _reserved0[24];
|
||||
__IO hw_port_isfr_t ISFR; /*!< [0xA0] Interrupt Status Flag Register */
|
||||
uint8_t _reserved1[28];
|
||||
__IO hw_port_dfer_t DFER; /*!< [0xC0] Digital Filter Enable Register */
|
||||
__IO hw_port_dfcr_t DFCR; /*!< [0xC4] Digital Filter Clock Register */
|
||||
__IO hw_port_dfwr_t DFWR; /*!< [0xC8] Digital Filter Width Register */
|
||||
} hw_port_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all PORT registers. */
|
||||
/*! @param x PORT module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
|
||||
#define HW_PORT(x) (*(hw_port_t *)(x))
|
||||
|
||||
#endif /* __HW_PORT_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_RFSYS_REGISTERS_H__
|
||||
#define __HW_RFSYS_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 RFSYS
|
||||
*
|
||||
* System register file
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_RFSYS_REGn - Register file register
|
||||
*
|
||||
* - hw_rfsys_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_RFSYS_REGn - Register file register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_RFSYS_REGn - Register file register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* Each register can be accessed as 8-, 16-, or 32-bits.
|
||||
*/
|
||||
typedef union _hw_rfsys_regn
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_rfsys_regn_bitfields
|
||||
{
|
||||
uint32_t LL : 8; /*!< [7:0] */
|
||||
uint32_t LH : 8; /*!< [15:8] */
|
||||
uint32_t HL : 8; /*!< [23:16] */
|
||||
uint32_t HH : 8; /*!< [31:24] */
|
||||
} B;
|
||||
} hw_rfsys_regn_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire RFSYS_REGn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_RFSYS_REGn_COUNT (8U)
|
||||
|
||||
#define HW_RFSYS_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
|
||||
|
||||
#define HW_RFSYS_REGn(x, n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(x, n))
|
||||
#define HW_RFSYS_REGn_RD(x, n) (HW_RFSYS_REGn(x, n).U)
|
||||
#define HW_RFSYS_REGn_WR(x, n, v) (HW_RFSYS_REGn(x, n).U = (v))
|
||||
#define HW_RFSYS_REGn_SET(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) | (v)))
|
||||
#define HW_RFSYS_REGn_CLR(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) & ~(v)))
|
||||
#define HW_RFSYS_REGn_TOG(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual RFSYS_REGn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field LL[7:0] (RW)
|
||||
*
|
||||
* Low lower byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFSYS_REGn_LL (0U) /*!< Bit position for RFSYS_REGn_LL. */
|
||||
#define BM_RFSYS_REGn_LL (0x000000FFU) /*!< Bit mask for RFSYS_REGn_LL. */
|
||||
#define BS_RFSYS_REGn_LL (8U) /*!< Bit field size in bits for RFSYS_REGn_LL. */
|
||||
|
||||
/*! @brief Read current value of the RFSYS_REGn_LL field. */
|
||||
#define BR_RFSYS_REGn_LL(x, n) (HW_RFSYS_REGn(x, n).B.LL)
|
||||
|
||||
/*! @brief Format value for bitfield RFSYS_REGn_LL. */
|
||||
#define BF_RFSYS_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LL) & BM_RFSYS_REGn_LL)
|
||||
|
||||
/*! @brief Set the LL field to a new value. */
|
||||
#define BW_RFSYS_REGn_LL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field LH[15:8] (RW)
|
||||
*
|
||||
* Low higher byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFSYS_REGn_LH (8U) /*!< Bit position for RFSYS_REGn_LH. */
|
||||
#define BM_RFSYS_REGn_LH (0x0000FF00U) /*!< Bit mask for RFSYS_REGn_LH. */
|
||||
#define BS_RFSYS_REGn_LH (8U) /*!< Bit field size in bits for RFSYS_REGn_LH. */
|
||||
|
||||
/*! @brief Read current value of the RFSYS_REGn_LH field. */
|
||||
#define BR_RFSYS_REGn_LH(x, n) (HW_RFSYS_REGn(x, n).B.LH)
|
||||
|
||||
/*! @brief Format value for bitfield RFSYS_REGn_LH. */
|
||||
#define BF_RFSYS_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LH) & BM_RFSYS_REGn_LH)
|
||||
|
||||
/*! @brief Set the LH field to a new value. */
|
||||
#define BW_RFSYS_REGn_LH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field HL[23:16] (RW)
|
||||
*
|
||||
* High lower byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFSYS_REGn_HL (16U) /*!< Bit position for RFSYS_REGn_HL. */
|
||||
#define BM_RFSYS_REGn_HL (0x00FF0000U) /*!< Bit mask for RFSYS_REGn_HL. */
|
||||
#define BS_RFSYS_REGn_HL (8U) /*!< Bit field size in bits for RFSYS_REGn_HL. */
|
||||
|
||||
/*! @brief Read current value of the RFSYS_REGn_HL field. */
|
||||
#define BR_RFSYS_REGn_HL(x, n) (HW_RFSYS_REGn(x, n).B.HL)
|
||||
|
||||
/*! @brief Format value for bitfield RFSYS_REGn_HL. */
|
||||
#define BF_RFSYS_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HL) & BM_RFSYS_REGn_HL)
|
||||
|
||||
/*! @brief Set the HL field to a new value. */
|
||||
#define BW_RFSYS_REGn_HL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field HH[31:24] (RW)
|
||||
*
|
||||
* High higher byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFSYS_REGn_HH (24U) /*!< Bit position for RFSYS_REGn_HH. */
|
||||
#define BM_RFSYS_REGn_HH (0xFF000000U) /*!< Bit mask for RFSYS_REGn_HH. */
|
||||
#define BS_RFSYS_REGn_HH (8U) /*!< Bit field size in bits for RFSYS_REGn_HH. */
|
||||
|
||||
/*! @brief Read current value of the RFSYS_REGn_HH field. */
|
||||
#define BR_RFSYS_REGn_HH(x, n) (HW_RFSYS_REGn(x, n).B.HH)
|
||||
|
||||
/*! @brief Format value for bitfield RFSYS_REGn_HH. */
|
||||
#define BF_RFSYS_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HH) & BM_RFSYS_REGn_HH)
|
||||
|
||||
/*! @brief Set the HH field to a new value. */
|
||||
#define BW_RFSYS_REGn_HH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_rfsys_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All RFSYS module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_rfsys
|
||||
{
|
||||
__IO hw_rfsys_regn_t REGn[8]; /*!< [0x0] Register file register */
|
||||
} hw_rfsys_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all RFSYS registers. */
|
||||
/*! @param x RFSYS module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_RFSYS(RFSYS_BASE)</code>. */
|
||||
#define HW_RFSYS(x) (*(hw_rfsys_t *)(x))
|
||||
|
||||
#endif /* __HW_RFSYS_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_RFVBAT_REGISTERS_H__
|
||||
#define __HW_RFVBAT_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 RFVBAT
|
||||
*
|
||||
* VBAT register file
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_RFVBAT_REGn - VBAT register file register
|
||||
*
|
||||
* - hw_rfvbat_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_RFVBAT_REGn - VBAT register file register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_RFVBAT_REGn - VBAT register file register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* Each register can be accessed as 8-, 16-, or 32-bits.
|
||||
*/
|
||||
typedef union _hw_rfvbat_regn
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_rfvbat_regn_bitfields
|
||||
{
|
||||
uint32_t LL : 8; /*!< [7:0] */
|
||||
uint32_t LH : 8; /*!< [15:8] */
|
||||
uint32_t HL : 8; /*!< [23:16] */
|
||||
uint32_t HH : 8; /*!< [31:24] */
|
||||
} B;
|
||||
} hw_rfvbat_regn_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire RFVBAT_REGn register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_RFVBAT_REGn_COUNT (8U)
|
||||
|
||||
#define HW_RFVBAT_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
|
||||
|
||||
#define HW_RFVBAT_REGn(x, n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(x, n))
|
||||
#define HW_RFVBAT_REGn_RD(x, n) (HW_RFVBAT_REGn(x, n).U)
|
||||
#define HW_RFVBAT_REGn_WR(x, n, v) (HW_RFVBAT_REGn(x, n).U = (v))
|
||||
#define HW_RFVBAT_REGn_SET(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) | (v)))
|
||||
#define HW_RFVBAT_REGn_CLR(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) & ~(v)))
|
||||
#define HW_RFVBAT_REGn_TOG(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual RFVBAT_REGn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field LL[7:0] (RW)
|
||||
*
|
||||
* Low lower byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFVBAT_REGn_LL (0U) /*!< Bit position for RFVBAT_REGn_LL. */
|
||||
#define BM_RFVBAT_REGn_LL (0x000000FFU) /*!< Bit mask for RFVBAT_REGn_LL. */
|
||||
#define BS_RFVBAT_REGn_LL (8U) /*!< Bit field size in bits for RFVBAT_REGn_LL. */
|
||||
|
||||
/*! @brief Read current value of the RFVBAT_REGn_LL field. */
|
||||
#define BR_RFVBAT_REGn_LL(x, n) (HW_RFVBAT_REGn(x, n).B.LL)
|
||||
|
||||
/*! @brief Format value for bitfield RFVBAT_REGn_LL. */
|
||||
#define BF_RFVBAT_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LL) & BM_RFVBAT_REGn_LL)
|
||||
|
||||
/*! @brief Set the LL field to a new value. */
|
||||
#define BW_RFVBAT_REGn_LL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field LH[15:8] (RW)
|
||||
*
|
||||
* Low higher byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFVBAT_REGn_LH (8U) /*!< Bit position for RFVBAT_REGn_LH. */
|
||||
#define BM_RFVBAT_REGn_LH (0x0000FF00U) /*!< Bit mask for RFVBAT_REGn_LH. */
|
||||
#define BS_RFVBAT_REGn_LH (8U) /*!< Bit field size in bits for RFVBAT_REGn_LH. */
|
||||
|
||||
/*! @brief Read current value of the RFVBAT_REGn_LH field. */
|
||||
#define BR_RFVBAT_REGn_LH(x, n) (HW_RFVBAT_REGn(x, n).B.LH)
|
||||
|
||||
/*! @brief Format value for bitfield RFVBAT_REGn_LH. */
|
||||
#define BF_RFVBAT_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LH) & BM_RFVBAT_REGn_LH)
|
||||
|
||||
/*! @brief Set the LH field to a new value. */
|
||||
#define BW_RFVBAT_REGn_LH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field HL[23:16] (RW)
|
||||
*
|
||||
* High lower byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFVBAT_REGn_HL (16U) /*!< Bit position for RFVBAT_REGn_HL. */
|
||||
#define BM_RFVBAT_REGn_HL (0x00FF0000U) /*!< Bit mask for RFVBAT_REGn_HL. */
|
||||
#define BS_RFVBAT_REGn_HL (8U) /*!< Bit field size in bits for RFVBAT_REGn_HL. */
|
||||
|
||||
/*! @brief Read current value of the RFVBAT_REGn_HL field. */
|
||||
#define BR_RFVBAT_REGn_HL(x, n) (HW_RFVBAT_REGn(x, n).B.HL)
|
||||
|
||||
/*! @brief Format value for bitfield RFVBAT_REGn_HL. */
|
||||
#define BF_RFVBAT_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HL) & BM_RFVBAT_REGn_HL)
|
||||
|
||||
/*! @brief Set the HL field to a new value. */
|
||||
#define BW_RFVBAT_REGn_HL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field HH[31:24] (RW)
|
||||
*
|
||||
* High higher byte
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_RFVBAT_REGn_HH (24U) /*!< Bit position for RFVBAT_REGn_HH. */
|
||||
#define BM_RFVBAT_REGn_HH (0xFF000000U) /*!< Bit mask for RFVBAT_REGn_HH. */
|
||||
#define BS_RFVBAT_REGn_HH (8U) /*!< Bit field size in bits for RFVBAT_REGn_HH. */
|
||||
|
||||
/*! @brief Read current value of the RFVBAT_REGn_HH field. */
|
||||
#define BR_RFVBAT_REGn_HH(x, n) (HW_RFVBAT_REGn(x, n).B.HH)
|
||||
|
||||
/*! @brief Format value for bitfield RFVBAT_REGn_HH. */
|
||||
#define BF_RFVBAT_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HH) & BM_RFVBAT_REGn_HH)
|
||||
|
||||
/*! @brief Set the HH field to a new value. */
|
||||
#define BW_RFVBAT_REGn_HH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_rfvbat_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All RFVBAT module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_rfvbat
|
||||
{
|
||||
__IO hw_rfvbat_regn_t REGn[8]; /*!< [0x0] VBAT register file register */
|
||||
} hw_rfvbat_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all RFVBAT registers. */
|
||||
/*! @param x RFVBAT module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_RFVBAT(RFVBAT_BASE)</code>. */
|
||||
#define HW_RFVBAT(x) (*(hw_rfvbat_t *)(x))
|
||||
|
||||
#endif /* __HW_RFVBAT_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,586 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_SMC_REGISTERS_H__
|
||||
#define __HW_SMC_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 SMC
|
||||
*
|
||||
* System Mode Controller
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_SMC_PMPROT - Power Mode Protection register
|
||||
* - HW_SMC_PMCTRL - Power Mode Control register
|
||||
* - HW_SMC_STOPCTRL - Stop Control Register
|
||||
* - HW_SMC_PMSTAT - Power Mode Status register
|
||||
*
|
||||
* - hw_smc_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_SMC_PMPROT - Power Mode Protection register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* This register provides protection for entry into any low-power run or stop
|
||||
* mode. The enabling of the low-power run or stop mode occurs by configuring the
|
||||
* Power Mode Control register (PMCTRL). The PMPROT register can be written only
|
||||
* once after any system reset. If the MCU is configured for a disallowed or
|
||||
* reserved power mode, the MCU remains in its current power mode. For example, if the
|
||||
* MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
|
||||
* PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
|
||||
* still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
|
||||
* reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
|
||||
* that do not trigger Chip Reset not VLLS. See the Reset section details for more
|
||||
* information.
|
||||
*/
|
||||
typedef union _hw_smc_pmprot
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_smc_pmprot_bitfields
|
||||
{
|
||||
uint8_t RESERVED0 : 1; /*!< [0] */
|
||||
uint8_t AVLLS : 1; /*!< [1] Allow Very-Low-Leakage Stop Mode */
|
||||
uint8_t RESERVED1 : 1; /*!< [2] */
|
||||
uint8_t ALLS : 1; /*!< [3] Allow Low-Leakage Stop Mode */
|
||||
uint8_t RESERVED2 : 1; /*!< [4] */
|
||||
uint8_t AVLP : 1; /*!< [5] Allow Very-Low-Power Modes */
|
||||
uint8_t RESERVED3 : 1; /*!< [6] */
|
||||
uint8_t AHSRUN : 1; /*!< [7] Allow High Speed Run mode */
|
||||
} B;
|
||||
} hw_smc_pmprot_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire SMC_PMPROT register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_SMC_PMPROT_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_SMC_PMPROT(x) (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x))
|
||||
#define HW_SMC_PMPROT_RD(x) (HW_SMC_PMPROT(x).U)
|
||||
#define HW_SMC_PMPROT_WR(x, v) (HW_SMC_PMPROT(x).U = (v))
|
||||
#define HW_SMC_PMPROT_SET(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) | (v)))
|
||||
#define HW_SMC_PMPROT_CLR(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v)))
|
||||
#define HW_SMC_PMPROT_TOG(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual SMC_PMPROT bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMPROT, field AVLLS[1] (RW)
|
||||
*
|
||||
* Provided the appropriate control bits are set up in PMCTRL, this write once
|
||||
* bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Any VLLSx mode is not allowed
|
||||
* - 1 - Any VLLSx mode is allowed
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMPROT_AVLLS (1U) /*!< Bit position for SMC_PMPROT_AVLLS. */
|
||||
#define BM_SMC_PMPROT_AVLLS (0x02U) /*!< Bit mask for SMC_PMPROT_AVLLS. */
|
||||
#define BS_SMC_PMPROT_AVLLS (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
|
||||
#define BR_SMC_PMPROT_AVLLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS))
|
||||
|
||||
/*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */
|
||||
#define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS)
|
||||
|
||||
/*! @brief Set the AVLLS field to a new value. */
|
||||
#define BW_SMC_PMPROT_AVLLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMPROT, field ALLS[3] (RW)
|
||||
*
|
||||
* Provided the appropriate control bits are set up in PMCTRL, this write-once
|
||||
* field allows the MCU to enter any low-leakage stop mode (LLS).
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Any LLSx mode is not allowed
|
||||
* - 1 - Any LLSx mode is allowed
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMPROT_ALLS (3U) /*!< Bit position for SMC_PMPROT_ALLS. */
|
||||
#define BM_SMC_PMPROT_ALLS (0x08U) /*!< Bit mask for SMC_PMPROT_ALLS. */
|
||||
#define BS_SMC_PMPROT_ALLS (1U) /*!< Bit field size in bits for SMC_PMPROT_ALLS. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
|
||||
#define BR_SMC_PMPROT_ALLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS))
|
||||
|
||||
/*! @brief Format value for bitfield SMC_PMPROT_ALLS. */
|
||||
#define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS)
|
||||
|
||||
/*! @brief Set the ALLS field to a new value. */
|
||||
#define BW_SMC_PMPROT_ALLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMPROT, field AVLP[5] (RW)
|
||||
*
|
||||
* Provided the appropriate control bits are set up in PMCTRL, this write-once
|
||||
* field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
|
||||
*
|
||||
* Values:
|
||||
* - 0 - VLPR, VLPW, and VLPS are not allowed.
|
||||
* - 1 - VLPR, VLPW, and VLPS are allowed.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMPROT_AVLP (5U) /*!< Bit position for SMC_PMPROT_AVLP. */
|
||||
#define BM_SMC_PMPROT_AVLP (0x20U) /*!< Bit mask for SMC_PMPROT_AVLP. */
|
||||
#define BS_SMC_PMPROT_AVLP (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLP. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
|
||||
#define BR_SMC_PMPROT_AVLP(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP))
|
||||
|
||||
/*! @brief Format value for bitfield SMC_PMPROT_AVLP. */
|
||||
#define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP)
|
||||
|
||||
/*! @brief Set the AVLP field to a new value. */
|
||||
#define BW_SMC_PMPROT_AVLP(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMPROT, field AHSRUN[7] (RW)
|
||||
*
|
||||
* Provided the appropriate control bits are set up in PMCTRL, this write-once
|
||||
* field allows the MCU to enter High Speed Run mode (HSRUN).
|
||||
*
|
||||
* Values:
|
||||
* - 0 - HSRUN is not allowed
|
||||
* - 1 - HSRUN is allowed
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMPROT_AHSRUN (7U) /*!< Bit position for SMC_PMPROT_AHSRUN. */
|
||||
#define BM_SMC_PMPROT_AHSRUN (0x80U) /*!< Bit mask for SMC_PMPROT_AHSRUN. */
|
||||
#define BS_SMC_PMPROT_AHSRUN (1U) /*!< Bit field size in bits for SMC_PMPROT_AHSRUN. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMPROT_AHSRUN field. */
|
||||
#define BR_SMC_PMPROT_AHSRUN(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN))
|
||||
|
||||
/*! @brief Format value for bitfield SMC_PMPROT_AHSRUN. */
|
||||
#define BF_SMC_PMPROT_AHSRUN(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AHSRUN) & BM_SMC_PMPROT_AHSRUN)
|
||||
|
||||
/*! @brief Set the AHSRUN field to a new value. */
|
||||
#define BW_SMC_PMPROT_AHSRUN(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_SMC_PMCTRL - Power Mode Control register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* The PMCTRL register controls entry into low-power Run and Stop modes,
|
||||
* provided that the selected power mode is allowed via an appropriate setting of the
|
||||
* protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
|
||||
* reset types that trigger Chip POR not VLLS. It is unaffected by reset types
|
||||
* that do not trigger Chip POR not VLLS. See the Reset section details for more
|
||||
* information.
|
||||
*/
|
||||
typedef union _hw_smc_pmctrl
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_smc_pmctrl_bitfields
|
||||
{
|
||||
uint8_t STOPM : 3; /*!< [2:0] Stop Mode Control */
|
||||
uint8_t STOPA : 1; /*!< [3] Stop Aborted */
|
||||
uint8_t RESERVED0 : 1; /*!< [4] */
|
||||
uint8_t RUNM : 2; /*!< [6:5] Run Mode Control */
|
||||
uint8_t RESERVED1 : 1; /*!< [7] */
|
||||
} B;
|
||||
} hw_smc_pmctrl_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire SMC_PMCTRL register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_SMC_PMCTRL_ADDR(x) ((x) + 0x1U)
|
||||
|
||||
#define HW_SMC_PMCTRL(x) (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x))
|
||||
#define HW_SMC_PMCTRL_RD(x) (HW_SMC_PMCTRL(x).U)
|
||||
#define HW_SMC_PMCTRL_WR(x, v) (HW_SMC_PMCTRL(x).U = (v))
|
||||
#define HW_SMC_PMCTRL_SET(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) | (v)))
|
||||
#define HW_SMC_PMCTRL_CLR(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v)))
|
||||
#define HW_SMC_PMCTRL_TOG(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual SMC_PMCTRL bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
|
||||
*
|
||||
* When written, controls entry into the selected stop mode when Sleep-Now or
|
||||
* Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
|
||||
* blocked if the protection level has not been enabled using the PMPROT register.
|
||||
* After any system reset, this field is cleared by hardware on any successful write
|
||||
* to the PMPROT register. When set to VLLSxor LLSx, the LLSM in the STOPCTRL
|
||||
* register is used to further select the particular VLLSor LLS submode which will
|
||||
* be entered. When set to STOP, the PSTOPO bits in the STOPCTRL register can be
|
||||
* used to select a Partial Stop mode if desired.
|
||||
*
|
||||
* Values:
|
||||
* - 000 - Normal Stop (STOP)
|
||||
* - 001 - Reserved
|
||||
* - 010 - Very-Low-Power Stop (VLPS)
|
||||
* - 011 - Low-Leakage Stop (LLSx)
|
||||
* - 100 - Very-Low-Leakage Stop (VLLSx)
|
||||
* - 101 - Reserved
|
||||
* - 110 - Reseved
|
||||
* - 111 - Reserved
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMCTRL_STOPM (0U) /*!< Bit position for SMC_PMCTRL_STOPM. */
|
||||
#define BM_SMC_PMCTRL_STOPM (0x07U) /*!< Bit mask for SMC_PMCTRL_STOPM. */
|
||||
#define BS_SMC_PMCTRL_STOPM (3U) /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
|
||||
#define BR_SMC_PMCTRL_STOPM(x) (HW_SMC_PMCTRL(x).B.STOPM)
|
||||
|
||||
/*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */
|
||||
#define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM)
|
||||
|
||||
/*! @brief Set the STOPM field to a new value. */
|
||||
#define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMCTRL, field STOPA[3] (RO)
|
||||
*
|
||||
* When set, this read-only status bit indicates an interrupt occured during the
|
||||
* previous stop mode entry sequence, preventing the system from entering that
|
||||
* mode. This field is cleared by reset or by hardware at the beginning of any
|
||||
* stop mode entry sequence and is set if the sequence was aborted.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The previous stop mode entry was successsful.
|
||||
* - 1 - The previous stop mode entry was aborted.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMCTRL_STOPA (3U) /*!< Bit position for SMC_PMCTRL_STOPA. */
|
||||
#define BM_SMC_PMCTRL_STOPA (0x08U) /*!< Bit mask for SMC_PMCTRL_STOPA. */
|
||||
#define BS_SMC_PMCTRL_STOPA (1U) /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
|
||||
#define BR_SMC_PMCTRL_STOPA(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
|
||||
*
|
||||
* When written, causes entry into the selected run mode. Writes to this field
|
||||
* are blocked if the protection level has not been enabled using the PMPROT
|
||||
* register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
|
||||
* VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. RUNM may be set to
|
||||
* HSRUN only when PMSTAT=RUN. After being programmed to HSRUN, RUNM should not
|
||||
* be programmed back to RUN until PMSTAT=HSRUN. Also, stop mode entry should not
|
||||
* be attempted while RUNM=HSRUN or PMSTAT=HSRUN.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Normal Run mode (RUN)
|
||||
* - 01 - Reserved
|
||||
* - 10 - Very-Low-Power Run mode (VLPR)
|
||||
* - 11 - High Speed Run mode (HSRUN)
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMCTRL_RUNM (5U) /*!< Bit position for SMC_PMCTRL_RUNM. */
|
||||
#define BM_SMC_PMCTRL_RUNM (0x60U) /*!< Bit mask for SMC_PMCTRL_RUNM. */
|
||||
#define BS_SMC_PMCTRL_RUNM (2U) /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
|
||||
#define BR_SMC_PMCTRL_RUNM(x) (HW_SMC_PMCTRL(x).B.RUNM)
|
||||
|
||||
/*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */
|
||||
#define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM)
|
||||
|
||||
/*! @brief Set the RUNM field to a new value. */
|
||||
#define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_SMC_STOPCTRL - Stop Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_SMC_STOPCTRL - Stop Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x03U
|
||||
*
|
||||
* The STOPCTRL register provides various control bits allowing the user to fine
|
||||
* tune power consumption during the stop mode selected by the STOPM field. This
|
||||
* register is reset on Chip POR not VLLS and by reset types that trigger Chip
|
||||
* POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not
|
||||
* VLLS. See the Reset section details for more information.
|
||||
*/
|
||||
typedef union _hw_smc_stopctrl
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_smc_stopctrl_bitfields
|
||||
{
|
||||
uint8_t LLSM : 3; /*!< [2:0] LLS or VLLS Mode Control */
|
||||
uint8_t RESERVED0 : 2; /*!< [4:3] */
|
||||
uint8_t PORPO : 1; /*!< [5] POR Power Option */
|
||||
uint8_t PSTOPO : 2; /*!< [7:6] Partial Stop Option */
|
||||
} B;
|
||||
} hw_smc_stopctrl_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire SMC_STOPCTRL register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_SMC_STOPCTRL_ADDR(x) ((x) + 0x2U)
|
||||
|
||||
#define HW_SMC_STOPCTRL(x) (*(__IO hw_smc_stopctrl_t *) HW_SMC_STOPCTRL_ADDR(x))
|
||||
#define HW_SMC_STOPCTRL_RD(x) (HW_SMC_STOPCTRL(x).U)
|
||||
#define HW_SMC_STOPCTRL_WR(x, v) (HW_SMC_STOPCTRL(x).U = (v))
|
||||
#define HW_SMC_STOPCTRL_SET(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) | (v)))
|
||||
#define HW_SMC_STOPCTRL_CLR(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) & ~(v)))
|
||||
#define HW_SMC_STOPCTRL_TOG(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual SMC_STOPCTRL bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_STOPCTRL, field LLSM[2:0] (RW)
|
||||
*
|
||||
* This field controls which LLS or VLLS sub-mode to enter if STOPM=LLSx or
|
||||
* VLLSx.
|
||||
*
|
||||
* Values:
|
||||
* - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
|
||||
* - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
|
||||
* - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
|
||||
* - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
|
||||
* - 100 - Reserved
|
||||
* - 101 - Reserved
|
||||
* - 110 - Reserved
|
||||
* - 111 - Reserved
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_STOPCTRL_LLSM (0U) /*!< Bit position for SMC_STOPCTRL_LLSM. */
|
||||
#define BM_SMC_STOPCTRL_LLSM (0x07U) /*!< Bit mask for SMC_STOPCTRL_LLSM. */
|
||||
#define BS_SMC_STOPCTRL_LLSM (3U) /*!< Bit field size in bits for SMC_STOPCTRL_LLSM. */
|
||||
|
||||
/*! @brief Read current value of the SMC_STOPCTRL_LLSM field. */
|
||||
#define BR_SMC_STOPCTRL_LLSM(x) (HW_SMC_STOPCTRL(x).B.LLSM)
|
||||
|
||||
/*! @brief Format value for bitfield SMC_STOPCTRL_LLSM. */
|
||||
#define BF_SMC_STOPCTRL_LLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_LLSM) & BM_SMC_STOPCTRL_LLSM)
|
||||
|
||||
/*! @brief Set the LLSM field to a new value. */
|
||||
#define BW_SMC_STOPCTRL_LLSM(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_LLSM) | BF_SMC_STOPCTRL_LLSM(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_STOPCTRL, field PORPO[5] (RW)
|
||||
*
|
||||
* This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - POR detect circuit is enabled in VLLS0
|
||||
* - 1 - POR detect circuit is disabled in VLLS0
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_STOPCTRL_PORPO (5U) /*!< Bit position for SMC_STOPCTRL_PORPO. */
|
||||
#define BM_SMC_STOPCTRL_PORPO (0x20U) /*!< Bit mask for SMC_STOPCTRL_PORPO. */
|
||||
#define BS_SMC_STOPCTRL_PORPO (1U) /*!< Bit field size in bits for SMC_STOPCTRL_PORPO. */
|
||||
|
||||
/*! @brief Read current value of the SMC_STOPCTRL_PORPO field. */
|
||||
#define BR_SMC_STOPCTRL_PORPO(x) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO))
|
||||
|
||||
/*! @brief Format value for bitfield SMC_STOPCTRL_PORPO. */
|
||||
#define BF_SMC_STOPCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PORPO) & BM_SMC_STOPCTRL_PORPO)
|
||||
|
||||
/*! @brief Set the PORPO field to a new value. */
|
||||
#define BW_SMC_STOPCTRL_PORPO(x, v) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_STOPCTRL, field PSTOPO[7:6] (RW)
|
||||
*
|
||||
* These bits control whether a Partial Stop mode is entered when STOPM=STOP.
|
||||
* When entering a Partial Stop mode from RUN mode, the PMC, MCG and flash remain
|
||||
* fully powered, allowing the device to wakeup almost instantaneously at the
|
||||
* expense of higher power consumption. In PSTOP2, only system clocks are gated
|
||||
* allowing peripherals running on bus clock to remain fully functional. In PSTOP1,
|
||||
* both system and bus clocks are gated.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - STOP - Normal Stop mode
|
||||
* - 01 - PSTOP1 - Partial Stop with both system and bus clocks disabled
|
||||
* - 10 - PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
|
||||
* - 11 - Reserved
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_STOPCTRL_PSTOPO (6U) /*!< Bit position for SMC_STOPCTRL_PSTOPO. */
|
||||
#define BM_SMC_STOPCTRL_PSTOPO (0xC0U) /*!< Bit mask for SMC_STOPCTRL_PSTOPO. */
|
||||
#define BS_SMC_STOPCTRL_PSTOPO (2U) /*!< Bit field size in bits for SMC_STOPCTRL_PSTOPO. */
|
||||
|
||||
/*! @brief Read current value of the SMC_STOPCTRL_PSTOPO field. */
|
||||
#define BR_SMC_STOPCTRL_PSTOPO(x) (HW_SMC_STOPCTRL(x).B.PSTOPO)
|
||||
|
||||
/*! @brief Format value for bitfield SMC_STOPCTRL_PSTOPO. */
|
||||
#define BF_SMC_STOPCTRL_PSTOPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PSTOPO) & BM_SMC_STOPCTRL_PSTOPO)
|
||||
|
||||
/*! @brief Set the PSTOPO field to a new value. */
|
||||
#define BW_SMC_STOPCTRL_PSTOPO(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_PSTOPO) | BF_SMC_STOPCTRL_PSTOPO(v)))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_SMC_PMSTAT - Power Mode Status register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
|
||||
*
|
||||
* Reset value: 0x01U
|
||||
*
|
||||
* PMSTAT is a read-only, one-hot register which indicates the current power
|
||||
* mode of the system. This register is reset on Chip POR not VLLS and by reset
|
||||
* types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
|
||||
* trigger Chip POR not VLLS. See the Reset section details for more information.
|
||||
*/
|
||||
typedef union _hw_smc_pmstat
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_smc_pmstat_bitfields
|
||||
{
|
||||
uint8_t PMSTAT : 8; /*!< [7:0] */
|
||||
} B;
|
||||
} hw_smc_pmstat_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire SMC_PMSTAT register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_SMC_PMSTAT_ADDR(x) ((x) + 0x3U)
|
||||
|
||||
#define HW_SMC_PMSTAT(x) (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x))
|
||||
#define HW_SMC_PMSTAT_RD(x) (HW_SMC_PMSTAT(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual SMC_PMSTAT bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register SMC_PMSTAT, field PMSTAT[7:0] (RO)
|
||||
*
|
||||
* When debug is enabled, the PMSTAT will not update to STOP or VLPS When a
|
||||
* PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_SMC_PMSTAT_PMSTAT (0U) /*!< Bit position for SMC_PMSTAT_PMSTAT. */
|
||||
#define BM_SMC_PMSTAT_PMSTAT (0xFFU) /*!< Bit mask for SMC_PMSTAT_PMSTAT. */
|
||||
#define BS_SMC_PMSTAT_PMSTAT (8U) /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */
|
||||
|
||||
/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
|
||||
#define BR_SMC_PMSTAT_PMSTAT(x) (HW_SMC_PMSTAT(x).U)
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_smc_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All SMC module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_smc
|
||||
{
|
||||
__IO hw_smc_pmprot_t PMPROT; /*!< [0x0] Power Mode Protection register */
|
||||
__IO hw_smc_pmctrl_t PMCTRL; /*!< [0x1] Power Mode Control register */
|
||||
__IO hw_smc_stopctrl_t STOPCTRL; /*!< [0x2] Stop Control Register */
|
||||
__I hw_smc_pmstat_t PMSTAT; /*!< [0x3] Power Mode Status register */
|
||||
} hw_smc_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all SMC registers. */
|
||||
/*! @param x SMC module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_SMC(SMC_BASE)</code>. */
|
||||
#define HW_SMC(x) (*(hw_smc_t *)(x))
|
||||
|
||||
#endif /* __HW_SMC_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,372 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Extension to the CMSIS register access layer header.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_VREF_REGISTERS_H__
|
||||
#define __HW_VREF_REGISTERS_H__
|
||||
|
||||
#include "MK22F12810.h"
|
||||
#include "fsl_bitaccess.h"
|
||||
|
||||
/*
|
||||
* MK22F12810 VREF
|
||||
*
|
||||
* Voltage Reference
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_VREF_TRM - VREF Trim Register
|
||||
* - HW_VREF_SC - VREF Status and Control Register
|
||||
*
|
||||
* - hw_vref_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
#define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_VREF_TRM - VREF Trim Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_VREF_TRM - VREF Trim Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* This register contains bits that contain the trim data for the Voltage
|
||||
* Reference.
|
||||
*/
|
||||
typedef union _hw_vref_trm
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_vref_trm_bitfields
|
||||
{
|
||||
uint8_t TRIM : 6; /*!< [5:0] Trim bits */
|
||||
uint8_t CHOPEN : 1; /*!< [6] Chop oscillator enable. When set,
|
||||
* internal chopping operation is enabled and the internal analog offset will be
|
||||
* minimized. */
|
||||
uint8_t RESERVED0 : 1; /*!< [7] */
|
||||
} B;
|
||||
} hw_vref_trm_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire VREF_TRM register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_VREF_TRM_ADDR(x) ((x) + 0x0U)
|
||||
|
||||
#define HW_VREF_TRM(x) (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x))
|
||||
#define HW_VREF_TRM_RD(x) (HW_VREF_TRM(x).U)
|
||||
#define HW_VREF_TRM_WR(x, v) (HW_VREF_TRM(x).U = (v))
|
||||
#define HW_VREF_TRM_SET(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) | (v)))
|
||||
#define HW_VREF_TRM_CLR(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v)))
|
||||
#define HW_VREF_TRM_TOG(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual VREF_TRM bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register VREF_TRM, field TRIM[5:0] (RW)
|
||||
*
|
||||
* These bits change the resulting VREF by approximately +/- 0.5 mV for each
|
||||
* step. Min = minimum and max = maximum voltage reference output. For minimum and
|
||||
* maximum voltage reference output values, refer to the Data Sheet for this chip.
|
||||
*
|
||||
* Values:
|
||||
* - 000000 - Min
|
||||
* - 111111 - Max
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_VREF_TRM_TRIM (0U) /*!< Bit position for VREF_TRM_TRIM. */
|
||||
#define BM_VREF_TRM_TRIM (0x3FU) /*!< Bit mask for VREF_TRM_TRIM. */
|
||||
#define BS_VREF_TRM_TRIM (6U) /*!< Bit field size in bits for VREF_TRM_TRIM. */
|
||||
|
||||
/*! @brief Read current value of the VREF_TRM_TRIM field. */
|
||||
#define BR_VREF_TRM_TRIM(x) (HW_VREF_TRM(x).B.TRIM)
|
||||
|
||||
/*! @brief Format value for bitfield VREF_TRM_TRIM. */
|
||||
#define BF_VREF_TRM_TRIM(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM)
|
||||
|
||||
/*! @brief Set the TRIM field to a new value. */
|
||||
#define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register VREF_TRM, field CHOPEN[6] (RW)
|
||||
*
|
||||
* This bit is set during factory trimming of the VREF voltage. This bit should
|
||||
* be written to 1 to achieve the performance stated in the data sheet.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Chop oscillator is disabled.
|
||||
* - 1 - Chop oscillator is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_VREF_TRM_CHOPEN (6U) /*!< Bit position for VREF_TRM_CHOPEN. */
|
||||
#define BM_VREF_TRM_CHOPEN (0x40U) /*!< Bit mask for VREF_TRM_CHOPEN. */
|
||||
#define BS_VREF_TRM_CHOPEN (1U) /*!< Bit field size in bits for VREF_TRM_CHOPEN. */
|
||||
|
||||
/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
|
||||
#define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN))
|
||||
|
||||
/*! @brief Format value for bitfield VREF_TRM_CHOPEN. */
|
||||
#define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN)
|
||||
|
||||
/*! @brief Set the CHOPEN field to a new value. */
|
||||
#define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* HW_VREF_SC - VREF Status and Control Register
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief HW_VREF_SC - VREF Status and Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* This register contains the control bits used to enable the internal voltage
|
||||
* reference and to select the buffer mode to be used.
|
||||
*/
|
||||
typedef union _hw_vref_sc
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_vref_sc_bitfields
|
||||
{
|
||||
uint8_t MODE_LV : 2; /*!< [1:0] Buffer Mode selection */
|
||||
uint8_t VREFST : 1; /*!< [2] Internal Voltage Reference stable */
|
||||
uint8_t RESERVED0 : 2; /*!< [4:3] */
|
||||
uint8_t ICOMPEN : 1; /*!< [5] Second order curvature compensation
|
||||
* enable */
|
||||
uint8_t REGEN : 1; /*!< [6] Regulator enable */
|
||||
uint8_t VREFEN : 1; /*!< [7] Internal Voltage Reference enable */
|
||||
} B;
|
||||
} hw_vref_sc_t;
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire VREF_SC register
|
||||
*/
|
||||
/*@{*/
|
||||
#define HW_VREF_SC_ADDR(x) ((x) + 0x1U)
|
||||
|
||||
#define HW_VREF_SC(x) (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x))
|
||||
#define HW_VREF_SC_RD(x) (HW_VREF_SC(x).U)
|
||||
#define HW_VREF_SC_WR(x, v) (HW_VREF_SC(x).U = (v))
|
||||
#define HW_VREF_SC_SET(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) | (v)))
|
||||
#define HW_VREF_SC_CLR(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v)))
|
||||
#define HW_VREF_SC_TOG(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^ (v)))
|
||||
/*@}*/
|
||||
|
||||
/*
|
||||
* Constants & macros for individual VREF_SC bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register VREF_SC, field MODE_LV[1:0] (RW)
|
||||
*
|
||||
* These bits select the buffer modes for the Voltage Reference module.
|
||||
*
|
||||
* Values:
|
||||
* - 00 - Bandgap on only, for stabilization and startup
|
||||
* - 01 - High power buffer mode enabled
|
||||
* - 10 - Low-power buffer mode enabled
|
||||
* - 11 - Reserved
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_VREF_SC_MODE_LV (0U) /*!< Bit position for VREF_SC_MODE_LV. */
|
||||
#define BM_VREF_SC_MODE_LV (0x03U) /*!< Bit mask for VREF_SC_MODE_LV. */
|
||||
#define BS_VREF_SC_MODE_LV (2U) /*!< Bit field size in bits for VREF_SC_MODE_LV. */
|
||||
|
||||
/*! @brief Read current value of the VREF_SC_MODE_LV field. */
|
||||
#define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV)
|
||||
|
||||
/*! @brief Format value for bitfield VREF_SC_MODE_LV. */
|
||||
#define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV)
|
||||
|
||||
/*! @brief Set the MODE_LV field to a new value. */
|
||||
#define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register VREF_SC, field VREFST[2] (RO)
|
||||
*
|
||||
* This bit indicates that the bandgap reference within the Voltage Reference
|
||||
* module has completed its startup and stabilization.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The module is disabled or not stable.
|
||||
* - 1 - The module is stable.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_VREF_SC_VREFST (2U) /*!< Bit position for VREF_SC_VREFST. */
|
||||
#define BM_VREF_SC_VREFST (0x04U) /*!< Bit mask for VREF_SC_VREFST. */
|
||||
#define BS_VREF_SC_VREFST (1U) /*!< Bit field size in bits for VREF_SC_VREFST. */
|
||||
|
||||
/*! @brief Read current value of the VREF_SC_VREFST field. */
|
||||
#define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register VREF_SC, field ICOMPEN[5] (RW)
|
||||
*
|
||||
* This bit should be written to 1 to achieve the performance stated in the data
|
||||
* sheet.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disabled
|
||||
* - 1 - Enabled
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_VREF_SC_ICOMPEN (5U) /*!< Bit position for VREF_SC_ICOMPEN. */
|
||||
#define BM_VREF_SC_ICOMPEN (0x20U) /*!< Bit mask for VREF_SC_ICOMPEN. */
|
||||
#define BS_VREF_SC_ICOMPEN (1U) /*!< Bit field size in bits for VREF_SC_ICOMPEN. */
|
||||
|
||||
/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
|
||||
#define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN))
|
||||
|
||||
/*! @brief Format value for bitfield VREF_SC_ICOMPEN. */
|
||||
#define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN)
|
||||
|
||||
/*! @brief Set the ICOMPEN field to a new value. */
|
||||
#define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register VREF_SC, field REGEN[6] (RW)
|
||||
*
|
||||
* This bit is used to enable the internal 1.75 V regulator to produce a
|
||||
* constant internal voltage supply in order to reduce the sensitivity to external
|
||||
* supply noise and variation. If it is desired to keep the regulator enabled in very
|
||||
* low power modes, refer to the Chip Configuration details for a description on
|
||||
* how this can be achieved. This bit should be written to 1 to achieve the
|
||||
* performance stated in the data sheet.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Internal 1.75 V regulator is disabled.
|
||||
* - 1 - Internal 1.75 V regulator is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_VREF_SC_REGEN (6U) /*!< Bit position for VREF_SC_REGEN. */
|
||||
#define BM_VREF_SC_REGEN (0x40U) /*!< Bit mask for VREF_SC_REGEN. */
|
||||
#define BS_VREF_SC_REGEN (1U) /*!< Bit field size in bits for VREF_SC_REGEN. */
|
||||
|
||||
/*! @brief Read current value of the VREF_SC_REGEN field. */
|
||||
#define BR_VREF_SC_REGEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN))
|
||||
|
||||
/*! @brief Format value for bitfield VREF_SC_REGEN. */
|
||||
#define BF_VREF_SC_REGEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN)
|
||||
|
||||
/*! @brief Set the REGEN field to a new value. */
|
||||
#define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Register VREF_SC, field VREFEN[7] (RW)
|
||||
*
|
||||
* This bit is used to enable the bandgap reference within the Voltage Reference
|
||||
* module. After the VREF is enabled, turning off the clock to the VREF module
|
||||
* via the corresponding clock gate register will not disable the VREF. VREF must
|
||||
* be disabled via this VREFEN bit.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - The module is disabled.
|
||||
* - 1 - The module is enabled.
|
||||
*/
|
||||
/*@{*/
|
||||
#define BP_VREF_SC_VREFEN (7U) /*!< Bit position for VREF_SC_VREFEN. */
|
||||
#define BM_VREF_SC_VREFEN (0x80U) /*!< Bit mask for VREF_SC_VREFEN. */
|
||||
#define BS_VREF_SC_VREFEN (1U) /*!< Bit field size in bits for VREF_SC_VREFEN. */
|
||||
|
||||
/*! @brief Read current value of the VREF_SC_VREFEN field. */
|
||||
#define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN))
|
||||
|
||||
/*! @brief Format value for bitfield VREF_SC_VREFEN. */
|
||||
#define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN)
|
||||
|
||||
/*! @brief Set the VREFEN field to a new value. */
|
||||
#define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* hw_vref_t - module struct
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief All VREF module registers.
|
||||
*/
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_vref
|
||||
{
|
||||
__IO hw_vref_trm_t TRM; /*!< [0x0] VREF Trim Register */
|
||||
__IO hw_vref_sc_t SC; /*!< [0x1] VREF Status and Control Register */
|
||||
} hw_vref_t;
|
||||
#pragma pack()
|
||||
|
||||
/*! @brief Macro to access all VREF registers. */
|
||||
/*! @param x VREF module instance base address. */
|
||||
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
* use the '&' operator, like <code>&HW_VREF(VREF_BASE)</code>. */
|
||||
#define HW_VREF(x) (*(hw_vref_t *)(x))
|
||||
|
||||
#endif /* __HW_VREF_REGISTERS_H__ */
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,515 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Version: rev. 1.3, 2014-05-06
|
||||
** Build: b140604
|
||||
**
|
||||
** Abstract:
|
||||
** Register bit field access macros.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-11-01)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2013-12-20)
|
||||
** Update according to reference manual rev. 0.1,
|
||||
** - rev. 1.2 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
||||
** - rev. 1.3 (2014-05-06)
|
||||
** Update according to reference manual rev. 1.0,
|
||||
** Update of system and startup files.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FSL_BITACCESS_H
|
||||
#define _FSL_BITACCESS_H 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
/**
|
||||
* @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
|
||||
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
|
||||
* @param Reg Register to access.
|
||||
* @param Bit Bit number to access.
|
||||
* @return Value of the targeted bit in the bit band region.
|
||||
*/
|
||||
#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
|
||||
|
||||
/**
|
||||
* @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
|
||||
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
|
||||
* @param Reg Register to access.
|
||||
* @param Bit Bit number to access.
|
||||
* @return Value of the targeted bit in the bit band region.
|
||||
*/
|
||||
#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
|
||||
|
||||
/**
|
||||
* @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
|
||||
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
|
||||
* @param Reg Register to access.
|
||||
* @param Bit Bit number to access.
|
||||
* @return Value of the targeted bit in the bit band region.
|
||||
*/
|
||||
#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
|
||||
|
||||
/*
|
||||
* Macros for single instance registers
|
||||
*/
|
||||
|
||||
#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
|
||||
#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
|
||||
#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
|
||||
|
||||
#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
|
||||
#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
|
||||
#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
|
||||
|
||||
#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BF_RD(reg, field) HW_##reg.B.field
|
||||
#define BF_WR(reg, field, v) BW_##reg##_##field(v)
|
||||
|
||||
#define BF_CS1(reg, f1, v1) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1)))
|
||||
|
||||
#define BF_CS2(reg, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2)))
|
||||
|
||||
#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3)))
|
||||
|
||||
#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4)))
|
||||
|
||||
#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5)))
|
||||
|
||||
#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6)))
|
||||
|
||||
#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7)))
|
||||
|
||||
#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8), \
|
||||
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8)))
|
||||
|
||||
/*
|
||||
* Macros for multiple instance registers
|
||||
*/
|
||||
|
||||
#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
|
||||
#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
|
||||
#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
|
||||
|
||||
#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
|
||||
#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
|
||||
#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
|
||||
|
||||
#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BF_RDn(reg, n, field) HW_##reg(n).B.field
|
||||
#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
|
||||
|
||||
#define BF_CS1n(reg, n, f1, v1) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
|
||||
|
||||
#define BF_CS2n(reg, n, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2))))
|
||||
|
||||
#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3))))
|
||||
|
||||
#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4))))
|
||||
|
||||
#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5))))
|
||||
|
||||
#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6))))
|
||||
|
||||
#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7))))
|
||||
|
||||
#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8)), \
|
||||
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8))))
|
||||
|
||||
/*
|
||||
* Macros for single instance MULTI-BLOCK registers
|
||||
*/
|
||||
|
||||
#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
|
||||
#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
|
||||
#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
|
||||
|
||||
#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
|
||||
#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
|
||||
#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
|
||||
|
||||
#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
|
||||
#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
|
||||
|
||||
#define BFn_CS1(reg, blk, f1, v1) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
|
||||
|
||||
#define BFn_CS2(reg, blk, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2)))
|
||||
|
||||
#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3)))
|
||||
|
||||
#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4)))
|
||||
|
||||
#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5)))
|
||||
|
||||
#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6)))
|
||||
|
||||
#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7)))
|
||||
|
||||
#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8), \
|
||||
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8)))
|
||||
|
||||
/*
|
||||
* Macros for MULTI-BLOCK multiple instance registers
|
||||
*/
|
||||
|
||||
#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
|
||||
#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
|
||||
#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
|
||||
|
||||
#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
|
||||
#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
|
||||
#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
|
||||
|
||||
#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
||||
#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
|
||||
|
||||
#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
|
||||
#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
|
||||
|
||||
#define BFn_CS1n(reg, blk, n, f1, v1) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
|
||||
|
||||
#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2))))
|
||||
|
||||
#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3))))
|
||||
|
||||
#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4))))
|
||||
|
||||
#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5))))
|
||||
|
||||
#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6))))
|
||||
|
||||
#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7))))
|
||||
|
||||
#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
||||
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
||||
BM_##reg##_##f2 | \
|
||||
BM_##reg##_##f3 | \
|
||||
BM_##reg##_##f4 | \
|
||||
BM_##reg##_##f5 | \
|
||||
BM_##reg##_##f6 | \
|
||||
BM_##reg##_##f7 | \
|
||||
BM_##reg##_##f8)), \
|
||||
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
||||
BF_##reg##_##f2(v2) | \
|
||||
BF_##reg##_##f3(v3) | \
|
||||
BF_##reg##_##f4(v4) | \
|
||||
BF_##reg##_##f5(v5) | \
|
||||
BF_##reg##_##f6(v6) | \
|
||||
BF_##reg##_##f7(v7) | \
|
||||
BF_##reg##_##f8(v8))))
|
||||
|
||||
#endif /* _FSL_BITACCESS_H */
|
||||
|
||||
/******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,32 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_api.h"
|
||||
|
||||
// called before main - implement here if board needs it ortherwise, let
|
||||
// the application override this if necessary
|
||||
//void mbed_sdk_init()
|
||||
//{
|
||||
//
|
||||
//}
|
||||
|
||||
// Change the NMI pin to an input. This allows NMI pin to
|
||||
// be used as a low power mode wakeup. The application will
|
||||
// need to change the pin back to NMI_b or wakeup only occurs once!
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
gpio_t gpio;
|
||||
gpio_init_in(&gpio, PTA4);
|
||||
}
|
||||
|
|
@ -31,6 +31,8 @@
|
|||
#include "fsl_phy_driver.h"
|
||||
#include "fsl_enet_hal.h"
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
|
@ -398,6 +400,9 @@ bool PHY_DRV_UpdateSpeed(uint32_t instance, uint32_t phyAddr, enet_phy_speed_t *
|
|||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
*/
|
||||
#include "fsl_enet_common.h"
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*! @brief Table of base addresses for Enet instances. */
|
||||
const uint32_t g_enetBaseAddr[] = ENET_BASE_ADDRS;
|
||||
|
||||
|
|
@ -38,6 +40,8 @@ const IRQn_Type g_enetRxIrqId[] = ENET_Receive_IRQS;
|
|||
const IRQn_Type g_enetTsIrqId[] = ENET_1588_Timer_IRQS;
|
||||
const IRQn_Type g_enetErrIrqId[] = ENET_Error_IRQS;
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@
|
|||
#include "fsl_device_registers.h"
|
||||
#include "fsl_enet_hal.h"
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*! @brief Array for eDMA module register base address. */
|
||||
extern const uint32_t g_enetBaseAddr[];
|
||||
|
||||
|
|
@ -44,6 +46,8 @@ extern const IRQn_Type g_enetRxIrqId[];
|
|||
extern const IRQn_Type g_enetTsIrqId[];
|
||||
extern const IRQn_Type g_enetErrIrqId[];
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
#endif /* __ENET_COMMON_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -34,6 +34,9 @@
|
|||
#include <stdbool.h>
|
||||
#include "fsl_enet_hal.h"
|
||||
#include "fsl_os_abstraction.h"
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*!
|
||||
* @addtogroup enet_driver
|
||||
* @{
|
||||
|
|
@ -763,6 +766,8 @@ extern }
|
|||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
#endif /* __FSL_ENET_DRIVER_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
|
|
|
|||
|
|
@ -30,6 +30,9 @@
|
|||
|
||||
#include "fsl_enet_driver.h"
|
||||
#include "fsl_clock_manager.h"
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
|
@ -58,6 +61,8 @@ void ENET_1588_Timer_IRQHandler(void)
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -32,6 +32,9 @@
|
|||
#define __FSL_ENET_RTCS_ADAPTOR_H__
|
||||
|
||||
#include "fsl_enet_hal.h"
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
#ifdef FSL_RTOS_MQX
|
||||
#include "rtcs.h"
|
||||
#include "pcb.h"
|
||||
|
|
@ -493,6 +496,8 @@ const char * ENET_strerror(uint32_t error);
|
|||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
#endif /* __FSL_ENET_RTCS_ADAPTOR_H__ */
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@
|
|||
#include "fsl_interrupt_manager.h"
|
||||
#include <string.h>
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
|
@ -2024,6 +2026,7 @@ void *enet_mac_dequeue_buffer( void **queue)
|
|||
return buffer;
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@
|
|||
#include "fsl_os_abstraction.h"
|
||||
#include <string.h>
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
|
@ -1394,6 +1396,8 @@ const char * ENET_strerror(uint32_t error)
|
|||
return ENET_errlist[error - kStatus_ENET_InvalidInput];
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@
|
|||
/* @brief Number of interrupt vectors. */
|
||||
#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#define MBED_NO_FLEXCAN
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_FLEXCAN_FEATURES_H__ */
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
*/
|
||||
#include "fsl_flexcan_hal.h"
|
||||
|
||||
#ifndef MBED_NO_FLEXCAN
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
|
@ -1835,6 +1837,8 @@ flexcan_status_t FLEXCAN_HAL_DisableOperationMode(
|
|||
return (kStatus_FLEXCAN_Success);
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_FLEXCAN */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@
|
|||
#include "fsl_flexcan_features.h"
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
#ifndef MBED_NO_FLEXCAN
|
||||
|
||||
/*!
|
||||
* @addtogroup flexcan_hal
|
||||
* @{
|
||||
|
|
@ -825,6 +827,8 @@ static inline uint32_t FLEXCAN_HAL_GetIdAcceptanceFilterRxFifo(uint32_t canBase
|
|||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* MBED_NO_FLEXCAN */
|
||||
|
||||
#endif /* __FSL_FLEXCAN_HAL_H__*/
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@
|
|||
/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
|
||||
#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (0)
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#define MBED_NO_ENET
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_ENET_FEATURES_H__ */
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@
|
|||
|
||||
#include "fsl_enet_hal.h"
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
|
@ -746,6 +748,8 @@ void ENET_HAL_Set1588Timer(uint32_t baseAddr,enet_config_ptp_timer_t *ptpCfgPtr)
|
|||
BW_ENET_ATCR_SLAVE(baseAddr, ptpCfgPtr->isSlaveEnabled);
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
|
|
|
|||
|
|
@ -37,6 +37,8 @@
|
|||
#include "fsl_enet_features.h"
|
||||
#include <assert.h>
|
||||
|
||||
#ifndef MBED_NO_ENET
|
||||
|
||||
/*!
|
||||
* @addtogroup enet_hal
|
||||
* @{
|
||||
|
|
@ -2317,6 +2319,8 @@ static inline uint32_t ENET_HAL_GetRxOtetsFramesOk(uint32_t baseAddr)
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* MBED_NO_ENET */
|
||||
|
||||
/*! @}*/
|
||||
#endif /*!< __FSL_ENET_HAL_H__*/
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Version: rev. 1.0, 2014-05-14
|
||||
** Build: b140515
|
||||
**
|
||||
** Abstract:
|
||||
** Chip specific module features.
|
||||
**
|
||||
** Copyright: 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2014-05-14)
|
||||
** Customer release.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if !defined(__FSL_LPUART_FEATURES_H__)
|
||||
#define __FSL_LPUART_FEATURES_H__
|
||||
|
||||
#if defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
|
||||
defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
|
||||
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \
|
||||
defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
|
||||
defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F128VLH10) || \
|
||||
defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
|
||||
defined(CPU_MKV31F512VLL12)
|
||||
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
|
||||
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_HAS_FIFO (0)
|
||||
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
|
||||
/* @brief Infrared (modulation) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
|
||||
/* @brief 2 bits long stop bit is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||
/* @brief Baud rate fine adjustment is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||
/* @brief Peripheral type. */
|
||||
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_FIFO_SIZE (0)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
|
||||
/* @brief Maximal data width with parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
|
||||
/* @brief Supports two match addresses to filter incoming frames. */
|
||||
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||
#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
|
||||
defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
|
||||
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
|
||||
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_HAS_FIFO (0)
|
||||
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
|
||||
/* @brief Infrared (modulation) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
|
||||
/* @brief 2 bits long stop bit is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||
/* @brief Baud rate fine adjustment is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||
/* @brief Peripheral type. */
|
||||
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_FIFO_SIZE (0)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
|
||||
/* @brief Maximal data width with parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
|
||||
/* @brief Supports two match addresses to filter incoming frames. */
|
||||
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0)
|
||||
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||
#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
|
||||
defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
|
||||
defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
|
||||
defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
|
||||
defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
|
||||
defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
|
||||
defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
|
||||
defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
|
||||
defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
|
||||
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
|
||||
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_HAS_FIFO (0)
|
||||
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
|
||||
/* @brief Infrared (modulation) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
|
||||
/* @brief 2 bits long stop bit is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||
/* @brief Baud rate fine adjustment is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||
/* @brief Peripheral type. */
|
||||
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_FIFO_SIZE (0)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
|
||||
/* @brief Maximal data width with parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
|
||||
/* @brief Supports two match addresses to filter incoming frames. */
|
||||
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||
#else
|
||||
#define MBED_NO_LPUART
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_LPUART_FEATURES_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
@ -0,0 +1,782 @@
|
|||
/*
|
||||
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "fsl_lpuart_hal.h"
|
||||
|
||||
#ifndef MBED_NO_LPUART
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_Init
|
||||
* Description : Initializes the LPUART controller to known state.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_Init(uint32_t baseAddr)
|
||||
{
|
||||
HW_LPUART_BAUD_WR(baseAddr, 0x0F000004);
|
||||
HW_LPUART_STAT_WR(baseAddr, 0xC01FC000);
|
||||
HW_LPUART_CTRL_WR(baseAddr, 0x00000000);
|
||||
HW_LPUART_MATCH_WR(baseAddr, 0x00000000);
|
||||
HW_LPUART_MODIR_WR(baseAddr, 0x00000000);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetBaudRate
|
||||
* Description : Configures the LPUART baud rate.
|
||||
* In some LPUART instances the user must disable the transmitter/receiver
|
||||
* before calling this function.
|
||||
* Generally, this may be applied to all LPUARTs to ensure safe operation.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_status_t LPUART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz,
|
||||
uint32_t desiredBaudRate)
|
||||
{
|
||||
uint16_t sbr, sbrTemp, i;
|
||||
uint32_t osr, tempDiff, calculatedBaud, baudDiff;
|
||||
|
||||
/* This lpuart instantiation uses a slightly different baud rate calculation */
|
||||
/* The idea is to use the best OSR (over-sampling rate) possible */
|
||||
/* Note, osr is typically hard-set to 16 in other lpuart instantiations */
|
||||
/* First calculate the baud rate using the minimum OSR possible (4) */
|
||||
osr = 4;
|
||||
sbr = (sourceClockInHz/(desiredBaudRate * osr));
|
||||
calculatedBaud = (sourceClockInHz / (osr * sbr));
|
||||
|
||||
if (calculatedBaud > desiredBaudRate)
|
||||
{
|
||||
baudDiff = calculatedBaud - desiredBaudRate;
|
||||
}
|
||||
else
|
||||
{
|
||||
baudDiff = desiredBaudRate - calculatedBaud;
|
||||
}
|
||||
|
||||
/* loop to find the best osr value possible, one that generates minimum baudDiff */
|
||||
/* iterate through the rest of the supported values of osr */
|
||||
for (i = 5; i <= 32; i++)
|
||||
{
|
||||
/* calculate the temporary sbr value */
|
||||
sbrTemp = (sourceClockInHz/(desiredBaudRate * i));
|
||||
/* calculate the baud rate based on the temporary osr and sbr values */
|
||||
calculatedBaud = (sourceClockInHz / (i * sbrTemp));
|
||||
|
||||
if (calculatedBaud > desiredBaudRate)
|
||||
{
|
||||
tempDiff = calculatedBaud - desiredBaudRate;
|
||||
}
|
||||
else
|
||||
{
|
||||
tempDiff = desiredBaudRate - calculatedBaud;
|
||||
}
|
||||
|
||||
if (tempDiff <= baudDiff)
|
||||
{
|
||||
baudDiff = tempDiff;
|
||||
osr = i; /* update and store the best osr value calculated */
|
||||
sbr = sbrTemp; /* update store the best sbr value calculated */
|
||||
}
|
||||
}
|
||||
|
||||
/* next, check to see if actual baud rate is within 3% of desired baud rate */
|
||||
/* based on the best calculate osr value */
|
||||
if (baudDiff < ((desiredBaudRate / 100) * 3))
|
||||
{
|
||||
/* Acceptable baud rate */
|
||||
/* Check if osr is between 4x and 7x oversampling */
|
||||
/* If so, then "BOTHEDGE" sampling must be turned on */
|
||||
if ((osr > 3) && (osr < 8))
|
||||
{
|
||||
BW_LPUART_BAUD_BOTHEDGE(baseAddr, 1);
|
||||
}
|
||||
|
||||
/* program the osr value (bit value is one less than actual value) */
|
||||
BW_LPUART_BAUD_OSR(baseAddr, (osr-1));
|
||||
|
||||
/* write the sbr value to the BAUD registers */
|
||||
BW_LPUART_BAUD_SBR(baseAddr, sbr);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Unacceptable baud rate difference of more than 3% */
|
||||
return kStatus_LPUART_BaudRatePercentDiffExceeded;
|
||||
}
|
||||
|
||||
return kStatus_LPUART_Success;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetBitCountPerChar
|
||||
* Description : Configures the number of bits per character in the LPUART controller.
|
||||
* In some LPUART instances, the user should disable the transmitter/receiver
|
||||
* before calling this function.
|
||||
* Generally, this may be applied to all LPUARTs to ensure safe operation.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_SetBitCountPerChar(uint32_t baseAddr, lpuart_bit_count_per_char_t bitCountPerChar)
|
||||
{
|
||||
if(bitCountPerChar == kLpuart10BitsPerChar)
|
||||
{
|
||||
BW_LPUART_BAUD_M10(baseAddr, 1); /* set M10 for 10-bit mode, M bit in C1 is don't care */
|
||||
}
|
||||
else
|
||||
{
|
||||
BW_LPUART_CTRL_M(baseAddr, bitCountPerChar); /* config 8- (M=0) or 9-bits (M=1) */
|
||||
BW_LPUART_BAUD_M10(baseAddr, 0); /* clear M10 to make sure not 10-bit mode */
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetParityMode
|
||||
* Description : Configures parity mode in the LPUART controller.
|
||||
* In some LPUART instances, the user should disable the transmitter/receiver
|
||||
* before calling this function.
|
||||
* Generally, this may be applied to all LPUARTs to ensure safe operation.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_SetParityMode(uint32_t baseAddr, lpuart_parity_mode_t parityModeType)
|
||||
{
|
||||
/* configure the parity enable/type */
|
||||
|
||||
if ((parityModeType) == kLpuartParityDisabled)
|
||||
{
|
||||
/* parity disabled, hence parity type is don't care */
|
||||
BW_LPUART_CTRL_PE(baseAddr, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* parity enabled */
|
||||
BW_LPUART_CTRL_PE(baseAddr, 1);
|
||||
/* parity odd/even depending on parity mode setting */
|
||||
BW_LPUART_CTRL_PT(baseAddr, (parityModeType) & 0x1);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetTxRxInversionCmd
|
||||
* Description : Configures the transmit and receive inversion control in the LPUART controller.
|
||||
* This function should only be called when the LPUART is between transmit and receive packets.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, uint32_t rxInvert, uint32_t txInvert)
|
||||
{
|
||||
/* 0 - receive data not inverted, 1 - receive data inverted */
|
||||
BW_LPUART_STAT_RXINV(baseAddr, rxInvert);
|
||||
/* 0 - transmit data not inverted, 1 - transmit data inverted */
|
||||
BW_LPUART_CTRL_TXINV(baseAddr, txInvert);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_EnableTransmitter
|
||||
* Description : Enables the LPUART transmitter.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_EnableTransmitter(uint32_t baseAddr)
|
||||
{
|
||||
/* enable the transmitter based on the lpuart baseAddr */
|
||||
|
||||
/* for this lpuart baseAddr, there is a two step process to clear the transmit complete */
|
||||
/* status flag: */
|
||||
/* 1. Read the status register with the status bit set */
|
||||
/* 2. enable the transmitter (change TE from 0 to 1) */
|
||||
/* first read the status register */
|
||||
|
||||
/* no need to store the read value, it's assumed the status bit is set */
|
||||
HW_LPUART_STAT_RD(baseAddr);
|
||||
/* second, enable the transmitter */
|
||||
BW_LPUART_CTRL_TE(baseAddr, 1);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetIntMode
|
||||
* Description : Configures the LPUART module interrupts to enable/disable various interrupt sources.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_SetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt, bool enable)
|
||||
{
|
||||
uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT;
|
||||
uint32_t temp = 1U << (uint32_t)interrupt;
|
||||
|
||||
switch ( reg )
|
||||
{
|
||||
case LPUART_BAUD_REG_ID:
|
||||
enable ? HW_LPUART_BAUD_SET(baseAddr, temp) : HW_LPUART_BAUD_CLR(baseAddr, temp);
|
||||
break;
|
||||
case LPUART_STAT_REG_ID:
|
||||
enable ? HW_LPUART_STAT_SET(baseAddr, temp) : HW_LPUART_STAT_CLR(baseAddr, temp);
|
||||
break;
|
||||
case LPUART_CTRL_REG_ID:
|
||||
enable ? HW_LPUART_CTRL_SET(baseAddr, temp) : HW_LPUART_CTRL_CLR(baseAddr, temp);
|
||||
break;
|
||||
case LPUART_DATA_REG_ID:
|
||||
enable ? HW_LPUART_DATA_SET(baseAddr, temp) : HW_LPUART_DATA_CLR(baseAddr, temp);
|
||||
break;
|
||||
case LPUART_MATCH_REG_ID:
|
||||
enable ? HW_LPUART_MATCH_SET(baseAddr, temp) : HW_LPUART_MATCH_CLR(baseAddr, temp);
|
||||
break;
|
||||
case LPUART_MODIR_REG_ID:
|
||||
enable ? HW_LPUART_MODIR_SET(baseAddr, temp) : HW_LPUART_MODIR_CLR(baseAddr, temp);
|
||||
break;
|
||||
default :
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_GetIntMode
|
||||
* Description : Returns whether the LPUART module interrupts is enabled/disabled.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
bool LPUART_HAL_GetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt)
|
||||
{
|
||||
uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT;
|
||||
bool retVal = false;
|
||||
|
||||
switch ( reg )
|
||||
{
|
||||
case LPUART_BAUD_REG_ID:
|
||||
retVal = HW_LPUART_BAUD_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
|
||||
break;
|
||||
case LPUART_STAT_REG_ID:
|
||||
retVal = HW_LPUART_STAT_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
|
||||
break;
|
||||
case LPUART_CTRL_REG_ID:
|
||||
retVal = HW_LPUART_CTRL_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
|
||||
break;
|
||||
case LPUART_DATA_REG_ID:
|
||||
retVal = HW_LPUART_DATA_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
|
||||
break;
|
||||
case LPUART_MATCH_REG_ID:
|
||||
retVal = HW_LPUART_MATCH_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
|
||||
break;
|
||||
case LPUART_MODIR_REG_ID:
|
||||
retVal = HW_LPUART_MODIR_RD(baseAddr) >> (uint32_t)(interrupt) & 1U;
|
||||
break;
|
||||
default :
|
||||
break;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
#if FSL_FEATURE_LPUART_HAS_DMA_ENABLE
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_ConfigureDma
|
||||
* Description : LPUART configures DMA requests for Transmitter and Receiver.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig)
|
||||
{
|
||||
/* TDMAE configures the transmit data register empty flag, S1[TDRE], */
|
||||
/* to generate a DMA request. */
|
||||
BW_LPUART_BAUD_TDMAE(baseAddr, txDmaConfig) ;/* set TDMAE to enable, clear to disable */
|
||||
/* RDMAE configures the receive data register fell flag, S1[RDRF], */
|
||||
/* to generate a DMA request. */
|
||||
BW_LPUART_BAUD_RDMAE(baseAddr, rxDmaConfig); /* set RDMAE to enable, clear to disable */
|
||||
}
|
||||
#endif
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_GetWaitModeOperationConfig
|
||||
* Description : LPUART configures DMA requests for Transmitter and Receiver.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_operation_config_t LPUART_HAL_GetWaitModeOperationConfig(uint32_t baseAddr)
|
||||
{
|
||||
/* get configuration lpuart operation in wait mode */
|
||||
/* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */
|
||||
if (BR_LPUART_CTRL_DOZEEN(baseAddr) == 0)
|
||||
{
|
||||
return kLpuartOperates;
|
||||
}
|
||||
else
|
||||
{
|
||||
return kLpuartStops;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SedLoopbackCmd
|
||||
* Description : Configures the LPUART loopback operation (enable/disable loopback operation)
|
||||
* In some LPUART instances, the user should disable the transmitter/receiver
|
||||
* before calling this function.
|
||||
* Generally, this may be applied to all LPUARTs to ensure safe operation.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_SedLoopbackCmd(uint32_t baseAddr, bool enable)
|
||||
{
|
||||
/* configure lpuart to enable/disable operation in loopback mode */
|
||||
|
||||
/* configure LOOPS bit to enable(1)/disable(0) loopback mode, but also need to clear RSRC */
|
||||
BW_LPUART_CTRL_LOOPS(baseAddr, enable);
|
||||
|
||||
/* clear RSRC for loopback mode, and if loopback disabled, */
|
||||
/* this bit has no meaning but clear anyway */
|
||||
/* to set it back to default value */
|
||||
BW_LPUART_CTRL_RSRC(baseAddr, 0);
|
||||
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetSingleWireCmd
|
||||
* Description : Configures the LPUART single-wire operation (enable/disable single-wire mode)
|
||||
* In some LPUART instances, the user should disable the transmitter/receiver
|
||||
* before calling this function.
|
||||
* Generally, this may be applied to all LPUARTs to ensure safe operation.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_SetSingleWireCmd(uint32_t baseAddr, bool enable)
|
||||
{
|
||||
/* configure lpuart to enable/disable operation in single mode */
|
||||
|
||||
/* to enable single-wire mode, need both LOOPS and RSRC set, to disable, clear both */
|
||||
BW_LPUART_CTRL_LOOPS(baseAddr, enable);
|
||||
BW_LPUART_CTRL_RSRC(baseAddr, enable);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_PutReceiverInStandbyMode
|
||||
* Description : Places the LPUART receiver in standby mode.
|
||||
* In some LPUART instances,
|
||||
* before placing LPUART in standby mode, first determine whether the receiver is set to
|
||||
* wake on idle or whether it is already in idle state.
|
||||
* NOTE that the RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently
|
||||
* not idle.
|
||||
* This can be determined by the S2[RAF] flag. If it is set to wake up an IDLE event and the channel is
|
||||
* already idle, it is possible that the LPUART will discard data since data must be received
|
||||
* (or a LIN break detect) after an IDLE is detected and before IDLE is allowed to reasserted.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_status_t LPUART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr)
|
||||
{
|
||||
/* In some lpuart instances, there is a condition that must be met before placing */
|
||||
/* rx in standby mode. */
|
||||
/* Before placing lpuart in standby, need to first determine if receiver is set to */
|
||||
/* wake on idle and if receiver is already in idle state. Per ref manual: */
|
||||
/* NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is */
|
||||
/* currently not idle. */
|
||||
/* This can be determined by the STAT[RAF] flag. If set to wake up an IDLE event and */
|
||||
/* the channel is already idle, it is possible that the LPUART will discard data since data */
|
||||
/* must be received (or a LIN break detect) after an IDLE is detected before IDLE is */
|
||||
/* allowed to reasserted. */
|
||||
lpuart_wakeup_method_t rxWakeMethod;
|
||||
bool lpuart_current_rx_state;
|
||||
|
||||
/* see if wake is set for idle or */
|
||||
rxWakeMethod = LPUART_HAL_GetReceiverWakeupMethod(baseAddr);
|
||||
lpuart_current_rx_state = LPUART_HAL_GetStatusFlag(baseAddr, kLpuartRxActive);
|
||||
|
||||
/* if both rxWakeMethod is set for idle and current rx state is idle, don't put in standy */
|
||||
if ((rxWakeMethod == kLpuartIdleLineWake) && (lpuart_current_rx_state == 0))
|
||||
{
|
||||
return kStatus_LPUART_RxStandbyModeError;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* set the RWU bit to place receiver into standby mode */
|
||||
BW_LPUART_CTRL_RWU(baseAddr, 1);
|
||||
return kStatus_LPUART_Success;
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_GetReceiverWakeupMethod
|
||||
* Description : Gets the LPUART receiver wakeup method (idle line or addr-mark) from standby mode.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_wakeup_method_t LPUART_HAL_GetReceiverWakeupMethod(uint32_t baseAddr)
|
||||
{
|
||||
/* get configuration of the WAKE bit for idle line wake or address mark wake */
|
||||
if(HW_LPUART_CTRL(baseAddr).B.WAKE == 1)
|
||||
{
|
||||
return kLpuartAddrMarkWake;
|
||||
}
|
||||
else
|
||||
{
|
||||
return kLpuartIdleLineWake;
|
||||
}
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_ConfigureIdleLineDetect
|
||||
* Description : LPUART idle-line detect operation configuration (idle line bit-count start and wake
|
||||
* up affect on IDLE status bit).
|
||||
* In some LPUART instances, the user should disable the transmitter/receiver
|
||||
* before calling this function.
|
||||
* Generally, this may be applied to all LPUARTs to ensure safe operation.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_ConfigureIdleLineDetect(uint32_t baseAddr,
|
||||
const lpuart_idle_line_config_t *config)
|
||||
{
|
||||
/* Configure the idle line detection configuration as follows: */
|
||||
/* configure the ILT to bit count after start bit or stop bit */
|
||||
/* configure RWUID to set or not set IDLE status bit upon detection of */
|
||||
/* an idle character when recevier in standby */
|
||||
BW_LPUART_CTRL_ILT(baseAddr, config->idleLineType);
|
||||
BW_LPUART_STAT_RWUID(baseAddr, config->rxWakeIdleDetect);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetMatchAddressOperation
|
||||
* Description : LPUART configures match address mode control (Note: Feature available on
|
||||
* select LPUART instances)
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_status_t LPUART_HAL_SetMatchAddressOperation( uint32_t baseAddr,
|
||||
bool matchAddrMode1, bool matchAddrMode2,
|
||||
uint8_t matchAddrValue1, uint8_t matchAddrValue2, lpuart_match_config_t config)
|
||||
{
|
||||
BW_LPUART_BAUD_MAEN1(baseAddr, matchAddrMode1); /* Match Address Mode Enable 1 */
|
||||
BW_LPUART_BAUD_MAEN2(baseAddr, matchAddrMode2); /* Match Address Mode Enable 2 */
|
||||
BW_LPUART_MATCH_MA1(baseAddr, matchAddrValue1); /* match address register 1 */
|
||||
BW_LPUART_MATCH_MA2(baseAddr, matchAddrValue2); /* match address register 2 */
|
||||
BW_LPUART_BAUD_MATCFG(baseAddr, config); /* Match Configuration */
|
||||
|
||||
return kStatus_LPUART_Success;
|
||||
}
|
||||
|
||||
#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_SetInfraredOperation
|
||||
* Description : Configures the LPUART infrared operation.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable,
|
||||
lpuart_ir_tx_pulsewidth_t pulseWidth)
|
||||
{
|
||||
/* enable or disable infrared */
|
||||
BW_LPUART_MODIR_IREN(baseAddr, enable);
|
||||
|
||||
/* configure the narrow pulse width of the IR pulse */
|
||||
BW_LPUART_MODIR_TNP(baseAddr, pulseWidth);
|
||||
}
|
||||
#endif /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_GetStatusFlag
|
||||
* Description : LPUART get status flag by passing flag enum.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
bool LPUART_HAL_GetStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag)
|
||||
{
|
||||
uint32_t reg = (uint32_t)(statusFlag) >> LPUART_SHIFT;
|
||||
bool retVal = false;
|
||||
|
||||
switch ( reg )
|
||||
{
|
||||
case LPUART_BAUD_REG_ID:
|
||||
retVal = HW_LPUART_BAUD_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
|
||||
break;
|
||||
case LPUART_STAT_REG_ID:
|
||||
retVal = HW_LPUART_STAT_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
|
||||
break;
|
||||
case LPUART_CTRL_REG_ID:
|
||||
retVal = HW_LPUART_CTRL_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
|
||||
break;
|
||||
case LPUART_DATA_REG_ID:
|
||||
retVal = HW_LPUART_DATA_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
|
||||
break;
|
||||
case LPUART_MATCH_REG_ID:
|
||||
retVal = HW_LPUART_MATCH_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
|
||||
break;
|
||||
case LPUART_MODIR_REG_ID:
|
||||
retVal = HW_LPUART_MODIR_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_ClearStatusFlag
|
||||
* Description : LPUART clears an individual status flag
|
||||
* (see lpuart_status_flag_t for list of status bits).
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_status_t LPUART_HAL_ClearStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag)
|
||||
{
|
||||
lpuart_status_t returnCode = kStatus_LPUART_Success;
|
||||
|
||||
/* clear the desired, individual status flag as passed in through statusFlag */
|
||||
switch(statusFlag)
|
||||
{
|
||||
case kLpuartTxDataRegEmpty:
|
||||
/* This flag is cleared automatically by other lpuart operations */
|
||||
/* and cannot be manually cleared, return error code */
|
||||
returnCode = kStatus_LPUART_ClearStatusFlagError;
|
||||
break;
|
||||
|
||||
case kLpuartTxComplete:
|
||||
/* This flag is cleared automatically by other lpuart operations */
|
||||
/* and cannot be manually cleared, return error code */
|
||||
returnCode = kStatus_LPUART_ClearStatusFlagError;
|
||||
break;
|
||||
|
||||
case kLpuartRxDataRegFull:
|
||||
/* This flag is cleared automatically by other lpuart operations and */
|
||||
/* cannot be manually cleared, return error code */
|
||||
returnCode = kStatus_LPUART_ClearStatusFlagError;
|
||||
break;
|
||||
|
||||
case kLpuartIdleLineDetect:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_IDLE(baseAddr, 1);
|
||||
break;
|
||||
|
||||
case kLpuartRxOverrun:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_OR(baseAddr, 1);
|
||||
break;
|
||||
|
||||
case kLpuartNoiseDetect:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_NF(baseAddr, 1);
|
||||
break;
|
||||
|
||||
case kLpuartFrameErr:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_FE(baseAddr, 1);
|
||||
break;
|
||||
|
||||
case kLpuartParityErr:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_PF(baseAddr, 1);
|
||||
break;
|
||||
|
||||
case kLpuartLineBreakDetect:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_LBKDIF(baseAddr, 1);
|
||||
break;
|
||||
|
||||
case kLpuartRxActiveEdgeDetect:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_RXEDGIF(baseAddr, (1U));
|
||||
break;
|
||||
|
||||
case kLpuartRxActive:
|
||||
/* This flag is cleared automatically by other lpuart operations and */
|
||||
/* cannot be manually cleared, return error code */
|
||||
returnCode = kStatus_LPUART_ClearStatusFlagError;
|
||||
break;
|
||||
|
||||
#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
|
||||
case kLpuartNoiseInCurrentWord:
|
||||
/* This flag is not clearable, it simply reflects the status in the */
|
||||
/* current data word and changes with each new data word */
|
||||
returnCode = kStatus_LPUART_ClearStatusFlagError;
|
||||
break;
|
||||
|
||||
case kLpuartParityErrInCurrentWord:
|
||||
/* This flag is not clearable, it simply reflects the status in the */
|
||||
/* current data word and changes with each new data word */
|
||||
returnCode = kStatus_LPUART_ClearStatusFlagError;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
|
||||
case kLpuartMatchAddrOne:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_MA1F(baseAddr, 1);
|
||||
break;
|
||||
case kLpuartMatchAddrTwo:
|
||||
/* write one to clear status flag */
|
||||
BW_LPUART_STAT_MA2F(baseAddr, 1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default: /* catch inputs that are not recognized */
|
||||
returnCode = kStatus_LPUART_ClearStatusFlagError;
|
||||
break;
|
||||
}
|
||||
|
||||
return (returnCode);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_ClearAllNonAutoclearStatusFlags
|
||||
* Description : LPUART clears ALL status flags.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr)
|
||||
{
|
||||
/* clear the status flags that can be manually cleared */
|
||||
/* note, some flags are automatically cleared and cannot be cleared automatically */
|
||||
LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartIdleLineDetect);
|
||||
LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartRxOverrun);
|
||||
LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartNoiseDetect);
|
||||
LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartFrameErr);
|
||||
LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartParityErr);
|
||||
LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartLineBreakDetect);
|
||||
LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartRxActiveEdgeDetect);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_Putchar9
|
||||
* Description : Sends the LPUART 9-bit character.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_Putchar9(uint32_t baseAddr, uint16_t data)
|
||||
{
|
||||
uint8_t ninthDataBit;
|
||||
|
||||
ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit */
|
||||
|
||||
/* put 9-bit data to transmit */
|
||||
|
||||
/* first, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, T8=9th bit) */
|
||||
BW_LPUART_CTRL_R9T8(baseAddr, ninthDataBit);
|
||||
|
||||
/* write to the data register last since this will trigger transmit complete status flag */
|
||||
/* also typecast to uint8_t to match register type */
|
||||
HW_LPUART_DATA_WR(baseAddr, (uint8_t)data);
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_Putchar10
|
||||
* Description : Sends the LPUART 10-bit character.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_status_t LPUART_HAL_Putchar10(uint32_t baseAddr, uint16_t data)
|
||||
{
|
||||
uint8_t ninthDataBit;
|
||||
uint8_t tenthDataBit;
|
||||
|
||||
/* put 10-bit data to transmit */
|
||||
ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit */
|
||||
tenthDataBit = (data >> 9U) & 0x1U; /* isolate the tenth data bit */
|
||||
|
||||
/* first, write to the tenth data bit (bit position T9, where T[0:7]=8-bits, */
|
||||
/* T9=10th bit, T8=9th bit) */
|
||||
BW_LPUART_CTRL_R8T9(baseAddr, tenthDataBit);
|
||||
|
||||
/* next, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, */
|
||||
/* T9=10th bit, T8=9th bit) */
|
||||
BW_LPUART_CTRL_R9T8(baseAddr, ninthDataBit);
|
||||
|
||||
/* write to the data register last since this will trigger transmit complete status flag */
|
||||
/* also typecast to uint8_t to match register type */
|
||||
HW_LPUART_DATA_WR(baseAddr, (uint8_t)data);
|
||||
|
||||
return kStatus_LPUART_Success;
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_Getchar
|
||||
* Description : Gets the LPUART 8-bit character.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData)
|
||||
{
|
||||
/* get 8-bit data from the lpuart data register */
|
||||
*readData = (uint8_t)HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_Getchar9
|
||||
* Description : Gets the LPUART 9-bit character.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void LPUART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
/* get 9-bit data from the lpuart data register */
|
||||
/* read ninth data bit and left shift to bit position R8 before reading */
|
||||
/* the 8 other data bits R[7:0] */
|
||||
temp = HW_LPUART_CTRL(baseAddr).B.R8T9; /* need this two step process to work around mishra rule */
|
||||
*readData = temp << 8;
|
||||
|
||||
/* do last: get 8-bit data from the lpuart data register, will clear certain */
|
||||
/* receive status bits once completed */
|
||||
/* need to OR these 8-bits with the ninth bit value above */
|
||||
*readData |= (uint8_t)HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */
|
||||
}
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : LPUART_HAL_Getchar10
|
||||
* Description : Gets the LPUART 10-bit character.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
lpuart_status_t LPUART_HAL_Getchar10(uint32_t baseAddr, uint16_t *readData)
|
||||
{
|
||||
/* get 10-bit data from the lpuart data register, available only on supported lpuarts */
|
||||
|
||||
/* read tenth data bit and left shift to bit position R9 before reading the 9 other */
|
||||
/* data bits: R8 and R[7:0] */
|
||||
*readData = (uint16_t)((uint32_t)(HW_LPUART_CTRL(baseAddr).B.R9T8) << 9U);
|
||||
|
||||
/* read ninth data bit and left shift to bit position R8 before reading the 8 other */
|
||||
/* data bits R[7:0] */
|
||||
*readData |= (uint16_t)((uint32_t)(HW_LPUART_CTRL(baseAddr).B.R8T9) << 8U);
|
||||
|
||||
/* do last: get 8-bit data from the lpuart data register, will clear certain receive */
|
||||
/* status bits once completed */
|
||||
/* need to OR these 8-bits with the ninth bit value above */
|
||||
*readData |= HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */
|
||||
|
||||
return kStatus_LPUART_Success;
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_LPUART */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -136,7 +136,7 @@
|
|||
/* @brief Has master 7. */
|
||||
#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#define MBED_NO_MPU
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_MPU_FEATURES_H__ */
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@
|
|||
|
||||
#include "fsl_mpu_hal.h"
|
||||
|
||||
#ifndef MBED_NO_MPU
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
*******************************************************************************/
|
||||
|
|
@ -65,3 +67,5 @@ void MPU_HAL_Init(uint32_t baseAddr)
|
|||
MPU_HAL_SetRegionEndAddr(baseAddr, (mpu_region_num)i, (uint32_t)0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_MPU */
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@
|
|||
#include "fsl_mpu_features.h"
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
#ifndef MBED_NO_MPU
|
||||
|
||||
#define MPU_REGION_NUMBER 12
|
||||
|
||||
/*!
|
||||
|
|
@ -1534,6 +1536,8 @@ void MPU_HAL_Init(uint32_t baseAddr);
|
|||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* MBED_NO_MPU */
|
||||
|
||||
#endif /* __FSL_MPU_HAL_H__*/
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@
|
|||
/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
|
||||
#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (1)
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#define MBED_NO_SDHC
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_SDHC_FEATURES_H__ */
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
*/
|
||||
#include "fsl_sdhc_hal.h"
|
||||
|
||||
#ifndef MBED_NO_SDHC
|
||||
|
||||
/*FUNCTION****************************************************************
|
||||
*
|
||||
* Function Name: SDHC_HAL_Init
|
||||
|
|
@ -158,6 +160,7 @@ uint32_t SDHC_HAL_Reset(uint32_t baseAddr, uint32_t type, uint32_t timeout)
|
|||
return (!timeout);
|
||||
}
|
||||
|
||||
#endif /* MBED_NO_SDHC */
|
||||
|
||||
/*************************************************************************************************
|
||||
* EOF
|
||||
|
|
|
|||
|
|
@ -33,6 +33,9 @@
|
|||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_sdhc_features.h"
|
||||
|
||||
#ifndef MBED_NO_SDHC
|
||||
|
||||
/*! @addtogroup sdhc_hal */
|
||||
/*! @{ */
|
||||
|
|
@ -1223,6 +1226,8 @@ void SDHC_HAL_Init(uint32_t baseAddr);
|
|||
#endif
|
||||
/*! @} */
|
||||
|
||||
#endif /* MBED_NO_SDHC */
|
||||
|
||||
#endif
|
||||
|
||||
/*************************************************************************************************
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
This document is not complete, please try to add more to it to keep it as much up-to-date as possible.
|
||||
|
||||
*************ADDING NEW TARGET*************
|
||||
TODO (partially)
|
||||
|
||||
UNAVAILABLE PERIPHERALS:
|
||||
The original build system of the KSDK simply does not compile files which are not available on a target, mbed tries to compile everything. If your target tries to compile a peripheral which is not available, compilation will fail with a "No valid CPU defined!" error message. In the file which throws the error, replace the error code with: #define MBED_NO_[PERIPHERAL-NAME]. Then in the other .h and .c file in the same folder add #ifndef guards. See for an example: \mbed\targets\hal\TARGET_Freescale\TARGET_KPSDK_MCUS\TARGET_KPSDK_CODE\hal\lpuart.
|
||||
|
||||
SYSTEM_MKXXXXX.C:
|
||||
The file included in the top cannot be found by the compiler, replace it by cmsis.h
|
||||
|
||||
|
||||
|
||||
************UPDATING KSDK FILES************
|
||||
TODO (Also good luck with it).
|
||||
Loading…
Reference in New Issue