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Merge pull request #4025 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.4.2
pull/4022/merge mbed_lib_rev139
Martin Kojtal 2017-03-29 10:58:25 +01:00 committed by GitHub
parent f4864dc642 0edca5ad20
commit 50b3418e45
1044 changed files with 243636 additions and 37458 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
TESTS/mbed_hal/flash/functional_tests/main.cpp
View File

@ -49,6 +49,7 @@ static void erase_range(flash_t *flash, uint32_t addr, uint32_t size)
TEST_ASSERT_NOT_EQUAL(0, sector_size);
int32_t ret = flash_erase_sector(flash, addr);
TEST_ASSERT_EQUAL_INT32(0, ret);
addr += sector_size;
size = size > sector_size ? size - sector_size : 0;
}
}

4
drivers/I2C.h
View File

@ -117,8 +117,8 @@ public:
* @param repeated Repeated start, true - do not send stop at end
*
* @returns
* 0 or non-zero - written number of bytes,
* negative - I2C_ERROR_XXX status
* 0 on success (ack),
* non-0 on failure (nack)
*/
int write(int address, const char *data, int length, bool repeated = false);

12
features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md
View File

@ -1,5 +1,17 @@
# Change Log
## [v4.0.3](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.3)
-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.2...v4.0.3)
**New feature**
- CoAP Protocol Confirmable resend fix and minor memory optimization (IOTMAC-328)
**Closed issues:**
- IOTCLT-1439 - stuck in while loop
## [v4.0.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.2)
**New feature**

3
features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h
View File

@ -83,7 +83,8 @@ extern int8_t sn_coap_protocol_destroy(struct coap_s *handle);
* In failure cases:\n
* -1 = Failure in CoAP header structure\n
* -2 = Failure in given pointer (= NULL)\n
* -3 = Failure in Reset message\ŋ
* -3 = Failure in Reset message\n
* -4 = Failure in Resending message store\n
* If there is not enough memory (or User given limit exceeded) for storing
* resending messages, situation is ignored.
*/

2
features/FEATURE_COMMON_PAL/mbed-coap/module.json
View File

@ -1,6 +1,6 @@
{
"name": "mbed-coap",
"version": "4.0.2",
"version": "4.0.3",
"description": "COAP library",
"keywords": [
"coap",

2
features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_header_internal.h
View File

@ -64,8 +64,6 @@ typedef struct sn_nsdl_transmit_ {
uint16_t packet_len;
uint8_t *packet_ptr;
uint8_t *uri_path_ptr;
uint8_t uri_path_len;
} sn_nsdl_transmit_s;
/* * * * * * * * * * * * * * * * * * * * * * */

30
features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c
View File

@ -174,21 +174,16 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(sn_coap_hdr_s *src_coap_
returned_byte_count += src_coap_msg_ptr->token_len;
}
/* URI PATH - Repeatable option. Length of one option is 0-255 */
/* Do not add uri-path for notification message.
* Uri-path is needed for cancelling observation with RESET message */
if (!src_coap_msg_ptr->options_list_ptr ||
(src_coap_msg_ptr->options_list_ptr &&
COAP_OBSERVE_NONE == src_coap_msg_ptr->options_list_ptr->observe)) {
if (src_coap_msg_ptr->uri_path_ptr != NULL) {
repeatable_option_size = sn_coap_builder_options_calc_option_size(src_coap_msg_ptr->uri_path_len,
src_coap_msg_ptr->uri_path_ptr, COAP_OPTION_URI_PATH);
if (repeatable_option_size) {
returned_byte_count += repeatable_option_size;
} else {
return 0;
}
if (src_coap_msg_ptr->uri_path_ptr != NULL) {
repeatable_option_size = sn_coap_builder_options_calc_option_size(src_coap_msg_ptr->uri_path_len,
src_coap_msg_ptr->uri_path_ptr, COAP_OPTION_URI_PATH);
if (repeatable_option_size) {
returned_byte_count += repeatable_option_size;
} else {
return 0;
}
}
uint16_t tempInt = 0;
/* CONTENT FORMAT - An integer option, up to 2 bytes */
if (src_coap_msg_ptr->content_format != COAP_CT_NONE) {
@ -574,13 +569,8 @@ static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, sn_c
&src_coap_msg_ptr->options_list_ptr->location_path_len, COAP_OPTION_LOCATION_PATH, &previous_option_number);
}
/* * * * Build Uri-Path option * * * */
/* Do not add uri-path for notification message.
* Uri-path is needed for cancelling observation with RESET message */
if (!src_coap_msg_ptr->options_list_ptr ||
(src_coap_msg_ptr->options_list_ptr &&
COAP_OBSERVE_NONE == src_coap_msg_ptr->options_list_ptr->observe))
sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, &src_coap_msg_ptr->uri_path_ptr,
&src_coap_msg_ptr->uri_path_len, COAP_OPTION_URI_PATH, &previous_option_number);
sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, &src_coap_msg_ptr->uri_path_ptr,
&src_coap_msg_ptr->uri_path_len, COAP_OPTION_URI_PATH, &previous_option_number);
/* * * * Build Content-Type option * * * */
if (src_coap_msg_ptr->content_format != COAP_CT_NONE) {

26
features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_parser.c
View File

@ -35,7 +35,6 @@
#include "mbed-coap/sn_coap_protocol.h"
#include "sn_coap_header_internal.h"
#include "sn_coap_protocol_internal.h"
/* * * * * * * * * * * * * * * * * * * * */
/* * * * LOCAL FUNCTION PROTOTYPES * * * */
/* * * * * * * * * * * * * * * * * * * * */
@ -315,6 +314,7 @@ static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **pack
(*packet_data_pptr) += 2;
}
message_left = packet_len - (*packet_data_pptr - packet_data_start_ptr);
/* * * Parse option itself * * */
/* Some options are handled independently in own functions */
@ -655,7 +655,7 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_
uint16_t i = 1;
/* Loop all Uri-Query options */
while (i < packet_left_len) {
while (i <= packet_left_len) {
if (option == COAP_OPTION_LOCATION_PATH && option_number_len > 255) {
return -1;
}
@ -677,14 +677,13 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_
i += option_number_len;
ret_value += option_number_len + 1; /* + 1 is for separator */
if(ret_value >= packet_left_len)
break;
if(ret_value >= packet_left_len)
break;
if( i == packet_left_len )
if( i == packet_left_len ) {
break;
}
else if( i > packet_left_len ) {
return -1;
}
if ((*(packet_data_ptr + i) >> COAP_OPTIONS_OPTION_NUMBER_SHIFT) != 0) {
return (ret_value - 1); /* -1 because last Part path does not include separator */
@ -693,9 +692,19 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_
option_number_len = (*(packet_data_ptr + i) & 0x0F);
if (option_number_len == 13) {
if(i + 1 >= packet_left_len) {
return -1;
}
i++;
option_number_len = *(packet_data_ptr + i) + 13;
} else if (option_number_len == 14) {
if(i + 2 >= packet_left_len) {
return -1;
}
option_number_len = *(packet_data_ptr + i + 2);
option_number_len += (*(packet_data_ptr + i + 1) << 8) + 269;
i += 2;
@ -750,3 +759,4 @@ static int8_t sn_coap_parser_payload_parse(uint16_t packet_data_len, uint8_t *pa
}
return 0;
}

155
features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c
View File

@ -67,7 +67,7 @@ static int8_t sn_coap_convert_block_size(uint16_t block_size);
static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *handle, sn_coap_hdr_s *source_header_ptr);
#endif
#if ENABLE_RESENDINGS
static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param, uint8_t *uri_path_ptr, uint8_t uri_path_len);
static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param);
static sn_nsdl_transmit_s *sn_coap_protocol_linked_list_send_msg_search(struct coap_s *handle,sn_nsdl_addr_s *src_addr_ptr, uint16_t msg_id);
static void sn_coap_protocol_linked_list_send_msg_remove(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, uint16_t msg_id);
static coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t packet_data_len);
@ -300,30 +300,9 @@ void sn_coap_protocol_clear_retransmission_buffer(struct coap_s *handle)
return;
}
ns_list_foreach_safe(coap_send_msg_s, tmp, &handle->linked_list_resent_msgs) {
if (tmp->send_msg_ptr) {
if (tmp->send_msg_ptr->dst_addr_ptr) {
if (tmp->send_msg_ptr->dst_addr_ptr->addr_ptr) {
handle->sn_coap_protocol_free(tmp->send_msg_ptr->dst_addr_ptr->addr_ptr);
tmp->send_msg_ptr->dst_addr_ptr->addr_ptr = 0;
}
handle->sn_coap_protocol_free(tmp->send_msg_ptr->dst_addr_ptr);
tmp->send_msg_ptr->dst_addr_ptr = 0;
}
if (tmp->send_msg_ptr->packet_ptr) {
handle->sn_coap_protocol_free(tmp->send_msg_ptr->packet_ptr);
tmp->send_msg_ptr->packet_ptr = 0;
}
if (tmp->send_msg_ptr->uri_path_ptr) {
handle->sn_coap_protocol_free(tmp->send_msg_ptr->uri_path_ptr);
tmp->send_msg_ptr->uri_path_ptr = 0;
}
handle->sn_coap_protocol_free(tmp->send_msg_ptr);
tmp->send_msg_ptr = 0;
}
ns_list_remove(&handle->linked_list_resent_msgs, tmp);
sn_coap_protocol_release_allocated_send_msg_mem(handle, tmp);
--handle->count_resent_msgs;
handle->sn_coap_protocol_free(tmp);
tmp = 0;
}
#endif
}
@ -445,9 +424,11 @@ int16_t sn_coap_protocol_build(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_p
/* Check if built Message type was confirmable, only these messages are resent */
if (src_coap_msg_ptr->msg_type == COAP_MSG_TYPE_CONFIRMABLE) {
/* Store message to Linked list for resending purposes */
sn_coap_protocol_linked_list_send_msg_store(handle, dst_addr_ptr, byte_count_built, dst_packet_data_ptr,
if (sn_coap_protocol_linked_list_send_msg_store(handle, dst_addr_ptr, byte_count_built, dst_packet_data_ptr,
handle->system_time + (uint32_t)(handle->sn_coap_resending_intervall * RESPONSE_RANDOM_FACTOR),
param, src_coap_msg_ptr->uri_path_ptr, src_coap_msg_ptr->uri_path_len);
param) == 0) {
return -4;
}
}
#endif /* ENABLE_RESENDINGS */
@ -702,15 +683,6 @@ sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src
removed_msg_ptr = sn_coap_protocol_linked_list_send_msg_search(handle, src_addr_ptr, returned_dst_coap_msg_ptr->msg_id);
if (removed_msg_ptr != NULL) {
if (returned_dst_coap_msg_ptr->msg_type == COAP_MSG_TYPE_RESET) {
if(removed_msg_ptr->uri_path_len) {
returned_dst_coap_msg_ptr->uri_path_ptr = handle->sn_coap_protocol_malloc(removed_msg_ptr->uri_path_len);
if (returned_dst_coap_msg_ptr->uri_path_ptr != NULL) {
memcpy(returned_dst_coap_msg_ptr->uri_path_ptr, removed_msg_ptr->uri_path_ptr, removed_msg_ptr->uri_path_len);
returned_dst_coap_msg_ptr->uri_path_len = removed_msg_ptr->uri_path_len;
}
}
}
/* Remove resending message from active message resending Linked list */
sn_coap_protocol_linked_list_send_msg_remove(handle, src_addr_ptr, returned_dst_coap_msg_ptr->msg_id);
}
@ -799,7 +771,7 @@ int8_t sn_coap_protocol_exec(struct coap_s *handle, uint32_t current_time)
#if ENABLE_RESENDINGS /* If Message resending is not used at all, this part of code will not be compiled */
/**************************************************************************//**
* \fn static void sn_coap_protocol_linked_list_send_msg_store(sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time)
* \fn static uint8_t sn_coap_protocol_linked_list_send_msg_store(sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time)
*
* \brief Stores message to Linked list for sending purposes.
@ -810,29 +782,33 @@ int8_t sn_coap_protocol_exec(struct coap_s *handle, uint32_t current_time)
* \param *send_packet_data_ptr is Packet data to be stored
*
* \param sending_time is stored sending time
*
* \return 0 Allocation or buffer limit reached
*
* \return 1 Msg stored properly
*****************************************************************************/
static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len,
uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param, uint8_t *uri_path_ptr, uint8_t uri_path_len)
static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len,
uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param)
{
coap_send_msg_s *stored_msg_ptr = NULL;
/* If both queue parameters are "0" or resending count is "0", then re-sending is disabled */
if (((handle->sn_coap_resending_queue_msgs == 0) && (handle->sn_coap_resending_queue_bytes == 0)) || (handle->sn_coap_resending_count == 0)) {
return;
return 1;
}
if (handle->sn_coap_resending_queue_msgs > 0) {
if (handle->count_resent_msgs >= handle->sn_coap_resending_queue_msgs) {
return;
return 0;
}
}
/* Count resending queue size, if buffer size is defined */
if (handle->sn_coap_resending_queue_bytes > 0) {
if ((sn_coap_count_linked_list_size(&handle->linked_list_resent_msgs) + send_packet_data_len) > handle->sn_coap_resending_queue_bytes) {
return;
return 0;
}
}
@ -840,7 +816,7 @@ static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, s
stored_msg_ptr = sn_coap_protocol_allocate_mem_for_msg(handle, dst_addr_ptr, send_packet_data_len);
if (stored_msg_ptr == 0) {
return;
return 0;
}
/* Filling of coap_send_msg_s with initialization values */
@ -861,19 +837,10 @@ static void sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, s
stored_msg_ptr->coap = handle;
stored_msg_ptr->param = param;
if (uri_path_len) {
stored_msg_ptr->send_msg_ptr->uri_path_ptr = handle->sn_coap_protocol_malloc(uri_path_len);
if (stored_msg_ptr->send_msg_ptr->uri_path_ptr == NULL){
return;
}
stored_msg_ptr->send_msg_ptr->uri_path_len = uri_path_len;
memcpy(stored_msg_ptr->send_msg_ptr->uri_path_ptr, uri_path_ptr, uri_path_len);
}
/* Storing Resending message to Linked list */
ns_list_add_to_end(&handle->linked_list_resent_msgs, stored_msg_ptr);
++handle->count_resent_msgs;
return 1;
}
/**************************************************************************//**
@ -1367,6 +1334,7 @@ static void sn_coap_protocol_linked_list_blockwise_remove_old_data(struct coap_s
*
* \param *dst_addr_ptr is pointer to destination address where message will be sent
* \param packet_data_len is length of allocated Packet data
* \param uri_path_len is length of messages path url
*
* \return pointer to allocated struct
*****************************************************************************/
@ -1377,45 +1345,35 @@ coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn
coap_send_msg_s *msg_ptr = handle->sn_coap_protocol_malloc(sizeof(coap_send_msg_s));
if (msg_ptr == NULL) {
return 0;
return NULL;
}
//Locall structure for 1 malloc for send msg
struct
{
sn_nsdl_transmit_s transmit;
sn_nsdl_addr_s addr;
uint8_t trail_data[];
} *m;
int trail_size = dst_addr_ptr->addr_len + packet_data_len;
m = handle->sn_coap_protocol_malloc(sizeof *m + trail_size);
if (!m) {
handle->sn_coap_protocol_free(msg_ptr);
return NULL;
}
//Init data
memset(m, 0, sizeof(*m) + trail_size);
memset(msg_ptr, 0, sizeof(coap_send_msg_s));
msg_ptr->send_msg_ptr = handle->sn_coap_protocol_malloc(sizeof(sn_nsdl_transmit_s));
msg_ptr->send_msg_ptr = &m->transmit;
msg_ptr->send_msg_ptr->dst_addr_ptr = &m->addr;
if (msg_ptr->send_msg_ptr == NULL) {
sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr);
return 0;
msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr = m->trail_data;
if (packet_data_len) {
msg_ptr->send_msg_ptr->packet_ptr = m->trail_data + dst_addr_ptr->addr_len;
}
memset(msg_ptr->send_msg_ptr, 0 , sizeof(sn_nsdl_transmit_s));
msg_ptr->send_msg_ptr->dst_addr_ptr = handle->sn_coap_protocol_malloc(sizeof(sn_nsdl_addr_s));
if (msg_ptr->send_msg_ptr->dst_addr_ptr == NULL) {
sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr);
return 0;
}
memset(msg_ptr->send_msg_ptr->dst_addr_ptr, 0, sizeof(sn_nsdl_addr_s));
msg_ptr->send_msg_ptr->packet_ptr = handle->sn_coap_protocol_malloc(packet_data_len);
if (msg_ptr->send_msg_ptr->packet_ptr == NULL) {
sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr);
return 0;
}
msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr = handle->sn_coap_protocol_malloc(dst_addr_ptr->addr_len);
if (msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr == NULL) {
sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr);
return 0;
}
memset(msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr, 0, dst_addr_ptr->addr_len);
return msg_ptr;
}
@ -1431,33 +1389,10 @@ coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn
static void sn_coap_protocol_release_allocated_send_msg_mem(struct coap_s *handle, coap_send_msg_s *freed_send_msg_ptr)
{
if (freed_send_msg_ptr != NULL) {
if (freed_send_msg_ptr->send_msg_ptr != NULL) {
if (freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr != NULL) {
if (freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr != NULL) {
handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr);
freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr->addr_ptr = 0;
}
handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr);
freed_send_msg_ptr->send_msg_ptr->dst_addr_ptr = 0;
}
if (freed_send_msg_ptr->send_msg_ptr->packet_ptr != NULL) {
handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->packet_ptr);
freed_send_msg_ptr->send_msg_ptr->packet_ptr = 0;
}
if (freed_send_msg_ptr->send_msg_ptr->uri_path_ptr != NULL) {
handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr->uri_path_ptr);
freed_send_msg_ptr->send_msg_ptr->uri_path_ptr = 0;
}
handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr);
freed_send_msg_ptr->send_msg_ptr = 0;
}
handle->sn_coap_protocol_free(freed_send_msg_ptr->send_msg_ptr);
freed_send_msg_ptr->send_msg_ptr = NULL;
handle->sn_coap_protocol_free(freed_send_msg_ptr);
freed_send_msg_ptr = 0;
freed_send_msg_ptr = NULL;
}
}
@ -1877,7 +1812,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
sn_coap_protocol_linked_list_send_msg_store(handle, src_addr_ptr,
dst_packed_data_needed_mem,
dst_ack_packet_data_ptr,
handle->system_time + (uint32_t)(handle->sn_coap_resending_intervall * RESPONSE_RANDOM_FACTOR), param, NULL, 0);
handle->system_time + (uint32_t)(handle->sn_coap_resending_intervall * RESPONSE_RANDOM_FACTOR), param);
#endif
handle->sn_coap_protocol_free(dst_ack_packet_data_ptr);
dst_ack_packet_data_ptr = 0;

1
features/FEATURE_COMMON_PAL/mbed-trace/.yotta_ignore
View File

@ -0,0 +1 @@
/*CMakeLists.txt

17
features/FEATURE_COMMON_PAL/mbed-trace/CMakeLists.txt Executable file
View File

@ -0,0 +1,17 @@
INCLUDE(CMakeForceCompiler)
cmake_minimum_required (VERSION 2.8)
SET(CMAKE_SYSTEM_NAME Generic)
project(mbedTrace)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/mbed-trace/)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../nanostack-libservice/mbed-client-libservice/)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../nanostack-libservice/)
set (MBED_TRACE_SRC ${CMAKE_CURRENT_SOURCE_DIR}/source/mbed_trace.c)
CREATE_LIBRARY(mbedTrace "${MBED_TRACE_SRC}" "")

18
features/FEATURE_COMMON_PAL/mbed-trace/README.md
View File

@ -33,9 +33,9 @@ The purpose of the library is to provide a light, simple and general tracing sol
```
[DBG ][abc ]: This is a debug message from module abc<cr><lf>
[ERR ][abc ]: Something goes wrong in module abc<cr><lf>
[WARN][br ]: Oh no, br warning occurs!<cr><lf>
[INFO][br ]: Hi there.<cr><lf>
[WARN][br ]: Oh no, br warning occurs!<cr><lf>
[ERR ][abc ]: Something goes wrong in module abc<cr><lf>
```
## Usage
@ -47,8 +47,10 @@ The purpose of the library is to provide a light, simple and general tracing sol
* To enable the tracing API:
* With yotta: set `YOTTA_CFG_MBED_TRACE` to 1 or true. Setting the flag to 0 or false disables tracing.
* [With mbed OS 5](#enabling-the-tracing-api-in-mbed-os-5)
* By default, trace uses 1024 bytes buffer for trace lines, but you can change it by yotta with: `YOTTA_CFG_MBED_TRACE_LINE_LENGTH`.
* To disable the IPv6 conversion, set `YOTTA_CFG_MBED_TRACE_FEA_IPV6 = 0`.
* By default, trace uses 1024 bytes buffer for trace lines, but you can change it by setting the configuration macro `MBED_TRACE_LINE_LENGTH` to the desired value.
* To disable the IPv6 conversion:
* With yotta: set `YOTTA_CFG_MBED_TRACE_FEA_IPV6 = 0`.
* With mbed OS 5: set `MBED_CONF_MBED_TRACE_FEA_IPV6 = 0`.
* If thread safety is needed, configure the wait and release callback functions before initialization to enable the protection. Usually, this needs to be done only once in the application's lifetime.
* Call the trace initialization (`mbed_trace_init`) once before using any other APIs. It allocates the trace buffer and initializes the internal variables.
* Define `TRACE_GROUP` in your source code (not in the header!) to use traces. It is a 1-4 characters long char-array (for example `#define TRACE_GROUP "APPL"`). This will be printed on every trace line.
@ -82,9 +84,9 @@ When you want to print traces, use the `tr_<level>` macros. The macros behave li
Available levels:
* debug
* info
* warning
* error
* info
* cmdline (special behavior, should not be used)
For the thread safety, set the mutex wait and release functions. You need do this before the initialization to have the functions available right away:
@ -128,7 +130,7 @@ See more in [mbed_trace.h](https://github.com/ARMmbed/mbed-trace/blob/master/mbe
## Usage example:
```c++
#define YOTTA_CFG_MBED_TRACE 1 //this can be defined also in the yotta configuration file config.json
#define MBED_CONF_MBED_TRACE_ENABLE 1 //this could be defined also in the mbed-cli configuration file mbed_app.json
#include "mbed-trace/mbed_trace.h"
#define TRACE_GROUP "main"
@ -148,9 +150,9 @@ int main(void){
mbed_trace_mutex_release_function_set( my_mutex_release ); // only if thread safety is needed
mbed_trace_init(); // initialize the trace library
tr_debug("this is debug msg"); //-> "[DBG ][main]: this is a debug msg"
tr_err("this is error msg"); //-> "[ERR ][main]: this is an error msg"
tr_warn("this is warning msg"); //-> "[WARN][main]: this is a warning msg"
tr_info("this is info msg"); //-> "[INFO][main]: this is an info msg"
tr_warn("this is warning msg"); //-> "[WARN][main]: this is a warning msg"
tr_err("this is error msg"); //-> "[ERR ][main]: this is an error msg"
char arr[] = {30, 31, 32};
tr_debug("printing array: %s", mbed_trace_array(arr, 3)); //-> "[DBG ][main]: printing array: 01:02:03"
return 0;

52
features/FEATURE_COMMON_PAL/mbed-trace/mbed-trace/mbed_trace.h
View File

@ -18,8 +18,8 @@
* \file mbed_trace.h
* Trace interface for MbedOS applications.
* This file provide simple but flexible way to handle software traces.
* Trace library are abstract layer, which use stdout (printf) by default,
* but outputs can be easily redirect to custom function, for example to
* Trace library are abstract layer, which use stdout (printf) by default,
* but outputs can be easily redirect to custom function, for example to
* store traces to memory or other interfaces.
*
* usage example:
@ -30,14 +30,15 @@
* int main(void){
* mbed_trace_init(); // initialize trace library
* tr_debug("this is debug msg"); //print debug message to stdout: "[DBG]
* tr_err("this is error msg");
* tr_warn("this is warning msg");
* tr_info("this is info msg");
* tr_warn("this is warning msg");
* tr_err("this is error msg");
* return 0;
* }
* \endcode
* Activate with compiler flag: YOTTA_CFG_MBED_TRACE
* Configure trace line buffer size with compiler flag: YOTTA_CFG_MBED_TRACE_LINE_LENGTH. Default length: 1024.
* Limit the size of flash by setting MBED_TRACE_MAX_LEVEL value. Default is TRACE_LEVEL_DEBUG (all included)
*
*/
#ifndef MBED_TRACE_H_
@ -63,12 +64,19 @@ extern "C" {
#ifndef YOTTA_CFG_MBED_TRACE_FEA_IPV6
#define YOTTA_CFG_MBED_TRACE_FEA_IPV6 1
#else
#warning YOTTA_CFG_MBED_TRACE_FEA_IPV6 is deprecated and will be removed in the future! Use MBED_CONF_MBED_TRACE_FEA_IPV6 instead.
#define MBED_CONF_MBED_TRACE_FEA_IPV6 YOTTA_CFG_MBED_TRACE_FEA_IPV6
#endif
#ifndef MBED_CONF_MBED_TRACE_ENABLE
#define MBED_CONF_MBED_TRACE_ENABLE 0
#endif
#ifndef MBED_CONF_MBED_TRACE_FEA_IPV6
#define MBED_CONF_MBED_TRACE_FEA_IPV6 1
#endif
/** 3 upper bits are trace modes related,
and 5 lower bits are trace level configuration */
@ -110,13 +118,39 @@ extern "C" {
/** special level for cmdline. Behaviours like "plain mode" */
#define TRACE_LEVEL_CMD 0x01
#ifndef MBED_TRACE_MAX_LEVEL
#define MBED_TRACE_MAX_LEVEL TRACE_LEVEL_DEBUG
#endif
//usage macros:
#define tr_info(...) mbed_tracef(TRACE_LEVEL_INFO, TRACE_GROUP, __VA_ARGS__) //!< Print info message
#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_DEBUG
#define tr_debug(...) mbed_tracef(TRACE_LEVEL_DEBUG, TRACE_GROUP, __VA_ARGS__) //!< Print debug message
#else
#define tr_debug(...)
#endif
#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_INFO
#define tr_info(...) mbed_tracef(TRACE_LEVEL_INFO, TRACE_GROUP, __VA_ARGS__) //!< Print info message
#else
#define tr_info(...)
#endif
#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_WARN
#define tr_warning(...) mbed_tracef(TRACE_LEVEL_WARN, TRACE_GROUP, __VA_ARGS__) //!< Print warning message
#define tr_warn(...) mbed_tracef(TRACE_LEVEL_WARN, TRACE_GROUP, __VA_ARGS__) //!< Alternative warning message
#else
#define tr_warning(...)
#define tr_warn(...)
#endif
#if MBED_TRACE_MAX_LEVEL >= TRACE_LEVEL_ERROR
#define tr_error(...) mbed_tracef(TRACE_LEVEL_ERROR, TRACE_GROUP, __VA_ARGS__) //!< Print Error Message
#define tr_err(...) mbed_tracef(TRACE_LEVEL_ERROR, TRACE_GROUP, __VA_ARGS__) //!< Alternative error message
#else
#define tr_error(...)
#define tr_err(...)
#endif
#define tr_cmdline(...) mbed_tracef(TRACE_LEVEL_CMD, TRACE_GROUP, __VA_ARGS__) //!< Special print for cmdline. See more from TRACE_LEVEL_CMD -level
//aliases for the most commonly used functions and the helper functions
@ -180,7 +214,7 @@ void mbed_trace_buffer_sizes(int lineLength, int tmpLength);
* @endcode
*/
void mbed_trace_config_set(uint8_t config);
/** get trace configurations
/** get trace configurations
* @return trace configuration byte
*/
uint8_t mbed_trace_config_get(void);
@ -232,7 +266,7 @@ void mbed_trace_mutex_release_function_set(void (*mutex_release_f)(void));
/**
* When trace group contains text in filters,
* trace print will be ignored.
* e.g.:
* e.g.:
* mbed_trace_exclude_filters_set("mygr");
* mbed_tracef(TRACE_ACTIVE_LEVEL_DEBUG, "ougr", "This is not printed");
*/
@ -294,7 +328,7 @@ void mbed_vtracef(uint8_t dlevel, const char* grp, const char *fmt, va_list ap);
* Get last trace from buffer
*/
const char* mbed_trace_last(void);
#if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1
#if MBED_CONF_MBED_TRACE_FEA_IPV6 == 1
/**
* mbed_tracef helping function for convert ipv6
* table to human readable string.
@ -327,7 +361,7 @@ char* mbed_trace_ipv6_prefix(const uint8_t *prefix, uint8_t prefix_len);
* @param buf hex array pointer
* @param len buffer length
* @return temporary buffer where string copied
* if array as string not fit to temp buffer, this function write '*' as last character,
* if array as string not fit to temp buffer, this function write '*' as last character,
* which indicate that buffer is too small for array.
*/
char* mbed_trace_array(const uint8_t* buf, uint16_t len);

5
features/FEATURE_COMMON_PAL/mbed-trace/mbed_lib.json
View File

@ -4,6 +4,11 @@
"enable": {
"help": "Used to globally enable traces.",
"value": null
},
"fea-ipv6": {
"help": "Used to globally disable ipv6 tracing features.",
"value": null
}
}
}

75
features/FEATURE_COMMON_PAL/mbed-trace/source/mbed_trace.c
View File

@ -17,13 +17,16 @@
#include <string.h>
#include <stdarg.h>
#ifndef YOTTA_CFG_MBED_TRACE
#define YOTTA_CFG_MBED_TRACE 1
#define YOTTA_CFG_MBED_TRACE_FEA_IPV6 1
#ifdef MBED_CONF_MBED_TRACE_ENABLE
#undef MBED_CONF_MBED_TRACE_ENABLE
#endif
#define MBED_CONF_MBED_TRACE_ENABLE 1
#ifndef MBED_CONF_MBED_TRACE_FEA_IPV6
#define MBED_CONF_MBED_TRACE_FEA_IPV6 1
#endif
#include "mbed-trace/mbed_trace.h"
#if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1
#if MBED_CONF_MBED_TRACE_FEA_IPV6 == 1
#include "mbed-client-libservice/ip6string.h"
#include "mbed-client-libservice/common_functions.h"
#endif
@ -52,23 +55,42 @@
#define VT100_COLOR_DEBUG "\x1b[90m"
/** default max trace line size in bytes */
#ifdef YOTTA_CFG_MBED_TRACE_LINE_LENGTH
#ifdef MBED_TRACE_LINE_LENGTH
#define DEFAULT_TRACE_LINE_LENGTH MBED_TRACE_LINE_LENGTH
#elif defined YOTTA_CFG_MBED_TRACE_LINE_LENGTH
#warning YOTTA_CFG_MBED_TRACE_LINE_LENGTH is deprecated and will be removed in the future! Use MBED_TRACE_LINE_LENGTH instead.
#define DEFAULT_TRACE_LINE_LENGTH YOTTA_CFG_MBED_TRACE_LINE_LENGTH
#else
#define DEFAULT_TRACE_LINE_LENGTH 1024
#endif
/** default max temporary buffer size in bytes, used in
trace_ipv6, trace_ipv6_prefix and trace_array */
#ifdef YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN
#ifdef MBED_TRACE_TMP_LINE_LENGTH
#define DEFAULT_TRACE_TMP_LINE_LEN MBED_TRACE_TMP_LINE_LENGTH
#elif defined YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN
#warning The YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN flag is deprecated and will be removed in the future! Use MBED_TRACE_TMP_LINE_LENGTH instead.
#define DEFAULT_TRACE_TMP_LINE_LEN YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN
#elif defined YOTTA_CFG_MTRACE_TMP_LINE_LEN
#warning The YOTTA_CFG_MTRACE_TMP_LINE_LEN flag is deprecated! Use YOTTA_CFG_MBED_TRACE_TMP_LINE_LEN instead.
#warning The YOTTA_CFG_MTRACE_TMP_LINE_LEN flag is deprecated and will be removed in the future! Use MBED_TRACE_TMP_LINE_LENGTH instead.
#define DEFAULT_TRACE_TMP_LINE_LEN YOTTA_CFG_MTRACE_TMP_LINE_LEN
#else
#define DEFAULT_TRACE_TMP_LINE_LEN 128
#endif
/** default max filters (include/exclude) length in bytes */
#ifdef MBED_TRACE_FILTER_LENGTH
#define DEFAULT_TRACE_FILTER_LENGTH MBED_TRACE_FILTER_LENGTH
#else
#define DEFAULT_TRACE_FILTER_LENGTH 24
#endif
/** default trace configuration bitmask */
#ifdef MBED_TRACE_CONFIG
#define DEFAULT_TRACE_CONFIG MBED_TRACE_CONFIG
#else
#define DEFAULT_TRACE_CONFIG TRACE_MODE_COLOR | TRACE_ACTIVE_LEVEL_ALL | TRACE_CARRIAGE_RETURN
#endif
/** default print function, just redirect str to printf */
static void mbed_trace_realloc( char **buffer, int *length_ptr, int new_length);
@ -112,13 +134,17 @@ typedef struct trace_s {
} trace_t;
static trace_t m_trace = {
.trace_config = DEFAULT_TRACE_CONFIG,
.filters_exclude = 0,
.filters_include = 0,
.filters_length = DEFAULT_TRACE_FILTER_LENGTH,
.line = 0,
.line_length = DEFAULT_TRACE_LINE_LENGTH,
.tmp_data = 0,
.tmp_data_length = DEFAULT_TRACE_TMP_LINE_LEN,
.prefix_f = 0,
.suffix_f = 0,
.printf = 0,
.printf = mbed_trace_default_print,
.cmd_printf = 0,
.mutex_wait_f = 0,
.mutex_release_f = 0,
@ -127,17 +153,15 @@ static trace_t m_trace = {
int mbed_trace_init(void)
{
m_trace.trace_config = TRACE_MODE_COLOR | TRACE_ACTIVE_LEVEL_ALL | TRACE_CARRIAGE_RETURN;
m_trace.line_length = DEFAULT_TRACE_LINE_LENGTH;
if (m_trace.line == NULL) {
m_trace.line = MBED_TRACE_MEM_ALLOC(m_trace.line_length);
}
m_trace.tmp_data_length = DEFAULT_TRACE_TMP_LINE_LEN;
if (m_trace.tmp_data == NULL) {
m_trace.tmp_data = MBED_TRACE_MEM_ALLOC(m_trace.tmp_data_length);
}
m_trace.tmp_data_ptr = m_trace.tmp_data;
m_trace.filters_length = DEFAULT_TRACE_FILTER_LENGTH;
if (m_trace.filters_exclude == NULL) {
m_trace.filters_exclude = MBED_TRACE_MEM_ALLOC(m_trace.filters_length);
}
@ -158,29 +182,28 @@ int mbed_trace_init(void)
memset(m_trace.filters_include, 0, m_trace.filters_length);
memset(m_trace.line, 0, m_trace.line_length);
m_trace.prefix_f = 0;
m_trace.suffix_f = 0;
m_trace.printf = mbed_trace_default_print;
m_trace.cmd_printf = 0;
return 0;
}
void mbed_trace_free(void)
{
// release memory
MBED_TRACE_MEM_FREE(m_trace.line);
m_trace.line_length = 0;
m_trace.line = 0;
MBED_TRACE_MEM_FREE(m_trace.tmp_data);
m_trace.tmp_data = 0;
m_trace.tmp_data_ptr = 0;
MBED_TRACE_MEM_FREE(m_trace.filters_exclude);
m_trace.filters_exclude = 0;
MBED_TRACE_MEM_FREE(m_trace.filters_include);
// reset to default values
m_trace.trace_config = DEFAULT_TRACE_CONFIG;
m_trace.filters_exclude = 0;
m_trace.filters_include = 0;
m_trace.filters_length = 0;
m_trace.filters_length = DEFAULT_TRACE_FILTER_LENGTH;
m_trace.line = 0;
m_trace.line_length = DEFAULT_TRACE_LINE_LENGTH;
m_trace.tmp_data = 0;
m_trace.tmp_data_length = DEFAULT_TRACE_TMP_LINE_LEN;
m_trace.prefix_f = 0;
m_trace.suffix_f = 0;
m_trace.printf = mbed_trace_default_print;
m_trace.printf = mbed_trace_default_print;
m_trace.cmd_printf = 0;
m_trace.mutex_wait_f = 0;
m_trace.mutex_release_f = 0;
@ -480,7 +503,7 @@ const char *mbed_trace_last(void)
}
/* Helping functions */
#define tmp_data_left() m_trace.tmp_data_length-(m_trace.tmp_data_ptr-m_trace.tmp_data)
#if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1
#if MBED_CONF_MBED_TRACE_FEA_IPV6 == 1
char *mbed_trace_ipv6(const void *addr_ptr)
{
/** Acquire mutex. It is released before returning from mbed_vtracef. */
@ -524,7 +547,7 @@ char *mbed_trace_ipv6_prefix(const uint8_t *prefix, uint8_t prefix_len)
m_trace.tmp_data_ptr += ip6_prefix_tos(prefix, prefix_len, str) + 1;
return str;
}
#endif //YOTTA_CFG_MBED_TRACE_FEA_IPV6
#endif //MBED_CONF_MBED_TRACE_FEA_IPV6
char *mbed_trace_array(const uint8_t *buf, uint16_t len)
{
/** Acquire mutex. It is released before returning from mbed_vtracef. */

38
features/FEATURE_COMMON_PAL/mbed-trace/test/Test.cpp
View File

@ -14,8 +14,8 @@
#include "mbed-cpputest/CppUTest/SimpleString.h"
#include "mbed-cpputest/CppUTest/CommandLineTestRunner.h"
#define YOTTA_CFG_MBED_TRACE 1
#define YOTTA_CFG_MBED_TRACE_FEA_IPV6 1
#define MBED_CONF_MBED_TRACE_ENABLE 1
#define MBED_CONF_MBED_TRACE_FEA_IPV6 1
#include "mbed-trace/mbed_trace.h"
#include "ip6tos_stub.h"
@ -118,6 +118,7 @@ TEST(trace, BufferResize)
{
uint8_t arr[20] = {0};
memset(arr, '0', 20);
mbed_trace_buffer_sizes(0, 10);
STRCMP_EQUAL("30:30:30*", mbed_trace_array(arr, 20));
mbed_trace_buffer_sizes(0, 15);
@ -125,7 +126,38 @@ TEST(trace, BufferResize)
mbed_trace_buffer_sizes(0, 15);
STRCMP_EQUAL("30:30:30:30", mbed_trace_array(arr, 4));
mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "flush buffers and locks");
const char * expectedStr = "0123456789";
mbed_trace_buffer_sizes(11, 0);
mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "01234567890123456789");
STRCMP_EQUAL(expectedStr, buf);
expectedStr = "012345678901234";
mbed_trace_buffer_sizes(16, 0);
mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "01234567890123456789");
STRCMP_EQUAL(expectedStr, buf);
expectedStr = "012345678901234";
mbed_trace_buffer_sizes(16, 0);
mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "012345678901234");
STRCMP_EQUAL(expectedStr, buf);
}
TEST(trace, PreInitConfiguration)
{
uint8_t arr[20] = {0};
memset(arr, '0', 20);
mbed_trace_free();
mbed_trace_config_set(TRACE_MODE_PLAIN|TRACE_ACTIVE_LEVEL_ALL);
mbed_trace_print_function_set( myprint );
mbed_trace_buffer_sizes(11, 10);
mbed_trace_mutex_wait_function_set( my_mutex_wait );
mbed_trace_mutex_release_function_set( my_mutex_release );
mbed_trace_init();
STRCMP_EQUAL("30:30:30*", mbed_trace_array(arr, 20));
const char * expectedStr = "0123456789";
mbed_tracef(TRACE_LEVEL_DEBUG, "mygr", "01234567890123456789");
STRCMP_EQUAL(expectedStr, buf);
}
#if YOTTA_CFG_MBED_TRACE_FEA_IPV6 == 1

39
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c
View File

@ -100,36 +100,43 @@ struct ethernetif {
// Override mbed_mac_address of mbed_interface.c to provide ethernet devices with a semi-unique MAC address
void mbed_mac_address(char *mac)
{
unsigned char my_mac_addr[6] = {0x02, 0x00, 0xac, 0x55, 0x66, 0x77}; // default mac adderss
uint32_t uID1;
// Fetch word 0
uint32_t word0 = *(uint32_t *)0x7FFFC;
uint32_t word0 = *(uint32_t *)0x7F804; // 2KB Data Flash at 0x7F800
// Fetch word 1
// we only want bottom 16 bits of word1 (MAC bits 32-47)
// and bit 9 forced to 1, bit 8 forced to 0
// Locally administered MAC, reduced conflicts
// http://en.wikipedia.org/wiki/MAC_address
uint32_t word1 = *(uint32_t *)0x7FFF8;
if( word0 == 0xFFFFFFFF ) // Not burn any mac address at the last 2 words of flash
uint32_t word1 = *(uint32_t *)0x7F800; // 2KB Data Flash at 0x7F800
if( word0 == 0xFFFFFFFF ) // Not burn any mac address at 1st 2 words of Data Flash
{
mac[0] = my_mac_addr[0];
mac[1] = my_mac_addr[1];
mac[2] = my_mac_addr[2];
mac[3] = my_mac_addr[3];
mac[4] = my_mac_addr[4];
mac[5] = my_mac_addr[5];
return;
// with a semi-unique MAC address from the UUID
/* Enable FMC ISP function */
SYS_UnlockReg();
FMC_Open();
// = FMC_ReadUID(0);
uID1 = FMC_ReadUID(1);
word1 = (uID1 & 0x003FFFFF) | ((uID1 & 0x030000) << 6) >> 8;
word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF)<<12) | (FMC_ReadUID(2) & 0xFFF);
/* Disable FMC ISP function */
FMC_Close();
/* Lock protected registers */
SYS_LockReg();
}
word1 |= 0x00000200;
word1 &= 0x0000FEFF;
mac[0] = (word1 & 0x000000ff);
mac[1] = (word1 & 0x0000ff00) >> 8;
mac[0] = (word1 & 0x0000ff00) >> 8;
mac[1] = (word1 & 0x000000ff);
mac[2] = (word0 & 0xff000000) >> 24;
mac[3] = (word0 & 0x00ff0000) >> 16;
mac[4] = (word0 & 0x0000ff00) >> 8;
mac[5] = (word0 & 0x000000ff);
LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING|LWIP_DBG_ON, ("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1],mac[2],mac[3],mac[4],mac[5]));
}
/**
@ -350,7 +357,7 @@ ethernetif_loopback_input(struct pbuf *p) // TODO: make sure packet no
{
/* pass all packets to ethernet_input, which decides what packets it supports */
if (netif->input(p, netif) != ERR_OK) {
LWIP_DEBUGF(NETIF_DEBUG, ("k64f_enetif_input: input error\n"));
LWIP_DEBUGF(NETIF_DEBUG, ("netif_input: input error\n"));
/* Free buffer */
pbuf_free(p);
}

1
features/FEATURE_LWIP/lwip-interface/lwip_stack.c
View File

@ -691,6 +691,7 @@ static nsapi_error_t mbed_lwip_socket_close(nsapi_stack_t *stack, nsapi_socket_t
{
struct lwip_socket *s = (struct lwip_socket *)handle;
netbuf_delete(s->buf);
err_t err = netconn_delete(s->conn);
mbed_lwip_arena_dealloc(s);
return mbed_lwip_err_remap(err);

137
features/TESTS/filesystem/heap_block_device/main.cpp
View File

@ -23,71 +23,124 @@
using namespace utest::v1;
/* It is not possible to build a KL25Z image with IAR including the file system if
* stack tracking statistics are enabled. If this is the case, build dummy
* tests.
*/
#if ! defined(__ICCARM__) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED)
#define TEST_BLOCK_SIZE 512
#define TEST_BLOCK_DEVICE_SIZE 16*TEST_BLOCK_SIZE
#define TEST_BLOCK_COUNT 10
#define TEST_ERROR_MASK 16
#define BLOCK_SIZE 512
#define HEAP_BLOCK_DEVICE_TEST_01 test_read_write
uint8_t write_block[BLOCK_SIZE];
uint8_t read_block[BLOCK_SIZE];
const struct {
const char *name;
bd_size_t (BlockDevice::*method)() const;
} ATTRS[] = {
{"read size", &BlockDevice::get_read_size},
{"program size", &BlockDevice::get_program_size},
{"erase size", &BlockDevice::get_erase_size},
{"total size", &BlockDevice::size},
};
// Simple test which reads and writes a block
// Simple test that read/writes random set of blocks
void test_read_write() {
HeapBlockDevice bd(16*BLOCK_SIZE, BLOCK_SIZE);
HeapBlockDevice bd(TEST_BLOCK_DEVICE_SIZE, TEST_BLOCK_SIZE);
int err = bd.init();
TEST_ASSERT_EQUAL(0, err);
// Fill with random sequence
srand(1);
for (int i = 0; i < BLOCK_SIZE; i++) {
write_block[i] = 0xff & rand();
for (unsigned a = 0; a < sizeof(ATTRS)/sizeof(ATTRS[0]); a++) {
static const char *prefixes[] = {"", "k", "M", "G"};
for (int i = 3; i >= 0; i--) {
bd_size_t size = (bd.*ATTRS[a].method)();
if (size >= (1ULL << 10*i)) {
printf("%s: %llu%sbytes (%llubytes)\n",
ATTRS[a].name, size >> 10*i, prefixes[i], size);
break;
}
}
}
// Write, sync, and read the block
err = bd.program(write_block, 0, BLOCK_SIZE);
TEST_ASSERT_EQUAL(0, err);
bd_size_t block_size = bd.get_erase_size();
uint8_t *write_block = new uint8_t[block_size];
uint8_t *read_block = new uint8_t[block_size];
uint8_t *error_mask = new uint8_t[TEST_ERROR_MASK];
unsigned addrwidth = ceil(log(float(bd.size()-1)) / log(float(16)))+1;
err = bd.read(read_block, 0, BLOCK_SIZE);
TEST_ASSERT_EQUAL(0, err);
for (int b = 0; b < TEST_BLOCK_COUNT; b++) {
// Find a random block
bd_addr_t block = (rand()*block_size) % bd.size();
// Check that the data was unmodified
srand(1);
for (int i = 0; i < BLOCK_SIZE; i++) {
TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]);
// Use next random number as temporary seed to keep
// the address progressing in the pseudorandom sequence
unsigned seed = rand();
// Fill with random sequence
srand(seed);
for (bd_size_t i = 0; i < block_size; i++) {
write_block[i] = 0xff & rand();
}
// erase, program, and read the block
printf("test %0*llx:%llu...\n", addrwidth, block, block_size);
err = bd.erase(block, block_size);
TEST_ASSERT_EQUAL(0, err);
err = bd.program(write_block, block, block_size);
TEST_ASSERT_EQUAL(0, err);
printf("write %0*llx:%llu ", addrwidth, block, block_size);
for (int i = 0; i < 16; i++) {
printf("%02x", write_block[i]);
}
printf("...\n");
err = bd.read(read_block, block, block_size);
TEST_ASSERT_EQUAL(0, err);
printf("read %0*llx:%llu ", addrwidth, block, block_size);
for (int i = 0; i < 16; i++) {
printf("%02x", read_block[i]);
}
printf("...\n");
// Find error mask for debugging
memset(error_mask, 0, TEST_ERROR_MASK);
bd_size_t error_scale = block_size / (TEST_ERROR_MASK*8);
srand(seed);
for (bd_size_t i = 0; i < TEST_ERROR_MASK*8; i++) {
for (bd_size_t j = 0; j < error_scale; j++) {
if ((0xff & rand()) != read_block[i*error_scale + j]) {
error_mask[i/8] |= 1 << (i%8);
}
}
}
printf("error %0*llx:%llu ", addrwidth, block, block_size);
for (int i = 0; i < 16; i++) {
printf("%02x", error_mask[i]);
}
printf("\n");
// Check that the data was unmodified
srand(seed);
for (bd_size_t i = 0; i < block_size; i++) {
TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]);
}
}
err = bd.deinit();
TEST_ASSERT_EQUAL(0, err);
}
#else /* ! defined(__ICCARM__) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */
#define HEAP_BLOCK_DEVICE_TEST_01 heap_block_device_test_dummy
/** @brief heap_block_device_test_dummy Dummy test case for testing when KL25Z being built with stack statistics enabled.
*
* @return success always
*/
static control_t heap_block_device_test_dummy()
{
printf("Null test\n");
return CaseNext;
}
#endif /* ! defined(__ICCARM__) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(10, "default_auto");
GREENTEA_SETUP(30, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
Case cases[] = {
Case("Testing read write of a block", HEAP_BLOCK_DEVICE_TEST_01),
Case("Testing read write random blocks", test_read_write),
};
Specification specification(test_setup, cases);

38
features/TESTS/filesystem/util_block_device/main.cpp
View File

@ -25,23 +25,15 @@
using namespace utest::v1;
/* It is not possible to build a KL25Z image with IAR including the file system if
* stack tracking statistics are enabled. If this is the case, build dummy
* tests.
*/
#if ! defined(TOOLCHAIN_IAR) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED)
#define BLOCK_COUNT 16
#define BLOCK_SIZE 512
#define UTIL_BLOCK_DEVICE_TEST_01 test_slicing
#define UTIL_BLOCK_DEVICE_TEST_02 test_chaining
uint8_t write_block[BLOCK_SIZE];
uint8_t read_block[BLOCK_SIZE];
// Simple test which read/writes blocks on a sliced block device
void test_slicing() {
HeapBlockDevice bd(BLOCK_COUNT*BLOCK_SIZE, BLOCK_SIZE);
uint8_t *write_block = new uint8_t[BLOCK_SIZE];
uint8_t *read_block = new uint8_t[BLOCK_SIZE];
// Test with first slice of block device
SlicingBlockDevice slice1(&bd, 0, (BLOCK_COUNT/2)*BLOCK_SIZE);
@ -123,6 +115,8 @@ void test_slicing() {
TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]);
}
delete[] write_block;
delete[] read_block;
err = slice2.deinit();
TEST_ASSERT_EQUAL(0, err);
}
@ -131,6 +125,8 @@ void test_slicing() {
void test_chaining() {
HeapBlockDevice bd1((BLOCK_COUNT/2)*BLOCK_SIZE, BLOCK_SIZE);
HeapBlockDevice bd2((BLOCK_COUNT/2)*BLOCK_SIZE, BLOCK_SIZE);
uint8_t *write_block = new uint8_t[BLOCK_SIZE];
uint8_t *read_block = new uint8_t[BLOCK_SIZE];
// Test with chain of block device
BlockDevice *bds[] = {&bd1, &bd2};
@ -174,26 +170,12 @@ void test_chaining() {
TEST_ASSERT_EQUAL(0xff & rand(), read_block[i]);
}
delete[] write_block;
delete[] read_block;
err = chain.deinit();
TEST_ASSERT_EQUAL(0, err);
}
#else /* ! defined(TOOLCHAIN_IAR) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */
#define UTIL_BLOCK_DEVICE_TEST_01 util_block_device_test_dummy
#define UTIL_BLOCK_DEVICE_TEST_02 util_block_device_test_dummy
/** @brief util_block_device_test_dummy Dummy test case for testing when KL25Z being built with stack statistics enabled.
*
* @return success always
*/
static control_t util_block_device_test_dummy()
{
printf("Null test\n");
return CaseNext;
}
#endif /* ! defined(TOOLCHAIN_IAR) && ! defined(TARGET_KL25Z) && ! defined(MBED_STACK_STATS_ENABLED) */
// Test setup
utest::v1::status_t test_setup(const size_t number_of_cases) {
@ -202,8 +184,8 @@ utest::v1::status_t test_setup(const size_t number_of_cases) {
}
Case cases[] = {
Case("Testing slicing of a block device", UTIL_BLOCK_DEVICE_TEST_01),
Case("Testing chaining of block devices", UTIL_BLOCK_DEVICE_TEST_02),
Case("Testing slicing of a block device", test_slicing),
Case("Testing chaining of block devices", test_chaining),
};
Specification specification(test_setup, cases);

26
features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/mbedtls_device.h Normal file
View File

@ -0,0 +1,26 @@
/*
* mbedtls_device.h
*******************************************************************************
* Copyright (c) 2017, STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef MBEDTLS_DEVICE_H
#define MBEDTLS_DEVICE_H
#define MBEDTLS_AES_ALT
#endif /* MBEDTLS_DEVICE_H */

295
features/mbedtls/targets/TARGET_STM/aes_alt.c Normal file
View File

@ -0,0 +1,295 @@
/*
* Hardware aes collector for the STM32F4 family
*******************************************************************************
* Copyright (c) 2017, STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#include <string.h>
#include "mbedtls/aes.h"
#if defined(MBEDTLS_AES_ALT)
static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits )
{
switch( keybits )
{
case 128:
ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_128B;
memcpy(ctx->aes_key, key, 16);
break;
case 192:
ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_192B;
memcpy(ctx->aes_key, key, 24);
break;
case 256:
ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_256B;
memcpy(ctx->aes_key, key, 32);
break;
default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
}
/* Deinitializes the CRYP peripheral */
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR)
return (HAL_ERROR);
ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
ctx->hcryp_aes.Instance = CRYP;
/* Enable CRYP clock */
__HAL_RCC_CRYP_CLK_ENABLE();
ctx->hcryp_aes.Init.pKey = ctx->aes_key;
if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR)
return (HAL_ERROR);
/* allow multi-instance of CRYP use: save context for CRYP HW module CR */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
return(0);
}
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
}
void mbedtls_aes_init( mbedtls_aes_context *ctx )
{
memset( ctx, 0, sizeof( mbedtls_aes_context ) );
}
void mbedtls_aes_free( mbedtls_aes_context *ctx )
{
if( ctx == NULL )
return;
/* Force the CRYP Periheral Clock Reset */
__HAL_RCC_CRYP_FORCE_RESET();
/* Release the CRYP Periheral Clock Reset */
__HAL_RCC_CRYP_RELEASE_RESET();
mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) );
}
int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits )
{
int ret_val = 0;
ret_val = aes_set_key(ctx, key, keybits);
return(ret_val);
}
int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits )
{
int ret_val = 0;
ret_val = aes_set_key(ctx, key, keybits);
return( ret_val );
}
int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
int mode,
const unsigned char input[16],
unsigned char output[16] )
{
/* allow multi-instance of CRYP use: restore context for CRYP hw module */
ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
if(mode == MBEDTLS_AES_DECRYPT) /* AES decryption */
{
ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
ctx->hcryp_aes.Init.pKey = ctx->aes_key;
mbedtls_aes_decrypt( ctx, input, output );
}
else /* AES encryption */
{
ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
ctx->hcryp_aes.Init.pKey = ctx->aes_key;
mbedtls_aes_encrypt( ctx, input, output );
}
/* allow multi-instance of CRYP use: save context for CRYP HW module CR */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
return( 0 );
}
#if defined(MBEDTLS_CIPHER_MODE_CBC)
int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output )
{
int status=0;
if( length % 16 )
return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
if( mode == MBEDTLS_AES_DECRYPT )
{
ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init
status = HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10);
}
else
{
ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init
status = HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10);
}
return( status );
}
#endif /* MBEDTLS_CIPHER_MODE_CBC */
#if defined(MBEDTLS_CIPHER_MODE_CFB)
int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output )
{
int c;
size_t n = *iv_off;
if( mode == MBEDTLS_AES_DECRYPT )
{
while( length-- )
{
if( n == 0 )
mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
c = *input++;
*output++ = (unsigned char)( c ^ iv[n] );
iv[n] = (unsigned char) c;
n = ( n + 1 ) & 0x0F;
}
}
else
{
while( length-- )
{
if( n == 0 )
mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
n = ( n + 1 ) & 0x0F;
}
}
*iv_off = n;
return( 0 );
}
int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output )
{
unsigned char c;
unsigned char ov[17];
while( length-- )
{
memcpy( ov, iv, 16 );
mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
if( mode == MBEDTLS_AES_DECRYPT )
ov[16] = *input;
c = *output++ = (unsigned char)( iv[0] ^ *input++ );
if( mode == MBEDTLS_AES_ENCRYPT )
ov[16] = c;
memcpy( iv, ov + 1, 16 );
}
return( 0 );
}
#endif /*MBEDTLS_CIPHER_MODE_CFB */
#if defined(MBEDTLS_CIPHER_MODE_CTR)
int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output )
{
int c, i;
size_t n = *nc_off;
while( length-- )
{
if( n == 0 ) {
mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block );
for( i = 16; i > 0; i-- )
if( ++nonce_counter[i - 1] != 0 )
break;
}
c = *input++;
*output++ = (unsigned char)( c ^ stream_block[n] );
n = ( n + 1 ) & 0x0F;
}
*nc_off = n;
return( 0 );
}
#endif /* MBEDTLS_CIPHER_MODE_CTR */
void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] )
{
if (HAL_CRYP_AESECB_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) !=0) {
// error found to be returned
}
}
void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] )
{
if(HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10)) {
// error found to be returned
}
}
#endif /*MBEDTLS_AES_ALT*/

264
features/mbedtls/targets/TARGET_STM/aes_alt.h Normal file
View File

@ -0,0 +1,264 @@
/*
* aes_alt.h AES block cipher
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef MBEDTLS_AES_ALT_H
#define MBEDTLS_AES_ALT_H
#if defined(MBEDTLS_AES_ALT)
#include "mbedtls/platform.h"
#include "mbedtls/config.h"
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief AES context structure
*
* \note buf is able to hold 32 extra bytes, which can be used:
* - for alignment purposes if VIA padlock is used, and/or
* - to simplify key expansion in the 256-bit case by
* generating an extra round key
*/
typedef struct
{
unsigned char aes_key[32]; /* Decryption key */
CRYP_HandleTypeDef hcryp_aes;
uint32_t ctx_save_cr; /* save context for multi-instance */
}
mbedtls_aes_context;
/**
* \brief Initialize AES context
*
* \param ctx AES context to be initialized
*/
void mbedtls_aes_init( mbedtls_aes_context *ctx );
/**
* \brief Clear AES context
*
* \param ctx AES context to be cleared
*/
void mbedtls_aes_free( mbedtls_aes_context *ctx );
/**
* \brief AES key schedule (encryption)
*
* \param ctx AES context to be initialized
* \param key encryption key
* \param keybits must be 128, 192 or 256
*
* \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
*/
int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits );
/**
* \brief AES key schedule (decryption)
*
* \param ctx AES context to be initialized
* \param key decryption key
* \param keybits must be 128, 192 or 256
*
* \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
*/
int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits );
/**
* \brief AES-ECB block encryption/decryption
*
* \param ctx AES context
* \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
* \param input 16-byte input block
* \param output 16-byte output block
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
int mode,
const unsigned char input[16],
unsigned char output[16] );
#if defined(MBEDTLS_CIPHER_MODE_CBC)
/**
* \brief AES-CBC buffer encryption/decryption
* Length should be a multiple of the block
* size (16 bytes)
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
* \param length length of the input data
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
*/
int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
#endif /* MBEDTLS_CIPHER_MODE_CBC */
#if defined(MBEDTLS_CIPHER_MODE_CFB)
/**
* \brief AES-CFB128 buffer encryption/decryption.
*
* Note: Due to the nature of CFB you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
* \param length length of the input data
* \param iv_off offset in IV (updated after use)
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
/**
* \brief AES-CFB8 buffer encryption/decryption.
*
* Note: Due to the nature of CFB you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
*
* \note Upon exit, the content of the IV is updated so that you can
* call the function same function again on the following
* block(s) of data and get the same result as if it was
* encrypted in one call. This allows a "streaming" usage.
* If on the other hand you need to retain the contents of the
* IV, you should either save it manually or use the cipher
* module instead.
*
* \param ctx AES context
* \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
* \param length length of the input data
* \param iv initialization vector (updated after use)
* \param input buffer holding the input data
* \param output buffer holding the output data
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
#endif /*MBEDTLS_CIPHER_MODE_CFB */
#if defined(MBEDTLS_CIPHER_MODE_CTR)
/**
* \brief AES-CTR buffer encryption/decryption
*
* Warning: You have to keep the maximum use of your counter in mind!
*
* Note: Due to the nature of CTR you should use the same key schedule for
* both encryption and decryption. So a context initialized with
* mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
*
* \param ctx AES context
* \param length The length of the data
* \param nc_off The offset in the current stream_block (for resuming
* within current cipher stream). The offset pointer to
* should be 0 at the start of a stream.
* \param nonce_counter The 128-bit nonce and counter.
* \param stream_block The saved stream-block for resuming. Is overwritten
* by the function.
* \param input The input data stream
* \param output The output data stream
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output );
#endif /* MBEDTLS_CIPHER_MODE_CTR */
/**
* \brief Internal AES block encryption function
* (Only exposed to allow overriding it,
* see MBEDTLS_AES_ENCRYPT_ALT)
*
* \param ctx AES context
* \param input Plaintext block
* \param output Output (ciphertext) block
*/
void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] );
/**
* \brief Internal AES block decryption function
* (Only exposed to allow overriding it,
* see MBEDTLS_AES_DECRYPT_ALT)
*
* \param ctx AES context
* \param input Ciphertext block
* \param output Output (plaintext) block
*/
void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] );
#ifdef __cplusplus
}
#endif
#endif /* MBEDTLS_AES_ALT */
#endif /* MBEDTLS_AES_ALT_H */

119
features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp
View File

@ -67,6 +67,8 @@ static const RAIL_CsmaConfig_t csma_config = RAIL_CSMA_CONFIG_802_15_4_2003_2p4_
#if defined(TARGET_EFR32MG1)
#include "ieee802154_subg_efr32xg1_configurator_out.h"
#include "ieee802154_efr32xg1_configurator_out.h"
#elif defined(TARGET_EFR32MG12)
#include "ieee802154_efr32xg12_configurator_out.h"
#else
#error "Not a valid target."
#endif
@ -78,7 +80,7 @@ static const RAIL_ChannelConfigEntry_t entry[] = {
};
#if MBED_CONF_SL_RAIL_BAND == 868
#ifndef DEVICE_RF_SUBGHZ
#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
#error "Sub-Gigahertz band is not supported on this target."
#endif
static const RAIL_ChannelConfig_t channels = {
@ -86,7 +88,7 @@ static const RAIL_ChannelConfig_t channels = {
1
};
#elif MBED_CONF_SL_RAIL_BAND == 915
#ifndef DEVICE_RF_SUBGHZ
#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
#error "Sub-Gigahertz band is not supported on this target."
#endif
static const RAIL_ChannelConfig_t channels = {
@ -94,7 +96,7 @@ static const RAIL_ChannelConfig_t channels = {
1
};
#elif MBED_CONF_SL_RAIL_BAND == 2400
#ifndef DEVICE_RF_2P4GHZ
#ifndef MBED_CONF_SL_RAIL_HAS_2P4
#error "2.4GHz band is not supported on this target."
#endif
static const RAIL_ChannelConfig_t channels = {
@ -111,7 +113,7 @@ static const RAIL_IEEE802154_Config_t config = { false, false,
static const RAIL_Init_t railInitParams = { 140, 38400000, RAIL_CAL_ALL_PENDING };
#if defined (DEVICE_RF_2P4GHZ)
#if defined (MBED_CONF_SL_RAIL_HAS_2P4)
// Set up the PA for 2.4 GHz operation
static const RADIO_PAInit_t paInit2p4 = {
PA_SEL_2P4_HP, /* Power Amplifier mode */
@ -122,7 +124,7 @@ static const RADIO_PAInit_t paInit2p4 = {
};
#endif
#if defined (DEVICE_RF_SUBGHZ)
#if defined (MBED_CONF_SL_RAIL_HAS_SUBGIG)
// Set up the PA for sub-GHz operation
static const RADIO_PAInit_t paInitSubGhz = {
PA_SEL_SUBGIG, /* Power Amplifier mode */
@ -173,21 +175,19 @@ static int8_t rf_device_register(void)
#endif
// Set up PTI since it makes life so much easier
#if defined(DEVICE_SL_PTI)
#if defined(MBED_CONF_SL_RAIL_PTI) && (MBED_CONF_SL_RAIL_PTI == 1)
RADIO_PTIInit_t ptiInit = {
RADIO_PTI_MODE_UART,
1600000,
6,
// TODO: Configure PTI pinout using config system.
// Not very urgent, since all boards use the same pins now.
gpioPortB,
12,
6,
gpioPortB,
11,
6,
gpioPortB,
13,
MBED_CONF_SL_RAIL_PTI_MODE,
MBED_CONF_SL_RAIL_PTI_BAUDRATE,
MBED_CONF_SL_RAIL_PTI_DOUT_LOCATION,
MBED_CONF_SL_RAIL_PTI_DOUT_PORT,
MBED_CONF_SL_RAIL_PTI_DOUT_PIN,
MBED_CONF_SL_RAIL_PTI_DCLK_LOCATION,
MBED_CONF_SL_RAIL_PTI_DCLK_PORT,
MBED_CONF_SL_RAIL_PTI_DCLK_PIN,
MBED_CONF_SL_RAIL_PTI_DFRAME_LOCATION,
MBED_CONF_SL_RAIL_PTI_DFRAME_PORT,
MBED_CONF_SL_RAIL_PTI_DFRAME_PIN
};
RADIO_PTI_Init(&ptiInit);
@ -196,13 +196,13 @@ static int8_t rf_device_register(void)
// Set up RAIL
RAIL_RfInit(&railInitParams);
RAIL_ChannelConfig(&channels);
#if MBED_CONF_SL_RAIL_BAND == 2400
#if (MBED_CONF_SL_RAIL_BAND == 2400)
RAIL_RadioConfig((void*) ieee802154_config_base);
channel = 11;
#elif (MBED_CONF_SL_RAIL_BAND == 915)
RAIL_RadioConfig((void*) ieee802154_config_915);
channel = 1;
#elif MBED_CONF_SL_RAIL_BAND == 868
#elif (MBED_CONF_SL_RAIL_BAND == 868)
RAIL_RadioConfig((void*) ieee802154_config_863);
channel = 0;
#endif
@ -286,8 +286,6 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
data_length + 3
};
tr_debug("Called TX, len %d, chan %d\n", data_length, channel);
switch(radio_state) {
case RADIO_UNINIT:
tr_debug("Radio uninit\n");
@ -327,6 +325,8 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
txOpt.waitForAck = false;
}
//tr_debug("Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0);
if(RAIL_TxStartWithOptions(channel, &txOpt, &RAIL_CcaCsma, (RAIL_CsmaConfig_t*) &csma_config) == 0) {
//Save packet number and sequence
current_tx_handle = tx_handle;
@ -612,7 +612,6 @@ void RAILCb_RfReady(void) {
* @param[in] status A bit field that defines what event caused the callback
*/
void RAILCb_TxRadioStatus(uint8_t status) {
tr_debug("Packet TX error %d\n", status);
if(device_driver.phy_tx_done_cb != NULL) {
if(status == RAIL_TX_CONFIG_BUFFER_UNDERFLOW ||
status == RAIL_TX_CONFIG_CHANNEL_BUSY ||
@ -624,6 +623,8 @@ void RAILCb_TxRadioStatus(uint8_t status) {
PHY_LINK_CCA_FAIL,
8,
1);
} else {
tr_debug("Packet TX error %d\n", status);
}
}
radio_state = RADIO_RX;
@ -643,7 +644,13 @@ void RAILCb_TxRadioStatus(uint8_t status) {
* @param[in] status The event that triggered this callback
*/
void RAILCb_RxRadioStatus(uint8_t status) {
tr_debug("RXE %d\n", status);
switch(status) {
case RAIL_RX_CONFIG_ADDRESS_FILTERED:
break;
default:
tr_debug("RXE %d\n", status);
break;
}
}
/**
@ -724,10 +731,10 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) {
/* Save the pending bit */
last_ack_pending_bit = (rxPacketInfo->dataPtr[1] & (1 << 4)) != 0;
/* Tell the stack we got an ACK */
tr_debug("rACK\n");
//tr_debug("rACK\n");
device_driver.phy_tx_done_cb( rf_radio_driver_id,
current_tx_handle,
PHY_LINK_TX_DONE,
last_ack_pending_bit ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE,
1,
1);
} else {
@ -745,7 +752,7 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) {
RAIL_AutoAckCancelAck();
}
tr_debug("rPKT %d\n", rxPacketInfo->dataLength);
//tr_debug("rPKT %d\n", rxPacketInfo->dataLength);
/* Feed the received packet into the stack */
device_driver.phy_rx_cb(rxPacketInfo->dataPtr + 1,
rxPacketInfo->dataLength - 1,
@ -785,6 +792,7 @@ void RAILCb_IEEE802154_DataRequestCommand(RAIL_IEEE802154_Address_t *address) {
*/
void RAILCb_RxAckTimeout(void) {
if(waiting_for_ack) {
tr_debug("nACK\n");
waiting_for_ack = false;
device_driver.phy_tx_done_cb( rf_radio_driver_id,
current_tx_handle,
@ -824,4 +832,59 @@ static bool rail_checkAndSwitchChannel(uint8_t newChannel) {
} else {
return false;
}
}
/**
* Callback that fires when the receive fifo exceeds the configured threshold
* value
*
* @param[in] bytesAvailable Number of bytes available in the receive fifo at
* the time of the callback dispatch
*
* @return void
* @warning You must implement a stub for this in your RAIL application.
*
* Callback that fires when the receive fifo exceeds the configured threshold
* value. Provides the number of bytes available in the receive fifo at the
* time of the callback dispatch.
*/
void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) {
tr_debug("RX near full (%d)\n", bytesAvailable);
}
/**
* Callback that fires when the transmit fifo falls under the configured
* threshold value
*
* @param[in] spaceAvailable Number of bytes open in the transmit fifo at the
* time of the callback dispatch
*
* @return void
* @warning You must implement a stub for this in your RAIL application.
*
* Callback that fires when the transmit fifo falls under the configured
* threshold value. It only fires if a rising edge occurs across this
* threshold. This callback will not fire on initailization nor after resetting
* the transmit fifo with RAIL_ResetFifo().
*
* Provides the number of bytes open in the transmit fifo at the time of the
* callback dispatch.
*/
void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) {
tr_debug("TX near empty (%d)\n", spaceAvailable);
}
/**
* Callback for when AGC averaged RSSI is done
*
* @param avgRssi Contains the the RSSI in quarter dBm (dbm*4) on success and
* returns \ref RAIL_RSSI_INVALID if there was a problem computing the result.
*
* Called in response to RAIL_StartAverageRSSI() to indicate that the hardware
* has completed averaging. If you would like you can instead use the
* RAIL_AverageRSSIReady() to wait for completion and RAIL_GetAverageRSSI() to
* get the result.
*/
void RAILCb_RssiAverageDone(int16_t avgRssi) {
tr_debug("RSSI done (%d)\n", avgRssi);
}

3
features/unsupported/tests/mbed/digitalin_digitalout/main.cpp
View File

@ -9,11 +9,12 @@ DigitalIn in(dp2);
// port pin), D1 is used as USBTX
DigitalOut out(D7);
DigitalIn in(D2);
#elif defined(TARGET_STM) && defined(TARGET_FF_ARDUINO)
// TARGET_FF_ARDUINO cannot be used
// D0 is used as USBRX for some NUCLEO64
// D7 is not used for some NUCLEO32
DigitalOut out(D9);
DigitalOut out(D3);
DigitalIn in(D2);
#elif defined(TARGET_DISCO_L053C8) || \

2
features/unsupported/tests/mbed/digitalinout/main.cpp
View File

@ -14,7 +14,7 @@ DigitalInOut d2(D7);
// TARGET_FF_ARDUINO cannot be used
// D0 is used as USBRX for some NUCLEO64
// D7 is not used for some NUCLEO32
DigitalInOut d1(D9);
DigitalInOut d1(D3);
DigitalInOut d2(D2);
#elif defined(TARGET_DISCO_L053C8) || \

2
features/unsupported/tests/mbed/interruptin/main.cpp
View File

@ -44,7 +44,7 @@ void in_handler() {
// D0 is used as USBRX for some NUCLEO64
// D7 is not used for some NUCLEO32
#define PIN_OUT D2
#define PIN_IN D9
#define PIN_IN D3
#elif defined(TARGET_DISCO_L053C8) || \
defined(TARGET_DISCO_F334C8)

32
features/unsupported/tests/mbed/portinout/main.cpp
View File

@ -1,5 +1,9 @@
#include "test_env.h"
#if !DEVICE_PORTINOUT
#error [NOT_SUPPORTED] PortInOut is not supported
#endif
#if defined(TARGET_K64F)
#define P1_1 (1 << 16)
#define P1_2 (1 << 17)
@ -103,14 +107,28 @@
defined(TARGET_NUCLEO_F411RE) || \
defined(TARGET_NUCLEO_L053R8) || \
defined(TARGET_NUCLEO_L073RZ) || \
defined(TARGET_NUCLEO_L476RG) || \
defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_NUCLEO_L152RE)
#define P1_1 (1 << 6) // PC_6
#define P1_2 (1 << 5) // PC_5
#define PORT_1 PortC
#define P1_1 (1 << 3) // PB_3 (D3)
#define P1_2 (1 << 10) // PB_10 (D6)
#define PORT_1 PortB
#define P2_1 (1 << 8) // PB_8
#define P2_2 (1 << 9) // PB_9
#define PORT_2 PortB
#define P2_1 (1 << 10) // PA_10 (D2)
#define P2_2 (1 << 8) // PA_8 (D7)
#define PORT_2 PortA
#elif defined(TARGET_NUCLEO_F767ZI) || \
defined(TARGET_NUCLEO_F303ZE) || \
defined(TARGET_NUCLEO_F207ZG) || \
defined(TARGET_NUCLEO_F746ZG)
#define P1_1 (1 << 13) // PE_13 (D3)
#define P1_2 (1 << 11) // PE_11 (D5)
#define PORT_1 PortE
#define P2_1 (1 << 15) // PF_15 (D2)
#define P2_2 (1 << 14) // PF_14 (D4)
#define PORT_2 PortF
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define P1_1 (1 << 0) // PD0
@ -193,6 +211,8 @@
#define P2_2 (1 << 1) /*P5_1*/
#define PORT_2 Port5
#else
#error [NOT_SUPPORTED] This test is not defined on this target
#endif
#define MASK_1 (P1_1 | P1_2)

28
features/unsupported/tests/mbed/portout_portin/main.cpp
View File

@ -121,14 +121,28 @@
defined(TARGET_NUCLEO_F411RE) || \
defined(TARGET_NUCLEO_L053R8) || \
defined(TARGET_NUCLEO_L073RZ) || \
defined(TARGET_NUCLEO_L476RG) || \
defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_NUCLEO_L152RE)
#define P1_1 (1 << 6) // PC_6
#define P1_2 (1 << 5) // PC_5
#define PORT_1 PortC
#define P1_1 (1 << 3) // PB_3 (D3)
#define P1_2 (1 << 10) // PB_10 (D6)
#define PORT_1 PortB
#define P2_1 (1 << 8) // PB_8
#define P2_2 (1 << 9) // PB_9
#define PORT_2 PortB
#define P2_1 (1 << 10) // PA_10 (D2)
#define P2_2 (1 << 8) // PA_8 (D7)
#define PORT_2 PortA
#elif defined(TARGET_NUCLEO_F767ZI) || \
defined(TARGET_NUCLEO_F303ZE) || \
defined(TARGET_NUCLEO_F207ZG) || \
defined(TARGET_NUCLEO_F746ZG)
#define P1_1 (1 << 13) // PE_13 (D3)
#define P1_2 (1 << 11) // PE_11 (D5)
#define PORT_1 PortE
#define P2_1 (1 << 15) // PF_15 (D2)
#define P2_2 (1 << 14) // PF_14 (D4)
#define PORT_2 PortF
#elif defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800)
#define P1_1 (1 << 0) // PD0
@ -212,7 +226,7 @@
#define PORT_2 Port5
#else
#error [NOT_SUPPORTED] This test is not supported on this target
#error [NOT_SUPPORTED] This test is not defined on this target
#endif
#define MASK_1 (P1_1 | P1_2)

4
mbed.h
View File

@ -16,13 +16,13 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 138
#define MBED_LIBRARY_VERSION 139
#if MBED_CONF_RTOS_PRESENT
// RTOS present, this is valid only for mbed OS 5
#define MBED_MAJOR_VERSION 5
#define MBED_MINOR_VERSION 4
#define MBED_PATCH_VERSION 1
#define MBED_PATCH_VERSION 2
#else
// mbed 2

6
platform/mbed_retarget.h
View File

@ -50,8 +50,13 @@ typedef int mode_t; ///< Mode for opening files
#if __cplusplus
namespace mbed { class Dir; }
typedef mbed::Dir DIR;
#else
typedef struct Dir DIR;
#endif
#if __cplusplus
extern "C" {
#endif
DIR *opendir(const char*);
struct dirent *readdir(DIR *);
int closedir(DIR*);
@ -59,6 +64,7 @@ extern "C" {
long telldir(DIR*);
void seekdir(DIR*, long);
int mkdir(const char *name, mode_t n);
#if __cplusplus
};
#endif

11
rtos/Thread.cpp
View File

@ -44,6 +44,7 @@ namespace rtos {
void Thread::constructor(osPriority priority,
uint32_t stack_size, unsigned char *stack_pointer) {
_tid = 0;
_finished = false;
_dynamic_stack = (stack_pointer == NULL);
#if defined(__MBED_CMSIS_RTOS_CA9) || defined(__MBED_CMSIS_RTOS_CM)
@ -74,7 +75,7 @@ void Thread::constructor(Callback<void()> task,
osStatus Thread::start(Callback<void()> task) {
_mutex.lock();
if (_tid != 0) {
if ((_tid != 0) || _finished) {
_mutex.unlock();
return osErrorParameter;
}
@ -117,6 +118,7 @@ osStatus Thread::terminate() {
osThreadId local_id = _tid;
_join_sem.release();
_tid = (osThreadId)NULL;
_finished = true;
ret = osThreadTerminate(local_id);
@ -177,11 +179,15 @@ int32_t Thread::signal_clr(int32_t signals) {
Thread::State Thread::get_state() {
#if !defined(__MBED_CMSIS_RTOS_CA9) && !defined(__MBED_CMSIS_RTOS_CM)
#ifdef CMSIS_OS_RTX
State status = Deleted;
State status;
_mutex.lock();
if (_tid != NULL) {
status = (State)_thread_def.tcb.state;
} else if (_finished) {
status = Deleted;
} else {
status = Inactive;
}
_mutex.unlock();
@ -367,6 +373,7 @@ void Thread::_thunk(const void * thread_ptr)
t->_task();
t->_mutex.lock();
t->_tid = (osThreadId)NULL;
t->_finished = true;
t->_join_sem.release();
// rtos will release the mutex automatically
}

10
rtos/Thread.h
View File

@ -197,6 +197,7 @@ public:
/** Starts a thread executing the specified function.
@param task function to be executed by this thread.
@return status code that indicates the execution status of the function.
@note a thread can only be started once
*/
osStatus start(mbed::Callback<void()> task);
@ -251,7 +252,7 @@ public:
/** State of the Thread */
enum State {
Inactive, /**< Not created or terminated */
Inactive, /**< Not created */
Ready, /**< Ready to run */
Running, /**< Running */
WaitingDelay, /**< Waiting for a delay to occur */
@ -330,6 +331,10 @@ public:
virtual ~Thread();
private:
/* disallow copy constructor and assignment operators */
Thread(const Thread&);
Thread& operator=(const Thread&);
// Required to share definitions without
// delegated constructors
void constructor(osPriority priority=osPriorityNormal,
@ -344,9 +349,10 @@ private:
mbed::Callback<void()> _task;
osThreadId _tid;
osThreadDef_t _thread_def;
bool _dynamic_stack;
Semaphore _join_sem;
Mutex _mutex;
bool _dynamic_stack;
bool _finished;
};
}

5
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/mbed_overrides.c
View File

@ -16,6 +16,7 @@
void mbed_sdk_init()
{
printf("", __TIME__, __DATE__);
char* debug_date = __DATE__;
char* debug_time = __TIME__;
}

116
targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h
View File

@ -23,95 +23,101 @@
extern "C" {
#endif
// NOTE: TIMER0_BASE=(APBPERIPH_BASE + 0x10000)
// TIMER1_BASE=(APBPERIPH_BASE + 0x10020)
#define NU_MODNAME(MODBASE, SUBINDEX) ((MODBASE) | (SUBINDEX))
#define NU_MODBASE(MODNAME) ((MODNAME) & 0xFFFFFFE0)
#define NU_MODSUBINDEX(MODNAME) ((MODNAME) & 0x0000001F)
// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name
// which encodes module base address and module index/subindex.
#define NU_MODSUBINDEX_Pos 0
#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos)
#define NU_MODINDEX_Pos 20
#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos)
#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos))
#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk))
#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos)
#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos)
#if 0
typedef enum {
GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0),
GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 0),
GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 0),
GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 0),
GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 0),
GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 0)
GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0),
GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0),
GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0),
GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0),
GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0),
GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0)
} GPIOName;
#endif
typedef enum {
ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0),
ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 1),
ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 2),
ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 3),
ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 4),
ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 5),
ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 6),
ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 7),
ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 8),
ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 9),
ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 10),
ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 11),
ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 12),
ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 13),
ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 14),
ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 15)
ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 0, 7),
ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 0, 8),
ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 0, 9),
ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 0, 10),
ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 0, 11),
ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 0, 12),
ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 0, 13),
ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 0, 14),
ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15)
} ADCName;
typedef enum {
UART_0 = (int) NU_MODNAME(UART0_BASE, 0),
UART_1 = (int) NU_MODNAME(UART1_BASE, 0),
UART_2 = (int) NU_MODNAME(UART2_BASE, 0),
UART_3 = (int) NU_MODNAME(UART3_BASE, 0),
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
// FIXME: board-specific
STDIO_UART = UART_3
} UARTName;
typedef enum {
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0),
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 0),
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 0)
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0)
} SPIName;
typedef enum {
I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0),
I2C_1 = (int) NU_MODNAME(I2C1_BASE, 0)
I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0),
I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0)
} I2CName;
typedef enum {
PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0),
PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 1),
PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 2),
PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 3),
PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 4),
PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 5),
PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0, 0),
PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 0, 1),
PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 0, 2),
PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 0, 3),
PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 0, 4),
PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 0, 5),
PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 0),
PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1),
PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 2),
PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 3),
PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 4),
PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 5)
PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 1, 0),
PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1, 1),
PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 1, 2),
PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 1, 3),
PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 1, 4),
PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 1, 5)
} PWMName;
typedef enum {
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x20, 0),
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x20, 0),
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x20, 1, 0),
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x20, 3, 0),
} TIMERName;
typedef enum {
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0)
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0)
} RTCName;
typedef enum {
DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0)
DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0, 0)
} DMAName;
typedef enum {
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0)
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0)
} CANName;
#ifdef __cplusplus

33
targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h
View File

@ -22,13 +22,32 @@
extern "C" {
#endif
#define NU_PORT_SHIFT 12
#define NU_PINNAME_TO_PORT(name) ((unsigned int)(name) >> NU_PORT_SHIFT)
#define NU_PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << NU_PORT_SHIFT))
#define NU_PORT_N_PIN_TO_PINNAME(port, pin) ((((unsigned int) (port)) << (NU_PORT_SHIFT)) | ((unsigned int) (pin)))
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
#define NU_MFP_POS(pin) ((pin % 8) * 4)
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
#define NU_PININDEX_Pos 0
#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos)
#define NU_PINPORT_Pos 8
#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos)
#define NU_PIN_MODINDEX_Pos 12
#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos)
#define NU_PIN_BIND_Pos 16
#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos)
#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos)
#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos)
#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos)
#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos)
#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos))
#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)
#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
#define NU_MFP_POS(pin) ((pin % 8) * 4)
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
// LEGACY
#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME)
#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME)
#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME)
#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN))
typedef enum {
PIN_INPUT,

43
targets/TARGET_NUVOTON/TARGET_M451/can_api.c
View File

@ -69,7 +69,7 @@
PA0 = 0x00;
PA1 = 0x00;
CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE);
CAN_Open((CAN_T *)NU_MODBASE(obj->can), 500000, CAN_NORMAL_MODE);
can_filter(obj, 0, 0, CANStandard, 0);
}
@ -91,9 +91,9 @@ void can_free(can_t *obj)
int can_frequency(can_t *obj, int hz)
{
CAN_SetBaudRate((CAN_T *)obj->can, hz);
CAN_SetBaudRate((CAN_T *)NU_MODBASE(obj->can), hz);
return CAN_GetCANBitRate((CAN_T *)obj->can);
return CAN_GetCANBitRate((CAN_T *)NU_MODBASE(obj->can));
}
static void can_irq(CANName name, int id)
@ -154,7 +154,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
void can_irq_free(can_t *obj)
{
CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
can_irq_ids[obj->index] = 0;
@ -163,8 +163,9 @@ void can_irq_free(can_t *obj)
void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
{
CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can);
CAN_EnterInitMode((CAN_T*)obj->can, ((enable != 0 )? CAN_CON_IE_Msk :0) );
CAN_EnterInitMode(can_base, ((enable != 0 )? CAN_CON_IE_Msk :0) );
switch (irq)
@ -172,15 +173,15 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
case IRQ_ERROR:
case IRQ_BUS:
case IRQ_PASSIVE:
((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk;
((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
can_base->CON = can_base->CON |CAN_CON_EIE_Msk;
can_base->CON = can_base->CON |CAN_CON_SIE_Msk;
break;
case IRQ_RX:
case IRQ_TX:
case IRQ_OVERRUN:
case IRQ_WAKEUP:
((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
can_base->CON = can_base->CON |CAN_CON_SIE_Msk;
break;
default:
@ -188,7 +189,7 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
}
CAN_LeaveInitMode((CAN_T*)obj->can);
CAN_LeaveInitMode(can_base);
NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
NVIC_EnableIRQ(CAN0_IRQn);
@ -205,14 +206,14 @@ int can_write(can_t *obj, CAN_Message msg, int cc)
CMsg.DLC = msg.len;
memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8);
return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg);
return CAN_Transmit((CAN_T *)NU_MODBASE(obj->can), cc, &CMsg);
}
int can_read(can_t *obj, CAN_Message *msg, int handle)
{
STR_CANMSG_T CMsg;
if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg))
if(!CAN_Receive((CAN_T *)NU_MODBASE(obj->can), handle, &CMsg))
return 0;
msg->format = (CANFormat)CMsg.IdType;
@ -226,32 +227,34 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
int can_mode(can_t *obj, CanMode mode)
{
CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can);
int success = 0;
switch (mode)
{
case MODE_RESET:
CAN_LeaveTestMode((CAN_T*)obj->can);
CAN_LeaveTestMode(can_base);
success = 1;
break;
case MODE_NORMAL:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk);
success = 1;
break;
case MODE_SILENT:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk);
success = 1;
break;
case MODE_TEST_LOCAL:
case MODE_TEST_GLOBAL:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_LBACK_Msk);
success = 1;
break;
case MODE_TEST_SILENT:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
success = 1;
break;
@ -267,7 +270,7 @@ int can_mode(can_t *obj, CanMode mode)
int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
{
return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id);
return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle , (uint32_t)format, id);
}
@ -285,19 +288,19 @@ void can_reset(can_t *obj)
unsigned char can_rderror(can_t *obj)
{
CAN_T *can = (CAN_T *)(obj->can);
CAN_T *can = (CAN_T *)NU_MODBASE(obj->can);
return ((can->ERR>>8)&0xFF);
}
unsigned char can_tderror(can_t *obj)
{
CAN_T *can = (CAN_T *)(obj->can);
CAN_T *can = (CAN_T *)NU_MODBASE(obj->can);
return ((can->ERR)&0xFF);
}
void can_monitor(can_t *obj, int silent)
{
CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk);
CAN_EnterTestMode((CAN_T *)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk);
}
#endif // DEVICE_CAN

1
targets/TARGET_NUVOTON/TARGET_M451/dma.h
View File

@ -32,6 +32,7 @@ extern "C" {
#define DMA_EVENT_MASK DMA_EVENT_ALL
void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event);
PDMA_T *dma_modbase(void);
#ifdef __cplusplus
}

7
targets/TARGET_NUVOTON/TARGET_M451/dma_api.c
View File

@ -111,6 +111,11 @@ void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t even
NVIC_EnableIRQ(dma_modinit.irq_n);
}
PDMA_T *dma_modbase(void)
{
return (PDMA_T *) NU_MODBASE(dma_modinit.modname);
}
static void pdma_vec(void)
{
uint32_t intsts = PDMA_GET_INT_STATUS();
@ -165,7 +170,7 @@ static void pdma_vec(void)
PDMA->INTSTS = reqto;
while (reqto) {
int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFn_Pos;
int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos;
if (dma_chn_mask & (1 << chn_id)) {
struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {

16
targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
View File

@ -99,9 +99,11 @@ void pwmout_init(pwmout_t* obj, PinName pin)
((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
// Mark this module to be inited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask |= 1 << i;
if (((struct nu_pwm_var *) modinit->var)->en_msk) {
// Mark this module to be inited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask |= 1 << i;
}
}
void pwmout_free(pwmout_t* obj)
@ -120,9 +122,11 @@ void pwmout_free(pwmout_t* obj)
CLK_DisableModuleClock(modinit->clkidx);
}
// Mark this module to be deinited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask &= ~(1 << i);
if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) {
// Mark this module to be deinited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask &= ~(1 << i);
}
}
void pwmout_write(pwmout_t* obj, float value)

28
targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
View File

@ -255,7 +255,7 @@ void serial_free(serial_t *obj)
void serial_baud(serial_t *obj, int baudrate) {
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
obj->serial.baudrate = baudrate;
UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
@ -263,7 +263,7 @@ void serial_baud(serial_t *obj, int baudrate) {
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
// TODO: Assert for not supported parity and data bits
obj->serial.databits = data_bits;
@ -325,7 +325,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
MBED_ASSERT(modinit != NULL);
@ -502,7 +502,9 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->serial.uart);
PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
PDMA_T *pdma_base = dma_modbase();
pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -515,7 +517,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
// NUC472: End of source address
// M451: Start of source address
PDMA_SAR_INC, // Source address incremental
(uint32_t) obj->serial.uart, // Destination address
(uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
PDMA_DAR_FIX); // Destination address fixed
PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
PDMA_REQ_SINGLE, // Single mode
@ -563,7 +565,9 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->serial.uart);
PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
PDMA_T *pdma_base = dma_modbase();
pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -572,7 +576,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
(rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
rx_length);
PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
(uint32_t) obj->serial.uart, // Source address
(uint32_t) NU_MODBASE(obj->serial.uart), // Source address
PDMA_SAR_FIX, // Source address fixed
(uint32_t) rx, // NOTE:
// NUC472: End of destination address
@ -593,14 +597,16 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
void serial_tx_abort_asynch(serial_t *obj)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
PDMA_T *pdma_base = dma_modbase();
if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
// FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->serial.dma_chn_id_tx);
PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
}
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
}
@ -615,11 +621,13 @@ void serial_tx_abort_asynch(serial_t *obj)
void serial_rx_abort_asynch(serial_t *obj)
{
if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
PDMA_T *pdma_base = dma_modbase();
if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
// FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->serial.dma_chn_id_rx);
PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
}
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
}

15
targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
View File

@ -314,8 +314,10 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->spi.spi);
PDMA_T *pdma_base = dma_modbase();
// Configure tx DMA
PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -339,7 +341,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
// Configure rx DMA
PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -380,6 +382,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
void spi_abort_asynch(spi_t *obj)
{
SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
PDMA_T *pdma_base = dma_modbase();
if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
// Receive FIFO Overrun in case of tx length > rx length on DMA way
@ -388,18 +391,18 @@ void spi_abort_asynch(spi_t *obj)
}
if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0);
PDMA_DisableInt(obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
// FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->spi.dma_chn_id_tx);
PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
}
SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0);
PDMA_DisableInt(obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
// FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->spi.dma_chn_id_rx);
PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
}
SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
}

140
targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h
View File

@ -23,111 +23,117 @@
extern "C" {
#endif
// NOTE: TIMER0_BASE=(APBPERIPH_BASE + 0x10000)
// TIMER1_BASE=(APBPERIPH_BASE + 0x10020)
#define NU_MODNAME(MODBASE, SUBINDEX) ((MODBASE) | (SUBINDEX))
#define NU_MODBASE(MODNAME) ((MODNAME) & 0xFFFFFFE0)
#define NU_MODSUBINDEX(MODNAME) ((MODNAME) & 0x0000001F)
// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name
// which encodes module base address and module index/subindex.
#define NU_MODSUBINDEX_Pos 0
#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos)
#define NU_MODINDEX_Pos 20
#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos)
#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos))
#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk))
#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos)
#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos)
#if 0
typedef enum {
GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0),
GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 0),
GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 0),
GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 0),
GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 0),
GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 0),
GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 0),
GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 0),
GPIO_I = (int) NU_MODNAME(GPIOI_BASE, 0)
GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0),
GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0),
GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0),
GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0),
GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0),
GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0),
GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 6, 0),
GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 7, 0),
GPIO_I = (int) NU_MODNAME(GPIOI_BASE, 8, 0)
} GPIOName;
#endif
typedef enum {
ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0),
ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 1),
ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 2),
ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 3),
ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 4),
ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 5),
ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 6),
ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 7),
ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 0, 7),
ADC_1_0 = (int) NU_MODNAME(EADC_BASE, 8),
ADC_1_1 = (int) NU_MODNAME(EADC_BASE, 9),
ADC_1_2 = (int) NU_MODNAME(EADC_BASE, 10),
ADC_1_3 = (int) NU_MODNAME(EADC_BASE, 11),
ADC_1_4 = (int) NU_MODNAME(EADC_BASE, 12),
ADC_1_5 = (int) NU_MODNAME(EADC_BASE, 13),
ADC_1_6 = (int) NU_MODNAME(EADC_BASE, 14),
ADC_1_7 = (int) NU_MODNAME(EADC_BASE, 15),
ADC_1_0 = (int) NU_MODNAME(EADC_BASE, 1, 0),
ADC_1_1 = (int) NU_MODNAME(EADC_BASE, 1, 1),
ADC_1_2 = (int) NU_MODNAME(EADC_BASE, 1, 2),
ADC_1_3 = (int) NU_MODNAME(EADC_BASE, 1, 3),
ADC_1_4 = (int) NU_MODNAME(EADC_BASE, 1, 4),
ADC_1_5 = (int) NU_MODNAME(EADC_BASE, 1, 5),
ADC_1_6 = (int) NU_MODNAME(EADC_BASE, 1, 6),
ADC_1_7 = (int) NU_MODNAME(EADC_BASE, 1, 7),
} ADCName;
typedef enum {
UART_0 = (int) NU_MODNAME(UART0_BASE, 0),
UART_1 = (int) NU_MODNAME(UART1_BASE, 0),
UART_2 = (int) NU_MODNAME(UART2_BASE, 0),
UART_3 = (int) NU_MODNAME(UART3_BASE, 0),
UART_4 = (int) NU_MODNAME(UART4_BASE, 0),
UART_5 = (int) NU_MODNAME(UART5_BASE, 0),
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
// FIXME: board-specific
STDIO_UART = UART_3
} UARTName;
typedef enum {
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0),
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 0),
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 0),
SPI_3 = (int) NU_MODNAME(SPI3_BASE, 0)
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0),
SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0)
} SPIName;
typedef enum {
I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0),
I2C_1 = (int) NU_MODNAME(I2C1_BASE, 0),
I2C_2 = (int) NU_MODNAME(I2C2_BASE, 0),
I2C_3 = (int) NU_MODNAME(I2C3_BASE, 0),
I2C_4 = (int) NU_MODNAME(I2C4_BASE, 0)
I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0),
I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0),
I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0),
I2C_3 = (int) NU_MODNAME(I2C3_BASE, 3, 0),
I2C_4 = (int) NU_MODNAME(I2C4_BASE, 4, 0)
} I2CName;
typedef enum {
PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0),
PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 1),
PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 2),
PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 3),
PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 4),
PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 5),
PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0, 0),
PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 0, 1),
PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 0, 2),
PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 0, 3),
PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 0, 4),
PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 0, 5),
PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 0),
PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1),
PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 2),
PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 3),
PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 4),
PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 5)
PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 1, 0),
PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1, 1),
PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 1, 2),
PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 1, 3),
PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 1, 4),
PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 1, 5)
} PWMName;
typedef enum {
TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0),
TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 0),
TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 0),
TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 0)
TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0, 0),
TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 1, 0),
TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 2, 0),
TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 3, 0)
} TIMERName;
typedef enum {
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0)
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0)
} RTCName;
typedef enum {
DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0)
DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0, 0)
} DMAName;
typedef enum {
SD_0_0 = (int) NU_MODNAME(SD_BASE, 0),
SD_0_1 = (int) NU_MODNAME(SD_BASE, 1)
SD_0_0 = (int) NU_MODNAME(SD_BASE, 0, 0),
SD_0_1 = (int) NU_MODNAME(SD_BASE, 0, 1)
} SDName;
typedef enum {
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0),
CAN_1 = (int) NU_MODNAME(CAN1_BASE, 0)
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0),
CAN_1 = (int) NU_MODNAME(CAN1_BASE, 1, 0)
} CANName;
#ifdef __cplusplus

33
targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h
View File

@ -22,13 +22,32 @@
extern "C" {
#endif
#define NU_PORT_SHIFT 12
#define NU_PINNAME_TO_PORT(name) ((unsigned int)(name) >> NU_PORT_SHIFT)
#define NU_PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << NU_PORT_SHIFT))
#define NU_PORT_N_PIN_TO_PINNAME(port, pin) ((((unsigned int) (port)) << (NU_PORT_SHIFT)) | ((unsigned int) (pin)))
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
#define NU_MFP_POS(pin) ((pin % 8) * 4)
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
#define NU_PININDEX_Pos 0
#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos)
#define NU_PINPORT_Pos 8
#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos)
#define NU_PIN_MODINDEX_Pos 12
#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos)
#define NU_PIN_BIND_Pos 16
#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos)
#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos)
#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos)
#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos)
#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos)
#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos))
#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)
#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
#define NU_MFP_POS(pin) ((pin % 8) * 4)
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
// LEGACY
#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME)
#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME)
#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME)
#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN))
typedef enum {
PIN_INPUT,

16
targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c
View File

@ -70,25 +70,27 @@ void analogin_init(analogin_t *obj, PinName pin)
EADC_Open(eadc_base, 0);
}
uint32_t chn = NU_MODSUBINDEX(obj->adc);
uint32_t smp_chn = NU_MODSUBINDEX(obj->adc);
uint32_t smp_mod = NU_MODINDEX(obj->adc) * 8 + smp_chn;
// Wire pinout
pinmap_pinout(pin, PinMap_ADC);
// Configure the sample module Nmod for analog input channel Nch and software trigger source
EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn % 8);
EADC_ConfigSampleModule(eadc_base, smp_mod, EADC_SOFTWARE_TRIGGER, smp_chn);
eadc_modinit_mask |= 1 << chn;
eadc_modinit_mask |= 1 << smp_mod;
}
uint16_t analogin_read_u16(analogin_t *obj)
{
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
uint32_t chn = NU_MODSUBINDEX(obj->adc);
uint32_t smp_chn = NU_MODSUBINDEX(obj->adc);
uint32_t smp_mod = NU_MODINDEX(obj->adc) * 8 + smp_chn;
EADC_START_CONV(eadc_base, 1 << chn);
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != (1 << chn));
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
EADC_START_CONV(eadc_base, 1 << smp_mod);
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << smp_mod) != (1 << smp_mod));
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, smp_mod);
// Just 12 bits are effective. Convert to 16 bits.
// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
// conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8

45
targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c
View File

@ -75,7 +75,7 @@
PA2 = 0x00;
PA3 = 0x00;
CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE);
CAN_Open((CAN_T *)NU_MODBASE(obj->can), 500000, CAN_NORMAL_MODE);
can_filter(obj, 0, 0, CANStandard, 0);
}
@ -97,9 +97,9 @@ void can_free(can_t *obj)
int can_frequency(can_t *obj, int hz)
{
CAN_SetBaudRate((CAN_T *)obj->can, hz);
CAN_SetBaudRate((CAN_T *)NU_MODBASE(obj->can), hz);
return CAN_GetCANBitRate((CAN_T *)obj->can);
return CAN_GetCANBitRate((CAN_T *)NU_MODBASE(obj->can));
}
static void can_irq(CANName name, int id)
@ -188,7 +188,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
void can_irq_free(can_t *obj)
{
CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
can_irq_ids[obj->index] = 0;
@ -202,25 +202,26 @@ void can_irq_free(can_t *obj)
void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
{
CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can);
CAN_EnterInitMode((CAN_T*)obj->can);
CAN_EnterInitMode((CAN_T*)can_base);
((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON ) | ((enable != 0 )? CAN_CON_IE_Msk :0);
((CAN_T *)can_base)->CON = (((CAN_T *)can_base)->CON ) | ((enable != 0 )? CAN_CON_IE_Msk :0);
switch (irq)
{
case IRQ_ERROR:
case IRQ_BUS:
case IRQ_PASSIVE:
((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk;
((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
can_base->CON = can_base->CON |CAN_CON_EIE_Msk;
can_base->CON = can_base->CON |CAN_CON_SIE_Msk;
break;
case IRQ_RX:
case IRQ_TX:
case IRQ_OVERRUN:
case IRQ_WAKEUP:
((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
can_base->CON = can_base->CON |CAN_CON_SIE_Msk;
break;
default:
@ -228,7 +229,7 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
}
CAN_LeaveInitMode((CAN_T*)obj->can);
CAN_LeaveInitMode(can_base);
if(!obj->index)
{
@ -253,14 +254,14 @@ int can_write(can_t *obj, CAN_Message msg, int cc)
CMsg.DLC = msg.len;
memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8);
return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg);
return CAN_Transmit((CAN_T *)NU_MODBASE(obj->can), cc, &CMsg);
}
int can_read(can_t *obj, CAN_Message *msg, int handle)
{
STR_CANMSG_T CMsg;
if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg))
if(!CAN_Receive((CAN_T *)NU_MODBASE(obj->can), handle, &CMsg))
return 0;
msg->format = (CANFormat)CMsg.IdType;
@ -274,32 +275,34 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
int can_mode(can_t *obj, CanMode mode)
{
CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can);
int success = 0;
switch (mode)
{
case MODE_RESET:
CAN_LeaveTestMode((CAN_T*)obj->can);
CAN_LeaveTestMode(can_base);
success = 1;
break;
case MODE_NORMAL:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk);
success = 1;
break;
case MODE_SILENT:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk);
success = 1;
break;
case MODE_TEST_LOCAL:
case MODE_TEST_GLOBAL:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_LBACK_Msk);
success = 1;
break;
case MODE_TEST_SILENT:
CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
success = 1;
break;
@ -315,7 +318,7 @@ int can_mode(can_t *obj, CanMode mode)
int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
{
return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id);
return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle , (uint32_t)format, id);
}
@ -333,19 +336,19 @@ void can_reset(can_t *obj)
unsigned char can_rderror(can_t *obj)
{
CAN_T *can = (CAN_T *)(obj->can);
CAN_T *can = (CAN_T *)NU_MODBASE(obj->can);
return ((can->ERR>>8)&0xFF);
}
unsigned char can_tderror(can_t *obj)
{
CAN_T *can = (CAN_T *)(obj->can);
CAN_T *can = (CAN_T *)NU_MODBASE(obj->can);
return ((can->ERR)&0xFF);
}
void can_monitor(can_t *obj, int silent)
{
CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk);
CAN_EnterTestMode((CAN_T *)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk);
}
#endif // DEVICE_CAN

1
targets/TARGET_NUVOTON/TARGET_NUC472/dma.h
View File

@ -32,6 +32,7 @@ extern "C" {
#define DMA_EVENT_MASK DMA_EVENT_ALL
void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event);
PDMA_T *dma_modbase(void);
#ifdef __cplusplus
}

7
targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c
View File

@ -111,6 +111,11 @@ void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t even
NVIC_EnableIRQ(dma_modinit.irq_n);
}
PDMA_T *dma_modbase(void)
{
return (PDMA_T *) NU_MODBASE(dma_modinit.modname);
}
static void pdma_vec(void)
{
uint32_t intsts = PDMA_GET_INT_STATUS();
@ -165,7 +170,7 @@ static void pdma_vec(void)
PDMA->INTSTS = reqto;
while (reqto) {
int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFX_Pos;
int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFX_Pos;
if (dma_chn_mask & (1 << chn_id)) {
struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {

16
targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c
View File

@ -105,9 +105,11 @@ void pwmout_init(pwmout_t* obj, PinName pin)
((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
// Mark this module to be inited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask |= 1 << i;
if (((struct nu_pwm_var *) modinit->var)->en_msk) {
// Mark this module to be inited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask |= 1 << i;
}
}
void pwmout_free(pwmout_t* obj)
@ -143,9 +145,11 @@ void pwmout_free(pwmout_t* obj)
}
}
// Mark this module to be deinited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask &= ~(1 << i);
if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) {
// Mark this module to be deinited.
int i = modinit - pwm_modinit_tab;
pwm_modinit_mask &= ~(1 << i);
}
}
void pwmout_write(pwmout_t* obj, float value)

28
targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c
View File

@ -285,7 +285,7 @@ void serial_free(serial_t *obj)
void serial_baud(serial_t *obj, int baudrate) {
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
obj->serial.baudrate = baudrate;
UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
@ -293,7 +293,7 @@ void serial_baud(serial_t *obj, int baudrate) {
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
// TODO: Assert for not supported parity and data bits
obj->serial.databits = data_bits;
@ -357,7 +357,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
MBED_ASSERT(modinit != NULL);
@ -544,7 +544,9 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->serial.uart);
PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
PDMA_T *pdma_base = dma_modbase();
pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -555,7 +557,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
((uint32_t) tx) + (tx_width / 8) * tx_length, // NOTE: End of source address
PDMA_SAR_INC, // Source address incremental
(uint32_t) obj->serial.uart, // Destination address
(uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
PDMA_DAR_FIX); // Destination address fixed
PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
PDMA_REQ_SINGLE, // Single mode
@ -603,7 +605,9 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->serial.uart);
PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
PDMA_T *pdma_base = dma_modbase();
pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -612,7 +616,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
(rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
rx_length);
PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
(uint32_t) obj->serial.uart, // Source address
(uint32_t) NU_MODBASE(obj->serial.uart), // Source address
PDMA_SAR_FIX, // Source address fixed
((uint32_t) rx) + (rx_width / 8) * rx_length, // NOTE: End of destination address
PDMA_DAR_INC); // Destination address incremental
@ -631,14 +635,16 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
void serial_tx_abort_asynch(serial_t *obj)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
PDMA_T *pdma_base = dma_modbase();
if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(obj->serial.dma_chn_id_tx, 0);
// FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->serial.dma_chn_id_tx);
PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
}
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
}
@ -653,11 +659,13 @@ void serial_tx_abort_asynch(serial_t *obj)
void serial_rx_abort_asynch(serial_t *obj)
{
if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
PDMA_T *pdma_base = dma_modbase();
if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(obj->serial.dma_chn_id_rx, 0);
// FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->serial.dma_chn_id_rx);
PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
}
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
}

11
targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c
View File

@ -317,8 +317,10 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->spi.spi);
PDMA_T *pdma_base = dma_modbase();
// Configure tx DMA
PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -340,7 +342,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
// Configure rx DMA
PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
@ -379,6 +381,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
void spi_abort_asynch(spi_t *obj)
{
SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
PDMA_T *pdma_base = dma_modbase();
if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
// Receive FIFO Overrun in case of tx length > rx length on DMA way
@ -390,7 +393,7 @@ void spi_abort_asynch(spi_t *obj)
PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0);
// FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->spi.dma_chn_id_tx);
PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
}
SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
@ -398,7 +401,7 @@ void spi_abort_asynch(spi_t *obj)
PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0);
// FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->spi.dma_chn_id_rx);
PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
}
SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
}

6
targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h
View File

@ -37,6 +37,7 @@ extern "C" {
#endif
typedef enum {
NC = (int)0xFFFFFFFF,
GPIO0 = 0,
GPIO1,
GPIO2,
@ -59,6 +60,8 @@ typedef enum {
A1,
A2,
A3,
A4 = NC,
A5 = NC,
UART1_TX = GPIO0,
UART1_RX = GPIO1,
UART2_TX = GPIO8,
@ -146,8 +149,7 @@ typedef enum {
D12 = GPIO16,
D13 = GPIO14,
D14 = GPIO3,
D15 = GPIO2,
NC = (int)0xFFFFFFFF
D15 = GPIO2
} PinName;
typedef enum {

2
targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c
View File

@ -88,7 +88,7 @@ void analogin_init(analogin_t *obj, PinName pin)
/* Single sample, absolute conversion, scale = 1 */
obj->adcReg->CONTROL.WORD = ((0 << ADC_CONTROL_MODE_BIT_POS) |
(1 << ADC_CONTROL_MEASTYPE_BIT_POS) |
(1 << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(6 << ADC_CONTROL_INPUTSCALE_BIT_POS) |
(((uint8_t)adc_pin) << ADC_CONTROL_MEAS_CH_BIT_POS));
/* Prescaler enabled; set to 7 */

9
targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
View File

@ -398,10 +398,11 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
break;
}
obj->serial.uart->SCSMR = data_bits << 6
| parity_enable << 5
| parity_select << 4
| stop_bits << 3;
obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078)
| (data_bits << 6)
| (parity_enable << 5)
| (parity_select << 4)
| (stop_bits << 3);
}
/******************************************************************************

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralPins.c
View File

@ -226,13 +226,13 @@ const PinMap PinMap_SPI_SSEL[] = {
};
const PinMap PinMap_CAN_RD[] = {
// {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, // Not available in 32 pins package
{PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
// {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, // Not available in 32 pins package
{PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
{NC, NC, 0}
};

4
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf
View File

@ -15,9 +15,9 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
/*-Sizes-*/
/*Heap 1/2 of ram and stack 1/8*/
/*Heap 64K and stack 24K */
define symbol __ICFEDIT_size_cstack__ = 0x6000;
define symbol __ICFEDIT_size_heap__ = 0x18000;
define symbol __ICFEDIT_size_heap__ = 0x10000;
/**** End of ICF editor section. ###ICF###*/

4
targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_IAR/stm32f439xx_flash.icf
View File

@ -15,9 +15,9 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
/*-Sizes-*/
/*Heap 1/2 of ram and stack 1/8*/
/*Heap 64kB and stack 24kB */
define symbol __ICFEDIT_size_cstack__ = 0x6000;
define symbol __ICFEDIT_size_heap__ = 0x18000;
define symbol __ICFEDIT_size_heap__ = 0x10000;
/**** End of ICF editor section. ###ICF###*/

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_stm32f7xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

20436
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h
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File diff suppressed because it is too large Load Diff

10
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -111,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.2
* @brief CMSIS Device version number V1.2.0
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/system_stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_stm32f7xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

20702
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h
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File diff suppressed because it is too large Load Diff

10
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -111,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.2
* @brief CMSIS Device version number V1.2.0
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/system_stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_stm32f7xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

21588
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h
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10
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -111,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.2
* @brief CMSIS Device version number V1.2.0
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/system_stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_stm32f7xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

25494
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h
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10
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -111,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.2
* @brief CMSIS Device version number V1.2.0
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/system_stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention

70
targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html
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144
targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -241,9 +241,9 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
#define DAC_WAVE_NONE 0x00000000U
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
@ -917,48 +917,45 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
#define ETH_MMCCR ((uint32_t)0x00000100U)
#define ETH_MMCRIR ((uint32_t)0x00000104U)
#define ETH_MMCTIR ((uint32_t)0x00000108U)
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MMCCR 0x00000100U
#define ETH_MMCRIR 0x00000104U
#define ETH_MMCTIR 0x00000108U
#define ETH_MMCRIMR 0x0000010CU
#define ETH_MMCTIMR 0x00000110U
#define ETH_MMCTGFSCCR 0x0000014CU
#define ETH_MMCTGFMSCCR 0x00000150U
#define ETH_MMCTGFCR 0x00000168U
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
/**
* @}
@ -2231,26 +2228,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@ -2784,11 +2781,14 @@
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
/**
* @}
*/
@ -2918,6 +2918,14 @@
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
/**
* @}
*/

10
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -68,11 +68,11 @@
* @{
*/
/**
* @brief STM32F7xx HAL Driver version number V1.1.2
* @brief STM32F7xx HAL Driver version number V1.2.0
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************

6
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@ -270,7 +270,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));

65
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
@ -88,6 +88,7 @@ typedef struct
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
Scan direction is upward: from rank1 to rank 'n'.
This parameter can be a value of @ref ADC_Scan_mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
This parameter can be a value of @ref ADC_EOCSelection.
@ -135,7 +136,8 @@ typedef struct
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels */
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
This parameter must be a number between Min_Data = 1 and Max_Data = 16
This parameter can be a value of @ref ADC_regular_rank */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
@ -337,6 +339,38 @@ typedef struct
* @}
*/
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
/**
* @}
*/
/** @defgroup ADC_regular_rank ADC group regular sequencer rank
* @{
*/
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
/**
* @}
*/
/** @defgroup ADC_channels ADC Common Channels
* @{
*/
@ -705,7 +739,8 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((__REGTRIG__) == ADC_SOFTWARE_START))
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
((__ALIGN__) == ADC_DATAALIGN_LEFT))
((__ALIGN__) == ADC_DATAALIGN_LEFT))
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
@ -730,9 +765,29 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
((__RANK__) == ADC_REGULAR_RANK_2 ) || \
((__RANK__) == ADC_REGULAR_RANK_3 ) || \
((__RANK__) == ADC_REGULAR_RANK_4 ) || \
((__RANK__) == ADC_REGULAR_RANK_5 ) || \
((__RANK__) == ADC_REGULAR_RANK_6 ) || \
((__RANK__) == ADC_REGULAR_RANK_7 ) || \
((__RANK__) == ADC_REGULAR_RANK_8 ) || \
((__RANK__) == ADC_REGULAR_RANK_9 ) || \
((__RANK__) == ADC_REGULAR_RANK_10) || \
((__RANK__) == ADC_REGULAR_RANK_11) || \
((__RANK__) == ADC_REGULAR_RANK_12) || \
((__RANK__) == ADC_REGULAR_RANK_13) || \
((__RANK__) == ADC_REGULAR_RANK_14) || \
((__RANK__) == ADC_REGULAR_RANK_15) || \
((__RANK__) == ADC_REGULAR_RANK_16))
#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
((__SCAN_MODE__) == ADC_SCAN_ENABLE))
#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions

13
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
@ -217,7 +217,7 @@ typedef struct
* @}
*/
/** @defgroup ADCEx_injected_rank ADC Injected Rank
/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
@ -333,9 +333,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \
((__RANK__) == ADC_INJECTED_RANK_2) || \
((__RANK__) == ADC_INJECTED_RANK_3) || \
((__RANK__) == ADC_INJECTED_RANK_4))
#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))
/**
* @brief Set the selected injected Channel rank.

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:

10
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -232,8 +232,8 @@ typedef struct
HAL_LockTypeDef Lock; /*!< CAN locking object */
__IO uint32_t ErrorCode; /*!< CAN Error code */
__IO uint32_t ErrorCode; /*!< CAN Error code
This parameter can be a value of @ref CAN_Error_Code */
}CAN_HandleTypeDef;
/**
@ -245,7 +245,7 @@ typedef struct
* @{
*/
/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface

8
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
@ -43,11 +43,11 @@
extern "C" {
#endif
#if defined (CEC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
#if defined (CEC)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/

15
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief HAL configuration file.
******************************************************************************
* @attention
@ -95,6 +95,8 @@
#define HAL_DSI_MODULE_ENABLED
#define HAL_JPEG_MODULE_ENABLED
#define HAL_MDIOS_MODULE_ENABLED
#define HAL_SMBUS_MODULE_ENABLED
#define HAL_MMC_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
@ -103,7 +105,6 @@
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
//#if !defined (HSE_VALUE)
#if defined(TARGET_DISCO_F746NG) || defined(TARGET_DISCO_F769NI)
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#else
@ -427,6 +428,14 @@
#include "stm32f7xx_hal_mdios.h"
#endif /* HAL_MDIOS_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f7xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f7xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention

1365
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c
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File diff suppressed because it is too large Load Diff

636
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@ -527,6 +527,638 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
* @}
*/
#if defined (AES)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup CRYP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRYP_Exported_Types CRYP Exported Types
* @{
*/
/**
* @brief CRYP Configuration Structure definition
*/
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< 128 or 256-bit key length.
This parameter can be a value of @ref CRYP_Key_Size */
uint32_t OperatingMode; /*!< AES operating mode.
This parameter can be a value of @ref CRYP_AES_OperatingMode */
uint32_t ChainingMode; /*!< AES chaining mode.
This parameter can be a value of @ref CRYP_AES_ChainingMode */
uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption.
This parameter can be a value of @ref CRYP_Key_Write */
uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
Galois Message Authentication Code (GMAC) or Cipher Message
Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when
the latter is applicable.
This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
uint8_t* pKey; /*!< Encryption/Decryption Key */
uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC,
(and CCM when applicable) modes */
uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */
uint64_t HeaderSize; /*!< Header size in bytes */
}CRYP_InitTypeDef;
/**
* @brief HAL CRYP State structures definition
*/
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
HAL_CRYP_STATE_ERROR = 0x04, /*!< CRYP error state */
HAL_CRYP_STATE_SUSPENDED = 0x05 /*!< CRYP suspended */
}HAL_CRYP_STATETypeDef;
/**
* @brief HAL CRYP phase structures definition
*/
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but
GCM/GMAC/CMAC(/CCM) initialization phase has not started */
HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out */
HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out */
HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */
HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out */
HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended */
HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */
HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */
}HAL_PhaseTypeDef;
/**
* @brief HAL CRYP mode suspend definitions
*/
typedef enum
{
HAL_CRYP_SUSPEND_NONE = 0x00, /*!< CRYP peripheral suspension not requested */
HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */
}HAL_SuspendTypeDef;
/**
* @brief HAL CRYP Error Codes definition
*/
#define HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001) /*!< Write error */
#define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */
#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */
#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */
/**
* @brief CRYP handle Structure definition
*/
typedef struct
{
AES_TypeDef *Instance; /*!< Register base address */
CRYP_InitTypeDef Init; /*!< CRYP initialization parameters */
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining
number of bytes to process */
uint32_t CrypOutCount; /*!< Output data size in bytes */
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC
(or CCM when applicable) modes.
Indicates the last phase carried out to ease
phase transitions */
DMA_HandleTypeDef *hdmain; /*!< CRYP peripheral Input DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< CRYP peripheral Output DMA handle parameters */
HAL_LockTypeDef Lock; /*!< CRYP locking object */
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
}CRYP_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
* @{
*/
/** @defgroup CRYP_Key_Size Key size selection
* @{
*/
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
/**
* @}
*/
/** @defgroup CRYP_Data_Type AES Data Type selection
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) /*!< 32-bit data type (no swapping) */
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
/**
* @}
*/
/** @defgroup CRYP_AES_State AES Enable state
* @{
*/
#define CRYP_AES_DISABLE ((uint32_t)0x00000000) /*!< Disable AES */
#define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */
/**
* @}
*/
/** @defgroup CRYP_AES_OperatingMode AES operating mode
* @{
*/
#define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */
#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */
#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */
#define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC authentication tag generation */
/**
* @}
*/
/** @defgroup CRYP_AES_ChainingMode AES chaining mode
* @{
*/
#define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000) /*!< Electronic codebook chaining algorithm */
#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */
#if defined(AES_CR_NPBLB)
#define CRYP_CHAINMODE_AES_CCM_CMAC AES_CR_CHMOD_2 /*!< Counter with Cipher Mode - Cipher message authentication code */
#endif
/**
* @}
*/
/** @defgroup CRYP_Key_Write AES decryption key write-up flag
* @{
*/
#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */
#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */
/**
* @}
*/
/** @defgroup CRYP_DMAIN DMA Input phase management enable state
* @{
*/
#define CRYP_DMAIN_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Input phase management */
#define CRYP_DMAIN_ENABLE AES_CR_DMAINEN /*!< Enable DMA Input phase management */
/**
* @}
*/
/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
* @{
*/
#define CRYP_DMAOUT_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Output phase management */
#define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */
/**
* @}
*/
/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
* @{
*/
#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */
#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC or (CCM/)CMAC header phase */
#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC or (CCM/)CMAC final phase */
/* Definitions duplication for code readibility's sake:
supported or not supported chain modes are not specified for each phase */
#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */
#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */
#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */
#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */
/**
* @}
*/
/** @defgroup CRYP_Flags AES status flags
* @{
*/
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
/**
* @}
*/
/** @defgroup CRYP_Clear_Flags AES clearing flags
* @{
*/
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
/**
* @}
*/
/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
* @{
*/
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
/**
* @}
*/
/** @defgroup CRYP_Interrupts_Flags AES Interrupts flags
* @{
*/
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
* @{
*/
/** @brief Reset CRYP handle state.
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
/**
* @brief Enable the CRYP AES peripheral.
* @retval None
*/
#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
/**
* @brief Disable the CRYP AES peripheral.
* @retval None
*/
#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
/**
* @brief Set the algorithm operating mode.
* @param __OPERATING_MODE__: specifies the operating mode
* This parameter can be one of the following values:
* @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
* @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
* @arg @ref CRYP_ALGOMODE_DECRYPT decryption
* @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
* @retval None
*/
#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
/**
* @brief Set the algorithm chaining mode.
* @param __CHAINING_MODE__: specifies the chaining mode
* This parameter can be one of the following values:
* @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
* @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
* @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
* @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
* @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
* @retval None
*/
#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the CRYP pending status flag.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @retval None
*/
#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
* @param __INTERRUPT__: CRYP interrupt source to check
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @retval State of interruption (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Clear the CRYP pending interrupt.
* @param __INTERRUPT__: specifies the IT to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @retval None
*/
#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
/**
* @brief Enable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @retval None
*/
#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @retval None
*/
#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup CRYP_Private_Macros CRYP Private Macros
* @{
*/
/**
* @brief Verify the key size length.
* @param __KEYSIZE__: Ciphering/deciphering algorithm key size.
* @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
*/
#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
((__KEYSIZE__) == CRYP_KEYSIZE_256B))
/**
* @brief Verify the input data type.
* @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
((__DATATYPE__) == CRYP_DATATYPE_16B) || \
((__DATATYPE__) == CRYP_DATATYPE_8B) || \
((__DATATYPE__) == CRYP_DATATYPE_1B))
/**
* @brief Verify the CRYP AES IP running mode.
* @param __MODE__: CRYP AES IP running mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
((__MODE__) == CRYP_AES_ENABLE))
/**
* @brief Verify the selected CRYP algorithm.
* @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
* @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
*/
#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \
((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \
((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \
((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))
/**
* @brief Verify the selected CRYP chaining algorithm.
* @param __CHAINMODE__: Selected CRYP chaining algorithm.
* @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
*/
#if defined(AES_CR_NPBLB)
#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC))
#else
#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
#endif
/**
* @brief Verify the deciphering key write option.
* @param __WRITE__: deciphering key write option.
* @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
*/
#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \
((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
/**
* @brief Verify the CRYP input data DMA mode.
* @param __MODE__: CRYP input data DMA mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
((__MODE__) == CRYP_DMAIN_ENABLE))
/**
* @brief Verify the CRYP output data DMA mode.
* @param __MODE__: CRYP output data DMA mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
((__MODE__) == CRYP_DMAOUT_ENABLE))
/**
* @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
* @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
* @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
*/
#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE) || \
((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
/**
* @}
*/
/* Include CRYP HAL Extended module */
#include "stm32f7xx_hal_cryp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
* @{
*/
/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
/* MSP initialization/de-initialization functions ****************************/
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions
* @{
*/
/* AES encryption/decryption processing functions ****************************/
/* AES encryption/decryption using polling ***********************************/
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
/* AES encryption/decryption using interrupt *********************************/
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
/* AES encryption/decryption using DMA ***************************************/
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
* @{
*/
/* CallBack functions ********************************************************/
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
* @{
*/
/* AES interrupt handling function *******************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions
* @{
*/
/* Peripheral State functions ************************************************/
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* AES */
#ifdef __cplusplus
}
#endif

2999
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c
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74
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
@ -209,6 +209,76 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
#endif /* CRYP */
#if defined (AES)
/** @addtogroup CRYPEx_Exported_Functions
* @{
*/
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
*/
/* CallBack functions ********************************************************/
void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
*/
/* AES encryption/decryption processing functions ****************************/
HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
/* AES encryption/decryption/authentication processing functions *************/
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
/**
* @}
*/
/** @addtogroup CRYPEx_Exported_Functions_Group3
* @{
*/
/* AES suspension/resumption functions ***************************************/
void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/**
* @}
*/
/* Private functions -----------------------------------------------------------*/
/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
* @{
*/
HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
#endif /* AES */
/**
* @}

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.1.2
* @date 23-September-2016
* @version V1.2.0
* @date 30-December-2016
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:

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