diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h deleted file mode 100644 index 156ec40c4b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h +++ /dev/null @@ -1,207 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_adc.h - * @brief This file provides all the functions prototypes for ADC driver. - * @version V2.0.2.1 - * @date 2015/10/09 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_ADC_H -#define __TMPM066_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -#if defined(__TMPM066_ADC_H) - -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -#define ADC_CONVERSION_35_CLOCK ((uint32_t)0x00000000) /* 35.5 conversion clock */ -#define ADC_CONVERSION_42_CLOCK ((uint32_t)0x00000040) /* 42 conversion clock */ -#define ADC_CONVERSION_68_CLOCK ((uint32_t)0x00000080) /* 68 conversion clock */ -#define ADC_CONVERSION_81_CLOCK ((uint32_t)0x000000C0) /* 81 conversion clock */ -#define IS_ADC_CONVERSION_TIME(param) (((param) == ADC_CONVERSION_35_CLOCK) || \ - ((param) == ADC_CONVERSION_42_CLOCK) || \ - ((param) == ADC_CONVERSION_68_CLOCK) || \ - ((param) == ADC_CONVERSION_81_CLOCK)) - -#define ADC_FC_DIVIDE_LEVEL_1 ((uint32_t)0x00000000) -#define ADC_FC_DIVIDE_LEVEL_2 ((uint32_t)0x00000001) -#define ADC_FC_DIVIDE_LEVEL_4 ((uint32_t)0x00000002) -#define ADC_FC_DIVIDE_LEVEL_6 ((uint32_t)0x00000008) -#define ADC_FC_DIVIDE_LEVEL_8 ((uint32_t)0x00000003) -#define ADC_FC_DIVIDE_LEVEL_12 ((uint32_t)0x00000009) -#define ADC_FC_DIVIDE_LEVEL_16 ((uint32_t)0x00000004) -#define ADC_FC_DIVIDE_LEVEL_24 ((uint32_t)0x0000000A) -#define ADC_FC_DIVIDE_LEVEL_48 ((uint32_t)0x0000000B) -#define ADC_FC_DIVIDE_LEVEL_96 ((uint32_t)0x0000000C) -#define IS_ADC_PRESCALER(param) (((param) == ADC_FC_DIVIDE_LEVEL_1) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_2) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_4) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_6) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_8) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_12) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_16) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_24) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_48) || \ - ((param) == ADC_FC_DIVIDE_LEVEL_96)) - -#define ADC_INT_SINGLE ((uint32_t)0x00000000) -#define ADC_INT_CONVERSION_4 ((uint32_t)0x00000008) -#define ADC_INT_CONVERSION_8 ((uint32_t)0x00000010) -#define IS_ADC_INT_MODE(param) (((param) == ADC_INT_SINGLE) || \ - ((param) == ADC_INT_CONVERSION_4) || \ - ((param) == ADC_INT_CONVERSION_8)) - -#define ADC_AN_0 ((uint32_t)0x00000000) -#define ADC_AN_1 ((uint32_t)0x00000001) -#define ADC_AN_2 ((uint32_t)0x00000002) -#define ADC_AN_3 ((uint32_t)0x00000003) -#define ADC_AN_4 ((uint32_t)0x00000004) -#define ADC_AN_5 ((uint32_t)0x00000005) -#define ADC_AN_6 ((uint32_t)0x00000006) -#define ADC_AN_7 ((uint32_t)0x00000007) - -#define IS_ADC_INPUT_CH(param) (((param) == ADC_AN_0) || \ - ((param) == ADC_AN_1) || \ - ((param) == ADC_AN_2) || \ - ((param) == ADC_AN_3) || \ - ((param) == ADC_AN_4) || \ - ((param) == ADC_AN_5) || \ - ((param) == ADC_AN_6) || \ - ((param) == ADC_AN_7)) - - -#define ADC_CMP_0 ((uint8_t)0x00) -#define ADC_CMP_1 ((uint8_t)0x01) -#define IS_ADC_CMP(param) (((param) == ADC_CMP_0) || \ - ((param) == ADC_CMP_1)) - -#define ADC_REG_0 ((uint32_t)0x00000000) -#define ADC_REG_1 ((uint32_t)0x00000001) -#define ADC_REG_2 ((uint32_t)0x00000002) -#define ADC_REG_3 ((uint32_t)0x00000003) -#define ADC_REG_4 ((uint32_t)0x00000004) -#define ADC_REG_5 ((uint32_t)0x00000005) -#define ADC_REG_6 ((uint32_t)0x00000006) -#define ADC_REG_7 ((uint32_t)0x00000007) -#define ADC_REG_SP ((uint32_t)0x00000008) -#define IS_ADC_REG(param) ((param) <= ADC_REG_SP) - -#define IS_ADC_RESULT_CMP_REG(param) ((param) <= ADC_REG_SP) - -#define ADC_EXT_TRG ((uint32_t)0x00000000) -#define ADC_MATCH_TB_0 ((uint32_t)0x00000020) -#define IS_ADC_HW_TRG_NORMAL(param) (((param) == ADC_EXT_TRG) || \ - ((param) == ADC_MATCH_TB_0)) - -#define ADC_MATCH_TB_1 ((uint32_t)0x00000080) -#define IS_ADC_HW_TRG_TOP(param) (((param) == ADC_EXT_TRG) || \ - ((param) == ADC_MATCH_TB_1)) - -#define IS_ADC_CMP_VALUE(param) ((param) <= (uint16_t)0x03ff) - - typedef enum { - ADC_NO_OVERRUN = 0U, - ADC_OVERRUN = 1U - } ADC_OverrunState; - - typedef enum { - ADC_SCAN_4CH = 0U, - ADC_SCAN_8CH = 1U - } ADC_ChannelScanMode; -#define IS_ADC_CH_SCAN_MODE(param) (((param) == ADC_SCAN_4CH) || \ - ((param) == ADC_SCAN_8CH)) - - typedef enum { - ADC_COMPARISON_SMALLER = 0U, - ADC_COMPARISON_LARGER = 1U - } ADC_ComparisonState; -#define IS_ADC_CMP_INT(param) (((param) == ADC_COMPARISON_SMALLER) || \ - ((param) == ADC_COMPARISON_LARGER)) - - typedef struct { - WorkState ADCResultStored; /*!< ADC result storage flag */ - ADC_OverrunState ADCOverrunState; /*!< ADC overrun flag */ - uint16_t ADCResultValue; /*!< ADC result value */ - } ADC_ResultTypeDef; - -#define ADC_DMA_REQ_NORMAL ((uint8_t)0x00) -#define ADC_DMA_REQ_TOP ((uint8_t)0x01) -#define ADC_DMA_REQ_MONITOR1 ((uint8_t)0x02) -#define ADC_DMA_REQ_MONITOR2 ((uint8_t)0x03) -#define IS_ADC_DMA_REQ(param) ((param) <= ADC_DMA_REQ_MONITOR2) - - typedef union { - uint32_t All; - struct { - uint32_t NormalBusy:1; /*!< bit0, Normal A/D conversion busy flag (MOD0) */ - uint32_t NormalComplete:1; /*!< bit1, Normal AD conversion complete flag (MOD0) */ - uint32_t TopBusy:1; /*!< bit2, Top-priority A/D conversion busy flag (MOD2) */ - uint32_t TopComplete:1; /*!< bit3, Top-priority AD conversion complete flag (MOD2) */ - uint32_t Reserved:28; /*!< bit4 to bit 31, reserved */ - } Bit; - } ADC_State; - -/** @} */ -/* End of group ADC_Exported_Types */ - -/** @defgroup ADC_Exported_FunctionPrototypes - * @{ - */ - void ADC_SWReset(void); - void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output); - void ADC_Start(void); - void ADC_SetScanMode(FunctionalState NewState); - void ADC_SetRepeatMode(FunctionalState NewState); - void ADC_SetINTMode(uint32_t INTMode); - ADC_State ADC_GetConvertState(void); - void ADC_SetInputChannel(uint32_t InputChannel); - void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode); - void ADC_SetIdleMode(FunctionalState NewState); - void ADC_SetVref(FunctionalState NewState); - void ADC_SetInputChannelTop(uint32_t TopInputChannel); - void ADC_StartTopConvert(void); - void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState); - void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison); - void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState); - void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState); - void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState); - ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx); - void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value); - void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState); - -/** @} */ -/* End of group ADC_Exported_FunctionPrototypes */ - -/** @} */ -/* End of group ADC */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* (__TMPM066_ADC_H) */ - -#ifdef __cplusplus -} -#endif -#endif /* __TMPM066_ADC_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h deleted file mode 100644 index 55d4f8b5f5..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_cg.h - * @brief This file provides all the functions prototypes for CG driver. - * @version V2.0.2.1 - * @date 2015/09/29 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_CG_H -#define __TMPM066_CG_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @addtogroup CG - * @{ - */ - -/** @addtogroup CG_Exported_types - * @{ - */ - - typedef enum { - CG_DIVIDE_1 = 0U, - CG_DIVIDE_2 = 1U, - CG_DIVIDE_4 = 2U, - CG_DIVIDE_8 = 3U, - CG_DIVIDE_16 = 4U, - CG_DIVIDE_32 = 5U, - CG_DIVIDE_64 = 6U, - CG_DIVIDE_128 = 7U, - CG_DIVIDE_256 = 8U, - CG_DIVIDE_512 = 9U, - CG_DIVIDE_UNKNOWN = 10U, - CG_DIVIDE_MAX = 16U - } CG_DivideLevel; -#define IS_CG_GEAR_DIVIDE_LEVEL(param) (((param) == CG_DIVIDE_1) || \ - ((param) == CG_DIVIDE_2) || \ - ((param) == CG_DIVIDE_4) || \ - ((param) == CG_DIVIDE_8) || \ - ((param) == CG_DIVIDE_16)) - -#define IS_CG_DIVIDE_FC_LEVEL(param) (((param) == CG_DIVIDE_1) || \ - ((param) == CG_DIVIDE_2) || \ - ((param) == CG_DIVIDE_4) || \ - ((param) == CG_DIVIDE_8) || \ - ((param) == CG_DIVIDE_16) || \ - ((param) == CG_DIVIDE_32) || \ - ((param) == CG_DIVIDE_64)|| \ - ((param) == CG_DIVIDE_128) || \ - ((param) == CG_DIVIDE_256) || \ - ((param) == CG_DIVIDE_512)) - - typedef enum { - CG_FOSC_OSC_INT = 0U, - CG_FOSC_OSC_EXT = 1U, - CG_FOSC_CLKIN_EXT = 2U - } CG_FoscSrc; -#define IS_CG_FOSC_SRC(param) (((param) == CG_FOSC_OSC_EXT) || \ - ((param) == CG_FOSC_OSC_INT) || \ - ((param) == CG_FOSC_CLKIN_EXT)) - -#define IS_CG_FOSC_STATE(param) (((param) == CG_FOSC_OSC_EXT) || \ - ((param) == CG_FOSC_OSC_INT) ) - - typedef enum { - CG_WARM_UP_SRC_OSC_INT_HIGH = 0U, - CG_WARM_UP_SRC_OSC_EXT_HIGH = 1U, - } CG_WarmUpSrc; -#define IS_CG_WARM_UP_SRC(param) (((param) == CG_WARM_UP_SRC_OSC_INT_HIGH) || \ - ((param) == CG_WARM_UP_SRC_OSC_EXT_HIGH)) - - typedef enum { - CG_FC_SRC_FOSC = 0U, - CG_FC_SRC_FPLL = 1U - } CG_FcSrc; -#define IS_CG_FC_SRC(param) (((param) == CG_FC_SRC_FOSC) || \ - ((param) == CG_FC_SRC_FPLL)) - -#define CG_8M_MUL_12_FPLL (0x00C60B00UL<<8U) /* 12 fold, input 8MHz, output 96MHz */ -#define CG_10M_MUL_8_FPLL (0x00C60700UL<<8U) /* 10 fold, input 10MHz, output 80MHz */ -#define CG_12M_MUL_8_FPLL (0x00C60700UL<<8U) /* 12 fold, input 12MHz, output 96MHz */ -#define CG_16M_MUL_6_FPLL (0x00C60500UL<<8U) /* 16 fold, input 16MHz, output 96MHz */ - -#define IS_CG_FPLL_VALUE(param) (((param) == CG_8M_MUL_12_FPLL) || \ - ((param) == CG_10M_MUL_8_FPLL) || \ - ((param) == CG_12M_MUL_8_FPLL) || \ - ((param) == CG_16M_MUL_6_FPLL)) - typedef enum { - CG_STBY_MODE_IDLE = 0U, - CG_STBY_MODE_STOP1 = 1U, - CG_STBY_MODE_UNKNOWN = 2U, - CG_STBY_MODE_MAX = 4U - } CG_STBYMode; -#define IS_CG_STBY_MODE(param) (((param) == CG_STBY_MODE_STOP1) || \ - ((param) == CG_STBY_MODE_IDLE)) -#define CG_FC_PERIPH_PORTH (0x00000001U << 7U) -#define CG_FC_PERIPH_PORTJ (0x00000001U << 8U) -#define CG_FC_PERIPH_TMRB0_3 (0x00000001U << 9U) -#define CG_FC_PERIPH_TMRB4_6 (0x00000001U << 10U) -#define CG_FC_PERIPH_TMR16A (0x00000001U << 11U) -#define CG_FC_PERIPH_I2C0 (0x00000001U << 12U) -#define CG_FC_PERIPH_SIO0 (0x00000001U << 13U) -#define CG_FC_PERIPH_TSPI (0x00000001U << 14U) -#define CG_FC_PERIPH_DMAC (0x00000001U << 15U) -#define CG_FC_PERIPH_ADC (0x00000001U << 16U) -#define CG_FC_PERIPH_USBD (0x00000001U << 17U) -#define CG_FC_PERIPH_TMRD (0x00000001U << 18U) -#define CG_FC_PERIPHA_ALL (0xFFFFFFFFU) -#define IS_CG_FC_PERIPHA(param) ( ((param) >= CG_FC_PERIPH_PORTH) && ((param) <= CG_FC_PERIPH_TMRD )) - -#define CG_FC_PERIPH_TMRB7 (0x00000001U << 28U) -#define CG_FC_PERIPH_SIO1 (0x00000001U << 29U) -#define CG_FC_PERIPH_WDT (0x00000001U << 30U) -#define CG_FC_PERIPH_I2C1 (0x00000001U << 31U) -#define CG_FC_PERIPHB_ALL (0xFFFFFFFFU) -#define IS_CG_FC_PERIPHB(param) (((param) >= CG_FC_PERIPH_TMRB7)) - -#define CG_FPLL_PERIPH_TMRD (0x00000001U << 5U) -#define CG_EHCLKSEL_8_24_48MHZ (0x00000001U << 4U) -#define CG_USBSEL_PLL_CLOCKIN (0x00000001U << 1U) -#define CG_USBENA_USB (0x00000001U) -#define CG_FPLL_OPTIONAL_ALL (0x0FFFFFFFU) -#define IS_CG_FPLL_OPTIONAL(param) (((param) > 0U) && ((param) <= CG_FPLL_OPTIONAL_ALL)) - -/** @} */ -/* End of group CG_Exported_types */ - -/** @defgroup CG_Exported_FunctionPrototypes - * @{ - */ - void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc); - CG_DivideLevel CG_GetFgearLevel(void); - Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc); - CG_DivideLevel CG_GetPhiT0Level(void); - void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time); - void CG_StartWarmUp(void); - WorkState CG_GetWarmUpState(void); - Result CG_SetFPLLValue(uint32_t NewValue); - uint32_t CG_GetFPLLValue(void); - Result CG_SetPLL(FunctionalState NewState); - FunctionalState CG_GetPLLState(void); - void CG_SetFoscSrc(CG_FoscSrc Source); - CG_FoscSrc CG_GetFoscSrc(void); - void CG_SetSTBYMode(CG_STBYMode Mode); - CG_STBYMode CG_GetSTBYMode(void); - void CG_SetFcSrc(CG_FcSrc Source); - CG_FcSrc CG_GetFcSrc(void); - void CG_SetProtectCtrl(FunctionalState NewState); - void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState); - void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState); - void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState); - void CG_SetADCClkSupply(FunctionalState NewState); - -/** @} */ -/* End of group CG_Exported_FunctionPrototype */ - -/** @} */ -/* End of group CG */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TMPM066_CG_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h deleted file mode 100644 index 6d0a86fa49..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h +++ /dev/null @@ -1,229 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_gpio.h - * @brief This file provides all the functions prototypes for GPIO driver. - * @version V2.0.2.1 - * @date 2015/09/29 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_GPIO_H -#define __TMPM066_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -#if defined(__TMPM066_GPIO_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ -/** @addtogroup GPIO - * @{ - */ -/** @addtogroup GPIO_Parameter_Definition - * @{ - */ - - -/** @brief :The maximum number of the Function Register - * Note for porting: - * If functiong register 2 is the maximum number in - * all the GPIO port,then define FRMAX (2U) - */ -#define FRMAX (2U) /* the max number of Port I/O function register is 2 */ - - -/** @brief: define for function register - * Note for porting: - * If the maximum number of the function Register is 2, - * then you need to define 2 GPIO_FUNC_REG_x , - * the value should be increased from 0 to 1 - */ -#define GPIO_FUNC_REG_1 ((uint8_t)0x00) -#define GPIO_FUNC_REG_2 ((uint8_t)0x01) - -/** @brief :The GPIO_Port enum - * Note for porting: - * the port value order from low to high with '1' step - * and begin with "0". - */ - typedef enum { - GPIO_PA = 0U, - GPIO_PB = 1U, - GPIO_PC = 2U, - GPIO_PD = 3U, - GPIO_PE = 4U, - GPIO_PF = 5U, - GPIO_PG = 6U, - GPIO_PH = 7U, - GPIO_PJ = 8U - } GPIO_Port; - -#define IS_GPIO_PORT(param) ((param) <= GPIO_PJ) /*parameter checking for port number */ - -#define IS_GPIO_PORT_INPUT_VOLTAGE(param) (((param) == GPIO_PC) || \ - ((param) == GPIO_PD) || \ - ((param) == GPIO_PG)) - -#define RESER (8U-(FRMAX)) - - typedef struct { - __IO uint32_t DATA; - __IO uint32_t CR; - __IO uint32_t FR[FRMAX]; - uint32_t RESERVED0[RESER]; - __IO uint32_t OD; - __IO uint32_t PUP; - __IO uint32_t PDN; - __IO uint32_t SEL; - __IO uint32_t IE; - } TSB_Port_TypeDef; - - typedef struct { - uint8_t PinDATA; - uint8_t PinCR; - uint8_t PinFR[FRMAX]; - uint8_t PinOD; - uint8_t PinPUP; - uint8_t PinPDN; - uint8_t PinSEL; - uint8_t PinIE; - } GPIO_RegTypeDef; - - typedef struct { - uint8_t IOMode; /* Set the port input or output mode */ - uint8_t PullUp; /* Enable or disable Pullup function */ - uint8_t OpenDrain; /* Enable or disable open drain function */ - uint8_t PullDown; /* Enable or disable Pulldown function */ - uint8_t InputVoltage; /* Enable or disable Input Voltage function */ - } GPIO_InitTypeDef; - -#define GPIO_INPUT_MODE ((uint8_t)0x00) -#define GPIO_OUTPUT_MODE ((uint8_t)0x01) -#define GPIO_IO_MODE_NONE ((uint8_t)0x02) -#define IS_GPIO_IO_MODE_STATE(param) (((param) == GPIO_INPUT_MODE) || \ - ((param) == GPIO_OUTPUT_MODE) || \ - ((param) == GPIO_IO_MODE_NONE)) - -#define GPIO_PULLUP_DISABLE ((uint8_t)0x00) -#define GPIO_PULLUP_ENABLE ((uint8_t)0x01) -#define GPIO_PULLUP_NONE ((uint8_t)0x02) -#define IS_GPIO_PULLUP_STATE(param) (((param) == GPIO_PULLUP_ENABLE) || \ - ((param) == GPIO_PULLUP_DISABLE) || \ - ((param) == GPIO_PULLUP_NONE)) - -#define GPIO_PULLDOWN_DISABLE ((uint8_t)0x00) -#define GPIO_PULLDOWN_ENABLE ((uint8_t)0x01) -#define GPIO_PULLDOWN_NONE ((uint8_t)0x02) -#define IS_GPIO_PULLDOWN_STATE(param) (((param) == GPIO_PULLDOWN_ENABLE) || \ - ((param) == GPIO_PULLDOWN_DISABLE) || \ - ((param) == GPIO_PULLDOWN_NONE)) - -#define GPIO_OPEN_DRAIN_DISABLE ((uint8_t)0x00) -#define GPIO_OPEN_DRAIN_ENABLE ((uint8_t)0x01) -#define GPIO_OPEN_DRAIN_NONE ((uint8_t)0x02) -#define IS_GPIO_OPEN_DRAIN_STATE(param) (((param) == GPIO_OPEN_DRAIN_ENABLE) || \ - ((param) == GPIO_OPEN_DRAIN_DISABLE) || \ - ((param) == GPIO_OPEN_DRAIN_NONE)) - -#define GPIO_INPUT_VOLTAGE_3V ((uint8_t)0x00) -#define GPIO_INPUT_VOLTAGE_1V8 ((uint8_t)0x01) -#define GPIO_INPUT_VOLTAGE_NONE ((uint8_t)0x02) -#define IS_GPIO_INPUT_VOLTAGE_STATE(param) (((param) == GPIO_INPUT_VOLTAGE_3V) || \ - ((param) == GPIO_INPUT_VOLTAGE_1V8) || \ - ((param) == GPIO_INPUT_VOLTAGE_NONE)) - -#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) -#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) - -#define IS_GPIO_BIT_VALUE(BitValue) (((BitValue) == GPIO_BIT_VALUE_1)|| \ - ((BitValue) == GPIO_BIT_VALUE_0)) - -#define GPIO_BIT_0 ((uint8_t)0x01) -#define GPIO_BIT_1 ((uint8_t)0x02) -#define GPIO_BIT_2 ((uint8_t)0x04) -#define GPIO_BIT_3 ((uint8_t)0x08) -#define GPIO_BIT_4 ((uint8_t)0x10) -#define GPIO_BIT_5 ((uint8_t)0x20) -#define GPIO_BIT_6 ((uint8_t)0x40) -#define GPIO_BIT_7 ((uint8_t)0x80) -#define GPIO_BIT_ALL ((uint8_t)0xFF) - -#define IS_GPIO_WRITE(GPIO_x) (GPIO_SFRs[(GPIO_x)].PinCR) - -#define IS_GPIO_BIT_DATA(GPIO_x,Bit_x) ((((GPIO_SFRs[(GPIO_x)].PinDATA) & (Bit_x))&&\ - (!((uint8_t)(~(GPIO_SFRs[(GPIO_x)].PinDATA))&(Bit_x))))) - -#define IS_GPIO_BIT_OUT(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinCR &(Bit_x))&&\ - (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinCR)&(Bit_x))))) - -#define IS_GPIO_BIT_IN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinIE &(Bit_x))&&\ - (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinIE)&(Bit_x))))) - -#define IS_GPIO_BIT_PUP(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPUP &(Bit_x))&&\ - (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPUP)&(Bit_x))))) - -#define IS_GPIO_BIT_PDN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPDN &(Bit_x))&&\ - (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPDN)&(Bit_x))))) - -#define IS_GPIO_BIT_OD(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinOD &(Bit_x))&&\ - (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinOD)&(Bit_x))))) - -#define IS_GPIO_BIT_SEL(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinSEL &(Bit_x))&&\ - (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinSEL)&(Bit_x))))) - -#define IS_GPIO_BIT_FR(GPIO_x,FuncReg_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)]&(Bit_x))&&\ - (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)])&(Bit_x))))) - - -#define IS_GPIO_FUNCTION_REG(param) ((param) < (FRMAX)) - -#define IS_GPIO_BIT(param) (((param) == GPIO_BIT_0)|| \ - ((param) == GPIO_BIT_1)|| \ - ((param) == GPIO_BIT_2)|| \ - ((param) == GPIO_BIT_3)|| \ - ((param) == GPIO_BIT_4)|| \ - ((param) == GPIO_BIT_5)|| \ - ((param) == GPIO_BIT_6)|| \ - ((param) == GPIO_BIT_7)) -/** @} */ -/* End of group GPIO_Bit_Define */ - -/** @defgroup GPIO_Exported_FunctionPrototypes - * @{ - */ - uint8_t GPIO_ReadData(GPIO_Port GPIO_x); - uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x); - void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data); - void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue); - void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct); - void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x); - void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x); - void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); - void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); - void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); - void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); - void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); - void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue); - void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x); - void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x); -/** @} */ -/* End of group GPIO_Exported_FunctionPrototypes */ -/** @} */ -/* End of group GPIO */ -/** @} */ -/* End of group TX00_Periph_Driver */ -#endif /* defined(__TMPM066_GPIO_H) */ - -#ifdef __cplusplus -} -#endif -#endif /* __TMPM066_GPIO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h deleted file mode 100644 index f8b73095ac..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_i2c.h - * @brief This file provides all the functions prototypes for I2C driver. - * @version V2.0.2.1 - * @date 2015/09/10 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_I2C_H -#define __TMPM066_I2C_H - - -#ifdef __cplusplus -extern "C" { -#endif /*__cplusplus*/ - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -#if defined(__TMPM066_I2C_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - typedef struct { - uint32_t I2CSelfAddr; /*!< Specify self-address of the I2C channel in I2C mode */ - uint32_t I2CDataLen; /*!< Specify data length of the I2C channel in I2C mode */ - FunctionalState I2CACKState; /*!< Enable or disable the generation of ACK clock */ - uint32_t I2CClkDiv; /*!< Select the division of the prescaler clock for generating the serial clock */ - uint32_t PrescalerClkDiv; /* Select the division of fsys for generating the fprsck */ - } I2C_InitTypeDef; - - typedef union { - uint32_t All; - struct { - uint32_t LastRxBit:1; - uint32_t GeneralCall:1; - uint32_t SlaveAddrMatch:1; - uint32_t ArbitrationLost:1; - uint32_t INTReq:1; - uint32_t BusState:1; - uint32_t TRx:1; - uint32_t MasterSlave:1; - } Bit; - } I2C_State; - -#define I2C_CHANNEL_NUMBER 2U -#define IS_I2C_PERIPH(param) (((param) == TSB_I2C0) || \ - ((param) == TSB_I2C1)) - - - - -#define I2C_DATA_LEN_8 ((uint32_t)0x00000000) -#define I2C_DATA_LEN_1 ((uint32_t)0x00000001) -#define I2C_DATA_LEN_2 ((uint32_t)0x00000002) -#define I2C_DATA_LEN_3 ((uint32_t)0x00000003) -#define I2C_DATA_LEN_4 ((uint32_t)0x00000004) -#define I2C_DATA_LEN_5 ((uint32_t)0x00000005) -#define I2C_DATA_LEN_6 ((uint32_t)0x00000006) -#define I2C_DATA_LEN_7 ((uint32_t)0x00000007) - -#define I2C_SCK_CLK_DIV_20 ((uint32_t)0x00000000) -#define I2C_SCK_CLK_DIV_24 ((uint32_t)0x00000001) -#define I2C_SCK_CLK_DIV_32 ((uint32_t)0x00000002) -#define I2C_SCK_CLK_DIV_48 ((uint32_t)0x00000003) -#define I2C_SCK_CLK_DIV_80 ((uint32_t)0x00000004) -#define I2C_SCK_CLK_DIV_144 ((uint32_t)0x00000005) -#define I2C_SCK_CLK_DIV_272 ((uint32_t)0x00000006) -#define I2C_SCK_CLK_DIV_528 ((uint32_t)0x00000007) -#define IS_I2C_SCK_CLK_DIV(param) (((param) == I2C_SCK_CLK_DIV_20) || \ - ((param) == I2C_SCK_CLK_DIV_24) || \ - ((param) == I2C_SCK_CLK_DIV_32) || \ - ((param) == I2C_SCK_CLK_DIV_48) || \ - ((param) == I2C_SCK_CLK_DIV_80) || \ - ((param) == I2C_SCK_CLK_DIV_144) || \ - ((param) == I2C_SCK_CLK_DIV_272) || \ - ((param) == I2C_SCK_CLK_DIV_528)) - -#define I2C_PRESCALER_DIV_1 ((uint32_t)0x00000001) -#define I2C_PRESCALER_DIV_2 ((uint32_t)0x00000002) -#define I2C_PRESCALER_DIV_3 ((uint32_t)0x00000003) -#define I2C_PRESCALER_DIV_4 ((uint32_t)0x00000004) -#define I2C_PRESCALER_DIV_5 ((uint32_t)0x00000005) -#define I2C_PRESCALER_DIV_6 ((uint32_t)0x00000006) -#define I2C_PRESCALER_DIV_7 ((uint32_t)0x00000007) -#define I2C_PRESCALER_DIV_8 ((uint32_t)0x00000008) -#define I2C_PRESCALER_DIV_9 ((uint32_t)0x00000009) -#define I2C_PRESCALER_DIV_10 ((uint32_t)0x0000000A) -#define I2C_PRESCALER_DIV_11 ((uint32_t)0x0000000B) -#define I2C_PRESCALER_DIV_12 ((uint32_t)0x0000000C) -#define I2C_PRESCALER_DIV_13 ((uint32_t)0x0000000D) -#define I2C_PRESCALER_DIV_14 ((uint32_t)0x0000000E) -#define I2C_PRESCALER_DIV_15 ((uint32_t)0x0000000F) -#define I2C_PRESCALER_DIV_16 ((uint32_t)0x00000010) -#define I2C_PRESCALER_DIV_17 ((uint32_t)0x00000011) -#define I2C_PRESCALER_DIV_18 ((uint32_t)0x00000012) -#define I2C_PRESCALER_DIV_19 ((uint32_t)0x00000013) -#define I2C_PRESCALER_DIV_20 ((uint32_t)0x00000014) -#define I2C_PRESCALER_DIV_21 ((uint32_t)0x00000015) -#define I2C_PRESCALER_DIV_22 ((uint32_t)0x00000016) -#define I2C_PRESCALER_DIV_23 ((uint32_t)0x00000017) -#define I2C_PRESCALER_DIV_24 ((uint32_t)0x00000018) -#define I2C_PRESCALER_DIV_25 ((uint32_t)0x00000019) -#define I2C_PRESCALER_DIV_26 ((uint32_t)0x0000001A) -#define I2C_PRESCALER_DIV_27 ((uint32_t)0x0000001B) -#define I2C_PRESCALER_DIV_28 ((uint32_t)0x0000001C) -#define I2C_PRESCALER_DIV_29 ((uint32_t)0x0000001D) -#define I2C_PRESCALER_DIV_30 ((uint32_t)0x0000001E) -#define I2C_PRESCALER_DIV_31 ((uint32_t)0x0000001F) -#define I2C_PRESCALER_DIV_32 ((uint32_t)0x00000020) - -/** @} */ -/* End of group I2C_Exported_Types */ - -/** @defgroup I2C_Exported_Macros - * @{ - */ -#define IS_PRESCALER_CLK_VALID(param1, param2) (((param1) >= I2C_PRESCALER_DIV_1) && \ - ((param1) <= I2C_PRESCALER_DIV_32) && \ - (((param2) / (param1)) > 666666U) && \ - (((param2) / (param1)) < 20000000U)) - -#define IS_I2C_DATA(param) ((param) <= (uint32_t)0x000000FF) - -#define IS_I2C_BIT_NUM(param) ((param) <= (uint32_t)0x00000007) - -#define IS_I2C_ADDR(param) (((param) < (uint32_t)0x000000FF) && \ - (!((param) & (uint32_t)0x00000001))) - -/** @} */ -/* End of group I2C_Exported_Macros */ - -/** @defgroup I2C_Exported_FunctionPrototypes - * @{ - */ - - void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct); - void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum); - void I2C_SWReset(TSB_I2C_TypeDef * I2Cx); - void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx); - void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx); - void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx); - I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx); - void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data); - uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx); - void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx); - void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock); - - void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - - FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx); - FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx); - FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx); - FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx); - - void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx); - void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx); - void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx); - void I2C_ClearINTI2COutput(TSB_I2C_TypeDef * I2Cx); - - void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx); - void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); - WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx); - - -/** @} */ -/* End of group I2C_Exported_FunctionPrototypes */ - -/** @} */ -/* End of group I2C */ - -/** @} */ -/* End of group TX00_Periph_Driver */ -#endif /* defined(__TMPM066_I2C_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TMPM066_I2C_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h deleted file mode 100644 index 15512150b3..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_intifao.h - * @brief This file provides all the functions prototypes for INTIFAO driver. - * @version V2.0.2.1 - * @date 2015/10/19 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_INTIFAO_H -#define __TMPM066_INTIFAO_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @addtogroup INTIFAO - * @{ - */ - -/** @addtogroup INTIFAO_Exported_types - * @{ - */ - typedef struct { - uint32_t All; - } INTIFAO_IntFlag1Factor; - - typedef enum { - INTIFAO_INT_SRC_0 = 0U, - INTIFAO_INT_SRC_1 = 1U, - INTIFAO_INT_SRC_2 = 2U, - INTIFAO_INT_SRC_3 = 3U, - INTIFAO_INT_SRC_4 = 4U, - INTIFAO_INT_SRC_5 = 5U, - INTIFAO_INT_SRC_I2CS = 6U, - INTIFAO_INT_SRC_USBWKUP = 7U - } INTIFAO_INTSrc; - -#define IS_INTIFAO_INT_SRC(param) (((param) == INTIFAO_INT_SRC_0) || \ - ((param) == INTIFAO_INT_SRC_1) || \ - ((param) == INTIFAO_INT_SRC_2) || \ - ((param) == INTIFAO_INT_SRC_3) || \ - ((param) == INTIFAO_INT_SRC_4) || \ - ((param) == INTIFAO_INT_SRC_5) || \ - ((param) == INTIFAO_INT_SRC_I2CS) || \ - ((param) == INTIFAO_INT_SRC_USBWKUP)) - - typedef enum { - INTIFAO_INT_ACTIVE_STATE_L = 0x0U, - INTIFAO_INT_ACTIVE_STATE_H = 0x1U, - INTIFAO_INT_ACTIVE_STATE_FALLING = 0x2U, - INTIFAO_INT_ACTIVE_STATE_RISING = 0x3U, - INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES = 0x4U, - INTIFAO_INT_ACTIVE_STATE_INVALID = 0x5U - } INTIFAO_INTActiveState; -#define IS_INTIFAO_INT_ACTIVE_STATE(param) (((param) == INTIFAO_INT_ACTIVE_STATE_L) || \ - ((param) == INTIFAO_INT_ACTIVE_STATE_H) || \ - ((param) == INTIFAO_INT_ACTIVE_STATE_FALLING) || \ - ((param) == INTIFAO_INT_ACTIVE_STATE_RISING) || \ - ((param) == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) - -#define IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(param) ((param) == INTIFAO_INT_ACTIVE_STATE_RISING) - -/** @} */ -/* End of group INTIFAO_Exported_types */ - -/** @defgroup INTIFAO_Exported_FunctionPrototypes - * @{ - */ - void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource, - INTIFAO_INTActiveState ActiveState, FunctionalState NewState); - INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource); - void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource); - - INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void); - -/** @} */ -/* End of group INTIFAO_Exported_FunctionPrototype */ - -/** @} */ -/* End of group INTIFAO */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TMPM066_INTIFAO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h deleted file mode 100644 index 456a51f54e..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h +++ /dev/null @@ -1,228 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_intifsd.h - * @brief This file provides all the functions prototypes for INTIFSD driver. - * @version V2.0.2.2 - * @date 2016/02/09 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_INTIFSD_H -#define __TMPM066_INTIFSD_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @addtogroup INTIFSD - * @{ - */ - -/** @addtogroup INTIFSD_Exported_types - * @{ - */ - typedef union { - uint32_t All; - struct { - uint32_t Reserved1:16; - uint32_t DetectLowVoltage:1; - uint32_t DetectOverVoltage:1; - uint32_t WDT:1; - uint32_t Reserved2:13; - } Bit; - } INTIFSD_NMIFactor; - - typedef struct { - uint32_t All; - } INTIFSD_IntFlag3Factor; - - typedef struct { - uint32_t All; - } INTIFSD_IntFlag4Factor; - - typedef struct { - uint32_t All; - } INTIFSD_IntFlag5Factor; - - typedef enum { - INTIFSD_INT_SRC_LVD_PSFD = 0U, - INTIFSD_INT_SRC_LVD_PRD = 1U, - INTIFSD_INT_SRC_WDT = 2U, - INTIFSD_INT_SRC_DMAC_0 = 3U, - INTIFSD_INT_SRC_DMAC_1 = 4U, - INTIFSD_INT_SRC_DMAC_2 = 5U, - INTIFSD_INT_SRC_DMAC_3 = 6U, - INTIFSD_INT_SRC_DMAC_4 = 7U, - INTIFSD_INT_SRC_DMAC_5 = 8U, - INTIFSD_INT_SRC_DMAC_6 = 9U, - INTIFSD_INT_SRC_DMAC_7 = 10U, - INTIFSD_INT_SRC_DMAC_8 = 11U, - INTIFSD_INT_SRC_DMAC_9 = 12U, - INTIFSD_INT_SRC_DMAC_10 = 13U, - INTIFSD_INT_SRC_DMAC_11 = 14U, - INTIFSD_INT_SRC_DMAC_12 = 15U, - INTIFSD_INT_SRC_DMAC_13 = 16U, - INTIFSD_INT_SRC_DMAC_14 = 17U, - INTIFSD_INT_SRC_DMAC_15 = 18U, - INTIFSD_INT_SRC_DMAC_16 = 19U, - INTIFSD_INT_SRC_DMAC_17 = 20U, - INTIFSD_INT_SRC_DMAC_18 = 21U, - INTIFSD_INT_SRC_DMAC_19 = 22U, - INTIFSD_INT_SRC_DMAC_20 = 23U, - INTIFSD_INT_SRC_DMAC_21 = 24U, - INTIFSD_INT_SRC_DMAC_22 = 25U, - INTIFSD_INT_SRC_DMAC_23 = 26U, - INTIFSD_INT_SRC_DMAC_24 = 27U, - INTIFSD_INT_SRC_DMAC_25 = 28U, - INTIFSD_INT_SRC_DMAC_26 = 29U, - INTIFSD_INT_SRC_DMAC_27 = 30U, - INTIFSD_INT_SRC_DMAC_28 = 31U, - INTIFSD_INT_SRC_DMAC_29 = 32U, - INTIFSD_INT_SRC_DMAC_30 = 33U, - INTIFSD_INT_SRC_DMAC_31 = 34U, - INTIFSD_INT_SRC_DMAC_ERR = 35U, - INTIFSD_INT_SRC_TMRB_0_MDOVF = 36U, - INTIFSD_INT_SRC_TMRB_0_CAP0 = 37U, - INTIFSD_INT_SRC_TMRB_0_CAP1 = 38U, - INTIFSD_INT_SRC_TMRB_1_MDOVF = 39U, - INTIFSD_INT_SRC_TMRB_1_CAP0 = 40U, - INTIFSD_INT_SRC_TMRB_1_CAP1 = 41U, - INTIFSD_INT_SRC_TMRB_2_MDOVF = 42U, - INTIFSD_INT_SRC_TMRB_2_CAP0 = 43U, - INTIFSD_INT_SRC_TMRB_2_CAP1 = 44U, - INTIFSD_INT_SRC_TMRB_3_MDOVF = 45U, - INTIFSD_INT_SRC_TMRB_3_CAP0 = 46U, - INTIFSD_INT_SRC_TMRB_3_CAP1 = 47U, - INTIFSD_INT_SRC_TMRB_4_MDOVF = 48U, - INTIFSD_INT_SRC_TMRB_4_CAP0 = 49U, - INTIFSD_INT_SRC_TMRB_4_CAP1 = 50U, - INTIFSD_INT_SRC_TMRB_5_MDOVF = 51U, - INTIFSD_INT_SRC_TMRB_5_CAP0 = 52U, - INTIFSD_INT_SRC_TMRB_5_CAP1 = 53U, - INTIFSD_INT_SRC_TMRB_6_MDOVF = 54U, - INTIFSD_INT_SRC_TMRB_6_CAP0 = 55U, - INTIFSD_INT_SRC_TMRB_6_CAP1 = 56U, - INTIFSD_INT_SRC_TMRB_7_MDOVF = 57U, - INTIFSD_INT_SRC_TMRB_7_CAP0 = 58U, - INTIFSD_INT_SRC_TMRB_7_CAP1 = 59U, - INTIFSD_INT_SRC_TMRD_00 = 60U, - INTIFSD_INT_SRC_TMRD_01 = 61U, - INTIFSD_INT_SRC_TMRD_02 = 62U, - INTIFSD_INT_SRC_TMRD_03 = 63U, - INTIFSD_INT_SRC_TMRD_04 = 64U, - INTIFSD_INT_SRC_TMRD_10 = 65U, - INTIFSD_INT_SRC_TMRD_11 = 66U, - INTIFSD_INT_SRC_TMRD_12 = 67U, - INTIFSD_INT_SRC_TMRD_13 = 68U, - INTIFSD_INT_SRC_TMRD_14 = 69U - } INTIFSD_INTSrc; - -#define IS_INTIFSD_INT_SRC(param) (((param) == INTIFSD_INT_SRC_LVD_PSFD) || \ - ((param) == INTIFSD_INT_SRC_LVD_PRD) || \ - ((param) == INTIFSD_INT_SRC_WDT) || \ - ((param) == INTIFSD_INT_SRC_DMAC_0) || \ - ((param) == INTIFSD_INT_SRC_DMAC_1) || \ - ((param) == INTIFSD_INT_SRC_DMAC_2) || \ - ((param) == INTIFSD_INT_SRC_DMAC_3) || \ - ((param) == INTIFSD_INT_SRC_DMAC_4) || \ - ((param) == INTIFSD_INT_SRC_DMAC_5) || \ - ((param) == INTIFSD_INT_SRC_DMAC_6) || \ - ((param) == INTIFSD_INT_SRC_DMAC_7) || \ - ((param) == INTIFSD_INT_SRC_DMAC_8) || \ - ((param) == INTIFSD_INT_SRC_DMAC_9) || \ - ((param) == INTIFSD_INT_SRC_DMAC_10) || \ - ((param) == INTIFSD_INT_SRC_DMAC_11) || \ - ((param) == INTIFSD_INT_SRC_DMAC_12) || \ - ((param) == INTIFSD_INT_SRC_DMAC_13) || \ - ((param) == INTIFSD_INT_SRC_DMAC_14) || \ - ((param) == INTIFSD_INT_SRC_DMAC_15) || \ - ((param) == INTIFSD_INT_SRC_DMAC_16) || \ - ((param) == INTIFSD_INT_SRC_DMAC_17) || \ - ((param) == INTIFSD_INT_SRC_DMAC_18) || \ - ((param) == INTIFSD_INT_SRC_DMAC_19) || \ - ((param) == INTIFSD_INT_SRC_DMAC_20) || \ - ((param) == INTIFSD_INT_SRC_DMAC_21) || \ - ((param) == INTIFSD_INT_SRC_DMAC_22) || \ - ((param) == INTIFSD_INT_SRC_DMAC_23) || \ - ((param) == INTIFSD_INT_SRC_DMAC_24) || \ - ((param) == INTIFSD_INT_SRC_DMAC_25) || \ - ((param) == INTIFSD_INT_SRC_DMAC_26) || \ - ((param) == INTIFSD_INT_SRC_DMAC_27) || \ - ((param) == INTIFSD_INT_SRC_DMAC_28) || \ - ((param) == INTIFSD_INT_SRC_DMAC_29) || \ - ((param) == INTIFSD_INT_SRC_DMAC_30) || \ - ((param) == INTIFSD_INT_SRC_DMAC_31) || \ - ((param) == INTIFSD_INT_SRC_DMAC_ERR) || \ - ((param) == INTIFSD_INT_SRC_TMRB_0_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_0_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_0_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRB_1_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_1_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_1_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRB_2_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_2_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_2_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRB_3_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_3_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_3_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRB_4_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_4_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_4_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRB_5_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_5_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_5_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRB_6_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_6_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_6_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRB_7_MDOVF) || \ - ((param) == INTIFSD_INT_SRC_TMRB_7_CAP0) || \ - ((param) == INTIFSD_INT_SRC_TMRB_7_CAP1) || \ - ((param) == INTIFSD_INT_SRC_TMRD_00) || \ - ((param) == INTIFSD_INT_SRC_TMRD_01) || \ - ((param) == INTIFSD_INT_SRC_TMRD_02) || \ - ((param) == INTIFSD_INT_SRC_TMRD_03) || \ - ((param) == INTIFSD_INT_SRC_TMRD_04) || \ - ((param) == INTIFSD_INT_SRC_TMRD_10) || \ - ((param) == INTIFSD_INT_SRC_TMRD_11) || \ - ((param) == INTIFSD_INT_SRC_TMRD_12) || \ - ((param) == INTIFSD_INT_SRC_TMRD_13) || \ - ((param) == INTIFSD_INT_SRC_TMRD_14)) - -/** @} */ -/* End of group INTIFSD_Exported_types */ - -/** @defgroup INTIFSD_Exported_FunctionPrototypes - * @{ - */ - INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void); - - void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource); - - INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void); - INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void); - INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void); - -/** @} */ -/* End of group INTIFSD_Exported_FunctionPrototype */ - -/** @} */ -/* End of group INTIFSD */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TMPM066_INTIFSD_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h deleted file mode 100644 index 16d84c5375..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_tmr16a.h - * @brief This file provides all the functions prototypes for TMR16A driver. - * @version V2.0.2.1 - * @date 2015/10/09 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_TMR16A_H -#define __TMPM066_TMR16A_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -#if defined(__TMPM066_TMR16A_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @addtogroup TMR16A - * @{ - */ - -/** @defgroup TMR16A_Exported_Types - * @{ - */ - -/** - * @brief TMR16A Flip-flop Structure definition - */ - - typedef struct { - uint32_t TMR16AFlipflopCtrl; /*!< Select TMR16A flip-flop output level */ - uint32_t TMR16AFlipflopReverseTrg; /*!< Specify TMR16A flip-flop reverse trigger */ - } TMR16A_FFOutputTypeDef; - -/** @} */ -/* End of group TMR16A_Exported_Types */ - -/** @defgroup TMR16A_Exported_Constants - * @{ - */ -#define IS_TMR16A_ALL_PERIPH(param) (((param) == TSB_T16A0) || \ - ((param) == TSB_T16A1)) - - - -#define TMR16A_SYSCK ((uint32_t)0x00000000) -#define TMR16A_PRCK ((uint32_t)0x00000001) -#define IS_TMR16A_SRCCLK(param) (((param) == TMR16A_SYSCK) || ((param) == TMR16A_PRCK)) - -#define TMR16A_RUN ((uint32_t)0x00000001) -#define TMR16A_STOP ((uint32_t)0x00000000) -#define IS_TMR16A_CMD(param) (((param) == TMR16A_RUN) || ((param) == TMR16A_STOP)) - -#define TMR16A_RUNNING_IN_CORE_HALT ((uint8_t)0x00) -#define TMR16A_STOP_IN_CORE_HALT ((uint8_t)0x02) -#define IS_TMR16A_CLK_IN_CORE_HALT(param) (((param) == TMR16A_RUNNING_IN_CORE_HALT) || \ - ((param) == TMR16A_STOP_IN_CORE_HALT)) - -#define TMR16A_FLIPFLOP_INVERT ((uint32_t)0x00000000) -#define TMR16A_FLIPFLOP_SET ((uint32_t)0x00000001) -#define TMR16A_FLIPFLOP_CLEAR ((uint32_t)0x00000002) -#define IS_TMR16A_FLIPFLOP_CTRL(param) (((param) == TMR16A_FLIPFLOP_INVERT) || \ - ((param) == TMR16A_FLIPFLOP_SET) || \ - ((param) == TMR16A_FLIPFLOP_CLEAR)) - -#define TMR16A_DISABLE_FLIPFLOP ((uint32_t)0x00000000) -#define TMR16A_FLIPFLOP_MATCH_CYCLE ((uint32_t)0x00000080) -#define IS_TMR16A_FLIPFLOP_TRG(param) (((param) == TMR16A_DISABLE_FLIPFLOP) || \ - ((param) == TMR16A_FLIPFLOP_MATCH_CYCLE)) - -#define IS_TMR16A_VALUE(param) ((param) <= 0x0000FFFFU) -#define IS_TMR16A_VALID_DUTY(param1, param2) ((param1) <= (param2)) - -/* End of group TMR16A_Exported_Constants */ -/** @defgroup TMR16A_Exported_FunctionPrototypes - * @{ - */ - void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState); - void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd); - void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk); - void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct); - void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle); - uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax); -/** @} */ -/* End of group TMR16A_Exported_FunctionPrototypes */ - -/** @} */ -/* End of group TMR16A */ - -/** @} */ -/* End of group TX00_Periph_Driver */ -#endif /* defined(__TMPM066_TMR16A_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TMPM066_TMR16A_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h deleted file mode 100644 index 5b1b9bdd12..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h +++ /dev/null @@ -1,259 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_tmrb.h - * @brief This file provides all the functions prototypes for TMRB driver. - * @version V2.0.2.1 - * @date 2015/10/09 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_TMRB_H -#define __TMPM066_TMRB_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -#if defined(__TMPM066_TMRB_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ -/** @addtogroup TMRB - * @{ - */ -/** @defgroup TMRB_Exported_Types - * @{ - */ -/** - * @brief TMRB Init Structure definition - */ - typedef struct { - uint32_t Mode; /*!< Select TMRB mode between internal interval - timer mode and external event counter */ - uint32_t ClkDiv; /*!< Select the division for TMRB source clock */ - uint32_t TrailingTiming; /*!< Specify the trailingtiming value to be written - into TBnRG1 */ - uint32_t UpCntCtrl; /*!< Select up-counter work mode between - freerun and auto-reload */ - uint32_t LeadingTiming; /*!< Specify the leadingtiming value to be written - into TBnRG0 */ - } TMRB_InitTypeDef; - -/** - * @brief TMRB Flip-flop Structure definition - */ - - typedef struct { - uint32_t FlipflopCtrl; /*!< Select TMRB flip-flop output level */ - uint32_t FlipflopReverseTrg; /*!< Specify TMRB flip-flop reverse trigger */ - } TMRB_FFOutputTypeDef; - -/** - * @brief TMRB Interrupt factor Union definition - */ - typedef union { - uint32_t All; - struct { - uint32_t MatchLeadingTiming:1; - uint32_t MatchTrailingTiming:1; - uint32_t OverFlow:1; - uint32_t Reserverd:29; - } Bit; - } TMRB_INTFactor; - -/** - * @brief TMRB Interrupt masked Union definition - */ - typedef union { - uint32_t All; - struct { - uint32_t MatchLeadingTimingMask:1; - uint32_t MatchTrailingTimingMask:1; - uint32_t OverFlowMask:1; - uint32_t Reserverd:29; - } Bit; - } TMRB_INTMask; - -/** @} */ -/* End of group TMRB_Exported_Types */ - -/** @defgroup TMRB_Exported_Constants - * @{ - */ -#define IS_TMRB_ALL_PERIPH(param) (((param) == TSB_TB0) || \ - ((param) == TSB_TB1) || \ - ((param) == TSB_TB2) || \ - ((param) == TSB_TB3) || \ - ((param) == TSB_TB4) || \ - ((param) == TSB_TB5) || \ - ((param) == TSB_TB6) || \ - ((param) == TSB_TB7)) - -#define IS_TMRB_SYNC_PERIPH(param) (((param) == TSB_TB1) || \ - ((param) == TSB_TB2) || \ - ((param) == TSB_TB3) || \ - ((param) == TSB_TB5) || \ - ((param) == TSB_TB6) || \ - ((param) == TSB_TB7)) - -#define IS_TMRB_CAP_PERIPH(param) (((param) == TSB_TB0) || \ - ((param) == TSB_TB1) || \ - ((param) == TSB_TB2) || \ - ((param) == TSB_TB3) || \ - ((param) == TSB_TB4) || \ - ((param) == TSB_TB5)) - -#define TMRB_INTERVAL_TIMER ((uint32_t)0x00000001) -#define TMRB_EVENT_CNT ((uint32_t)0x00000000) -#define IS_TMRB_MODE(param) (((param) == TMRB_INTERVAL_TIMER) || \ - ((param) == TMRB_EVENT_CNT)) - -#define TMRB_CLK_DIV_2 ((uint32_t)0x00000001) -#define TMRB_CLK_DIV_8 ((uint32_t)0x00000002) -#define TMRB_CLK_DIV_32 ((uint32_t)0x00000003) -#define TMRB_CLK_DIV_64 ((uint32_t)0x00000004) -#define TMRB_CLK_DIV_128 ((uint32_t)0x00000005) -#define TMRB_CLK_DIV_256 ((uint32_t)0x00000006) -#define TMRB_CLK_DIV_512 ((uint32_t)0x00000007) -#define IS_TMRB_CLK_DIV(param) (((param) == TMRB_CLK_DIV_2) || \ - ((param) == TMRB_CLK_DIV_8) || \ - ((param) == TMRB_CLK_DIV_32) || \ - ((param) == TMRB_CLK_DIV_64) || \ - ((param) == TMRB_CLK_DIV_128) || \ - ((param) == TMRB_CLK_DIV_256) || \ - ((param) == TMRB_CLK_DIV_512)) - -#define TMRB_FREE_RUN ((uint32_t)0x00000000) -#define TMRB_AUTO_CLEAR ((uint32_t)0x00000008) -#define IS_TMRB_UC_CTRL(param) (((param) == TMRB_FREE_RUN) || \ - ((param) == TMRB_AUTO_CLEAR)) - -#define TMRB_FLIPFLOP_INVERT ((uint32_t)0x00000000) -#define TMRB_FLIPFLOP_SET ((uint32_t)0x00000001) -#define TMRB_FLIPFLOP_CLEAR ((uint32_t)0x00000002) -#define IS_TMRB_FLIPFLOP_CTRL(param) (((param) == TMRB_FLIPFLOP_INVERT) || \ - ((param) == TMRB_FLIPFLOP_SET) || \ - ((param) == TMRB_FLIPFLOP_CLEAR)) - -#define TMRB_DISABLE_FLIPFLOP ((uint32_t)0x00000000) -#define TMRB_FLIPFLOP_TAKE_CAPTURE_0 ((uint32_t)0x00000010) -#define TMRB_FLIPFLOP_TAKE_CAPTURE_1 ((uint32_t)0x00000020) -#define TMRB_FLIPFLOP_MATCH_TRAILINGTIMING ((uint32_t)0x00000008) -#define TMRB_FLIPFLOP_MATCH_LEADINGTIMING ((uint32_t)0x00000004) -#define IS_TMRB_FLIPFLOP_TRG(param) (((param) == TMRB_DISABLE_FLIPFLOP) || \ - ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_0) || \ - ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_1) || \ - ((param) == TMRB_FLIPFLOP_MATCH_TRAILINGTIMING) || \ - ((param) == TMRB_FLIPFLOP_MATCH_LEADINGTIMING) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ - ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING))) - -#define TMRB_DISABLE_CAPTURE ((uint32_t)0x00000000) -#define TMRB_CAPTURE_IN_RISING_FALLING ((uint32_t)0x00000020) -#define TMRB_CAPTURE_FF_RISING_FALLING ((uint32_t)0x00000030) -#define IS_TMRB_CAPTURE_TIMING(param) (((param) == TMRB_DISABLE_CAPTURE) || \ - ((param) == TMRB_CAPTURE_IN_RISING_FALLING) || \ - ((param) == TMRB_CAPTURE_FF_RISING_FALLING)) - -#define TMRB_RUN ((uint32_t)0x00000005) -#define TMRB_STOP ((uint32_t)0x00000000) -#define IS_TMRB_CMD(param) (((param) == TMRB_RUN) || ((param) == TMRB_STOP)) - -#define TMRB_REG_0 ((uint8_t)0x00) -#define TMRB_REG_1 ((uint8_t)0x01) -#define IS_TMRB_REG(param) (((param) == TMRB_REG_0) || ((param) == TMRB_REG_1)) - -#define TMRB_CAPTURE_0 ((uint8_t)0x00) -#define TMRB_CAPTURE_1 ((uint8_t)0x01) -#define IS_TMRB_CAPTURE_REG(param) (((param) == TMRB_CAPTURE_0) || ((param) == TMRB_CAPTURE_1)) - -#define TMRB_NO_INT_MASK ((uint32_t)0x00000000) -#define TMRB_MASK_MATCH_LEADINGTIMING_INT ((uint32_t)0x00000001) -#define TMRB_MASK_MATCH_TRAILINGTIMING_INT ((uint32_t)0x00000002) -#define TMRB_MASK_OVERFLOW_INT ((uint32_t)0x00000004) -#define IS_TMRB_INT_MASK(param) (((param) == TMRB_NO_INT_MASK) || \ - ((param) == TMRB_MASK_MATCH_LEADINGTIMING_INT) || \ - ((param) == TMRB_MASK_MATCH_TRAILINGTIMING_INT) || \ - ((param) == TMRB_MASK_OVERFLOW_INT) || \ - ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT)) || \ - ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \ - ((param) == (TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \ - ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT))) - -#define TMRB_TRG_EDGE_RISING ((uint8_t)0x00) -#define TMRB_TRG_EDGE_FALLING ((uint8_t)0x02) -#define IS_TMRB_TRG_EDGE(param) (((param) == TMRB_TRG_EDGE_RISING) || \ - ((param) == TMRB_TRG_EDGE_FALLING)) - -#define TMRB_RUNNING_IN_CORE_HALT ((uint8_t)0x00) -#define TMRB_STOP_IN_CORE_HALT ((uint8_t)0x40) -#define IS_TMRB_CLK_IN_CORE_HALT(param) (((param) == TMRB_RUNNING_IN_CORE_HALT) || \ - ((param) == TMRB_STOP_IN_CORE_HALT)) - -#define TMRB_NO_INT ((uint32_t)0x00000000) -#define IS_TMRB_VALUE(param) ((param) <= 0x0000FFFFU) -#define IS_VALID_LEADINGTIMING(param1, param2) ((param1) <= (param2)) - -#define TMRB_DMA_REQ_CMP_MATCH ((uint32_t)0x000000004) -#define TMRB_DMA_REQ_CAPTURE_1 ((uint32_t)0x000000002) -#define TMRB_DMA_REQ_CAPTURE_0 ((uint32_t)0x000000001) -#define IS_TMRB_DMA_REQ(param) (((param) == TMRB_DMA_REQ_CMP_MATCH) || \ - ((param) == TMRB_DMA_REQ_CAPTURE_1) || \ - ((param) == TMRB_DMA_REQ_CAPTURE_0)) - -/** @} */ -/* End of group TMRB_Exported_Constants */ -/** @defgroup TMRB_Exported_FunctionPrototypes - * @{ - */ - void TMRB_Enable(TSB_TB_TypeDef * TBx); - void TMRB_Disable(TSB_TB_TypeDef * TBx); - void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd); - void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct); - void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming); - void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct); - TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx); - TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx); - void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask); - void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming); - void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming); - uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg); - uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx); - uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg); - void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx); - void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState); - void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState); - void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode); - void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState); - void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq); - -/** @} */ -/* End of group TMRB_Exported_FunctionPrototypes */ - -/** @} */ -/* End of group TMRB */ - -/** @} */ -/* End of group TX00_Periph_Driver */ -#endif /* defined(__TMPM066_TMRB_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TMPM066_TMRB_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h deleted file mode 100644 index 8f5df68ef2..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h +++ /dev/null @@ -1,381 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_uart.h - * @brief This file provides all the functions prototypes for UART driver. - * @version V2.0.2.1 - * @date 2015/09/10 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TMPM066_UART_H -#define __TMPM066_UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "TMPM066.h" -#include "tx00_common.h" - -#if defined(__TMPM066_UART_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** @defgroup UART_Exported_Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ - - typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication - baud rate. */ - uint32_t DataBits; /*!< Specifies UART transfer mode, which could be - 7-bit mode, 8-bit mode or 9-bit mode. */ - uint32_t StopBits; /*!< Specifies the length of stop bit transmission - in UART mode. */ - uint32_t Parity; /*!< Specifies the parity mode which could be odd - parity, even parity or no parity. */ - uint32_t Mode; /*!< Enables or disables Receive, Transmit or - both. */ - uint32_t FlowCtrl; /*!< Specifies wether the hardware flow control - mode is enabled or disabled. */ - } UART_InitTypeDef; - - typedef struct { - uint32_t InputClkEdge; /*!< Select the input clock edge.on the SCLK output mode - this bit only can set to be 0(SIO_SCLKS_TXDF_RXDR) */ - uint32_t TIDLE; /*!< The status of TXDx pin after output of the - last bit */ - uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error - is occured in SCLK input mode */ - uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK - input mode */ - uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which - could be None,1*SCLK,2*SCLK,4*SCLK,8*SCLK,16*SCLK,32*SCLK,64*SCLK. - this bit is valid only for SCLK output mode and double - buffer is enabled. */ - uint32_t TransferMode; /*!< Setting transfer mode which could be transfer prohibited, - half duplex(Receive),half duplex(Transmit) or full duplex. */ - uint32_t TransferDir; /*!< Setting transfer direction which could be - LSB_FRIST or MSB_FRIST. */ - uint32_t Mode; /*!< Enables or disables Receive, Transmit or both. */ - uint32_t DoubleBuffer; /*!< Double Buffer mode is enabled or disabled. */ - uint32_t BaudRateClock; /*!< Select the input clock for baud rate generator */ - uint32_t Divider; /*!< Division ratio "N" */ - } SIO_InitTypeDef; - -/** @} */ -/* End of group UART_Exported_Types */ - -/** @defgroup UART_Exported_Constants - * @{ - */ - -#define UART0 TSB_SC0 -#define UART1 TSB_SC1 - -#define IS_UART_PERIPH(param) (((param) == UART0) || \ - ((param) == UART1)) - -#define SIO0 TSB_SC0 -#define SIO1 TSB_SC1 - -#define IS_SIO_PERIPH(param) (((param) == SIO0) || \ - ((param) == SIO1)) - -#define UART_DATA_BITS_7 ((uint32_t)0x00000004) -#define UART_DATA_BITS_8 ((uint32_t)0x00000008) -#define UART_DATA_BITS_9 ((uint32_t)0x0000000C) -#define IS_UART_DATA_BITS(param) (((param) == UART_DATA_BITS_7) || \ - ((param) == UART_DATA_BITS_8) || \ - ((param) == UART_DATA_BITS_9)) - -#define UART_STOP_BITS_1 ((uint32_t)0x00000000) -#define UART_STOP_BITS_2 ((uint32_t)0x00000010) -#define IS_UART_STOPBITS(param) (((param) == UART_STOP_BITS_1) || \ - ((param) == UART_STOP_BITS_2)) - -#define UART_NO_PARITY ((uint32_t)0x00000000) -#define UART_EVEN_PARITY ((uint32_t)0x00000060) -#define UART_ODD_PARITY ((uint32_t)0x00000020) -#define IS_UART_PARITY(param) (((param) == UART_NO_PARITY) || \ - ((param) == UART_EVEN_PARITY) || \ - ((param) == UART_ODD_PARITY)) - -#define SIO_CLK_SCLKOUTPUT ((uint32_t)0x00000000) -#define SIO_CLK_SCLKINPUT ((uint32_t)0x00000001) -#define IS_SIO_CLK_SEL(param) (((param) == SIO_CLK_SCLKOUTPUT) || \ - ((param) == SIO_CLK_SCLKINPUT)) - -#define SIO_SCLKS_TXDF_RXDR ((uint32_t)0x00000000) -#define SIO_SCLKS_TXDR_RXDF ((uint32_t)0x00000002) -#define IS_SIO_SCLKS_TRXD(param) (((param) == SIO_SCLKS_TXDF_RXDR) || \ - ((param) == SIO_SCLKS_TXDR_RXDF)) - -#define SIO_TIDLE_LOW ((uint32_t)0x00000000) -#define SIO_TIDLE_HIGH ((uint32_t)0x00000100) -#define SIO_TIDLE_LAST ((uint32_t)0x00000200) -#define IS_SIO_TIDLE_LEVEL(param) (((param) == SIO_TIDLE_LOW) || \ - ((param) == SIO_TIDLE_HIGH) || \ - ((param) == SIO_TIDLE_LAST)) - -#define SIO_TXDEMP_LOW ((uint32_t)0x00000000) -#define SIO_TXDEMP_HIGH ((uint32_t)0x00000400) -#define IS_SIO_TXDEMP_LEVEL(param) (((param) == SIO_TXDEMP_LOW) || \ - ((param) == SIO_TXDEMP_HIGH)) - -#define SIO_EHOLD_FC_2 ((uint32_t)0x00000000) -#define SIO_EHOLD_FC_4 ((uint32_t)0x00001000) -#define SIO_EHOLD_FC_8 ((uint32_t)0x00002000) -#define SIO_EHOLD_FC_16 ((uint32_t)0x00003000) -#define SIO_EHOLD_FC_32 ((uint32_t)0x00004000) -#define SIO_EHOLD_FC_64 ((uint32_t)0x00005000) -#define SIO_EHOLD_FC_128 ((uint32_t)0x00006000) -#define IS_SIO_EHOLD_TIME(param) (((param) == SIO_EHOLD_FC_2) || \ - ((param) == SIO_EHOLD_FC_4) || \ - ((param) == SIO_EHOLD_FC_8) || \ - ((param) == SIO_EHOLD_FC_16) || \ - ((param) == SIO_EHOLD_FC_32) || \ - ((param) == SIO_EHOLD_FC_64) || \ - ((param) == SIO_EHOLD_FC_128)) - -#define SIO_SINT_TIME_NONE ((uint32_t)0x00000000) -#define SIO_SINT_TIME_SCLK_1 ((uint32_t)0x00000002) -#define SIO_SINT_TIME_SCLK_2 ((uint32_t)0x00000004) -#define SIO_SINT_TIME_SCLK_4 ((uint32_t)0x00000006) -#define SIO_SINT_TIME_SCLK_8 ((uint32_t)0x00000008) -#define SIO_SINT_TIME_SCLK_16 ((uint32_t)0x0000000A) -#define SIO_SINT_TIME_SCLK_32 ((uint32_t)0x0000000C) -#define SIO_SINT_TIME_SCLK_64 ((uint32_t)0x0000000E) -#define IS_SIO_SINT_TIME(param) (((param) == SIO_SINT_TIME_NONE) || \ - ((param) == SIO_SINT_TIME_SCLK_1) || \ - ((param) == SIO_SINT_TIME_SCLK_2) || \ - ((param) == SIO_SINT_TIME_SCLK_4) || \ - ((param) == SIO_SINT_TIME_SCLK_8) || \ - ((param) == SIO_SINT_TIME_SCLK_16) || \ - ((param) == SIO_SINT_TIME_SCLK_32) || \ - ((param) == SIO_SINT_TIME_SCLK_64)) - -#define SIO_TRANSFER_PROHIBIT ((uint32_t)0x00000000) -#define SIO_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020) -#define SIO_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040) -#define SIO_TRANSFER_FULLDPX ((uint32_t)0x00000060) -#define IS_SIO_TRANSFER_MODE(param) (((param) == SIO_TRANSFER_PROHIBIT) || \ - ((param) == SIO_TRANSFER_HALFDPX_RX) || \ - ((param) == SIO_TRANSFER_HALFDPX_TX) || \ - ((param) == SIO_TRANSFER_FULLDPX)) - -#define SIO_ENABLE_RX ((uint32_t)0x00000020) -#define SIO_ENABLE_TX ((uint32_t)0x00000010) -#define IS_SIO_MODE(param) (((param) == SIO_ENABLE_RX) || \ - ((param) == SIO_ENABLE_TX) || \ - ((param) == (SIO_ENABLE_TX | SIO_ENABLE_RX))) - -#define SIO_LSB_FRIST ((uint32_t)0x00000000) -#define SIO_MSB_FRIST ((uint32_t)0x00000008) -#define IS_SIO_TRANS_DIR(param) (((param) == SIO_LSB_FRIST) || \ - ((param) == SIO_MSB_FRIST)) - -#define SIO_WBUF_DISABLE ((uint32_t)0x00000000) -#define SIO_WBUF_ENABLE ((uint32_t)0x00000004) -#define IS_SIO_WBUF_SET(param) (((param) == SIO_WBUF_DISABLE) || \ - ((param) == SIO_WBUF_ENABLE)) - -#define SIO_BR_CLOCK_TS0 ((uint32_t)0x00000000) -#define SIO_BR_CLOCK_TS2 ((uint32_t)0x00000010) -#define SIO_BR_CLOCK_TS8 ((uint32_t)0x00000020) -#define SIO_BR_CLOCK_TS32 ((uint32_t)0x00000030) -#define IS_SIO_BR_CLOCK(param) (((param) == SIO_BR_CLOCK_TS0) || \ - ((param) == SIO_BR_CLOCK_TS2) || \ - ((param) == SIO_BR_CLOCK_TS8) || \ - ((param) == SIO_BR_CLOCK_TS32)) - -#define SIO_BR_DIVIDER_16 ((uint32_t)0x00000000) -#define SIO_BR_DIVIDER_1 ((uint32_t)0x00000001) -#define SIO_BR_DIVIDER_2 ((uint32_t)0x00000002) -#define SIO_BR_DIVIDER_3 ((uint32_t)0x00000003) -#define SIO_BR_DIVIDER_4 ((uint32_t)0x00000004) -#define SIO_BR_DIVIDER_5 ((uint32_t)0x00000005) -#define SIO_BR_DIVIDER_6 ((uint32_t)0x00000006) -#define SIO_BR_DIVIDER_7 ((uint32_t)0x00000007) -#define SIO_BR_DIVIDER_8 ((uint32_t)0x00000008) -#define SIO_BR_DIVIDER_9 ((uint32_t)0x00000009) -#define SIO_BR_DIVIDER_10 ((uint32_t)0x0000000A) -#define SIO_BR_DIVIDER_11 ((uint32_t)0x0000000B) -#define SIO_BR_DIVIDER_12 ((uint32_t)0x0000000C) -#define SIO_BR_DIVIDER_13 ((uint32_t)0x0000000D) -#define SIO_BR_DIVIDER_14 ((uint32_t)0x0000000E) -#define SIO_BR_DIVIDER_15 ((uint32_t)0x0000000F) -#define IS_SIO_BR_DIVIDER(param) ((param) <= SIO_BR_DIVIDER_15) - -#define IS_SIO_DATA(param) ((param) <= 0xFFU) - -#define SIO_CLOCK_T0_HALF ((uint32_t)0x00000000) -#define SIO_CLOCK_T0 ((uint32_t)0x00000002) -#define IS_SIO_CLOCK(param) (((param) == SIO_CLOCK_T0_HALF) || \ - ((param) == SIO_CLOCK_T0)) - -#define UART_ENABLE_RX ((uint32_t)0x00000020) -#define UART_ENABLE_TX ((uint32_t)0x00000010) -#define IS_UART_MODE(param) (((param) == UART_ENABLE_RX) || \ - ((param) == UART_ENABLE_TX) || \ - ((param) == (UART_ENABLE_TX | UART_ENABLE_RX))) - -#define UART_NONE_FLOW_CTRL ((uint32_t)0x00000000) -#define IS_UART_FLOW_CONTROL(param) ((param) == UART_NONE_FLOW_CTRL) - -#define IS_UART_BAUDRATE(param) (((param) >= 2400U) && \ - ((param) <= 115200U)) - -#define IS_UART_DATA(param) ((param) <= 0x01FFU) - -#define IS_UART_CLOCK(param) ((param) <= ((uint32_t)0x00000001)) -#define IS_UART_TIME(param) ((param) <= ((uint32_t)0x00000006)) -#define UART_RX ((uint32_t)0x00000020) -#define UART_TX ((uint32_t)0x00000040) -#define IS_UART_TRX(param) (((param) == UART_RX) || \ - ((param) == UART_TX)) - -#define UART_TRANSFER_PROHIBIT ((uint32_t)0x00000000) -#define UART_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020) -#define UART_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040) -#define UART_TRANSFER_FULLDPX ((uint32_t)0x00000060) -#define IS_UART_TRANSFER_MODE(param) (((param) == UART_TRANSFER_PROHIBIT) || \ - ((param) == UART_TRANSFER_HALFDPX_RX) || \ - ((param) == UART_TRANSFER_HALFDPX_TX) || \ - ((param) == UART_TRANSFER_FULLDPX)) - -#define UART_RXFIFO_MAX ((uint32_t)0x00000000) -#define UART_RXFIFO_RXFLEVEL ((uint32_t)0x00000010) -#define IS_UATR_RXFIFO_BYTESUSED(param) (((param) == UART_RXFIFO_MAX) || \ - ((param) == UART_RXFIFO_RXFLEVEL)) - -#define UART_RXFIFO4B_FLEVLE_4_2B ((uint32_t)0x00000000) -#define UART_RXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001) -#define UART_RXFIFO4B_FLEVLE_2_2B ((uint32_t)0x00000002) -#define UART_RXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003) -#define IS_UART_RXFIFO4B_FLEVLE(param) (((param) == UART_RXFIFO4B_FLEVLE_4_2B) || \ - ((param) == UART_RXFIFO4B_FLEVLE_1_1B) || \ - ((param) == UART_RXFIFO4B_FLEVLE_2_2B) || \ - ((param) == UART_RXFIFO4B_FLEVLE_3_1B)) - -#define UART_RFIS_REACH_FLEVEL ((uint32_t)0x00000000) -#define UART_RFIS_REACH_EXCEED_FLEVEL ((uint32_t)0x00000040) -#define IS_UATR_RFIS_CONDITION(param) (((param) == UART_RFIS_REACH_FLEVEL) || \ - ((param) == UART_RFIS_REACH_EXCEED_FLEVEL)) - -#define UART_TXFIFO4B_FLEVLE_0_0B ((uint32_t)0x00000000) -#define UART_TXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001) -#define UART_TXFIFO4B_FLEVLE_2_0B ((uint32_t)0x00000002) -#define UART_TXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003) -#define IS_UART_TXFIFO4B_FLEVLE(param) (((param) == UART_TXFIFO4B_FLEVLE_0_0B) || \ - ((param) == UART_TXFIFO4B_FLEVLE_1_1B) || \ - ((param) == UART_TXFIFO4B_FLEVLE_2_0B) || \ - ((param) == UART_TXFIFO4B_FLEVLE_3_1B)) - -#define UART_TRXFIFO_EMPTY ((uint32_t)0x00000000) -#define UART_TRXFIFO_1B ((uint32_t)0x00000001) -#define UART_TRXFIFO_2B ((uint32_t)0x00000002) -#define UART_TRXFIFO_3B ((uint32_t)0x00000003) -#define UART_TRXFIFO_4B ((uint32_t)0x00000004) - -#define UART_TFIS_REACH_FLEVEL ((uint32_t)0x00000000) -#define UART_TFIS_REACH_NOREACH_FLEVEL ((uint32_t)0x00000040) -#define IS_UATR_TFIS_CONDITION(param) (((param) == UART_TFIS_REACH_FLEVEL) || \ - ((param) == UART_TFIS_REACH_NOREACH_FLEVEL)) - -#define UART_RXFIFO_OVERRUN ((uint32_t)0x00000001) - -#define UART_TXFIFO_UNDERRUN ((uint32_t)0x00000001) - -/** @} */ -/* End of group UART_Exported_Constants */ - -/** @addtogroup UART_Exported_Types - * @{ - */ - typedef enum { - UART_NO_ERR = 0U, - UART_OVERRUN = 1U, - UART_PARITY_ERR = 2U, - UART_FRAMING_ERR = 3U, - UART_ERRS = 4U - } UART_Err; - - typedef enum { - UART_RXTXCNT_NONE = 0U, - UART_RXTXCNT_AUTODISABLE = 1U - } UART_TRxDisable; -#define IS_UATR_TRX_AUTODISABLE(param) (((param) == UART_RXTXCNT_NONE) || \ - ((param) == UART_RXTXCNT_AUTODISABLE)) - -/** @} */ -/* End of group UART_Exported_Types */ - -/** @defgroup UART_Exported_FunctionPrototypes - * @{ - */ - - void UART_Enable(TSB_SC_TypeDef * UARTx); - void UART_Disable(TSB_SC_TypeDef * UARTx); - WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint32_t Direction); - void UART_SWReset(TSB_SC_TypeDef * UARTx); - void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct); - uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx); - void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data); - void UART_DefaultConfig(TSB_SC_TypeDef * UARTx); - UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx); - void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState); - void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState); - void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock); - void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState); - void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode); - void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable); - void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState); - void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState); - void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed); - void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel); - void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition); - void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx); - void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel); - void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition); - void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx); - void UART_TxBufferClear(TSB_SC_TypeDef * UARTx); - uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx); - uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx); - uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx); - uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx); - void UART_SetRxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState); - void UART_SetTxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState); - void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock); - void SIO_Enable(TSB_SC_TypeDef * SIOx); - void SIO_Disable(TSB_SC_TypeDef * SIOx); - uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx); - void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data); - void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct); -/** @} */ -/* End of group UART_Exported_FunctionPrototypes */ - -/** @} */ -/* End of group UART */ - -/** @} */ -/* End of group TX00_Periph_Driver */ -#endif /* defined(__TMPM066_UART_H) */ - -#ifdef __cplusplus -} -#endif -#endif /* __TMPM066_UART_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h deleted file mode 100644 index 249356e870..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - ******************************************************************************* - * @file tx00_common.h - * @brief All common macro and definition for TX00 peripheral drivers - * @version V2.1.1 - * @date 2014/11/22 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TX00_COMMON_H -#define __TX00_COMMON_H - -typedef enum { - SUCCESS = 0U, - ERROR = 1U -} Result; - -typedef enum { - BUSY = 0U, - DONE = 1U -} WorkState; - -typedef enum { - DISABLE = 0U, - ENABLE = 1U -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -#define IS_POINTER_NOT_NULL(param) ((void*)(param) != (void*)0) - -/* - * To report the name of the source file and source line number where the - * assert_param error has occurred, "DEBUG" must be defined. And detailed - * definition of assert_failed() is needed to be implemented, which can be - * done, for example, in the main.c file. - */ -#ifdef DEBUG -void assert_failed(char *file, int32_t line); -#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) -#else -#define assert_param(expr) -#endif /* DEBUG */ - -#endif /* __TX00_COMMON_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c deleted file mode 100644 index 862280b10c..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c +++ /dev/null @@ -1,571 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_adc.c - * @brief This file provides API functions for ADC driver. - * @version V2.0.2.1 - * @date 2015/10/09 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_adc.h" - -#if defined(__TMPM066_ADC_H) - -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ -#define MOD0_ADS_SET ((uint32_t)0x00000001) -#define MOD0_SCAN_MASK ((uint32_t)0xFFFFFFFD) -#define MOD0_REPEAT_MASK ((uint32_t)0xFFFFFFFB) -#define MOD0_ITM_CLEAR ((uint32_t)0xFFFFFFE7) -#define MOD0_ADBFN_EOCFN_MASK ((uint32_t)0x000000C0) - -#define MOD1_ADCH_CLEAR ((uint32_t)0xFFFFFFF0) -#define MOD1_ADSCN_CLEAR ((uint32_t)0xFFFFFFCF) - -#define MOD2_HPADCH_CLEAR ((uint32_t)0xFFFFFFF0) -#define MOD2_HPADCE_SET ((uint32_t)0x00000020) -#define MOD2_ADBFHP_EOCFHP_MASK ((uint32_t)0x000000C0) - -#define MOD4_ADHTG_CLEAR ((uint32_t)0xFFFFFFEF) -#define MOD4_ADHTG_SET ((uint32_t)0x00000010) -#define MOD4_ADHS_CLEAR ((uint32_t)0xFFFFFFDF) -#define MOD4_HADHTG_CLEAR ((uint32_t)0xFFFFFFBF) -#define MOD4_HADHTG_SET ((uint32_t)0x00000040) -#define MOD4_HADHS_CLEAR ((uint32_t)0xFFFFFF7F) -#define MOD4_ADRST_MASK ((uint32_t)0xFFFFFFFC) -#define MOD4_ADRST_10 ((uint32_t)0x00000002) -#define MOD4_ADRST_01 ((uint32_t)0x00000001) - -#define ADC_CMPREG_CLEAR ((uint32_t)0xFFFFFF21) -#define ADC_REGx_ADRxRF_MASK ((uint32_t)0x00000001) -#define ADC_REGx_OVRx_MASK ((uint32_t)0x00000002) -#define ADC_REGx_RESULT_MASK ((uint32_t)0x0000FFC0) - -/** @} */ -/* End of group ADC_Private_Defines */ - -/** @defgroup ADC_Private_FunctionPrototypes - * @{ - */ - -/** @} */ -/* End of group ADC_Private_FunctionPrototypes */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @} */ -/* End of group ADC_Private_Functions */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -/** - * @brief Software reset ADC function. - * @param None. - * @retval None. - */ -void ADC_SWReset(void) -{ - /* Set MOD4 = 0b10, 0b01 to reset ADC */ - TSB_AD->MOD4 = MOD4_ADRST_10; - TSB_AD->MOD4 = MOD4_ADRST_01; -} - -/** - * @brief Set A/D conversion time and prescaler output. - * @param Conversion_Time: Select the A/D conversion time. - * This parameter can be one of the following values: - * ADC_CONVERSION_35_CLOCK, ADC_CONVERSION_42_CLOCK, - * ADC_CONVERSION_68_CLOCK, ADC_CONVERSION_81_CLOCK - * @param Prescaler_Output: Select the A/D prescaler output. - * This parameter can be one of the following values: - * ADC_FC_DIVIDE_LEVEL_1, ADC_FC_DIVIDE_LEVEL_2, ADC_FC_DIVIDE_LEVEL_4, ADC_FC_DIVIDE_LEVEL_6, - * ADC_FC_DIVIDE_LEVEL_8, ADC_FC_DIVIDE_LEVEL_12, ADC_FC_DIVIDE_LEVEL_16, - * ADC_FC_DIVIDE_LEVEL_24, ADC_FC_DIVIDE_LEVEL_48, ADC_FC_DIVIDE_LEVEL_96. - * @retval None. - */ -void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output) -{ - /* Check the parameters */ - assert_param(IS_ADC_CONVERSION_TIME(Conversion_Time)); - assert_param(IS_ADC_PRESCALER(Prescaler_Output)); - /* Set ADCLK */ - TSB_AD->CLK = Conversion_Time + Prescaler_Output; -} - -/** - * @brief Start ADC function. - * @param None. - * @retval None. - */ -void ADC_Start(void) -{ - /* Set ADMOD0 = 1 to start ADC */ - TSB_AD->MOD0 |= MOD0_ADS_SET; -} - -/** - * @brief Set ADC scan mode. - * @param NewState: Specify ADC scan mode. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetScanMode(FunctionalState NewState) -{ - /* read MOD0, and clear bit1 which is "ADMOD0" */ - uint32_t tmp = TSB_AD->MOD0 & MOD0_SCAN_MASK; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* Set ADMOD0 */ - tmp |= (uint32_t) NewState << 1U; - TSB_AD->MOD0 = tmp; -} - -/** - * @brief Set ADC repeat mode. - * @param NewState: Specify ADC repeat mode. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetRepeatMode(FunctionalState NewState) -{ - /* read MOD0, and clear bit2 which is "ADMOD0" */ - uint32_t tmp = TSB_AD->MOD0 & MOD0_REPEAT_MASK; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Set ADMOD0 */ - tmp |= (uint32_t) NewState << 2U; - TSB_AD->MOD0 = tmp; -} - -/** - * @brief Set ADC interrupt mode in fixed channel repeat conversion mode. - * @param INTMode: Specify AD conversion interrupt mode. - * This parameter can be one of the following values: - * ADC_INT_SINGLE, ADC_INT_CONVERSION_4 or ADC_INT_CONVERSION_8. - * @retval None. - */ -void ADC_SetINTMode(uint32_t INTMode) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_ADC_INT_MODE(INTMode)); - /* Set ADMOD0 */ - tmp = TSB_AD->MOD0; - tmp &= MOD0_ITM_CLEAR; - tmp |= INTMode; - TSB_AD->MOD0 = tmp; -} - -/** - * @brief Read AD conversion completion/busy flag (normal and top-priority). - * @param None - * @retval A union with the state of AD conversion. - */ -ADC_State ADC_GetConvertState(void) -{ - uint32_t tmpmod0 = TSB_AD->MOD0; - uint32_t tmpmod2 = TSB_AD->MOD2; - ADC_State retval = { 0U }; - - tmpmod0 &= MOD0_ADBFN_EOCFN_MASK; - tmpmod2 &= MOD2_ADBFHP_EOCFHP_MASK; - retval.All = (tmpmod0 >> 6U) | (tmpmod2 >> 4U); - return retval; -} - -/** - * @brief Set ADC input channel. - * @param InputChannel: Analog input channel, it also related with other settings. - * This parameter can be one of the following values: - * ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3, - * ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7. - * @retval None. - */ -void ADC_SetInputChannel(uint32_t InputChannel) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_ADC_INPUT_CH(InputChannel)); - /* Set ADMOD1 */ - tmp = TSB_AD->MOD1; - tmp &= MOD1_ADCH_CLEAR; - tmp |= InputChannel; - TSB_AD->MOD1 = tmp; -} - -/** - * @brief Set ADC operation for scanning. - * @param ScanMode: Spcifiy operation mode for channel scanning. - * This parameter can be one of the following values: - * ADC_SCAN_4CH, ADC_SCAN_8CH. - * @retval None. - */ -void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_ADC_CH_SCAN_MODE(ScanMode)); - tmp = TSB_AD->MOD1; - tmp &= MOD1_ADSCN_CLEAR; - tmp |= ((uint32_t) ScanMode << 4U); - TSB_AD->MOD1 = tmp; -} - -/** - * @brief Set ADC in IDLE mode. - * @param NewState: Specify AD conversion in IDLE mode. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetIdleMode(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* Set ADMOD1 */ - TSB_AD_MOD1_I2AD = NewState; -} - -/** - * @brief Set ADC VREF application. - * @param NewState: Specify ADC Vref application. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetVref(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* Set ADMOD1 */ - TSB_AD_MOD1_VREFON = NewState; -} - -/** - * @brief Set ADC top-priority conversion analog input channel select. - * @param TopInputChannel: Analog input channel for top-priority conversion. - * This parameter can be one of the following values: - * ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3, - * ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7. - * @retval None. - */ -void ADC_SetInputChannelTop(uint32_t TopInputChannel) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_ADC_INPUT_CH(TopInputChannel)); - /* Set ADMOD2 */ - tmp = TSB_AD->MOD2; - tmp &= MOD2_HPADCH_CLEAR; - tmp |= TopInputChannel; - TSB_AD->MOD2 = tmp; -} - -/** - * @brief Start top-priority ADC. - * @param None. - * @retval None. - */ -void ADC_StartTopConvert(void) -{ - /* Set ADMOD2 = 1 to start top-priority ADC */ - TSB_AD->MOD2 |= MOD2_HPADCE_SET; -} - -/** - * @brief Set ADC monitor function. - * @param ADCMPx: Select ADC compare register. - * This parameter can be one of the following values: - * ADC_CMP_0 or ADC_CMP_1. - * @param NewState: Specify ADC monitor function. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_CMP(ADCMPx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (ADCMPx == ADC_CMP_0) { - /* Set ADMOD3 */ - TSB_AD_MOD3_ADOBSV0 = NewState; - } else { - /* Set ADMOD5 */ - TSB_AD_MOD5_ADOBSV1 = NewState; - } -} - -/** - * @brief Set ADC result output register or comparison register. - * @param ADCMPx: Select AD compare register. - * This parameter can be one of the following values: - * ADC_CMP_0 or ADC_CMP_1. - * @param ResultComparison: Set AD conversion result storage register or - * comparison register if ADC monitor function is enabled. - * This parameter can be one of the following values: - * ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3, - * ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP. - * @retval None. - */ -void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_ADC_CMP(ADCMPx)); - assert_param(IS_ADC_RESULT_CMP_REG(ResultComparison)); - if (ADC_CMP_0 == ADCMPx) { - /* Set ADMOD3 */ - tmp = TSB_AD->MOD3; - tmp &= ADC_CMPREG_CLEAR; - tmp |= ResultComparison; - TSB_AD->MOD3 = tmp; - } else { - /* Set ADMOD5 */ - tmp = TSB_AD->MOD5; - tmp &= ADC_CMPREG_CLEAR; - tmp |= ResultComparison; - TSB_AD->MOD5 = tmp; - } -} - -/** - * @brief Set ADC monitor interrupt. - * @param ADCMPx: Select ADC compare register. - * This parameter can be one of the following values: - * ADC_CMP_0 or ADC_CMP_1. - * @param NewState: Specify ADC monitor function. - * This parameter can be one of the following values: - * ADC_COMPARISON_SMALLER or ADC_COMPARISON_LARGER. - * @retval None. - */ -void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_CMP(ADCMPx)); - assert_param(IS_ADC_CMP_INT(NewState)); - if (ADCMPx == ADC_CMP_0) { - /* Set ADMOD3 */ - TSB_AD_MOD3_ADOBIC0 = NewState; - } else { - /* Set ADMOD5 */ - TSB_AD_MOD5_ADOBIC1 = NewState; - } -} - -/** - * @brief Set hardware trigger for normal ADC function. - * @param HwSource: HW source for activating normal ADC. - * This parameter can be one of the following values: - * ADC_EXT_TRG or ADC_MATCH_TB_0. - * @param NewState: Specify HW for activating normal ADC. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_ADC_HW_TRG_NORMAL(HwSource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* Set ADMOD4 */ - tmp = TSB_AD->MOD4; - tmp &= MOD4_ADHS_CLEAR; - tmp |= HwSource; - /* Set ADMOD4 */ - if (NewState == ENABLE) { - tmp |= MOD4_ADHTG_SET; - } else { - tmp &= MOD4_ADHTG_CLEAR; - } - TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK; -} - -/** - * @brief Set hardware trigger for top-priority ADC function. - * @param HwSource: HW source for activating top-priority ADC. - * This parameter can be one of the following values: - * ADC_EXT_TRG or ADC_MATCH_TB_1. - * @param NewState: Specify HW for activating top-priority ADC. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_ADC_HW_TRG_TOP(HwSource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* Set ADMOD4 */ - tmp = TSB_AD->MOD4; - tmp &= MOD4_HADHS_CLEAR; - tmp |= HwSource; - /* Set ADMOD4 */ - if (NewState == ENABLE) { - tmp |= MOD4_HADHTG_SET; - } else { - tmp &= MOD4_HADHTG_CLEAR; - } - TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK; -} - -/** - * @brief Read ADC result. - * @param ADREGx: ADC result register. - * This parameter can be one of the following values: - * ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3, - * ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP. - * @retval ADC result. - */ -ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx) -{ - uint32_t tmp = 0U; - ADC_ResultTypeDef retval = { BUSY, ADC_NO_OVERRUN, 0U }; - - /* Check the parameters */ - assert_param(IS_ADC_REG(ADREGx)); - /* Read ADREGx to get ADC result */ - switch (ADREGx) { - case ADC_REG_0: - tmp = TSB_AD->REG0; - break; - case ADC_REG_1: - tmp = TSB_AD->REG1; - break; - case ADC_REG_2: - tmp = TSB_AD->REG2; - break; - case ADC_REG_3: - tmp = TSB_AD->REG3; - break; - case ADC_REG_4: - tmp = TSB_AD->REG4; - break; - case ADC_REG_5: - tmp = TSB_AD->REG5; - break; - case ADC_REG_6: - tmp = TSB_AD->REG6; - break; - case ADC_REG_7: - tmp = TSB_AD->REG7; - break; - case ADC_REG_SP: - tmp = TSB_AD->REGSP; - break; - default: /* Do nothing */ - break; - } - - if ((tmp & ADC_REGx_ADRxRF_MASK) == 0U) { - retval.ADCResultStored = BUSY; - } else { - retval.ADCResultStored = DONE; - } - - if ((tmp & ADC_REGx_OVRx_MASK) == 0U) { - retval.ADCOverrunState = ADC_NO_OVERRUN; - } else { - retval.ADCOverrunState = ADC_OVERRUN; - } - - retval.ADCResultValue = (uint16_t) tmp & ADC_REGx_RESULT_MASK; - retval.ADCResultValue >>= 6U; - - return retval; -} - -/** - * @brief Set ADC comparison register value. - * @param ADCMPx: Select AD compare register. - * This parameter can be one of the following values: - * ADC_CMP_0 or ADC_CMP_1. - * @param value: The value setting to ADC comparison register. - * @retval None. - */ -void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value) -{ - - /* Check the parameters */ - assert_param(IS_ADC_CMP(ADCMPx)); - assert_param(IS_ADC_CMP_VALUE(value)); - value <<= 6U; - if (ADCMPx == ADC_CMP_0) { - /* Set ADCMP0 */ - TSB_AD->CMP0 = value; - } else { - /* Set ADCMP1 */ - TSB_AD->CMP1 = value; - } -} - -/** - * @breif Enable or disable DMA activation factor for normal or top-priority AD conversion. - * @param DMAReq: Specify AD conversion DMA request type. - * This parameter can be one of the following values: - * ADC_DMA_REQ_NORMAL, ADC_DMA_REQ_TOP, - * ADC_DMA_REQ_MONITOR1, ADC_DMA_REQ_MONITOR2. - * @param NewState: Specify AD conversion DMA activation factor. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_REQ(DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - switch (DMAReq) { - case ADC_DMA_REQ_NORMAL: - TSB_AD_MOD6_ADDMA = NewState; - break; - case ADC_DMA_REQ_TOP: - TSB_AD_MOD6_ADHPDMA = NewState; - break; - case ADC_DMA_REQ_MONITOR1: - TSB_AD_MOD6_ADM0DMA = NewState; - break; - case ADC_DMA_REQ_MONITOR2: - TSB_AD_MOD6_ADM1DMA = NewState; - break; - default: - /* Do nothing */ - break; - } -} - -/** @} */ -/* End of group ADC_Exported_Functions */ - -/** @} */ -/* End of group ADC */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_ADC_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c deleted file mode 100644 index 7fd55c2b16..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c +++ /dev/null @@ -1,698 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_cg.c - * @brief This file provides API functions for CG driver - * @version V2.0.2.1 - * @date 2015/09/22 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_cg.h" - -#if defined(__TMPM066_CG_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup CG - * @brief CG driver modules - * @{ - */ - -/** @defgroup CG_Private_Defines - * @{ - */ - -#define CG_FC_GEAR_MASK ((uint32_t)0xFFFFFFF8) -#define CG_PRCK_MASK ((uint32_t)0xFFFFF0FF) -#define CG_WUP_TIME_MASK ((uint32_t)0x000FFFFF) -#define CG_WUP_COUNTER_MASK ((uint32_t)0xFFFFFEFF) -#define CG_WUP_START_SET ((uint32_t)0x00000001) -#define CG_WUEF_VALUE_MASK ((uint32_t)0x00000002) -#define CG_OSCCR_IOSCEN_SET ((uint32_t)0x00000001) -#define CG_OSCCR_IOSCEN_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_OSCCR_EOSCEN_EHOSC ((uint32_t)0x00000002) -#define CG_OSCCR_EOSCEN_NOUSE ((uint32_t)0xFFFFFFF9) -#define CG_OSCCR_EOSCEN_MASK ((uint32_t)0x00000006) -#define CG_OSCCR_EOSCEN_CLKIN ((uint32_t)0x00000004) -#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) -#define CG_OSCCR_OSCSEL_CLEAR ((uint32_t)0xFFFFFEFF) -#define CG_OSCCR_OSCF_SET ((uint32_t)0x00000200) -#define CG_OSCCR_WUPT_MASK ((uint32_t)0x00FFFFFF) - -#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) -#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) -#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) -#define CG_PLL0SEL_PLLST_SET ((uint32_t)0x00000004) - -#define CG_PLL0SET_VALUE_MASK ((uint32_t)0xFFFFFF00) -#define CG_PLL0SEL_PLL0SET_MASK ((uint32_t)0xFFFFFF00) - -#define CG_STBY_MODE_MASK ((uint32_t)0xFFFFFFFC) -//#define CG_NMIFLG_MASK ((uint32_t)0xFFF8FFFF) - -#define FC_GEAR_1_1 ((uint32_t)0x00000000) -#define FC_GEAR_1_2 ((uint32_t)0x00000001) -#define FC_GEAR_1_4 ((uint32_t)0x00000002) -#define FC_GEAR_1_8 ((uint32_t)0x00000003) -#define FC_GEAR_1_16 ((uint32_t)0x00000004) - -#define WARM_UP_SEL_OSC_INT_HIGH ((uint32_t)0xFFFFFEFF) -#define WARM_UP_SEL_OSC_EXT_HIGH ((uint32_t)0x00000100) - -#define CG_PROTECT_SET ((uint32_t)0x000000C1) -#define CG_PROTECT_CLEAR ((uint32_t)0x0000003E) - -//#define INT_NCLR_PCLR_CLEAR ((uint8_t)0x01) -#define ADC_MOD0_BUSY_MASK ((uint32_t)0x00000040) -#define CG_SPCLKEN_ADCKEN_CLEAR ((uint32_t)0xFFFEFFFF) -#define CG_SPCLKEN_ADCKEN_SET ((uint32_t)0x00010000) - - -static CG_DivideLevel numToDivideLevel_table[CG_DIVIDE_MAX] = { - CG_DIVIDE_1, - CG_DIVIDE_2, - CG_DIVIDE_4, - CG_DIVIDE_8, - CG_DIVIDE_16, - CG_DIVIDE_32, - CG_DIVIDE_64, - CG_DIVIDE_128, - CG_DIVIDE_256, - CG_DIVIDE_512, - CG_DIVIDE_UNKNOWN, -}; - -static CG_STBYMode numToSTBYMode_table[CG_STBY_MODE_MAX] = { - CG_STBY_MODE_IDLE, - CG_STBY_MODE_STOP1, - CG_STBY_MODE_UNKNOWN, - CG_STBY_MODE_UNKNOWN, -}; - -/** @} */ -/* End of group CG_Private_Defines */ - -/** @defgroup CG_Private_FunctionPrototypes - * @{ - */ - -/** @} */ -/* End of group CG_Private_FunctionPrototypes */ - -/** @defgroup CG_Private_Functions - * @{ - */ - -/** @} */ -/* End of group CG_Private_Functions */ - -/** @defgroup CG_Exported_Functions - * @{ - */ - -/** - * @brief Set dividing level between clock fgear and fc. - * @param DivideFgearFromFc: Dividing level between fgear and fc. - * This parameter can be one of the following values: - * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, CG_DIVIDE_16 - * @retval None - */ -void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc) -{ - uint32_t gear = FC_GEAR_1_1; - uint32_t regval = TSB_CG->SYSCR; - - /* Check the parameters */ - assert_param(IS_CG_GEAR_DIVIDE_LEVEL(DivideFgearFromFc)); - - /* Set the value of fgear */ - switch (DivideFgearFromFc) { - case CG_DIVIDE_1: - gear = FC_GEAR_1_1; - break; - case CG_DIVIDE_2: - gear = FC_GEAR_1_2; - break; - case CG_DIVIDE_4: - gear = FC_GEAR_1_4; - break; - case CG_DIVIDE_8: - gear = FC_GEAR_1_8; - break; - case CG_DIVIDE_16: - gear = FC_GEAR_1_16; - break; - default: - /* Do nothing */ - break; - } - - regval &= CG_FC_GEAR_MASK; - regval |= gear; - TSB_CG->SYSCR = regval; -} - -/** - * @brief Get dividing level between clock fgear and fc. - * @param None - * @retval The dividing level between clock fgear and fc - * The value returned can be one of the following values: - * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, - * CG_DIVIDE_8, CG_DIVIDE_16 or CG_DIVIDE_UNKNOWN - */ -CG_DivideLevel CG_GetFgearLevel(void) -{ - CG_DivideLevel DivideFgearFromFc = CG_DIVIDE_UNKNOWN; - uint32_t syscr = TSB_CG->SYSCR; - syscr &= (~CG_FC_GEAR_MASK); - - switch (syscr) { - case FC_GEAR_1_1: - DivideFgearFromFc = CG_DIVIDE_1; - break; - case FC_GEAR_1_2: - DivideFgearFromFc = CG_DIVIDE_2; - break; - case FC_GEAR_1_4: - DivideFgearFromFc = CG_DIVIDE_4; - break; - case FC_GEAR_1_8: - DivideFgearFromFc = CG_DIVIDE_8; - break; - case FC_GEAR_1_16: - DivideFgearFromFc = CG_DIVIDE_16; - break; - default: - /* Do nothing */ - break; - } - - return DivideFgearFromFc; -} - -/** - * @brief Set dividing level between clock PhiT0 and fc. - * @param DividePhiT0FromFc: Dividing level between PhiT0 and fc. - * This parameter can be one of the following values: - * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, - * CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128, - * CG_DIVIDE_256 or CG_DIVIDE_512 - * @retval Success or not - * The value returned can be one of the following values: - * SUCCESS or ERROR - */ -Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc) -{ - uint32_t fprclk = 0U; - Result retval = ERROR; - uint32_t regval = TSB_CG->SYSCR; - - /* Check the parameters */ - assert_param(IS_CG_DIVIDE_FC_LEVEL(DividePhiT0FromFc)); - - fprclk = (uint32_t) DividePhiT0FromFc; - regval &= CG_PRCK_MASK; - fprclk <<= 8U; - regval |= fprclk; - TSB_CG->SYSCR = regval; - retval = SUCCESS; - - return retval; -} - -/** - * @brief Get dividing level between clock phiT0 and fc. - * @param None - * @retval The divide level between clock phiT0 and fc - * The value returned can be one of the following values: - * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, - * CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128, - * CG_DIVIDE_256, CG_DIVIDE_512 or CG_DIVIDE_UNKNOWN - */ -CG_DivideLevel CG_GetPhiT0Level(void) -{ - uint32_t fprclk = 0U; - CG_DivideLevel phiT0Level = CG_DIVIDE_UNKNOWN; - - fprclk = TSB_CG->SYSCR & (~CG_PRCK_MASK); - fprclk = (uint32_t) (fprclk >> 8U); - - phiT0Level = numToDivideLevel_table[fprclk]; - - return phiT0Level; -} - -/** - * @brief Set the warm up time - * @param Source: Select source of warm-up counter - * This parameter can be one of the following values: - * CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WARM_UP_SRC_OSC_EXT_HIGH. - * Warm-up function is not necessary when using stable external clock. - * @param Time: Set number of warm-up cycle. It is between 0x0000 and 0xFFFF. - * @retval None - */ -void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time) -{ - uint32_t wupt = 0U; - uint32_t regval = TSB_CG->WUPHCR; - - /* Check the parameters */ - assert_param(IS_CG_WARM_UP_SRC(Source)); - - /* Get high 12 bits of warm-up time */ - wupt = (((uint32_t) Time) & CG_OSCCR_WUPT_MASK) << 20U; - - regval &= CG_WUP_TIME_MASK; - regval &= CG_WUP_COUNTER_MASK; - - switch (Source) { - case CG_WARM_UP_SRC_OSC_INT_HIGH: - regval |= wupt; - regval &= WARM_UP_SEL_OSC_INT_HIGH; - break; - case CG_WARM_UP_SRC_OSC_EXT_HIGH: - regval |= wupt; - regval |= WARM_UP_SEL_OSC_EXT_HIGH; - break; - default: - /* Do nothing */ - break; - } - - TSB_CG->WUPHCR = regval; -} - -/** - * @brief Start operation of warm up timer for oscillator. - * @param None - * @retval None - */ -void CG_StartWarmUp(void) -{ - uint32_t regval = TSB_CG->WUPHCR; - regval |= CG_WUP_START_SET; - TSB_CG->WUPHCR = regval; -} - -/** - * @brief Check whether warm up is completed or not. - * @param None - * @retval The state of warm-up - * The value returned can be one of the following values: - * DONE or BUSY - */ -WorkState CG_GetWarmUpState(void) -{ - WorkState state = BUSY; - uint32_t wuef = 0U; - uint32_t regval = TSB_CG->WUPHCR; - - wuef = regval & CG_WUEF_VALUE_MASK; - if (wuef == 0U) { - state = DONE; - } else { - /* Do nothing */ - } - - return state; -} - -/** - * @brief Set PLL multiplying value - * @param NewValue: PLL multiplying value - * This parameter can be one of the following values: - * CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL, - * CG_16M_MUL_6_FPLL. - * @retval Success or not - * The value returned can be one of the following values: - * SUCCESS or ERROR - */ -Result CG_SetFPLLValue(uint32_t NewValue) -{ - Result retval = SUCCESS; - - /* read PLL0SEL and clear PLL0SET(bit14:0) */ - uint32_t tmp = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0SET_MASK; - - /* Check the parameters */ - assert_param(IS_CG_FPLL_VALUE(NewValue)); - - /* Don't use the PLL when internal high-speed oscillator (IHOSC) is used as system clock */ - /* When PLL is on, don't change the PLL setting value */ - if (CG_FOSC_OSC_INT == CG_GetFoscSrc()) { - retval = ERROR; - } else if (ENABLE == CG_GetPLLState()) { - retval = ERROR; - } else { - tmp |= NewValue; - TSB_CG->PLL0SEL = tmp; - } - - return retval; -} - -/** - * @brief Get the value of PLL setting - * @param None - * @retval Get the value of PLL setting. - * CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL, - * CG_16M_MUL_6_FPLL. - */ -uint32_t CG_GetFPLLValue(void) -{ - uint32_t PLL0SEL = TSB_CG->PLL0SEL & CG_PLL0SET_VALUE_MASK; - - return PLL0SEL; -} - -/** - * @brief Enable PLL or disable it. - * @param NewState: New state of PLL - * This parameter can be one of the following values: - * DISABLE or ENABLE - * @retval Success or not - * The value returned can be one of the following values: - * SUCCESS or ERROR - */ -Result CG_SetPLL(FunctionalState NewState) -{ - Result retval = ERROR; - uint32_t regval = TSB_CG->PLL0SEL; - CG_FcSrc fcsrc = CG_FC_SRC_FPLL; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - regval |= CG_PLL0SEL_PLL0ON_SET; - retval = SUCCESS; - } else { - fcsrc = CG_GetFcSrc(); - if (fcsrc == CG_FC_SRC_FOSC) { /* PLL is not used. So it can be shut off */ - /* Set register to disable PLL */ - regval &= CG_PLL0SEL_PLL0ON_CLEAR; - retval = SUCCESS; - } else { /*fcsrc == CG_FC_SRC_FPLL. PLL is in use, so disabling it should be invalid */ - /* Do nothing */ - } - } - TSB_CG->PLL0SEL = regval; - return retval; -} - -/** - * @brief Get the status of PLL operation - * @param None - * @retval Run or stop - * The value returned can be one of the following values: - * ENABLE or DISABLE - */ -FunctionalState CG_GetPLLState(void) -{ - FunctionalState pllstate = DISABLE; - uint32_t regval = TSB_CG->PLL0SEL; - - regval &= CG_PLL0SEL_PLL0ON_SET; - if (regval == CG_PLL0SEL_PLL0ON_SET) { - pllstate = ENABLE; - } else { - /* Do nothing */ - } - - return pllstate; -} - - -/** - * @brief Set the source of high-speed oscillator (fosc) - * @param Source: Select clock source for fosc - * This parameter can be one of the following values: - * CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT - * @retval None - */ -void CG_SetFoscSrc(CG_FoscSrc Source) -{ - /* Check the parameters */ - assert_param(IS_CG_FOSC_SRC(Source)); - - if (Source == CG_FOSC_OSC_INT) { - /*Selects internal high-speed oscillator */ - TSB_CG->OSCCR |= CG_OSCCR_IOSCEN_SET; - TSB_CG->OSCCR &= CG_OSCCR_OSCSEL_CLEAR; - } else { - /*Selects external high-speed oscillator */ - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - TSB_CG->OSCCR &= CG_OSCCR_IOSCEN_CLEAR | CG_OSCCR_EOSCEN_NOUSE; - if (Source == CG_FOSC_OSC_EXT) { - /*Selects external high-speed oscillator */ - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_EHOSC; - } else { - /*Selects an external clock input */ - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_CLKIN; - } - } -} - -/** - * @brief Get the source of high-speed oscillator (fosc) - * @param None - * @retval Source of fosc - * The value returned can be one of the following values: - * CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT - */ -CG_FoscSrc CG_GetFoscSrc(void) -{ - uint32_t regval = TSB_CG->OSCCR; - uint32_t oscf = 0U; - uint32_t hoscon = 0U; - CG_FoscSrc fosc_src = CG_FOSC_CLKIN_EXT; - - oscf = regval & CG_OSCCR_OSCF_SET; - hoscon = regval & CG_OSCCR_EOSCEN_MASK; - if (oscf == 0U) { - fosc_src = CG_FOSC_OSC_INT; - } else { - if (hoscon == CG_OSCCR_EOSCEN_EHOSC) { - fosc_src = CG_FOSC_OSC_EXT; - } else { - /* Do nothing */ - } - } - - return fosc_src; -} - -/** - * @brief Set to the specified low-power mode - * @param Low power mode - * The value can be one of the following values: - * CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE. - * @retval None - */ -void CG_SetSTBYMode(CG_STBYMode Mode) -{ - uint32_t regval = TSB_CG->STBYCR; - - /* Check the parameter */ - assert_param(IS_CG_STBY_MODE(Mode)); - - regval &= CG_STBY_MODE_MASK; - regval |= (uint32_t) Mode; - - TSB_CG->STBYCR = regval; -} - -/** - * @brief Get the low-power consumption mode - * @param None - * @retval Low power mode - * The value returned can be one of the following values: - * CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE, CG_STBY_MODE_UNKNOWN. - */ -CG_STBYMode CG_GetSTBYMode(void) -{ - CG_STBYMode stby_mode = CG_STBY_MODE_UNKNOWN; - uint8_t regval = (uint8_t) (TSB_CG->STBYCR & (~CG_STBY_MODE_MASK)); - - stby_mode = numToSTBYMode_table[regval]; - - return stby_mode; -} - -/** - * @brief Set the source of fc - * @param Source: The source of fc - * This parameter can be one of the following values: - * CG_FC_SRC_FOSC or CG_FC_SRC_FPLL - * @retval None - */ -void CG_SetFcSrc(CG_FcSrc Source) -{ - uint32_t regval = TSB_CG->PLL0SEL; - - /* Check the parameters */ - assert_param(IS_CG_FC_SRC(Source)); - - if (Source == CG_FC_SRC_FOSC) { - regval &= CG_PLL0SEL_PLL0SEL_CLEAR; - } else { - regval |= CG_PLL0SEL_PLL0SEL_SET; - } - TSB_CG->PLL0SEL = regval; -} - -/** - * @brief Get the source of fc - * @param None - * @retval The source of fc - * The value returned can be one of the following values: - * CG_FC_SRC_FOSC or CG_FC_SRC_FPLL - */ -CG_FcSrc CG_GetFcSrc(void) -{ - uint32_t regval = TSB_CG->PLL0SEL; - CG_FcSrc fcsrc = CG_FC_SRC_FOSC; - - regval &= CG_PLL0SEL_PLLST_SET; - if (regval == CG_PLL0SEL_PLLST_SET) { - fcsrc = CG_FC_SRC_FPLL; - } else { - /* Do nothing */ - } - - return fcsrc; -} - -/** - * @brief Enable or disable to protect CG registers - * @param NewState: New state of the CG protect register - * This parameter can be one of the following values: - * DISABLE or ENABLE - * @retval None - */ -void CG_SetProtectCtrl(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - TSB_CG->PROTECT = CG_PROTECT_SET; - } else { - TSB_CG->PROTECT = CG_PROTECT_CLEAR; - } -} - -/** - * @brief Enable or disable supplying clock fsys to peripheries - * @param Periph: The target peripheral of CG supplies clock - * This parameter can be one of the following values or their combination: - * CG_FC_PERIPH_PORTH, CG_FC_PERIPH_PORTJ, CG_FC_PERIPH_TMRB0_3, - * CG_FC_PERIPH_TMRB4_6, CG_FC_PERIPH_TMR16A, CG_FC_PERIPH_I2C0, - * CG_FC_PERIPH_SIO0, CG_FC_PERIPH_TSPI, CG_FC_PERIPH_DMAC, - * CG_FC_PERIPH_ADC, CG_FC_PERIPH_USBD, CG_FC_PERIPH_TMRD, - * CG_FC_PERIPHA_ALL. - * @param NewState: New state of clock supply setting. - * This parameter can be one of the following values: - * DISABLE or ENABLE - * @retval None - */ -void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_CG_FC_PERIPHA(Periph)); - if (NewState == ENABLE) { /* write '1' to enable */ - TSB_CG->FSYSENA |= Periph; - } else { /* clear to '0' to disable */ - TSB_CG->FSYSENA &= ~Periph; - } -} - - /** - * @brief Enable or disable supplying clock fsys to peripheries - * @param Periph: The target peripheral of CG supplies clock - * This parameter can be one of the following values or their combination: - * CG_FC_PERIPH_TMRB7, CG_FC_PERIPH_SIO1, CG_FC_PERIPH_WDT, - * CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL. - * @param NewState: New state of clock supply setting. - * This parameter can be one of the following values: - * DISABLE or ENABLE - * @retval None - */ -void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_CG_FC_PERIPHB(Periph)); - if (NewState == ENABLE) { /* write '1' to enable */ - TSB_CG->FSYSENB |= Periph; - } else { /* clear to '0' to disable */ - TSB_CG->FSYSENB &= ~Periph; - } -} - - /** - * @brief Enable or disable supplying clock fsys to peripheries - * @param Periph: The target peripheral of CG supplies clock - * This parameter can be one of the following values or their combination: - * CG_FPLL_PERIPH_TMRD, CG_EHCLKSEL_8_24_48MHZ, CG_USBSEL_PLL_CLOCKIN, - * CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL. - * @param NewState: New state of clock supply setting. - * This parameter can be one of the following values: - * DISABLE or ENABLE - * @retval None - */ -void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_CG_FPLL_OPTIONAL(Periph)); - if (NewState == ENABLE) { /* write '1' to enable */ - TSB_CG->EXTENDO0 |= Periph; - } else { /* clear to '0' to disable */ - TSB_CG->EXTENDO0 &= ~Periph; - } -} - -/** - * @brief Enable or disable supplying clock fsys for ADC. - * @param NewState: New state of clock fsys supply setting for ADC. - * This parameter can be one of the following values: - * ENABLE or DISABLE. - * @retval None. - */ -void CG_SetADCClkSupply(FunctionalState NewState) -{ - volatile uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check ADC is not during conversion */ - do { - tmp = TSB_AD->MOD0 & ADC_MOD0_BUSY_MASK; - } - while (tmp); - - /* Set CGSPCLKEN */ - tmp = TSB_CG->SPCLKEN; - if (NewState == ENABLE) { - tmp |= CG_SPCLKEN_ADCKEN_SET; - } else { - tmp &= CG_SPCLKEN_ADCKEN_CLEAR; - } - TSB_CG->SPCLKEN = tmp; -} - -/** @} */ -/* End of group CG_Exported_Functions */ - -/** @} */ -/* End of group CG */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_CG_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c deleted file mode 100644 index ab2ec589a6..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c +++ /dev/null @@ -1,696 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_gpio.c - * @brief This file provides API functions for GPIO driver. - * @version V2.0.2.1 - * @date 2015/09/08 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_gpio.h" - -#if defined(__TMPM066_GPIO_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -#define GPIO_NUM (9U) /*total number of gpio */ -/** - * @brief the base address of GPIO port. - */ -const uint32_t GPIO_Base[GPIO_NUM] = { - TSB_PA_BASE, TSB_PB_BASE, TSB_PC_BASE, - TSB_PD_BASE, TSB_PE_BASE, TSB_PF_BASE, - TSB_PG_BASE, TSB_PH_BASE, TSB_PJ_BASE -}; - -/** - * @brief:Information of gpio port. - * Note: for bit0 to bit7 of each member below, its value '0' or '1' has the means: - * '0': that bit is not available - * '1': that bit is availabe - * For example, if DATA = 0x7F, it mean the bit0 to bit6 of DATA register are avaiable; -*/ -const GPIO_RegTypeDef GPIO_SFRs[GPIO_NUM] = { -/* DATA CR FR1 FR2 OD PUP PDN SEL IE */ -/* PA */ {0xFFU, 0xFFU, {0x80U, 0x00U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU}, -/* PB */ {0x0FU, 0x0FU, {0x00U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU}, -/* PC */ {0x3FU, 0x3FU, {0x3FU, 0x00U}, 0x3FU, 0x3FU, 0x3FU, 0x03U, 0x3FU}, -/* PD */ {0x3FU, 0x3FU, {0x1FU, 0x0FU}, 0x3FU, 0x3FU, 0x3FU, 0x30U, 0x3FU}, -/* PE */ {0x3FU, 0x3FU, {0x3FU, 0x02U}, 0x3FU, 0x3FU, 0x3FU, 0x00U, 0x3FU}, -/* PF */ {0xFFU, 0xFFU, {0x3FU, 0x01U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU}, -/* PG */ {0x03U, 0x03U, {0x03U, 0x00U}, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U}, -/* PH */ {0x0FU, 0x0FU, {0x0FU, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU}, -/* PJ */ {0x0FU, 0x0FU, {0x03U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x0FU, 0x0FU} -}; - -/** @defgroup GPIO_Exported_Functions - * @{ - */ - -/** - * @brief Read GPIO Data register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @retval Data:The value of DATA register. - */ -uint8_t GPIO_ReadData(GPIO_Port GPIO_x) -{ - uint8_t Data = 0U; - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - Data = (uint8_t) PORT->DATA; - return Data; -} - -/** - * @brief Read Bit of GPIO Data register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7. - * @retval BitValue:The value of specified Bit. - * This parameter can be one of the following values: - * GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1 - */ -uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x) -{ - uint8_t Data = 0U; - uint8_t tmp = 0U; - uint8_t BitValue = 0U; - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_GPIO_BIT(Bit_x)); - assert_param(IS_GPIO_BIT_DATA(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - Data = (uint8_t) PORT->DATA; - tmp = (uint8_t) (Data & Bit_x); - if (tmp) { - BitValue = GPIO_BIT_VALUE_1; - } else { - BitValue = GPIO_BIT_VALUE_0; - } - return (BitValue); - -} - -/** - * @brief Write specified value to GPIO DATA register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Data: specified value will be written to GPIO DATA register. - * @retval None - */ -void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data) -{ - - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_GPIO_WRITE(GPIO_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - PORT->DATA = Data; - -} - -/** - * @brief Write to specified Bit of GPIO DATA register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin,which can set as output. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param BitValue:The value of specified Bit. - * This parameter can be one of the following values: - * GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1 - * @retval None - */ -void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue) -{ - uint8_t tmp = 0U; - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_GPIO_BIT_VALUE(BitValue)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinCR; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - tmp = GPIO_ReadData(GPIO_x); - if (BitValue) { - tmp |= Bit_x; - } else { - Bit_x = (~Bit_x); - tmp &= Bit_x; - } - PORT->DATA = tmp; -} - -/** - * @brief Initialize the specified GPIO pin. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param GPIO_InitStruct: The structure containing basic GPIO configuration. - * @retval None - */ -void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct) -{ - uint8_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_POINTER_NOT_NULL(GPIO_InitStruct)); - assert_param(IS_GPIO_IO_MODE_STATE(GPIO_InitStruct->IOMode)); - assert_param(IS_GPIO_PULLUP_STATE(GPIO_InitStruct->PullUp)); - assert_param(IS_GPIO_PULLDOWN_STATE(GPIO_InitStruct->PullDown)); - assert_param(IS_GPIO_OPEN_DRAIN_STATE(GPIO_InitStruct->OpenDrain)); - - if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) { - assert_param(IS_GPIO_INPUT_VOLTAGE_STATE(GPIO_InitStruct->InputVoltage)); - } - tmp = GPIO_InitStruct->IOMode; - switch (tmp) { - case GPIO_INPUT_MODE: - GPIO_SetInput(GPIO_x, Bit_x); - break; - case GPIO_OUTPUT_MODE: - GPIO_SetOutput(GPIO_x, Bit_x); - break; - default: - /* Do nothing */ - break; - } - tmp = GPIO_InitStruct->PullUp; - switch (tmp) { - case GPIO_PULLUP_ENABLE: - GPIO_SetPullUp(GPIO_x, Bit_x, ENABLE); - break; - case GPIO_PULLUP_DISABLE: - GPIO_SetPullUp(GPIO_x, Bit_x, DISABLE); - break; - default: - /* Do nothing */ - break; - } - tmp = GPIO_InitStruct->PullDown; - switch (tmp) { - case GPIO_PULLDOWN_ENABLE: - GPIO_SetPullDown(GPIO_x, Bit_x, ENABLE); - break; - case GPIO_PULLDOWN_DISABLE: - GPIO_SetPullDown(GPIO_x, Bit_x, DISABLE); - break; - default: - /* Do nothing */ - break; - } - tmp = GPIO_InitStruct->OpenDrain; - switch (tmp) { - case GPIO_OPEN_DRAIN_ENABLE: - GPIO_SetOpenDrain(GPIO_x, Bit_x, ENABLE); - break; - case GPIO_OPEN_DRAIN_DISABLE: - GPIO_SetOpenDrain(GPIO_x, Bit_x, DISABLE); - break; - default: - /* Do nothing */ - break; - } - if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) { - tmp = GPIO_InitStruct->InputVoltage; - switch (tmp) { - case GPIO_INPUT_VOLTAGE_3V: - GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_0); - break; - case GPIO_INPUT_VOLTAGE_1V8: - GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_1); - break; - default: - /* Do nothing */ - break; - } - } -} - -/** - * @brief Set specified GPIO Pin as output port. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @retval None - */ -void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x) -{ - uint8_t tmp = 0U; - uint32_t i; - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinCR; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - tmp = (~Bit_x); - for (i = 0U; i < FRMAX; i++) { - if (GPIO_SFRs[GPIO_x].PinFR[i]) { - PORT->FR[i] &= tmp; - } else { - /* Do nothing */ - } - } - if (GPIO_SFRs[GPIO_x].PinIE) { - PORT->IE &= tmp; - } else { - /* Do nothing */ - } - PORT->CR |= Bit_x; -} - -/** - * @brief Set specified GPIO Pin as input port. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @retval None - */ -void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x) -{ - uint8_t tmp = 0U; - uint32_t i; - TSB_Port_TypeDef *PORT = 0U; - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinIE; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - tmp = (~Bit_x); - for (i = 0U; i < FRMAX; i++) { - if (GPIO_SFRs[GPIO_x].PinFR[i]) { - PORT->FR[i] &= tmp; - } else { - /* Do nothing */ - } - } - if (GPIO_SFRs[GPIO_x].PinCR) { - PORT->CR &= tmp; - } else { - /* Do nothing */ - } - PORT->IE |= Bit_x; - -} - -/** - * @brief Set or clear the bit setting in output control register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param NewState: The output state of the pin. - * This parameter can be one of the following values: - * ENABLE , DISABLE. - * @retval None - */ -void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) -{ - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinCR; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - if (NewState == ENABLE) { - PORT->CR |= Bit_x; - } else { - PORT->CR &= (~(uint32_t) Bit_x); - } - -} - -/** - * @brief Set or clear the bit setting in input control register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param NewState: The input state of the pin. - * This parameter can be one of the following values: - * ENABLE , DISABLE. - * @retval None - */ -void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) -{ - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinIE; - } else { - /* Do nothing */ - } - - /* Check the parameters */ - assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x)); - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - - if (NewState == ENABLE) { - PORT->IE |= Bit_x; - } else { - PORT->IE &= (~(uint32_t) Bit_x); - } -} - -/** - * @brief Enable or Disable pull-up function of specified GPIO Pin. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param NewState: New state of the Pull-Up function. - * This parameter can be one of the following values: - * ENABLE , DISABLE. - * @retval None - */ -void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) -{ - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinPUP; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_PUP(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - - if (NewState == ENABLE) { - PORT->PUP |= Bit_x; - } else { - PORT->PUP &= (~(uint32_t) Bit_x); - } -} - -/** - * @brief Enable or Disable pull-down function of specified GPIO Pin. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param NewState: New state of the Pull-Down function. - * This parameter can be one of the following values: - * ENABLE , DISABLE. - * @retval None - */ -void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) -{ - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinPDN; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_PDN(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - - if (NewState == ENABLE) { - PORT->PDN |= Bit_x; - } else { - PORT->PDN &= (~(uint32_t) Bit_x); - } -} - -/** - * @brief Set specified GPIO Pin as open drain port or CMOS port. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param NewState: New state of the Open Drian function. - * This parameter can be one of the following values: - * ENABLE , DISABLE. - * @retval None - */ -void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) -{ - - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinOD; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_OD(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - - if (NewState == ENABLE) { - PORT->OD |= Bit_x; - } else { - PORT->OD &= (~(uint32_t) Bit_x); - } -} - -/** - * @brief Input voltage selection function of specified GPIO Pin. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PC, GPIO_PD, GPIO_PG. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @param BitValue:The value of specified Bit. - * This parameter can be one of the following values: - * GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1 - * @retval None - */ -void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue) -{ - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT_INPUT_VOLTAGE(GPIO_x)); - assert_param(IS_GPIO_BIT_VALUE(BitValue)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinSEL; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_SEL(GPIO_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - - if (BitValue) { - PORT->SEL |= Bit_x; - } else { - PORT->SEL &= (~(uint8_t) Bit_x); - } -} - -/** - * @brief Enable specified GPIO Function register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param FuncReg_x: Select Function register of GPIO. - * This parameter can be one of the following values: - * GPIO_FUNC_REG_1, GPIO_FUNC_REG_2. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @retval None - */ -void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x) -{ - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x]; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - PORT->FR[FuncReg_x] |= Bit_x; -} - -/** - * @brief Disable specified GPIO Function register. - * @param GPIO_x: Select GPIO port. - * This parameter can be one of the following values: - * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, - * GPIO_PH, GPIO_PJ. - * @param FuncReg_x: Select Function register of GPIO. - * This parameter can be one of the following values: - * GPIO_FUNC_REG_1, GPIO_FUNC_REG_2. - * @param Bit_x: Select GPIO pin. - * This parameter can be one of the following values: - * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, - * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, - * or combination of the effective bits. - * @retval None - */ -void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x) -{ - TSB_Port_TypeDef *PORT = 0U; - - /* Check the parameters */ - assert_param(IS_GPIO_PORT(GPIO_x)); - assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x)); - - if (Bit_x == GPIO_BIT_ALL) { - Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x]; - } else { - /* Do nothing */ - } - /* Check the parameters */ - assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x)); - - PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; - - PORT->FR[FuncReg_x] &= (~(uint32_t) Bit_x); -} - -/** @} */ -/* End of group GPIO_Exported_Functions */ -/** @} */ -/* End of group GPIO */ -/** @} */ -/* End of group TX00_Periph_Driver */ -#endif /* (__TMPM066_GPIO_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c deleted file mode 100644 index 2a90f4a30f..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c +++ /dev/null @@ -1,931 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_i2c.c - * @brief This file provides API functions for I2C driver. - * @version V2.0.2.1 - * @date 2015/09/10 - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_i2c.h" - -#if defined(__TMPM066_I2C_H) - -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/** @defgroup I2C_Private_Defines - * @{ - */ - -#define I2CCR1_BC_MASK ((uint32_t)0x0000001F) -#define I2CCR1_ACK_SET ((uint32_t)0x00000010) -#define I2CCR1_ACK_CLEAR ((uint32_t)0x000000EF) -#define I2CCR1_SCK_MASK ((uint32_t)0x000000F8) -#define I2CCR1_NOACK_MASK ((uint32_t)0x00000008) -#define I2CCR1_NOACK_ENABLE ((uint32_t)0x00000000) - -#define I2CCR2_PIN_SET ((uint32_t)0x00000010) -#define I2CCR2_I2CM_I2C ((uint32_t)0x00000008) -#define I2CCR2_SWRST_MASK ((uint32_t)0xFFFFFFFC) -#define I2CCR2_SWRST_CMD1 ((uint32_t)0x00000002) -#define I2CCR2_SWRST_CMD2 ((uint32_t)0x00000001) -#define I2CCR2_START_CONDITION ((uint32_t)0x000000F0) -#define I2CCR2_STOP_CONDITION ((uint32_t)0x000000D0) - - -#define I2CAR_SA_MASK ((uint32_t)0x000000FE) -#define I2CAR_ALS_SET ((uint32_t)0x00000001) -#define I2CAR_ALS_CLEAR ((uint32_t)0xFFFFFFFE) -#define I2C_DATA_MASK ((uint32_t)0x000000FF) - -#define I2CIE_IE_SELPINCD_SET ((uint32_t)0x00000040) -#define I2CIE_IE_DMARI2CTX_SET ((uint32_t)0x00000020) -#define I2CIE_IE_DMARI2CRX_SET ((uint32_t)0x00000010) -#define I2CIE_IE_INTNACK_SET ((uint32_t)0x00000008) -#define I2CIE_IE_INTI2CBF_SET ((uint32_t)0x00000004) -#define I2CIE_IE_INTI2CAL_SET ((uint32_t)0x00000002) -#define I2CIE_IE_INTI2C_SET ((uint32_t)0x00000001) - - -#define I2CIE_IE_SELPINCD_CLEAR ((uint32_t)0xFFFFFFBF) -#define I2CIE_IE_DMARI2CTX_CLEAR ((uint32_t)0xFFFFFFDF) -#define I2CIE_IE_DMARI2CRX_CLEAR ((uint32_t)0xFFFFFFEF) -#define I2CIE_IE_INTNACK_CLEAR ((uint32_t)0xFFFFFFF7) -#define I2CIE_IE_INTI2CBF_CLEAR ((uint32_t)0xFFFFFFFB) -#define I2CIE_IE_INTI2CAL_CLEAR ((uint32_t)0xFFFFFFFD) -#define I2CIE_IE_NTI2C_CLEAR ((uint32_t)0xFFFFFFFE) - -#define I2CST_NACK_MASK ((uint32_t)0x00000008) -#define I2CST_I2CBF_MASK ((uint32_t)0x00000004) -#define I2CST_I2CAL_MASK ((uint32_t)0x00000002) -#define I2CST_I2C_MASK ((uint32_t)0x00000001) - -#define I2CST_NACK_SET ((uint32_t)0x00000008) -#define I2CST_I2CBF_SET ((uint32_t)0x00000004) -#define I2CST_I2CAL_SET ((uint32_t)0x00000002) -#define I2CST_I2C_SET ((uint32_t)0x00000001) - -#define I2COP_GCDI_ON ((uint32_t)0x000000FB) -#define I2COP_GCDI_OFF ((uint32_t)0x00000004) - -#define I2COP_RSTA_SET ((uint32_t)0x00000008) -#define I2COP_RSTA_CLEAR ((uint32_t)0xFFFFFFF7) - -#define I2COP_MFACK_NACK ((uint32_t)0x00000001) -#define I2COP_MFACK_ACK ((uint32_t)0xFFFFFFFE) - -#define I2COP_SREN_SET ((uint32_t)0x00000002) -#define I2COP_SREN_CLEAR ((uint32_t)0xFFFFFFFD) - -#define I2CAR2_SA2EN_USE ((uint32_t)0x00000001) -#define I2CAR2_SA2EN_NOUSE ((uint32_t)0x000000FE) - -/** @} */ -/* End of group I2C_Private_Defines */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ - -/** - * @brief Enable or disable the generation of ACK clock. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: New state of ACK clock. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = I2Cx->CR1; - if (NewState == ENABLE) { - /* Set I2CxCR1 to enable generation of ACK clock */ - tmp |= I2CCR1_ACK_SET; - } else { - /* Clear I2CxCR1 to disable generation of ACK clock */ - tmp &= I2CCR1_ACK_CLEAR; - } - I2Cx->CR1 = tmp; - -} - -/** - * @brief Initialize the specified I2C channel in I2C mode. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param InitI2CStruct: The structure containing I2C in I2C mode configuration. - * @retval None - */ -void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_POINTER_NOT_NULL(InitI2CStruct)); - assert_param(IS_I2C_ADDR(InitI2CStruct->I2CSelfAddr)); - assert_param(IS_I2C_BIT_NUM(InitI2CStruct->I2CDataLen)); - assert_param(IS_I2C_SCK_CLK_DIV(InitI2CStruct->I2CClkDiv)); - assert_param(IS_FUNCTIONAL_STATE(InitI2CStruct->I2CACKState)); - - /* Get the system clock frequency */ - SystemCoreClockUpdate(); - - /* Check the prescaler clock in the range between 50ns and 150ns */ - assert_param(IS_PRESCALER_CLK_VALID(InitI2CStruct->PrescalerClkDiv, SystemCoreClock)); - - /* Set prescaler clock */ - I2Cx->PRS = InitI2CStruct->PrescalerClkDiv % I2C_PRESCALER_DIV_32; - - /* Set selfaddress for I2Cx */ - I2Cx->AR = InitI2CStruct->I2CSelfAddr & I2CAR_SA_MASK; - - /* Set I2C bit length of transfer data */ - tmp = I2Cx->CR1 & I2CCR1_BC_MASK; - tmp |= (InitI2CStruct->I2CDataLen << 5U); - /* Set I2C clock division */ - tmp &= I2CCR1_SCK_MASK; - tmp |= InitI2CStruct->I2CClkDiv; - if (InitI2CStruct->I2CACKState) { - /* Set I2CxCR1 to enable generation of ACK clock */ - tmp |= I2CCR1_ACK_SET; - } else { - /* Clear I2CxCR1 to disable generation of ACK clock */ - tmp &= I2CCR1_ACK_CLEAR; - } - I2Cx->CR1 = tmp; - - /* Intilize I2C to I2C Slave-Rx mode */ - I2Cx->CR2 = I2CCR2_PIN_SET | I2CCR2_I2CM_I2C; -} - -/** - * @brief Specify the number of bits per transfer. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param I2CBitNum: Specify the number of bits. - * This parameter can be one of the following values: - * I2C_DATA_LEN_8, I2C_DATA_LEN_1,I2C_DATA_LEN_2,I2C_DATA_LEN_3, - * I2C_DATA_LEN_4, I2C_DATA_LEN_5,I2C_DATA_LEN_6 and I2C_DATA_LEN_7. - * @retval None - */ -void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_I2C_BIT_NUM(I2CBitNum)); - - /* Write number of bits per transfer into I2CxCR1 */ - tmp = I2Cx->CR1 & I2CCR1_BC_MASK; - tmp |= ((uint32_t) I2CBitNum << 5U); - - I2Cx->CR1 = tmp; -} - -/** - * @brief Reset the state of the specified I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_SWReset(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->CR2 & I2CCR2_SWRST_MASK; - I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD1; - I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD2; -} - -/** - * @brief Clear I2C interrupt request in I2C mode. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Set I2CxCR2 to clear request, and Set I2CxCR2 to enable I2C operation */ - tmp = I2Cx->SR; - tmp &= (uint32_t) 0x000000E0; - tmp |= (I2CCR2_PIN_SET | I2CCR2_I2CM_I2C); - I2Cx->CR2 = tmp; -} - -/** - * @brief Set I2c bus to Master mode and Generate start condition in I2C mode. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Set I2CxCR2, , and to generate start condition */ - I2Cx->CR2 = I2CCR2_START_CONDITION | I2CCR2_I2CM_I2C; -} - -/** - * @brief Set I2c bus to Master mode and Generate stop condition in I2C mode. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Set I2CxCR2, , and clear to generate stop condition */ - I2Cx->CR2 = I2CCR2_STOP_CONDITION | I2CCR2_I2CM_I2C; -} - -/** - * @brief Get the I2C channel state in I2C mode - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval The state of the I2C channel in I2C bus. - */ -I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx) -{ - I2C_State state; - state.All = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - state.All = I2Cx->SR; - state.All &= I2C_DATA_MASK; - return state; -} - - -/** - * @brief Set data to be sent and MCU starts transmission. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param Data: The data to be sent, max 0xFF. - * @retval None - */ -void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_I2C_DATA(Data)); - - /* Write data into I2CxDBR */ - I2Cx->DBR = Data; -} - -/** - * @brief Get data having been received. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval The data having been received - */ -uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t retval = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Save the received data */ - retval = I2Cx->DBR; - retval &= I2C_DATA_MASK; - - return retval; -} - -/** - * @brief Enable or disable I2C free data mode of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: New state of free data mode. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxI2CAR to use free data mode transfer in I2C mode */ - I2Cx->AR |= I2CAR_ALS_SET; - } else { - /* Clear I2CxI2CAR to not use free data mode transfer in I2C mode */ - I2Cx->AR &= I2CAR_ALS_CLEAR; - } -} - -/** - * @brief Get slave address match detection state. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval DISABLE or ENABLE. - */ -FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - FunctionalState retval = DISABLE; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->CR1 & I2CCR1_NOACK_MASK; - if (tmp == I2CCR1_NOACK_ENABLE) { - /* the slave address match or general call detection are enabled. */ - retval = ENABLE; - } else { - /* Do nothing */ - } - return retval; -} - -/** - * @brief Set prescaler clock of the specified I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param PrescalerClock: the prescaler clock value. - * This parameter can be one of the following values: - * I2C_PRESCALER_DIV_1 to I2C_PRESCALER_DIV_32 - * @retval None - */ -void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Get the system clock frequency */ - SystemCoreClockUpdate(); - - /* Check the prescaler clock in the range between 50ns and 150ns */ - assert_param(IS_PRESCALER_CLK_VALID(PrescalerClock, SystemCoreClock)); - - /* Write prescaler clock into I2CxPRS */ - I2Cx->PRS = PrescalerClock % I2C_PRESCALER_DIV_32; -} - -/** - * @brief Enable or disable open condition of the pin. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: Specify I2C interrupt setting. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxIE to enable pin open by reading DBR */ - I2Cx->IE |= I2CIE_IE_SELPINCD_SET; - } else { - /* Clear I2CxIE to disable pin open by reading DBR */ - I2Cx->IE &= I2CIE_IE_SELPINCD_CLEAR; - } -} - - -/** - * @brief Enable or disable a DMAC transmisstion request output. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: Specify I2C interrupt setting. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxIE to enable a DMAC transmisstion request */ - I2Cx->IE |= I2CIE_IE_DMARI2CTX_SET; - } else { - /* Clear I2CxIE to disable a DMAC transmisstion request */ - I2Cx->IE &= I2CIE_IE_DMARI2CTX_CLEAR; - } -} - -/** - * @brief Enable or disable a DMAC reception request output. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: Specify I2C interrupt setting. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxIE to enable a DMAC reception request */ - I2Cx->IE |= I2CIE_IE_DMARI2CRX_SET; - } else { - /* Clear I2CxIE to disable a DMAC reception request */ - I2Cx->IE &= I2CIE_IE_DMARI2CRX_CLEAR; - } -} - -/** - * @brief Enable or disable NACK detection interrupt of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: Specify I2C interrupt setting. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxIE to enable NACK detection interrupt */ - I2Cx->IE |= I2CIE_IE_INTNACK_SET; - } else { - /* Clear I2CxIE to disable NACK detection interrupt */ - I2Cx->IE &= I2CIE_IE_INTNACK_CLEAR; - } -} - -/** - * @brief Enable or disable bus-free interrupt of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: Specify I2C interrupt setting. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxIE to enable bus-free interrupt */ - I2Cx->IE |= I2CIE_IE_INTI2CBF_SET; - } else { - /* Clear I2CxIE to disable bus-free interrupt */ - I2Cx->IE &= I2CIE_IE_INTI2CBF_CLEAR; - } -} - -/** - * @brief Enable or disable AL interrupt of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: Specify I2C interrupt setting. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxIE to enable AL interrupt */ - I2Cx->IE |= I2CIE_IE_INTI2CAL_SET; - } else { - /* Clear I2CxIE to disable AL interrupt */ - I2Cx->IE &= I2CIE_IE_INTI2CAL_CLEAR; - } -} - -/** - * @brief Enable or disable I2C interrupt request of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: Specify I2C interrupt setting. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxIE to enable I2C interrupt request */ - I2Cx->IE |= I2CIE_IE_INTI2C_SET; - } else { - /* Clear I2CxIE to disable I2C interrupt request */ - I2Cx->IE &= I2CIE_IE_NTI2C_CLEAR; - } -} - -/** - * @brief Get NACK interrupt generation state. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval DISABLE or ENABLE. - */ -FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - FunctionalState retval = DISABLE; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->ST & I2CST_NACK_MASK; - if (tmp == I2CST_NACK_SET) { - /* the NACK interrupt has been generated */ - retval = ENABLE; - } else { - /* Do nothing */ - } - return retval; -} - -/** - * @brief Get I2CBF interrupt generation state. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval DISABLE or ENABLE. - */ -FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - FunctionalState retval = DISABLE; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->ST & I2CST_I2CBF_MASK; - if (tmp == I2CST_I2CBF_SET) { - /* the I2CBF interrupt has been generated */ - retval = ENABLE; - } else { - /* Do nothing */ - } - return retval; -} - -/** - * @brief Get I2CAL interrupt generation state. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval DISABLE or ENABLE. - */ -FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - FunctionalState retval = DISABLE; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->ST & I2CST_I2CAL_MASK; - if (tmp == I2CST_I2CAL_SET) { - /* the I2CAL interrupt has been generated */ - retval = ENABLE; - } else { - /* Do nothing */ - } - return retval; -} - -/** - * @brief Get I2C interrupt generation state. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval DISABLE or ENABLE. - */ -FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - FunctionalState retval = DISABLE; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->ST & I2CST_I2C_MASK; - if (tmp == I2CST_I2C_SET) { - /* the I2C interrupt has been generated */ - retval = ENABLE; - } else { - /* Do nothing */ - } - return retval; -} - -/** - * @brief Clear the NACK interrupt output. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Set I2CxST to clear the NACK interrupt output(INTI2Cx) */ - I2Cx->ST = I2CST_NACK_SET; -} - -/** - * @brief Clear the I2CBF interrupt output. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Set I2CxST to clear the I2CBF interrupt output(INTI2Cx) */ - I2Cx->ST = I2CST_I2CBF_SET; -} - -/** - * @brief Clear the I2CAL interrupt output. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Set I2CxST to clear the I2CAL interrupt output(INTI2Cx) */ - I2Cx->ST = I2CST_I2CAL_SET; -} - -/** - * @brief Clear the I2C interrupt output. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval None - */ -void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - /* Set I2CxST to clear the I2C interrupt output(INTI2Cx) */ - I2Cx->ST = I2CST_I2C_SET; -} - -/** - * @brief Enable or disable general-call detection. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: New state of general call detection. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = I2Cx->OP; - if (NewState == ENABLE) { - /* Clear I2CxOP, general-call detection is ON */ - tmp &= I2COP_GCDI_ON; - } else { - /* Set I2CxOP, general-call detection is OFF */ - tmp |= I2COP_GCDI_OFF; - } - I2Cx->OP = tmp; - -} - -/** - * @brief Detect or not a repeated start of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: New state of free data mode. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxI2COP to detect a repeated start */ - I2Cx->OP |= I2COP_RSTA_SET; - } else { - /* Clear I2CxI2COP to not detect a repeated start */ - I2Cx->OP &= I2COP_RSTA_CLEAR; - } -} - -/** - * @brief Get repeated start detection state. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval DISABLE or ENABLE. - */ -FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - FunctionalState retval = DISABLE; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->OP & I2COP_RSTA_SET; - if (tmp == I2COP_RSTA_SET) { - /* the repeated start detection are enabled. */ - retval = ENABLE; - } else { - /* Do nothing */ - } - return retval; -} - -/** - * @brief Select an ACK output of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: New state of free data mode. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxI2COP to select NACK output */ - I2Cx->OP |= I2COP_MFACK_NACK; - } else { - /* Clear I2CxI2COP to select ACK output */ - I2Cx->OP &= I2COP_MFACK_ACK; - } -} - -/** - * @brief Enable or disable repeat start of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: New state of free data mode. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxI2COP to enable repeat start output */ - I2Cx->OP |= I2COP_SREN_SET; - } else { - /* Clear I2CxI2COP to disable repeat start output */ - I2Cx->OP &= I2COP_SREN_CLEAR; - } -} - -/** - * @brief Get repeated start state. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @retval BUSY or DONE. - */ -WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx) -{ - uint32_t tmp = 0U; - WorkState retval = BUSY; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - - tmp = I2Cx->OP & I2COP_SREN_SET; - if (tmp == I2COP_SREN_SET) { - /* the repeated start detection has completed. */ - retval = DONE; - } else { - /* Do nothing */ - } - return retval; -} - -/** - * @brief Enable or disable using 2nd slave address of the I2C channel. - * @param I2Cx: Select the I2C channel. - * This parameter can be one of the following values: - * TSB_I2C0,TSB_I2C1 - * @param NewState: New state of free data mode. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void I2C_Set2ndSlaveAddress(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set I2CxI2CAR2 to using 2nd slave address */ - I2Cx->AR2 |= I2CAR2_SA2EN_USE; - } else { - /* Clear I2CxI2CAR2 to not using 2nd slave address */ - I2Cx->AR2 &= I2CAR2_SA2EN_NOUSE; - } -} - -/** @} */ -/* End of group I2C_Exported_Functions */ - -/** @} */ -/* End of group I2C */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_I2C_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c deleted file mode 100644 index 99199dcb12..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c +++ /dev/null @@ -1,284 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_intifao.c - * @brief This file provides API functions for INTIFAO driver - * @version V2.0.2.2 - * @date 2016/02/15 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_intifao.h" - -#if defined(__TMPM066_INTIFAO_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup INTIFAO - * @brief INTIFAO driver modules - * @{ - */ - -/** @defgroup INTIFAO_Private_Defines - * @{ - */ -#define INT_NCLR_PCLR_CLEAR ((uint8_t)0x01) -#define INT_EN_MODE_MASK ((uint8_t)0xF0) -#define INT_MODE_MASK ((uint8_t)0x0E) - -#define INTIFAO_INTFLAG1_MASK ((uint32_t)0xFFFFFF00) - -/** @} */ -/* End of group INTIFAO_Private_Defines */ - -/** @defgroup INTIFAO_Private_FunctionPrototypes - * @{ - */ - -/** @} */ -/* End of group INTIFAO_Private_FunctionPrototypes */ - -/** @defgroup INTIFAO_Private_Functions - * @{ - */ - -/** @} */ -/* End of group INTIFAO_Private_Functions */ - -/** @defgroup INTIFAO_Exported_Functions - * @{ - */ - -/** - * @brief Setup the INT source for releasing low power mode. - * @param INTSource: Select the release INT source - * This parameter can be one of the following values: - * INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3, - * INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP. - * @param ActiveState: select the active state for release trigger - * This parameter can be one of the following values: - * INTIFAO_INT_ACTIVE_STATE_L, - * INTIFAO_INT_ACTIVE_STATE_H, - * INTIFAO_INT_ACTIVE_STATE_FALLING, - * INTIFAO_INT_ACTIVE_STATE_RISING or - * INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES. - * @param NewState: Enable or disable this release trigger - * This parameter can be one of the following values: - * DISABLE or ENABLE - * @retval None - */ -void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource, - INTIFAO_INTActiveState ActiveState, FunctionalState NewState) -{ - uint8_t num = 0U; - uint32_t regval; - - /* Check the parameters */ - assert_param(IS_INTIFAO_INT_SRC(INTSource)); - assert_param(IS_INTIFAO_INT_ACTIVE_STATE(ActiveState)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if ((INTSource == INTIFAO_INT_SRC_I2CS) || (INTSource == INTIFAO_INT_SRC_USBWKUP)) { - assert_param(IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(ActiveState)); - } else { - /* Do nothing */ - } - - num = (uint32_t) INTSource; - - switch (num) { - case 0U: /* STOP2INT_032 */ - regval = TSB_INTIFAO ->STOP2INT_032; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_032 = regval; - break; - case 1U: /* STOP2INT_033 */ - regval = TSB_INTIFAO ->STOP2INT_033; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_033 = regval; - break; - case 2U: /* STOP2INT_034 */ - regval = TSB_INTIFAO ->STOP2INT_034; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_034 = regval; - break; - case 3U: /* STOP2INT_035 */ - regval = TSB_INTIFAO ->STOP2INT_035; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_035 = regval; - break; - case 4U: /* STOP2INT_036 */ - regval = TSB_INTIFAO ->STOP2INT_036; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_036 = regval; - break; - case 5U: /* STOP2INT_037 */ - regval = TSB_INTIFAO ->STOP2INT_037; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_037 = regval; - break; - case 6U: /* STOP2INT_038 */ - regval = TSB_INTIFAO ->STOP2INT_038; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_038 = regval; - break; - case 7U: /* STOP2INT_039 */ - regval = TSB_INTIFAO ->STOP2INT_039; - regval &= INT_EN_MODE_MASK; - regval |= NewState; - regval |= ActiveState << 1; - TSB_INTIFAO ->STOP2INT_039 = regval; - break; - default: - /* Do nothing */ - break; - } -} - -/** - * @brief Get the active state of INT source standby clear request - * @param INTSource: Select the release INT source - * This parameter can be one of the following values: - * INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3, - * INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP. - * @retval Active state of the input INT - * The value returned can be one of the following values: - * INTIFAO_INT_ACTIVE_STATE_FALLING, INTIFAO_INT_ACTIVE_STATE_RISING, - * INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES or INTIFAO_INT_ACTIVE_STATE_INVALID - */ -INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource) -{ - INTIFAO_INTActiveState int_active_state = INTIFAO_INT_ACTIVE_STATE_INVALID; - uint8_t tmp = 0U; - uint8_t num = 0U; - uint8_t regval[8] = {0}; - - /* Check the parameters */ - assert_param(IS_INTIFAO_INT_SRC(INTSource)); - - regval[0] = TSB_INTIFAO ->STOP2INT_032 & INT_MODE_MASK; - regval[1] = TSB_INTIFAO ->STOP2INT_033 & INT_MODE_MASK; - regval[2] = TSB_INTIFAO ->STOP2INT_034 & INT_MODE_MASK; - regval[3] = TSB_INTIFAO ->STOP2INT_035 & INT_MODE_MASK; - regval[4] = TSB_INTIFAO ->STOP2INT_036 & INT_MODE_MASK; - regval[5] = TSB_INTIFAO ->STOP2INT_037 & INT_MODE_MASK; - regval[6] = TSB_INTIFAO ->STOP2INT_038 & INT_MODE_MASK; - regval[7] = TSB_INTIFAO ->STOP2INT_039 & INT_MODE_MASK; - - num = (uint32_t) INTSource; - tmp = regval[num]; - tmp = tmp >>1; - switch (tmp) { - case 3U: - int_active_state = INTIFAO_INT_ACTIVE_STATE_RISING; - break; - case 2U: - int_active_state = INTIFAO_INT_ACTIVE_STATE_FALLING; - break; - case 4U: - int_active_state = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES; - break; - default: - /* Do nothing */ - break; - } - - return (int_active_state); -} - -/** - * @brief Clears the input INT request. - * @param INTSource: Select the release INT source - * This parameter can be one of the following values: - * INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3, - * INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP. - * @retval None - */ -void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource) -{ - uint8_t num = 0U; - - /* Check the parameters */ - assert_param(IS_INTIFAO_INT_SRC(INTSource)); - - num = (uint32_t) INTSource; - switch (num) { - case 0U: /* STOP2INT_032 */ - TSB_INTIFAO_STOP2INT_032_INT032PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_032_INT032NCLR = INT_NCLR_PCLR_CLEAR; - break; - case 1U: /* STOP2INT_033 */ - TSB_INTIFAO_STOP2INT_033_INT033PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_033_INT033NCLR = INT_NCLR_PCLR_CLEAR; - break; - case 2U: /* STOP2INT_034 */ - TSB_INTIFAO_STOP2INT_034_INT034PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_034_INT034NCLR = INT_NCLR_PCLR_CLEAR; - break; - case 3U: /* STOP2INT_035 */ - TSB_INTIFAO_STOP2INT_035_INT035PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_035_INT035NCLR = INT_NCLR_PCLR_CLEAR; - break; - case 4U: /* STOP2INT_036 */ - TSB_INTIFAO_STOP2INT_036_INT036PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_036_INT036NCLR = INT_NCLR_PCLR_CLEAR; - break; - case 5U: /* STOP2INT_037 */ - TSB_INTIFAO_STOP2INT_037_INT037PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_037_INT037NCLR = INT_NCLR_PCLR_CLEAR; - break; - case 6U: /* STOP2INT_038 */ - TSB_INTIFAO_STOP2INT_038_INT038PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_038_INT038NCLR = INT_NCLR_PCLR_CLEAR; - break; - case 7U: /* STOP2INT_039 */ - TSB_INTIFAO_STOP2INT_039_INT039PCLR = INT_NCLR_PCLR_CLEAR; - TSB_INTIFAO_STOP2INT_039_INT039NCLR = INT_NCLR_PCLR_CLEAR; - break; - default: - /* Do nothing */ - break; - } -} - -/** - * @brief Get the INTFLAG1. - * @param None - * @retval INTFLAG1 flag - */ -INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void) -{ - INTIFAO_IntFlag1Factor intifao_intflag1_factor = { 0U }; - - intifao_intflag1_factor.All = TSB_INTIFSD->FLAG1 & (~INTIFAO_INTFLAG1_MASK); - - return intifao_intflag1_factor; -} - -/** @} */ -/* End of group INTIFAO_Exported_Functions */ - -/** @} */ -/* End of group INTIFAO */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_INTIFAO_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c deleted file mode 100644 index 6cd8329acd..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c +++ /dev/null @@ -1,368 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_intifsd.c - * @brief This file provides API functions for INTIFSD driver - * @version V2.0.2.1 - * @date 2015/10/19 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_intifsd.h" - -#if defined(__TMPM066_INTIFSD_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup INTIFSD - * @brief INTIFSD driver modules - * @{ - */ - -/** @defgroup INTIFSD_Private_Defines - * @{ - */ -#define INTIFSD_NMIFLG_MASK ((uint32_t)0xFFF8FFFF) - -#define INTIFSD_INTFLAG4_MASK ((uint32_t)0xE0000000) -#define INTIFSD_INTFLAG5_MASK ((uint32_t)0xFFFFFC00) - -/** @} */ -/* End of group INTIFSD_Private_Defines */ - -/** @defgroup INTIFSD_Private_FunctionPrototypes - * @{ - */ - -/** @} */ -/* End of group INTIFSD_Private_FunctionPrototypes */ - -/** @defgroup INTIFSD_Private_Functions - * @{ - */ - -/** @} */ -/* End of group INTIFSD_Private_Functions */ - -/** @defgroup INTIFSD_Exported_Functions - * @{ - */ - -/** - * @brief Get the NMI flag that shows who triggered NMI. - * @param None - * @retval NMI flag - */ -INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void) -{ - INTIFSD_NMIFactor intifsd_nmi_factor = { 0U }; - - intifsd_nmi_factor.All = TSB_INTIFSD->FLAG0 & (~INTIFSD_NMIFLG_MASK); - - return intifsd_nmi_factor; -} - -/** - * @brief Get the INTFLAG3. - * @param None - * @retval INTFLAG3 flag - */ -INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void) -{ - INTIFSD_IntFlag3Factor intifsd_intflag3_factor = { 0U }; - - intifsd_intflag3_factor.All = TSB_INTIFSD->FLAG3; - - return intifsd_intflag3_factor; -} - -/** - * @brief Get the INTFLAG4. - * @param None - * @retval INTFLAG4 flag - */ -INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void) -{ - INTIFSD_IntFlag4Factor intifsd_intflag4_factor = { 0U }; - - intifsd_intflag4_factor.All = TSB_INTIFSD->FLAG4 & (~INTIFSD_INTFLAG4_MASK); - - return intifsd_intflag4_factor; -} - -/** - * @brief Get the INTFLAG5. - * @param None - * @retval INTFLAG5 flag - */ -INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void) -{ - INTIFSD_IntFlag5Factor intifsd_intflag5_factor = { 0U }; - - intifsd_intflag5_factor.All = TSB_INTIFSD->FLAG5 & (~INTIFSD_INTFLAG5_MASK); - - return intifsd_intflag5_factor; -} - -/** - * @brief Clears the input INT request. - * @param INTSource: Select the release INT source - * This parameter can be one of the following values: - * INTIFSD_INT_SRC_LVD_PSFD, INTIFSD_INT_SRC_LVD_PRD, INTIFSD_INT_SRC_WDT, INTIFSD_INT_SRC_DMAC_0, - * INTIFSD_INT_SRC_DMAC_1, INTIFSD_INT_SRC_DMAC_2, INTIFSD_INT_SRC_DMAC_3, INTIFSD_INT_SRC_DMAC_4, - * INTIFSD_INT_SRC_DMAC_5, INTIFSD_INT_SRC_DMAC_6, INTIFSD_INT_SRC_DMAC_7, INTIFSD_INT_SRC_DMAC_8, - * INTIFSD_INT_SRC_DMAC_9, INTIFSD_INT_SRC_DMAC_10, INTIFSD_INT_SRC_DMAC_11, INTIFSD_INT_SRC_DMAC_12, - * INTIFSD_INT_SRC_DMAC_13, INTIFSD_INT_SRC_DMAC_14, INTIFSD_INT_SRC_DMAC_15, INTIFSD_INT_SRC_DMAC_16, - * INTIFSD_INT_SRC_DMAC_17, INTIFSD_INT_SRC_DMAC_18, INTIFSD_INT_SRC_DMAC_19, INTIFSD_INT_SRC_DMAC_20, - * INTIFSD_INT_SRC_DMAC_21, INTIFSD_INT_SRC_DMAC_22, INTIFSD_INT_SRC_DMAC_23, INTIFSD_INT_SRC_DMAC_24, - * INTIFSD_INT_SRC_DMAC_25, INTIFSD_INT_SRC_DMAC_26, INTIFSD_INT_SRC_DMAC_27, INTIFSD_INT_SRC_DMAC_28, - * INTIFSD_INT_SRC_DMAC_29, INTIFSD_INT_SRC_DMAC_30, INTIFSD_INT_SRC_DMAC_31, INTIFSD_INT_SRC_DMAC_ERR, - * INTIFSD_INT_SRC_TMRB_0_MDOVF, INTIFSD_INT_SRC_TMRB_0_CAP0, INTIFSD_INT_SRC_TMRB_0_CAP1, INTIFSD_INT_SRC_TMRB_1_MDOVF, - * INTIFSD_INT_SRC_TMRB_1_CAP0, INTIFSD_INT_SRC_TMRB_1_CAP1, INTIFSD_INT_SRC_TMRB_2_MDOVF, INTIFSD_INT_SRC_TMRB_2_CAP0, - * INTIFSD_INT_SRC_TMRB_2_CAP1, INTIFSD_INT_SRC_TMRB_3_MDOVF, INTIFSD_INT_SRC_TMRB_3_CAP0, INTIFSD_INT_SRC_TMRB_3_CAP1, - * INTIFSD_INT_SRC_TMRB_4_MDOVF,INTIFSD_INT_SRC_TMRB_4_CAP0, INTIFSD_INT_SRC_TMRB_4_CAP1, INTIFSD_INT_SRC_TMRB_5_MDOVF, - * INTIFSD_INT_SRC_TMRB_5_CAP0, INTIFSD_INT_SRC_TMRB_5_CAP1, INTIFSD_INT_SRC_TMRB_6_MDOVF, INTIFSD_INT_SRC_TMRB_6_CAP0, - * INTIFSD_INT_SRC_TMRB_6_CAP1, INTIFSD_INT_SRC_TMRB_7_MDOVF, INTIFSD_INT_SRC_TMRB_7_CAP0, INTIFSD_INT_SRC_TMRB_7_CAP1, - * INTIFSD_INT_SRC_TMRD_00, INTIFSD_INT_SRC_TMRD_01, INTIFSD_INT_SRC_TMRD_02, INTIFSD_INT_SRC_TMRD_03, - * INTIFSD_INT_SRC_TMRD_04, INTIFSD_INT_SRC_TMRD_10, INTIFSD_INT_SRC_TMRD_11, INTIFSD_INT_SRC_TMRD_12, - * INTIFSD_INT_SRC_TMRD_13, INTIFSD_INT_SRC_TMRD_14. - * @retval None - */ -void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource) -{ - uint8_t num = 0U; - - /* Check the parameters */ - assert_param(IS_INTIFSD_INT_SRC(INTSource)); - - num = (uint32_t) INTSource; - switch (num) { - case 0U: /* STOP1INT_016 */ - TSB_INTIFSD->STOP1INT_016 |= 0xC0; - break; - case 1U: /* STOP1INT_017 */ - TSB_INTIFSD->STOP1INT_017 |= 0xC0; - break; - case 2U: /* IDLEINT_018 */ - TSB_INTIFSD->IDLEINT_018 |= 0xC0; - break; - case 3U: /* IDLEINT_096 */ - TSB_INTIFSD->IDLEINT_096 |= 0xC0; - break; - case 4U: /* IDLEINT_097 */ - TSB_INTIFSD->IDLEINT_097 |= 0xC0; - break; - case 5U: /* IDLEINT_098 */ - TSB_INTIFSD->IDLEINT_098 |= 0xC0; - break; - case 6U: /* IDLEINT_099 */ - TSB_INTIFSD->IDLEINT_099 |= 0xC0; - break; - case 7U: /* IDLEINT_100 */ - TSB_INTIFSD->IDLEINT_100 |= 0xC0; - break; - case 8U: /* IDLEINT_101 */ - TSB_INTIFSD->IDLEINT_101 |= 0xC0; - break; - case 9U: /* IDLEINT_102 */ - TSB_INTIFSD->IDLEINT_102 |= 0xC0; - break; - case 10U: /* IDLEINT_103 */ - TSB_INTIFSD->IDLEINT_103 |= 0xC0; - break; - case 11U: /* IDLEINT_104 */ - TSB_INTIFSD->IDLEINT_104 |= 0xC0; - break; - case 12U: /* IDLEINT_105 */ - TSB_INTIFSD->IDLEINT_105 |= 0xC0; - break; - case 13U: /* IDLEINT_106 */ - TSB_INTIFSD->IDLEINT_106 |= 0xC0; - break; - case 14U: /* IDLEINT_107 */ - TSB_INTIFSD->IDLEINT_107 |= 0xC0; - break; - case 15U: /* IDLEINT_108 */ - TSB_INTIFSD->IDLEINT_108 |= 0xC0; - break; - case 16U: /* IDLEINT_109 */ - TSB_INTIFSD->IDLEINT_109 |= 0xC0; - break; - case 17U: /* IDLEINT_110 */ - TSB_INTIFSD->IDLEINT_110 |= 0xC0; - break; - case 18U: /* IDLEINT_111 */ - TSB_INTIFSD->IDLEINT_111 |= 0xC0; - break; - case 19U: /* IDLEINT_112 */ - TSB_INTIFSD->IDLEINT_112 |= 0xC0; - break; - case 20U: /* IDLEINT_113 */ - TSB_INTIFSD->IDLEINT_113 |= 0xC0; - break; - case 21U: /* IDLEINT_114 */ - TSB_INTIFSD->IDLEINT_114 |= 0xC0; - break; - case 22U: /* IDLEINT_115 */ - TSB_INTIFSD->IDLEINT_115 |= 0xC0; - break; - case 23U: /* IDLEINT_116 */ - TSB_INTIFSD->IDLEINT_116 |= 0xC0; - break; - case 24U: /* IDLEINT_117 */ - TSB_INTIFSD->IDLEINT_117 |= 0xC0; - break; - case 25U: /* IDLEINT_118 */ - TSB_INTIFSD->IDLEINT_118 |= 0xC0; - break; - case 26U: /* IDLEINT_119 */ - TSB_INTIFSD->IDLEINT_119 |= 0xC0; - break; - case 27U: /* IDLEINT_120 */ - TSB_INTIFSD->IDLEINT_120 |= 0xC0; - break; - case 28U: /* IDLEINT_121 */ - TSB_INTIFSD->IDLEINT_121 |= 0xC0; - break; - case 29U: /* IDLEINT_122 */ - TSB_INTIFSD->IDLEINT_122 |= 0xC0; - break; - case 30U: /* IDLEINT_123 */ - TSB_INTIFSD->IDLEINT_123 |= 0xC0; - break; - case 31U: /* IDLEINT_124 */ - TSB_INTIFSD->IDLEINT_124 |= 0xC0; - break; - case 32U: /* IDLEINT_125 */ - TSB_INTIFSD->IDLEINT_125 |= 0xC0; - break; - case 33U: /* IDLEINT_126 */ - TSB_INTIFSD->IDLEINT_126 |= 0xC0; - break; - case 34U: /* IDLEINT_127 */ - TSB_INTIFSD->IDLEINT_127 |= 0xC0; - break; - case 35U: /* IDLEINT_128 */ - TSB_INTIFSD->IDLEINT_128 |= 0xC0; - break; - case 36U: /* IDLEINT_129 */ - TSB_INTIFSD->IDLEINT_129 |= 0xC0; - break; - case 37U: /* IDLEINT_130 */ - TSB_INTIFSD->IDLEINT_130 |= 0xC0; - break; - case 38U: /* IDLEINT_131 */ - TSB_INTIFSD->IDLEINT_131 |= 0xC0; - break; - case 39U: /* IDLEINT_132 */ - TSB_INTIFSD->IDLEINT_132 |= 0xC0; - break; - case 40U: /* IDLEINT_133 */ - TSB_INTIFSD->IDLEINT_133 |= 0xC0; - break; - case 41U: /* IDLEINT_134 */ - TSB_INTIFSD->IDLEINT_134 |= 0xC0; - break; - case 42U: /* IDLEINT_135 */ - TSB_INTIFSD->IDLEINT_135 |= 0xC0; - break; - case 43U: /* IDLEINT_136 */ - TSB_INTIFSD->IDLEINT_136 |= 0xC0; - break; - case 44U: /* IDLEINT_137 */ - TSB_INTIFSD->IDLEINT_137 |= 0xC0; - break; - case 45U: /* IDLEINT_138 */ - TSB_INTIFSD->IDLEINT_138 |= 0xC0; - break; - case 46U: /* IDLEINT_139 */ - TSB_INTIFSD->IDLEINT_139 |= 0xC0; - break; - case 47U: /* IDLEINT_140 */ - TSB_INTIFSD->IDLEINT_140 |= 0xC0; - break; - case 48U: /* IDLEINT_141 */ - TSB_INTIFSD->IDLEINT_141 |= 0xC0; - break; - case 49U: /* IDLEINT_142 */ - TSB_INTIFSD->IDLEINT_142 |= 0xC0; - break; - case 50U: /* IDLEINT_143 */ - TSB_INTIFSD->IDLEINT_143 |= 0xC0; - break; - case 51U: /* IDLEINT_144 */ - TSB_INTIFSD->IDLEINT_144 |= 0xC0; - break; - case 52U: /* IDLEINT_145 */ - TSB_INTIFSD->IDLEINT_145 |= 0xC0; - break; - case 53U: /* IDLEINT_146 */ - TSB_INTIFSD->IDLEINT_146 |= 0xC0; - break; - case 54U: /* IDLEINT_147 */ - TSB_INTIFSD->IDLEINT_147 |= 0xC0; - break; - case 55U: /* IDLEINT_148 */ - TSB_INTIFSD->IDLEINT_148 |= 0xC0; - break; - case 56U: /* IDLEINT_149 */ - TSB_INTIFSD->IDLEINT_149 |= 0xC0; - break; - case 57U: /* IDLEINT_150 */ - TSB_INTIFSD->IDLEINT_150 |= 0xC0; - break; - case 58U: /* IDLEINT_151 */ - TSB_INTIFSD->IDLEINT_151 |= 0xC0; - break; - case 59U: /* IDLEINT_152 */ - TSB_INTIFSD->IDLEINT_152 |= 0xC0; - break; - case 60U: /* IDLEINT_160 */ - TSB_INTIFSD->IDLEINT_160 |= 0xC0; - break; - case 61U: /* IDLEINT_161 */ - TSB_INTIFSD->IDLEINT_161 |= 0xC0; - break; - case 62U: /* IDLEINT_162 */ - TSB_INTIFSD->IDLEINT_162 |= 0xC0; - break; - case 63U: /* IDLEINT_163 */ - TSB_INTIFSD->IDLEINT_163 |= 0xC0; - break; - case 64U: /* IDLEINT_164 */ - TSB_INTIFSD->IDLEINT_164 |= 0xC0; - break; - case 65U: /* IDLEINT_165 */ - TSB_INTIFSD->IDLEINT_165 |= 0xC0; - break; - case 66U: /* IDLEINT_166 */ - TSB_INTIFSD->IDLEINT_166 |= 0xC0; - break; - case 67U: /* IDLEINT_167 */ - TSB_INTIFSD->IDLEINT_167 |= 0xC0; - break; - case 68U: /* IDLEINT_168 */ - TSB_INTIFSD->IDLEINT_168 |= 0xC0; - break; - case 69U: /* IDLEINT_169 */ - TSB_INTIFSD->IDLEINT_169 |= 0xC0; - break; - default: - /* Do nothing */ - break; - } -} - -/** @} */ -/* End of group INTIFSD_Exported_Functions */ - -/** @} */ -/* End of group INTIFSD */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_INTIFSD_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c deleted file mode 100644 index 32f1f1f403..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c +++ /dev/null @@ -1,195 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_tmr16a.c - * @brief This file provides API functions for TMR16A driver. - * @version V2.0.2.1 - * @date 2015/10/09 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_tmr16a.h" - -#if defined(__TMPM066_TMR16A_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup TMR16A - * @brief TMR16A driver modules - * @{ - */ - -/** @defgroup TMR16A_Private_Defines - * @{ - */ -#define CR_CLK_SYSCK ((uint32_t)0xFFFFFFFE) -#define CR_CLK_PRCK ((uint32_t)0x00000001) -#define CR_FF_MASK ((uint32_t)0xFFFFFF4F) - -#define CP_CP_CLEAR ((uint32_t)0xFFFF0000) -/** @} */ -/* End of group TMR16A_Private_Defines */ - -/** @defgroup TMR16A_Private_FunctionPrototypes - * @{ - */ - -/** @} */ -/* End of group TMR16A_Private_FunctionPrototypes */ - -/** @defgroup TMR16A_Private_Functions - * @{ - */ - -/** @} */ -/* End of group TMR16A_Private_Functions */ - -/** @defgroup TMR16A_Exported_Functions - * @{ - */ - -/** - * @brief Start or stop counter of the specified TMR16A channel. - * @param T16Ax: Select the TMR16A channel. - * This parameter can be one of the following values: - * TSB_T16A0, TSB_T16A1. - * @param Cmd: The command for the counter. - * This parameter can be TMR16A_RUN or TMR16A_STOP. - * @retval None - */ -void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd) -{ - /* Check the parameters */ - assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); - assert_param(IS_TMR16A_CMD(Cmd)); - - /* Write command into RUN register */ - T16Ax->RUN = Cmd; -} - -/** - * @brief Specifies a source clock. - * @param T16Ax: Select the TMR16A channel. - * This parameter can be one of the following values: - * TSB_T16A0, TSB_T16A1. - * @param SrcClk: The command for the counter. - * This parameter can be TMR16A_SYSCK or TMR16A_PRCK. - * @retval None - */ -void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); - assert_param(IS_TMR16A_SRCCLK(SrcClk)); - - tmp = T16Ax->CR; - /* Write Sorce clock into register */ - if (SrcClk == TMR16A_PRCK) { - /* Set T16AxCR Source clock to PRCK */ - tmp |= CR_CLK_PRCK; - } else { - /* Clear T16AxCR Source clock to SYSCK */ - tmp &= CR_CLK_SYSCK; - } - T16Ax->CR = tmp; -} - -/** - * @brief Configure the flip-flop function. - * @param T16Ax: Select the TMR16A channel. - * This parameter can be one of the following values: - * TSB_T16A0, TSB_T16A1. - * @param FFStruct: The structure containing TMR16A flip-flop configuration - * @retval None - */ -void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_POINTER_NOT_NULL(FFStruct)); - assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); - assert_param(IS_TMR16A_FLIPFLOP_CTRL(FFStruct->TMR16AFlipflopCtrl)); - assert_param(IS_TMR16A_FLIPFLOP_TRG(FFStruct->TMR16AFlipflopReverseTrg)); - - /* Configure the flip-flop function of T16Ax */ - tmp = T16Ax->CR; - tmp &= CR_FF_MASK; - tmp |= (FFStruct->TMR16AFlipflopCtrl | FFStruct->TMR16AFlipflopReverseTrg); - T16Ax->CR = tmp; -} - -/** - * @brief Change cycle value of T16Ax. - * @param T16Ax: Select the TMR16A channel. - * This parameter can be one of the following values: - * TSB_T16A0, TSB_T16A1. - * @param Cycle: New cycle value, max 0xFFFF. - * @retval None - */ -void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle) -{ - /* Check the parameters */ - assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); - assert_param(IS_TMR16A_VALUE(Cycle)); - - /* Write cycle into RG1 */ - T16Ax->RG = Cycle; -} - -/** - * @brief Get TMR16A capture value of T16Ax. - * @param T16Ax: Select the TMR16A channel. - * This parameter can be one of the following values: - * TSB_T16A0, TSB_T16A1. - * @retval Capture value of T16Ax - */ -uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax) -{ - uint16_t CapVal; - - /* Check the parameters */ - assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); - - CapVal = (uint16_t) T16Ax->CP; - - return CapVal; -} - -/** - * @brief Enable or disable clock operation during debug HALT. - * @param T16Ax: Select the TMR16A channel. - * This parameter can be one of the following values: - * TSB_T16A0, TSB_T16A1. - * @param ClkState: Timer state in HALT mode. - * This parameter can be TMR16A_RUNNING_IN_CORE_HALT or TMR16A_STOP_IN_CORE_HALT. - * @retval None - */ -void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState) -{ - /* Check the parameters */ - assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); - assert_param(IS_TMR16A_CLK_IN_CORE_HALT(ClkState)); - - if (ClkState == TMR16A_STOP_IN_CORE_HALT) { - /* Set T16AEN */ - T16Ax->EN |= (uint32_t) TMR16A_STOP_IN_CORE_HALT; - } else { - /* Clear T16AEN */ - T16Ax->EN &= ~(uint32_t) TMR16A_STOP_IN_CORE_HALT; - } -} - -/** @} */ -/* End of group TMR16A_Exported_Functions */ - -/** @} */ -/* End of group TMR16A */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_TMR16A_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c deleted file mode 100644 index b72b987b9d..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c +++ /dev/null @@ -1,555 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm066_tmrb.c - * @brief This file provides API functions for TMRB driver. - * @version V2.0.2.1 - * @date 2015/10/09 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_tmrb.h" - -#if defined (__TMPM066_TMRB_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup TMRB - * @brief TMRB driver modules - * @{ - */ - -/** @defgroup TMRB_Private_Defines - * @{ - */ - -#define EN_TBEN_SET ((uint32_t)0x00000080) -#define EN_TBEN_CLEAR ((uint32_t)0xFFFFFF7F) - -#define CR_TBSYNC_SET ((uint32_t)0x00000020) -#define CR_TBSYNC_CLEAR ((uint32_t)0xFFFFFFDF) -#define CR_TBWBF_SET ((uint32_t)0x00000080) -#define CR_TBWBF_CLEAR ((uint32_t)0xFFFFFF7F) -#define CR_CSSEL_SET ((uint32_t)0x00000001) -#define CR_CSSEL_CLEAR ((uint32_t)0xFFFFFFFE) -#define CR_TRGSEL_CLEAR ((uint32_t)0xFFFFFFFD) -#define CR_BIT6_CLEAR ((uint32_t)0xFFFFFFBF) - -#define MOD_BIT7_CLEAR ((uint32_t)0xFFFFFF7F) -#define MOD_CLK_CLE_CLEAR ((uint32_t)0xFFFFFFF0) -#define MOD_TBCPM_CLEAR ((uint32_t)0xFFFFFF8F) -#define MOD_TBCP_SET ((uint32_t)0x00000040) -#define MOD_TBCP_CLEAR ((uint32_t)0xFFFFFFBF) - -#define TB_ST_MASK ((uint32_t)0x00000007) -#define TB_IM_MASK ((uint32_t)0x00000007) - -/** @} */ -/* End of group TMRB_Private_Defines */ - -/** @defgroup TMRB_Private_FunctionPrototypes - * @{ - */ - -/** @} */ -/* End of group TMRB_Private_FunctionPrototypes */ - -/** @defgroup TMRB_Private_Functions - * @{ - */ - -/** @} */ -/* End of group TMRB_Private_Functions */ - -/** @defgroup TMRB_Exported_Functions - * @{ - */ - -/** - * @brief Enable the specified TMRB channel. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @retval None - */ -void TMRB_Enable(TSB_TB_TypeDef * TBx) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - /* Set TBxEN to enable TBx */ - TBx->EN |= EN_TBEN_SET; -} - -/** - * @brief Disable the specified TMRB channel. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @retval None - */ -void TMRB_Disable(TSB_TB_TypeDef * TBx) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - /* Clear TBxEN to disable TBx */ - TBx->EN &= EN_TBEN_CLEAR; -} - -/** - * @brief Start or stop counter of the specified TMRB channel. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param Cmd: The command for the counter. - * This parameter can be TMRB_RUN or TMRB_STOP. - * @retval None - */ -void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_CMD(Cmd)); - - /* Write command into RUN register */ - TBx->RUN = Cmd; -} - -/** - * @brief Initialize the specified TMRB channel. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param InitStruct: The structure containing basic TMRB configuration. - * @retval None - */ -void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_POINTER_NOT_NULL(InitStruct)); - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_MODE(InitStruct->Mode)); - if (InitStruct->Mode != 0U) { - assert_param(IS_TMRB_CLK_DIV(InitStruct->ClkDiv)); - } else { - /* Do nothing */ - } - assert_param(IS_TMRB_VALUE(InitStruct->TrailingTiming)); - assert_param(IS_TMRB_UC_CTRL(InitStruct->UpCntCtrl)); - assert_param(IS_TMRB_VALUE(InitStruct->LeadingTiming)); - assert_param(IS_VALID_LEADINGTIMING(InitStruct->LeadingTiming, InitStruct->TrailingTiming)); - - /* Configure source clock for TBx */ - tmp = TBx->MOD; - tmp &= MOD_BIT7_CLEAR; - tmp &= MOD_CLK_CLE_CLEAR; - if (InitStruct->Mode != 0U) { - /* Use internal clock, set the prescaler */ - tmp |= InitStruct->ClkDiv; - } else { - /* Use external clock */ - tmp |= InitStruct->Mode; - } - /* Set up-counter running mode */ - tmp |= InitStruct->UpCntCtrl; - tmp |= MOD_TBCP_SET; - TBx->MOD = tmp; - - /* Write leadingtiming into RG0 */ - TBx->RG0 = InitStruct->LeadingTiming; - - /* Write trailingtiminginto RG1 */ - TBx->RG1 = InitStruct->TrailingTiming; -} - -/** - * @brief Configure the capture timing. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5. - * @param CaptureTiming: Specify TMRB capture timing. - * This parameter can be one of the following values: - * TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_IN_RISING_FALLING, TMRB_CAPTURE_FF_RISING_FALLING. - * @retval None - */ -void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_TMRB_CAP_PERIPH(TBx)); - assert_param(IS_TMRB_CAPTURE_TIMING(CaptureTiming)); - - /* Configure capture timing */ - tmp = TBx->MOD; - tmp &= MOD_BIT7_CLEAR; - tmp &= MOD_TBCPM_CLEAR; - tmp |= CaptureTiming; - tmp |= MOD_TBCP_SET; - TBx->MOD = tmp; -} - -/** - * @brief Configure the flip-flop function. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param FFStruct: The structure containing TMRB flip-flop configuration - * @retval None - */ -void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct) -{ - /* Check the parameters */ - assert_param(IS_POINTER_NOT_NULL(FFStruct)); - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_FLIPFLOP_CTRL(FFStruct->FlipflopCtrl)); - assert_param(IS_TMRB_FLIPFLOP_TRG(FFStruct->FlipflopReverseTrg)); - - /* Configure the flip-flop function of TBx */ - TBx->FFCR = (FFStruct->FlipflopCtrl | FFStruct->FlipflopReverseTrg); -} - -/** - * @brief Indicate what causes the interrupt. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @retval The interrupt factor of TBx. - */ -TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx) -{ - TMRB_INTFactor retval = { 0U }; - - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - - retval.All = TBx->ST & TB_ST_MASK; - return retval; -} - -/** - * @brief Indicate what interrupt cause source be masked. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @retval The masked interrupt cause source of TBx. - */ -TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx) -{ - TMRB_INTMask retval = { 0U }; - - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - - retval.All = TBx->IM & TB_IM_MASK; - return retval; -} - -/** - * @brief Mask some TMRB interrupts. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param INTMask: Select the mask of TMRB interrupt. - * This parameter can be one of the following values: - * TMRB_NO_INT_MASK, TMRB_MASK_MATCH_LEADINGTIMING_INT, TMRB_MASK_MATCH_TRAILINGTIMING_INT, - * or TMRB_MASK_OVERFLOW_INT. - * @retval None - */ -void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_INT_MASK(INTMask)); - - /* Mask the specified interrupt */ - TBx->IM = INTMask; -} - -/** - * @brief Change leadingtiming value of TBx. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param LeadingTiming: New leadingtiming value, max 0xFFFF. - * @retval None - */ -void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_VALUE(LeadingTiming)); - assert_param(IS_VALID_LEADINGTIMING(LeadingTiming, TBx->RG1)); - - /* Write leadingtiming into RG0 */ - TBx->RG0 = LeadingTiming; -} - -/** - * @brief Change trailingtiming value of TBx. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param TrailingTiming: New trailingtiming value, max 0xFFFF. - * @retval None - */ -void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_VALUE(TrailingTiming)); - assert_param(IS_VALID_LEADINGTIMING(TBx->RG0, TrailingTiming)); - - /* Write trailingtiming into RG1 */ - TBx->RG1 = TrailingTiming; -} - -/** - * @brief Get TMRB register value of TBx. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param Reg: Select the timer register to read. - * This parameter can be: TMRB_REG_0 or TMRB_REG_1. - * @retval Register value of TBx - */ -uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_REG(Reg)); - - return Reg ? (uint16_t) TBx->RG1 : (uint16_t) TBx->RG0; -} - -/** - * @brief Get up-counter value of TBx. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @retval Up-counter value of TBx - */ -uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - - /* Return up-counter value */ - return (uint16_t) TBx->UC; -} - -/** - * @brief Get TMRB capture value of TBx. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5. - * @param CapReg: Select the capture register to read. - * This parameter can be: TMRB_CAPTURE_0 or TMRB_CAPTURE_1. - * @retval Capture value of TBx - */ -uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg) -{ - /* Check the parameters */ - assert_param(IS_TMRB_CAP_PERIPH(TBx)); - assert_param(IS_TMRB_CAPTURE_REG(CapReg)); - - return CapReg ? (uint16_t) TBx->CP1 : (uint16_t) TBx->CP0; -} - -/** - * @brief Capture counter by software and take them into capture register 0. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5. - * @retval None - */ -void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_TMRB_CAP_PERIPH(TBx)); - - /* Set software capture */ - tmp = TBx->MOD; - tmp &= MOD_BIT7_CLEAR; - TBx->MOD = tmp & MOD_TBCP_CLEAR; -} - -/** - * @brief Enable or disable the synchronous mode of specified TMRB channel. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB5, TSB_TB6, TSB_TB7. - * @param NewState: New state of TBx synchronous mode. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_TMRB_SYNC_PERIPH(TBx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = TBx->CR; - tmp &= CR_BIT6_CLEAR; - if (NewState == ENABLE) { - /* Set TBxCR to make TBx running in synchronous mode */ - TBx->CR = tmp | CR_TBSYNC_SET; - } else { - /* Clear TBxCR to make TBx running in individual mode */ - TBx->CR = tmp & CR_TBSYNC_CLEAR; - } -} - -/** - * @brief Enable or disable double buffer of TBx. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param NewState: New state of TBx double buffer. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = TBx->CR; - tmp &= CR_BIT6_CLEAR; - if (NewState == ENABLE) { - /* Set TBxCR to enable TBx double buffer */ - TBx->CR = tmp | CR_TBWBF_SET; - } else { - /* Clear TBxCR to disable TBx double buffer */ - TBx->CR = tmp & CR_TBWBF_CLEAR; - } -} - -/** - * @brief Enable or disable external trigger to start count and set the active edge. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param NewState: New state of external trigger. - * This parameter can be ENABLE or DISABLE. - * @param TrgMode: Active edge of the external trigger signal. - * This parameter can be TMRB_TRG_EDGE_RISING or TMRB_TRG_EDGE_FALLING. - * @retval None - */ -void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_TMRB_TRG_EDGE(TrgMode)); - - tmp = TBx->CR; - tmp &= CR_BIT6_CLEAR; - if (NewState == ENABLE) { - /* Set TBxCR to choose external trigger */ - tmp |= CR_CSSEL_SET; - } else { - /* Clear TBxCR to choose software start */ - tmp &= CR_CSSEL_CLEAR; - } - - /* external trigger selection */ - tmp &= CR_TRGSEL_CLEAR; - tmp |= (uint32_t) TrgMode; - TBx->CR = tmp; -} - -/** - * @brief Enable or disable clock operation during debug HALT. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param ClkState: Timer state in HALT mode. - * This parameter can be TMRB_RUNNING_IN_CORE_HALT or TMRB_STOP_IN_CORE_HALT. - * @retval None - */ -void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_TMRB_CLK_IN_CORE_HALT(ClkState)); - - if (ClkState == TMRB_STOP_IN_CORE_HALT) { - /* Set TBxEN */ - TBx->EN |= (uint32_t) TMRB_STOP_IN_CORE_HALT; - } else { - /* Clear TBxEN */ - TBx->EN &= ~(uint32_t) TMRB_STOP_IN_CORE_HALT; - } -} - -/** - * @brief Enable or disable DMA request. - * @param TBx: Select the TMRB channel. - * This parameter can be one of the following values: - * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, - * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. - * @param NewState: New state of DMA request. - * This parameter can be ENABLE or DISABLE. - * @param DMAReq: DMA request. - * This parameter can be TMRB_DMA_REQ_CMP_MATCH, TMRB_DMA_REQ_CAPTURE_1 or TMRB_DMA_REQ_CAPTURE_0. - * @retval None - */ -void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq) -{ - /* Check the parameters */ - assert_param(IS_TMRB_ALL_PERIPH(TBx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_TMRB_DMA_REQ(DMAReq)); - - if (NewState == ENABLE) { - /* set TBxDMA(n can be 0,1,2) */ - TBx->DMA |= (uint32_t) DMAReq; - } else { - /* clear TBxDMA(n can be 0,1,2) */ - TBx->DMA &= ~((uint32_t) DMAReq); - } -} - - -/** @} */ -/* End of group TMRB_Exported_Functions */ - -/** @} */ -/* End of group TMRB */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_TMRB_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c deleted file mode 100644 index 2dd7cc1b8c..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c +++ /dev/null @@ -1,1198 +0,0 @@ - -/** - ******************************************************************************* - * @file tmpm066_uart.c - * @brief This file provides API functions for UART driver. - * @version V2.0.2.1 - * @date 2015/09/10 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tmpm066_uart.h" - -#if defined(__TMPM066_UART_H) -/** @addtogroup TX00_Periph_Driver - * @{ - */ - -/** @defgroup UART - * @brief UART driver modules - * @{ - */ - -/** @defgroup UART_Private_Defines - * @{ - */ -#define EN_SIOE_SET ((uint32_t)0x00000001) -#define EN_SIOE_CLEAR ((uint32_t)0xFFFFFFFE) -#define EN_BRCKSEL_MASK ((uint32_t)0xFFFFFFFD) - -#define CR_PARITY_MASK ((uint32_t)0x0000779F) -#define CR_ERROR_MASK ((uint32_t)0x0000001C) -#define CR_OERR_FLAG ((uint8_t)0x10) -#define CR_PERR_FLAG ((uint8_t)0x08) -#define CR_FERR_FLAG ((uint8_t)0x04) -#define CR_IOC_MASK ((uint32_t)0x000077FE) -#define CR_SCLKS_MASK ((uint32_t)0x000077FD) -#define CR_TIDLE_MASK ((uint32_t)0x000074FF) -#define CR_TXDEMP_MASK ((uint32_t)0x000073FF) -#define CR_EHOLD_MASK ((uint32_t)0x000007FF) - -#define MOD0_CTSE_MASK ((uint32_t)0x000000BF) -#define MOD0_RXE_CLEAR ((uint32_t)0x000000DF) -#define MOD0_WU_SET ((uint32_t)0x00000010) -#define MOD0_WU_CLEAR ((uint32_t)0x000000EF) -#define MOD0_SM_MASK ((uint32_t)0x000000F3) -#define MOD0_SC_MASK ((uint32_t)0x000000FC) -#define MOD0_SC_BRG ((uint32_t)0x00000001) - -#define MOD1_I2SC_SET ((uint32_t)0x00000080) -#define MOD1_I2SC_CLEAR ((uint32_t)0x0000007F) -#define MOD1_TXE_CLEAR ((uint32_t)0x000000EF) -#define MOD1_CLEAR ((uint32_t)0x000000FE) -#define MOD1_FDPX_CLEAR ((uint32_t)0x0000009F) -#define MOD1_SINT_MASK ((uint32_t)0x000000F1) - -#define MOD2_BUF_MASK ((uint32_t)0x000000C0) -#define MOD2_TBEMP_FLAG ((uint8_t)0x80) -#define MOD2_RBFLL_FLAG ((uint8_t)0x40) -#define MOD2_SBLEN_MASK ((uint32_t)0x000000EF) -#define MOD2_DRCHG_MASK ((uint32_t)0x000000F7) -#define MOD2_WBUF_SET ((uint32_t)0x00000004) -#define MOD2_WBUF_MASK ((uint32_t)0x000000FB) -#define MOD2_SWRST_MASK ((uint32_t)0x000000FC) -#define MOD2_SWRST_CMD1 ((uint32_t)0x00000002) -#define MOD2_SWRST_CMD2 ((uint32_t)0x00000001) - -#define BRCR_BRADDE_SET ((uint32_t)0x00000040) -#define BRCR_BRCK_MASK ((uint32_t)0x000000CF) -#define BRCR_BRS_MASK ((uint32_t)0x000000F0) -#define BRCR_CLEAR ((uint32_t)0x0000007F) - -#define BRADD_BRK_MASK ((uint32_t)0x00000000) - -#define FCNF_BIT567_CLEAR ((uint32_t)0x0000001F) -#define FCNF_RFST_CLEAR ((uint32_t)0x000000EF) -#define FCNF_TFIE_SET ((uint32_t)0x00000008) -#define FCNF_TFIE_CLEAR ((uint32_t)0x00000017) -#define FCNF_RFIE_SET ((uint32_t)0x00000004) -#define FCNF_RFIE_CLEAR ((uint32_t)0x0000001B) -#define FCNF_RXTXCNT_SET ((uint32_t)0x00000002) -#define FCNF_RXTXCNT_CLEAR ((uint32_t)0x0000001D) -#define FCNF_CNFG_SET ((uint32_t)0x00000001) -#define FCNF_CNFG_CLEAR ((uint32_t)0x0000001E) - -#define RFC_4B_RIL_CLEAR ((uint32_t)0x000000FC) -#define TFC_4B_TIL_CLEAR ((uint32_t)0x000001FC) -#define RFC_RFIS_CLEAR ((uint32_t)0x000000BF) -#define TFC_TFIS_CLEAR ((uint32_t)0x000001BF) -#define TRFC_TRFCS_SET ((uint32_t)0x00000080) -#define TFC_TBCLR_SET ((uint32_t)0x00000100) - -#define TRXST_TUR_ROR_MASK ((uint32_t)0x00000080) -#define TRXST_4B_TRLVL_MASK ((uint32_t)0x00000007) - -#define DMA_EN0_SET ((uint32_t)0x00000001) -#define DMA_EN0_CLEAR ((uint32_t)0x00000002) - -#define DMA_EN1_SET ((uint32_t)0x00000002) -#define DMA_EN1_CLEAR ((uint32_t)0x00000001) - -/** @} */ -/* End of group UART_Private_Defines */ - -/** @defgroup UART_Private_FunctionPrototypes - * @{ - */ - -/** @} */ -/* End of group UART_Private_FunctionPrototypes */ - -/** @defgroup UART_Private_Functions - * @{ - */ - -/** @} */ -/* End of group UART_Private_Functions */ - -/** @defgroup UART_Exported_Functions - * @{ - */ - -/** - * @brief Enable the specified UART channel. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval None - */ -void UART_Enable(TSB_SC_TypeDef * UARTx) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - /* Set SCxEN to enable UARTx */ - UARTx->EN |= EN_SIOE_SET; -} - -/** - * @brief Disable the specified UART channel. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval None - */ -void UART_Disable(TSB_SC_TypeDef * UARTx) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - /* Clear SCxEN to disable UARTx */ - UARTx->EN &= EN_SIOE_CLEAR; -} - -/** - * @brief Indicate whether the transfer buffer is full or not. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param Direction: Select the direction of transfer. - * This parameter can be UART_RX or UART_TX. - * @retval The transfer buffer status. - * The value returned can be one of the followings: - * BUSY or DONE. - */ -WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint32_t Direction) -{ - uint8_t tmp = 0U; - WorkState retval = BUSY; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UART_TRX(Direction)); - - tmp = ((uint8_t) (UARTx->MOD2 & MOD2_BUF_MASK)); - switch (Direction) { - case UART_TX: - if ((tmp & MOD2_TBEMP_FLAG) == MOD2_TBEMP_FLAG) { - /* Return Tx buffer empty if the flag is set */ - retval = DONE; - } else { - /* Do nothing */ - } - break; - case UART_RX: - if ((tmp & MOD2_RBFLL_FLAG) == MOD2_RBFLL_FLAG) { - /* Return Rx buffer full if the flag is set */ - retval = DONE; - } else { - /* Do nothing */ - } - break; - default: /* Do nothing */ - break; - } - - return retval; -} - -/** - * @brief Reset the specified UART channel. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval None - */ -void UART_SWReset(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - /* Write software-reset command */ - tmp = UARTx->MOD2; - tmp &= MOD2_SWRST_MASK; - UARTx->MOD2 = tmp | MOD2_SWRST_CMD1; - tmp &= MOD2_SWRST_MASK; - UARTx->MOD2 = tmp | MOD2_SWRST_CMD2; -} - -/** - * @brief Initialize the specified UART channel. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param InitStruct: The structure containing basic UART configuration. - * @retval None - * @note UART_SetInputClock need to use before UART_Init. - */ -void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct) -{ - uint32_t T0 = 0U; - uint32_t T = 0U; - uint32_t t = 0U; - uint32_t N = 0U; - uint32_t K = 0U; - uint32_t tmp = 0U; - uint32_t divider = 0U; - const uint32_t a = 1U; - const uint32_t b = 4U; - /* Check the parameters */ - assert_param(IS_POINTER_NOT_NULL(InitStruct)); - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UART_BAUDRATE(InitStruct->BaudRate)); - assert_param(IS_UART_DATA_BITS(InitStruct->DataBits)); - assert_param(IS_UART_STOPBITS(InitStruct->StopBits)); - assert_param(IS_UART_PARITY(InitStruct->Parity)); - assert_param(IS_UART_MODE(InitStruct->Mode)); - assert_param(IS_UART_FLOW_CONTROL(InitStruct->FlowCtrl)); - - /* Configure the flow control */ - tmp = UARTx->MOD0; - tmp &= MOD0_SM_MASK; - tmp &= MOD0_CTSE_MASK; - tmp &= MOD0_SC_MASK; - tmp |= (InitStruct->DataBits | InitStruct->FlowCtrl); - /* Use baud rate generator */ - tmp |= MOD0_SC_BRG; - UARTx->MOD0 = tmp; - - /* Set the stop bit */ - tmp = UARTx->MOD2; - tmp &= MOD2_SBLEN_MASK; - tmp |= InitStruct->StopBits; - tmp |= MOD2_WBUF_SET; - UARTx->MOD2 = tmp; - - /* Enable or disable parity check */ - tmp = UARTx->CR; - tmp &= CR_PARITY_MASK; - tmp |= InitStruct->Parity; - UARTx->CR = tmp; - - /* Get the peripheral I/O clock frequency */ - SystemCoreClockUpdate(); - T0 = SystemCoreClock / (a << ((TSB_CG->SYSCR >> 8U) & 0xFU)); - if (UARTx->EN & (0x1U << 1)) { - T0 *= 2U; - } else { - /* Do nothing */ - } - /* Baud rate setting */ - while ((divider < 200U) || (divider > 1600U)) { - if (t == 0U) { - T = 2U; - } else { - if (T < 128U) { - T = T * b; - } else { - /* Do nothing */ - } - } - divider = (100U * (T0 >> 4U)) / (InitStruct->BaudRate * T); - t++; - } - N = divider / 100U; - /* K value setting */ - if ((divider - (N * 100U)) == 0) { - /* Do nothing */ - } else { - K = (16U * (100U - (divider - (N * 100U)))) / 100U; - if (K < 1U) { - K = 1U; - } else { - /* Do nothing */ - } - tmp = UARTx->BRADD; - tmp &= BRADD_BRK_MASK; - tmp |= (K & 0x0FU); - UARTx->BRADD = tmp; - } - /* N value, , setting */ - /* */ - tmp = UARTx->BRCR; - if ((divider - (N * 100U)) == 0) { - tmp &= ~BRCR_BRADDE_SET; - } else { - tmp |= BRCR_BRADDE_SET; - } - tmp &= BRCR_BRCK_MASK; - tmp &= BRCR_BRS_MASK; - tmp |= (((t - 1U) & 3U) << 4U); - tmp |= (N & 0x0FU); - tmp &= BRCR_CLEAR; - UARTx->BRCR = tmp; - - tmp = UARTx->MOD1; - /* Enable or disable transmission or reception */ - switch (InitStruct->Mode) { - case UART_ENABLE_RX: - UARTx->MOD0 |= InitStruct->Mode; - tmp &= MOD1_TXE_CLEAR; - break; - case UART_ENABLE_TX: - tmp |= InitStruct->Mode; - UARTx->MOD0 &= MOD0_RXE_CLEAR; - break; - default: - UARTx->MOD0 |= UART_ENABLE_RX; - tmp |= UART_ENABLE_TX; - break; - } - tmp &= MOD1_CLEAR; - UARTx->MOD1 = tmp; -} - -/** - * @brief Get received data of the specified UART channel. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval The received data - */ -uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx) -{ - uint32_t retval = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - /* Return received data */ - retval = (UARTx->CR & 0x80U) << 1U; - retval = retval | (UARTx->BUF & 0xFFU); - - return retval; -} - -/** - * @brief Set data to be sent and start transmitting via the specified - UART channel. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param Data: the data to be sent. - * @retval None - */ -void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data) -{ - uint32_t tmp = UARTx->MOD0 & 0x7FU; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UART_DATA(Data)); - - /* Write MSB to SCxMOD0 at first if in 9-bit mode */ - tmp |= ((Data & 0x100U) >> 1U); - UARTx->MOD0 = tmp; - - UARTx->BUF = Data & 0xFFU; -} - -/** - * @brief Initialize the specified UART channel in default configuration. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval None - */ -void UART_DefaultConfig(TSB_SC_TypeDef * UARTx) -{ - UART_InitTypeDef uartdefault; - uartdefault.BaudRate = 115200U; - uartdefault.DataBits = UART_DATA_BITS_8; - uartdefault.StopBits = UART_STOP_BITS_1; - uartdefault.Parity = UART_NO_PARITY; - uartdefault.Mode = UART_ENABLE_RX | UART_ENABLE_TX; - uartdefault.FlowCtrl = UART_NONE_FLOW_CTRL; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - /* Enable the selected UART channel */ - UART_Enable(UARTx); - /* Select baud rate generator as UART source clcok */ - /* Set baud rate as 115200bps */ - /* Select 8-bit UART mode */ - /* Select 1-bit stop */ - /* No parity check */ - /* No flow control */ - /* Enable both transmission and reception */ - UART_Init(UARTx, &uartdefault); -} - -/** - * @brief Indicate UART transfer error. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval The error flag. - * The value returned can be one of the followings: - * UART_NO_ERR, UART_OVERRUN, UART_PARITY_ERR, UART_FRAMING_ERR or UART_ERRS. - */ -UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx) -{ - uint8_t tmp = 0U; - UART_Err retval = UART_NO_ERR; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = ((uint8_t) (UARTx->CR & CR_ERROR_MASK)); - switch (tmp) { - case CR_OERR_FLAG: /* Check overrun flag */ - retval = UART_OVERRUN; - break; - case CR_PERR_FLAG: /* Check parity flag */ - retval = UART_PARITY_ERR; - break; - case CR_FERR_FLAG: /* Check framing flag */ - retval = UART_FRAMING_ERR; - break; - default: - if (tmp != 0U) { - /* more than one error */ - retval = UART_ERRS; - } else { - /* Do nothing */ - } - break; - } - return retval; -} - -/** - * @brief Enable or disable the wake-up function in 9-bit UART mode - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param NewState: New state of this function. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set SCxMOD0 to enable wake-up function */ - UARTx->MOD0 |= MOD0_WU_SET; - } else { - /* Clear SCxMOD0 to disable wake-up function */ - UARTx->MOD0 &= MOD0_WU_CLEAR; - } -} - -/** - * @brief Enable or disable the specified UART channel when system is in IDLE - mode. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param NewState: New state of the UART channel in IDLE. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = UARTx->MOD1; - if (NewState == ENABLE) { - /* Set SCxMOD1 to enable UARTx running in IDLE */ - tmp |= MOD1_I2SC_SET; - } else { - /* Clear SCxMOD1 to disable UARTx running in IDLE */ - tmp &= MOD1_I2SC_CLEAR; - } - tmp &= MOD1_CLEAR; - UARTx->MOD1 = tmp; -} - -/** - * @brief Selects input clock for prescaler. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param clock: Selects input clock for prescaler as PhiT0/2 or PhiT0. - * This parameter can be: - * 0: PhiT0/2 - * 1: PhiT0 - * @retval None - * @note UART_SetInputClock need to use before UART_Init. - */ -void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock) -{ - uint32_t tmp = 0U; - - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UART_CLOCK(clock)); - - tmp = UARTx->EN; - tmp &= EN_BRCKSEL_MASK; - tmp |= (uint32_t) (clock << 1U); - UARTx->EN = tmp; -} - -/** - * @brief Enable or disable the FIFO of specified UART channel. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param NewState: New state of the UART FIFO. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = UARTx->FCNF; - tmp &= FCNF_BIT567_CLEAR; - if (NewState == ENABLE) { - /* Set SCxFCNF to enable UARTx FIFO */ - UARTx->FCNF = tmp | FCNF_CNFG_SET; - } else { - /* Clear SCxFCNF to disable UARTx FIFO */ - UARTx->FCNF = tmp & FCNF_CNFG_CLEAR; - } -} - -/** - * @brief Transfer mode setting. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param TransferMode: Transfer mode. - * This parameter can be: UART_TRANSFER_PROHIBIT, UART_TRANSFER_HALFDPX_RX, - * UART_TRANSFER_HALFDPX_TX or UART_TRANSFER_FULLDPX. - * @retval None - */ -void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UART_TRANSFER_MODE(TransferMode)); - - tmp = UARTx->MOD1; - tmp &= MOD1_FDPX_CLEAR; - tmp |= TransferMode; - UARTx->MOD1 = tmp; -} - -/** - * @brief Controls automatic disabling of transmission and reception. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param TRxAutoDisable: Disabling transmission and reception or not. - * This parameter can be: UART_RXTXCNT_NONE or UART_RXTXCNT_AUTODISABLE . - * @retval None - */ -void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UATR_TRX_AUTODISABLE(TRxAutoDisable)); - - tmp = UARTx->FCNF; - tmp &= FCNF_BIT567_CLEAR; - if (TRxAutoDisable == UART_RXTXCNT_AUTODISABLE) { - /* Set SCxFCNF to automatic disabling of transmission and reception */ - UARTx->FCNF = tmp | FCNF_RXTXCNT_SET; - } else { - /* Clear SCxFCNF to do none */ - UARTx->FCNF = tmp & FCNF_RXTXCNT_CLEAR; - } -} - -/** - * @brief Enable or disable receive interrupt for receive FIFO. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param NewState: New state of receive interrupt for receive FIFO. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = UARTx->FCNF; - tmp &= FCNF_BIT567_CLEAR; - if (NewState == ENABLE) { - /* Set SCxFCNF to enable receive FIFO interrupt */ - UARTx->FCNF = tmp | FCNF_RFIE_SET; - } else { - /* Clear SCxFCNF to disable receive FIFO interrupt */ - UARTx->FCNF = tmp & FCNF_RFIE_CLEAR; - } -} - -/** - * @brief Enable or disable transmit interrupt for transmit FIFO. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param NewState: New state of transmit interrupt for transmit FIFO. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = UARTx->FCNF; - tmp &= FCNF_BIT567_CLEAR; - if (NewState == ENABLE) { - /* Set SCxFCNF to enable transmit FIFO interrupt */ - UARTx->FCNF = tmp | FCNF_TFIE_SET; - } else { - /* Clear SCxFCNF to disable transmit FIFO interrupt */ - UARTx->FCNF = tmp & FCNF_TFIE_CLEAR; - } -} - -/** - * @brief Bytes used in receive FIFO. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param BytesUsed: Bytes used in receive FIFO. - * This parameter can be: UART_RXFIFO_MAX or UART_RXFIFO_RXFLEVEL. - * @retval None - */ -void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UATR_RXFIFO_BYTESUSED(BytesUsed)); - - tmp = UARTx->FCNF; - tmp &= FCNF_BIT567_CLEAR; - tmp &= FCNF_RFST_CLEAR; - tmp |= BytesUsed; - UARTx->FCNF = tmp; -} - -/** - * @brief Receive FIFO fill level to generate receive interrupts. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param RxFIFOLevel: Receive FIFO fill level. - * This parameter can be one of the following values: - * UART_RXFIFO4B_FLEVLE_4_2B, UART_RXFIFO4B_FLEVLE_1_1B, - * UART_RXFIFO4B_FLEVLE_2_2B or UART_RXFIFO4B_FLEVLE_3_1B. - * @retval None - */ -void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UART_RXFIFO4B_FLEVLE(RxFIFOLevel)); - - tmp = UARTx->RFC; - tmp &= RFC_4B_RIL_CLEAR; - tmp |= RxFIFOLevel; - UARTx->RFC = tmp; -} - -/** - * @brief Select RX interrupt generation condition. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param RxINTCondition: RX interrupt generation condition. - * This parameter can be: UART_RFIS_REACH_FLEVEL or UART_RFIS_REACH_EXCEED_FLEVEL. - * @retval None - */ -void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UATR_RFIS_CONDITION(RxINTCondition)); - - tmp = UARTx->RFC; - tmp &= RFC_RFIS_CLEAR; - tmp |= RxINTCondition; - UARTx->RFC = tmp; -} - -/** - * @brief Receive FIFO clear. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval None - */ -void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = UARTx->RFC; - tmp |= TRFC_TRFCS_SET; - UARTx->RFC = tmp; -} - -/** - * @brief Transmit FIFO fill level to generate transmit interrupts. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param TxFIFOLevel: Transmit FIFO fill level. - * This parameter can be one of the following values: - * UART_TXFIFO4B_FLEVLE_0_0B, UART_TXFIFO4B_FLEVLE_1_1B, - * UART_TXFIFO4B_FLEVLE_2_0B or UART_TXFIFO4B_FLEVLE_3_1B. - * @retval None - */ -void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UART_TXFIFO4B_FLEVLE(TxFIFOLevel)); - - - tmp = UARTx->TFC; - tmp &= TFC_4B_TIL_CLEAR; - tmp |= TxFIFOLevel; - UARTx->TFC = tmp; -} - -/** - * @brief Select TX interrupt generation condition. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param TxINTCondition: TX interrupt generation condition. - * This parameter can be: UART_TFIS_REACH_FLEVEL or UART_TFIS_REACH_NOREACH_FLEVEL. - * @retval None - */ -void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_UATR_TFIS_CONDITION(TxINTCondition)); - - tmp = UARTx->TFC; - tmp &= TFC_TFIS_CLEAR; - tmp |= TxINTCondition; - UARTx->TFC = tmp; -} - -/** - * @brief Transmit FIFO clear. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval None - */ -void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = UARTx->TFC; - tmp |= TRFC_TRFCS_SET; - UARTx->TFC = tmp; -} - -/** - * @brief Transmit buffer clear. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval None - */ -void UART_TxBufferClear(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = UARTx->TFC; - tmp |= TFC_TBCLR_SET; - UARTx->TFC = tmp; -} - -/** - * @brief Status of receive FIFO fill level. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval Receive FIFO fill level status. - */ -uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = UARTx->RST; - tmp &= TRXST_4B_TRLVL_MASK; - /* Return the value */ - return tmp; -} - -/** - * @brief Receive FIFO overrun. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval Receive FIFO overrun status. - */ -uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - uint32_t regval = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = UARTx->RST; - if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) { - regval = UART_RXFIFO_OVERRUN; - } else { - /* Do nothing */ - } - /* Return the value */ - return regval; -} - -/** - * @brief Status of transmit FIFO fill level. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval Transmit FIFO fill level status. - */ -uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = UARTx->TST; - tmp &= TRXST_4B_TRLVL_MASK; - /* Return the value */ - return tmp; -} - -/** - * @brief Transmit FIFO under run. - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @retval Transmit FIFO under run status. - */ -uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx) -{ - uint32_t tmp = 0U; - uint32_t regval = 0U; - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - - tmp = UARTx->TST; - if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) { - regval = UART_TXFIFO_UNDERRUN; - } else { - /* Do nothing */ - } - /* Return the value */ - return regval; -} - -/** - * @brief Enable or disable the specified UART channel DMA Request By - receive interrupt INTRX - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param NewState: New state of the UART channel in IDLE. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_SetRxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set SCxDMA to enable UARTx DMA Request */ - UARTx->DMA |= DMA_EN1_SET; - } else { - /* Clear SCxDMA to disable UARTx DMA Request */ - UARTx->DMA &= DMA_EN1_CLEAR; - } -} - -/** - * @brief Enable or disable the specified UART channel DMA Request By - receive interrupt INTTX - * @param UARTx: Select the UART channel. - * This parameter can be one of the following values: - * UART0,UART1. - * @param NewState: New state of the UART channel in IDLE. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_SetTxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(UARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState == ENABLE) { - /* Set SCxDMA to enable UARTx DMA Request */ - UARTx->DMA |= DMA_EN0_SET; - } else { - /* Clear SCxDMA to disable UARTx DMA Request */ - UARTx->DMA &= DMA_EN0_CLEAR; - } -} - -/** - * @brief Selects input clock for prescaler. - * @param SIOx: Select the SIO channel. - * This parameter can be one of the following values: - * SIO0,SIO1. - * @param clock: Selects input clock for prescaler as PhiT0/2 or PhiT0. - * This parameter can be: - * SIO_CLOCK_T0_HALF (PhiT0/2)or SIO_CLOCK_T0(PhiT0) - * @retval None - * @note SIO_SetInputClock need to use before SIO_Init. - */ -void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock) -{ - uint32_t tmp = 0U; - assert_param(IS_SIO_PERIPH(SIOx)); - assert_param(IS_SIO_CLOCK(Clock)); - - tmp = SIOx->EN; - tmp &= EN_BRCKSEL_MASK; - tmp |= Clock; - SIOx->EN = tmp; -} - -/** - * @brief Enable the specified SIO channel. - * @param SIOx: Select the SIO channel. - * This parameter can be one of the following values: - * SIO0,SIO1. - * @retval None - */ -void SIO_Enable(TSB_SC_TypeDef * SIOx) -{ - /* Check the parameters */ - assert_param(IS_SIO_PERIPH(SIOx)); - /* Set SCxEN to enable SIOx */ - SIOx->EN |= EN_SIOE_SET; -} - -/** - * @brief Disable the specified SIO channel. - * @param SIOx: Select the SIO channel. - * This parameter can be one of the following values: - * SIO0,SIO1. - * @retval None - */ -void SIO_Disable(TSB_SC_TypeDef * SIOx) -{ - /* Check the parameters */ - assert_param(IS_SIO_PERIPH(SIOx)); - /* Clear SCxEN to disable SIOx */ - SIOx->EN &= EN_SIOE_CLEAR; -} - -/** - * @brief Get received data of the specified SIO channel. - * @param SIOx: Select the SIO channel. - * This parameter can be one of the following values: - * SIO0,SIO1. - * @retval The received data - */ -uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx) -{ - uint8_t retval = 0U; - /* Check the parameters */ - assert_param(IS_SIO_PERIPH(SIOx)); - - /* Return received data */ - retval = (uint8_t) SIOx->BUF; - - return retval; -} - -/** - * @brief Set data to be sent and start transmitting via the specified - SIO channel. - * @param SIOx: Select the SIO channel. - * This parameter can be one of the following values: - * SIO0,SIO1. - * @param Data: the data to be sent. - * @retval None - */ -void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_SIO_PERIPH(SIOx)); - - SIOx->BUF = (uint32_t) Data; -} - -/** - * @brief Initialize the specified SIO channel. - * @param SIOx: Select the SIO channel. - * This parameter can be one of the following values: - * SIO0,SIO1. - * @param IOClkSel: Selecting clock. - * This parameter can be one of the following values: - * SIO_CLK_SCLKOUTPUT or SIO_CLK_SCLKINPUT. - * @param InitStruct: The structure containing basic SIO configuration. - * @retval None - * @note SIO_SetInputClock need to use before SIO_Init. - */ -void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_POINTER_NOT_NULL(InitStruct)); - assert_param(IS_SIO_PERIPH(SIOx)); - assert_param(IS_SIO_CLK_SEL(IOClkSel)); - assert_param(IS_SIO_SCLKS_TRXD(InitStruct->InputClkEdge)); - assert_param(IS_SIO_TIDLE_LEVEL(InitStruct->TIDLE)); - assert_param(IS_SIO_TRANSFER_MODE(InitStruct->TransferMode)); - assert_param(IS_SIO_TRANS_DIR(InitStruct->TransferDir)); - assert_param(IS_SIO_MODE(InitStruct->Mode)); - assert_param(IS_SIO_WBUF_SET(InitStruct->DoubleBuffer)); - if (IOClkSel == SIO_CLK_SCLKINPUT) { - /* Only used for SCLK pin input mode */ - assert_param(IS_SIO_TXDEMP_LEVEL(InitStruct->TXDEMP)); - assert_param(IS_SIO_EHOLD_TIME(InitStruct->EHOLDTime)); - } else { - /* Only used for baud rate generator(SCLK pin output) mode */ - assert_param(IS_SIO_SINT_TIME(InitStruct->IntervalTime)); - assert_param(IS_SIO_BR_CLOCK(InitStruct->BaudRateClock)); - assert_param(IS_SIO_BR_DIVIDER(InitStruct->Divider)); - } - - /* Configure the transfer mode to I/O interface mode */ - tmp = SIOx->MOD0; - tmp &= MOD0_SM_MASK; - SIOx->MOD0 = tmp; - - /* Selecting the clock(SCLK input or output),input clock edge - for I/O interface mode */ - tmp = SIOx->CR; - tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK); - tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE); - - /* Set status of TXDx pin when an under run error is occured - and The last bit hold time of TXDx pin in SCLK input mode */ - if (IOClkSel == SIO_CLK_SCLKINPUT) { - tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK); - tmp |= (InitStruct->TXDEMP | InitStruct->EHOLDTime); - } else { - /* Do nothing */ - } - SIOx->CR = tmp; - - /* Set the transfer mode and interval time */ - tmp = SIOx->MOD1; - tmp &= MOD1_FDPX_CLEAR; - tmp |= InitStruct->TransferMode; - /* Set the interval time that valid only for SCLK output mode and double - buffer is enabled */ - if ((IOClkSel == SIO_CLK_SCLKOUTPUT) && (InitStruct->DoubleBuffer == SIO_WBUF_ENABLE)) { - tmp &= MOD1_SINT_MASK; - tmp |= InitStruct->IntervalTime; - } else { - /* Do nothing */ - } - tmp &= MOD1_CLEAR; - SIOx->MOD1 = tmp; - - /* Set the transfer direction and double buffer */ - tmp = SIOx->MOD2; - tmp &= MOD2_DRCHG_MASK; - tmp &= MOD2_WBUF_MASK; - tmp |= (InitStruct->TransferDir | InitStruct->DoubleBuffer); - SIOx->MOD2 = tmp; - - /* Select the input clock for baud rate generator and setting - Division ratio "N" */ - tmp = SIOx->BRCR; - if (IOClkSel == SIO_CLK_SCLKOUTPUT) { - tmp &= BRCR_BRCK_MASK; - tmp &= BRCR_BRS_MASK; - tmp |= (InitStruct->BaudRateClock | InitStruct->Divider); - } else { - /* Do nothing */ - } - tmp &= BRCR_CLEAR; - SIOx->BRCR = tmp; - - /* Enable or disable transmission or reception and both */ - tmp = SIOx->MOD1; - switch (InitStruct->Mode) { - case SIO_ENABLE_RX: - SIOx->MOD0 |= InitStruct->Mode; - tmp &= MOD1_TXE_CLEAR; - break; - case SIO_ENABLE_TX: - tmp |= InitStruct->Mode; - SIOx->MOD0 &= MOD0_RXE_CLEAR; - break; - default: - SIOx->MOD0 |= SIO_ENABLE_RX; - tmp |= SIO_ENABLE_TX; - break; - } - tmp &= MOD1_CLEAR; - SIOx->MOD1 = tmp; -} - -/** @} */ -/* End of group UART_Exported_Functions */ - -/** @} */ -/* End of group UART */ - -/** @} */ -/* End of group TX00_Periph_Driver */ - -#endif /* defined(__TMPM066_UART_H)) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h deleted file mode 100644 index 0bb14ed38b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h +++ /dev/null @@ -1,100 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SERIAL_0 = 0, - SERIAL_1, - INVALID_SERIAL = (int)NC -} UARTName; - -typedef enum { - ADC_A0 = 0, - ADC_A1, - ADC_A2, - ADC_A3, - ADC_A4, - ADC_A5, - ADC_A6, - ADC_A7, - INVALID_ADC = (int)NC -} ADCName; - -typedef enum { - I2C_0 = 0, - I2C_1, - INVALID_I2C = (int)NC -} I2CName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - INVALID_PWM = (int)NC -} PWMName; - -typedef enum { - GPIO_IRQ_0 = 0, - GPIO_IRQ_1, - GPIO_IRQ_2, - GPIO_IRQ_3, - GPIO_IRQ_4, - GPIO_IRQ_5, - INVALID_GPIO_IRQ = (int)NC -} GPIO_IRQName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART SERIAL_0 - -#define MBED_UART0 PC2, PC3 -#define MBED_UART1 PE2, PE1 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 PC1, PC0 -#define MBED_I2C1 PG1, PG0 - -#define MBED_ANALOGIN0 A0 -#define MBED_ANALOGIN1 A1 -#define MBED_ANALOGIN2 A2 -#define MBED_ANALOGIN3 A3 -#define MBED_ANALOGIN4 A4 -#define MBED_ANALOGIN5 A5 - -#define MBED_PWMOUT0 PD1 -#define MBED_PWMOUT1 PD2 -#define MBED_PWMOUT2 PD3 -#define MBED_PWMOUT3 PF4 -#define MBED_PWMOUT4 PF5 -#define MBED_PWMOUT5 PJ0 -#define MBED_PWMOUT6 PJ1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h deleted file mode 100644 index 3a96aa4361..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h +++ /dev/null @@ -1,115 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF) -#define PIN_POS(X) ((uint32_t)(X) & 0x7) - -// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) -#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) -#define PIN_DIR(X) ((X) & 0xffff) - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INOUT -} PinDirection; - -typedef enum { - // TMPM066 Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, - PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PG0 = 6 << 3, PG1, - PH0 = 7 << 3, PH1, PH2, PH3, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, - - // Other mbed Pin Names - LED1 = PB0, - LED2 = PB1, - LED3 = LED1, - LED4 = LED2, - - // External data bus Pin Names - D0 = PE1, - D1 = PE2, - D2 = PE0, - D3 = PD1, - D4 = PJ1, - D5 = PD2, - D6 = PD3, - D7 = PJ2, - D8 = PJ3, - D9 = PF4, - D10 = PF0, - D11 = PF1, - D12 = PF2, - D13 = PF3, - D14 = PC1, - D15 = PC0, - - // Analogue out pins - A0 = PA2, - A1 = PA3, - A2 = PA4, - A3 = PA5, - A4 = PA6, - A5 = PA7, - - // DAP_UART - USBTX = PC2, - USBRX = PC3, - MBEDIF_TXD = USBTX, - MBEDIF_RXD = USBRX, - - // Switches - SW1 = PB2, - SW2 = PB3, - - // I2C pins - SDA = PC1, - SCL = PC0, - I2C_SDA = SDA, - I2C_SCL = SCL, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 0, - PullDown, - PullNone, - OpenDrain, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h deleted file mode 100644 index 97ab0cc533..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortC, - PortD, - PortE, - PortF, - PortG, - PortH, - PortJ -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c deleted file mode 100644 index 176a73483c..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c +++ /dev/null @@ -1,98 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogin_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" - -static uint8_t adc_reset_init = 0; // Is ADC Reset happened yet? -#define ADC_10BIT_RANGE 0x3FF - -static const PinMap PinMap_ADC[] = { - {PA0, ADC_A0, PIN_DATA(0, 0)}, - {PA1, ADC_A1, PIN_DATA(0, 0)}, - {PA2, ADC_A2, PIN_DATA(0, 0)}, - {PA3, ADC_A3, PIN_DATA(0, 0)}, - {PA4, ADC_A4, PIN_DATA(0, 0)}, - {PA5, ADC_A5, PIN_DATA(0, 0)}, - {PA6, ADC_A6, PIN_DATA(0, 0)}, - {PA7, ADC_A7, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Check that pin belong to ADC module - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // enable clock supply to ADC - CG_SetFcPeriphA(CG_FC_PERIPH_ADC, ENABLE); - CG_SetADCClkSupply(ENABLE); - // Set pin function as ADC - pinmap_pinout(pin, PinMap_ADC); - if (!adc_reset_init) { - // Software reset ADC - ADC_SWReset(); - adc_reset_init = 1; - } - // Set sample hold time and pre-scale clock - ADC_SetClk(ADC_CONVERSION_81_CLOCK, ADC_FC_DIVIDE_LEVEL_8); - // Set input channel - ADC_SetInputChannel(obj->adc); - // Turn VREF on - ADC_SetVref(ENABLE); - // Use fixed-channel single conversion mode - ADC_SetRepeatMode(DISABLE); - ADC_SetScanMode(DISABLE); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - ADC_ResultTypeDef ret; - - // Assert that ADC channel is valid - MBED_ASSERT(obj->adc != (ADCName) NC); - - // Set input channel - ADC_SetInputChannel(obj->adc); - // Enable Vref - ADC_SetVref(ENABLE); - // Wait at least 3us to ensure the voltage is stable - wait_us(10U); - // Start ADC conversion - ADC_Start(); - // Wait until AD conversion complete - while (ADC_GetConvertState().Bit.NormalComplete != 1) { - // Do nothing - } - // Convert result - ret = ADC_GetConvertResult(obj->adc); - // Disable Vref to go into standby mode - ADC_SetVref(DISABLE); - return (uint16_t)ret.ADCResultValue; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return (float)(value * (1.0f / (float)ADC_10BIT_RANGE)); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h deleted file mode 100644 index 73b9c874f9..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h +++ /dev/null @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 32 - -#include "objects.h" -#include - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h deleted file mode 100644 index 75017f2f05..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h +++ /dev/null @@ -1,2287 +0,0 @@ -/** - ******************************************************************************* - * @file TMPM066.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM066' Device Series - * @version V2.0.2.2 (Tentative) - * @date 2016/02/15 - * - *(C)Copyright TOSHIBA CORPORATION 2016 All rights reserved - ******************************************************************************* - */ - -/** @addtogroup TOSHIBA_TX00_MICROCONTROLLER - * @{ - */ - -/** @addtogroup TMPM066 - * @{ - */ - -#ifndef __TMPM066_H__ -#define __TMPM066_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/** Interrupt Number Definition */ - typedef enum IRQn { -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** TMPM066 Specific Interrupt Numbers *******************************************************************/ - INT0_IRQn = 0, /*!< Interrupt Pin0 */ - INT1_IRQn = 1, /*!< Interrupt Pin1 */ - INT2_IRQn = 2, /*!< Interrupt Pin2 */ - INT3_IRQn = 3, /*!< Interrupt Pin3 */ - INT4_IRQn = 4, /*!< Interrupt Pin4 */ - INT5_IRQn = 5, /*!< Interrupt Pin5 */ - INTRX0_IRQn = 6, /*!< Serial reception interrupt(channel0) */ - INTTX0_IRQn = 7, /*!< Serial transmission interrupt(channel0) */ - INTRX1_IRQn = 8, /*!< Serial reception interrupt(channel1) */ - INTTX1_IRQn = 9, /*!< Serial transmission interrupt(channel1) */ - INTSPIRX_IRQn = 10, /*!< SPI serial reception interrupt */ - INTSPITX_IRQn = 11, /*!< SPI serial transmission interrupt */ - INTSPIERR_IRQn = 12, /*!< SPI serial error interrupt */ - INTI2C0_IRQn = 13, /*!< Serial bus interface (channel.0) */ - INTI2C1_IRQn = 14, /*!< Serial bus interface (channel.1) */ - INTDMA_IRQn = 15, /*!< DMAC interrupt */ - INT16A0_IRQn = 16, /*!< 16-bit TMR16A match detection (channel.0) */ - INT16A1_IRQn = 17, /*!< 16-bit TMR16A match detection (channel.1) */ - INTTB0_IRQn = 18, /*!< 16-bit TMRB interrupt(channel.0) */ - INTTB1_IRQn = 19, /*!< 16-bit TMRB interrupt(channel.1) */ - INTTB2_IRQn = 20, /*!< 16-bit TMRB interrupt(channel.2) */ - INTTB3_IRQn = 21, /*!< 16-bit TMRB interrupt(channel.3) */ - INTTB4_IRQn = 22, /*!< 16-bit TMRB interrupt(channel.4) */ - INTTB5_IRQn = 23, /*!< 16-bit TMRB interrupt(channel.5) */ - INTTB6_IRQn = 24, /*!< 16-bit TMRB interrupt(channel.6) */ - INTTB7_IRQn = 25, /*!< 16-bit TMRB interrupt(channel.7) */ - INTI2CS_IRQn = 26, /*!< Serial bus interface for Wakeup(channel.1) */ - INTTMRD_IRQn = 27, /*!< TMRD interrupt */ - INTUSB_IRQn = 28, /*!< USB interrupt */ - INTUSBWKUP_IRQn = 29, /*!< USB wakeup interrupt */ - INTADHP_IRQn = 30, /*!< High Priority A/D conversion interrupt */ - INTAD_IRQn = 31 /*!< Normal A/D conversion completion interrupt */ - } IRQn_Type; - -/** Processor and Core Peripheral Section */ - -/* Configuration of the Cortex-M0 Processor and Core Peripherals */ -#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - /** @} *//* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_TMPM066.h" /* TMPM066 System */ - -/** @addtogroup Device_Peripheral_registers - * @{ - */ - -/** Device Specific Peripheral registers structures */ - -/** - * @brief UDC2 AHB Bridge - */ - typedef struct { - __IO uint32_t INTSTS; /*!< Interrupt Status Register */ - __IO uint32_t INTENB; /*!< Interrupt Enable Register */ - __IO uint32_t MWTOUT; /*!< Master Write Timeout Register */ - __IO uint32_t C2STSET; /*!< UDC2 setting */ - __IO uint32_t MSTSET; /*!< DMAC setting */ - __IO uint32_t DMACRDREQ; /*!< DMAC Read request */ - __I uint32_t DMACRDVL; /*!< DMAC Read Value */ - __IO uint32_t UDC2RDREQ; /*!< UDC2 Read Request */ - __I uint32_t UDC2RDVL; /*!< UDC2 Read Value */ - uint32_t RESERVED0[6]; - __IO uint32_t ARBTSET; /*!< Arbiter Setting */ - __IO uint32_t MWSADR; /*!< Master Write Start Address */ - __IO uint32_t MWEADR; /*!< Master Write End Address */ - __I uint32_t MWCADR; /*!< Master Write Current Address */ - __I uint32_t MWAHBADR; /*!< Master Write AHB Address */ - __IO uint32_t MRSADR; /*!< Master Read Start Address */ - __IO uint32_t MREADR; /*!< Master Read End Address */ - __I uint32_t MRCADR; /*!< Master Read Current Address */ - __I uint32_t MRAHBADR; /*!< Master Read AHB Address */ - uint32_t RESERVED1[8]; - __IO uint32_t PWCTL; /*!< Power Detect Control */ - __I uint32_t MSTSTS; /*!< Master Status */ - __I uint32_t TOUTCNT; /*!< Timeout Count */ - } TSB_UDFS_TypeDef; - -/** - * @brief UDC2(USB -Spec2.0 Device contoller) - */ - typedef struct { - __IO uint32_t ADR; /*!< UDC2 Address State */ - __IO uint32_t FRM; /*!< UDC2 Frame */ - uint32_t RESERVED0; - __IO uint32_t CMD; /*!< UDC2 Command */ - __I uint32_t BRQ; /*!< UDC2 bRequest-bmRequest Type */ - __I uint32_t WVL; /*!< UDC2 wValue */ - __I uint32_t WIDX; /*!< UDC2 wIndex */ - __I uint32_t WLGTH; /*!< UDC2 wLength */ - __IO uint32_t INT; /*!< UDC2 INT */ - __IO uint32_t INTEP; /*!< UDC2 INT_EP */ - __IO uint32_t INTEPMSK; /*!< UDC2 INT_EP_MASK */ - __IO uint32_t INTRX0; /*!< UDC2 INT RX DATA0 */ - __IO uint32_t EP0MSZ; /*!< UDC2 EP0 Max Packet Size */ - __I uint32_t EP0STS; /*!< UDC2 EP0 Status */ - __I uint32_t EP0DSZ; /*!< UDC2 EP0 Data Size */ - __IO uint32_t EP0FIFO; /*!< UDC2 EP0 FIFO */ - __IO uint32_t EP1MSZ; /*!< UDC2 EP1 Max Packet Size */ - __IO uint32_t EP1STS; /*!< UDC2 EP1 Status */ - __I uint32_t EP1DSZ; /*!< UDC2 EP1 Data Size */ - __IO uint32_t EP1FIFO; /*!< UDC2 EP1 FIFO */ - __IO uint32_t EP2MSZ; /*!< UDC2 EP2 Max Packet Size */ - __IO uint32_t EP2STS; /*!< UDC2 EP2 Status */ - __I uint32_t EP2DSZ; /*!< UDC2 EP2 Data Size */ - __IO uint32_t EP2FIFO; /*!< UDC2 EP2 FIFO */ - __IO uint32_t EP3MSZ; /*!< UDC2 EP3 Max Packet Size */ - __IO uint32_t EP3STS; /*!< UDC2 EP3 Status */ - __I uint32_t EP3DSZ; /*!< UDC2 EP3 Data Size */ - __IO uint32_t EP3FIFO; /*!< UDC2 EP3 FIFO */ - __IO uint32_t EP4MSZ; /*!< UDC2 EP4 Max Packet Size */ - __IO uint32_t EP4STS; /*!< UDC2 EP4 Status */ - __I uint32_t EP4DSZ; /*!< UDC2 EP4 Data Size */ - __IO uint32_t EP4FIFO; /*!< UDC2 EP4 FIFO */ - uint32_t RESERVED1[44]; - __IO uint32_t INTNAK; /*!< UDC2 INT NAK */ - __IO uint32_t INTNAKMSK; /*!< UDC2 INT NAK MASK */ - } TSB_UDFS2_TypeDef; - -/** - * @brief AO Area register1 - */ - typedef struct { - uint8_t RESERVED0[32]; - __IO uint8_t STOP2INT_032; /*!< STOP2INT I/F Control Register in AO Area */ - __IO uint8_t STOP2INT_033; /*!< STOP2INT I/F Control Register in AO Area */ - __IO uint8_t STOP2INT_034; /*!< STOP2INT I/F Control Register in AO Area */ - __IO uint8_t STOP2INT_035; /*!< STOP2INT I/F Control Register in AO Area */ - __IO uint8_t STOP2INT_036; /*!< STOP2INT I/F Control Register in AO Area */ - __IO uint8_t STOP2INT_037; /*!< STOP2INT I/F Control Register in AO Area */ - __IO uint8_t STOP2INT_038; /*!< STOP2INT I/F Control Register in AO Area */ - __IO uint8_t STOP2INT_039; /*!< STOP2INT I/F Control Register in AO Area */ - } TSB_INTIFAO_TypeDef; - -/** - * @brief AO Area register2 - */ - typedef struct { - uint8_t RESERVED0[2]; - __IO uint8_t RSTFLG; /*!< Reset Flag register */ - __IO uint8_t RSTFLG1; /*!< Reset Flag1 register */ - } TSB_AOREG_TypeDef; - -/** - * @brief I2C Wakeup I/F register - */ - typedef struct { - __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ - __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ - __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ - __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ - } TSB_I2CS_TypeDef; - -/** - * @brief DMA Controller - */ - typedef struct { - __I uint32_t STATUS; /*!< DMA Status Register */ - __O uint32_t CFG; /*!< DMA Configuration Register */ - __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ - __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base - Pointer Register */ - uint32_t RESERVED0; - __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ - __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ - __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ - __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ - __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ - __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ - __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ - __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ - __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ - __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ - __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ - uint32_t RESERVED1[3]; - __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ - } TSB_DMA_TypeDef; - -/** - * @brief Timer D (Unit0) - */ - typedef struct { - __O uint32_t RUN; /*!< Timer Run Register (Unit0) */ - __IO uint32_t CR; /*!< Timer Control Register (Unit0) */ - __IO uint32_t MOD; /*!< Timer Mode Register (Unit0) */ - __IO uint32_t DMA; /*!< DMA Request Enable Register (Unit0) */ - uint32_t RESERVED0; - __IO uint32_t RG0; /*!< Timer Register0 (Unit0) */ - __IO uint32_t RG1; /*!< Timer Register1 (Unit0) */ - __IO uint32_t RG2; /*!< Timer Register2 (Unit0) */ - __IO uint32_t RG3; /*!< Timer Register3 (Unit0) */ - __IO uint32_t RG4; /*!< Timer Register4 (Unit0) */ - __IO uint32_t RG5; /*!< Timer Register5 (Unit0) */ - uint32_t RESERVED1[13]; - __IO uint32_t HSWB0; /*!< H-SW Control Circuit Register Buffer0 (Unit0) */ - __IO uint32_t HSWB1; /*!< H-SW Control Circuit Register Buffer1 (Unit0) */ - uint32_t RESERVED2[43]; - __I uint32_t CP0; /*!< Compare Register0 (Unit0) */ - __I uint32_t CP1; /*!< Compare Register1 (Unit0) */ - __I uint32_t CP2; /*!< Compare Register2 (Unit0) */ - __I uint32_t CP3; /*!< Compare Register3 (Unit0) */ - __I uint32_t CP4; /*!< Compare Register4 (Unit0) */ - __I uint32_t CP5; /*!< Compare Register5 (Unit0) */ - uint32_t RESERVED3[13]; - __I uint32_t HSW0; /*!< H-SW Control Circuit Register (Unit0) */ - __I uint32_t HSW1; /*!< H-SW Control Circuit Register (Unit0) */ - } TSB_TD0_TypeDef; - -/** - * @brief Timer D common - */ - typedef struct { - __IO uint32_t BCR; /*!< Update Flag Setting Register */ - uint32_t RESERVED0[3]; - __IO uint32_t EN; /*!< Timer Enable Register */ - __IO uint32_t CONF; /*!< Timer Configuration Register */ - } TSB_TD_TypeDef; - -/** - * @brief Timer D (Unit1) - */ - typedef struct { - __IO uint32_t RG0; /*!< Timer Register0 (Unit1) */ - __IO uint32_t RG1; /*!< Timer Register1 (Unit1) */ - __IO uint32_t RG2; /*!< Timer Register2 (Unit1) */ - __IO uint32_t RG3; /*!< Timer Register3 (Unit1) */ - __IO uint32_t RG4; /*!< Timer Register4 (Unit1) */ - uint32_t RESERVED0[10]; - __IO uint32_t HSWB0; /*!< H-SW Control Circuit Register Buffer0 (Unit1) */ - __IO uint32_t HSWB1; /*!< H-SW Control Circuit Register Buffer1 (Unit1) */ - uint32_t RESERVED1[36]; - __O uint32_t RUN; /*!< Timer Run Register (Unit1) */ - __IO uint32_t CR; /*!< Timer Control Register (Unit1) */ - __IO uint32_t MOD; /*!< Timer Mode Register (Unit1) */ - __IO uint32_t DMA; /*!< DMA Request Enable Register (Unit1) */ - uint32_t RESERVED2[7]; - __I uint32_t CP0; /*!< Compare Register0 (Unit1) */ - __I uint32_t CP1; /*!< Compare Register1 (Unit1) */ - __I uint32_t CP2; /*!< Compare Register2 (Unit1) */ - __I uint32_t CP3; /*!< Compare Register3 (Unit1) */ - __I uint32_t CP4; /*!< Compare Register4 (Unit1) */ - uint32_t RESERVED3[10]; - __I uint32_t HSW0; /*!< H-SW Control Circuit Register (Unit1) */ - __I uint32_t HSW1; /*!< H-SW Control Circuit Register (Unit1) */ - } TSB_TD1_TypeDef; - -/** - * @brief 16-bit TimerA - */ - typedef struct { - __IO uint32_t EN; /*!< Enable Register */ - __IO uint32_t RUN; /*!< RUN Register */ - __IO uint32_t CR; /*!< Control Register */ - __IO uint32_t RG; /*!< Timer Register */ - __I uint32_t CP; /*!< Capture Register */ - } TSB_T16A_TypeDef; - -/** - * @brief Serial Interface (TSPI) - */ - typedef struct { - __IO uint32_t CR0; /*!< TSPI Control Register 0 */ - __IO uint32_t CR1; /*!< TSPI Control Register 1 */ - __IO uint32_t CR2; /*!< TSPI Control Register 2 */ - __IO uint32_t CR3; /*!< TSPI Control Register 3 */ - __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ - __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ - __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ - uint32_t RESERVED0[57]; - __IO uint32_t DR; /*!< TSPI Data Register */ - uint32_t RESERVED1[63]; - __IO uint32_t SR; /*!< TSPI Status Register */ - __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ - } TSB_TSPI_TypeDef; - -#if defined ( __CC_ARM ) /* RealView Compiler */ -#pragma anon_unions -#elif (defined (__ICCARM__)) /* ICC Compiler */ -#pragma language=extended -#endif - -/** - * @brief I2C - */ - typedef struct { - __IO uint32_t CR1; /*!< I2C Control Register 1 */ - __IO uint32_t DBR; /*!< Data Buffer Register */ - __IO uint32_t AR; /*!< Bus address Register */ - union { - __O uint32_t CR2; /*!< Control Register 2 */ - __I uint32_t SR; /*!< Status Register */ - }; - __IO uint32_t PRS; /*!< Prescaler clcok setting Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t ST; /*!< Interrupt Register */ - __IO uint32_t OP; /*!< Optiononal Function register */ - __I uint32_t PM; /*!< Bus Monitor register */ - __IO uint32_t AR2; /*!< Second Slave address register */ - } TSB_I2C_TypeDef; - -/** - * @brief Port A - */ - typedef struct { - __IO uint32_t DATA; /*!< PA Data Register */ - __IO uint32_t CR; /*!< PA Control Register */ - __IO uint32_t FR1; /*!< PA Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PA Open Drain Control Register */ - __IO uint32_t PUP; /*!< PA Pull-up Control Register */ - __IO uint32_t PDN; /*!< PA Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PA Input Enable Control Register */ - } TSB_PA_TypeDef; - -/** - * @brief Port B - */ - typedef struct { - __IO uint32_t DATA; /*!< PB Data Register */ - __IO uint32_t CR; /*!< PB Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PB Open Drain Control Register */ - __IO uint32_t PUP; /*!< PB Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PB Input Enable Control Register */ - } TSB_PB_TypeDef; - -/** - * @brief Port C - */ - typedef struct { - __IO uint32_t DATA; /*!< PC Data Register */ - __IO uint32_t CR; /*!< PC Control Register */ - __IO uint32_t FR1; /*!< PC Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PC Open Drain Control Register */ - __IO uint32_t PUP; /*!< PC Pull-up Control Register */ - __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ - __IO uint32_t SEL; /*!< PC input voltage selection Register */ - __IO uint32_t IE; /*!< PC Input Enable Control Register */ - } TSB_PC_TypeDef; - -/** - * @brief Port D - */ - typedef struct { - __IO uint32_t DATA; /*!< PD Data Register */ - __IO uint32_t CR; /*!< PD Control Register */ - __IO uint32_t FR1; /*!< PD Function Register 1 */ - __IO uint32_t FR2; /*!< PD Function Register 2 */ - uint32_t RESERVED0[6]; - __IO uint32_t OD; /*!< PD Open Drain Control Register */ - __IO uint32_t PUP; /*!< PD Pull-up Control Register */ - __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ - __IO uint32_t SEL; /*!< PD input voltage selection Register */ - __IO uint32_t IE; /*!< PD Input Enable Control Register */ - } TSB_PD_TypeDef; - -/** - * @brief Port E - */ - typedef struct { - __IO uint32_t DATA; /*!< PE Data Register */ - __IO uint32_t CR; /*!< PE Control Register */ - __IO uint32_t FR1; /*!< PE Function Register 1 */ - __IO uint32_t FR2; /*!< PE Function Register 2 */ - uint32_t RESERVED0[6]; - __IO uint32_t OD; /*!< PE Open Drain Control Register */ - __IO uint32_t PUP; /*!< PE Pull-up Control Register */ - __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PE Input Enable Control Register */ - } TSB_PE_TypeDef; - -/** - * @brief Port F - */ - typedef struct { - __IO uint32_t DATA; /*!< PF Data Register */ - __IO uint32_t CR; /*!< PF Control Register */ - __IO uint32_t FR1; /*!< PF Function Register 1 */ - __IO uint32_t FR2; /*!< PF Function Register 2 */ - uint32_t RESERVED0[6]; - __IO uint32_t OD; /*!< PF Open Drain Control Register */ - __IO uint32_t PUP; /*!< PF Pull-up Control Register */ - __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PF Input Enable Control Register */ - } TSB_PF_TypeDef; - -/** - * @brief Port G - */ - typedef struct { - __IO uint32_t DATA; /*!< PG Data Register */ - __IO uint32_t CR; /*!< PG Control Register */ - __IO uint32_t FR1; /*!< PG Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PG Open Drain Control Register */ - __IO uint32_t PUP; /*!< PG Pull-up Control Register */ - __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ - __IO uint32_t SEL; /*!< PG input voltage selection Register */ - __IO uint32_t IE; /*!< PG Input Enable Control Register */ - } TSB_PG_TypeDef; - -/** - * @brief Port H - */ - typedef struct { - __IO uint32_t DATA; /*!< PH Data Register */ - __IO uint32_t CR; /*!< PH Control Register */ - __IO uint32_t FR1; /*!< PF Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PH Open Drain Control Register */ - __IO uint32_t PUP; /*!< PH Pull-up Control Register */ - __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PH Input Enable Control Register */ - } TSB_PH_TypeDef; - -/** - * @brief Port J - */ - typedef struct { - __IO uint32_t DATA; /*!< PJ Data Register */ - __IO uint32_t CR; /*!< PJ Control Register */ - __IO uint32_t FR1; /*!< PJ Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PJ Open Drain Control Register */ - __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ - __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PJ Input Enable Control Register */ - } TSB_PJ_TypeDef; - -/** - * @brief 16-bit Timer/Event Counter (TB) - */ - typedef struct { - __IO uint32_t EN; /*!< TB Enable Register */ - __IO uint32_t RUN; /*!< TB RUN Register */ - __IO uint32_t CR; /*!< TB Control Register */ - __IO uint32_t MOD; /*!< TB Mode Register */ - __IO uint32_t FFCR; /*!< TB Flip-Flop Control Register */ - __I uint32_t ST; /*!< TB Status Register */ - __IO uint32_t IM; /*!< TB Interrupt Mask Register */ - __I uint32_t UC; /*!< TB Read Capture Register */ - __IO uint32_t RG0; /*!< TB RG0 Timer Register */ - __IO uint32_t RG1; /*!< TB RG1 Timer Register */ - __I uint32_t CP0; /*!< TB CP0 Capture Register */ - __I uint32_t CP1; /*!< TB CP1 Capture Register */ - __IO uint32_t DMA; /*!< TB DMA Enable Register */ - } TSB_TB_TypeDef; - -/** - * @brief SC - */ - typedef struct { - __IO uint32_t EN; /*!< SC Enable Register */ - __IO uint32_t BUF; /*!< SC Buffer Register */ - __IO uint32_t CR; /*!< SC Control Register */ - __IO uint32_t MOD0; /*!< SC Mode Control Register 0 */ - __IO uint32_t BRCR; /*!< SC Baud Rate Generator Control Register */ - __IO uint32_t BRADD; /*!< SC Baud Rate Generator Control Register 2 */ - __IO uint32_t MOD1; /*!< SC Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< SC Mode Control Register 2 */ - __IO uint32_t RFC; /*!< SC RX FIFO Configuration Register */ - __IO uint32_t TFC; /*!< SC TX FIFO Configuration Register */ - __I uint32_t RST; /*!< SC RX FIFO Status Register */ - __I uint32_t TST; /*!< SC TX FIFO Status Register */ - __IO uint32_t FCNF; /*!< SC FIFO Configuration Register */ - __IO uint32_t DMA; /*!< SC DMA Request Register */ - } TSB_SC_TypeDef; - -/** - * @brief WDT - */ - typedef struct { - __IO uint32_t MOD; /*!< WD Mode Register */ - __O uint32_t CR; /*!< WD Control Register */ - __I uint32_t FLG; /*!< WD Flag Register */ - } TSB_WD_TypeDef; - -/** - * @brief CG - */ - typedef struct { - __IO uint32_t PROTECT; /*!< Protect Register */ - __IO uint32_t OSCCR; /*!< Oscillation Control Register */ - __IO uint32_t SYSCR; /*!< System clock control register */ - __IO uint32_t STBYCR; /*!< Standby Control Register */ - uint32_t RESERVED0[4]; - __IO uint32_t PLL0SEL; /*!< PLL select register for fsys */ - uint32_t RESERVED1[3]; - __IO uint32_t WUPHCR; /*!< Warmup register for HOSC */ - uint32_t RESERVED2[7]; - __IO uint32_t FSYSENA; /*!< output control register A for fsys clock */ - __O uint32_t FSYSENB; /*!< output control register B for fsys clock */ - uint32_t RESERVED3; - __IO uint32_t SPCLKEN; /*!< Output control register for ADC and TRACE CLOCK */ - __IO uint32_t EXTENDO0; /*!< Optional Function setting Register */ - } TSB_CG_TypeDef; - -/** - * @brief LVD - */ - typedef struct { - __IO uint32_t CR0; /*!< LVD Control register0 */ - __IO uint32_t CR1; /*!< LVD Control register1 */ - } TSB_LVD_TypeDef; - -/** - * @brief SD Area register1 - */ - typedef struct { - uint8_t RESERVED0[16]; - __IO uint8_t STOP1INT_016; /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */ - __IO uint8_t STOP1INT_017; /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_018; /*!< ILDEINT(NMI_WDT) I/F Control Register in SD Area */ - uint8_t RESERVED1[77]; - __IO uint8_t IDLEINT_096; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_097; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_098; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_099; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_100; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_101; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_102; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_103; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_104; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_105; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_106; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_107; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_108; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_109; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_110; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_111; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_112; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_113; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_114; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_115; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_116; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_117; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_118; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_119; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_120; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_121; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_122; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_123; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_124; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_125; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_126; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_127; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_128; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_129; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_130; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_131; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_132; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_133; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_134; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_135; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_136; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_137; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_138; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_139; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_140; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_141; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_142; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_143; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_144; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_145; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_146; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_147; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_148; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_149; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_150; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_151; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_152; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_153; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_154; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_155; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_156; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_157; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_158; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_159; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_160; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_161; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_162; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_163; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_164; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_165; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_166; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_167; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_168; /*!< IDLEINT I/F Control Register in SD Area */ - __IO uint8_t IDLEINT_169; /*!< IDLEINT I/F Control Register in SD Area */ - uint32_t RESERVED2[21]; - __I uint32_t FLAG0; /*!< NMI interrupt status flag register */ - __I uint32_t FLAG1; /*!< interrupt status flag register1 for AO area */ - uint32_t RESERVED3; - __I uint32_t FLAG3; /*!< interrupt status flag register3 for SD area */ - __I uint32_t FLAG4; /*!< interrupt status flag register4 for SD area */ - __I uint32_t FLAG5; /*!< interrupt status flag register5 for SD area */ - } TSB_INTIFSD_TypeDef; - -/** - * @brief ADC - */ - typedef struct { - __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ - __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ - __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ - __IO uint32_t MOD3; /*!< AD Mode Control Register 3 */ - __IO uint32_t MOD4; /*!< AD Mode Control Register 4 */ - __IO uint32_t MOD5; /*!< AD Mode Control Register 5 */ - __IO uint32_t MOD6; /*!< AD Mode Control Register 6 */ - uint32_t RESERVED0[4]; - __I uint32_t REG0; /*!< AD Conversion Result Register 0 */ - __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ - __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ - __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ - __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ - __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ - __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ - __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ - uint32_t RESERVED1[4]; - __I uint32_t REGSP; /*!< AD Conversion Result Register SP */ - __IO uint32_t CMP0; /*!< AD Conversion Result comparing register0 */ - __IO uint32_t CMP1; /*!< AD Conversion result comparing register1 */ - } TSB_AD_TypeDef; - -/** - * @brief FC - */ - typedef struct { - uint32_t RESERVED0[4]; - __IO uint32_t SECBIT; /*!< FC Security Bit Register */ - uint32_t RESERVED1[3]; - __I uint32_t SR; /*!< FC Flash Status Register */ - uint32_t RESERVED2[3]; - __I uint32_t PSRA; /*!< FC Protect status register */ - uint32_t RESERVED3; - __IO uint32_t PMRA; /*!< FC Protect Mask register */ - } TSB_FC_TypeDef; - - -/* Memory map */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x20000000UL) -#define PERI_BASE (0x40000000UL) - - -#define TSB_UDFS_BASE (PERI_BASE + 0x0008000UL) -#define TSB_UDFS2_BASE (PERI_BASE + 0x0008200UL) -#define TSB_INTIFAO_BASE (PERI_BASE + 0x0038000UL) -#define TSB_AOREG_BASE (PERI_BASE + 0x0038400UL) -#define TSB_I2CS_BASE (PERI_BASE + 0x0038800UL) -#define TSB_DMA_BASE (PERI_BASE + 0x004C000UL) -#define TSB_TD0_BASE (PERI_BASE + 0x0058000UL) -#define TSB_TD_BASE (PERI_BASE + 0x0058040UL) -#define TSB_TD1_BASE (PERI_BASE + 0x005802CUL) -#define TSB_T16A0_BASE (PERI_BASE + 0x008D000UL) -#define TSB_T16A1_BASE (PERI_BASE + 0x008E000UL) -#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) -#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) -#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) -#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) -#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) -#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) -#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) -#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) -#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) -#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) -#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) -#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) -#define TSB_TB0_BASE (PERI_BASE + 0x00C4000UL) -#define TSB_TB1_BASE (PERI_BASE + 0x00C4100UL) -#define TSB_TB2_BASE (PERI_BASE + 0x00C4200UL) -#define TSB_TB3_BASE (PERI_BASE + 0x00C4300UL) -#define TSB_TB4_BASE (PERI_BASE + 0x00C4400UL) -#define TSB_TB5_BASE (PERI_BASE + 0x00C4500UL) -#define TSB_TB6_BASE (PERI_BASE + 0x00C4600UL) -#define TSB_TB7_BASE (PERI_BASE + 0x00C4700UL) -#define TSB_SC0_BASE (PERI_BASE + 0x00E1000UL) -#define TSB_SC1_BASE (PERI_BASE + 0x00E1100UL) -#define TSB_WD_BASE (PERI_BASE + 0x00F2000UL) -#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) -#define TSB_LVD_BASE (PERI_BASE + 0x00F4000UL) -#define TSB_INTIFSD_BASE (PERI_BASE + 0x00F4E00UL) -#define TSB_AD_BASE (PERI_BASE + 0x00FC000UL) -#define TSB_FC_BASE (PERI_BASE + 0x1FFF000UL) - - -/* Peripheral declaration */ -#define TSB_UDFS (( TSB_UDFS_TypeDef *) TSB_UDFS_BASE) -#define TSB_UDFS2 (( TSB_UDFS2_TypeDef *) TSB_UDFS2_BASE) -#define TSB_INTIFAO ((TSB_INTIFAO_TypeDef *)TSB_INTIFAO_BASE) -#define TSB_AOREG (( TSB_AOREG_TypeDef *) TSB_AOREG_BASE) -#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) -#define TSB_DMA (( TSB_DMA_TypeDef *) TSB_DMA_BASE) -#define TSB_TD0 (( TSB_TD0_TypeDef *) TSB_TD0_BASE) -#define TSB_TD (( TSB_TD_TypeDef *) TSB_TD_BASE) -#define TSB_TD1 (( TSB_TD1_TypeDef *) TSB_TD1_BASE) -#define TSB_T16A0 (( TSB_T16A_TypeDef *) TSB_T16A0_BASE) -#define TSB_T16A1 (( TSB_T16A_TypeDef *) TSB_T16A1_BASE) -#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) -#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) -#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) -#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) -#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) -#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) -#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) -#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) -#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) -#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) -#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) -#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) -#define TSB_TB0 (( TSB_TB_TypeDef *) TSB_TB0_BASE) -#define TSB_TB1 (( TSB_TB_TypeDef *) TSB_TB1_BASE) -#define TSB_TB2 (( TSB_TB_TypeDef *) TSB_TB2_BASE) -#define TSB_TB3 (( TSB_TB_TypeDef *) TSB_TB3_BASE) -#define TSB_TB4 (( TSB_TB_TypeDef *) TSB_TB4_BASE) -#define TSB_TB5 (( TSB_TB_TypeDef *) TSB_TB5_BASE) -#define TSB_TB6 (( TSB_TB_TypeDef *) TSB_TB6_BASE) -#define TSB_TB7 (( TSB_TB_TypeDef *) TSB_TB7_BASE) -#define TSB_SC0 (( TSB_SC_TypeDef *) TSB_SC0_BASE) -#define TSB_SC1 (( TSB_SC_TypeDef *) TSB_SC1_BASE) -#define TSB_WD (( TSB_WD_TypeDef *) TSB_WD_BASE) -#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) -#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) -#define TSB_INTIFSD ((TSB_INTIFSD_TypeDef *)TSB_INTIFSD_BASE) -#define TSB_AD (( TSB_AD_TypeDef *) TSB_AD_BASE) -#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) - - -/* Bit-Band for Device Specific Peripheral Registers */ -#define BITBAND_OFFSET (0x02000000UL) -#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) -#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) - - - -/* UDC2 AHB Bridge */ -#define TSB_UDFS_INTSTS_INT_SETUP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,0))) -#define TSB_UDFS_INTSTS_INT_STATUS_NAK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,1))) -#define TSB_UDFS_INTSTS_INT_STATUS (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,2))) -#define TSB_UDFS_INTSTS_INT_RX_ZERO (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,3))) -#define TSB_UDFS_INTSTS_INT_SOF (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,4))) -#define TSB_UDFS_INTSTS_INT_EP0 (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,5))) -#define TSB_UDFS_INTSTS_INT_EP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,6))) -#define TSB_UDFS_INTSTS_INT_NAK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,7))) -#define TSB_UDFS_INTSTS_INT_SUSPEND_RESUME (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,8))) -#define TSB_UDFS_INTSTS_INT_USB_RESET (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,9))) -#define TSB_UDFS_INTSTS_INT_USB_RESET_END (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,10))) -#define TSB_UDFS_INTSTS_INT_MW_SET_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,17))) -#define TSB_UDFS_INTSTS_INT_MW_END_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,18))) -#define TSB_UDFS_INTSTS_INT_MW_TIMEOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,19))) -#define TSB_UDFS_INTSTS_INT_MW_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,20))) -#define TSB_UDFS_INTSTS_INT_MR_END_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,21))) -#define TSB_UDFS_INTSTS_INT_MR_EP_DSET (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,22))) -#define TSB_UDFS_INTSTS_INT_MR_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,23))) -#define TSB_UDFS_INTSTS_INT_UDC2_REGINT__RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,24))) -#define TSB_UDFS_INTSTS_INT_DMAC_REG_RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,25))) -#define TSB_UDFS_INTSTS_INT_POWERDETECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,28))) -#define TSB_UDFS_INTSTS_INT_MW_RERROR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,29))) -#define TSB_UDFS_INTENB_SUSPEND_RESUME_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,8))) -#define TSB_UDFS_INTENB_RESET_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,9))) -#define TSB_UDFS_INTENB_RESET_END_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,10))) -#define TSB_UDFS_INTENB_MW_SET_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,17))) -#define TSB_UDFS_INTENB_MW_END_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,18))) -#define TSB_UDFS_INTENB_MW_TIMEOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,19))) -#define TSB_UDFS_INTENB_MW_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,20))) -#define TSB_UDFS_INTENB_MR_END_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,21))) -#define TSB_UDFS_INTENB_MR_EP_DSET_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,22))) -#define TSB_UDFS_INTENB_MR_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,23))) -#define TSB_UDFS_INTENB_UDC2_REG_RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,24))) -#define TSB_UDFS_INTENB_DMAC_REG_RD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,25))) -#define TSB_UDFS_INTENB_POWER_DETECT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,28))) -#define TSB_UDFS_INTENB_MW_RERROR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,29))) -#define TSB_UDFS_MWTOUT_TIMEOUT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->MWTOUT,0))) -#define TSB_UDFS_C2STSET_TX0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,0))) -#define TSB_UDFS_C2STSET_EOPB_ENABLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,4))) -#define TSB_UDFS_DMACRDREQ_DMARDCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,30))) -#define TSB_UDFS_DMACRDREQ_DMARDREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,31))) -#define TSB_UDFS_UDC2RDREQ_UDC2RDCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,30))) -#define TSB_UDFS_UDC2RDREQ_UDC2RDREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,31))) -#define TSB_UDFS_ARBTSET_ABTMOD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,28))) -#define TSB_UDFS_ARBTSET_ABT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,31))) -#define TSB_UDFS_PWCTL_USB_RESET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,0))) -#define TSB_UDFS_PWCTL_PW_RESETB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,1))) -#define TSB_UDFS_PWCTL_PW_DETECT (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,2))) -#define TSB_UDFS_PWCTL_PHY_SUSPEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,3))) -#define TSB_UDFS_PWCTL_SUSPEND_X (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,4))) -#define TSB_UDFS_PWCTL_PHY_RESETB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,5))) -#define TSB_UDFS_PWCTL_PHY_REMOTE_WKUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,6))) -#define TSB_UDFS_PWCTL_WAKEUP_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,7))) -#define TSB_UDFS_MSTSTS_MWEPDSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,0))) -#define TSB_UDFS_MSTSTS_MREPDSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,1))) -#define TSB_UDFS_MSTSTS_MWBFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,2))) -#define TSB_UDFS_MSTSTS_MRBFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,3))) -#define TSB_UDFS_MSTSTS_MREPEMPTY (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,4))) - - -/* UDC2(USB -Spec2.0 Device contoller) */ -#define TSB_UDFS2_ADR_SUSPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,11))) -#define TSB_UDFS2_ADR_EP_BI_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,14))) -#define TSB_UDFS2_ADR_STAGE_ERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,15))) -#define TSB_UDFS2_FRM_CREATE_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->FRM,15))) -#define TSB_UDFS2_CMD_INT_TOGGLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->CMD,15))) -#define TSB_UDFS2_BRQ_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->BRQ,7))) -#define TSB_UDFS2_INT_I_SETUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,0))) -#define TSB_UDFS2_INT_I_STATUS_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,1))) -#define TSB_UDFS2_INT_I_STATUS (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,2))) -#define TSB_UDFS2_INT_I_RX_DATA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,3))) -#define TSB_UDFS2_INT_I_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,4))) -#define TSB_UDFS2_INT_I_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,5))) -#define TSB_UDFS2_INT_I_EP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,6))) -#define TSB_UDFS2_INT_I_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,7))) -#define TSB_UDFS2_INT_M_SETUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,8))) -#define TSB_UDFS2_INT_M_STATUS_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,9))) -#define TSB_UDFS2_INT_M_STATUS (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,10))) -#define TSB_UDFS2_INT_M_RX_DATA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,11))) -#define TSB_UDFS2_INT_M_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,12))) -#define TSB_UDFS2_INT_M_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,13))) -#define TSB_UDFS2_INT_M_EP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,14))) -#define TSB_UDFS2_INT_M_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,15))) -#define TSB_UDFS2_INTEP_I_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,1))) -#define TSB_UDFS2_INTEP_I_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,2))) -#define TSB_UDFS2_INTEP_I_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,3))) -#define TSB_UDFS2_INTEP_I_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,4))) -#define TSB_UDFS2_INTEPMSK_M_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,0))) -#define TSB_UDFS2_INTEPMSK_M_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,1))) -#define TSB_UDFS2_INTEPMSK_M_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,2))) -#define TSB_UDFS2_INTEPMSK_M_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,3))) -#define TSB_UDFS2_INTEPMSK_M_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,4))) -#define TSB_UDFS2_INTRX0_RX_D0_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,0))) -#define TSB_UDFS2_INTRX0_RX_D0_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,1))) -#define TSB_UDFS2_INTRX0_RX_D0_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,2))) -#define TSB_UDFS2_INTRX0_RX_D0_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,3))) -#define TSB_UDFS2_INTRX0_RX_D0_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,4))) -#define TSB_UDFS2_EP0MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,12))) -#define TSB_UDFS2_EP0MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,15))) -#define TSB_UDFS2_EP0STS_EP0_MASK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0STS,15))) -#define TSB_UDFS2_EP1MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,12))) -#define TSB_UDFS2_EP1MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,15))) -#define TSB_UDFS2_EP1STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,7))) -#define TSB_UDFS2_EP1STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,8))) -#define TSB_UDFS2_EP1STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,14))) -#define TSB_UDFS2_EP1STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,15))) -#define TSB_UDFS2_EP2MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,12))) -#define TSB_UDFS2_EP2MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,15))) -#define TSB_UDFS2_EP2STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,7))) -#define TSB_UDFS2_EP2STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,8))) -#define TSB_UDFS2_EP2STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,14))) -#define TSB_UDFS2_EP2STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,15))) -#define TSB_UDFS2_EP3MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,12))) -#define TSB_UDFS2_EP3MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,15))) -#define TSB_UDFS2_EP3STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,7))) -#define TSB_UDFS2_EP3STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,8))) -#define TSB_UDFS2_EP3STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,14))) -#define TSB_UDFS2_EP3STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,15))) -#define TSB_UDFS2_EP4MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,12))) -#define TSB_UDFS2_EP4MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,15))) -#define TSB_UDFS2_EP4STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,7))) -#define TSB_UDFS2_EP4STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,8))) -#define TSB_UDFS2_EP4STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,14))) -#define TSB_UDFS2_EP4STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,15))) -#define TSB_UDFS2_INTNAK_I_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,1))) -#define TSB_UDFS2_INTNAK_I_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,2))) -#define TSB_UDFS2_INTNAK_I_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,3))) -#define TSB_UDFS2_INTNAKMSK_M_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,1))) -#define TSB_UDFS2_INTNAKMSK_M_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,2))) -#define TSB_UDFS2_INTNAKMSK_M_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,3))) - - -/* AO Area register1 */ -#define TSB_INTIFAO_STOP2INT_032_INT032EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,0))) -#define TSB_INTIFAO_STOP2INT_032_INT032PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,4))) -#define TSB_INTIFAO_STOP2INT_032_INT032NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,5))) -#define TSB_INTIFAO_STOP2INT_032_INT032PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,6))) -#define TSB_INTIFAO_STOP2INT_032_INT032NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,7))) -#define TSB_INTIFAO_STOP2INT_033_INT033EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,0))) -#define TSB_INTIFAO_STOP2INT_033_INT033PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,4))) -#define TSB_INTIFAO_STOP2INT_033_INT033NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,5))) -#define TSB_INTIFAO_STOP2INT_033_INT033PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,6))) -#define TSB_INTIFAO_STOP2INT_033_INT033NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,7))) -#define TSB_INTIFAO_STOP2INT_034_INT034EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,0))) -#define TSB_INTIFAO_STOP2INT_034_INT034PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,4))) -#define TSB_INTIFAO_STOP2INT_034_INT034NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,5))) -#define TSB_INTIFAO_STOP2INT_034_INT034PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,6))) -#define TSB_INTIFAO_STOP2INT_034_INT034NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,7))) -#define TSB_INTIFAO_STOP2INT_035_INT035EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,0))) -#define TSB_INTIFAO_STOP2INT_035_INT035PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,4))) -#define TSB_INTIFAO_STOP2INT_035_INT035NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,5))) -#define TSB_INTIFAO_STOP2INT_035_INT035PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,6))) -#define TSB_INTIFAO_STOP2INT_035_INT035NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,7))) -#define TSB_INTIFAO_STOP2INT_036_INT036EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,0))) -#define TSB_INTIFAO_STOP2INT_036_INT036PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,4))) -#define TSB_INTIFAO_STOP2INT_036_INT036NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,5))) -#define TSB_INTIFAO_STOP2INT_036_INT036PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,6))) -#define TSB_INTIFAO_STOP2INT_036_INT036NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,7))) -#define TSB_INTIFAO_STOP2INT_037_INT037EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,0))) -#define TSB_INTIFAO_STOP2INT_037_INT037PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,4))) -#define TSB_INTIFAO_STOP2INT_037_INT037NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,5))) -#define TSB_INTIFAO_STOP2INT_037_INT037PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,6))) -#define TSB_INTIFAO_STOP2INT_037_INT037NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,7))) -#define TSB_INTIFAO_STOP2INT_038_INT038EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,0))) -#define TSB_INTIFAO_STOP2INT_038_INT038PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,4))) -#define TSB_INTIFAO_STOP2INT_038_INT038NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,5))) -#define TSB_INTIFAO_STOP2INT_038_INT038PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,6))) -#define TSB_INTIFAO_STOP2INT_038_INT038NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,7))) -#define TSB_INTIFAO_STOP2INT_039_INT039EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,0))) -#define TSB_INTIFAO_STOP2INT_039_INT039PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,4))) -#define TSB_INTIFAO_STOP2INT_039_INT039NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,5))) -#define TSB_INTIFAO_STOP2INT_039_INT039PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,6))) -#define TSB_INTIFAO_STOP2INT_039_INT039NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,7))) - - -/* AO Area register2 */ -#define TSB_AOREG_RSTFLG_PORF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,0))) -#define TSB_AOREG_RSTFLG_PINRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,3))) -#define TSB_AOREG_RSTFLG_LVDRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,5))) -#define TSB_AOREG_RSTFLG1_SYSRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,0))) -#define TSB_AOREG_RSTFLG1_WDTRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,2))) - - -/* I2C Wakeup I/F register */ -#define TSB_I2CS_WUPCR1_INTEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,0))) -#define TSB_I2CS_WUPCR1_GC (*((uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,1))) -#define TSB_I2CS_WUPCR1_RW (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,3))) -#define TSB_I2CS_WUPCR1_I2RES (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,4))) -#define TSB_I2CS_WUPCR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,5))) -#define TSB_I2CS_WUPCR1_SGCDI (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,6))) -#define TSB_I2CS_WUPCR1_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,7))) -#define TSB_I2CS_WUPCR3_WUPSA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR3,0))) -#define TSB_I2CS_WUPSL_WUPSA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,1))) -#define TSB_I2CS_WUPSL_WUPSA2 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,2))) - - -/* DMA Controller */ -#define TSB_DMA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMA->STATUS,0))) -#define TSB_DMA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMA->CFG,0))) -#define TSB_DMA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMA->ERRCLR,0))) - - -/* Timer D (Unit0) */ -#define TSB_TD0_RUN_TDRUN (*((__O uint32_t *)BITBAND_PERI(&TSB_TD0->RUN,0))) -#define TSB_TD0_CR_TDRDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,2))) -#define TSB_TD0_CR_TDMDPT00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,4))) -#define TSB_TD0_CR_TDMDPT01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,8))) -#define TSB_TD0_MOD_TDCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,4))) -#define TSB_TD0_MOD_TDIV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,6))) -#define TSB_TD0_MOD_TDIV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,7))) -#define TSB_TD0_DMA_DMAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->DMA,0))) -#define TSB_TD0_RG2_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG2,31))) -#define TSB_TD0_RG4_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG4,31))) -#define TSB_TD0_HSWB0_OUTV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB0,2))) -#define TSB_TD0_HSWB1_OUTV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB1,2))) -#define TSB_TD0_CP2_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->CP2,31))) -#define TSB_TD0_CP4_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->CP4,31))) -#define TSB_TD0_HSW0_OUTV0 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->HSW0,2))) -#define TSB_TD0_HSW1_OUTV1 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->HSW1,2))) - - -/* Timer D common */ -#define TSB_TD_BCR_TDSFT00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,0))) -#define TSB_TD_BCR_TDSFT01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,1))) -#define TSB_TD_BCR_TDSFT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,2))) -#define TSB_TD_BCR_TDSFT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,3))) -#define TSB_TD_BCR_PHSCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,4))) -#define TSB_TD_EN_TDHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,5))) -#define TSB_TD_EN_TDEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,6))) -#define TSB_TD_EN_TDEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,7))) - - -/* Timer D (Unit1) */ -#define TSB_TD1_RG2_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG2,31))) -#define TSB_TD1_RG4_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG4,31))) -#define TSB_TD1_HSWB0_OUTV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB0,2))) -#define TSB_TD1_HSWB1_OUTV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB1,2))) -#define TSB_TD1_RUN_TDRUN (*((__O uint32_t *)BITBAND_PERI(&TSB_TD1->RUN,0))) -#define TSB_TD1_CR_TDRDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,2))) -#define TSB_TD1_CR_TDMDPT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,4))) -#define TSB_TD1_CR_TDMDPT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,8))) -#define TSB_TD1_MOD_TDCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,4))) -#define TSB_TD1_MOD_TDIV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,6))) -#define TSB_TD1_MOD_TDIV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,7))) -#define TSB_TD1_DMA_DMAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->DMA,0))) -#define TSB_TD1_CP2_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->CP2,31))) -#define TSB_TD1_CP4_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->CP4,31))) -#define TSB_TD1_HSW0_OUTV0 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->HSW0,2))) -#define TSB_TD1_HSW1_OUTV1 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->HSW1,2))) - - -/* 16-bit TimerA */ -#define TSB_T16A0_EN_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->EN,1))) -#define TSB_T16A0_RUN_RUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->RUN,0))) -#define TSB_T16A0_CR_CLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,0))) -#define TSB_T16A0_CR_FFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,7))) - -#define TSB_T16A1_EN_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->EN,1))) -#define TSB_T16A1_RUN_RUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->RUN,0))) -#define TSB_T16A1_CR_CLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,0))) -#define TSB_T16A1_CR_FFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,7))) - - -/* Serial Interface (TSPI) */ -#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) -#define TSB_TSPI0_CR1_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,8))) -#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) -#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) -#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) -#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) -#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) -#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) -#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) -#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) -#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) -#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) -#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) -#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) -#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) -#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,8))) -#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) -#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) -#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) -#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) -#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) -#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) -#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) -#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) -#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) -#define TSB_TSPI0_SR_INTTXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) -#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) -#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) -#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) -#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,9))) -#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,10))) -#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,11))) - - -/* I2C */ -#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) -#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) -#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) -#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) -#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) -#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) -#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) -#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) -#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) -#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) -#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) -#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) -#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) -#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) -#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) -#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) -#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) -#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) -#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) -#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) -#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) -#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) -#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) -#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) -#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) -#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) -#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) -#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) -#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) -#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) -#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) -#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) -#define TSB_I2C0_OP_SAST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) -#define TSB_I2C0_OP_SA2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) -#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) -#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) -#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) - -#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) -#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) -#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) -#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) -#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) -#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) -#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) -#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) -#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) -#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) -#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) -#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) -#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) -#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) -#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) -#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) -#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) -#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) -#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) -#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) -#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) -#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) -#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) -#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) -#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) -#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) -#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) -#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) -#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) -#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) -#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) -#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) -#define TSB_I2C1_OP_SAST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) -#define TSB_I2C1_OP_SA2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) -#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) -#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) -#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) - - -/* Port A */ -#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) -#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) -#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) -#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) -#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) -#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) -#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) -#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) -#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) -#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) -#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) -#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) -#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) -#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) -#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) -#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) -#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) -#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) -#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) -#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) -#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) -#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) -#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) -#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) -#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) -#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) -#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) -#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) -#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) -#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) -#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) -#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) -#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) -#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) -#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) -#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) -#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) -#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) -#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) -#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) -#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) -#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) -#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) -#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) -#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) -#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) -#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) -#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) -#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) - - -/* Port B */ -#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) -#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) -#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) -#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) -#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) -#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) -#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) -#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) -#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) -#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) -#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) -#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) -#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) -#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) -#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) -#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) -#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) -#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) -#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) -#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) -#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) -#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) -#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) -#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) - - -/* Port C */ -#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) -#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) -#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) -#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) -#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) -#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) -#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) -#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) -#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) -#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) -#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) -#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) -#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) -#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) -#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) -#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) -#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) -#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) -#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) -#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) -#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) -#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) -#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) -#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) -#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) -#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) -#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) -#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) -#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) -#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) -#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) -#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) -#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) -#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) -#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) -#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) -#define TSB_PC_SEL_PC0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,0))) -#define TSB_PC_SEL_PC1SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,1))) -#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) -#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) -#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) -#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) -#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) -#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) - - -/* Port D */ -#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) -#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) -#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) -#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) -#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) -#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) -#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) -#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) -#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) -#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) -#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) -#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) -#define TSB_PD_FR1_PD0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0))) -#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1))) -#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) -#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) -#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4))) -#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0))) -#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1))) -#define TSB_PD_FR2_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,2))) -#define TSB_PD_FR2_PD3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,3))) -#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) -#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) -#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) -#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) -#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) -#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) -#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) -#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) -#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) -#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) -#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) -#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) -#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) -#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) -#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) -#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) -#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) -#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) -#define TSB_PD_SEL_PD4SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,4))) -#define TSB_PD_SEL_PD5SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,5))) -#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) -#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) -#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) -#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) -#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) -#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) - - -/* Port E */ -#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) -#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) -#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) -#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) -#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) -#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) -#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) -#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) -#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) -#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) -#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) -#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) -#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0))) -#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1))) -#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2))) -#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3))) -#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4))) -#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5))) -#define TSB_PE_FR2_PE1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,1))) -#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) -#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) -#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) -#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) -#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) -#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) -#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) -#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) -#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) -#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) -#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) -#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) -#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) -#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) -#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) -#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) -#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) -#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) -#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) -#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) -#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) -#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) -#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) -#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) - - -/* Port F */ -#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) -#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) -#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) -#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) -#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) -#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) -#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) -#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) -#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) -#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) -#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) -#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) -#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) -#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) -#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) -#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) -#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) -#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) -#define TSB_PF_FR1_PF2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,2))) -#define TSB_PF_FR1_PF3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,3))) -#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) -#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5))) -#define TSB_PF_FR2_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,0))) -#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) -#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) -#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) -#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) -#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) -#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) -#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) -#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) -#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) -#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) -#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) -#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) -#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) -#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) -#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) -#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) -#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) -#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) -#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) -#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) -#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) -#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) -#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) -#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) -#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) -#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) -#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) -#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) -#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) -#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) -#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) -#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) - - -/* Port G */ -#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) -#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) -#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) -#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) -#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0))) -#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) -#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) -#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) -#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) -#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) -#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) -#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) -#define TSB_PG_SEL_PG0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,0))) -#define TSB_PG_SEL_PG1SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,1))) -#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) -#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) - - -/* Port H */ -#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) -#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) -#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) -#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) -#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0))) -#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1))) -#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2))) -#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3))) -#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0))) -#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1))) -#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2))) -#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3))) -#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0))) -#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1))) -#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2))) -#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3))) -#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0))) -#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1))) -#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2))) -#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3))) -#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) -#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) -#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) -#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) -#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) -#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) -#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) -#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) - - -/* Port J */ -#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) -#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) -#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) -#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) -#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) -#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) -#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) -#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) -#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) -#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) -#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) -#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) -#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) -#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) -#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) -#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) -#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) -#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) -#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) -#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) -#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) -#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) -#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) -#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) -#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) -#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) - - -/* 16-bit Timer/Event Counter (TB) */ -#define TSB_TB0_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,6))) -#define TSB_TB0_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,7))) -#define TSB_TB0_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,0))) -#define TSB_TB0_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,2))) -#define TSB_TB0_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,0))) -#define TSB_TB0_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,1))) -#define TSB_TB0_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,5))) -#define TSB_TB0_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,7))) -#define TSB_TB0_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,3))) -#define TSB_TB0_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,6))) -#define TSB_TB0_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,2))) -#define TSB_TB0_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,3))) -#define TSB_TB0_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,4))) -#define TSB_TB0_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,5))) -#define TSB_TB0_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,0))) -#define TSB_TB0_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,1))) -#define TSB_TB0_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,2))) -#define TSB_TB0_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,0))) -#define TSB_TB0_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,1))) -#define TSB_TB0_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,2))) - -#define TSB_TB1_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,6))) -#define TSB_TB1_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,7))) -#define TSB_TB1_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,0))) -#define TSB_TB1_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,2))) -#define TSB_TB1_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,0))) -#define TSB_TB1_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,1))) -#define TSB_TB1_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,5))) -#define TSB_TB1_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,7))) -#define TSB_TB1_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,3))) -#define TSB_TB1_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,6))) -#define TSB_TB1_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,2))) -#define TSB_TB1_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,3))) -#define TSB_TB1_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,4))) -#define TSB_TB1_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,5))) -#define TSB_TB1_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,0))) -#define TSB_TB1_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,1))) -#define TSB_TB1_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,2))) -#define TSB_TB1_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,0))) -#define TSB_TB1_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,1))) -#define TSB_TB1_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,2))) - -#define TSB_TB2_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,6))) -#define TSB_TB2_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,7))) -#define TSB_TB2_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,0))) -#define TSB_TB2_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,2))) -#define TSB_TB2_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,0))) -#define TSB_TB2_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,1))) -#define TSB_TB2_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,5))) -#define TSB_TB2_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,7))) -#define TSB_TB2_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,3))) -#define TSB_TB2_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,6))) -#define TSB_TB2_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,2))) -#define TSB_TB2_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,3))) -#define TSB_TB2_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,4))) -#define TSB_TB2_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,5))) -#define TSB_TB2_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,0))) -#define TSB_TB2_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,1))) -#define TSB_TB2_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,2))) -#define TSB_TB2_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,0))) -#define TSB_TB2_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,1))) -#define TSB_TB2_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,2))) - -#define TSB_TB3_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,6))) -#define TSB_TB3_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,7))) -#define TSB_TB3_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,0))) -#define TSB_TB3_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,2))) -#define TSB_TB3_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,0))) -#define TSB_TB3_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,1))) -#define TSB_TB3_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,5))) -#define TSB_TB3_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,7))) -#define TSB_TB3_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,3))) -#define TSB_TB3_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,6))) -#define TSB_TB3_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,2))) -#define TSB_TB3_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,3))) -#define TSB_TB3_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,4))) -#define TSB_TB3_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,5))) -#define TSB_TB3_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,0))) -#define TSB_TB3_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,1))) -#define TSB_TB3_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,2))) -#define TSB_TB3_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,0))) -#define TSB_TB3_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,1))) -#define TSB_TB3_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,2))) - -#define TSB_TB4_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,6))) -#define TSB_TB4_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,7))) -#define TSB_TB4_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,0))) -#define TSB_TB4_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,2))) -#define TSB_TB4_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,0))) -#define TSB_TB4_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,1))) -#define TSB_TB4_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,5))) -#define TSB_TB4_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,7))) -#define TSB_TB4_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,3))) -#define TSB_TB4_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,6))) -#define TSB_TB4_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,2))) -#define TSB_TB4_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,3))) -#define TSB_TB4_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,4))) -#define TSB_TB4_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,5))) -#define TSB_TB4_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,0))) -#define TSB_TB4_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,1))) -#define TSB_TB4_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,2))) -#define TSB_TB4_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,0))) -#define TSB_TB4_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,1))) -#define TSB_TB4_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,2))) - -#define TSB_TB5_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,6))) -#define TSB_TB5_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,7))) -#define TSB_TB5_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,0))) -#define TSB_TB5_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,2))) -#define TSB_TB5_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,0))) -#define TSB_TB5_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,1))) -#define TSB_TB5_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,5))) -#define TSB_TB5_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,7))) -#define TSB_TB5_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,3))) -#define TSB_TB5_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,6))) -#define TSB_TB5_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,2))) -#define TSB_TB5_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,3))) -#define TSB_TB5_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,4))) -#define TSB_TB5_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,5))) -#define TSB_TB5_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,0))) -#define TSB_TB5_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,1))) -#define TSB_TB5_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,2))) -#define TSB_TB5_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,0))) -#define TSB_TB5_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,1))) -#define TSB_TB5_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,2))) - -#define TSB_TB6_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,6))) -#define TSB_TB6_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,7))) -#define TSB_TB6_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,0))) -#define TSB_TB6_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,2))) -#define TSB_TB6_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,0))) -#define TSB_TB6_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,1))) -#define TSB_TB6_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,5))) -#define TSB_TB6_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,7))) -#define TSB_TB6_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,3))) -#define TSB_TB6_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,6))) -#define TSB_TB6_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,2))) -#define TSB_TB6_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,3))) -#define TSB_TB6_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,4))) -#define TSB_TB6_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,5))) -#define TSB_TB6_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,0))) -#define TSB_TB6_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,1))) -#define TSB_TB6_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,2))) -#define TSB_TB6_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,0))) -#define TSB_TB6_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,1))) -#define TSB_TB6_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,2))) - -#define TSB_TB7_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,6))) -#define TSB_TB7_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,7))) -#define TSB_TB7_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,0))) -#define TSB_TB7_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,2))) -#define TSB_TB7_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,0))) -#define TSB_TB7_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,1))) -#define TSB_TB7_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,5))) -#define TSB_TB7_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,7))) -#define TSB_TB7_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,3))) -#define TSB_TB7_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,6))) -#define TSB_TB7_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,2))) -#define TSB_TB7_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,3))) -#define TSB_TB7_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,4))) -#define TSB_TB7_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,5))) -#define TSB_TB7_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,0))) -#define TSB_TB7_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,1))) -#define TSB_TB7_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,2))) -#define TSB_TB7_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,0))) -#define TSB_TB7_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,1))) -#define TSB_TB7_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,2))) - - -/* SC */ -#define TSB_SC0_EN_SIOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,0))) -#define TSB_SC0_EN_BRCKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,1))) -#define TSB_SC0_MOD0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,4))) -#define TSB_SC0_MOD0_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,5))) -#define TSB_SC0_MOD0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,6))) -#define TSB_SC0_MOD0_TB8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,7))) -#define TSB_SC0_BRCR_BRADDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->BRCR,6))) -#define TSB_SC0_MOD1_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD1,4))) -#define TSB_SC0_MOD2_WBUF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,2))) -#define TSB_SC0_MOD2_DRCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,3))) -#define TSB_SC0_MOD2_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,4))) -#define TSB_SC0_MOD2_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,5))) -#define TSB_SC0_MOD2_RBFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,6))) -#define TSB_SC0_MOD2_TBEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,7))) -#define TSB_SC0_RST_ROR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->RST,7))) -#define TSB_SC0_TST_TUR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->TST,7))) -#define TSB_SC0_FCNF_CNFG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,0))) -#define TSB_SC0_FCNF_RXTXCNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,1))) -#define TSB_SC0_FCNF_RFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,2))) -#define TSB_SC0_FCNF_TFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,3))) -#define TSB_SC0_FCNF_RFST (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,4))) -#define TSB_SC0_DMA_DMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,0))) -#define TSB_SC0_DMA_DMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,1))) - -#define TSB_SC1_EN_SIOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,0))) -#define TSB_SC1_EN_BRCKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,1))) -#define TSB_SC1_MOD0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,4))) -#define TSB_SC1_MOD0_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,5))) -#define TSB_SC1_MOD0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,6))) -#define TSB_SC1_MOD0_TB8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,7))) -#define TSB_SC1_BRCR_BRADDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->BRCR,6))) -#define TSB_SC1_MOD1_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD1,4))) -#define TSB_SC1_MOD2_WBUF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,2))) -#define TSB_SC1_MOD2_DRCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,3))) -#define TSB_SC1_MOD2_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,4))) -#define TSB_SC1_MOD2_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,5))) -#define TSB_SC1_MOD2_RBFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,6))) -#define TSB_SC1_MOD2_TBEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,7))) -#define TSB_SC1_RST_ROR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->RST,7))) -#define TSB_SC1_TST_TUR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->TST,7))) -#define TSB_SC1_FCNF_CNFG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,0))) -#define TSB_SC1_FCNF_RXTXCNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,1))) -#define TSB_SC1_FCNF_RFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,2))) -#define TSB_SC1_FCNF_TFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,3))) -#define TSB_SC1_FCNF_RFST (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,4))) -#define TSB_SC1_DMA_DMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,0))) -#define TSB_SC1_DMA_DMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,1))) - - -/* WDT */ -#define TSB_WD_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,1))) -#define TSB_WD_MOD_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,7))) -#define TSB_WD_FLG_FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_WD->FLG,0))) - - -/* CG */ -#define TSB_CG_OSCCR_IOSCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) -#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) -#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) -#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) -#define TSB_CG_PLL0SEL_PPL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) -#define TSB_CG_PLL0SEL_PLL0ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) -#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) -#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) -#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) -#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) -#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) -#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) -#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) -#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) -#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) -#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) -#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) -#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) -#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) -#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) -#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) -#define TSB_CG_FSYSENB_IPENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,28))) -#define TSB_CG_FSYSENB_IPENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,29))) -#define TSB_CG_FSYSENB_IPENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,30))) -#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) -#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) -#define TSB_CG_EXTENDO0_USBENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,0))) -#define TSB_CG_EXTENDO0_USBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,1))) -#define TSB_CG_EXTENDO0_EHCLKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,4))) -#define TSB_CG_EXTENDO0_DCLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,5))) - - -/* LVD */ -#define TSB_LVD_CR0_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,0))) -#define TSB_LVD_CR0_INTSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,4))) -#define TSB_LVD_CR0_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,5))) -#define TSB_LVD_CR0_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,6))) -#define TSB_LVD_CR0_ST (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,7))) -#define TSB_LVD_CR1_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0))) -#define TSB_LVD_CR1_INTSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,4))) -#define TSB_LVD_CR1_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,5))) -#define TSB_LVD_CR1_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,6))) -#define TSB_LVD_CR1_ST (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,7))) - - -/* SD Area register1 */ -#define TSB_INTIFSD_STOP1INT_016_INT016EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,0))) -#define TSB_INTIFSD_STOP1INT_016_INT016PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,4))) -#define TSB_INTIFSD_STOP1INT_016_INT016NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,5))) -#define TSB_INTIFSD_STOP1INT_016_INT016PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,6))) -#define TSB_INTIFSD_STOP1INT_016_INT016NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,7))) -#define TSB_INTIFSD_STOP1INT_017_INT017EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,0))) -#define TSB_INTIFSD_STOP1INT_017_INT017PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,4))) -#define TSB_INTIFSD_STOP1INT_017_INT017NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,5))) -#define TSB_INTIFSD_STOP1INT_017_INT017PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,6))) -#define TSB_INTIFSD_STOP1INT_017_INT017NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,7))) -#define TSB_INTIFSD_IDLEINT_018_INT018EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,0))) -#define TSB_INTIFSD_IDLEINT_018_INT018PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,4))) -#define TSB_INTIFSD_IDLEINT_018_INT018NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,5))) -#define TSB_INTIFSD_IDLEINT_018_INT018PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,6))) -#define TSB_INTIFSD_IDLEINT_018_INT018NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,7))) -#define TSB_INTIFSD_IDLEINT_096_INT096EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,0))) -#define TSB_INTIFSD_IDLEINT_096_INT096PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,4))) -#define TSB_INTIFSD_IDLEINT_096_INT096NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,5))) -#define TSB_INTIFSD_IDLEINT_096_INT096PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,6))) -#define TSB_INTIFSD_IDLEINT_096_INT096NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,7))) -#define TSB_INTIFSD_IDLEINT_097_INT097EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,0))) -#define TSB_INTIFSD_IDLEINT_097_INT097PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,4))) -#define TSB_INTIFSD_IDLEINT_097_INT097NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,5))) -#define TSB_INTIFSD_IDLEINT_097_INT097PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,6))) -#define TSB_INTIFSD_IDLEINT_097_INT097NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,7))) -#define TSB_INTIFSD_IDLEINT_098_INT098EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,0))) -#define TSB_INTIFSD_IDLEINT_098_INT098PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,4))) -#define TSB_INTIFSD_IDLEINT_098_INT098NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,5))) -#define TSB_INTIFSD_IDLEINT_098_INT098PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,6))) -#define TSB_INTIFSD_IDLEINT_098_INT098NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,7))) -#define TSB_INTIFSD_IDLEINT_099_INT099EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,0))) -#define TSB_INTIFSD_IDLEINT_099_INT099PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,4))) -#define TSB_INTIFSD_IDLEINT_099_INT099NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,5))) -#define TSB_INTIFSD_IDLEINT_099_INT099PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,6))) -#define TSB_INTIFSD_IDLEINT_099_INT099NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,7))) -#define TSB_INTIFSD_IDLEINT_100_INT100EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,0))) -#define TSB_INTIFSD_IDLEINT_100_INT100PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,4))) -#define TSB_INTIFSD_IDLEINT_100_INT100NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,5))) -#define TSB_INTIFSD_IDLEINT_100_INT100PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,6))) -#define TSB_INTIFSD_IDLEINT_100_INT100NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,7))) -#define TSB_INTIFSD_IDLEINT_101_INT101EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,0))) -#define TSB_INTIFSD_IDLEINT_101_INT101PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,4))) -#define TSB_INTIFSD_IDLEINT_101_INT101NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,5))) -#define TSB_INTIFSD_IDLEINT_101_INT101PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,6))) -#define TSB_INTIFSD_IDLEINT_101_INT101NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,7))) -#define TSB_INTIFSD_IDLEINT_102_INT102EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,0))) -#define TSB_INTIFSD_IDLEINT_102_INT102PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,4))) -#define TSB_INTIFSD_IDLEINT_102_INT102NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,5))) -#define TSB_INTIFSD_IDLEINT_102_INT102PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,6))) -#define TSB_INTIFSD_IDLEINT_102_INT102NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,7))) -#define TSB_INTIFSD_IDLEINT_103_INT103EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,0))) -#define TSB_INTIFSD_IDLEINT_103_INT103PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,4))) -#define TSB_INTIFSD_IDLEINT_103_INT103NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,5))) -#define TSB_INTIFSD_IDLEINT_103_INT103PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,6))) -#define TSB_INTIFSD_IDLEINT_103_INT103NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,7))) -#define TSB_INTIFSD_IDLEINT_104_INT104EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,0))) -#define TSB_INTIFSD_IDLEINT_104_INT104PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,4))) -#define TSB_INTIFSD_IDLEINT_104_INT104NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,5))) -#define TSB_INTIFSD_IDLEINT_104_INT104PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,6))) -#define TSB_INTIFSD_IDLEINT_104_INT104NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,7))) -#define TSB_INTIFSD_IDLEINT_105_INT105EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,0))) -#define TSB_INTIFSD_IDLEINT_105_INT105PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,4))) -#define TSB_INTIFSD_IDLEINT_105_INT105NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,5))) -#define TSB_INTIFSD_IDLEINT_105_INT105PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,6))) -#define TSB_INTIFSD_IDLEINT_105_INT105NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,7))) -#define TSB_INTIFSD_IDLEINT_106_INT106EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,0))) -#define TSB_INTIFSD_IDLEINT_106_INT106PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,4))) -#define TSB_INTIFSD_IDLEINT_106_INT106NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,5))) -#define TSB_INTIFSD_IDLEINT_106_INT106PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,6))) -#define TSB_INTIFSD_IDLEINT_106_INT106NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,7))) -#define TSB_INTIFSD_IDLEINT_107_INT107EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,0))) -#define TSB_INTIFSD_IDLEINT_107_INT107PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,4))) -#define TSB_INTIFSD_IDLEINT_107_INT107NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,5))) -#define TSB_INTIFSD_IDLEINT_107_INT107PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,6))) -#define TSB_INTIFSD_IDLEINT_107_INT107NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,7))) -#define TSB_INTIFSD_IDLEINT_108_INT108EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,0))) -#define TSB_INTIFSD_IDLEINT_108_INT108PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,4))) -#define TSB_INTIFSD_IDLEINT_108_INT108NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,5))) -#define TSB_INTIFSD_IDLEINT_108_INT108PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,6))) -#define TSB_INTIFSD_IDLEINT_108_INT108NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,7))) -#define TSB_INTIFSD_IDLEINT_109_INT109EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,0))) -#define TSB_INTIFSD_IDLEINT_109_INT109PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,4))) -#define TSB_INTIFSD_IDLEINT_109_INT109NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,5))) -#define TSB_INTIFSD_IDLEINT_109_INT109PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,6))) -#define TSB_INTIFSD_IDLEINT_109_INT109NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,7))) -#define TSB_INTIFSD_IDLEINT_110_INT110EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,0))) -#define TSB_INTIFSD_IDLEINT_110_INT110PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,4))) -#define TSB_INTIFSD_IDLEINT_110_INT110NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,5))) -#define TSB_INTIFSD_IDLEINT_110_INT110PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,6))) -#define TSB_INTIFSD_IDLEINT_110_INT110NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,7))) -#define TSB_INTIFSD_IDLEINT_111_INT111EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,0))) -#define TSB_INTIFSD_IDLEINT_111_INT111PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,4))) -#define TSB_INTIFSD_IDLEINT_111_INT111NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,5))) -#define TSB_INTIFSD_IDLEINT_111_INT111PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,6))) -#define TSB_INTIFSD_IDLEINT_111_INT111NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,7))) -#define TSB_INTIFSD_IDLEINT_112_INT112EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,0))) -#define TSB_INTIFSD_IDLEINT_112_INT112PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,4))) -#define TSB_INTIFSD_IDLEINT_112_INT112NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,5))) -#define TSB_INTIFSD_IDLEINT_112_INT112PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,6))) -#define TSB_INTIFSD_IDLEINT_112_INT112NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,7))) -#define TSB_INTIFSD_IDLEINT_113_INT113EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,0))) -#define TSB_INTIFSD_IDLEINT_113_INT113PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,4))) -#define TSB_INTIFSD_IDLEINT_113_INT113NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,5))) -#define TSB_INTIFSD_IDLEINT_113_INT113PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,6))) -#define TSB_INTIFSD_IDLEINT_113_INT113NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,7))) -#define TSB_INTIFSD_IDLEINT_114_INT114EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,0))) -#define TSB_INTIFSD_IDLEINT_114_INT114PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,4))) -#define TSB_INTIFSD_IDLEINT_114_INT114NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,5))) -#define TSB_INTIFSD_IDLEINT_114_INT114PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,6))) -#define TSB_INTIFSD_IDLEINT_114_INT114NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,7))) -#define TSB_INTIFSD_IDLEINT_115_INT115EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,0))) -#define TSB_INTIFSD_IDLEINT_115_INT115PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,4))) -#define TSB_INTIFSD_IDLEINT_115_INT115NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,5))) -#define TSB_INTIFSD_IDLEINT_115_INT115PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,6))) -#define TSB_INTIFSD_IDLEINT_115_INT115NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,7))) -#define TSB_INTIFSD_IDLEINT_116_INT116EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,0))) -#define TSB_INTIFSD_IDLEINT_116_INT116PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,4))) -#define TSB_INTIFSD_IDLEINT_116_INT116NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,5))) -#define TSB_INTIFSD_IDLEINT_116_INT116PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,6))) -#define TSB_INTIFSD_IDLEINT_116_INT116NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,7))) -#define TSB_INTIFSD_IDLEINT_117_INT117EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,0))) -#define TSB_INTIFSD_IDLEINT_117_INT117PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,4))) -#define TSB_INTIFSD_IDLEINT_117_INT117NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,5))) -#define TSB_INTIFSD_IDLEINT_117_INT117PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,6))) -#define TSB_INTIFSD_IDLEINT_117_INT117NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,7))) -#define TSB_INTIFSD_IDLEINT_118_INT118EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,0))) -#define TSB_INTIFSD_IDLEINT_118_INT118PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,4))) -#define TSB_INTIFSD_IDLEINT_118_INT118NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,5))) -#define TSB_INTIFSD_IDLEINT_118_INT118PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,6))) -#define TSB_INTIFSD_IDLEINT_118_INT118NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,7))) -#define TSB_INTIFSD_IDLEINT_119_INT119EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,0))) -#define TSB_INTIFSD_IDLEINT_119_INT119PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,4))) -#define TSB_INTIFSD_IDLEINT_119_INT119NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,5))) -#define TSB_INTIFSD_IDLEINT_119_INT119PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,6))) -#define TSB_INTIFSD_IDLEINT_119_INT119NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,7))) -#define TSB_INTIFSD_IDLEINT_120_INT120EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,0))) -#define TSB_INTIFSD_IDLEINT_120_INT120PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,4))) -#define TSB_INTIFSD_IDLEINT_120_INT120NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,5))) -#define TSB_INTIFSD_IDLEINT_120_INT120PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,6))) -#define TSB_INTIFSD_IDLEINT_120_INT120NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,7))) -#define TSB_INTIFSD_IDLEINT_121_INT121EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,0))) -#define TSB_INTIFSD_IDLEINT_121_INT121PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,4))) -#define TSB_INTIFSD_IDLEINT_121_INT121NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,5))) -#define TSB_INTIFSD_IDLEINT_121_INT121PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,6))) -#define TSB_INTIFSD_IDLEINT_121_INT121NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,7))) -#define TSB_INTIFSD_IDLEINT_122_INT122EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,0))) -#define TSB_INTIFSD_IDLEINT_122_INT122PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,4))) -#define TSB_INTIFSD_IDLEINT_122_INT122NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,5))) -#define TSB_INTIFSD_IDLEINT_122_INT122PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,6))) -#define TSB_INTIFSD_IDLEINT_122_INT122NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,7))) -#define TSB_INTIFSD_IDLEINT_123_INT123EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,0))) -#define TSB_INTIFSD_IDLEINT_123_INT123PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,4))) -#define TSB_INTIFSD_IDLEINT_123_INT123NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,5))) -#define TSB_INTIFSD_IDLEINT_123_INT123PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,6))) -#define TSB_INTIFSD_IDLEINT_123_INT123NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,7))) -#define TSB_INTIFSD_IDLEINT_124_INT124EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,0))) -#define TSB_INTIFSD_IDLEINT_124_INT124PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,4))) -#define TSB_INTIFSD_IDLEINT_124_INT124NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,5))) -#define TSB_INTIFSD_IDLEINT_124_INT124PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,6))) -#define TSB_INTIFSD_IDLEINT_124_INT124NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,7))) -#define TSB_INTIFSD_IDLEINT_125_INT125EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,0))) -#define TSB_INTIFSD_IDLEINT_125_INT125PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,4))) -#define TSB_INTIFSD_IDLEINT_125_INT125NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,5))) -#define TSB_INTIFSD_IDLEINT_125_INT125PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,6))) -#define TSB_INTIFSD_IDLEINT_125_INT125NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,7))) -#define TSB_INTIFSD_IDLEINT_126_INT126EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,0))) -#define TSB_INTIFSD_IDLEINT_126_INT126PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,4))) -#define TSB_INTIFSD_IDLEINT_126_INT126NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,5))) -#define TSB_INTIFSD_IDLEINT_126_INT126PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,6))) -#define TSB_INTIFSD_IDLEINT_126_INT126NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,7))) -#define TSB_INTIFSD_IDLEINT_127_INT127EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,0))) -#define TSB_INTIFSD_IDLEINT_127_INT127PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,4))) -#define TSB_INTIFSD_IDLEINT_127_INT127NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,5))) -#define TSB_INTIFSD_IDLEINT_127_INT127PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,6))) -#define TSB_INTIFSD_IDLEINT_127_INT127NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,7))) -#define TSB_INTIFSD_IDLEINT_128_INT128EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,0))) -#define TSB_INTIFSD_IDLEINT_128_INT128PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,4))) -#define TSB_INTIFSD_IDLEINT_128_INT128NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,5))) -#define TSB_INTIFSD_IDLEINT_128_INT128PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,6))) -#define TSB_INTIFSD_IDLEINT_128_INT128NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,7))) -#define TSB_INTIFSD_IDLEINT_129_INT129EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,0))) -#define TSB_INTIFSD_IDLEINT_129_INT129PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,4))) -#define TSB_INTIFSD_IDLEINT_129_INT129NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,5))) -#define TSB_INTIFSD_IDLEINT_129_INT129PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,6))) -#define TSB_INTIFSD_IDLEINT_129_INT129NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,7))) -#define TSB_INTIFSD_IDLEINT_130_INT130EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,0))) -#define TSB_INTIFSD_IDLEINT_130_INT130PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,4))) -#define TSB_INTIFSD_IDLEINT_130_INT130NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,5))) -#define TSB_INTIFSD_IDLEINT_130_INT130PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,6))) -#define TSB_INTIFSD_IDLEINT_130_INT130NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,7))) -#define TSB_INTIFSD_IDLEINT_131_INT131EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,0))) -#define TSB_INTIFSD_IDLEINT_131_INT131PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,4))) -#define TSB_INTIFSD_IDLEINT_131_INT131NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,5))) -#define TSB_INTIFSD_IDLEINT_131_INT131PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,6))) -#define TSB_INTIFSD_IDLEINT_131_INT131NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,7))) -#define TSB_INTIFSD_IDLEINT_132_INT132EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,0))) -#define TSB_INTIFSD_IDLEINT_132_INT132PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,4))) -#define TSB_INTIFSD_IDLEINT_132_INT132NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,5))) -#define TSB_INTIFSD_IDLEINT_132_INT132PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,6))) -#define TSB_INTIFSD_IDLEINT_132_INT132NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,7))) -#define TSB_INTIFSD_IDLEINT_133_INT133EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,0))) -#define TSB_INTIFSD_IDLEINT_133_INT133PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,4))) -#define TSB_INTIFSD_IDLEINT_133_INT133NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,5))) -#define TSB_INTIFSD_IDLEINT_133_INT133PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,6))) -#define TSB_INTIFSD_IDLEINT_133_INT133NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,7))) -#define TSB_INTIFSD_IDLEINT_134_INT134EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,0))) -#define TSB_INTIFSD_IDLEINT_134_INT134PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,4))) -#define TSB_INTIFSD_IDLEINT_134_INT134NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,5))) -#define TSB_INTIFSD_IDLEINT_134_INT134PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,6))) -#define TSB_INTIFSD_IDLEINT_134_INT134NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,7))) -#define TSB_INTIFSD_IDLEINT_135_INT135EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,0))) -#define TSB_INTIFSD_IDLEINT_135_INT135PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,4))) -#define TSB_INTIFSD_IDLEINT_135_INT135NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,5))) -#define TSB_INTIFSD_IDLEINT_135_INT135PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,6))) -#define TSB_INTIFSD_IDLEINT_135_INT135NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,7))) -#define TSB_INTIFSD_IDLEINT_136_INT136EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,0))) -#define TSB_INTIFSD_IDLEINT_136_INT136PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,4))) -#define TSB_INTIFSD_IDLEINT_136_INT136NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,5))) -#define TSB_INTIFSD_IDLEINT_136_INT136PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,6))) -#define TSB_INTIFSD_IDLEINT_136_INT136NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,7))) -#define TSB_INTIFSD_IDLEINT_137_INT137EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,0))) -#define TSB_INTIFSD_IDLEINT_137_INT137PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,4))) -#define TSB_INTIFSD_IDLEINT_137_INT137NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,5))) -#define TSB_INTIFSD_IDLEINT_137_INT137PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,6))) -#define TSB_INTIFSD_IDLEINT_137_INT137NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,7))) -#define TSB_INTIFSD_IDLEINT_138_INT138EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,0))) -#define TSB_INTIFSD_IDLEINT_138_INT138PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,4))) -#define TSB_INTIFSD_IDLEINT_138_INT138NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,5))) -#define TSB_INTIFSD_IDLEINT_138_INT138PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,6))) -#define TSB_INTIFSD_IDLEINT_138_INT138NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,7))) -#define TSB_INTIFSD_IDLEINT_139_INT139EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,0))) -#define TSB_INTIFSD_IDLEINT_139_INT139PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,4))) -#define TSB_INTIFSD_IDLEINT_139_INT139NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,5))) -#define TSB_INTIFSD_IDLEINT_139_INT139PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,6))) -#define TSB_INTIFSD_IDLEINT_139_INT139NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,7))) -#define TSB_INTIFSD_IDLEINT_140_INT140EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,0))) -#define TSB_INTIFSD_IDLEINT_140_INT140PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,4))) -#define TSB_INTIFSD_IDLEINT_140_INT140NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,5))) -#define TSB_INTIFSD_IDLEINT_140_INT140PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,6))) -#define TSB_INTIFSD_IDLEINT_140_INT140NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,7))) -#define TSB_INTIFSD_IDLEINT_141_INT141EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,0))) -#define TSB_INTIFSD_IDLEINT_141_INT141PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,4))) -#define TSB_INTIFSD_IDLEINT_141_INT141NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,5))) -#define TSB_INTIFSD_IDLEINT_141_INT141PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,6))) -#define TSB_INTIFSD_IDLEINT_141_INT141NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,7))) -#define TSB_INTIFSD_IDLEINT_142_INT142EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,0))) -#define TSB_INTIFSD_IDLEINT_142_INT142PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,4))) -#define TSB_INTIFSD_IDLEINT_142_INT142NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,5))) -#define TSB_INTIFSD_IDLEINT_142_INT142PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,6))) -#define TSB_INTIFSD_IDLEINT_142_INT142NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,7))) -#define TSB_INTIFSD_IDLEINT_143_INT143EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,0))) -#define TSB_INTIFSD_IDLEINT_143_INT143PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,4))) -#define TSB_INTIFSD_IDLEINT_143_INT143NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,5))) -#define TSB_INTIFSD_IDLEINT_143_INT143PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,6))) -#define TSB_INTIFSD_IDLEINT_143_INT143NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,7))) -#define TSB_INTIFSD_IDLEINT_144_INT144EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,0))) -#define TSB_INTIFSD_IDLEINT_144_INT144PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,4))) -#define TSB_INTIFSD_IDLEINT_144_INT144NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,5))) -#define TSB_INTIFSD_IDLEINT_144_INT144PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,6))) -#define TSB_INTIFSD_IDLEINT_144_INT144NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,7))) -#define TSB_INTIFSD_IDLEINT_145_INT145EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,0))) -#define TSB_INTIFSD_IDLEINT_145_INT145PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,4))) -#define TSB_INTIFSD_IDLEINT_145_INT145NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,5))) -#define TSB_INTIFSD_IDLEINT_145_INT145PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,6))) -#define TSB_INTIFSD_IDLEINT_145_INT145NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,7))) -#define TSB_INTIFSD_IDLEINT_146_INT146EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,0))) -#define TSB_INTIFSD_IDLEINT_146_INT146PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,4))) -#define TSB_INTIFSD_IDLEINT_146_INT146NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,5))) -#define TSB_INTIFSD_IDLEINT_146_INT146PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,6))) -#define TSB_INTIFSD_IDLEINT_146_INT146NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,7))) -#define TSB_INTIFSD_IDLEINT_147_INT147EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,0))) -#define TSB_INTIFSD_IDLEINT_147_INT147PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,4))) -#define TSB_INTIFSD_IDLEINT_147_INT147NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,5))) -#define TSB_INTIFSD_IDLEINT_147_INT147PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,6))) -#define TSB_INTIFSD_IDLEINT_147_INT147NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,7))) -#define TSB_INTIFSD_IDLEINT_148_INT148EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,0))) -#define TSB_INTIFSD_IDLEINT_148_INT148PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,4))) -#define TSB_INTIFSD_IDLEINT_148_INT148NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,5))) -#define TSB_INTIFSD_IDLEINT_148_INT148PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,6))) -#define TSB_INTIFSD_IDLEINT_148_INT148NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,7))) -#define TSB_INTIFSD_IDLEINT_149_INT149EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,0))) -#define TSB_INTIFSD_IDLEINT_149_INT149PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,4))) -#define TSB_INTIFSD_IDLEINT_149_INT149NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,5))) -#define TSB_INTIFSD_IDLEINT_149_INT149PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,6))) -#define TSB_INTIFSD_IDLEINT_149_INT149NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,7))) -#define TSB_INTIFSD_IDLEINT_150_INT150EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,0))) -#define TSB_INTIFSD_IDLEINT_150_INT150PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,4))) -#define TSB_INTIFSD_IDLEINT_150_INT150NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,5))) -#define TSB_INTIFSD_IDLEINT_150_INT150PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,6))) -#define TSB_INTIFSD_IDLEINT_150_INT150NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,7))) -#define TSB_INTIFSD_IDLEINT_151_INT151EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,0))) -#define TSB_INTIFSD_IDLEINT_151_INT151PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,4))) -#define TSB_INTIFSD_IDLEINT_151_INT151NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,5))) -#define TSB_INTIFSD_IDLEINT_151_INT151PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,6))) -#define TSB_INTIFSD_IDLEINT_151_INT151NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,7))) -#define TSB_INTIFSD_IDLEINT_152_INT152EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,0))) -#define TSB_INTIFSD_IDLEINT_152_INT152PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,4))) -#define TSB_INTIFSD_IDLEINT_152_INT152NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,5))) -#define TSB_INTIFSD_IDLEINT_152_INT152PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,6))) -#define TSB_INTIFSD_IDLEINT_152_INT152NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,7))) -#define TSB_INTIFSD_IDLEINT_153_INT153EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,0))) -#define TSB_INTIFSD_IDLEINT_153_INT153PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,4))) -#define TSB_INTIFSD_IDLEINT_153_INT153NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,5))) -#define TSB_INTIFSD_IDLEINT_153_INT153PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,6))) -#define TSB_INTIFSD_IDLEINT_153_INT153NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,7))) -#define TSB_INTIFSD_IDLEINT_154_INT154EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,0))) -#define TSB_INTIFSD_IDLEINT_154_INT154PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,4))) -#define TSB_INTIFSD_IDLEINT_154_INT154NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,5))) -#define TSB_INTIFSD_IDLEINT_154_INT154PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,6))) -#define TSB_INTIFSD_IDLEINT_154_INT154NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,7))) -#define TSB_INTIFSD_IDLEINT_155_INT155EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,0))) -#define TSB_INTIFSD_IDLEINT_155_INT155PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,4))) -#define TSB_INTIFSD_IDLEINT_155_INT155NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,5))) -#define TSB_INTIFSD_IDLEINT_155_INT155PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,6))) -#define TSB_INTIFSD_IDLEINT_155_INT155NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,7))) -#define TSB_INTIFSD_IDLEINT_156_INT156EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,0))) -#define TSB_INTIFSD_IDLEINT_156_INT156PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,4))) -#define TSB_INTIFSD_IDLEINT_156_INT156NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,5))) -#define TSB_INTIFSD_IDLEINT_156_INT156PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,6))) -#define TSB_INTIFSD_IDLEINT_156_INT156NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,7))) -#define TSB_INTIFSD_IDLEINT_157_INT157EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,0))) -#define TSB_INTIFSD_IDLEINT_157_INT157PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,4))) -#define TSB_INTIFSD_IDLEINT_157_INT157NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,5))) -#define TSB_INTIFSD_IDLEINT_157_INT157PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,6))) -#define TSB_INTIFSD_IDLEINT_157_INT157NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,7))) -#define TSB_INTIFSD_IDLEINT_158_INT158EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,0))) -#define TSB_INTIFSD_IDLEINT_158_INT158PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,4))) -#define TSB_INTIFSD_IDLEINT_158_INT158NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,5))) -#define TSB_INTIFSD_IDLEINT_158_INT158PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,6))) -#define TSB_INTIFSD_IDLEINT_158_INT158NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,7))) -#define TSB_INTIFSD_IDLEINT_159_INT159EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,0))) -#define TSB_INTIFSD_IDLEINT_159_INT159PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,4))) -#define TSB_INTIFSD_IDLEINT_159_INT159NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,5))) -#define TSB_INTIFSD_IDLEINT_159_INT159PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,6))) -#define TSB_INTIFSD_IDLEINT_159_INT159NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,7))) -#define TSB_INTIFSD_IDLEINT_160_INT160EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,0))) -#define TSB_INTIFSD_IDLEINT_160_INT160PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,4))) -#define TSB_INTIFSD_IDLEINT_160_INT160NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,5))) -#define TSB_INTIFSD_IDLEINT_160_INT160PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,6))) -#define TSB_INTIFSD_IDLEINT_160_INT160NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,7))) -#define TSB_INTIFSD_IDLEINT_161_INT161EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,0))) -#define TSB_INTIFSD_IDLEINT_161_INT161PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,4))) -#define TSB_INTIFSD_IDLEINT_161_INT161NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,5))) -#define TSB_INTIFSD_IDLEINT_161_INT161PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,6))) -#define TSB_INTIFSD_IDLEINT_161_INT161NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,7))) -#define TSB_INTIFSD_IDLEINT_162_INT162EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,0))) -#define TSB_INTIFSD_IDLEINT_162_INT162PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,4))) -#define TSB_INTIFSD_IDLEINT_162_INT162NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,5))) -#define TSB_INTIFSD_IDLEINT_162_INT162PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,6))) -#define TSB_INTIFSD_IDLEINT_162_INT162NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,7))) -#define TSB_INTIFSD_IDLEINT_163_INT163EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,0))) -#define TSB_INTIFSD_IDLEINT_163_INT163PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,4))) -#define TSB_INTIFSD_IDLEINT_163_INT163NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,5))) -#define TSB_INTIFSD_IDLEINT_163_INT163PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,6))) -#define TSB_INTIFSD_IDLEINT_163_INT163NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,7))) -#define TSB_INTIFSD_IDLEINT_164_INT164EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,0))) -#define TSB_INTIFSD_IDLEINT_164_INT164PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,4))) -#define TSB_INTIFSD_IDLEINT_164_INT164NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,5))) -#define TSB_INTIFSD_IDLEINT_164_INT164PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,6))) -#define TSB_INTIFSD_IDLEINT_164_INT164NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,7))) -#define TSB_INTIFSD_IDLEINT_165_INT165EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,0))) -#define TSB_INTIFSD_IDLEINT_165_INT165PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,4))) -#define TSB_INTIFSD_IDLEINT_165_INT165NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,5))) -#define TSB_INTIFSD_IDLEINT_165_INT165PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,6))) -#define TSB_INTIFSD_IDLEINT_165_INT165NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,7))) -#define TSB_INTIFSD_IDLEINT_166_INT166EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,0))) -#define TSB_INTIFSD_IDLEINT_166_INT166PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,4))) -#define TSB_INTIFSD_IDLEINT_166_INT166NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,5))) -#define TSB_INTIFSD_IDLEINT_166_INT166PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,6))) -#define TSB_INTIFSD_IDLEINT_166_INT166NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,7))) -#define TSB_INTIFSD_IDLEINT_167_INT167EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,0))) -#define TSB_INTIFSD_IDLEINT_167_INT167PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,4))) -#define TSB_INTIFSD_IDLEINT_167_INT167NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,5))) -#define TSB_INTIFSD_IDLEINT_167_INT167PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,6))) -#define TSB_INTIFSD_IDLEINT_167_INT167NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,7))) -#define TSB_INTIFSD_IDLEINT_168_INT168EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,0))) -#define TSB_INTIFSD_IDLEINT_168_INT168PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,4))) -#define TSB_INTIFSD_IDLEINT_168_INT168NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,5))) -#define TSB_INTIFSD_IDLEINT_168_INT168PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,6))) -#define TSB_INTIFSD_IDLEINT_168_INT168NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,7))) -#define TSB_INTIFSD_IDLEINT_169_INT169EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,0))) -#define TSB_INTIFSD_IDLEINT_169_INT169PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,4))) -#define TSB_INTIFSD_IDLEINT_169_INT169NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,5))) -#define TSB_INTIFSD_IDLEINT_169_INT169PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,6))) -#define TSB_INTIFSD_IDLEINT_169_INT169NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,7))) -#define TSB_INTIFSD_FLAG0_INT16FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,16))) -#define TSB_INTIFSD_FLAG0_INT17FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,17))) -#define TSB_INTIFSD_FLAG0_INT18FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,18))) -#define TSB_INTIFSD_FLAG1_INT32FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,0))) -#define TSB_INTIFSD_FLAG1_INT33FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,1))) -#define TSB_INTIFSD_FLAG1_INT34FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,2))) -#define TSB_INTIFSD_FLAG1_INT35FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,3))) -#define TSB_INTIFSD_FLAG1_INT36FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,4))) -#define TSB_INTIFSD_FLAG1_INT37FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,5))) -#define TSB_INTIFSD_FLAG1_INT38FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,6))) -#define TSB_INTIFSD_FLAG1_INT39FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,7))) -#define TSB_INTIFSD_FLAG3_INT96FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,0))) -#define TSB_INTIFSD_FLAG3_INT97FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,1))) -#define TSB_INTIFSD_FLAG3_INT98FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,2))) -#define TSB_INTIFSD_FLAG3_INT99FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,3))) -#define TSB_INTIFSD_FLAG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,4))) -#define TSB_INTIFSD_FLAG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,5))) -#define TSB_INTIFSD_FLAG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,6))) -#define TSB_INTIFSD_FLAG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,7))) -#define TSB_INTIFSD_FLAG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,8))) -#define TSB_INTIFSD_FLAG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,9))) -#define TSB_INTIFSD_FLAG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,10))) -#define TSB_INTIFSD_FLAG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,11))) -#define TSB_INTIFSD_FLAG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,12))) -#define TSB_INTIFSD_FLAG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,13))) -#define TSB_INTIFSD_FLAG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,14))) -#define TSB_INTIFSD_FLAG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,15))) -#define TSB_INTIFSD_FLAG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,16))) -#define TSB_INTIFSD_FLAG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,17))) -#define TSB_INTIFSD_FLAG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,18))) -#define TSB_INTIFSD_FLAG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,19))) -#define TSB_INTIFSD_FLAG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,20))) -#define TSB_INTIFSD_FLAG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,21))) -#define TSB_INTIFSD_FLAG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,22))) -#define TSB_INTIFSD_FLAG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,23))) -#define TSB_INTIFSD_FLAG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,24))) -#define TSB_INTIFSD_FLAG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,25))) -#define TSB_INTIFSD_FLAG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,26))) -#define TSB_INTIFSD_FLAG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,27))) -#define TSB_INTIFSD_FLAG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,28))) -#define TSB_INTIFSD_FLAG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,29))) -#define TSB_INTIFSD_FLAG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,30))) -#define TSB_INTIFSD_FLAG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,31))) -#define TSB_INTIFSD_FLAG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,0))) -#define TSB_INTIFSD_FLAG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,1))) -#define TSB_INTIFSD_FLAG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,2))) -#define TSB_INTIFSD_FLAG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,3))) -#define TSB_INTIFSD_FLAG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,4))) -#define TSB_INTIFSD_FLAG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,5))) -#define TSB_INTIFSD_FLAG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,6))) -#define TSB_INTIFSD_FLAG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,7))) -#define TSB_INTIFSD_FLAG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,8))) -#define TSB_INTIFSD_FLAG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,9))) -#define TSB_INTIFSD_FLAG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,10))) -#define TSB_INTIFSD_FLAG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,11))) -#define TSB_INTIFSD_FLAG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,12))) -#define TSB_INTIFSD_FLAG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,13))) -#define TSB_INTIFSD_FLAG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,14))) -#define TSB_INTIFSD_FLAG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,15))) -#define TSB_INTIFSD_FLAG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,16))) -#define TSB_INTIFSD_FLAG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,17))) -#define TSB_INTIFSD_FLAG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,18))) -#define TSB_INTIFSD_FLAG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,19))) -#define TSB_INTIFSD_FLAG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,20))) -#define TSB_INTIFSD_FLAG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,21))) -#define TSB_INTIFSD_FLAG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,22))) -#define TSB_INTIFSD_FLAG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,23))) -#define TSB_INTIFSD_FLAG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,24))) -#define TSB_INTIFSD_FLAG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,0))) -#define TSB_INTIFSD_FLAG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,1))) -#define TSB_INTIFSD_FLAG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,2))) -#define TSB_INTIFSD_FLAG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,3))) -#define TSB_INTIFSD_FLAG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,4))) -#define TSB_INTIFSD_FLAG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,5))) -#define TSB_INTIFSD_FLAG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,6))) -#define TSB_INTIFSD_FLAG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,7))) -#define TSB_INTIFSD_FLAG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,8))) -#define TSB_INTIFSD_FLAG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,9))) - - -/* ADC */ -#define TSB_AD_MOD1_I2AD (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,6))) -#define TSB_AD_MOD1_VREFON (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,7))) -#define TSB_AD_MOD3_ADOBSV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,0))) -#define TSB_AD_MOD3_ADOBIC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,5))) -#define TSB_AD_MOD4_ADHTG (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,4))) -#define TSB_AD_MOD4_ADHS (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,5))) -#define TSB_AD_MOD4_HADHTG (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,6))) -#define TSB_AD_MOD4_HADHS (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,7))) -#define TSB_AD_MOD5_ADOBSV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,0))) -#define TSB_AD_MOD5_ADOBIC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,5))) -#define TSB_AD_MOD6_ADDMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,0))) -#define TSB_AD_MOD6_ADHPDMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,1))) -#define TSB_AD_MOD6_ADM0DMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,2))) -#define TSB_AD_MOD6_ADM1DMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,3))) - - /** @} *//* End of group Device_Peripheral_registers */ - -#ifdef __cplusplus -} -#endif -#endif /* __TMPM066_H__ */ - -/** @} *//* End of group TMPM066 */ -/** @} *//* End of group TOSHIBA_TX00_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S deleted file mode 100644 index e2371e51c1..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S +++ /dev/null @@ -1,189 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM066.S -; * @brief CMSIS Cortex-M0 Core Device Startup File for the -; * TOSHIBA 'TMPM066' Device Series -; * @version V2.0.2.1 (Tentative) -; * @date 2015/08/05 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT0_IRQHandler ; 0: Interrupt Pin0 - DCD INT1_IRQHandler ; 1: Interrupt Pin1 - DCD INT2_IRQHandler ; 2: Interrupt Pin2 - DCD INT3_IRQHandler ; 3: Interrupt Pin3 - DCD INT4_IRQHandler ; 4: Interrupt Pin4 - DCD INT5_IRQHandler ; 5: Interrupt Pin5 - DCD INTRX0_IRQHandler ; 6: Serial reception interrupt(channel0) - DCD INTTX0_IRQHandler ; 7: Serial transmission interrupt(channel0) - DCD INTRX1_IRQHandler ; 8: Serial reception interrupt(channel1) - DCD INTTX1_IRQHandler ; 9: Serial transmission interrupt(channel1) - DCD INTSPIRX_IRQHandler ; 10: SPI serial reception interrupt - DCD INTSPITX_IRQHandler ; 11: SPI serial transmission interrupt - DCD INTSPIERR_IRQHandler ; 12: SPI serial error interrupt - DCD INTI2C0_IRQHandler ; 13: Serial bus interface (channel.0) - DCD INTI2C1_IRQHandler ; 14: Serial bus interface (channel.1) - DCD INTDMA_IRQHandler ; 15: DMAC interrupt - DCD INT16A0_IRQHandler ; 16: 16-bit TMR16A match detection (channel.0) - DCD INT16A1_IRQHandler ; 17: 16-bit TMR16A match detection (channel.1) - DCD INTTB0_IRQHandler ; 18: 16-bit TMRB interrupt(channel.0) - DCD INTTB1_IRQHandler ; 19: 16-bit TMRB interrupt(channel.1) - DCD INTTB2_IRQHandler ; 20: 16-bit TMRB interrupt(channel.2) - DCD INTTB3_IRQHandler ; 21: 16-bit TMRB interrupt(channel.3) - DCD INTTB4_IRQHandler ; 22: 16-bit TMRB interrupt(channel.4) - DCD INTTB5_IRQHandler ; 23: 16-bit TMRB interrupt(channel.5) - DCD INTTB6_IRQHandler ; 24: 16-bit TMRB interrupt(channel.6) - DCD INTTB7_IRQHandler ; 25: 16-bit TMRB interrupt(channel.7) - DCD INTI2CS_IRQHandler ; 26: Serial bus interface for Wakeup(channel.1) - DCD INTTMRD_IRQHandler ; 27: TMRD interrupt - DCD INTUSB_IRQHandler ; 28: USB interrupt - DCD INTUSBWKUP_IRQHandler ; 29: USB wakeup interrupt - DCD INTADHP_IRQHandler ; 30: High Priority A/D conversion interrupt - DCD INTAD_IRQHandler ; 31: Normal A/D conversion completion interrupt - - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT0_IRQHandler [WEAK] - EXPORT INT1_IRQHandler [WEAK] - EXPORT INT2_IRQHandler [WEAK] - EXPORT INT3_IRQHandler [WEAK] - EXPORT INT4_IRQHandler [WEAK] - EXPORT INT5_IRQHandler [WEAK] - EXPORT INTRX0_IRQHandler [WEAK] - EXPORT INTTX0_IRQHandler [WEAK] - EXPORT INTRX1_IRQHandler [WEAK] - EXPORT INTTX1_IRQHandler [WEAK] - EXPORT INTSPIRX_IRQHandler [WEAK] - EXPORT INTSPITX_IRQHandler [WEAK] - EXPORT INTSPIERR_IRQHandler [WEAK] - EXPORT INTI2C0_IRQHandler [WEAK] - EXPORT INTI2C1_IRQHandler [WEAK] - EXPORT INTDMA_IRQHandler [WEAK] - EXPORT INT16A0_IRQHandler [WEAK] - EXPORT INT16A1_IRQHandler [WEAK] - EXPORT INTTB0_IRQHandler [WEAK] - EXPORT INTTB1_IRQHandler [WEAK] - EXPORT INTTB2_IRQHandler [WEAK] - EXPORT INTTB3_IRQHandler [WEAK] - EXPORT INTTB4_IRQHandler [WEAK] - EXPORT INTTB5_IRQHandler [WEAK] - EXPORT INTTB6_IRQHandler [WEAK] - EXPORT INTTB7_IRQHandler [WEAK] - EXPORT INTI2CS_IRQHandler [WEAK] - EXPORT INTTMRD_IRQHandler [WEAK] - EXPORT INTUSB_IRQHandler [WEAK] - EXPORT INTUSBWKUP_IRQHandler [WEAK] - EXPORT INTADHP_IRQHandler [WEAK] - EXPORT INTAD_IRQHandler [WEAK] - -INT0_IRQHandler -INT1_IRQHandler -INT2_IRQHandler -INT3_IRQHandler -INT4_IRQHandler -INT5_IRQHandler -INTRX0_IRQHandler -INTTX0_IRQHandler -INTRX1_IRQHandler -INTTX1_IRQHandler -INTSPIRX_IRQHandler -INTSPITX_IRQHandler -INTSPIERR_IRQHandler -INTI2C0_IRQHandler -INTI2C1_IRQHandler -INTDMA_IRQHandler -INT16A0_IRQHandler -INT16A1_IRQHandler -INTTB0_IRQHandler -INTTB1_IRQHandler -INTTB2_IRQHandler -INTTB3_IRQHandler -INTTB4_IRQHandler -INTTB5_IRQHandler -INTTB6_IRQHandler -INTTB7_IRQHandler -INTI2CS_IRQHandler -INTTMRD_IRQHandler -INTUSB_IRQHandler -INTUSBWKUP_IRQHandler -INTADHP_IRQHandler -INTAD_IRQHandler - - B . - - ENDP - - END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct deleted file mode 100644 index 35409d4fa0..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct +++ /dev/null @@ -1,43 +0,0 @@ -#! armcc -E - -;; TMPM066FWUG scatter file - -;; Vector table starts at 0 -;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) -;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) -;; Initial PC == &__main (with LSB set to indicate Thumb) -;; These two values are provided by the library -;; Other vectors must be provided by the user -;; Code starts after the last possible vector -;; Data starts at 0x20000000 -;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) -;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) - -;; Compatible with ISSM model - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x20000 -{ - ER_IROM1 0x00000000 0x20000 - { - *.o (RESET, +First) - *(InRoot$$Sections) - *.o (+RO-CODE) - .ANY2 (+RO-DATA) - .ANY (+RO) - } - - /* 8_byte_aligned(32 + 16 vect * 4 bytes) = 8_byte_aligned(0xC0) */ - RW_IRAM1 0x200000C0 (0x4000 - 0xC0 - Stack_Size) - { - .ANY (+RW, +ZI) - } - - ARM_LIB_STACK (0x200000C0+0x4000) EMPTY -Stack_Size { ; stack - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S deleted file mode 100644 index 1709f1f880..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S +++ /dev/null @@ -1,220 +0,0 @@ -/** - ******************************************************************************* - * @file startup_TMPM066.S - * @brief CMSIS Cortex-M0 Core Device Startup File for the - * TOSHIBA 'TMPM066' Device Series - * @version V2.0.2.1 (Tentative) - * @date 2015/08/05 - *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -.syntax unified -.arch armv6-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .stack -.align 3 -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - -/* Vector Table */ - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long INT0_IRQHandler // 0: Interrupt Pin0 - .long INT1_IRQHandler // 1: Interrupt Pin1 - .long INT2_IRQHandler // 2: Interrupt Pin2 - .long INT3_IRQHandler // 3: Interrupt Pin3 - .long INT4_IRQHandler // 4: Interrupt Pin4 - .long INT5_IRQHandler // 5: Interrupt Pin5 - .long INTRX0_IRQHandler // 6: Serial reception interrupt(channel0) - .long INTTX0_IRQHandler // 7: Serial transmission interrupt(channel0) - .long INTRX1_IRQHandler // 8: Serial reception interrupt(channel1) - .long INTTX1_IRQHandler // 9: Serial transmission interrupt(channel1) - .long INTSPIRX_IRQHandler // 10: SPI serial reception interrupt - .long INTSPITX_IRQHandler // 11: SPI serial transmission interrupt - .long INTSPIERR_IRQHandler // 12: SPI serial error interrupt - .long INTI2C0_IRQHandler // 13: Serial bus interface (channel.0) - .long INTI2C1_IRQHandler // 14: Serial bus interface (channel.1) - .long INTDMA_IRQHandler // 15: DMAC interrupt - .long INT16A0_IRQHandler // 16: 16-bit TMR16A match detection (channel.0) - .long INT16A1_IRQHandler // 17: 16-bit TMR16A match detection (channel.1) - .long INTTB0_IRQHandler // 18: 16-bit TMRB interrupt(channel.0) - .long INTTB1_IRQHandler // 19: 16-bit TMRB interrupt(channel.1) - .long INTTB2_IRQHandler // 20: 16-bit TMRB interrupt(channel.2) - .long INTTB3_IRQHandler // 21: 16-bit TMRB interrupt(channel.3) - .long INTTB4_IRQHandler // 22: 16-bit TMRB interrupt(channel.4) - .long INTTB5_IRQHandler // 23: 16-bit TMRB interrupt(channel.5) - .long INTTB6_IRQHandler // 24: 16-bit TMRB interrupt(channel.6) - .long INTTB7_IRQHandler // 25: 16-bit TMRB interrupt(channel.7) - .long INTI2CS_IRQHandler // 26: Serial bus interface for Wakeup(channel.1) - .long INTTMRD_IRQHandler // 27: TMRD interrupt - .long INTUSB_IRQHandler // 28: USB interrupt - .long INTUSBWKUP_IRQHandler // 29: USB wakeup interrupt - .long INTADHP_IRQHandler // 30: High Priority A/D conversion interrupt - .long INTAD_IRQHandler // 31: Normal A/D conversion completion interrupt - .size __isr_vector, . - __isr_vector - -/* Reset Handler */ - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function - Reset_Handler: - /* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 - .Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop - .Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text - /* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function - \handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler INT0_IRQHandler - def_irq_default_handler INT1_IRQHandler - def_irq_default_handler INT2_IRQHandler - def_irq_default_handler INT3_IRQHandler - def_irq_default_handler INT4_IRQHandler - def_irq_default_handler INT5_IRQHandler - def_irq_default_handler INTRX0_IRQHandler - def_irq_default_handler INTTX0_IRQHandler - def_irq_default_handler INTRX1_IRQHandler - def_irq_default_handler INTTX1_IRQHandler - def_irq_default_handler INTSPIRX_IRQHandler - def_irq_default_handler INTSPITX_IRQHandler - def_irq_default_handler INTSPIERR_IRQHandler - def_irq_default_handler INTI2C0_IRQHandler - def_irq_default_handler INTI2C1_IRQHandler - def_irq_default_handler INTDMA_IRQHandler - def_irq_default_handler INT16A0_IRQHandler - def_irq_default_handler INT16A1_IRQHandler - def_irq_default_handler INTTB0_IRQHandler - def_irq_default_handler INTTB1_IRQHandler - def_irq_default_handler INTTB2_IRQHandler - def_irq_default_handler INTTB3_IRQHandler - def_irq_default_handler INTTB4_IRQHandler - def_irq_default_handler INTTB5_IRQHandler - def_irq_default_handler INTTB6_IRQHandler - def_irq_default_handler INTTB7_IRQHandler - def_irq_default_handler INTI2CS_IRQHandler - def_irq_default_handler INTTMRD_IRQHandler - def_irq_default_handler INTUSB_IRQHandler - def_irq_default_handler INTUSBWKUP_IRQHandler - def_irq_default_handler INTADHP_IRQHandler - def_irq_default_handler INTAD_IRQHandler - - .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld deleted file mode 100644 index e8c906edf3..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* Linker script for Toshiba TMPM066 */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - Image$$RW_IRAM1$$Base = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$RW_IRAM1$$ZI$$Limit = . ; - } > RAM - - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S deleted file mode 100644 index 3c8738e3e8..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S +++ /dev/null @@ -1,281 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM066.S -; * @brief CMSIS Cortex-M0 Core Device Startup File for the -; * TOSHIBA 'TMPM066' Device Series -; * @version V2.0.2.1 (Tentative) -; * @date 2015/08/05 -; * -; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT0_IRQHandler ; 0: Interrupt Pin0 - DCD INT1_IRQHandler ; 1: Interrupt Pin1 - DCD INT2_IRQHandler ; 2: Interrupt Pin2 - DCD INT3_IRQHandler ; 3: Interrupt Pin3 - DCD INT4_IRQHandler ; 4: Interrupt Pin4 - DCD INT5_IRQHandler ; 5: Interrupt Pin5 - DCD INTRX0_IRQHandler ; 6: Serial reception interrupt(channel0) - DCD INTTX0_IRQHandler ; 7: Serial transmission interrupt(channel0) - DCD INTRX1_IRQHandler ; 8: Serial reception interrupt(channel1) - DCD INTTX1_IRQHandler ; 9: Serial transmission interrupt(channel1) - DCD INTSPIRX_IRQHandler ; 10: SPI serial reception interrupt - DCD INTSPITX_IRQHandler ; 11: SPI serial transmission interrupt - DCD INTSPIERR_IRQHandler ; 12: SPI serial error interrupt - DCD INTI2C0_IRQHandler ; 13: Serial bus interface (channel.0) - DCD INTI2C1_IRQHandler ; 14: Serial bus interface (channel.1) - DCD INTDMA_IRQHandler ; 15: DMAC interrupt - DCD INT16A0_IRQHandler ; 16: 16-bit TMR16A match detection (channel.0) - DCD INT16A1_IRQHandler ; 17: 16-bit TMR16A match detection (channel.1) - DCD INTTB0_IRQHandler ; 18: 16-bit TMRB interrupt(channel.0) - DCD INTTB1_IRQHandler ; 19: 16-bit TMRB interrupt(channel.1) - DCD INTTB2_IRQHandler ; 20: 16-bit TMRB interrupt(channel.2) - DCD INTTB3_IRQHandler ; 21: 16-bit TMRB interrupt(channel.3) - DCD INTTB4_IRQHandler ; 22: 16-bit TMRB interrupt(channel.4) - DCD INTTB5_IRQHandler ; 23: 16-bit TMRB interrupt(channel.5) - DCD INTTB6_IRQHandler ; 24: 16-bit TMRB interrupt(channel.6) - DCD INTTB7_IRQHandler ; 25: 16-bit TMRB interrupt(channel.7) - DCD INTI2CS_IRQHandler ; 26: Serial bus interface for Wakeup(channel.1) - DCD INTTMRD_IRQHandler ; 27: TMRD interrupt - DCD INTUSB_IRQHandler ; 28: USB interrupt - DCD INTUSBWKUP_IRQHandler ; 29: USB wakeup interrupt - DCD INTADHP_IRQHandler ; 30: High Priority A/D conversion interrupt - DCD INTAD_IRQHandler ; 31: Normal A/D conversion completion interrupt - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT0_IRQHandler - B INT0_IRQHandler - - PUBWEAK INT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT1_IRQHandler - B INT1_IRQHandler - - PUBWEAK INT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT2_IRQHandler - B INT2_IRQHandler - - PUBWEAK INT3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT3_IRQHandler - B INT3_IRQHandler - - PUBWEAK INT4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT4_IRQHandler - B INT4_IRQHandler - - PUBWEAK INT5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT5_IRQHandler - B INT5_IRQHandler - - PUBWEAK INTRX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRX0_IRQHandler - B INTRX0_IRQHandler - - PUBWEAK INTTX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTX0_IRQHandler - B INTTX0_IRQHandler - - PUBWEAK INTRX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRX1_IRQHandler - B INTRX1_IRQHandler - - PUBWEAK INTTX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTX1_IRQHandler - B INTTX1_IRQHandler - - PUBWEAK INTSPIRX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTSPIRX_IRQHandler - B INTSPIRX_IRQHandler - - PUBWEAK INTSPITX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTSPITX_IRQHandler - B INTSPITX_IRQHandler - - PUBWEAK INTSPIERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTSPIERR_IRQHandler - B INTSPIERR_IRQHandler - - PUBWEAK INTI2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0_IRQHandler - B INTI2C0_IRQHandler - - PUBWEAK INTI2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1_IRQHandler - B INTI2C1_IRQHandler - - PUBWEAK INTDMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMA_IRQHandler - B INTDMA_IRQHandler - - PUBWEAK INT16A0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT16A0_IRQHandler - B INT16A0_IRQHandler - - PUBWEAK INT16A1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT16A1_IRQHandler - B INT16A1_IRQHandler - - PUBWEAK INTTB0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB0_IRQHandler - B INTTB0_IRQHandler - - PUBWEAK INTTB1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB1_IRQHandler - B INTTB1_IRQHandler - - PUBWEAK INTTB2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB2_IRQHandler - B INTTB2_IRQHandler - - PUBWEAK INTTB3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB3_IRQHandler - B INTTB3_IRQHandler - - PUBWEAK INTTB4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB4_IRQHandler - B INTTB4_IRQHandler - - PUBWEAK INTTB5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB5_IRQHandler - B INTTB5_IRQHandler - - PUBWEAK INTTB6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB6_IRQHandler - B INTTB6_IRQHandler - - PUBWEAK INTTB7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTB7_IRQHandler - B INTTB7_IRQHandler - - PUBWEAK INTI2CS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2CS_IRQHandler - B INTI2CS_IRQHandler - - PUBWEAK INTTMRD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTTMRD_IRQHandler - B INTTMRD_IRQHandler - - PUBWEAK INTUSB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUSB_IRQHandler - B INTUSB_IRQHandler - - PUBWEAK INTUSBWKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUSBWKUP_IRQHandler - B INTUSBWKUP_IRQHandler - - PUBWEAK INTADHP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADHP_IRQHandler - B INTADHP_IRQHandler - - PUBWEAK INTAD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTAD_IRQHandler - B INTAD_IRQHandler - - END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf deleted file mode 100644 index f0868f8f66..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf +++ /dev/null @@ -1,34 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0xC00; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h deleted file mode 100644 index df61c39c5a..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h +++ /dev/null @@ -1,12 +0,0 @@ -/* mbed Microcontroller Library - CMSIS for TMPM066 - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in TMPM066 specifics - */ -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "TMPM066.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c deleted file mode 100644 index dabf0d419d..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for TMPM066 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - static int vector_copied = 0; - uint32_t *vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (vector_copied == 0) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS; - for (i = 0; i < NVIC_NUM_VECTORS; i++) { - vectors[i] = old_vectors[i]; - } - vector_copied = 1; - } - vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS; - return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h deleted file mode 100644 index 77a40de438..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h +++ /dev/null @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for TMPM066 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF -// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#ifdef __cplusplus -extern "C" { -#endif - -/** Set the ISR for IRQn - * - * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM - * the first time this function is called - * @param[in] IRQn The Interrupt Request number for which a vector will be registered - * @param[in] vector The ISR vector to register for IRQn - */ -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); - -/** Get the ISR registered for IRQn - * - * Reads the Interrupt Service Routine currently registered for IRQn - * @param[in] IRQn The Interrupt Request number the vector of which will be read - * @return Returns the ISR registered for IRQn - */ -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c deleted file mode 100644 index 9e9de9004f..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c +++ /dev/null @@ -1,301 +0,0 @@ -/** - ******************************************************************************* - * @file system_TMPM066.c - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for the - * TOSHIBA 'TMPM066' Device Series - * @version V2.0.2.1 - * @date 2015/10/22 - * - * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved - ******************************************************************************* - */ - -#include "TMPM066.h" - -/*-------- <<< Start of configuration section >>> ----------------------------*/ - -/* Watchdog Timer (WD) Configuration */ -#define WD_SETUP (1U) -#define WDMOD_Val (0x00000000UL) -#define WDCR_Val (0x000000B1UL) - -/* Clock Generator (CG) Configuration */ -#define CLOCK_SETUP (1U) -#define SYSCR_Val (0x00000000UL) -#define OSCCR_Val (0x00000102UL) /* OSCCR = 1, OSCCR = 01 */ - -#define STBYCR_Val (0x00000000UL) - -#define CG_8M_MUL_12_FPLL (0x00C60B00UL<<8U) - -#define CG_10M_MUL_8_FPLL (0x00C60700UL<<8U) - -#define CG_12M_MUL_8_FPLL (0x00C60700UL<<8U) - -#define CG_16M_MUL_6_FPLL (0x00C60500UL<<8U) - - -#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) -#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) -#define CG_PLL0SEL_PLL0ST_MASK ((uint32_t)0x00000004) - -#define CG_OSCCR_IOSCEN_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) -#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) -#define CG_OSCCR_OSCF_MASK ((uint32_t)0x00000200) - -#define CG_WUON_START_SET ((uint32_t)0x00000001) -#define CG_WUEF_VALUE_MASK ((uint32_t)0x00000002) -#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) - -#define WD_MOD_WDTE_SET ((uint32_t)0x00000080) - -#define PLLSEL_Ready CG_12M_MUL_8_FPLL - -#define PLLSEL_Val (PLLSEL_Ready|0x00000003UL) -#define PLLSEL_MASK (0xFFFFFF00UL) - -/*-------- <<< End of configuration section >>> ------------------------------*/ - -/*-------- DEFINES -----------------------------------------------------------*/ -/* Define clocks */ -#define OSC_8M ( 8000000UL) -#define OSC_10M (10000000UL) -#define OSC_12M (12000000UL) -#define OSC_16M (16000000UL) -#define EXTALH OSC_12M /* External high-speed oscillator freq */ -#define XTALH OSC_10M /* Internal high-speed oscillator freq */ - -/* Configure Warm-up time */ -#define HZ_1M (1000000UL) -#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ -#define WU_TIME_PLL (100UL) /* warm-up time for PLL is 100us */ -#define WUPHCR_WUPT_MASK (0x000FFFFFUL) -#define WUPHCR_WUPT_EXT ((uint32_t)(((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M / 16UL) << 20U)) /* WUPHCR = warm-up time(us) * EXTALH / 16 */ -#define WUPHCR_WUPT_PLL ((WU_TIME_PLL * EXTALH / HZ_1M /16UL) << 20U) - -#if (CLOCK_SETUP) /* Clock(external) Setup */ -/* Determine core clock frequency according to settings */ -/* System clock is high-speed clock*/ -#if (OSCCR_Val & (1U<<8U)) -#define CORE_TALH (EXTALH) -#else -#define CORE_TALH (XTALH) -#endif - -#if ((PLLSEL_Val & (1U<<1U)) && (PLLSEL_Val & (1U<<0U))) /* If PLL selected and enabled */ -#if (CORE_TALH == OSC_8M) /* If input is 8MHz */ -#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_12_FPLL)) -#define __CORE_CLK ((CORE_TALH * 12U) / 4U) /* output clock is 24MHz */ -#else /* fc -> reserved */ -#define __CORE_CLK (0U) -#endif /* End input is 8MHz */ -#elif (CORE_TALH == OSC_10M) /* If input is 10MHz */ -#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_8_FPLL)) -#define __CORE_CLK ((CORE_TALH * 8U) / 4U) /* output clock is 20MHz */ -#else /* fc -> reserved */ -#define __CORE_CLK (0U) -#endif /* End input is 10MHz */ -#elif (CORE_TALH == OSC_12M) /* If input is 12MHz */ -#if ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) -#define __CORE_CLK ((CORE_TALH * 8U) / 4U) /* output clock is 24MHz */ -#else /* fc -> reserved */ -#define __CORE_CLK (0U) -#endif /* End input is 12MHz */ -#elif (CORE_TALH == OSC_16M) /* If input is 16MHz */ -#if ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_6_FPLL) -#define __CORE_CLK ((CORE_TALH * 6U) / 4U) /* output clock is 24MHz */ -#else /* fc -> reserved */ -#define __CORE_CLK (0U) -#endif /* End input is 16MHz */ -#else /* input clock not known */ -#define __CORE_CLK (0U) -#error "Core Oscillator Frequency invalid!" -#endif /* End switch input clock */ -#else -#define __CORE_CLK (CORE_TALH) -#endif - -#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ -#define __CORE_SYS (__CORE_CLK) -#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ -#define __CORE_SYS (__CORE_CLK / 2U) -#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ -#define __CORE_SYS (__CORE_CLK / 4U) -#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ -#define __CORE_SYS (__CORE_CLK / 8U) -#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ -#define __CORE_SYS (__CORE_CLK / 16U) -#else /* Gear -> reserved */ -#define __CORE_SYS (0U) -#endif - -#else -#define __CORE_SYS (XTALH) - -#endif /* clock Setup */ - -/* Clock Variable definitions */ -uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Update SystemCoreClock according register values. - */ -void SystemCoreClockUpdate(void) -{ /* Get Core Clock Frequency */ - uint32_t CoreClock = 0U; - uint32_t CoreClockInput = 0U; - uint32_t regval = 0U; - uint32_t oscsel = 0U; - uint32_t pllsel = 0U; - uint32_t pllon = 0U; - /* Determine clock frequency according to clock register values */ - /* System clock is high-speed clock */ - regval = TSB_CG->OSCCR; - oscsel = regval & CG_OSCCR_OSCSEL_SET; - if (oscsel) { /* If system clock is External high-speed oscillator freq */ - CoreClock = EXTALH; - } else { /* If system clock is Internal high-speed oscillator freq */ - CoreClock = XTALH; - } - regval = TSB_CG->PLL0SEL; - pllsel = regval & CG_PLL0SEL_PLL0SEL_SET; - pllon = regval & CG_PLL0SEL_PLL0ON_SET; - if (pllsel && pllon) { /* If PLL enabled */ - if (CoreClock == OSC_8M) { /* If input is 8MHz */ - if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_8M_MUL_12_FPLL) { - CoreClockInput = (CoreClock * 12U) / 4U; /* output clock is 24MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == OSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_10M_MUL_8_FPLL) { - CoreClockInput = (CoreClock * 8U) / 4U; /* output clock is 20MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == OSC_12M) { /* If input is 12MHz */ - if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) { - CoreClockInput = (CoreClock * 8U) / 4U; /* output clock is 24MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == OSC_16M) { /* If input is 16MHz */ - if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_16M_MUL_6_FPLL) { - CoreClockInput = (CoreClock * 6U) / 4U; /* output clock is 24MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else { - CoreClockInput = 0U; - } - } else { - CoreClockInput = CoreClock; - } - switch (TSB_CG->SYSCR & 7U) { - case 0U: - SystemCoreClock = CoreClockInput; /* Gear -> fc */ - break; - case 1U: /* Gear -> fc/2 */ - SystemCoreClock = CoreClockInput / 2U; - break; - case 2U: /* Gear -> fc/4 */ - SystemCoreClock = CoreClockInput / 4U; - break; - case 3U: /* Gear -> fc/8 */ - SystemCoreClock = CoreClockInput / 8U; - break; - case 4U: /* Gear -> fc/16 */ - if (CoreClockInput >= OSC_16M) { - SystemCoreClock = CoreClockInput / 16U; - } else { - SystemCoreClock = 0U; - } - break; - default: - SystemCoreClock = 0U; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ - uint32_t regval = 0U; - volatile uint32_t pllst = 0U; - volatile uint32_t wuef = 0U; - volatile uint32_t oscf = 0U; - uint32_t wdte = 0U; - -#if (WD_SETUP) /* Watchdog Setup */ - while (TSB_WD->FLG != 0U) { - } /* When writing to WDMOD or WDCR, confirm "0" of WDFLG. */ - TSB_WD->MOD = WDMOD_Val; - regval = TSB_WD->MOD; - wdte = regval & WD_MOD_WDTE_SET; - if (!wdte) { /* If watchdog is to be disabled */ - TSB_WD->CR = WDCR_Val; - } else { - /*Do nothing*/ - } -#endif - -#if (CLOCK_SETUP) /* Clock(external) Setup */ - TSB_CG->SYSCR = SYSCR_Val; - TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK; - TSB_CG->WUPHCR |= WUPHCR_WUPT_EXT; - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; - TSB_CG->WUPHCR |= CG_WUPHCR_WUCLK_SET; - TSB_CG->WUPHCR |= CG_WUON_START_SET; - wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; - while (wuef) { - wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; - } /* Warm-up */ - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK; - while (oscf != CG_OSCCR_OSCF_MASK) { - oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK; - } /* Confirm CGOSCCR="1" */ - - TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK; - TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL; - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; - TSB_CG->PLL0SEL = PLLSEL_Ready; - TSB_CG->WUPHCR |= CG_WUON_START_SET; - wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; - while (wuef) { - wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; - } /* Warm-up */ - - TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK; - TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL; - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ - TSB_CG->STBYCR = STBYCR_Val; - TSB_CG->WUPHCR |= CG_WUON_START_SET; - wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; - while (wuef) { - wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; - } /* Warm-up */ - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; - pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK; - while (pllst != CG_PLL0SEL_PLL0ST_MASK) { - pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK; - } /*Confirm CGPLLSEL = "1" */ - -#endif -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h deleted file mode 100644 index a8b1053e00..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - ***************************************************************************** - * @file system_TMPM066.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM066' Device Series - * @version V2.0.2.1 (Tentative) - * @date 2015/8/13 - * - * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved - ***************************************************************************** - */ - -#include - -#ifndef __SYSTEM_TMPM066_H -#define __SYSTEM_TMPM066_H - -#ifdef __cplusplus -extern "C" { -#endif - - extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ - extern void SystemInit(void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ - extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c deleted file mode 100644 index 0b6025e165..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c +++ /dev/null @@ -1,99 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define GPIO_DATA PIN_DATA(0, 3) -extern const PinMap PinMap_GPIO_IRQ[]; - -uint32_t gpio_set(PinName pin) -{ - // Check that pin is valid - MBED_ASSERT(pin != (PinName)NC); - - // Checking pin name is not interrupt pins - if (pinmap_find_peripheral(pin, PinMap_GPIO_IRQ) == (uint32_t) NC) { - // Set pin function as GPIO pin - pin_function(pin, GPIO_DATA); - } - - // Return pin mask - return (1 << (pin & 0x07)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - // Store above pin mask, pin name into GPIO object - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - obj->mask = gpio_set(pin); - obj->port = (GPIO_Port) (pin >> 3); - if ((PortName)obj->port == PortH) { - CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE); - } - if ((PortName)obj->port == PortJ) { - CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); - } -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - // Set pin mode - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - // Set direction - switch (direction) { - case PIN_INPUT: - // Set pin input - GPIO_SetInput(obj->port, obj->mask); - break; - case PIN_OUTPUT: - // Set pin output - GPIO_SetOutput(obj->port, obj->mask); - break; - case PIN_INOUT: - // Set pin both input and output - GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE); - GPIO_SetInputEnableReg(obj->port, obj->mask, ENABLE); - break; - default: - error("Invalid direction\n"); - break; - } -} - -void gpio_write(gpio_t *obj, int value) -{ - // Write gpio object pin data - if ((value == 0) || (value == 1)) { - GPIO_WriteDataBit(obj->port, obj->mask, value); - } else { - error("Invalid value\n"); - } -} - -int gpio_read(gpio_t *obj) -{ - // Read gpio object pin data - return GPIO_ReadDataBit(obj->port, obj->mask); -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c deleted file mode 100644 index c463d12405..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c +++ /dev/null @@ -1,234 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_critical.h" - -#define CHANNEL_NUM 6 - -const PinMap PinMap_GPIO_IRQ[] = { - {PD5, GPIO_IRQ_0, PIN_DATA(0, 0)}, - {PA5, GPIO_IRQ_1, PIN_DATA(0, 0)}, - {PA6, GPIO_IRQ_2, PIN_DATA(0, 0)}, - {PF1, GPIO_IRQ_3, PIN_DATA(0, 0)}, - {PC5, GPIO_IRQ_4, PIN_DATA(0, 0)}, - {PF0, GPIO_IRQ_5, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; - -static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index) -{ - uint32_t val; - GPIO_Port port; - uint32_t mask; - INTIFAO_INTActiveState ActiveState; - port = (GPIO_Port)(pin >> 3); - mask = 0x01 << (pin & 0x07); - // Clear interrupt request - INTIFAO_ClearINTReq((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index)); - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)irq_id); - ActiveState = INTIFAO_GetSTBYReleaseINTState((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index)); - INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index), - ActiveState, DISABLE); - // Get pin value - val = GPIO_ReadDataBit(port, mask); - switch (val) { - // Falling edge detection - case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); - break; - // Rising edge detection - case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); - break; - default: - break; - } - - // Enable interrupt request - INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index), - ActiveState, ENABLE); -} - -void INT0_IRQHandler(void) -{ - INT_IRQHandler(PD5, GPIO_IRQ_0, 0); -} - -void INT1_IRQHandler(void) -{ - INT_IRQHandler(PA5, GPIO_IRQ_1, 1); -} - -void INT2_IRQHandler(void) -{ - INT_IRQHandler(PA6, GPIO_IRQ_2, 2); -} - -void INT3_IRQHandler(void) -{ - INT_IRQHandler(PF1, GPIO_IRQ_3, 3); -} - -void INT4_IRQHandler(void) -{ - INT_IRQHandler(PC5, GPIO_IRQ_4, 4); -} - -void INT5_IRQHandler(void) -{ - INT_IRQHandler(PF0, GPIO_IRQ_5, 5); -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - // Get gpio interrupt ID - obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - core_util_critical_section_enter(); - // Get pin mask - obj->mask = (uint32_t)(1 << (pin & 0x07)); - // Get GPIO port - obj->port = (GPIO_Port)(pin >> 3); - // Set pin level as LOW - GPIO_WriteDataBit(obj->port, obj->mask, 0); - // Enable gpio interrupt function - pinmap_pinout(pin, PinMap_GPIO_IRQ); - - // Get GPIO irq source - switch (obj->irq_id) { - case GPIO_IRQ_0: - obj->irq_src = INTIFAO_INT_SRC_0; - break; - case GPIO_IRQ_1: - obj->irq_src = INTIFAO_INT_SRC_1; - break; - case GPIO_IRQ_2: - obj->irq_src = INTIFAO_INT_SRC_2; - break; - case GPIO_IRQ_3: - obj->irq_src = INTIFAO_INT_SRC_3; - break; - case GPIO_IRQ_4: - obj->irq_src = INTIFAO_INT_SRC_4; - break; - case GPIO_IRQ_5: - obj->irq_src = INTIFAO_INT_SRC_5; - break; - default: - break; - } - - // Save irq handler - hal_irq_handler[obj->irq_src] = handler; - // Save irq id - channel_ids[obj->irq_src] = id; - // Initialize interrupt event as both edges detection - obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID; - // Set interrupt event and enable INTx clear - INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE); - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - core_util_critical_section_exit();; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Clear gpio_irq - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Reset interrupt handler - hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - //Disable GPIO interrupt on obj - gpio_irq_disable(obj); - if (enable) { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) || - (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = INTIFAO_INT_ACTIVE_STATE_RISING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) || - (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING; - } - } else { - error("Not supported event\n"); - } - } else { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) || - (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) { - obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID; - } else { - obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) || - (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) { - obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID; - } else { - obj->event = INTIFAO_INT_ACTIVE_STATE_RISING; - } - } else { - error("Not supported event\n"); - } - } - - if (obj->event != INTIFAO_INT_ACTIVE_STATE_INVALID) { - // Set interrupt event and enable INTx clear - INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE); - GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE); - } else { - GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE); - } - - // Clear interrupt request - INTIFAO_ClearINTReq(obj->irq_src); - // Enable GPIO interrupt on obj - gpio_irq_enable(obj); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear and Enable gpio_irq object - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - NVIC_EnableIRQ((IRQn_Type)obj->irq_id); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable gpio_irq object - NVIC_DisableIRQ((IRQn_Type)obj->irq_id); -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h deleted file mode 100644 index 72138a8c86..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - GPIO_Port port; -} gpio_t; - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return (obj->pin != (PinName)NC); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c deleted file mode 100644 index 9a538d909d..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c +++ /dev/null @@ -1,368 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "mbed_error.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define I2C_NACK (0) -#define I2C_ACK (1) -#define I2C_NO_DATA (0) -#define I2C_READ_ADDRESSED (1) -#define I2C_WRITE_GENERAL (2) -#define I2C_WRITE_ADDRESSED (3) -#define SELF_ADDR (0xE0) -#define I2C_TIMEOUT (100000) - -static const PinMap PinMap_I2C_SDA[] = { - {PC1, I2C_0, PIN_DATA(1, 2)}, - {PG1, I2C_1, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PC0, I2C_0, PIN_DATA(1, 2)}, - {PG0, I2C_1, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx); -// Clock setting structure definition -typedef struct { - uint32_t sck; - uint32_t prsck; -} I2C_clock_setting_t; - -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {20, 24, 32, 48, 80, 144, 272, 528}; // SCK Divider value table -static uint32_t start_flag = 0; -I2C_clock_setting_t clk; -I2C_State status; - -static int32_t wait_status(i2c_t *obj) -{ - volatile int32_t timeout = I2C_TIMEOUT; - - while (I2C_GetINTI2CStatus(obj->i2c) == DISABLE) { - if ((timeout--) == 0) { - return (-1); - } - } - return (0); -} - -// Initialize the I2C peripheral. It sets the default parameters for I2C -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - MBED_ASSERT(obj != NULL); - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)i2c_name != NC); - - switch (i2c_name) { - case I2C_0: - CG_SetFcPeriphA(CG_FC_PERIPH_I2C0, ENABLE); - obj->i2c = TSB_I2C0; - obj->IRQn = INTI2C0_IRQn; - break; - case I2C_1: - CG_SetFcPeriphB(CG_FC_PERIPH_I2C1, ENABLE); - obj->i2c = TSB_I2C1; - obj->IRQn = INTI2C1_IRQn; - break; - default: - error("I2C is not available"); - break; - } - - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - pin_mode(sda, PullUp); - - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pin_mode(scl, PullUp); - - NVIC_DisableIRQ(obj->IRQn); - - i2c_reset(obj); - i2c_frequency(obj, 100000); -} - -// Configure the I2C frequency -void i2c_frequency(i2c_t *obj, int hz) -{ - uint64_t sck, tmp_sck; - uint64_t prsck, tmp_prsck; - uint64_t fscl, tmp_fscl; - uint64_t fx; - - SystemCoreClockUpdate(); - - if (hz <= 1000000) { - sck = tmp_sck = 0; - prsck = tmp_prsck = 1; - fscl = tmp_fscl = 0; - for (prsck = 1; prsck <= 32; prsck++) { - fx = ((uint64_t)SystemCoreClock / prsck); - if ((fx < 40000000U) && (fx > 6666666U)) { - for (sck = 0; sck <= 7; sck++) { - fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - tmp_sck = sck; - tmp_prsck = (prsck < 32)? prsck: 0; - } - } - } - } - clk.sck = (uint32_t)tmp_sck; - clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck) : 0; - } - obj->myi2c.I2CSelfAddr = SELF_ADDR; - obj->myi2c.I2CDataLen = I2C_DATA_LEN_8; - obj->myi2c.I2CACKState = ENABLE; - obj->myi2c.I2CClkDiv = clk.sck; - obj->myi2c.PrescalerClkDiv = clk.prsck; - - I2C_Init(obj->i2c, &obj->myi2c); - NVIC_DisableIRQ(obj->IRQn); -} - -int i2c_start(i2c_t *obj) -{ - start_flag = 1; - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - I2C_GenerateStop(obj->i2c); - return 0; -} - -void i2c_reset(i2c_t *obj) -{ - I2C_SWReset(obj->i2c); -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - - if (length > 0) { - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { - while (count < length) { - int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - } - return (result); -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) // Blocking sending data -{ - int32_t result = 0; - int32_t count = 0; - - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, address) == I2C_ACK) { - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - return (result); -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - int32_t result; - - I2C_ClearINTOutput(obj->i2c); - - if (last) { - I2C_SelectACKoutput(obj->i2c, ENABLE); - } else { - I2C_SelectACKoutput(obj->i2c, DISABLE); - } - I2C_SetSendData(obj->i2c, 0x00); - - if (wait_status(obj) < 0) { - result = -1; - } else { - result = (int32_t)I2C_GetReceiveData(obj->i2c); - } - return (result); -} - -void I2C_Start_Condition(i2c_t *p_obj, uint32_t data) -{ - status = I2C_GetState(p_obj->i2c); - if (status.Bit.BusState) { - I2C_SetRepeatStart(p_obj->i2c, ENABLE); - } - I2C_SetSendData(p_obj->i2c, (uint32_t)data); - I2C_GenerateStart(p_obj->i2c); -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - int32_t result; - - I2C_ClearINTOutput(obj->i2c); - - if (start_flag == 1) { - I2C_Start_Condition(obj, (uint32_t)data); - start_flag = 0; - } else { - I2C_SetSendData(obj->i2c, (uint32_t)data); - } - - if (wait_status(obj) < 0) { - return (-1); - } - - status = I2C_GetState(obj->i2c); - if (!status.Bit.LastRxBit) { - result = 1; - } else { - result = 0; - } - return (result); -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - i2c_reset(obj); - - obj->myi2c.I2CDataLen = I2C_DATA_LEN_8; - obj->myi2c.I2CACKState = ENABLE; - obj->myi2c.I2CClkDiv = clk.sck; - obj->myi2c.PrescalerClkDiv = clk.prsck; - - if (enable_slave) { - obj->myi2c.I2CSelfAddr = obj->address; - I2C_SetINTI2CReq(obj->i2c, ENABLE); - } else { - obj->myi2c.I2CSelfAddr = SELF_ADDR; - NVIC_DisableIRQ(obj->IRQn); - I2C_ClearINTOutput(obj->i2c); - } - I2C_Init(obj->i2c, &obj->myi2c); -} - -int i2c_slave_receive(i2c_t *obj) -{ - int32_t result = I2C_NO_DATA; - - if ((I2C_GetINTI2CStatus(obj->i2c)) && (I2C_GetSlaveAddrMatchState(obj->i2c))) { - status = I2C_GetState(obj->i2c); - if (!status.Bit.TRx) { - result = I2C_WRITE_ADDRESSED; - } else { - result = I2C_READ_ADDRESSED; - } - } - return (result); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - int32_t count = 0; - - while (count < length) { - int32_t pdata = i2c_byte_read(obj, ((count < (length - 1))? 0: 1)); - status = I2C_GetState(obj->i2c); - if (status.Bit.TRx) { - return (count); - } else { - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - } - i2c_slave_mode(obj, 1); - return (count); -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int32_t count = 0; - - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - i2c_slave_mode(obj, 1); - return (count); -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - obj->address = address & 0xFE; - i2c_slave_mode(obj, 1); -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h deleted file mode 100644 index 04328f191b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h +++ /dev/null @@ -1,80 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "PortNames.h" -#include "PeripheralNames.h" -#include "tmpm066_gpio.h" -#include "tmpm066_uart.h" -#include "tmpm066_cg.h" -#include "tmpm066_intifao.h" -#include "tmpm066_i2c.h" -#include "tmpm066_adc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t mask; - GPIO_Port port; - uint32_t irq_id; - INTIFAO_INTActiveState event; - INTIFAO_INTSrc irq_src; -}; - -struct port_s { - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - PinName pin; - TSB_TB_TypeDef *channel; - uint16_t trailing_timing; - uint16_t leading_timing; - uint16_t divisor; - float period; -}; - -struct serial_s { - PinName pin; - uint32_t index; - TSB_SC_TypeDef *UARTx; - UART_InitTypeDef uart_config; -}; - -struct analogin_s { - PinName pin; - ADCName adc; - TSB_AD_TypeDef *obj; -}; - -struct i2c_s { - uint32_t address; - IRQn_Type IRQn; - TSB_I2C_TypeDef *i2c; - I2C_InitTypeDef myi2c; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c deleted file mode 100644 index 78dbec1295..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c +++ /dev/null @@ -1,106 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "tmpm066_gpio.h" - -#define PIN_FUNC_MAX 6 - -void pin_function(PinName pin, int function) -{ - uint32_t port = 0; - uint8_t bit = 0; - uint8_t i = 0; - uint8_t func = 0; - uint8_t dir = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Calculate pin function and pin direction - func = PIN_FUNC(function); - dir = PIN_DIR(function); - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - // Set function if function is in range - if (func <= PIN_FUNC_MAX) { - // Disable other functions - for (i = 0; i < PIN_FUNC_MAX; i++) { - if (i != (func - 1)) { - GPIO_DisableFuncReg((GPIO_Port)port, i, (1 << bit)); - } - } - // Set pin function - if (func) { - GPIO_EnableFuncReg((GPIO_Port)port, (uint8_t)(func - 1), (1 << bit)); - } - } - - // Set direction if direction is in range - switch (dir) { - case PIN_INPUT: - GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); - GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), DISABLE); - break; - case PIN_OUTPUT: - GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); - GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), DISABLE); - break; - case PIN_INOUT: - GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); - GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); - break; - default: - break; - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - uint32_t port = 0; - uint8_t bit = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Check if function is in range - if (mode > OpenDrain) { - return; - } - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - // Set pin mode - switch (mode) { - case PullNone: - GPIO_SetPullUp((GPIO_Port)port, (1 << bit), DISABLE); - GPIO_SetPullDown((GPIO_Port)port, (1 << bit), DISABLE); - GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), DISABLE); - break; - case PullUp: - GPIO_SetPullUp((GPIO_Port)port, (1 << bit), ENABLE); - break; - case PullDown: - GPIO_SetPullDown((GPIO_Port)port, (1 << bit), ENABLE); - break; - case OpenDrain: - GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), ENABLE); - break; - default: - break; - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c deleted file mode 100644 index f8020aec2f..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c +++ /dev/null @@ -1,124 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" - -#define PORT_PIN_NUM 8 - -PinName port_pin(PortName port, int pin_n) -{ - PinName pin = NC; - pin = (PinName)((port << 3) | pin_n); - return pin; -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(port <= PortJ); - - // Store port and port mask for future use - obj->port = port; - obj->mask = mask; - - if ((PortName)obj->port == PortH) { - CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE); - } - if ((PortName)obj->port == PortJ) { - CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); - } - - // Set port function and port direction - for (i = 0; i < PORT_PIN_NUM; i++) { - // If the pin is used - if (obj->mask & (1 << i)) { - pin_function(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortJ); - - // Set mode for masked pins - for (i = 0; i < PORT_PIN_NUM; i++) { - // If the pin is used - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - // Assert that port is valid - MBED_ASSERT(obj->port <= PortJ); - - // Set direction for masked pins - switch (dir) { - case PIN_INPUT: - GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE); - GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); - break; - case PIN_OUTPUT: - GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE); - GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); - break; - case PIN_INOUT: - GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); - GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); - break; - default: - break; - } -} - -void port_write(port_t *obj, int value) -{ - uint8_t port_data = 0; - uint8_t data = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortJ); - - // Get current data of port - port_data = GPIO_ReadData((GPIO_Port)obj->port); - // Calculate data to write to masked pins - data = (port_data & ~obj->mask) | (value & obj->mask); - // Write data to masked pins of the port - GPIO_WriteData((GPIO_Port)obj->port, data); -} - -int port_read(port_t *obj) -{ - uint8_t port_data = 0; - uint8_t data = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortJ); - - // Get current data of port - port_data = GPIO_ReadData((GPIO_Port)obj->port); - // Calculate data of masked pins - data = port_data & obj->mask; - return data; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c deleted file mode 100644 index 8d40e3657c..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c +++ /dev/null @@ -1,248 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pwmout_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "tmpm066_tmrb.h" - -#define CLOCK_FREQUENCY SystemCoreClock // input source clock -#define MAX_COUNTER_16B 0xFFFF -#define DEFAULT_CLOCK_DIVISION 32 -#define DEFAULT_PERIOD 0.02f // 20ms - -static const PinMap PinMap_PWM[] = { - {PD1, PWM_0, PIN_DATA(1, 1)}, - {PD2, PWM_1, PIN_DATA(1, 1)}, - {PD3, PWM_2, PIN_DATA(1, 1)}, - {PF4, PWM_3, PIN_DATA(1, 1)}, - {PF5, PWM_4, PIN_DATA(1, 1)}, - {PJ0, PWM_5, PIN_DATA(1, 1)}, - {PJ1, PWM_6, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const uint32_t prescale_tbl[] = { - 2, 8, 32, 64, 128, 256, 512 -}; - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - uint16_t counter = 0; - TMRB_FFOutputTypeDef FFStruct; - TMRB_InitTypeDef m_tmrb; - - // Determine the pwm channel - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - //Assert input is valid - MBED_ASSERT(pwm != (PWMName)NC); - - // Enable clock supply to TB0 - CG_SetFcPeriphA(CG_FC_PERIPH_TMRB0_3, ENABLE); - CG_SetFcPeriphA(CG_FC_PERIPH_TMRB4_6, ENABLE); - - switch (pwm) { - case PWM_0: - obj->channel = TSB_TB0; - break; - case PWM_1: - obj->channel = TSB_TB1; - break; - case PWM_2: - obj->channel = TSB_TB2; - break; - case PWM_3: - obj->channel = TSB_TB3; - break; - case PWM_4: - obj->channel = TSB_TB4; - break; - case PWM_5: - obj->channel = TSB_TB5; - CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); - break; - case PWM_6: - obj->channel = TSB_TB6; - CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); - break; - default: - obj->channel = NULL; - return; - } - // Set pin function as PWM - pinmap_pinout(pin, PinMap_PWM); - obj->pin = pin; - obj->period = DEFAULT_PERIOD; - // Enable channel - TMRB_Enable(obj->channel); - // Stops and clear count operation - TMRB_SetRunState(obj->channel, TMRB_STOP); - // Disables double buffering - TMRB_SetDoubleBuf(obj->channel, DISABLE); - // Set default period = 20ms, duty cycle = 0 - obj->divisor = DEFAULT_CLOCK_DIVISION; - counter = (uint16_t)((DEFAULT_PERIOD * CLOCK_FREQUENCY) / obj->divisor); - - // Init timer variable for using PPG mode - m_tmrb.Mode = TMRB_INTERVAL_TIMER; - m_tmrb.ClkDiv = TMRB_CLK_DIV_32; - m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR; // clear UC when matching value - m_tmrb.TrailingTiming = counter; // period = 20ms - m_tmrb.LeadingTiming = counter; // duty cycle = 0% - - // Init timer function - TMRB_Init(obj->channel, &m_tmrb); - obj->trailing_timing = counter; - obj->leading_timing = counter; - - // Enable double buffering - TMRB_SetDoubleBuf(obj->channel, ENABLE); - - // Setting to TBxFF0 reverse trigger - FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR; - FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING; - TMRB_SetFlipFlop(obj->channel, &FFStruct); - - // Start count operation - TMRB_SetRunState(obj->channel, TMRB_RUN); -} - -void pwmout_free(pwmout_t *obj) -{ - // Stops and clear count operation - TMRB_SetRunState(obj->channel, TMRB_STOP); - pwmout_write(obj,0); - obj->pin = NC; - obj->channel = NULL; - obj->trailing_timing = 0; - obj->leading_timing = 0; - obj->divisor = 0; -} - -void pwmout_write(pwmout_t *obj, float value) -{ - TMRB_FFOutputTypeDef FFStruct; - - // Stop timer for setting clock again - TMRB_SetRunState(obj->channel, TMRB_STOP); - // values outside this range will be saturated to 0.0f or 1.0f - // Disable flip-flop reverse trigger when leading_timing and trailing_timing are duplicated - if (value <= 0.0f) { - value = 0; - FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR; - FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP; - TMRB_SetFlipFlop(obj->channel, &FFStruct); - } else if (value >= 1.0f) { - value = 1; - FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET; - FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP; - TMRB_SetFlipFlop(obj->channel, &FFStruct); - } else { - FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR; - FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING; - TMRB_SetFlipFlop(obj->channel, &FFStruct); - } - - // Store the new leading_timing value - obj->leading_timing = obj->trailing_timing - (uint16_t)(obj->trailing_timing * value); - - // Setting TBxRG0 register - TMRB_ChangeLeadingTiming(obj->channel, obj->leading_timing); - TMRB_SetRunState(obj->channel, TMRB_RUN); -} - -float pwmout_read(pwmout_t *obj) -{ - float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; - return duty_cycle; -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t *obj, int us) -{ - float seconds = 0; - int cycles = 0; - uint32_t clkdiv = 0; - float duty_cycle = 0; - TMRB_InitTypeDef m_tmrb; - seconds = (float)((us) / 1000000.0f); - obj->period = seconds; - - MBED_ASSERT(obj->channel != NULL); - - // Select highest timer resolution - for (int i = 0; i < 7; ++i) { - cycles = (int)((CLOCK_FREQUENCY / prescale_tbl[i]) * seconds); - if (cycles <= MAX_COUNTER_16B) { - clkdiv = i + 1; // range 1:7 - break; - } - } - // Stop timer for setting clock again - TMRB_SetRunState(obj->channel, TMRB_STOP); - // Restore the duty-cycle - duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; - obj->trailing_timing = cycles; - obj->leading_timing = (cycles - (uint16_t)(cycles * duty_cycle)); - - // Change the source clock division and period - m_tmrb.Mode = TMRB_INTERVAL_TIMER; - m_tmrb.ClkDiv = clkdiv; - m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR; - m_tmrb.TrailingTiming = obj->trailing_timing; - m_tmrb.LeadingTiming = obj->leading_timing; - - //Init timer function - TMRB_Init(obj->channel, &m_tmrb); - //Start timer function - TMRB_SetRunState(obj->channel, TMRB_RUN); -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - float seconds = 0; - float value = 0; - - MBED_ASSERT(obj->channel != NULL); - - seconds = (float)(us / 1000000.0f); - value = (((seconds / obj->period) * 100.0f) / 100.0f); - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/reset_reason_api.c deleted file mode 100644 index 0c17fcd410..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/reset_reason_api.c +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "reset_reason_api.h" - -#ifdef DEVICE_RESET_REASON - -#include "TMPM066.h" -#include - -#define MAXRSTREASON 6 - -static uint8_t set_bit_count(uint32_t reg); -static uint8_t bit_pos(uint32_t reg); -static bool bit_status(uint32_t reg, uint8_t bit_no); - -static reset_reason_t reset_reason1[MAXRSTREASON] = { - RESET_REASON_POWER_ON, - RESET_REASON_UNKNOWN, - RESET_REASON_UNKNOWN, - RESET_REASON_PIN_RESET, - RESET_REASON_UNKNOWN, - RESET_REASON_BROWN_OUT -}; - -static reset_reason_t reset_reason2[MAXRSTREASON] = { - RESET_REASON_SOFTWARE, - RESET_REASON_UNKNOWN, - RESET_REASON_WATCHDOG -}; - -void hal_reset_reason_clear(void) -{ - TSB_AOREG->RSTFLG = 0x00; - TSB_AOREG->RSTFLG1 = 0x00; -} - -uint32_t hal_reset_reason_get_raw(void) -{ - uint32_t ret = 0x00; - - ret = (((TSB_AOREG->RSTFLG1 & 0xFF) << 8) | (TSB_AOREG->RSTFLG & 0xFF)); - - return ret; -} - -reset_reason_t hal_reset_reason_get(void) -{ - reset_reason_t ret; - - uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_AOREG->RSTFLG); - uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_AOREG->RSTFLG1); - - if (NoOfSetBitCountReg1 != 0x00) { - if (NoOfSetBitCountReg1 > 0x01) { - if (bit_status(TSB_AOREG->RSTFLG, 0) && bit_status(TSB_AOREG->RSTFLG, 3)) { - ret = RESET_REASON_POWER_ON; - } else { - ret = RESET_REASON_MULTIPLE; - } - } else { - ret = reset_reason1[bit_pos(TSB_AOREG->RSTFLG)]; - } - } else if (NoOfSetBitCountReg2 != 0x00) { - if (NoOfSetBitCountReg2 > 0x01) { - ret = RESET_REASON_MULTIPLE; - } else { - ret = reset_reason2[bit_pos(TSB_AOREG->RSTFLG1)]; - } - } else { - ret = RESET_REASON_UNKNOWN; - } - - return ret; -} - -void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) -{ - cap->reasons = 1 << RESET_REASON_UNKNOWN; - cap->reasons |= 1 << RESET_REASON_POWER_ON; - cap->reasons |= 1 << RESET_REASON_MULTIPLE; -} - -static bool bit_status(uint32_t reg, uint8_t bit_no) -{ - bool status = false; - - if (reg & (1 << bit_no)) { - status = true; - } - - return status; -} - -static uint8_t set_bit_count(uint32_t reg) -{ - uint8_t count = 0; - int8_t index = 0; - - for (index = 0; index < (sizeof(uint32_t) * 8); index++) { - if (reg & (1 << index)) { - count++; - if (count > 0x01) { - break; - } - } - } - - return count; -} - -static uint8_t bit_pos(uint32_t reg) -{ - uint8_t bit_no = 0; - - for (bit_no = 0; bit_no < (sizeof(uint32_t) * 8); bit_no++) { - if (reg & (1 << bit_no)) { - return bit_no; - } - } -} - -#endif // DEVICE_RESET_REASON diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c deleted file mode 100644 index e3a58dbe8a..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c +++ /dev/null @@ -1,281 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "serial_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define UART_NUM 2 - -static const PinMap PinMap_UART_TX[] = { - {PC2, SERIAL_0, PIN_DATA(1, 1)}, - {PE2, SERIAL_1, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PC3, SERIAL_0, PIN_DATA(1, 0)}, - {PE1, SERIAL_1, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -static int serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart_name != NC); - - obj->index = uart_name; - // Initialize UART instance - switch (uart_name) { - case SERIAL_0: - CG_SetFcPeriphA(CG_FC_PERIPH_SIO0, ENABLE); - obj->UARTx = UART0; - break; - case SERIAL_1: - CG_SetFcPeriphB(CG_FC_PERIPH_SIO1, ENABLE); - obj->UARTx = UART1; - break; - default: - break; - } - - obj->uart_config.BaudRate = 9600; - obj->uart_config.DataBits = UART_DATA_BITS_8; - obj->uart_config.StopBits = UART_STOP_BITS_1; - obj->uart_config.Parity = UART_NO_PARITY; - obj->uart_config.FlowCtrl = UART_NONE_FLOW_CTRL; - - if (tx != NC && rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; - } else { - if (tx != NC) { - obj->uart_config.Mode = UART_ENABLE_TX; - } else { - if (rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX; - } - } - } - - // Pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - // Initialize UART configure - UART_Enable(obj->UARTx); - UART_SetIdleMode(obj->UARTx, ENABLE); - UART_Init(obj->UARTx, &obj->uart_config); - is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Disable UART - UART_Disable(obj->UARTx); - UART_SWReset(obj->UARTx); - // Set information of object to invalid - obj->uart_config.BaudRate = 0; - obj->uart_config.DataBits = 0; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = 0; - obj->uart_config.Mode = 0; - obj->uart_config.FlowCtrl = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->uart_config.BaudRate = baudrate; - UART_Init(obj->UARTx, &obj->uart_config); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); - // 0: 7 data bits ... 2: 9 data bits - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); - - obj->uart_config.DataBits = data_bits; - obj->uart_config.StopBits = stop_bits; - obj->uart_config.Parity = parity; - UART_Init(obj->UARTx, &obj->uart_config); -} - -// INTERRUPTS HANDLING -void INTTX0_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); -} - -void INTRX0_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); -} - -void INTTX1_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); -} - -void INTRX1_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch (obj->index) { - case SERIAL_0: - if (irq == RxIrq) { - irq_n = INTRX0_IRQn; - } else { - irq_n = INTTX0_IRQn; - } - break; - case SERIAL_1: - if (irq == RxIrq) { - irq_n = INTRX1_IRQn; - } else { - irq_n = INTTX1_IRQn; - } - break; - default: - break; - } - - if (enable) { - NVIC_EnableIRQ(irq_n); - } else { - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) -{ - // Wait until Rx buffer is full - while (!serial_readable(obj)) { - // Do nothing - } - - return UART_GetRxData(obj->UARTx); -} - -void serial_putc(serial_t *obj, int c) -{ - // Wait until Tx buffer is empty - while (!serial_writable(obj)) { - // Do nothing - } - - UART_SetTxData(obj->UARTx, (uint32_t)c); -} - -int serial_readable(serial_t *obj) -{ - int ret = 0; - - if (UART_GetBufState(obj->UARTx, UART_RX) == DONE) { - ret = 1; - } - - return ret; -} - -int serial_writable(serial_t *obj) -{ - int ret = 0; - - if (UART_GetBufState(obj->UARTx, UART_TX) == DONE) { - ret = 1; - } - - return ret; -} - -void serial_clear(serial_t *obj) -{ - UART_TxFIFOClear(obj->UARTx); - UART_RxFIFOClear(obj->UARTx); - UART_TxBufferClear(obj->UARTx); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ -} - -void serial_break_clear(serial_t *obj) -{ -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c deleted file mode 100644 index 79ee066031..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" - -// number of warm-up cycle = warm-up time to set / input frequency cycle (s) -// number of 3*10^-6 (s) / (1/12 (MHz)) = 60000 = 0xea60 -#define CG_WUODR_INT ((uint16_t)0xea60) - -void external_losc_enable(void); - -void hal_sleep(void) -{ - // Set low power consumption mode IDLE - CG_SetSTBYMode(CG_STBY_MODE_IDLE); - // Enter idle mode - __WFI(); -} - -void hal_deepsleep(void) -{ - // Set low power consumption mode STOP1 - CG_SetSTBYMode(CG_STBY_MODE_STOP1); - // Setup warm up time - CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_EXT_HIGH, CG_WUODR_INT); - // Enter stop1 mode - __WFI(); - // Switch over from IHOSC to EHOSC - external_losc_enable(); -} - -void external_losc_enable(void) -{ - // Enable high-speed oscillator - CG_SetFoscSrc(CG_FOSC_OSC_EXT); - // Select internal(fIHOSC) as warm-up clock - CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WUODR_INT); - // Start warm-up - CG_StartWarmUp(); - // Wait until EHOSC become stable - while (CG_GetWarmUpState() != DONE) { - // Do nothing - } - - // Set fosc source - CG_SetFoscSrc(CG_FOSC_OSC_EXT); - // Wait for to become "1" - while (CG_GetFoscSrc() != CG_FOSC_OSC_EXT) { - // Do nothing - } - - // Stop IHOSC - CG_SetFoscSrc(CG_FOSC_OSC_INT); -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c deleted file mode 100644 index cc64b8aeb3..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c +++ /dev/null @@ -1,120 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "tmpm066_tmrb.h" -#include "tmpm066_intifsd.h" - -#define MAX_TICK_16_BIT 0xFFFF - -static bool us_ticker_inited = false; // Is ticker initialized yet? - -void INTTB7_IRQHandler(void) -{ - us_ticker_irq_handler(); -} - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - 3000000, // 3MHz, - 16 // 16 bit counter - }; - return &info; -} - -// initialize us_ticker -void us_ticker_init(void) -{ - TMRB_InitTypeDef m_tmrb0; - - if (us_ticker_inited) { - us_ticker_disable_interrupt(); - return; - } - us_ticker_inited = true; - - // TSB_TB7 using free-run - m_tmrb0.Mode = TMRB_INTERVAL_TIMER; - m_tmrb0.ClkDiv = TMRB_CLK_DIV_8; - m_tmrb0.UpCntCtrl = TMRB_FREE_RUN; - m_tmrb0.TrailingTiming = MAX_TICK_16_BIT; - m_tmrb0.LeadingTiming = MAX_TICK_16_BIT; - - // Enable channel 0 - TMRB_Enable(TSB_TB7); - // Stops and clear count operation - TMRB_SetRunState(TSB_TB7, TMRB_STOP); - // Mask All interrupts - TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT); - // Initialize timer - TMRB_Init(TSB_TB7, &m_tmrb0); - // Starts TSB_TB7 - TMRB_SetRunState(TSB_TB7, TMRB_RUN); -} - -uint32_t us_ticker_read(void) -{ - uint32_t ret_val = 0; - - if (!us_ticker_inited) { - us_ticker_init(); - } - - ret_val = (uint32_t)TMRB_GetUpCntValue(TSB_TB7); - - return ret_val; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - NVIC_DisableIRQ(INTTB7_IRQn); - NVIC_ClearPendingIRQ(INTTB7_IRQn); - TMRB_ChangeTrailingTiming(TSB_TB7, timestamp); - //Mask all Interrupts except trailing edge interrupt - TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT); - NVIC_EnableIRQ(INTTB7_IRQn); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INTTB7_IRQn); - NVIC_EnableIRQ(INTTB7_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - // Mask All interrupts - TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT); - // Also clear and disable interrupts by NVIC - NVIC_ClearPendingIRQ(INTTB7_IRQn); - NVIC_DisableIRQ(INTTB7_IRQn); -} - -void us_ticker_clear_interrupt(void) -{ - INTIFSD_ClearINTReq(INTIFSD_INT_SRC_TMRB_7_MDOVF); - NVIC_ClearPendingIRQ(INTTB7_IRQn); -} - -void us_ticker_free(void) -{ - TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT); - NVIC_ClearPendingIRQ(INTTB7_IRQn); - NVIC_DisableIRQ(INTTB7_IRQn); - TMRB_SetRunState(TSB_TB7, TMRB_STOP); - TMRB_Disable(TSB_TB7); -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PeripheralNames.h deleted file mode 100644 index 97f5d61cba..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PeripheralNames.h +++ /dev/null @@ -1,108 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SERIAL_0 = 0, - SERIAL_1, - SERIAL_2, - INVALID_SERIAL = (int)NC -} UARTName; - -typedef enum { - ADC_AINA0 = 0, - ADC_AINA1, - ADC_AINA2, - ADC_AINA3, - ADC_AINA4, - ADC_AINA5, - ADC_AINA6, - ADC_AINA7, - ADC_AINA8, - ADC_AINA9, - ADC_AINA10, - ADC_AINA11, - ADC_AINA12, - ADC_AINA13, - ADC_AINA14, - ADC_AINA15, - INVALID_ADC = (int)NC -} ADCName; - -typedef enum { - DAC_A0 = 0, - DAC_A1, - INVALID_DAC = (int)NC -} DACName; - -typedef enum { - SPI_0 = 0, - SPI_1, - INVALID_SPI = (int)NC -} SPIName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - INVALID_I2C = (int)NC -} I2CName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - INVALID_PWM = (int)NC -} PWMName; - -typedef enum { - GPIO_IRQ_0 = 0, - GPIO_IRQ_1, - GPIO_IRQ_2, - GPIO_IRQ_3, - GPIO_IRQ_4, - GPIO_IRQ_5, - GPIO_IRQ_6, - GPIO_IRQ_7, - GPIO_IRQ_8, - GPIO_IRQ_9, - GPIO_IRQ_A, - GPIO_IRQ_B, - GPIO_IRQ_C, - GPIO_IRQ_D, - GPIO_IRQ_E, - GPIO_IRQ_F, - INVALID_GPIO_IRQ = (int)NC -} GPIO_IRQName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART SERIAL_1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PinNames.h deleted file mode 100644 index bd6ad2e663..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PinNames.h +++ /dev/null @@ -1,121 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INOUT -} PinDirection; - -typedef enum { - // TMPM3H6 Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, - PD0 = 3 << 3, PD1, PD2, PD3, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, - PG0 = 6 << 3, PG1, - PH0 = 7 << 3, PH1, PH2, PH3, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, - PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, - PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, - PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, - PN0 = 12 << 3, PN1, PN2, PN3, PN4,PN5, - PP0 = 13 << 3, PP1, PP2, PP3, - PR0 = 14 << 3, PR1, PR2, PR3, - - // Other mbed Pin Names - LED1 = PB4, - LED2 = PB5, - LED3 = PB6, - LED4 = PB7, - - // external data bus Pin Names - D0 = PL0, - D1 = PL1, - D2 = PJ4, - D3 = PJ3, - D4 = PC4, - D5 = PC3, - D6 = PB3, - D7 = PB2, - D8 = PK1, - D9 = PJ0, - D10 = PL6, - D11 = PP1, - D12 = PP2, - D13 = PP0, - D14 = PA5, - D15 = PA4, - - A0 = PE0, - A1 = PE1, - A2 = PE2, - A3 = PE3, - A4 = PE4, - A5 = PE5, - - DAC0 = PG0, - DAC1 = PG1, - - USBTX = PJ2, - USBRX = PJ1, - - SW1 = PN4, - SW2 = PN3, - SW3 = PN2, - SW4 = PN1, - - // I2C - EEPROM_SDA = PC1, - EEPROM_SCL = PC0, - - // TSPI - MOSI = PP1, - MISO = PP2, - SCLK = PP0, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 0, - PullDown, - PullNone, - OpenDrain, - PullDefault -} PinMode; - -typedef enum { - DISABLE = 0, - ENABLE -} FunctionalState; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PortNames.h deleted file mode 100644 index 5e91d20ab3..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PortNames.h +++ /dev/null @@ -1,47 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortC, - PortD, - PortE, - PortF, - PortG, - PortH, - PortJ, - PortK, - PortL, - PortM, - PortN, - PortP, - PortR, -} PortName; - -#define IS_GPIO_PORT(param) ((param) <= PortR) // parameter checking for port number - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogin_api.c deleted file mode 100644 index 12d0a3b68d..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogin_api.c +++ /dev/null @@ -1,96 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogin_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "gpio_include.h" - -static const PinMap PinMap_ADC[] = { - {PD0, ADC_AINA0, PIN_DATA(0, 0)}, - {PD1, ADC_AINA1, PIN_DATA(0, 0)}, - {PD2, ADC_AINA2, PIN_DATA(0, 0)}, - {PD3, ADC_AINA3, PIN_DATA(0, 0)}, - {PE0, ADC_AINA4, PIN_DATA(0, 0)}, - {PE1, ADC_AINA5, PIN_DATA(0, 0)}, - {PE2, ADC_AINA6, PIN_DATA(0, 0)}, - {PE3, ADC_AINA7, PIN_DATA(0, 0)}, - {PE4, ADC_AINA8, PIN_DATA(0, 0)}, - {PE5, ADC_AINA9, PIN_DATA(0, 0)}, - {PE6, ADC_AINA10, PIN_DATA(0, 0)}, - {PF0, ADC_AINA11, PIN_DATA(0, 0)}, - {PF1, ADC_AINA12, PIN_DATA(0, 0)}, - {PF2, ADC_AINA13, PIN_DATA(0, 0)}, - {PF3, ADC_AINA14, PIN_DATA(0, 0)}, - {PF4, ADC_AINA15, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Check that pin belong to ADC module - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - obj->obj = TSB_ADA; - TSB_CG_FSYSENB_IPENB00 = ENABLE; // ADC CG Fsys Enable - pinmap_pinout(pin, PinMap_ADC); // Set pin function as ADC - obj->obj->CLK = ADC_SCLK_1; // Set sample hold time and prescale clock - obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); - TSB_CG_SPCLKEN_ADCKEN = ENABLE; // ADC Clock Enable -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t ADCResultValue = 0; - uint32_t ADCResultStored = 0; - - wait_us(3U); // Wait at least 3us to ensure the voltage is stable - obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); // Disable Conversion - obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); // Enable Conversion - obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | - ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); - - while ((obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE) { - // Wait until AD conversion complete - } - - wait_us(1U); // Wait for register to update with convert value. - ADCResultStored = obj->obj->REG0; // Convert result - - if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { - ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4); - } - - return ADCResultValue; -} - -float analogin_read(analogin_t *obj) -{ - float result = 0.0; - uint16_t value = 0; - - value = analogin_read_u16(obj); - result = ((float)value * (1.0f / (float)ADC_12BIT_RANGE)); - - return result; -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogout_api.c deleted file mode 100644 index 74bee0d0b0..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogout_api.c +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogout_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "gpio_include.h" - -static const PinMap PinMap_DAC[] = { - {DAC0, DAC_A0, PIN_DATA(0, 3)}, - {DAC1, DAC_A1, PIN_DATA(0, 3)}, - {NC, NC, 0} -}; - -void analogout_init(dac_t *obj, PinName pin) -{ - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module - MBED_ASSERT(obj->dac != (DACName)NC); - - pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC - TSB_CG_FSYSENA_IPENA06 = ENABLE; - if (obj->dac == DAC_A0) { // Compute handler - obj->handler = TSB_DA0; - TSB_CG_FSYSENB_IPENB01 = ENABLE; - } else { - if (obj->dac == DAC_A1) { - obj->handler = TSB_DA1; - TSB_CG_FSYSENB_IPENB02 = ENABLE; - } else { - obj->handler = NULL; - } - } - obj->handler->CTL = DAC_STOP; -} - -void analogout_free(dac_t *obj) -{ - obj->handler->CTL = DAC_STOP; -} - -void analogout_write(dac_t *obj, float value) -{ - uint8_t outputcode = 0; - - // Enable DAC - obj->handler->CTL = DAC_START; - - if (value < 0.0f) { - value = 0.0f; - } else { - if (value >= 1.0f) { - value = 1.0f; - } - } - - outputcode = (uint8_t)(value * 255.0f); - obj->handler->REG = outputcode; - wait_ms(3); -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - // Enable DAC - obj->handler->CTL = DAC_START; - obj->handler->REG = (uint8_t)(value & 0xFF); - wait_ms(3); -} - -float analogout_read(dac_t *obj) -{ - float result = 0.0; - uint32_t value = 0; - - value = ((obj->handler->REG) & (0xFF)); - result = ((float)value / 255.0f); - - return result; -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - uint16_t value = 0; - - value = (uint16_t)((obj->handler->REG) & (0xFF)); - - return value; -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device.h deleted file mode 100644 index 53fa475078..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device.h +++ /dev/null @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 32 -#define TRANSACTION_QUEUE_SIZE_SPI 4 - -#include "objects.h" - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TMPM3H6.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TMPM3H6.h deleted file mode 100644 index 40a7c8e538..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TMPM3H6.h +++ /dev/null @@ -1,3145 +0,0 @@ -/** - ******************************************************************************* - * @file TMPM3H6.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3H6' Device Series - * @version V1.0.9.0 - * $Date:: 2017-12-27 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER - * @{ - */ - -/** @addtogroup TMPM3H6 - * @{ - */ - -#ifndef __TMPM3H6_H__ -#define __TMPM3H6_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** TMPM3H6 Specific Interrupt Numbers *******************************************************************/ - INT00_IRQn = 0, /*!< Interrupt Pin0 */ - INT01_IRQn = 1, /*!< Interrupt Pin1 */ - INT02_IRQn = 2, /*!< Interrupt Pin2 */ - INT03_IRQn = 3, /*!< Interrupt Pin3 */ - INT04_IRQn = 4, /*!< Interrupt Pin4 */ - INT05_IRQn = 5, /*!< Interrupt Pin5 */ - INT06_IRQn = 6, /*!< Interrupt Pin6 */ - INT07_IRQn = 7, /*!< Interrupt Pin7 */ - INT08_IRQn = 8, /*!< Interrupt Pin8 */ - INT09_IRQn = 9, /*!< Interrupt Pin9 */ - INT10_IRQn = 10, /*!< Interrupt Pin10 */ - INT11_IRQn = 11, /*!< Interrupt Pin11 */ - INT12_IRQn = 12, /*!< Interrupt Pin12 */ - INT13_IRQn = 13, /*!< Interrupt Pin13 */ - INT14_IRQn = 14, /*!< Interrupt Pin14 */ - INT15_IRQn = 15, /*!< Interrupt Pin15 */ - INTEMG0_IRQn = 16, /*!< PMD0 EMG interrupt */ - INTOVV0_IRQn = 17, /*!< PMD0 OVV interrupt */ - INTPMD0_IRQn = 18, /*!< PMD0 interrupt */ - INTENC00_IRQn = 19, /*!< Encoder 0 interrupt 0 */ - INTENC01_IRQn = 20, /*!< Encoder 0 interrupt 1 */ - INTADAPDA_IRQn = 21, /*!< ADC conversion triggered by PMD is finished A */ - INTADAPDB_IRQn = 22, /*!< ADC conversion triggered by PMD is finished B */ - INTADACP0_IRQn = 23, /*!< ADC conversion monitoring function interrupt 0 */ - INTADACP1_IRQn = 24, /*!< ADC conversion monitoring function interrupt 1 */ - INTADATRG_IRQn = 25, /*!< ADC conversion triggered by General purpose is finished */ - INTADASGL_IRQn = 26, /*!< ADC conversion triggered by Single program is finished */ - INTADACNT_IRQn = 27, /*!< ADC conversion triggered by Continuity program is finished */ - INTT0RX_IRQn = 28, /*!< TSPI/SIO reception (channel 0) */ - INTT0TX_IRQn = 29, /*!< TSPI/SIO transmit (channel 0) */ - INTT0ERR_IRQn = 30, /*!< TSPI/SIO error (channel 0) */ - INTT1RX_IRQn = 31, /*!< TSPI/SIO reception (channel 1) */ - INTT1TX_IRQn = 32, /*!< TSPI/SIO transmit (channel 1) */ - INTT1ERR_IRQn = 33, /*!< TSPI/SIO error (channel 1) */ - INTI2CWUP_IRQn = 34, /*!< Serial bus interface (WakeUp) interrupt (channel 0) */ - INTI2C0_IRQn = 35, /*!< I2C0 transmission and reception interrupt */ - INTI2C0AL_IRQn = 36, /*!< I2C0 arbitration lost interrupt */ - INTI2C0BF_IRQn = 37, /*!< I2C0 bus free interrupt */ - INTI2C0NA_IRQn = 38, /*!< I2C0 no ack interrupt */ - INTI2C1_IRQn = 39, /*!< I2C1 transmission and reception interrupt */ - INTI2C1AL_IRQn = 40, /*!< I2C1 arbitration lost interrupt */ - INTI2C1BF_IRQn = 41, /*!< I2C1 bus free interrupt */ - INTI2C1NA_IRQn = 42, /*!< I2C1 no ack interrupt */ - INTI2C2_IRQn = 43, /*!< I2C2 transmission and reception interrupt */ - INTI2C2AL_IRQn = 44, /*!< I2C2 arbitration lost interrupt */ - INTI2C2BF_IRQn = 45, /*!< I2C2 bus free interrupt */ - INTI2C2NA_IRQn = 46, /*!< I2C2 no ack interrupt */ - INTUART0RX_IRQn = 47, /*!< UART reception (channel 0) */ - INTUART0TX_IRQn = 48, /*!< UART transmit (channel 0) */ - INTUART0ERR_IRQn = 49, /*!< UART error (channel 0) */ - INTUART1RX_IRQn = 50, /*!< UART reception (channel 1) */ - INTUART1TX_IRQn = 51, /*!< UART transmit (channel 1) */ - INTUART1ERR_IRQn = 52, /*!< UART error (channel 1) */ - INTUART2RX_IRQn = 53, /*!< UART reception (channel 2) */ - INTUART2TX_IRQn = 54, /*!< UART transmit (channel 2) */ - INTUART2ERR_IRQn = 55, /*!< UART error (channel 2) */ - INTT32A00A_IRQn = 56, /*!< 32bit T32A00A compare match detection 0 / Over flow / under flow*/ - INTT32A00ACAP0_IRQn = 57, /*!< 32bit T32A00A input capture 0 */ - INTT32A00ACAP1_IRQn = 58, /*!< 32bit T32A00A input capture 1 */ - INTT32A00B_IRQn = 59, /*!< 32bit T32A00B compare match detection 0 / Over flow / under flow*/ - INTT32A00BCAP0_IRQn = 60, /*!< 32bit T32A00B input capture 0 */ - INTT32A00BCAP1_IRQn = 61, /*!< 32bit T32A00B input capture 1 */ - INTT32A00C_IRQn = 62, /*!< 32bit T32A00C compare match detection 0 / Over flow / under flow*/ - INTT32A00CCAP0_IRQn = 63, /*!< 32bit T32A00C input capture 0 */ - INTT32A00CCAP1_IRQn = 64, /*!< 32bit T32A00C input capture 1 */ - INTT32A01A_IRQn = 65, /*!< 32bit T32A01A compare match detection 0 / Over flow / under flow*/ - INTT32A01ACAP0_IRQn = 66, /*!< 32bit T32A01A input capture 0 */ - INTT32A01ACAP1_IRQn = 67, /*!< 32bit T32A01A input capture 1 */ - INTT32A01B_IRQn = 68, /*!< 32bit T32A01B compare match detection 0 / Over flow / under flow*/ - INTT32A01BCAP0_IRQn = 69, /*!< 32bit T32A01B input capture 0 */ - INTT32A01BCAP1_IRQn = 70, /*!< 32bit T32A01B input capture 1 */ - INTT32A01C_IRQn = 71, /*!< 32bit T32A01C compare match detection 0 / Over flow / under flow*/ - INTT32A01CCAP0_IRQn = 72, /*!< 32bit T32A01C input capture 0 */ - INTT32A01CCAP1_IRQn = 73, /*!< 32bit T32A01C input capture 1 */ - INTT32A02A_IRQn = 74, /*!< 32bit T32A02A compare match detection 0 / Over flow / under flow*/ - INTT32A02ACAP0_IRQn = 75, /*!< 32bit T32A02A input capture 0 */ - INTT32A02ACAP1_IRQn = 76, /*!< 32bit T32A02A input capture 1 */ - INTT32A02B_IRQn = 77, /*!< 32bit T32A02B compare match detection 0 / Over flow / under flow*/ - INTT32A02BCAP0_IRQn = 78, /*!< 32bit T32A02B input capture 0 */ - INTT32A02BCAP1_IRQn = 79, /*!< 32bit T32A02B input capture 1 */ - INTT32A02C_IRQn = 80, /*!< 32bit T32A02C compare match detection 0 / Over flow / under flow*/ - INTT32A02CCAP0_IRQn = 81, /*!< 32bit T32A02C input capture 0 */ - INTT32A02CCAP1_IRQn = 82, /*!< 32bit T32A02C input capture 1 */ - INTT32A03A_IRQn = 83, /*!< 32bit T32A03A compare match detection 0 / Over flow / under flow*/ - INTT32A03ACAP0_IRQn = 84, /*!< 32bit T32A03A input capture 0 */ - INTT32A03ACAP1_IRQn = 85, /*!< 32bit T32A03A input capture 1 */ - INTT32A03B_IRQn = 86, /*!< 32bit T32A03B compare match detection 0 / Over flow / under flow*/ - INTT32A03BCAP0_IRQn = 87, /*!< 32bit T32A03B input capture 0 */ - INTT32A03BCAP1_IRQn = 88, /*!< 32bit T32A03B input capture 1 */ - INTT32A03C_IRQn = 89, /*!< 32bit T32A03C compare match detection 0 / Over flow / under flow*/ - INTT32A03CCAP0_IRQn = 90, /*!< 32bit T32A03C input capture 0 */ - INTT32A03CCAP1_IRQn = 91, /*!< 32bit T32A03C input capture 1 */ - INTT32A04A_IRQn = 92, /*!< 32bit T32A04A compare match detection 0 / Over flow / under flow*/ - INTT32A04ACAP0_IRQn = 93, /*!< 32bit T32A04A input capture 0 */ - INTT32A04ACAP1_IRQn = 94, /*!< 32bit T32A04A input capture 1 */ - INTT32A04B_IRQn = 95, /*!< 32bit T32A04B compare match detection 0 / Over flow / under flow*/ - INTT32A04BCAP0_IRQn = 96, /*!< 32bit T32A04B input capture 0 */ - INTT32A04BCAP1_IRQn = 97, /*!< 32bit T32A04B input capture 1 */ - INTT32A04C_IRQn = 98, /*!< 32bit T32A04C compare match detection 0 / Over flow / under flow*/ - INTT32A04CCAP0_IRQn = 99, /*!< 32bit T32A04C input capture 0 */ - INTT32A04CCAP1_IRQn = 100, /*!< 32bit T32A04C input capture 1 */ - INTT32A05A_IRQn = 101, /*!< 32bit T32A05A compare match detection 0 / Over flow / under flow*/ - INTT32A05ACAP0_IRQn = 102, /*!< 32bit T32A05A input capture 0 */ - INTT32A05ACAP1_IRQn = 103, /*!< 32bit T32A05A input capture 1 */ - INTT32A05B_IRQn = 104, /*!< 32bit T32A05B compare match detection 0 / Over flow / under flow*/ - INTT32A05BCAP0_IRQn = 105, /*!< 32bit T32A05B input capture 0 */ - INTT32A05BCAP1_IRQn = 106, /*!< 32bit T32A05B input capture 1 */ - INTT32A05C_IRQn = 107, /*!< 32bit T32A05C compare match detection 0 / Over flow / under flow*/ - INTT32A05CCAP0_IRQn = 108, /*!< 32bit T32A05C input capture 0 */ - INTT32A05CCAP1_IRQn = 109, /*!< 32bit T32A05C input capture 1 */ - INTDMAATC_IRQn = 110, /*!< DMA end of transfer */ - INTDMAAERR_IRQn = 111, /*!< DMA transfer error */ - INTRTC_IRQn = 112, /*!< Real time clock(XHz) interrupt */ - INTRMC0_IRQn = 114, /*!< Remote control reception interrupt */ - INTFLCRDY_IRQn = 115, /*!< Code FLASH Ready interrupt */ - INTFLDRDY_IRQn = 116 /*!< Data FLASH Ready interrupt */ -} IRQn_Type; - -/** Processor and Core Peripheral Section */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_TMPM3H6.h" /* TMPM3Hx System */ - -/** @addtogroup Device_Peripheral_registers - * @{ - */ - -/** Device Specific Peripheral registers structures */ - -/** - * @brief Interrupt control A Register - */ -typedef struct -{ - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(A) 00 */ - uint8_t RESERVED0[31]; - __IO uint8_t IMC00; /*!< Interrupu Mode Control Register(A) 00 */ - __IO uint8_t IMC01; /*!< Interrupu Mode Control Register(A) 01 */ - __IO uint8_t IMC02; /*!< Interrupu Mode Control Register(A) 02 */ - uint8_t RESERVED1[13]; - __IO uint8_t IMC16; /*!< Interrupu Mode Control Register(A) 16 */ - __IO uint8_t IMC17; /*!< Interrupu Mode Control Register(A) 17 */ -} TSB_IA_TypeDef; - -/** - * @brief Reset LOSC Management register - */ -typedef struct -{ - __IO uint8_t LOSCCR; /*!< Low OSC Control Register */ - __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ - __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ - __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ - uint8_t RESERVED0[11]; - __IO uint8_t PROTECT; /*!< Protect Register */ -} TSB_RLM_TypeDef; - -/** - * @brief I2C Wakeup control register - */ -typedef struct -{ - __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ - __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ - __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ - __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ -} TSB_I2CS_TypeDef; - -/** - * @brief LVD0 - */ -typedef struct -{ - __IO uint8_t CR; /*!< LVD Control register */ -} TSB_LVD_TypeDef; - -/** - * @brief DMA Controller - */ -typedef struct -{ - __I uint32_t STATUS; /*!< DMA Status Register */ - __O uint32_t CFG; /*!< DMA Configuration Register */ - __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ - __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base -Pointer Register*/ - uint32_t RESERVED0; - __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ - __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ - __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ - __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ - __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ - __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ - __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ - __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ - __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ - __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ - __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ - uint32_t RESERVED1[3]; - __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ -} TSB_DMA_TypeDef; - -/** - * @brief Digital analog converter (DAC) - */ -typedef struct -{ - __IO uint32_t CTL; /*!< DAC Control Register */ - __IO uint32_t REG; /*!< DAC output Register */ -} TSB_DA_TypeDef; - -/** - * @brief Serial Interface (TSPI) - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TSPI Control Register 0 */ - __IO uint32_t CR1; /*!< TSPI Control Register 1 */ - __IO uint32_t CR2; /*!< TSPI Control Register 2 */ - __IO uint32_t CR3; /*!< TSPI Control Register 3 */ - __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ - __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ - __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ - uint32_t RESERVED0[57]; - __IO uint32_t DR; /*!< TSPI Data Register */ - uint32_t RESERVED1[63]; - __IO uint32_t SR; /*!< TSPI Status Register */ - __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ -} TSB_TSPI_TypeDef; - -#if defined ( __CC_ARM ) /* RealView Compiler */ -#pragma anon_unions -#elif (defined (__ICCARM__)) /* ICC Compiler */ -#pragma language=extended -#endif - -/** - * @brief I2C - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control Register 1 */ - __IO uint32_t DBR; /*!< I2C Data Buffer Register */ - __IO uint32_t AR; /*!< I2C Bus address Register */ -union { - __O uint32_t CR2; /*!< I2C Control Register 2 */ - __I uint32_t SR; /*!< I2C Status Register */ - }; - __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ - __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ - __IO uint32_t ST; /*!< I2C Interrupt Register */ - __IO uint32_t OP; /*!< I2C Optiononal Function register */ - __I uint32_t PM; /*!< I2C Bus Monitor register */ - __IO uint32_t AR2; /*!< I2C Second Slave address register */ -} TSB_I2C_TypeDef; - -/** - * @brief ADC - */ -typedef struct -{ - __IO uint32_t CR0; /*!< AD Control Register 0 */ - __IO uint32_t CR1; /*!< AD Control Register 1 */ - __I uint32_t ST; /*!< AD Status Register */ - __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ - __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ - __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ - uint32_t RESERVED0; - __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ - __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ - __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ - __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ - __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ - uint32_t RESERVED1[3]; - __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ - __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ - __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ - __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ - __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ - __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ - __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ - __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ - __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ - __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ - __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ - __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ - __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ - __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ - __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ - __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ - __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ - __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ - __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ - __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ - __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register*/ - uint32_t RESERVED2[3]; - __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ - __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ - __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ - __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ - __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ - __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ - __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ - __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ - __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ - __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ - __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ - __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ - __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ - __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ - __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ - __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ - __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ - __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ - __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ - __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ - __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ - __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ - __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ - __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ - __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ - __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ - __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ - __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ - __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ - __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ - __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ - __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ - uint32_t RESERVED3[8]; - __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ - __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ - __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ - __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ - __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ - __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ - __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ - __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ - __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ - __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ - __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ - __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ - __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ - __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ - __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ - __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ - __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ - __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ - __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ - __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ - __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ - __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ - __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ - __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ -} TSB_AD_TypeDef; - -/** - * @brief T32A - */ -typedef struct -{ - __IO uint32_t MOD; /*!< T32A Mode Register */ - uint32_t RESERVED0[15]; - __IO uint32_t RUNA; /*!< T32A Run Register A */ - __IO uint32_t CRA; /*!< T32A Counter control Register A */ - __IO uint32_t CAPCRA; /*!< T32A Capture control Register A */ - __IO uint32_t OUTCRA0; /*!< T32A Output control Register A0 */ - __IO uint32_t OUTCRA1; /*!< T32A Output control Register A1 */ - __IO uint32_t STA; /*!< T32A Status Register A */ - __IO uint32_t IMA; /*!< T32A Interrupt mask Register A */ - __I uint32_t TMRA; /*!< T32A Counter capture Register A */ - __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ - __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ - __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ - __I uint32_t CAPA0; /*!< T32A Timer capturer A0 */ - __I uint32_t CAPA1; /*!< T32A Timer capturer A1 */ - __IO uint32_t DMAA; /*!< T32A DMA Request Enabl eRegister A */ - uint32_t RESERVED1[2]; - __IO uint32_t RUNB; /*!< T32A Run Register B */ - __IO uint32_t CRB; /*!< T32A Counter control Register B */ - __IO uint32_t CAPCRB; /*!< T32A Capture control Register B */ - __IO uint32_t OUTCRB0; /*!< T32A Output control Register B0 */ - __IO uint32_t OUTCRB1; /*!< T32A Output control Register B1 */ - __IO uint32_t STB; /*!< T32A Status Register B */ - __IO uint32_t IMB; /*!< T32A Interrupt mask Register B */ - __I uint32_t TMRB; /*!< T32A Counter capture Register B */ - __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ - __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ - __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ - __I uint32_t CAPB0; /*!< T32A Timer capturer B0 */ - __I uint32_t CAPB1; /*!< T32A Timer capturer B1 */ - __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ - uint32_t RESERVED2[2]; - __IO uint32_t RUNC; /*!< T32A Run Register C */ - __IO uint32_t CRC; /*!< T32A Counter control Register C */ - __IO uint32_t CAPCRC; /*!< T32A Capture control Register C */ - __IO uint32_t OUTCRC0; /*!< T32A Output control Register C0 */ - __IO uint32_t OUTCRC1; /*!< T32A Output control Register C1 */ - __IO uint32_t STC; /*!< T32A Status Register C */ - __IO uint32_t IMC; /*!< T32A Interrupt mask Register C */ - __I uint32_t TMRC; /*!< T32A Counter capture Register C */ - __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ - __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ - __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ - __I uint32_t CAPC0; /*!< T32A Timer capturer C0 */ - __I uint32_t CAPC1; /*!< T32A Timer capturer C1 */ - __IO uint32_t DMAC; /*!< T32A DMA Request Enabl eRegister C */ - __IO uint32_t PLSCR; /*!< T32A Pulse count control register */ -} TSB_T32A_TypeDef; - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t SWRST; /*!< UART Software reset register */ - __IO uint32_t CR0; /*!< UART Control register 0 */ - __IO uint32_t CR1; /*!< UART Control register 1 */ - __IO uint32_t CLK; /*!< UART Clock Control register */ - __IO uint32_t BRD; /*!< UART Baud rate register */ - __IO uint32_t TRANS; /*!< UART Transfer enable register */ - __IO uint32_t DR; /*!< UART Data register */ - __IO uint32_t SR; /*!< UART Status register */ - __IO uint32_t FIFOCLR; /*!< UART FIFO Clear register */ - __IO uint32_t ERR; /*!< UART Error register */ -} TSB_UART_TypeDef; - -/** - * @brief SIWD - */ -typedef struct -{ - __IO uint32_t PRO; /*!< SIWD Protect register */ - __IO uint32_t EN; /*!< SIWD Enable register */ - __O uint32_t CR; /*!< SIWD Control register */ - __IO uint32_t MOD; /*!< SIWD Mode register */ - __I uint32_t MONI; /*!< SIWD Monitor register */ - __IO uint32_t OSCCR; /*!< SIWD Oscillation control register */ -} TSB_SIWD_TypeDef; - -/** - * @brief DNF - */ -typedef struct -{ - __IO uint32_t CKCR; /*!< DNF clock Control register */ - __IO uint32_t ENCR; /*!< DNF Enable register */ -} TSB_DNF_TypeDef; - -/** - * @brief TRGSEL - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ - __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ - __IO uint32_t CR2; /*!< TSEL Control register 2 */ - __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ - __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ - __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ - __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ - __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ - __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ - __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ - __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ -} TSB_TSEL_TypeDef; - -/** - * @brief Port A - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PA Data Register */ - __IO uint32_t CR; /*!< PA Control Register */ - __IO uint32_t FR1; /*!< PA Function Register 1 */ - __IO uint32_t FR2; /*!< PA Function Register 2 */ - __IO uint32_t FR3; /*!< PA Function Register 3 */ - __IO uint32_t FR4; /*!< PA Function Register 4 */ - __IO uint32_t FR5; /*!< PA Function Register 5 */ - __IO uint32_t FR6; /*!< PA Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PA Open Drain Control Register */ - __IO uint32_t PUP; /*!< PA Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PA Input Enable Control Register */ -} TSB_PA_TypeDef; - -/** - * @brief Port B - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PB Data Register */ - __IO uint32_t CR; /*!< PB Control Register */ - __IO uint32_t FR1; /*!< PB Function Register 1 */ - __IO uint32_t FR2; /*!< PB Function Register 2 */ - __IO uint32_t FR3; /*!< PB Function Register 3 */ - __IO uint32_t FR4; /*!< PB Function Register 4 */ - __IO uint32_t FR5; /*!< PB Function Register 5 */ - __IO uint32_t FR6; /*!< PB Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PB Open Drain Control Register */ - __IO uint32_t PUP; /*!< PB Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PB Input Enable Control Register */ -} TSB_PB_TypeDef; - -/** - * @brief Port C - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PC Data Register */ - __IO uint32_t CR; /*!< PC Control Register */ - __IO uint32_t FR1; /*!< PC Function Register 1 */ - uint32_t RESERVED0; - __IO uint32_t FR3; /*!< PC Function Register 3 */ - __IO uint32_t FR4; /*!< PC Function Register 4 */ - __IO uint32_t FR5; /*!< PC Function Register 5 */ - uint32_t RESERVED1[3]; - __IO uint32_t OD; /*!< PC Open Drain Control Register */ - __IO uint32_t PUP; /*!< PC Pull-up Control Register */ - __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< PC Input Enable Control Register */ -} TSB_PC_TypeDef; - -/** - * @brief Port D - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PD Data Register */ - __IO uint32_t CR; /*!< PD Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PD Open Drain Control Register */ - __IO uint32_t PUP; /*!< PD Pull-up Control Register */ - __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PD Input Enable Control Register */ -} TSB_PD_TypeDef; - -/** - * @brief Port E - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PE Data Register */ - __IO uint32_t CR; /*!< PE Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PE Open Drain Control Register */ - __IO uint32_t PUP; /*!< PE Pull-up Control Register */ - __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PE Input Enable Control Register */ -} TSB_PE_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PF Data Register */ - __IO uint32_t CR; /*!< PF Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PF Open Drain Control Register */ - __IO uint32_t PUP; /*!< PF Pull-up Control Register */ - __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PF Input Enable Control Register */ -} TSB_PF_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PG Data Register */ - __IO uint32_t CR; /*!< PG Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PG Open Drain Control Register */ - __IO uint32_t PUP; /*!< PG Pull-up Control Register */ - __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PG Input Enable Control Register */ -} TSB_PG_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PH Data Register */ - uint32_t RESERVED0[11]; - __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PH Input Enable Control Register */ -} TSB_PH_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PJ Data Register */ - __IO uint32_t CR; /*!< PJ Control Register */ - __IO uint32_t FR1; /*!< PJ Function Register 1 */ - __IO uint32_t FR2; /*!< PJ Function Register 2 */ - __IO uint32_t FR3; /*!< PJ Function Register 3 */ - __IO uint32_t FR4; /*!< PJ Function Register 4 */ - __IO uint32_t FR5; /*!< PJ Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PJ Open Drain Control Register */ - __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ - __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PJ Input Enable Control Register */ -} TSB_PJ_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PK Data Register */ - __IO uint32_t CR; /*!< PK Control Register */ - __IO uint32_t FR1; /*!< PK Function Register 1 */ - __IO uint32_t FR2; /*!< PK Function Register 2 */ - __IO uint32_t FR3; /*!< PK Function Register 3 */ - __IO uint32_t FR4; /*!< PK Function Register 4 */ - __IO uint32_t FR5; /*!< PK Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PK Open Drain Control Register */ - __IO uint32_t PUP; /*!< PK Pull-up Control Register */ - __IO uint32_t PDN; /*!< PK Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PK Input Enable Control Register */ -} TSB_PK_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PL Data Register */ - __IO uint32_t CR; /*!< PL Control Register */ - __IO uint32_t FR1; /*!< PL Function Register 1 */ - __IO uint32_t FR2; /*!< PL Function Register 2 */ - __IO uint32_t FR3; /*!< PL Function Register 3 */ - uint32_t RESERVED0[5]; - __IO uint32_t OD; /*!< PL Open Drain Control Register */ - __IO uint32_t PUP; /*!< PL Pull-up Control Register */ - __IO uint32_t PDN; /*!< PL Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PL Input Enable Control Register */ -} TSB_PL_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PM Data Register */ - __IO uint32_t CR; /*!< PM Control Register */ - __IO uint32_t FR1; /*!< PM Function Register 1 */ - __IO uint32_t FR2; /*!< PM Function Register 2 */ - __IO uint32_t FR3; /*!< PM Function Register 3 */ - __IO uint32_t FR4; /*!< PM Function Register 4 */ - __IO uint32_t FR5; /*!< PM Function Register 5 */ - __IO uint32_t FR6; /*!< PM Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PM Open Drain Control Register */ - __IO uint32_t PUP; /*!< PM Pull-up Control Register */ - __IO uint32_t PDN; /*!< PM Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PM Input Enable Control Register */ -} TSB_PM_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PN Data Register */ - __IO uint32_t CR; /*!< PN Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t FR3; /*!< PN Function Register 3 */ - __IO uint32_t FR4; /*!< PN Function Register 4 */ - __IO uint32_t FR5; /*!< PN Function Register 5 */ - uint32_t RESERVED1[3]; - __IO uint32_t OD; /*!< PN Open Drain Control Register */ - __IO uint32_t PUP; /*!< PN Pull-up Control Register */ - __IO uint32_t PDN; /*!< PN Pull-Down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< PN Input Enable Control Register */ -} TSB_PN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PP Data Register */ - __IO uint32_t CR; /*!< PP Control Register */ - __IO uint32_t FR1; /*!< PP Function Register 1 */ - uint32_t RESERVED0; - __IO uint32_t FR3; /*!< PP Function Register 3 */ - __IO uint32_t FR4; /*!< PP Function Register 4 */ - uint32_t RESERVED1[4]; - __IO uint32_t OD; /*!< PP Open Drain Control Register */ - __IO uint32_t PUP; /*!< PP Pull-up Control Register */ - __IO uint32_t PDN; /*!< PP Pull-Down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< PP Input Enable Control Register */ -} TSB_PP_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PR Data Register */ - __IO uint32_t CR; /*!< PR Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t FR3; /*!< PR Function Register 3 */ - __IO uint32_t FR4; /*!< PR Function Register 4 */ - uint32_t RESERVED1[4]; - __IO uint32_t OD; /*!< PR Open Drain Control Register */ - __IO uint32_t PUP; /*!< PR Pull-up Control Register */ - __IO uint32_t PDN; /*!< PR Pull-Down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< PR Input Enable Control Register */ -} TSB_PR_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint8_t SECR; /*!< RTC Sec setting register */ - __IO uint8_t MINR; /*!< RTC Min settging register */ - __IO uint8_t HOURR; /*!< RTC Hour setting register */ - uint8_t RESERVED0; - __IO uint8_t DAYR; /*!< RTC Day setting register */ - __IO uint8_t DATER; /*!< RTC Date setting register */ - __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ - __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ - __IO uint8_t PAGER; /*!< RTC Page register */ - uint8_t RESERVED1[3]; - __IO uint8_t RESTR; /*!< RTC Reset register */ - uint8_t RESERVED2; - __IO uint8_t PROTECT; /*!< RTC protect register */ - __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ - __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ -} TSB_RTC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t EN; /*!< RMC Enable Register */ - __IO uint32_t REN; /*!< RMC Receive Enable Register */ - __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ - __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ - __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ - __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ - __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ - __I uint32_t RSTAT; /*!< RMC Receive Status Register */ - __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ - __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ - __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ - __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ -} TSB_RMC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t CR1; /*!< OFD Control Register 1 */ - __IO uint32_t CR2; /*!< OFD Control Register 2 */ - __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ - __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ - __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ - __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ - __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ - __I uint32_t STAT; /*!< OFD Status Register */ - __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ -} TSB_OFD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t PROTECT; /*!< CG Protect Register */ - __IO uint32_t OSCCR; /*!< CG Oscillation Control Register */ - __IO uint32_t SYSCR; /*!< CG System clock control register */ - __IO uint32_t STBYCR; /*!< CG Standby Control Register */ - __IO uint32_t SCOCR; /*!< CG SCOUT Control Register */ - uint32_t RESERVED0[3]; - __IO uint32_t PLL0SEL; /*!< CG PLL select register for fsys */ - uint32_t RESERVED1[3]; - __IO uint32_t WUPHCR; /*!< CG Warmup register for HOSC */ - __IO uint32_t WUPLCR; /*!< CG Low-speed oscillation warm-up register */ - uint32_t RESERVED2[6]; - __IO uint32_t FSYSENA; /*!< CG output control register A for fsys clock */ - __IO uint32_t FSYSENB; /*!< CG output control register B for fsys clock */ - uint32_t RESERVED3; - __IO uint32_t SPCLKEN; /*!< CG Output control register for ADC AND TRACE CLOCK*/ -} TSB_CG_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t OSCPRO; /*!< TRM Protect register */ - __IO uint32_t OSCEN; /*!< TRM Enable register */ - __I uint32_t OSCINIT; /*!< TRM Initial trimming level monitor register */ - __IO uint32_t OSCSET; /*!< TRM Trimming level setting register */ -} TSB_TRM_TypeDef; - -/** - * @brief Interrupt control register B - */ -typedef struct -{ - uint8_t RESERVED0[16]; - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(B) 00 */ - uint8_t RESERVED1[79]; - __IO uint8_t IMC000; /*!< Interrupu Mode Control Register(B) 000 */ - __IO uint8_t IMC001; /*!< Interrupu Mode Control Register(B) 001 */ - __IO uint8_t IMC002; /*!< Interrupu Mode Control Register(B) 002 */ - __IO uint8_t IMC003; /*!< Interrupu Mode Control Register(B) 003 */ - __IO uint8_t IMC004; /*!< Interrupu Mode Control Register(B) 004 */ - __IO uint8_t IMC005; /*!< Interrupu Mode Control Register(B) 005 */ - __IO uint8_t IMC006; /*!< Interrupu Mode Control Register(B) 006 */ - __IO uint8_t IMC007; /*!< Interrupu Mode Control Register(B) 007 */ - __IO uint8_t IMC008; /*!< Interrupu Mode Control Register(B) 008 */ - __IO uint8_t IMC009; /*!< Interrupu Mode Control Register(B) 009 */ - __IO uint8_t IMC010; /*!< Interrupu Mode Control Register(B) 010 */ - __IO uint8_t IMC011; /*!< Interrupu Mode Control Register(B) 011 */ - __IO uint8_t IMC012; /*!< Interrupu Mode Control Register(B) 012 */ - __IO uint8_t IMC013; /*!< Interrupu Mode Control Register(B) 013 */ - __IO uint8_t IMC014; /*!< Interrupu Mode Control Register(B) 014 */ - __IO uint8_t IMC015; /*!< Interrupu Mode Control Register(B) 015 */ - __IO uint8_t IMC016; /*!< Interrupu Mode Control Register(B) 016 */ - __IO uint8_t IMC017; /*!< Interrupu Mode Control Register(B) 017 */ - __IO uint8_t IMC018; /*!< Interrupu Mode Control Register(B) 018 */ - __IO uint8_t IMC019; /*!< Interrupu Mode Control Register(B) 019 */ - __IO uint8_t IMC020; /*!< Interrupu Mode Control Register(B) 020 */ - __IO uint8_t IMC021; /*!< Interrupu Mode Control Register(B) 021 */ - __IO uint8_t IMC022; /*!< Interrupu Mode Control Register(B) 022 */ - __IO uint8_t IMC023; /*!< Interrupu Mode Control Register(B) 023 */ - __IO uint8_t IMC024; /*!< Interrupu Mode Control Register(B) 024 */ - __IO uint8_t IMC025; /*!< Interrupu Mode Control Register(B) 025 */ - __IO uint8_t IMC026; /*!< Interrupu Mode Control Register(B) 026 */ - __IO uint8_t IMC027; /*!< Interrupu Mode Control Register(B) 027 */ - __IO uint8_t IMC028; /*!< Interrupu Mode Control Register(B) 028 */ - __IO uint8_t IMC029; /*!< Interrupu Mode Control Register(B) 029 */ - __IO uint8_t IMC030; /*!< Interrupu Mode Control Register(B) 030 */ - __IO uint8_t IMC031; /*!< Interrupu Mode Control Register(B) 031 */ - __IO uint8_t IMC032; /*!< Interrupu Mode Control Register(B) 032 */ - __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ - __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ - __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ - __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ - __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ - __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ - __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ - __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ - __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ - __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ - __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ - __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ - __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ - __IO uint8_t IMC046; /*!< Interrupu Mode Control Register(B) 046 */ -} TSB_IB_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __I uint32_t FLGNMI; /*!< Interrupt Monitor Flag 0 */ - __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 */ - uint32_t RESERVED0; - __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 */ - __I uint32_t FLG4; /*!< NMI Interrupt Monitor Flag 4 */ -} TSB_IMN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MDEN; /*!< PMD Enable Register */ - __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ - __IO uint32_t MDCR; /*!< PMD Control Register */ - __I uint32_t CNTSTA; /*!< PMD PWM Counter Status Register */ - __I uint32_t MDCNT; /*!< PMD PWM Counter Register */ - __IO uint32_t MDPRD; /*!< PMD PWM Period Register */ - __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ - __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ - __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ - uint32_t RESERVED0; - __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ - __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ - __O uint32_t EMGREL; /*!< PMD EMG Release Register */ - __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ - __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ - __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ - __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ - __IO uint32_t DTR; /*!< PMD Dead Time Register */ - __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ - __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ - __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ - __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ - __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ - __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ - __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ - __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ -} TSB_PMD_TypeDef; - -/** - * @brief Encoder Input (ENC) - */ -typedef struct -{ - __IO uint32_t TNCR; /*!< ENC Control Register */ - __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ - __IO uint32_t INT; /*!< ENC INT Compare Register */ - __IO uint32_t CNT; /*!< ENC Counter/Capture Register */ - __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ - __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ - __I uint32_t STS; /*!< ENC Status Register */ - __IO uint32_t INPCR; /*!< ENC Input Process Cntrol Register */ - __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ - __I uint32_t INPMON; /*!< ENC Input Moniter Register */ - __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ - __IO uint32_t INTCR; /*!< ENC Interrupt Reqyest Control Register */ - __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ -} TSB_EN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - uint32_t RESERVED0[4]; - __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ - __IO uint32_t SSR; /*!< Flash Security Status Register */ - __O uint32_t KCR; /*!< Flash Key Code Register */ - uint32_t RESERVED1; - __IO uint32_t SR0; /*!< Flash Status Register 0 */ - uint32_t RESERVED2[3]; - __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ - __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ - uint32_t RESERVED3[4]; - __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ - uint32_t RESERVED4; - __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ - __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ - uint32_t RESERVED5[4]; - __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ - uint32_t RESERVED6[37]; - __I uint32_t SR1; /*!< Flash Status Register 1 */ - __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ - uint32_t RESERVED7[14]; - __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ - uint32_t RESERVED8; - __IO uint32_t CR; /*!< Flash Control Register */ - __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ - __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ - uint32_t RESERVED9; - __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ -} TSB_FC_TypeDef; - - -/* Memory map */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x20000000UL) -#define PERI_BASE (0x40000000UL) - - -#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) -#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) -#define TSB_I2CS_BASE (PERI_BASE + 0x003E800UL) -#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) -#define TSB_DMAA_BASE (PERI_BASE + 0x004C000UL) -#define TSB_DA0_BASE (PERI_BASE + 0x0054000UL) -#define TSB_DA1_BASE (PERI_BASE + 0x0055000UL) -#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) -#define TSB_TSPI1_BASE (PERI_BASE + 0x0099000UL) -#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) -#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) -#define TSB_I2C2_BASE (PERI_BASE + 0x00A2000UL) -#define TSB_ADA_BASE (PERI_BASE + 0x00B8800UL) -#define TSB_T32A0_BASE (PERI_BASE + 0x00BA000UL) -#define TSB_T32A1_BASE (PERI_BASE + 0x00BA100UL) -#define TSB_T32A2_BASE (PERI_BASE + 0x00BA200UL) -#define TSB_T32A3_BASE (PERI_BASE + 0x00BA300UL) -#define TSB_T32A4_BASE (PERI_BASE + 0x00BA400UL) -#define TSB_T32A5_BASE (PERI_BASE + 0x00BA500UL) -#define TSB_UART0_BASE (PERI_BASE + 0x00BB000UL) -#define TSB_UART1_BASE (PERI_BASE + 0x00BB100UL) -#define TSB_UART2_BASE (PERI_BASE + 0x00BB200UL) -#define TSB_SIWD0_BASE (PERI_BASE + 0x00BB400UL) -#define TSB_DNFA_BASE (PERI_BASE + 0x00BB600UL) -#define TSB_TSEL0_BASE (PERI_BASE + 0x00BB800UL) -#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) -#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) -#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) -#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) -#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) -#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) -#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) -#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) -#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) -#define TSB_PK_BASE (PERI_BASE + 0x00C0900UL) -#define TSB_PL_BASE (PERI_BASE + 0x00C0A00UL) -#define TSB_PM_BASE (PERI_BASE + 0x00C0B00UL) -#define TSB_PN_BASE (PERI_BASE + 0x00C0C00UL) -#define TSB_PP_BASE (PERI_BASE + 0x00C0D00UL) -#define TSB_PR_BASE (PERI_BASE + 0x00C0E00UL) -#define TSB_RTC_BASE (PERI_BASE + 0x00CC000UL) -#define TSB_RMC0_BASE (PERI_BASE + 0x00E7000UL) -#define TSB_OFD_BASE (PERI_BASE + 0x00F1000UL) -#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) -#define TSB_TRM_BASE (PERI_BASE + 0x00F3200UL) -#define TSB_IB_BASE (PERI_BASE + 0x00F4E00UL) -#define TSB_IMN_BASE (PERI_BASE + 0x00F4F00UL) -#define TSB_PMD0_BASE (PERI_BASE + 0x00F6000UL) -#define TSB_EN0_BASE (PERI_BASE + 0x00F7000UL) -#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) - - -/* Peripheral declaration */ -#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) -#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) -#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) -#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) -#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) -#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) -#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) -#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) -#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) -#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) -#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) -#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) -#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) -#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) -#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) -#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) -#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) -#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) -#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) -#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) -#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) -#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) -#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) -#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) -#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) -#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) -#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) -#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) -#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) -#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) -#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) -#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) -#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) -#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) -#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) -#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) -#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) -#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) -#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) -#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) -#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) -#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) -#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) -#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) -#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) -#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) -#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) -#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) -#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) -#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) - - -/* Bit-Band for Device Specific Peripheral Registers */ -#define BITBAND_OFFSET (0x02000000UL) -#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) -#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) - - - - - - - -/* DMA Controller */ -#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) -#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) -#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) - - -/* Digital analog converter (DAC) */ -#define TSB_DA0_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CTL,0))) - -#define TSB_DA1_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CTL,0))) - - -/* Serial Interface (TSPI) */ -#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) -#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) -#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) -#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) -#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) -#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) -#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) -#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) -#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) -#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) -#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) -#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) -#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) -#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) -#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) -#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) -#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) -#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) -#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) -#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) -#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) -#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) -#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) -#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) -#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) -#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) -#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) -#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) -#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) -#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) -#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) -#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) -#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) -#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) -#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) -#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) -#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) -#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) - -#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) -#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) -#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) -#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) -#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) -#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) -#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) -#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) -#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) -#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) -#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) -#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) -#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) -#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) -#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) -#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) -#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) -#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) -#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) -#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) -#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) -#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) -#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) -#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) -#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) -#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) -#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) -#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) -#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) -#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) -#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) -#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) -#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) -#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) -#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) -#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) -#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) -#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) - - -/* I2C */ -#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) -#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) -#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) -#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) -#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) -#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) -#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) -#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) -#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) -#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) -#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) -#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) -#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) -#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) -#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) -#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) -#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) -#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) -#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) -#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) -#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) -#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) -#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) -#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) -#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) -#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) -#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) -#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) -#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) -#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) -#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) -#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) -#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) -#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) -#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) -#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) -#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) -#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) - -#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) -#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) -#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) -#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) -#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) -#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) -#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) -#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) -#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) -#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) -#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) -#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) -#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) -#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) -#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) -#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) -#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) -#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) -#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) -#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) -#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) -#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) -#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) -#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) -#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) -#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) -#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) -#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) -#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) -#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) -#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) -#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) -#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) -#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) -#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) -#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) -#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) -#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) - -#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) -#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) -#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) -#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) -#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) -#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) -#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) -#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) -#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) -#define TSB_I2C2_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) -#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) -#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) -#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) -#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) -#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) -#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) -#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) -#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) -#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) -#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) -#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) -#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) -#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) -#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) -#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) -#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) -#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) -#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) -#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) -#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) -#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) -#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) -#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) -#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) -#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) -#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) -#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) -#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) - - -/* ADC */ -#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) -#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) -#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) -#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) -#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) -#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) -#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) -#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) -#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) -#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) -#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) -#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) -#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) -#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) -#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) -#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) -#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) -#define TSB_ADA_CMPCR0_COMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) -#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) -#define TSB_ADA_CMPCR1_COMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) -#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) -#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) -#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) -#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) -#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) -#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) -#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) -#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) -#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) -#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) -#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) -#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) -#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) -#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) -#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) -#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) -#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) -#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) -#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) -#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) -#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) -#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) -#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) -#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) -#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) -#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) -#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) -#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) -#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) -#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) -#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) -#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) -#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) -#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) -#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) -#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) -#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) -#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) -#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) -#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) -#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) -#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) -#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) -#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) -#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) -#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) -#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) -#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) -#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) -#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) -#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) -#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) -#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) -#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) -#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) -#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) -#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) -#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) -#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) -#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) -#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) -#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) -#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) -#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) -#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) -#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) -#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) -#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) -#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) -#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) -#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) -#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) -#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) -#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) -#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) -#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) -#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) -#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) -#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) -#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) -#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) -#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) -#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) -#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) -#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) -#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) -#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) -#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) -#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) -#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) -#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) -#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) -#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) -#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) -#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) -#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) -#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) -#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) -#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) -#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) -#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) -#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) -#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) -#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) -#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) -#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) -#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) -#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) -#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) -#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) -#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) -#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) -#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) -#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) -#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) -#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) -#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) -#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) -#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) -#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) -#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) -#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) -#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) -#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) -#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) -#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) -#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) -#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) -#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) -#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) -#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) -#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) -#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) -#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) -#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) -#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) -#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) -#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) -#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) -#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) -#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) -#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) -#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) -#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) -#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) -#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) -#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) -#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) -#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) -#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) -#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) -#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) -#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) -#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) -#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) -#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) -#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) -#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) -#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) -#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) -#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) -#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) -#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) -#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) - - -/* T32A */ -#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) -#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) -#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) -#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) -#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) -#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) -#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) -#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) -#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) -#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) -#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) -#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) -#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) -#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) -#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) -#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) -#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) -#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) -#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) -#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) -#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) -#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) -#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) -#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) -#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) -#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) -#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) -#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) -#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) -#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) -#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) -#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) -#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) -#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) -#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) -#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) -#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) -#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) -#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) -#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) -#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) -#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) -#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) -#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) -#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) -#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) -#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) -#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) -#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) -#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) -#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) -#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) -#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) -#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) - -#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) -#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) -#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) -#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) -#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) -#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) -#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) -#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) -#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) -#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) -#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) -#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) -#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) -#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) -#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) -#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) -#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) -#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) -#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) -#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) -#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) -#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) -#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) -#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) -#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) -#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) -#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) -#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) -#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) -#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) -#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) -#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) -#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) -#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) -#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) -#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) -#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) -#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) -#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) -#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) -#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) -#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) -#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) -#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) -#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) -#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) -#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) -#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) -#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) -#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) -#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) -#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) -#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) -#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) - -#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) -#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) -#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) -#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) -#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) -#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) -#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) -#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) -#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) -#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) -#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) -#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) -#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) -#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) -#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) -#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) -#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) -#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) -#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) -#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) -#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) -#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) -#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) -#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) -#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) -#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) -#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) -#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) -#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) -#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) -#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) -#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) -#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) -#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) -#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) -#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) -#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) -#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) -#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) -#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) -#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) -#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) -#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) -#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) -#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) -#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) -#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) -#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) -#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) -#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) -#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) -#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) -#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) -#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) - -#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) -#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) -#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) -#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) -#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) -#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) -#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) -#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) -#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) -#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) -#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) -#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) -#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) -#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) -#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) -#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) -#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) -#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) -#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) -#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) -#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) -#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) -#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) -#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) -#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) -#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) -#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) -#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) -#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) -#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) -#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) -#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) -#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) -#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) -#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) -#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) -#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) -#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) -#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) -#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) -#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) -#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) -#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) -#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) -#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) -#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) -#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) -#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) -#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) -#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) -#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) -#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) -#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) -#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) - -#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) -#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) -#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) -#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) -#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) -#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) -#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) -#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) -#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) -#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) -#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) -#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) -#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) -#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) -#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) -#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) -#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) -#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) -#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) -#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) -#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) -#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) -#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) -#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) -#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) -#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) -#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) -#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) -#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) -#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) -#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) -#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) -#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) -#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) -#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) -#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) -#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) -#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) -#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) -#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) -#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) -#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) -#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) -#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) -#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) -#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) -#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) -#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) -#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) -#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) -#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) -#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) -#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) -#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) - -#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) -#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) -#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) -#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) -#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) -#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) -#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) -#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) -#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) -#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) -#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) -#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) -#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) -#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) -#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) -#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) -#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) -#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) -#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) -#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) -#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) -#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) -#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) -#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) -#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) -#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) -#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) -#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) -#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) -#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) -#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) -#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) -#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) -#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) -#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) -#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) -#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) -#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) -#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) -#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) -#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) -#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) -#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) -#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) -#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) -#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) -#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) -#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) -#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) -#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) -#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) -#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) -#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) -#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) - - -/* UART */ -#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) -#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) -#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) -#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) -#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) -#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) -#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) -#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) -#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) -#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) -#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) -#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) -#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) -#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) -#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) -#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) -#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) -#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) -#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) -#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) -#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) -#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) -#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) -#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) -#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) -#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) -#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) -#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) -#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) -#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) -#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) -#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) -#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) -#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) -#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) -#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) -#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) -#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) -#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) -#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) -#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) -#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) - -#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) -#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) -#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) -#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) -#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) -#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) -#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) -#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) -#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) -#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) -#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) -#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) -#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) -#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) -#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) -#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) -#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) -#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) -#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) -#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) -#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) -#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) -#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) -#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) -#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) -#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) -#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) -#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) -#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) -#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) -#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) -#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) -#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) -#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) -#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) -#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) -#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) -#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) -#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) -#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) -#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) -#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) - -#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) -#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) -#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) -#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) -#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) -#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) -#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) -#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) -#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) -#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) -#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) -#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) -#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) -#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) -#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) -#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) -#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) -#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) -#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) -#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) -#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) -#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) -#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) -#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) -#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) -#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) -#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) -#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) -#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) -#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) -#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) -#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) -#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) -#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) -#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) -#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) -#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) -#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) -#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) -#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) -#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) -#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) - - -/* SIWD */ -#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) -#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) -#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) -#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) -#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) - - -/* DNF */ -#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) -#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) -#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) -#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) -#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) -#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) -#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) -#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) -#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) -#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) -#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) -#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) -#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) -#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) -#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) -#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) - - -/* TRGSEL */ -#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) -#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) -#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) -#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) -#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) -#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) -#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) -#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) -#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) -#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) -#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) -#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) -#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) -#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) -#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) -#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) -#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) -#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) -#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) -#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) -#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) -#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) -#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) -#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) -#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) -#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) -#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) -#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) -#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) -#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) -#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) -#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) -#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) -#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) -#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) -#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) -#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) -#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) -#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) -#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) -#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) -#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) -#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) -#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) -#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) -#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) -#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) -#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) -#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) -#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) -#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) -#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) -#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) -#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) -#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) -#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) -#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) -#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) -#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) -#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) -#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) -#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) -#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) -#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) -#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) -#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) -#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) -#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) -#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) -#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) -#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) -#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) -#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) -#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) -#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) -#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) -#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) -#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) -#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) -#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) -#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) -#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) -#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) -#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) -#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) -#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) -#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) -#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) -#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) -#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) -#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) -#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) -#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) -#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) -#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) -#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) -#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) -#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) -#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) -#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) -#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) -#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) -#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) -#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) -#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) -#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) -#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) -#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) -#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) -#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) -#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) -#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) -#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) -#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) -#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) -#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) -#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) -#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) -#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) -#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) -#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) -#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) -#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) - - -/* Port A */ -#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) -#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) -#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) -#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) -#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) -#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) -#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) -#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) -#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) -#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) -#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) -#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) -#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) -#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) -#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) -#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) -#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) -#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) -#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) -#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) -#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) -#define TSB_PA_FR2_PA1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,1))) -#define TSB_PA_FR2_PA2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,2))) -#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) -#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) -#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) -#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) -#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) -#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) -#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) -#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) -#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) -#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) -#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) -#define TSB_PA_FR4_PA5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,5))) -#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) -#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) -#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) -#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) -#define TSB_PA_FR6_PA1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,1))) -#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) -#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) -#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) -#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) -#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) -#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) -#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) -#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) -#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) -#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) -#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) -#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) -#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) -#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) -#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) -#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) -#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) -#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) -#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) -#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) -#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) -#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) -#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) -#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) -#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) -#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) -#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) -#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) -#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) -#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) -#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) -#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) -#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) -#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) - - -/* Port B */ -#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) -#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) -#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) -#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) -#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) -#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) -#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) -#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) -#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) -#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) -#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) -#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) -#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) -#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) -#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) -#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) -#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) -#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) -#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) -#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) -#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) -#define TSB_PB_FR2_PB2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,2))) -#define TSB_PB_FR2_PB3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,3))) -#define TSB_PB_FR2_PB4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,4))) -#define TSB_PB_FR2_PB5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,5))) -#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) -#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) -#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) -#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) -#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) -#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) -#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) -#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) -#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) -#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) -#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) -#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) -#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) -#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) -#define TSB_PB_FR5_PB5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,5))) -#define TSB_PB_FR6_PB0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,0))) -#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) -#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) -#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) -#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) -#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) -#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) -#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) -#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) -#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) -#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) -#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) -#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) -#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) -#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) -#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) -#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) -#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) -#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) -#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) -#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) -#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) -#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) -#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) -#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) -#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) -#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) -#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) -#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) -#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) -#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) -#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) -#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) - - -/* Port C */ -#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) -#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) -#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) -#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) -#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) -#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) -#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) -#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) -#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) -#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) -#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) -#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) -#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) -#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) -#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) -#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) -#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) -#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) -#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) -#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) -#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) -#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) -#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) -#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) -#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) -#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) -#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) -#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) -#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) -#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) -#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) -#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) -#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) -#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) -#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) -#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) -#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) -#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) -#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) -#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) -#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) -#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) -#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) -#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) -#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) -#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) -#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) -#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) -#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) -#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) -#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) -#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) -#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) -#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) - - -/* Port D */ -#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) -#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) -#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) -#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) -#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) -#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) -#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) -#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) -#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) -#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) -#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) -#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) -#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) -#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) -#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) -#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) -#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) -#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) -#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) -#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) -#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) -#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) -#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) - - -/* Port E */ -#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) -#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) -#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) -#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) -#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) -#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) -#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) -#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) -#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) -#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) -#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) -#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) -#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) -#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) -#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) -#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) -#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) -#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) -#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) -#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) -#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) -#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) -#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) -#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) -#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) -#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) -#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) -#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) -#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) -#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) -#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) -#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) -#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) -#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) -#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) -#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) -#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) -#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) -#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) -#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) -#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) -#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) - - -/* */ -#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) -#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) -#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) -#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) -#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) -#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) -#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) -#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) -#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) -#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) -#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) -#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) -#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) -#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) -#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) -#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) -#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) -#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) -#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) -#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) -#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) -#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) -#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) -#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) -#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) -#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) -#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) -#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) -#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) -#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) - - -/* */ -#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) -#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) -#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) -#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) -#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) -#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) -#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) -#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) -#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) -#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) -#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) -#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) - - -/* */ -#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) -#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) -#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) -#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) -#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) -#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) -#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) -#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) -#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) -#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) -#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) -#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) - - -/* */ -#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) -#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) -#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) -#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) -#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) -#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) -#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) -#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) -#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) -#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) -#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) -#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) -#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) -#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) -#define TSB_PJ_FR1_PJ2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,2))) -#define TSB_PJ_FR1_PJ3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,3))) -#define TSB_PJ_FR1_PJ4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,4))) -#define TSB_PJ_FR2_PJ1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,1))) -#define TSB_PJ_FR2_PJ2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,2))) -#define TSB_PJ_FR2_PJ3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,3))) -#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) -#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) -#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) -#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) -#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) -#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) -#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) -#define TSB_PJ_FR4_PJ0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,0))) -#define TSB_PJ_FR4_PJ1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,1))) -#define TSB_PJ_FR4_PJ2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,2))) -#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) -#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) -#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) -#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) -#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) -#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) -#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) -#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) -#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) -#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) -#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) -#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) -#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) -#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) -#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) -#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) -#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) -#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) -#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) -#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) -#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) -#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) -#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) -#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) -#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) -#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) -#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) -#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) -#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) -#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) - - -/* */ -#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) -#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) -#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) -#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) -#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) -#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) -#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) -#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) -#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) -#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) -#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) -#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) -#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) -#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) -#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) -#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) -#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) -#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) -#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) -#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) -#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) -#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) -#define TSB_PK_FR2_PK2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,2))) -#define TSB_PK_FR2_PK3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,3))) -#define TSB_PK_FR2_PK4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,4))) -#define TSB_PK_FR3_PK2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,2))) -#define TSB_PK_FR3_PK3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,3))) -#define TSB_PK_FR3_PK4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,4))) -#define TSB_PK_FR3_PK5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,5))) -#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) -#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) -#define TSB_PK_FR4_PK2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,2))) -#define TSB_PK_FR4_PK3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,3))) -#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) -#define TSB_PK_FR5_PK0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,0))) -#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) -#define TSB_PK_FR5_PK2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,2))) -#define TSB_PK_FR5_PK3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,3))) -#define TSB_PK_FR5_PK4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,4))) -#define TSB_PK_FR5_PK5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,5))) -#define TSB_PK_FR5_PK6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,6))) -#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) -#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) -#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) -#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) -#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) -#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) -#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) -#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) -#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) -#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) -#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) -#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) -#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) -#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) -#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) -#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) -#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) -#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) -#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) -#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) -#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) -#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) -#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) -#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) -#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) -#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) -#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) -#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) -#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) -#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) -#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) -#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) - - -/* */ -#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) -#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) -#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) -#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) -#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) -#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) -#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) -#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) -#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) -#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) -#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) -#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) -#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) -#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) -#define TSB_PL_FR1_PL0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,0))) -#define TSB_PL_FR1_PL1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,1))) -#define TSB_PL_FR1_PL2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,2))) -#define TSB_PL_FR1_PL3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,3))) -#define TSB_PL_FR1_PL5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,5))) -#define TSB_PL_FR1_PL6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,6))) -#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) -#define TSB_PL_FR2_PL1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,1))) -#define TSB_PL_FR2_PL2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,2))) -#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) -#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6))) -#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) -#define TSB_PL_FR3_PL1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,1))) -#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) -#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) -#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) -#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) -#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) -#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) -#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) -#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) -#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) -#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) -#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) -#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) -#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) -#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) -#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) -#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) -#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) -#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) -#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) -#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) -#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) -#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) -#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) -#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) -#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) -#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) -#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) -#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) - - -/* */ -#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) -#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) -#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) -#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) -#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) -#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) -#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) -#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) -#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) -#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) -#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) -#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) -#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) -#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) -#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) -#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) -#define TSB_PM_FR1_PM2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,2))) -#define TSB_PM_FR1_PM3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,3))) -#define TSB_PM_FR1_PM4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,4))) -#define TSB_PM_FR2_PM1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,1))) -#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) -#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) -#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) -#define TSB_PM_FR3_PM0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,0))) -#define TSB_PM_FR3_PM1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,1))) -#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) -#define TSB_PM_FR3_PM3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,3))) -#define TSB_PM_FR3_PM4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,4))) -#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) -#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) -#define TSB_PM_FR4_PM2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,2))) -#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) -#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) -#define TSB_PM_FR4_PM5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,5))) -#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) -#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) -#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) -#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) -#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) -#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) -#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) -#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) -#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) -#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) -#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) -#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) -#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) -#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) -#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) -#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) -#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) -#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) -#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) -#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) -#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) -#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) -#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) -#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) -#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) -#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) -#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) -#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) -#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) -#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) -#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) -#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) -#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) -#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) -#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) -#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) -#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) - - -/* */ -#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) -#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) -#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) -#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) -#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) -#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) -#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) -#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) -#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) -#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) -#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) -#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) -#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) -#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) -#define TSB_PN_FR3_PN2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,2))) -#define TSB_PN_FR3_PN3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,3))) -#define TSB_PN_FR3_PN4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,4))) -#define TSB_PN_FR3_PN5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,5))) -#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) -#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) -#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) -#define TSB_PN_FR5_PN3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,3))) -#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) -#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) -#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) -#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) -#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) -#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) -#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) -#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) -#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) -#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) -#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) -#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) -#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) -#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) -#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) -#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) -#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) -#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) -#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) -#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) -#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) -#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) -#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) -#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) - - -/* */ -#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) -#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) -#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) -#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) -#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) -#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) -#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) -#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) -#define TSB_PP_FR1_PP0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,0))) -#define TSB_PP_FR1_PP1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,1))) -#define TSB_PP_FR1_PP2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,2))) -#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) -#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) -#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) -#define TSB_PP_FR4_PP0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,0))) -#define TSB_PP_FR4_PP1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,1))) -#define TSB_PP_FR4_PP2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,2))) -#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) -#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) -#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) -#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) -#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) -#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) -#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) -#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) -#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) -#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) -#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) -#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) -#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) -#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) -#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) -#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) - - -/* */ -#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) -#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) -#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) -#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) -#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) -#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) -#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) -#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) -#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) -#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) -#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) -#define TSB_PR_FR4_PR0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,0))) -#define TSB_PR_FR4_PR1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,1))) -#define TSB_PR_FR4_PR2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,2))) -#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) -#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) -#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) -#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) -#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) -#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) -#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) -#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) -#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) -#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) -#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) -#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) -#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) -#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) -#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) -#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) - - -/* */ -#define TSB_RTC_ADJCTL_AJEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJCTL,0))) - - -/* */ -#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) -#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) -#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) -#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) -#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) -#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) -#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) -#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) -#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) -#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) -#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) -#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) -#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) - - -/* */ -#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) -#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) -#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) -#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) - - -/* */ -#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) -#define TSB_CG_OSCCR_IHOSC2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,3))) -#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) -#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) -#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) -#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) -#define TSB_CG_SCOCR_SCOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SCOCR,0))) -#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) -#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) -#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) -#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) -#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) -#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) -#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) -#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) -#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) -#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) -#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) -#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) -#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) -#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) -#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) -#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) -#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) -#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) -#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) -#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) -#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) -#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) -#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) -#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) -#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) -#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) -#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) -#define TSB_CG_FSYSENA_IPENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,19))) -#define TSB_CG_FSYSENA_IPENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,20))) -#define TSB_CG_FSYSENA_IPENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,21))) -#define TSB_CG_FSYSENA_IPENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,22))) -#define TSB_CG_FSYSENA_IPENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,23))) -#define TSB_CG_FSYSENA_IPENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,24))) -#define TSB_CG_FSYSENA_IPENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,25))) -#define TSB_CG_FSYSENA_IPENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,26))) -#define TSB_CG_FSYSENA_IPENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,27))) -#define TSB_CG_FSYSENA_IPENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,28))) -#define TSB_CG_FSYSENA_IPENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,29))) -#define TSB_CG_FSYSENA_IPENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,30))) -#define TSB_CG_FSYSENA_IPENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,31))) -#define TSB_CG_FSYSENB_IPENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,0))) -#define TSB_CG_FSYSENB_IPENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,1))) -#define TSB_CG_FSYSENB_IPENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,2))) -#define TSB_CG_FSYSENB_IPENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,3))) -#define TSB_CG_FSYSENB_IPENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,4))) -#define TSB_CG_FSYSENB_IPENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,5))) -#define TSB_CG_FSYSENB_IPENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,6))) -#define TSB_CG_FSYSENB_IPENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,7))) -#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) -#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) -#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) - - -/* */ -#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) - - - -/* */ -#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) -#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) -#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) -#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) -#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) -#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) -#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) -#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) -#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) -#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) -#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) -#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) -#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) -#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) -#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) -#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) -#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) -#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) -#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) -#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) -#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) -#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) -#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) -#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) -#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) -#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) -#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) -#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) -#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) -#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) -#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) -#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) -#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) -#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) -#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) -#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) -#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) -#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) -#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) -#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) -#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) -#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) -#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) -#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) -#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) -#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) -#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) -#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) -#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) -#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) -#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) -#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) -#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) -#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) - - -/* */ -#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) -#define TSB_PMD0_MDCR_PWMMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,0))) -#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) -#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) -#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) -#define TSB_PMD0_MDCR_PWMCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) -#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) -#define TSB_PMD0_CNTSTA_UPDWN (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CNTSTA,0))) -#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) -#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) -#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) -#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) -#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) -#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) -#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) -#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) -#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) -#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) -#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) -#define TSB_PMD0_OVVCR_OVVRS (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) -#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) -#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) -#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) -#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) -#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) -#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) -#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) -#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) -#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) -#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) -#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) - - -/* Encoder Input (ENC) */ -#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) -#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) -#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) -#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) -#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) -#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) -#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) -#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) -#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) -#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) -#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) -#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) -#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) -#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) -#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) -#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) -#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) -#define TSB_EN0_INPCR_SYNCSPLND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) -#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) -#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) -#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) -#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) -#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) -#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) -#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) -#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) -#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) -#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) -#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) -#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) -#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) -#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) -#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) -#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) -#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) -#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) -#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) -#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) -#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) - -/** @} */ /* End of group Device_Peripheral_registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* __TMPM3H6_H__ */ - -/** @} */ /* End of group TMPM3H6 */ -/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/startup_TMPM3H6.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/startup_TMPM3H6.S deleted file mode 100644 index 8cffcd4f95..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/startup_TMPM3H6.S +++ /dev/null @@ -1,464 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3H6.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3H6' Device Series -; * @version V1.0.0.0 -; * $Date:: #$ -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin0 - DCD INT01_IRQHandler ; 1: Interrupt Pin1 - DCD INT02_IRQHandler ; 2: Interrupt Pin2 - DCD INT03_IRQHandler ; 3: Interrupt Pin3 - DCD INT04_IRQHandler ; 4: Interrupt Pin4 - DCD INT05_IRQHandler ; 5: Interrupt Pin5 - DCD INT06_IRQHandler ; 6: Interrupt Pin6 - DCD INT07_IRQHandler ; 7: Interrupt Pin7 - DCD INT08_IRQHandler ; 8: Interrupt Pin8 - DCD INT09_IRQHandler ; 9: Interrupt Pin9 - DCD INT10_IRQHandler ; 10: Interrupt Pin10 - DCD INT11_IRQHandler ; 11: Interrupt Pin11 - DCD INT12_IRQHandler ; 12: Interrupt Pin12 - DCD INT13_IRQHandler ; 13: Interrupt Pin13 - DCD INT14_IRQHandler ; 14: Interrupt Pin14 - DCD INT15_IRQHandler ; 15: Interrupt Pin15 - DCD INTEMG0_IRQHandler ; 16: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 17: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 18: PMD0 interrupt - DCD INTENC00_IRQHandler ; 19: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 20: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 21: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 22: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 23: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 24: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 25: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 26: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 27: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 28: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 29: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 30: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 31: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 32: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 33: TSPI/SIO error (channel 1) - DCD INTI2CWUP_IRQHandler ; 34: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 35: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 36: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 37: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 38: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 39: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 40: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 41: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 42: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 43: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 44: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 45: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 46: I2C2 no ack interrupt - DCD INTUART0RX_IRQHandler ; 47: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 48: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 49: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 50: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 51: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 52: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 53: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 54: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 55: UART error (channel 2) - DCD INTT32A00A_IRQHandler ; 56: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 57: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 58: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 59: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 60: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 61: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 62: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 63: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 64: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 65: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 66: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 67: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 68: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 69: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 70: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 71: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 72: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 73: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 74: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 75: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 76: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 77: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 78: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 79: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 80: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 81: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 82: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 83: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 84: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 85: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 86: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 87: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 88: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 89: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 90: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 91: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 92: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 93: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 94: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 95: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 96: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 97: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 98: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 99: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 100: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 101: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 102: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 103: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 104: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 105: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 106: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 107: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 108: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 109: 32bit T32A05C input capture 1 - DCD INTDMAATC_IRQHandler ; 110: DMA end of transfer - DCD INTDMAAERR_IRQHandler ; 111: DMA transfer error - DCD INTRTC_IRQHandler ; 112: Real time clock(XHz) interrupt - DCD 0 ; 113: Reserved - DCD INTRMC0_IRQHandler ; 114: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 115: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 116: Data FLASH Ready interrupt - - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT00_IRQHandler [WEAK] - EXPORT INT01_IRQHandler [WEAK] - EXPORT INT02_IRQHandler [WEAK] - EXPORT INT03_IRQHandler [WEAK] - EXPORT INT04_IRQHandler [WEAK] - EXPORT INT05_IRQHandler [WEAK] - EXPORT INT06_IRQHandler [WEAK] - EXPORT INT07_IRQHandler [WEAK] - EXPORT INT08_IRQHandler [WEAK] - EXPORT INT09_IRQHandler [WEAK] - EXPORT INT10_IRQHandler [WEAK] - EXPORT INT11_IRQHandler [WEAK] - EXPORT INT12_IRQHandler [WEAK] - EXPORT INT13_IRQHandler [WEAK] - EXPORT INT14_IRQHandler [WEAK] - EXPORT INT15_IRQHandler [WEAK] - EXPORT INTEMG0_IRQHandler [WEAK] - EXPORT INTOVV0_IRQHandler [WEAK] - EXPORT INTPMD0_IRQHandler [WEAK] - EXPORT INTENC00_IRQHandler [WEAK] - EXPORT INTENC01_IRQHandler [WEAK] - EXPORT INTADAPDA_IRQHandler [WEAK] - EXPORT INTADAPDB_IRQHandler [WEAK] - EXPORT INTADACP0_IRQHandler [WEAK] - EXPORT INTADACP1_IRQHandler [WEAK] - EXPORT INTADATRG_IRQHandler [WEAK] - EXPORT INTADASGL_IRQHandler [WEAK] - EXPORT INTADACNT_IRQHandler [WEAK] - EXPORT INTT0RX_IRQHandler [WEAK] - EXPORT INTT0TX_IRQHandler [WEAK] - EXPORT INTT0ERR_IRQHandler [WEAK] - EXPORT INTT1RX_IRQHandler [WEAK] - EXPORT INTT1TX_IRQHandler [WEAK] - EXPORT INTT1ERR_IRQHandler [WEAK] - EXPORT INTI2CWUP_IRQHandler [WEAK] - EXPORT INTI2C0_IRQHandler [WEAK] - EXPORT INTI2C0AL_IRQHandler [WEAK] - EXPORT INTI2C0BF_IRQHandler [WEAK] - EXPORT INTI2C0NA_IRQHandler [WEAK] - EXPORT INTI2C1_IRQHandler [WEAK] - EXPORT INTI2C1AL_IRQHandler [WEAK] - EXPORT INTI2C1BF_IRQHandler [WEAK] - EXPORT INTI2C1NA_IRQHandler [WEAK] - EXPORT INTI2C2_IRQHandler [WEAK] - EXPORT INTI2C2AL_IRQHandler [WEAK] - EXPORT INTI2C2BF_IRQHandler [WEAK] - EXPORT INTI2C2NA_IRQHandler [WEAK] - EXPORT INTUART0RX_IRQHandler [WEAK] - EXPORT INTUART0TX_IRQHandler [WEAK] - EXPORT INTUART0ERR_IRQHandler [WEAK] - EXPORT INTUART1RX_IRQHandler [WEAK] - EXPORT INTUART1TX_IRQHandler [WEAK] - EXPORT INTUART1ERR_IRQHandler [WEAK] - EXPORT INTUART2RX_IRQHandler [WEAK] - EXPORT INTUART2TX_IRQHandler [WEAK] - EXPORT INTUART2ERR_IRQHandler [WEAK] - EXPORT INTT32A00A_IRQHandler [WEAK] - EXPORT INTT32A00ACAP0_IRQHandler [WEAK] - EXPORT INTT32A00ACAP1_IRQHandler [WEAK] - EXPORT INTT32A00B_IRQHandler [WEAK] - EXPORT INTT32A00BCAP0_IRQHandler [WEAK] - EXPORT INTT32A00BCAP1_IRQHandler [WEAK] - EXPORT INTT32A00C_IRQHandler [WEAK] - EXPORT INTT32A00CCAP0_IRQHandler [WEAK] - EXPORT INTT32A00CCAP1_IRQHandler [WEAK] - EXPORT INTT32A01A_IRQHandler [WEAK] - EXPORT INTT32A01ACAP0_IRQHandler [WEAK] - EXPORT INTT32A01ACAP1_IRQHandler [WEAK] - EXPORT INTT32A01B_IRQHandler [WEAK] - EXPORT INTT32A01BCAP0_IRQHandler [WEAK] - EXPORT INTT32A01BCAP1_IRQHandler [WEAK] - EXPORT INTT32A01C_IRQHandler [WEAK] - EXPORT INTT32A01CCAP0_IRQHandler [WEAK] - EXPORT INTT32A01CCAP1_IRQHandler [WEAK] - EXPORT INTT32A02A_IRQHandler [WEAK] - EXPORT INTT32A02ACAP0_IRQHandler [WEAK] - EXPORT INTT32A02ACAP1_IRQHandler [WEAK] - EXPORT INTT32A02B_IRQHandler [WEAK] - EXPORT INTT32A02BCAP0_IRQHandler [WEAK] - EXPORT INTT32A02BCAP1_IRQHandler [WEAK] - EXPORT INTT32A02C_IRQHandler [WEAK] - EXPORT INTT32A02CCAP0_IRQHandler [WEAK] - EXPORT INTT32A02CCAP1_IRQHandler [WEAK] - EXPORT INTT32A03A_IRQHandler [WEAK] - EXPORT INTT32A03ACAP0_IRQHandler [WEAK] - EXPORT INTT32A03ACAP1_IRQHandler [WEAK] - EXPORT INTT32A03B_IRQHandler [WEAK] - EXPORT INTT32A03BCAP0_IRQHandler [WEAK] - EXPORT INTT32A03BCAP1_IRQHandler [WEAK] - EXPORT INTT32A03C_IRQHandler [WEAK] - EXPORT INTT32A03CCAP0_IRQHandler [WEAK] - EXPORT INTT32A03CCAP1_IRQHandler [WEAK] - EXPORT INTT32A04A_IRQHandler [WEAK] - EXPORT INTT32A04ACAP0_IRQHandler [WEAK] - EXPORT INTT32A04ACAP1_IRQHandler [WEAK] - EXPORT INTT32A04B_IRQHandler [WEAK] - EXPORT INTT32A04BCAP0_IRQHandler [WEAK] - EXPORT INTT32A04BCAP1_IRQHandler [WEAK] - EXPORT INTT32A04C_IRQHandler [WEAK] - EXPORT INTT32A04CCAP0_IRQHandler [WEAK] - EXPORT INTT32A04CCAP1_IRQHandler [WEAK] - EXPORT INTT32A05A_IRQHandler [WEAK] - EXPORT INTT32A05ACAP0_IRQHandler [WEAK] - EXPORT INTT32A05ACAP1_IRQHandler [WEAK] - EXPORT INTT32A05B_IRQHandler [WEAK] - EXPORT INTT32A05BCAP0_IRQHandler [WEAK] - EXPORT INTT32A05BCAP1_IRQHandler [WEAK] - EXPORT INTT32A05C_IRQHandler [WEAK] - EXPORT INTT32A05CCAP0_IRQHandler [WEAK] - EXPORT INTT32A05CCAP1_IRQHandler [WEAK] - EXPORT INTDMAATC_IRQHandler [WEAK] - EXPORT INTDMAAERR_IRQHandler [WEAK] - EXPORT INTRTC_IRQHandler [WEAK] - EXPORT INTRMC0_IRQHandler [WEAK] - EXPORT INTFLCRDY_IRQHandler [WEAK] - EXPORT INTFLDRDY_IRQHandler [WEAK] - -INT00_IRQHandler -INT01_IRQHandler -INT02_IRQHandler -INT03_IRQHandler -INT04_IRQHandler -INT05_IRQHandler -INT06_IRQHandler -INT07_IRQHandler -INT08_IRQHandler -INT09_IRQHandler -INT10_IRQHandler -INT11_IRQHandler -INT12_IRQHandler -INT13_IRQHandler -INT14_IRQHandler -INT15_IRQHandler -INTEMG0_IRQHandler -INTOVV0_IRQHandler -INTPMD0_IRQHandler -INTENC00_IRQHandler -INTENC01_IRQHandler -INTADAPDA_IRQHandler -INTADAPDB_IRQHandler -INTADACP0_IRQHandler -INTADACP1_IRQHandler -INTADATRG_IRQHandler -INTADASGL_IRQHandler -INTADACNT_IRQHandler -INTT0RX_IRQHandler -INTT0TX_IRQHandler -INTT0ERR_IRQHandler -INTT1RX_IRQHandler -INTT1TX_IRQHandler -INTT1ERR_IRQHandler -INTI2CWUP_IRQHandler -INTI2C0_IRQHandler -INTI2C0AL_IRQHandler -INTI2C0BF_IRQHandler -INTI2C0NA_IRQHandler -INTI2C1_IRQHandler -INTI2C1AL_IRQHandler -INTI2C1BF_IRQHandler -INTI2C1NA_IRQHandler -INTI2C2_IRQHandler -INTI2C2AL_IRQHandler -INTI2C2BF_IRQHandler -INTI2C2NA_IRQHandler -INTUART0RX_IRQHandler -INTUART0TX_IRQHandler -INTUART0ERR_IRQHandler -INTUART1RX_IRQHandler -INTUART1TX_IRQHandler -INTUART1ERR_IRQHandler -INTUART2RX_IRQHandler -INTUART2TX_IRQHandler -INTUART2ERR_IRQHandler -INTT32A00A_IRQHandler -INTT32A00ACAP0_IRQHandler -INTT32A00ACAP1_IRQHandler -INTT32A00B_IRQHandler -INTT32A00BCAP0_IRQHandler -INTT32A00BCAP1_IRQHandler -INTT32A00C_IRQHandler -INTT32A00CCAP0_IRQHandler -INTT32A00CCAP1_IRQHandler -INTT32A01A_IRQHandler -INTT32A01ACAP0_IRQHandler -INTT32A01ACAP1_IRQHandler -INTT32A01B_IRQHandler -INTT32A01BCAP0_IRQHandler -INTT32A01BCAP1_IRQHandler -INTT32A01C_IRQHandler -INTT32A01CCAP0_IRQHandler -INTT32A01CCAP1_IRQHandler -INTT32A02A_IRQHandler -INTT32A02ACAP0_IRQHandler -INTT32A02ACAP1_IRQHandler -INTT32A02B_IRQHandler -INTT32A02BCAP0_IRQHandler -INTT32A02BCAP1_IRQHandler -INTT32A02C_IRQHandler -INTT32A02CCAP0_IRQHandler -INTT32A02CCAP1_IRQHandler -INTT32A03A_IRQHandler -INTT32A03ACAP0_IRQHandler -INTT32A03ACAP1_IRQHandler -INTT32A03B_IRQHandler -INTT32A03BCAP0_IRQHandler -INTT32A03BCAP1_IRQHandler -INTT32A03C_IRQHandler -INTT32A03CCAP0_IRQHandler -INTT32A03CCAP1_IRQHandler -INTT32A04A_IRQHandler -INTT32A04ACAP0_IRQHandler -INTT32A04ACAP1_IRQHandler -INTT32A04B_IRQHandler -INTT32A04BCAP0_IRQHandler -INTT32A04BCAP1_IRQHandler -INTT32A04C_IRQHandler -INTT32A04CCAP0_IRQHandler -INTT32A04CCAP1_IRQHandler -INTT32A05A_IRQHandler -INTT32A05ACAP0_IRQHandler -INTT32A05ACAP1_IRQHandler -INTT32A05B_IRQHandler -INTT32A05BCAP0_IRQHandler -INTT32A05BCAP1_IRQHandler -INTT32A05C_IRQHandler -INTT32A05CCAP0_IRQHandler -INTT32A05CCAP1_IRQHandler -INTDMAATC_IRQHandler -INTDMAAERR_IRQHandler -INTRTC_IRQHandler -INTRMC0_IRQHandler -INTFLCRDY_IRQHandler -INTFLDRDY_IRQHandler - - B . - - ENDP - - END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/tmpm3h6fwfg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/tmpm3h6fwfg.sct deleted file mode 100644 index c6f1a37059..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/tmpm3h6fwfg.sct +++ /dev/null @@ -1,40 +0,0 @@ -#! armcc -E - -;; TMPM3H6FWFG scatter file - -;; Vector table starts at 0 -;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) -;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) -;; Initial PC == &__main (with LSB set to indicate Thumb) -;; These two values are provided by the library -;; Other vectors must be provided by the user -;; Code starts after the last possible vector -;; Data starts at 0x20000000 -;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) -;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) - -;; Compatible with ISSM model - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x20000 -{ - ER_IROM1 0x00000000 0x20000 - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(117 + 16 vect * 4 bytes) = 8_byte_aligned(0x214) = 0x218 - RW_IRAM1 (0x20000000 + 0x218) (0x4000 - 0x218 - Stack_Size) - { - .ANY (+RW, +ZI) - } - - ARM_LIB_STACK (0x20000000+0x4000) EMPTY -Stack_Size { ; stack - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/startup_TMPM3H6.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/startup_TMPM3H6.S deleted file mode 100644 index cb469a620c..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/startup_TMPM3H6.S +++ /dev/null @@ -1,483 +0,0 @@ -/** - ******************************************************************************* - * @file startup_TMPM3H6.s - * @brief CMSIS Cortex-M3 Core Device Startup File for the - * TOSHIBA 'TMPM3H6' Device Series - * @version V5.00 - * @date 2016/03/02 - *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long INT00_IRQHandler // 0: Interrupt Pin0 - .long INT01_IRQHandler // 1: Interrupt Pin1 - .long INT02_IRQHandler // 2: Interrupt Pin2 - .long INT03_IRQHandler // 3: Interrupt Pin3 - .long INT04_IRQHandler // 4: Interrupt Pin4 - .long INT05_IRQHandler // 5: Interrupt Pin5 - .long INT06_IRQHandler // 6: Interrupt Pin6 - .long INT07_IRQHandler // 7: Interrupt Pin7 - .long INT08_IRQHandler // 8: Interrupt Pin8 - .long INT09_IRQHandler // 9: Interrupt Pin9 - .long INT10_IRQHandler // 10: Interrupt Pin10 - .long INT11_IRQHandler // 11: Interrupt Pin11 - .long INT12_IRQHandler // 12: Interrupt Pin12 - .long INT13_IRQHandler // 13: Interrupt Pin13 - .long INT14_IRQHandler // 14: Interrupt Pin14 - .long INT15_IRQHandler // 15: Interrupt Pin15 - .long INTEMG0_IRQHandler // 16: PMD0 EMG interrupt - .long INTOVV0_IRQHandler // 17: PMD0 OVV interrupt - .long INTPMD0_IRQHandler // 18: PMD0 interrupt - .long INTENC00_IRQHandler // 19: Encoder 0 interrupt 0 - .long INTENC01_IRQHandler // 20: Encoder 0 interrupt 1 - .long INTADAPDA_IRQHandler // 21: ADC conversion triggered by PMD is finished A - .long INTADAPDB_IRQHandler // 22: ADC conversion triggered by PMD is finished B - .long INTADACP0_IRQHandler // 23: ADC conversion monitoring function interrupt A - .long INTADACP1_IRQHandler // 24: ADC conversion monitoring function interrupt B - .long INTADATRG_IRQHandler // 25: ADC conversion triggered by General purpose is finished - .long INTADASGL_IRQHandler // 26: ADC conversion triggered by Single program is finished - .long INTADACNT_IRQHandler // 27: ADC conversion triggered by Continuity program is finished - .long INTT0RX_IRQHandler // 28: TSPI/SIO reception (channel 0) - .long INTT0TX_IRQHandler // 29: TSPI/SIO transmit (channel 0) - .long INTT0ERR_IRQHandler // 30: TSPI/SIO error (channel 0) - .long INTT1RX_IRQHandler // 31: TSPI/SIO reception (channel 1) - .long INTT1TX_IRQHandler // 32: TSPI/SIO transmit (channel 1) - .long INTT1ERR_IRQHandler // 33: TSPI/SIO error (channel 1) - .long INTI2CWUP_IRQHandler // 34: Serial bus interface (WakeUp) interrupt (channel 0) - .long INTI2C0_IRQHandler // 35: I2C0 transmission and reception interrupt - .long INTI2C0AL_IRQHandler // 36: I2C0 arbitration lost interrupt - .long INTI2C0BF_IRQHandler // 37: I2C0 bus free interrupt - .long INTI2C0NA_IRQHandler // 38: I2C0 no ack interrupt - .long INTI2C1_IRQHandler // 39: I2C1 transmission and reception interrupt - .long INTI2C1AL_IRQHandler // 40: I2C1 arbitration lost interrupt - .long INTI2C1BF_IRQHandler // 41: I2C1 bus free interrupt - .long INTI2C1NA_IRQHandler // 42: I2C1 no ack interrupt - .long INTI2C2_IRQHandler // 43: I2C2 transmission and reception interrupt - .long INTI2C2AL_IRQHandler // 44: I2C2 arbitration lost interrupt - .long INTI2C2BF_IRQHandler // 45: I2C2 bus free interrupt - .long INTI2C2NA_IRQHandler // 46: I2C2 no ack interrupt - .long INTUART0RX_IRQHandler // 47: UART reception (channel 0) - .long INTUART0TX_IRQHandler // 48: UART transmit (channel 0) - .long INTUART0ERR_IRQHandler // 49: UART error (channel 0) - .long INTUART1RX_IRQHandler // 50: UART reception (channel 1) - .long INTUART1TX_IRQHandler // 51: UART transmit (channel 1) - .long INTUART1ERR_IRQHandler // 52: UART error (channel 1) - .long INTUART2RX_IRQHandler // 53: UART reception (channel 2) - .long INTUART2TX_IRQHandler // 54: UART transmit (channel 2) - .long INTUART2ERR_IRQHandler // 55: UART error (channel 2) - .long INTT32A00A_IRQHandler // 56: 32bit T32A0A compare match detection 0 / Over flow / under flow - .long INTT32A00ACAP0_IRQHandler // 57: 32bit T32A0A input capture 0 - .long INTT32A00ACAP1_IRQHandler // 58: 32bit T32A0A input capture 1 - .long INTT32A00B_IRQHandler // 59: 32bit T32A0B compare match detection 0 / Over flow / under flow - .long INTT32A00BCAP0_IRQHandler // 60: 32bit T32A0B input capture 0 - .long INTT32A00BCAP1_IRQHandler // 61: 32bit T32A0B input capture 1 - .long INTT32A00C_IRQHandler // 62: 32bit T32A0C compare match detection 0 / Over flow / under flow - .long INTT32A00CCAP0_IRQHandler // 63: 32bit T32A0C input capture 0 - .long INTT32A00CCAP1_IRQHandler // 64: 32bit T32A0C input capture 1 - .long INTT32A01A_IRQHandler // 65: 32bit T32A1A compare match detection 0 / Over flow / under flow - .long INTT32A01ACAP0_IRQHandler // 66: 32bit T32A1A input capture 0 - .long INTT32A01ACAP1_IRQHandler // 67: 32bit T32A1A input capture 1 - .long INTT32A01B_IRQHandler // 68: 32bit T32A1B compare match detection 0 / Over flow / under flow - .long INTT32A01BCAP0_IRQHandler // 69: 32bit T32A1B input capture 0 - .long INTT32A01BCAP1_IRQHandler // 70: 32bit T32A1B input capture 1 - .long INTT32A01C_IRQHandler // 71: 32bit T32A1C compare match detection 0 / Over flow / under flow - .long INTT32A01CCAP0_IRQHandler // 72: 32bit T32A1C input capture 0 - .long INTT32A01CCAP1_IRQHandler // 73: 32bit T32A1C input capture 1 - .long INTT32A02A_IRQHandler // 74: 32bit T32A2A compare match detection 0 / Over flow / under flow - .long INTT32A02ACAP0_IRQHandler // 75: 32bit T32A2A input capture 0 - .long INTT32A02ACAP1_IRQHandler // 76: 32bit T32A2A input capture 1 - .long INTT32A02B_IRQHandler // 77: 32bit T32A2B compare match detection 0 / Over flow / under flow - .long INTT32A02BCAP0_IRQHandler // 78: 32bit T32A2B input capture 0 - .long INTT32A02BCAP1_IRQHandler // 79: 32bit T32A2B input capture 1 - .long INTT32A02C_IRQHandler // 80: 32bit T32A2C compare match detection 0 / Over flow / under flow - .long INTT32A02CCAP0_IRQHandler // 81: 32bit T32A2C input capture 0 - .long INTT32A02CCAP1_IRQHandler // 82: 32bit T32A2C input capture 1 - .long INTT32A03A_IRQHandler // 83: 32bit T32A3A compare match detection 0 / Over flow / under flow - .long INTT32A03ACAP0_IRQHandler // 84: 32bit T32A3A input capture 0 - .long INTT32A03ACAP1_IRQHandler // 85: 32bit T32A3A input capture 1 - .long INTT32A03B_IRQHandler // 86: 32bit T32A3B compare match detection 0 / Over flow / under flow - .long INTT32A03BCAP0_IRQHandler // 87: 32bit T32A3B input capture 0 - .long INTT32A03BCAP1_IRQHandler // 88: 32bit T32A3B input capture 1 - .long INTT32A03C_IRQHandler // 89: 32bit T32A3C compare match detection 0 / Over flow / under flow - .long INTT32A03CCAP0_IRQHandler // 90: 32bit T32A3C input capture 0 - .long INTT32A03CCAP1_IRQHandler // 91: 32bit T32A3C input capture 1 - .long INTT32A04A_IRQHandler // 92: 32bit T32A4A compare match detection 0 / Over flow / under flow - .long INTT32A04ACAP0_IRQHandler // 93: 32bit T32A4A input capture 0 - .long INTT32A04ACAP1_IRQHandler // 94: 32bit T32A4A input capture 1 - .long INTT32A04B_IRQHandler // 95: 32bit T32A4B compare match detection 0 / Over flow / under flow - .long INTT32A04BCAP0_IRQHandler // 96: 32bit T32A4B input capture 0 - .long INTT32A04BCAP1_IRQHandler // 97: 32bit T32A4B input capture 1 - .long INTT32A04C_IRQHandler // 98: 32bit T32A4C compare match detection 0 / Over flow / under flow - .long INTT32A04CCAP0_IRQHandler // 99: 32bit T32A4C input capture 0 - .long INTT32A04CCAP1_IRQHandler // 100: 32bit T32A4C input capture 1 - .long INTT32A05A_IRQHandler // 101: 32bit T32A5A compare match detection 0 / Over flow / under flow - .long INTT32A05ACAP0_IRQHandler // 102: 32bit T32A5A input capture 0 - .long INTT32A05ACAP1_IRQHandler // 103: 32bit T32A5A input capture 1 - .long INTT32A05B_IRQHandler // 104: 32bit T32A5B compare match detection 0 / Over flow / under flow - .long INTT32A05BCAP0_IRQHandler // 105: 32bit T32A5B input capture 0 - .long INTT32A05BCAP1_IRQHandler // 106: 32bit T32A5B input capture 1 - .long INTT32A05C_IRQHandler // 107: 32bit T32A5C compare match detection 0 / Over flow / under flow - .long INTT32A05CCAP0_IRQHandler // 108: 32bit T32A5C input capture 0 - .long INTT32A05CCAP1_IRQHandler // 109: 32bit T32A5C input capture 1 - .long INTDMAATC_IRQHandler // 110: DMA end of transfer - .long INTDMAAERR_IRQHandler // 111: DMA transfer error - .long INTRTC_IRQHandler // 112: Real time clock(XHz) interrupt - .long 0 // 113: Reserved - .long INTRMC0_IRQHandler // 114: Remote control reception interrupt - .long INTFLCRDY_IRQHandler // 115: Code FLASH Ready interrupt - .long INTFLDRDY_IRQHandler // 116: Data FLASH Ready interrupt - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler INT00_IRQHandler - def_irq_handler INT01_IRQHandler - def_irq_handler INT02_IRQHandler - def_irq_handler INT03_IRQHandler - def_irq_handler INT04_IRQHandler - def_irq_handler INT05_IRQHandler - def_irq_handler INT06_IRQHandler - def_irq_handler INT07_IRQHandler - def_irq_handler INT08_IRQHandler - def_irq_handler INT09_IRQHandler - def_irq_handler INT10_IRQHandler - def_irq_handler INT11_IRQHandler - def_irq_handler INT12_IRQHandler - def_irq_handler INT13_IRQHandler - def_irq_handler INT14_IRQHandler - def_irq_handler INT15_IRQHandler - def_irq_handler INTEMG0_IRQHandler - def_irq_handler INTOVV0_IRQHandler - def_irq_handler INTPMD0_IRQHandler - def_irq_handler INTENC00_IRQHandler - def_irq_handler INTENC01_IRQHandler - def_irq_handler INTADAPDA_IRQHandler - def_irq_handler INTADAPDB_IRQHandler - def_irq_handler INTADACP0_IRQHandler - def_irq_handler INTADACP1_IRQHandler - def_irq_handler INTADATRG_IRQHandler - def_irq_handler INTADASGL_IRQHandler - def_irq_handler INTADACNT_IRQHandler - def_irq_handler INTT0RX_IRQHandler - def_irq_handler INTT0TX_IRQHandler - def_irq_handler INTT0ERR_IRQHandler - def_irq_handler INTT1RX_IRQHandler - def_irq_handler INTT1TX_IRQHandler - def_irq_handler INTT1ERR_IRQHandler - def_irq_handler INTI2CWUP_IRQHandler - def_irq_handler INTI2C0_IRQHandler - def_irq_handler INTI2C0AL_IRQHandler - def_irq_handler INTI2C0BF_IRQHandler - def_irq_handler INTI2C0NA_IRQHandler - def_irq_handler INTI2C1_IRQHandler - def_irq_handler INTI2C1AL_IRQHandler - def_irq_handler INTI2C1BF_IRQHandler - def_irq_handler INTI2C1NA_IRQHandler - def_irq_handler INTI2C2_IRQHandler - def_irq_handler INTI2C2AL_IRQHandler - def_irq_handler INTI2C2BF_IRQHandler - def_irq_handler INTI2C2NA_IRQHandler - def_irq_handler INTUART0RX_IRQHandler - def_irq_handler INTUART0TX_IRQHandler - def_irq_handler INTUART0ERR_IRQHandler - def_irq_handler INTUART1RX_IRQHandler - def_irq_handler INTUART1TX_IRQHandler - def_irq_handler INTUART1ERR_IRQHandler - def_irq_handler INTUART2RX_IRQHandler - def_irq_handler INTUART2TX_IRQHandler - def_irq_handler INTUART2ERR_IRQHandler - def_irq_handler INTT32A00A_IRQHandler - def_irq_handler INTT32A00ACAP0_IRQHandler - def_irq_handler INTT32A00ACAP1_IRQHandler - def_irq_handler INTT32A00B_IRQHandler - def_irq_handler INTT32A00BCAP0_IRQHandler - def_irq_handler INTT32A00BCAP1_IRQHandler - def_irq_handler INTT32A00C_IRQHandler - def_irq_handler INTT32A00CCAP0_IRQHandler - def_irq_handler INTT32A00CCAP1_IRQHandler - def_irq_handler INTT32A01A_IRQHandler - def_irq_handler INTT32A01ACAP0_IRQHandler - def_irq_handler INTT32A01ACAP1_IRQHandler - def_irq_handler INTT32A01B_IRQHandler - def_irq_handler INTT32A01BCAP0_IRQHandler - def_irq_handler INTT32A01BCAP1_IRQHandler - def_irq_handler INTT32A01C_IRQHandler - def_irq_handler INTT32A01CCAP0_IRQHandler - def_irq_handler INTT32A01CCAP1_IRQHandler - def_irq_handler INTT32A02A_IRQHandler - def_irq_handler INTT32A02ACAP0_IRQHandler - def_irq_handler INTT32A02ACAP1_IRQHandler - def_irq_handler INTT32A02B_IRQHandler - def_irq_handler INTT32A02BCAP0_IRQHandler - def_irq_handler INTT32A02BCAP1_IRQHandler - def_irq_handler INTT32A02C_IRQHandler - def_irq_handler INTT32A02CCAP0_IRQHandler - def_irq_handler INTT32A02CCAP1_IRQHandler - def_irq_handler INTT32A03A_IRQHandler - def_irq_handler INTT32A03ACAP0_IRQHandler - def_irq_handler INTT32A03ACAP1_IRQHandler - def_irq_handler INTT32A03B_IRQHandler - def_irq_handler INTT32A03BCAP0_IRQHandler - def_irq_handler INTT32A03BCAP1_IRQHandler - def_irq_handler INTT32A03C_IRQHandler - def_irq_handler INTT32A03CCAP0_IRQHandler - def_irq_handler INTT32A03CCAP1_IRQHandler - def_irq_handler INTT32A04A_IRQHandler - def_irq_handler INTT32A04ACAP0_IRQHandler - def_irq_handler INTT32A04ACAP1_IRQHandler - def_irq_handler INTT32A04B_IRQHandler - def_irq_handler INTT32A04BCAP0_IRQHandler - def_irq_handler INTT32A04BCAP1_IRQHandler - def_irq_handler INTT32A04C_IRQHandler - def_irq_handler INTT32A04CCAP0_IRQHandler - def_irq_handler INTT32A04CCAP1_IRQHandler - def_irq_handler INTT32A05A_IRQHandler - def_irq_handler INTT32A05ACAP0_IRQHandler - def_irq_handler INTT32A05ACAP1_IRQHandler - def_irq_handler INTT32A05B_IRQHandler - def_irq_handler INTT32A05BCAP0_IRQHandler - def_irq_handler INTT32A05BCAP1_IRQHandler - def_irq_handler INTT32A05C_IRQHandler - def_irq_handler INTT32A05CCAP0_IRQHandler - def_irq_handler INTT32A05CCAP1_IRQHandler - def_irq_handler INTDMAATC_IRQHandler - def_irq_handler INTDMAAERR_IRQHandler - def_irq_handler INTRTC_IRQHandler - def_irq_handler INTRMC0_IRQHandler - def_irq_handler INTFLCRDY_IRQHandler - def_irq_handler INTFLDRDY_IRQHandler - - .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld deleted file mode 100644 index 1ec6c93f72..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld +++ /dev/null @@ -1,169 +0,0 @@ -/* Linker script for Toshiba TMPM3H6 */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K - /* 8_byte_aligned(117 + 16 vect * 4 bytes) = 8_byte_aligned(0x214) = 0x218 */ - RAM (rwx) : ORIGIN = (0x20000000 + 0x218), LENGTH = (16K - 0x218) -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/startup_TMPM3H6.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/startup_TMPM3H6.S deleted file mode 100644 index 61120ca6af..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/startup_TMPM3H6.S +++ /dev/null @@ -1,808 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3H6.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3H6' Device Series -; * @version V1.0.0.0 -; * $Date:: #$ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin0 - DCD INT01_IRQHandler ; 1: Interrupt Pin1 - DCD INT02_IRQHandler ; 2: Interrupt Pin2 - DCD INT03_IRQHandler ; 3: Interrupt Pin3 - DCD INT04_IRQHandler ; 4: Interrupt Pin4 - DCD INT05_IRQHandler ; 5: Interrupt Pin5 - DCD INT06_IRQHandler ; 6: Interrupt Pin6 - DCD INT07_IRQHandler ; 7: Interrupt Pin7 - DCD INT08_IRQHandler ; 8: Interrupt Pin8 - DCD INT09_IRQHandler ; 9: Interrupt Pin9 - DCD INT10_IRQHandler ; 10: Interrupt Pin10 - DCD INT11_IRQHandler ; 11: Interrupt Pin11 - DCD INT12_IRQHandler ; 12: Interrupt Pin12 - DCD INT13_IRQHandler ; 13: Interrupt Pin13 - DCD INT14_IRQHandler ; 14: Interrupt Pin14 - DCD INT15_IRQHandler ; 15: Interrupt Pin15 - DCD INTEMG0_IRQHandler ; 16: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 17: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 18: PMD0 interrupt - DCD INTENC00_IRQHandler ; 19: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 20: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 21: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 22: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 23: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 24: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 25: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 26: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 27: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 28: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 29: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 30: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 31: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 32: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 33: TSPI/SIO error (channel 1) - DCD INTI2CWUP_IRQHandler ; 34: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 35: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 36: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 37: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 38: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 39: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 40: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 41: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 42: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 43: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 44: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 45: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 46: I2C2 no ack interrupt - DCD INTUART0RX_IRQHandler ; 47: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 48: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 49: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 50: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 51: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 52: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 53: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 54: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 55: UART error (channel 2) - DCD INTT32A00A_IRQHandler ; 56: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 57: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 58: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 59: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 60: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 61: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 62: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 63: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 64: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 65: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 66: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 67: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 68: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 69: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 70: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 71: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 72: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 73: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 74: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 75: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 76: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 77: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 78: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 79: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 80: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 81: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 82: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 83: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 84: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 85: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 86: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 87: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 88: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 89: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 90: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 91: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 92: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 93: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 94: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 95: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 96: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 97: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 98: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 99: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 100: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 101: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 102: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 103: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 104: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 105: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 106: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 107: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 108: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 109: 32bit T32A05C input capture 1 - DCD INTDMAATC_IRQHandler ; 110: DMA end of transfer - DCD INTDMAAERR_IRQHandler ; 111: DMA transfer error - DCD INTRTC_IRQHandler ; 112: Real time clock(XHz) interrupt - DCD 0 ; 113: Reserved - DCD INTRMC0_IRQHandler ; 114: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 115: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 116: Data FLASH Ready interrupt - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT00_IRQHandler - B INT00_IRQHandler - - PUBWEAK INT01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT01_IRQHandler - B INT01_IRQHandler - - PUBWEAK INT02_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT02_IRQHandler - B INT02_IRQHandler - - PUBWEAK INT03_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT03_IRQHandler - B INT03_IRQHandler - - PUBWEAK INT04_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT04_IRQHandler - B INT04_IRQHandler - - PUBWEAK INT05_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT05_IRQHandler - B INT05_IRQHandler - - PUBWEAK INT06_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT06_IRQHandler - B INT06_IRQHandler - - PUBWEAK INT07_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT07_IRQHandler - B INT07_IRQHandler - - PUBWEAK INT08_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT08_IRQHandler - B INT08_IRQHandler - - PUBWEAK INT09_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT09_IRQHandler - B INT09_IRQHandler - - PUBWEAK INT10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT10_IRQHandler - B INT10_IRQHandler - - PUBWEAK INT11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT11_IRQHandler - B INT11_IRQHandler - - PUBWEAK INT12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT12_IRQHandler - B INT12_IRQHandler - - PUBWEAK INT13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT13_IRQHandler - B INT13_IRQHandler - - PUBWEAK INT14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT14_IRQHandler - B INT14_IRQHandler - - PUBWEAK INT15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT15_IRQHandler - B INT15_IRQHandler - - PUBWEAK INTEMG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTEMG0_IRQHandler - B INTEMG0_IRQHandler - - PUBWEAK INTOVV0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTOVV0_IRQHandler - B INTOVV0_IRQHandler - - PUBWEAK INTPMD0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPMD0_IRQHandler - B INTPMD0_IRQHandler - - PUBWEAK INTENC00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC00_IRQHandler - B INTENC00_IRQHandler - - PUBWEAK INTENC01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC01_IRQHandler - B INTENC01_IRQHandler - - PUBWEAK INTADAPDA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDA_IRQHandler - B INTADAPDA_IRQHandler - - PUBWEAK INTADAPDB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDB_IRQHandler - B INTADAPDB_IRQHandler - - PUBWEAK INTADACP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP0_IRQHandler - B INTADACP0_IRQHandler - - PUBWEAK INTADACP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP1_IRQHandler - B INTADACP1_IRQHandler - - PUBWEAK INTADATRG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADATRG_IRQHandler - B INTADATRG_IRQHandler - - PUBWEAK INTADASGL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADASGL_IRQHandler - B INTADASGL_IRQHandler - - PUBWEAK INTADACNT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACNT_IRQHandler - B INTADACNT_IRQHandler - - PUBWEAK INTT0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0RX_IRQHandler - B INTT0RX_IRQHandler - - PUBWEAK INTT0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0TX_IRQHandler - B INTT0TX_IRQHandler - - PUBWEAK INTT0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0ERR_IRQHandler - B INTT0ERR_IRQHandler - - PUBWEAK INTT1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1RX_IRQHandler - B INTT1RX_IRQHandler - - PUBWEAK INTT1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1TX_IRQHandler - B INTT1TX_IRQHandler - - PUBWEAK INTT1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1ERR_IRQHandler - B INTT1ERR_IRQHandler - - PUBWEAK INTI2CWUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2CWUP_IRQHandler - B INTI2CWUP_IRQHandler - - PUBWEAK INTI2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0_IRQHandler - B INTI2C0_IRQHandler - - PUBWEAK INTI2C0AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0AL_IRQHandler - B INTI2C0AL_IRQHandler - - PUBWEAK INTI2C0BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0BF_IRQHandler - B INTI2C0BF_IRQHandler - - PUBWEAK INTI2C0NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0NA_IRQHandler - B INTI2C0NA_IRQHandler - - PUBWEAK INTI2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1_IRQHandler - B INTI2C1_IRQHandler - - PUBWEAK INTI2C1AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1AL_IRQHandler - B INTI2C1AL_IRQHandler - - PUBWEAK INTI2C1BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1BF_IRQHandler - B INTI2C1BF_IRQHandler - - PUBWEAK INTI2C1NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1NA_IRQHandler - B INTI2C1NA_IRQHandler - - PUBWEAK INTI2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2_IRQHandler - B INTI2C2_IRQHandler - - PUBWEAK INTI2C2AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2AL_IRQHandler - B INTI2C2AL_IRQHandler - - PUBWEAK INTI2C2BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2BF_IRQHandler - B INTI2C2BF_IRQHandler - - PUBWEAK INTI2C2NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2NA_IRQHandler - B INTI2C2NA_IRQHandler - - PUBWEAK INTUART0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0RX_IRQHandler - B INTUART0RX_IRQHandler - - PUBWEAK INTUART0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0TX_IRQHandler - B INTUART0TX_IRQHandler - - PUBWEAK INTUART0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0ERR_IRQHandler - B INTUART0ERR_IRQHandler - - PUBWEAK INTUART1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1RX_IRQHandler - B INTUART1RX_IRQHandler - - PUBWEAK INTUART1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1TX_IRQHandler - B INTUART1TX_IRQHandler - - PUBWEAK INTUART1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1ERR_IRQHandler - B INTUART1ERR_IRQHandler - - PUBWEAK INTUART2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2RX_IRQHandler - B INTUART2RX_IRQHandler - - PUBWEAK INTUART2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2TX_IRQHandler - B INTUART2TX_IRQHandler - - PUBWEAK INTUART2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2ERR_IRQHandler - B INTUART2ERR_IRQHandler - - PUBWEAK INTT32A00A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00A_IRQHandler - B INTT32A00A_IRQHandler - - PUBWEAK INTT32A00ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP0_IRQHandler - B INTT32A00ACAP0_IRQHandler - - PUBWEAK INTT32A00ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP1_IRQHandler - B INTT32A00ACAP1_IRQHandler - - PUBWEAK INTT32A00B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00B_IRQHandler - B INTT32A00B_IRQHandler - - PUBWEAK INTT32A00BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP0_IRQHandler - B INTT32A00BCAP0_IRQHandler - - PUBWEAK INTT32A00BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP1_IRQHandler - B INTT32A00BCAP1_IRQHandler - - PUBWEAK INTT32A00C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00C_IRQHandler - B INTT32A00C_IRQHandler - - PUBWEAK INTT32A00CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP0_IRQHandler - B INTT32A00CCAP0_IRQHandler - - PUBWEAK INTT32A00CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP1_IRQHandler - B INTT32A00CCAP1_IRQHandler - - PUBWEAK INTT32A01A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01A_IRQHandler - B INTT32A01A_IRQHandler - - PUBWEAK INTT32A01ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP0_IRQHandler - B INTT32A01ACAP0_IRQHandler - - PUBWEAK INTT32A01ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP1_IRQHandler - B INTT32A01ACAP1_IRQHandler - - PUBWEAK INTT32A01B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01B_IRQHandler - B INTT32A01B_IRQHandler - - PUBWEAK INTT32A01BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP0_IRQHandler - B INTT32A01BCAP0_IRQHandler - - PUBWEAK INTT32A01BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP1_IRQHandler - B INTT32A01BCAP1_IRQHandler - - PUBWEAK INTT32A01C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01C_IRQHandler - B INTT32A01C_IRQHandler - - PUBWEAK INTT32A01CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP0_IRQHandler - B INTT32A01CCAP0_IRQHandler - - PUBWEAK INTT32A01CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP1_IRQHandler - B INTT32A01CCAP1_IRQHandler - - PUBWEAK INTT32A02A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02A_IRQHandler - B INTT32A02A_IRQHandler - - PUBWEAK INTT32A02ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP0_IRQHandler - B INTT32A02ACAP0_IRQHandler - - PUBWEAK INTT32A02ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP1_IRQHandler - B INTT32A02ACAP1_IRQHandler - - PUBWEAK INTT32A02B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02B_IRQHandler - B INTT32A02B_IRQHandler - - PUBWEAK INTT32A02BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP0_IRQHandler - B INTT32A02BCAP0_IRQHandler - - PUBWEAK INTT32A02BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP1_IRQHandler - B INTT32A02BCAP1_IRQHandler - - PUBWEAK INTT32A02C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02C_IRQHandler - B INTT32A02C_IRQHandler - - PUBWEAK INTT32A02CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP0_IRQHandler - B INTT32A02CCAP0_IRQHandler - - PUBWEAK INTT32A02CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP1_IRQHandler - B INTT32A02CCAP1_IRQHandler - - PUBWEAK INTT32A03A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03A_IRQHandler - B INTT32A03A_IRQHandler - - PUBWEAK INTT32A03ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP0_IRQHandler - B INTT32A03ACAP0_IRQHandler - - PUBWEAK INTT32A03ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP1_IRQHandler - B INTT32A03ACAP1_IRQHandler - - PUBWEAK INTT32A03B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03B_IRQHandler - B INTT32A03B_IRQHandler - - PUBWEAK INTT32A03BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP0_IRQHandler - B INTT32A03BCAP0_IRQHandler - - PUBWEAK INTT32A03BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP1_IRQHandler - B INTT32A03BCAP1_IRQHandler - - PUBWEAK INTT32A03C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03C_IRQHandler - B INTT32A03C_IRQHandler - - PUBWEAK INTT32A03CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP0_IRQHandler - B INTT32A03CCAP0_IRQHandler - - PUBWEAK INTT32A03CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP1_IRQHandler - B INTT32A03CCAP1_IRQHandler - - PUBWEAK INTT32A04A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04A_IRQHandler - B INTT32A04A_IRQHandler - - PUBWEAK INTT32A04ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP0_IRQHandler - B INTT32A04ACAP0_IRQHandler - - PUBWEAK INTT32A04ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP1_IRQHandler - B INTT32A04ACAP1_IRQHandler - - PUBWEAK INTT32A04B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04B_IRQHandler - B INTT32A04B_IRQHandler - - PUBWEAK INTT32A04BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP0_IRQHandler - B INTT32A04BCAP0_IRQHandler - - PUBWEAK INTT32A04BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP1_IRQHandler - B INTT32A04BCAP1_IRQHandler - - PUBWEAK INTT32A04C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04C_IRQHandler - B INTT32A04C_IRQHandler - - PUBWEAK INTT32A04CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP0_IRQHandler - B INTT32A04CCAP0_IRQHandler - - PUBWEAK INTT32A04CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP1_IRQHandler - B INTT32A04CCAP1_IRQHandler - - PUBWEAK INTT32A05A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05A_IRQHandler - B INTT32A05A_IRQHandler - - PUBWEAK INTT32A05ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP0_IRQHandler - B INTT32A05ACAP0_IRQHandler - - PUBWEAK INTT32A05ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP1_IRQHandler - B INTT32A05ACAP1_IRQHandler - - PUBWEAK INTT32A05B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05B_IRQHandler - B INTT32A05B_IRQHandler - - PUBWEAK INTT32A05BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP0_IRQHandler - B INTT32A05BCAP0_IRQHandler - - PUBWEAK INTT32A05BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP1_IRQHandler - B INTT32A05BCAP1_IRQHandler - - PUBWEAK INTT32A05C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05C_IRQHandler - B INTT32A05C_IRQHandler - - PUBWEAK INTT32A05CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP0_IRQHandler - B INTT32A05CCAP0_IRQHandler - - PUBWEAK INTT32A05CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP1_IRQHandler - B INTT32A05CCAP1_IRQHandler - - PUBWEAK INTDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAATC_IRQHandler - B INTDMAATC_IRQHandler - - PUBWEAK INTDMAAERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAAERR_IRQHandler - B INTDMAAERR_IRQHandler - - PUBWEAK INTRTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRTC_IRQHandler - B INTRTC_IRQHandler - - PUBWEAK INTRMC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC0_IRQHandler - B INTRMC0_IRQHandler - - PUBWEAK INTFLCRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY_IRQHandler - B INTFLCRDY_IRQHandler - - PUBWEAK INTFLDRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLDRDY_IRQHandler - B INTFLDRDY_IRQHandler - - END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf deleted file mode 100644 index 246835bf9b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf +++ /dev/null @@ -1,43 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000218; /* 8_byte_aligned(117 + 16 vect * 4 bytes) */ -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0xC00; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol __BRAM_start__ = 0x20004000; -define symbol __BRAM_end__ = 0x200047FF; -define symbol __DFLASH_start__ = 0x30000000; -define symbol __DFLASH_end__ = 0x30007FFF; -define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ]; -define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in BRAM_region { section .backup_ram }; -place in DFLASH_region { section .data_flash }; diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis.h deleted file mode 100644 index 5a2ec44300..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS for TMPM3H6 - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in TMPM3Hx specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "TMPM3H6.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis_nvic.h deleted file mode 100644 index c112a33ca2..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis_nvic.h +++ /dev/null @@ -1,15 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for TMPM3H6 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_FLASH_VECTOR_ADDRESS 0x00000000 -#define NVIC_USER_IRQ_NUMBER 117 -#define NVIC_NUM_VECTORS (16 + 117) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.c deleted file mode 100644 index 8933ce3738..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.c +++ /dev/null @@ -1,311 +0,0 @@ -/** - ******************************************************************************* - * @file system_TMPM3Hx.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the - * TOSHIBA 'TMPM3Hx' Device Series - * @version V1.0.7.0 - * $Date:: 2017-11-06 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#include "TMPM3H6.h" - -/*-------- <<< Start of configuration section >>> ----------------------------*/ - -/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ -#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ -#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ -#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ - -/* Clock Generator (CG) Configuration */ -#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ -#define SYSCR_Val (0x00000000UL) - -#define STBYCR_Val (0x00000000UL) - -#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */ -#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */ -#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */ -#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */ - -#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) -#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) -#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) - -#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) -#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) - -#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001) - -#if (CLOCK_SETUP) - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) - #define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL -#else - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000) - #define PLL0SEL_Ready CG_10M_MUL_4_FPLL -#endif -#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) -#define PLL0SEL_MASK (0xFFFFFF00UL) - -/*-------- <<< End of configuration section >>> ------------------------------*/ - -/*-------- DEFINES -----------------------------------------------------------*/ -/* Define clocks */ -#define EOSC_6M (6000000UL) -#define EOSC_8M (8000000UL) -#define EOSC_10M (10000000UL) -#define EOSC_12M (12000000UL) -#define IOSC_10M (10000000UL) -#define EXTALH EOSC_12M /* External high-speed oscillator freq */ -#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ -#define EOSC_6M_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ -#define EOSC_8M_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ -#define EOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ -#define EOSC_12M_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ -#define IOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ - -/* Configure Warm-up time */ -#define HZ_1M (1000000UL) -#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ -#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ -#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ -#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = warm-up time(us) * EXTALH / 16 */ -#if (CLOCK_SETUP) - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#else - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#endif -/* Determine core clock frequency according to settings */ -/* System clock is high-speed clock*/ -#if (CLOCK_SETUP) - #define CORE_TALH (EXTALH) -#else - #define CORE_TALH (IXTALH) -#endif - -#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ - #if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL)) - #define __CORE_CLK EOSC_6M_PLLON /* output clock is 39.98MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 6MHz */ - #elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL)) - #define __CORE_CLK EOSC_8M_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 8MHz */ - #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK EOSC_10M_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) - #define __CORE_CLK EOSC_12M_PLLON /* output clock is 39.94MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 12MHz */ - #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK IOSC_10M_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #else /* input clock not known */ - #define __CORE_CLK (0U) - #error "Core Oscillator Frequency invalid!" - #endif /* End switch input clock */ -#else - #define __CORE_CLK (CORE_TALH) -#endif - -#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ - #define __CORE_SYS (__CORE_CLK) -#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ - #define __CORE_SYS (__CORE_CLK / 2U) -#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ - #define __CORE_SYS (__CORE_CLK / 4U ) -#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ - #define __CORE_SYS (__CORE_CLK / 8U) -#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ - #define __CORE_SYS (__CORE_CLK / 16U) -#else /* Gear -> reserved */ - #define __CORE_SYS (0U) -#endif - - -/* Clock Variable definitions */ -uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Update SystemCoreClock according register values. - */ -void SystemCoreClockUpdate(void) -{ /* Get Core Clock Frequency */ - uint32_t CoreClock = 0U; - uint32_t CoreClockInput = 0U; - uint32_t regval = 0U; - uint32_t oscsel = 0U; - uint32_t pll0sel = 0U; - uint32_t pll0on = 0U; - /* Determine clock frequency according to clock register values */ - /* System clock is high-speed clock */ - regval = TSB_CG->OSCCR; - oscsel = regval & CG_OSCCR_OSCSEL_SET; - if (oscsel) { /* If system clock is External high-speed oscillator freq */ - CoreClock = EXTALH; - } else { /* If system clock is Internal high-speed oscillator freq */ - CoreClock = IXTALH; - } - regval = TSB_CG->PLL0SEL; - pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; - pll0on = regval & CG_PLL0SEL_PLL0ON_SET; - if (pll0sel && pll0on) { /* If PLL enabled */ - if (CoreClock == EOSC_6M) { /* If input is 6MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) { - CoreClockInput = EOSC_6M_PLLON; /* output clock is 39.98MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) { - CoreClockInput = EOSC_8M_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = EOSC_10M_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) { - CoreClockInput = EOSC_12M_PLLON; /* output clock is 39.94MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = IOSC_10M_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else { - CoreClockInput = 0U; - } - } else { /* If PLL not used */ - CoreClockInput = CoreClock; - } - - switch (TSB_CG->SYSCR & 7U) { - case 0U: /* Gear -> fc */ - SystemCoreClock = CoreClockInput; - break; - case 1U: /* Gear -> fc/2 */ - SystemCoreClock = CoreClockInput / 2U; - break; - case 2U: /* Gear -> fc/4 */ - SystemCoreClock = CoreClockInput / 4U; - break; - case 3U: /* Gear -> fc/8 */ - if (CoreClockInput >= EOSC_8M) { - SystemCoreClock = CoreClockInput / 8U; - } else { - SystemCoreClock = 0U; - } - break; - case 4U: /* Gear -> fc/16 */ - if (CoreClockInput > EOSC_12M) { - SystemCoreClock = CoreClockInput / 16U; - } else { - SystemCoreClock = 0U; - } - break; - case 5U: - case 6U: - case 7U: - SystemCoreClock = 0U; - break; - default: - SystemCoreClock = 0U; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ -#if (SIWD_SETUP) /* Watchdog Setup */ - /* SIWD Disable */ - TSB_SIWD0->EN = SIWDEN_Val; - TSB_SIWD0->CR = SIWDCR_Val; -#else - /* SIWD Enable (Setting after a Reset) */ -#endif - -#if (CLOCK_SETUP) /* Clock(external) Setup */ - TSB_CG->SYSCR = SYSCR_Val; - - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - while (!TSB_CG_OSCCR_OSCF) { - ; - } /* Confirm CGOSCCR="1" */ - TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; -#else - /* Internal HOSC Enable (Setting after a Reset) */ -#endif - - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; - TSB_CG->PLL0SEL = PLL0SEL_Ready; - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ - TSB_CG->STBYCR = STBYCR_Val; - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Lockup */ - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; - while (!TSB_CG_PLL0SEL_PLL0ST) { - ; - } /*Confirm CGPLL0SEL = "1" */ -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.h deleted file mode 100644 index 07e40532ed..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ***************************************************************************** - * @file system_TMPM3Hx.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3Hx' Device Series - * @version V1.0.1.0 - * $Date:: 2017-06-23 13:52:12 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ***************************************************************************** - */ - -#include - -#ifndef __SYSTEM_TMPM3H6_H -#define __SYSTEM_TMPM3H6_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_api.c deleted file mode 100644 index ae51ea47b7..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_api.c +++ /dev/null @@ -1,122 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" - -extern const PinMap PinMap_GPIO_IRQ[]; - -void gpio_init(gpio_t *obj, PinName pin) -{ - // Store above pin mask, pin name into GPIO object - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - obj->mask = gpio_set(pin); - obj->port = (PortName)(pin >> 3); - TSB_CG->FSYSENA |= (1 << (obj->port)); -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -uint32_t gpio_set(PinName pin) -{ - // Check that pin is valid - MBED_ASSERT(pin != (PinName)NC); - - // Set pin function as GPIO pin - pin_function(pin, GPIO_DATA); - - // Return pin mask - return (1 << (pin & 0x07)); -} - -// Set gpio object pin direction -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - // Set direction - switch (direction) { - case PIN_INPUT: - pin_function(obj->pin, PIN_INPUT); - break; - - case PIN_OUTPUT: - pin_function(obj->pin, PIN_OUTPUT); - break; - - case PIN_INOUT: - pin_function(obj->pin, PIN_INOUT); - break; - - default: - error("Invalid direction\n"); - break; - } -} - -// Write gpio object pin data -void gpio_write(gpio_t *obj, int value) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base = 0; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - if (value == GPIO_PIN_SET) { - BITBAND_PORT_SET(base, bit); - } else if (value == GPIO_PIN_RESET) { - BITBAND_PORT_CLR(base, bit); - } else { - error("Invalid value\n"); - } -} - -// Read gpio object pin data -int gpio_read(gpio_t *obj) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base = 0; - uint32_t val = 0; - int BitValue = 0; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - BITBAND_PORT_READ(val, base, bit); - - if (val == GPIO_PIN_RESET) { - BitValue = GPIO_PIN_RESET; - } else { - BitValue = GPIO_PIN_SET; - } - - return (BitValue); -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_include.h deleted file mode 100644 index ca6c8cd2b8..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_include.h +++ /dev/null @@ -1,174 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __GPIO_INCLUDE_H -#define __GPIO_INCLUDE_H - -#include -#include -#include "TMPM3H6.h" -#include "objects.h" -#include "serial_api.h" -#include "txz_driver_def.h" - -enum BitMode { - GPIO_PIN_RESET = 0, - GPIO_PIN_SET, -}; - -enum PortFunction { - GPIO_Mode_DATA = 0x0, // 0x0: PxDATA - GPIO_Mode_CR = 0x04, // 0x4: PxCR - GPIO_Mode_FR1 = 0x08, // 0x8: PxFR1 - GPIO_Mode_FR2 = 0x0C, // 0xC: PxFR2 - GPIO_Mode_FR3 = 0x10, // 0x10: PxFR3 - GPIO_Mode_FR4 = 0x14, // 0x14: PxFR4 - GPIO_Mode_FR5 = 0x18, // 0x18: PxFR5 - GPIO_Mode_FR6 = 0x1C, // 0x1C: PxFR6 - GPIO_Mode_OD = 0x28, // 0x28: PxOD - GPIO_Mode_PUP = 0x2C, // 0x2C: PxPUP - GPIO_Mode_PDN = 0x30, // 0x30: PxPDN - GPIO_Mode_IE = 0x38 // 0x38: PxIE -}; - -// GPIO -#define PORT_BASE (0x400C0000UL) // Port Register Base Adress -#define BITBAND_PORT_OFFSET (0x0000100UL) // Port Register Offset Value -#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) // Operational target Port Adress -#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) // Operational target Control Register Adress -#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) // Target Pin Bit set -#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) // Target Pin Bit clear -#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) // Target Pin Bit read -#define GPIO_DATA PIN_DATA(0, 2) -#define CHANNEL_NUM 16 -#define PORT_PIN_NUM 8 -#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF) -#define PIN_POS(X) ((uint32_t)(X) & 0x7) -// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) -#define PIN_FUNC(X) (((X) & 0xFFFF0000) >> 16) -#define PIN_DIR(X) ((X) & 0xFFFF) -// SPI -#define TIMEOUT 1000 -#define INITIAL_SPI_FREQ 1000000 -// I2C -#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080) -#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) -#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) -#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) -#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) -#define I2CxCR2_INIT ((uint32_t)0x00000008) -#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) -#define I2CxCR2_TRX ((uint32_t)0x00000040) -#define I2CxST_I2C ((uint32_t)0x00000001) -#define I2CxST_CLEAR ((uint32_t)0x0000000F) -#define I2CxCR1_ACK ((uint32_t)0x00000010) -#define I2CxSR_BB ((uint32_t)0x00000020) -#define I2CxSR_LRB ((uint32_t)0x00000001) -#define I2CxOP_RSTA ((uint32_t)0x00000008) -#define I2CxOP_SREN ((uint32_t)0x00000002) -#define I2CxOP_MFACK ((uint32_t)0x00000001) -#define I2CxOP_INIT ((uint32_t)0x00000084) -#define I2CxIE_CLEAR ((uint32_t)0x00000000) -#define I2CxPRS_PRCK ((uint32_t)0x0000000F) -#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) -#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) -#define I2CAR_SA_MASK ((uint32_t)0x000000FE) -#define I2CxSR_TRX ((uint32_t)0x00000040) -#define I2CxOP_SAST ((uint32_t)0x00000020) -#define I2CxIE_INTI2C ((uint32_t)0x00000001) -#define I2C_NO_DATA (0) -#define I2C_READ_ADDRESSED (1) -#define I2C_WRITE_ADDRESSED (3) -#define I2C_ACK (1) -#define I2C_TIMEOUT (100000) -// DAC -#define DAC_START ((uint32_t)0x00000001) -#define DAC_STOP ((uint32_t)0x00000000) -// ADC -#define ADC_12BIT_RANGE 0xFFF -#define ADC_SCLK_1 ((uint32_t)0x00000000) -#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) -#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) -#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) -#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) -#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) -#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) -#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) -#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) -#define ADxST_SNGF_RUN ((uint32_t)0x00000004) -#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) -#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) -#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) -// Timer & PWM -#define T32A_INT_MASK ((uint32_t)0x0000000F) -#define T32A_MODE_32 ((uint32_t)0x00000001) -#define T32A_PRSCLx_32 ((uint32_t)0x30000000) -#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) -#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) -#define T32A_COUNT_STOP ((uint32_t)0x00000004) -#define T32A_COUNT_START ((uint32_t)0x00000002) -#define T32A_RUN_ENABLE ((uint32_t)0x00000001) -#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) -#define T32A_COUNT_DONT_START ((uint32_t)0x00000000) -#define T32A_RUN_DISABLE ((uint32_t)0x00000000) -#define T32A_WBF_ENABLE ((uint32_t)0x00100000) -#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) -#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) -#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) -#define T32A_OCR_DISABLE ((uint32_t)0x00000000) -#define DEFAULT_PERIOD 0.02f // 20ms -#define DEFAULT_CLOCK_DIVISION 32 -#define MAX_COUNTER_16B 0xFFFF -// UART -#define UART_ENABLE_RX ((uint32_t)0x00000001) -#define UART_ENABLE_TX ((uint32_t)0x00000002) -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) -#define UART_PLESCALER_1 ((uint32_t)0x00000000) -#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) -#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) -#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) -#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) -#define UART_RANGE_K_MIN ((uint32_t)0x00000000) -#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) -#define UART_RANGE_N_MIN ((uint32_t)0x00000001) -#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) -#define UART_NUM 3 - -typedef struct { - uint32_t ken; // Enable/Disable Division Definition - uint32_t brk; // Division Value K - uint32_t brn; // Division Value N -} uart_boudrate_t; - -// Sleep -#define CG_STBY_MODE_IDLE 0x0 -#define CG_STBY_MODE_STOP1 0x1 -#define EXTERNEL_OSC_MASK 0xFFFFFFF9 -#define IHOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) -#define IHOSC_CFG_CLOCK ((uint64_t)(10000000)) -#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000) - -#endif // __GPIO_INCLUDE_H diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_irq_api.c deleted file mode 100644 index 631ee540dc..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_irq_api.c +++ /dev/null @@ -1,365 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "gpio_include.h" -#include "mbed_critical.h" - -const PinMap PinMap_GPIO_IRQ[] = { - {PC0, GPIO_IRQ_0, PIN_DATA(0, 0)}, - {PC1, GPIO_IRQ_1, PIN_DATA(0, 0)}, - {PC2, GPIO_IRQ_2, PIN_DATA(0, 0)}, - {PB1, GPIO_IRQ_3, PIN_DATA(0, 0)}, - {PJ4, GPIO_IRQ_4, PIN_DATA(0, 0)}, - {PK1, GPIO_IRQ_5, PIN_DATA(0, 0)}, - {PH3, GPIO_IRQ_6, PIN_DATA(0, 0)}, - {PA6, GPIO_IRQ_7, PIN_DATA(0, 0)}, - {PL3, GPIO_IRQ_8, PIN_DATA(0, 0)}, - {PM2, GPIO_IRQ_9, PIN_DATA(0, 0)}, - {PN3, GPIO_IRQ_A, PIN_DATA(0, 0)}, - {PA7, GPIO_IRQ_B, PIN_DATA(0, 0)}, - {PL4, GPIO_IRQ_C, PIN_DATA(0, 0)}, - {PK7, GPIO_IRQ_D, PIN_DATA(0, 0)}, - {PP3, GPIO_IRQ_E, PIN_DATA(0, 0)}, - {PM6, GPIO_IRQ_F, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; -static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState); -static cg_intactivestate CurrentState; -static void INT_IRQHandler(PinName pin, uint32_t index); - -// Initialize gpio IRQ pin -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - // Get gpio interrupt ID - obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - - // Disable interrupt by CPU - core_util_critical_section_enter(); - - // Calculate port and pin position - obj->port = (PortName)PIN_PORT(pin); - obj->pin = pin; - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_CLR(port_base, bit); - // Enable gpio interrupt function - pinmap_pinout(pin, PinMap_GPIO_IRQ); - - // Get GPIO irq source - switch (obj->irq_id) { - case GPIO_IRQ_0: - obj->irq_src = cg_int_src_0; - break; - case GPIO_IRQ_1: - obj->irq_src = cg_int_src_1; - break; - case GPIO_IRQ_2: - obj->irq_src = cg_int_src_2; - break; - case GPIO_IRQ_3: - obj->irq_src = cg_int_src_3; - break; - case GPIO_IRQ_4: - obj->irq_src = cg_int_src_4; - break; - case GPIO_IRQ_5: - obj->irq_src = cg_int_src_5; - break; - case GPIO_IRQ_6: - obj->irq_src = cg_int_src_6; - break; - case GPIO_IRQ_7: - obj->irq_src = cg_int_src_7; - break; - case GPIO_IRQ_8: - obj->irq_src = cg_int_src_8; - break; - case GPIO_IRQ_9: - obj->irq_src = cg_int_src_9; - break; - case GPIO_IRQ_A: - obj->irq_src = cg_int_src_a; - break; - case GPIO_IRQ_B: - obj->irq_src = cg_int_src_b; - break; - case GPIO_IRQ_C: - obj->irq_src = cg_int_src_c; - break; - case GPIO_IRQ_D: - obj->irq_src = cg_int_src_d; - break; - case GPIO_IRQ_E: - obj->irq_src = cg_int_src_e; - break; - case GPIO_IRQ_F: - obj->irq_src = cg_int_src_f; - break; - default: - break; - } - - // Save irq handler - hal_irq_handler[obj->irq_src] = handler; - - // Save irq id - channel_ids[obj->irq_src] = id; - - // Initialize interrupt event as both edges detection - obj->event = cg_int_active_state_both_edges; - CurrentState = cg_int_active_state_both_edges; - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE); - - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id); - - core_util_critical_section_exit(); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Clear gpio_irq - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Reset interrupt handler - hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; -} - -// Set interrupt event of gpio_irq object -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - //Disable GPIO interrupt on obj - gpio_irq_disable(obj); - if (enable) { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_both_edges)) { - obj->event = cg_int_active_state_both_edges; - } else { - obj->event = cg_int_active_state_rising; - } - } else if (event == IRQ_FALL) { - if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_both_edges)) { - obj->event = cg_int_active_state_both_edges; - } else { - obj->event = cg_int_active_state_falling; - } - } else { - error("Not supported event\n"); - } - } else { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_invalid)) { - obj->event = cg_int_active_state_invalid; - } else { - obj->event = cg_int_active_state_falling; - } - } else if (event == IRQ_FALL) { - if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_invalid)) { - obj->event = cg_int_active_state_invalid; - } else { - obj->event = cg_int_active_state_rising; - } - } else { - error("Not supported event\n"); - } - } - CurrentState = obj->event; - // Calculate port and pin position - bit = PIN_POS(obj->pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - - if (obj->event != cg_int_active_state_invalid ) { - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE); - BITBAND_PORT_CLR(port_base, bit); - } else { - BITBAND_PORT_SET(port_base, bit); - } - //Enable GPIO interrupt on obj - gpio_irq_enable(obj); -} - -// Enable gpio_irq object -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear and Enable gpio_irq object - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - NVIC_EnableIRQ((IRQn_Type)obj->irq_id); -} - -// Disable gpio_irq object -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable gpio_irq object - NVIC_DisableIRQ((IRQn_Type)obj->irq_id); -} - -static void INT_IRQHandler(PinName pin, uint32_t index) -{ - int port = 0; - uint8_t bit = 0; - uint32_t data = 0; - uint32_t port_base = 0; - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - // Clear interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_0 + index), CurrentState, DISABLE); - - port_base = BITBAND_PORT_BASE(port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_READ(data, port_base, bit); - - switch (data) { - // Falling edge detection - case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); - break; - // Rising edge detection - case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); - break; - default: - break; - } - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)(cg_int_src_0 + index)); - - // Enable interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_0 + index), CurrentState, ENABLE); -} - -void INT00_IRQHandler(void) -{ - INT_IRQHandler(PC0, 0); -} - -void INT01_IRQHandler(void) -{ - INT_IRQHandler(PC1, 1); -} - -void INT02_IRQHandler(void) -{ - INT_IRQHandler(PC2, 2); -} - -void INT03_IRQHandler(void) -{ - INT_IRQHandler(PB1, 3); -} - -void INT04_IRQHandler(void) -{ - INT_IRQHandler(PJ4, 4); -} - -void INT05_IRQHandler(void) -{ - INT_IRQHandler(PK1, 5); -} - -void INT06_IRQHandler(void) -{ - INT_IRQHandler(PH3, 6); -} - -void INT07_IRQHandler(void) -{ - INT_IRQHandler(PA6, 7); -} - -void INT08_IRQHandler(void) -{ - INT_IRQHandler(PL3, 8); -} - -void INT09_IRQHandler(void) -{ - INT_IRQHandler(PM2, 9); -} - -void INT10_IRQHandler(void) -{ - INT_IRQHandler(PN3, 10); -} - -void INT11_IRQHandler(void) -{ - INT_IRQHandler(PA7, 11); -} - -void INT12_IRQHandler(void) -{ - INT_IRQHandler(PL4, 12); -} - -void INT13_IRQHandler(void) -{ - INT_IRQHandler(PK7, 13); -} - -void INT14_IRQHandler(void) -{ - INT_IRQHandler(PP3, 14); -} - -void INT15_IRQHandler(void) -{ - INT_IRQHandler(PM6, 15); -} - -static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState) -{ - __IO uint8_t *p_imc; - - if (intsource < 3U) { - p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } else { - intsource -= 3; - p_imc = (__IO uint8_t *)(&TSB_IB->IMC033 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } - // Dummy read is need - { - __IO uint8_t imc = *p_imc; - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_object.h deleted file mode 100644 index ec18793a16..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_object.h +++ /dev/null @@ -1,81 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) -#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) -#define GPIO_BIT_ALL ((uint8_t)0xFF) - -typedef enum { - cg_int_src_0 = 0U, - cg_int_src_1, - cg_int_src_2, - cg_int_src_3, - cg_int_src_4, - cg_int_src_5, - cg_int_src_6, - cg_int_src_7, - cg_int_src_8, - cg_int_src_9, - cg_int_src_a, - cg_int_src_b, - cg_int_src_c, - cg_int_src_d, - cg_int_src_e, - cg_int_src_f -} cg_intsrc; - -typedef enum { - cg_int_active_state_l = 0x00U, - cg_int_active_state_h = 0x02U, - cg_int_active_state_falling = 0x04U, - cg_int_active_state_rising = 0x06U, - cg_int_active_state_both_edges = 0x08U, - cg_int_active_state_invalid = 0x0AU -} cg_intactivestate; - -typedef struct { - PinName pin; - uint32_t mask; - PortName port; -} gpio_t; - -struct gpio_irq_s { - uint32_t mask; - PortName port; - PinName pin; - uint32_t irq_id; - cg_intactivestate event; - cg_intsrc irq_src; -}; - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return (obj->pin != (PinName)NC); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/i2c_api.c deleted file mode 100644 index 66dd86332b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/i2c_api.c +++ /dev/null @@ -1,673 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" - -#if DEVICE_I2C_ASYNCH -#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) -#else -#define I2C_S(obj) (struct i2c_s *) (obj) -#endif - -static const PinMap PinMap_I2C_SDA[] = { - {PC1, I2C_0, PIN_DATA(1, 2)}, - {PA5, I2C_1, PIN_DATA(1, 2)}, - {PL1, I2C_2, PIN_DATA(3, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PC0, I2C_0, PIN_DATA(1, 2)}, - {PA4, I2C_1, PIN_DATA(1, 2)}, - {PL0, I2C_2, PIN_DATA(3, 2)}, - {NC, NC, 0} -}; - -// Clock setting structure definition -typedef struct { - uint32_t sck; - uint32_t prsck; -} I2C_clock_setting_t; - -// SCK Divider value table -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { - 20, 24, 32, 48, 80, 144, 272, 528 -}; - -I2C_clock_setting_t clk; -static uint32_t start_flag = 0; - -#if DEVICE_I2C_ASYNCH -enum { - I2C_TRANSFER_STATE_IDLE = 0U, - I2C_TRANSFER_STATE_START, - I2C_TRANSFER_STATE_WRITE, - I2C_TRANSFER_STATE_RESTART, - I2C_TRANSFER_STATE_READ, - I2C_TRANSFER_STATE_MAX -} TransferState; - -typedef struct { - IRQn_Type i2c; -} i2c_irq_t; - -static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = { - {INTI2C0_IRQn} -}; - -static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = { - {INTI2C1_IRQn} -}; - -static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = { - {INTI2C2_IRQn} -}; -#endif - -static int32_t wait_status(i2c_t *p_obj); -static void i2c_start_bit(i2c_t *obj); - -#if DEVICE_I2C_ASYNCH -static void disable_irq(uint32_t irqn); -static void clear_irq(uint32_t irqn); -static void i2c_irq_handler(i2c_t *obj); -#endif - -// Initialize the I2C peripheral. It sets the default parameters for I2C -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - struct i2c_s *obj_s = I2C_S(obj); - MBED_ASSERT(obj_s != NULL); - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)i2c_name != NC); - - switch (i2c_name) { - case I2C_0: - TSB_CG_FSYSENA_IPENA20 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - obj_s->i2c = TSB_I2C0; -#if DEVICE_I2C_ASYNCH - obj_s->irqn = (uint32_t)&I2C_CH0_IRQN_TBL; -#endif - break; - case I2C_1: - TSB_CG_FSYSENA_IPENA21 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - obj_s->i2c = TSB_I2C1; -#if DEVICE_I2C_ASYNCH - obj_s->irqn = (uint32_t)&I2C_CH1_IRQN_TBL; -#endif - break; - case I2C_2: - TSB_CG_FSYSENA_IPENA22 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; - obj_s->i2c = TSB_I2C2; -#if DEVICE_I2C_ASYNCH - obj_s->irqn = (uint32_t)&I2C_CH2_IRQN_TBL; -#endif - break; - default: - error("I2C is not available"); - break; - } -#if DEVICE_I2C_ASYNCH - obj_s->state = I2C_TRANSFER_STATE_IDLE; -#endif - - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - pin_mode(sda, PullUp); - - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pin_mode(scl, PullUp); - - i2c_reset(obj); - i2c_frequency(obj, 100000); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->IE = I2CxIE_CLEAR; -} - -// Configure the I2C frequency -void i2c_frequency(i2c_t *obj, int hz) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint64_t sck; - uint64_t tmp_sck; - uint64_t prsck; - uint64_t tmp_prsck; - uint64_t fscl; - uint64_t tmp_fscl; - uint64_t fx; - - SystemCoreClockUpdate(); - - if (hz <= 1000000) { - sck = tmp_sck = 0; - prsck = tmp_prsck = 1; - fscl = tmp_fscl = 0; - for (prsck = 1; prsck <= 32; prsck++) { - fx = ((uint64_t)SystemCoreClock / prsck); - if ((fx < 20000000U) && (fx > 6666666U)) { - for (sck = 0; sck <= 7; sck++) { - fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - tmp_sck = sck; - tmp_prsck = (prsck < 32) ? prsck : 0; - } - } - } - } - clk.sck = (uint32_t)tmp_sck; - clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0; - } - - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); -} - -int i2c_start(i2c_t *obj) -{ - start_flag = 1; // Start Condition - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t timeout = I2C_TIMEOUT; - - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - - while ((obj_s->i2c->SR & I2CxSR_BB) == I2CxSR_BB) { - if (timeout == 0) { - break; - } - timeout--; - } - - return 0; -} - -void i2c_reset(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->i2c->CR2 = I2CxCR2_SWRES_10; - obj_s->i2c->CR2 = I2CxCR2_SWRES_01; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - int32_t pdata = 0; - - if (length > 0) { - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { - while (count < length) { - pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - } - - return result; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - - start_flag = 1; // Start Condition - - if (i2c_byte_write(obj, address) == I2C_ACK) { - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - - return result; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = 0; - - obj_s->i2c->ST = I2CxST_CLEAR; - - if (last) { - obj_s->i2c->OP |= I2CxOP_MFACK; - } else { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } - - obj_s->i2c->DBR = (0 & I2CxDBR_DB_MASK); - - if (wait_status(obj) < 0) { - result = -1; - } else { - result = (int32_t)(obj_s->i2c->DBR & I2CxDBR_DB_MASK); - } - - return result; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = 0; - - obj_s->i2c->ST = I2CxST_CLEAR; - if (start_flag == 1) { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - i2c_start_bit(obj); - start_flag = 0; - } else { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - } - - if (wait_status(obj) < 0) { - return -1; - } - - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - result = 1; - } else { - result = 0; - } - - return result; -} - -static void i2c_start_bit(i2c_t *obj) // Send START command -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t opreg = 0; - - opreg = obj_s->i2c->OP; - opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); - - if ((obj_s->i2c->SR & I2CxSR_BB)) { - opreg |= I2CxOP_SREN; - } - - obj_s->i2c->OP = opreg; - obj_s->i2c->CR2 |= I2CxCR2_START_CONDITION; -} - -static int32_t wait_status(i2c_t *p_obj) -{ - struct i2c_s *obj_s = I2C_S(p_obj); - volatile int32_t timeout; - timeout = I2C_TIMEOUT; - - while (!((obj_s->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) { - if ((timeout--) == 0) { - return (-1); - } - } - - return 0; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - struct i2c_s *obj_s = I2C_S(obj); - if (enable_slave) { - i2c_reset(obj); - obj_s->i2c->OP = I2CxOP_SLAVE_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - obj_s->i2c->CR2 = I2CxCR2_INIT; - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->AR = (obj_s->address & I2CAR_SA_MASK); - obj_s->i2c->IE = I2CxIE_INTI2C; - } else { - i2c_reset(obj); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->ST = I2CxST_CLEAR; - } -} - -int i2c_slave_receive(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = I2C_NO_DATA; - - if ((obj_s->i2c->ST & I2CxST_I2C) && (obj_s->i2c->OP & I2CxOP_SAST)) { - // Detect and clear arbitration lost. - if(!(obj_s->i2c->SR & 0x08)) { - obj_s->i2c->DBR = 0x00; - } - if ((obj_s->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) { - result = I2C_READ_ADDRESSED; - } else { - result = I2C_WRITE_ADDRESSED; - } - } - - return (result); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t count = 0; - - while (count < length) { - int32_t pdata = i2c_byte_read(obj, 0); - if ((obj_s->i2c->SR & I2CxSR_TRX)) { - return (count); - } else { - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - } - - i2c_slave_mode(obj,1); - - return (count); -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int32_t count = 0; - - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - - i2c_slave_mode(obj,1); - - return (count); -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->address = address & I2CAR_SA_MASK; - i2c_slave_mode(obj,1); -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#if DEVICE_I2C_ASYNCH - -void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, - uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) -{ - struct i2c_s *obj_s = I2C_S(obj); - i2c_irq_t *p_irqn = (i2c_irq_t *)obj_s->irqn; - - if(obj_s->state == I2C_TRANSFER_STATE_IDLE) { - // Disable and clear interrupt flag. - disable_irq(obj_s->irqn); - obj_s->i2c->IE = I2CxIE_CLEAR; - obj_s->i2c->ST = I2CxST_CLEAR; - clear_irq(obj_s->irqn); - - // Store given buffer data and lenght into I2C object and set state as I2C_TRANSFER_STATE_START. - obj_s->address = address; - obj_s->event = 0; - obj_s->stop = stop; - obj->tx_buff.buffer = (void *)tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - obj->rx_buff.buffer = rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - obj_s->state = I2C_TRANSFER_STATE_START; - - // Enable I2C interrupt. - obj_s->i2c->IE = I2CxIE_INTI2C; - - if ((tx_length == 0) && (rx_length != 0)) { - i2c_start_bit(obj); - obj_s->i2c->DBR = ((address | 1U) & I2CxDBR_DB_MASK); - } else { - i2c_start_bit(obj); - obj_s->i2c->DBR = (address & I2CxDBR_DB_MASK); - } - - // Enable I2C interrupr in NVIC. - NVIC_EnableIRQ(p_irqn->i2c); - NVIC_SetVector(p_irqn->i2c, handler); - } -} - -uint32_t i2c_irq_handler_asynch(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - i2c_irq_handler(obj); - return (obj_s->event & I2C_EVENT_ALL); -} - -uint8_t i2c_active(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint8_t ret_val = 0; - - if ((obj_s->i2c->CR2 & 0x08)) { - ret_val = 1; - } - return ret_val; -} - -void i2c_abort_asynch(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - - // Generate Stop condition on I2C bus - i2c_stop(obj); - - // Set state as idle and disable I2C interrupt. - obj_s->state = I2C_TRANSFER_STATE_IDLE; - disable_irq(obj_s->irqn); - clear_irq(obj_s->irqn); - obj_s->i2c->IE = I2CxIE_CLEAR; - - // Given I2C Software Reset - i2c_reset(obj); - - // Re-Store the I2C configuration - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->ST = I2CxST_CLEAR; - -} - -static void disable_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - NVIC_DisableIRQ(p_irqn->i2c); -} - -static void clear_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - NVIC_ClearPendingIRQ(p_irqn->i2c); -} - -static void i2c_irq_handler(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->i2c->ST = I2CxST_CLEAR; - - switch(obj_s->state) { - case I2C_TRANSFER_STATE_START: - // Check ACK for sent slave address. - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - - if(obj->tx_buff.length != (unsigned long)0) { // Check Tx buff length. - obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK; - obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t); - obj->tx_buff.pos++; - obj_s->state = I2C_TRANSFER_STATE_WRITE; - } else if(obj->rx_buff.length != 0) { // Check Rx buff length. - if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } else { - obj_s->i2c->OP |= I2CxOP_MFACK; - } - obj_s->i2c->DBR = 0x00; - obj_s->state = I2C_TRANSFER_STATE_READ; - } else { // Return transfer complete because of not given any Tx/Rx data. - obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - } else { // Return "No Slave", Because of Did not get any ACK for sent slave address. - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - case I2C_TRANSFER_STATE_WRITE: - if(obj->tx_buff.pos < obj->tx_buff.length) { - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK; - obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t); - obj->tx_buff.pos++; - } else { - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - } else if(obj->rx_buff.length != 0) { - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - i2c_start_bit(obj); - obj_s->i2c->DBR = ((obj_s->address | 1U) & I2CxDBR_DB_MASK); - obj_s->state = I2C_TRANSFER_STATE_RESTART; - } else { - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - } else { - if(obj_s->stop) { - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - } - obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - case I2C_TRANSFER_STATE_RESTART: - if(!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - // Set ACK/NACK - if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } else { - obj_s->i2c->OP |= I2CxOP_MFACK; - } - obj_s->i2c->DBR = 0x00; - obj_s->state = I2C_TRANSFER_STATE_READ; - } else { - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - case I2C_TRANSFER_STATE_READ: - if(obj->rx_buff.pos < obj->rx_buff.length) { - *((uint8_t *)obj->rx_buff.buffer) = (uint8_t)obj_s->i2c->DBR & I2CxDBR_DB_MASK; - obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + sizeof(uint8_t); - obj->rx_buff.pos++; - } - if(obj->rx_buff.pos < obj->rx_buff.length) { - // Set ACK/NACK - if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } else { - obj_s->i2c->OP |= I2CxOP_MFACK; - } - obj_s->i2c->DBR = 0x00; - } else { - if(obj_s->stop) { - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - } - obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - default: - break; - } - if(obj_s->state == I2C_TRANSFER_STATE_IDLE) { - disable_irq(obj_s->irqn); - obj_s->i2c->IE = I2CxIE_CLEAR; - } -} - -#endif // #if DEVICE_I2C_ASYNCH - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/objects.h deleted file mode 100644 index a02e801149..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/objects.h +++ /dev/null @@ -1,127 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "PortNames.h" -#include "PeripheralNames.h" -#include "txz_tspi.h" -#include "PinNames.h" -#include "TMPM3H6.h" -#include "gpio_include.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t BaudRate; - uint32_t DataBits; - uint32_t StopBits; - uint32_t Parity; - uint32_t Mode; - uint32_t FlowCtrl; -} uart_inittypedef_t; - -struct port_s { - PortName port; - uint32_t mask; -}; - -typedef struct { - uint8_t PinDATA; - uint8_t PinCR; - uint8_t PinFR[6]; - uint8_t PinOD; - uint8_t PinPUP; - uint8_t PinPDN; - uint8_t PinIE; -} gpio_regtypedef_t; - -typedef struct { - __IO uint32_t DATA; - __IO uint32_t CR; - __IO uint32_t FR[6]; - uint32_t RESERVED0[2]; - __IO uint32_t OD; - __IO uint32_t PUP; - __IO uint32_t PDN; - uint32_t RESERVED1; - __IO uint32_t IE; -} TSB_Port_TypeDef; - -struct serial_s { - PinName pin; - uint32_t index; - TSB_UART_TypeDef *UARTx; - uart_inittypedef_t uart_config; -}; - -struct analogin_s { - PinName pin; - ADCName adc; - TSB_AD_TypeDef *obj; -}; - -struct dac_s { - DACName dac; - TSB_DA_TypeDef *handler; -}; - -struct pwmout_s { - PinName pin; - TSB_T32A_TypeDef *channel; - uint16_t trailing_timing; - uint16_t leading_timing; - uint16_t divisor; - float period; -}; - -struct i2c_s { - uint32_t address; - TSB_I2C_TypeDef *i2c; -#if DEVICE_I2C_ASYNCH - uint32_t irqn; - uint32_t state; - uint32_t event; - uint32_t stop; -#endif -}; - -struct spi_s { - tspi_t p_obj; - SPIName module; - uint8_t bits; - PinName Slave_SCK; -#if DEVICE_SPI_ASYNCH - uint32_t irqn; - uint32_t event; - uint32_t max_size; - uint32_t state; -#endif -}; - -extern const gpio_regtypedef_t GPIO_SFRs[]; -extern const uint32_t GPIO_Base[]; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_driver_def.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_driver_def.h deleted file mode 100644 index 1b3ab6c5dd..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_driver_def.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - ******************************************************************************* - * @file txz_driver_def.h - * @brief All common macro and definition for TXZ peripheral drivers - * @version V1.0.0.0 - * $Date:: 2018-01-22 15:26:40 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TXZ_DRIVER_DEF_H -#define __TXZ_DRIVER_DEF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF - * @brief All common macro and definition for TXZ peripheral drivers - * @{ - */ - -/** @defgroup Device_Header_Included Device Header Included - * @brief Include the Device header file of a Target. - * @{ - */ -#include "TMPM3H6.h" /*!< TMPM3H6 Group Header file. */ -/** - * @} - */ /* End of group Device_Header */ - - -/** @defgroup TXZ_Exported_typedef TXZ Exported typedef - * @{ - */ -typedef enum { - TXZ_SUCCESS = 0U, - TXZ_ERROR = 1U -} TXZ_Result; - -typedef enum { - TXZ_BUSY = 0U, - TXZ_DONE = 1U -} TXZ_WorkState; - -typedef enum { - TXZ_DISABLE = 0U, - TXZ_ENABLE = 1U -} TXZ_FunctionalState; -/** - * @} - */ /* End of group TXZ_Exported_typedef */ - -/** @defgroup TXZ_Exported_macro TXZ Exported macro - * @{ - */ -#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) - -/** - * @brief To report the name of the source file and source line number where the - * assert_param error has occurred, "DEBUG" must be defined. And detailed - * definition of assert_failed() is needed to be implemented, which can be - * done, for example, in the main.c file. - */ -#ifdef DEBUG -void assert_failed(char *file, int32_t line); -#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) -#else -#define assert_param(expr) -#endif /* DEBUG */ -/** - * @} - */ /* End of group TXZ_Exported_macro */ - -/** - * @} - */ /* End of group Periph_Driver */ - -/** - * @} - */ /* End of group TXZ_DRIVER_DEF */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.c deleted file mode 100644 index f8b408a4b6..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.c +++ /dev/null @@ -1,2555 +0,0 @@ -/** - ******************************************************************************* - * @file txz_tspi.c - * @brief This file provides API functions for TSPI driver. - * @version V1.0.0.9 - * $Date:: 2018-01-22 15:26:40 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_tspi.h" - -#if defined(__TSPI_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup TSPI - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_define TSPI Private Define - * @{ - */ -/** - * @name TSPI NULL Pointer - * @brief Null Pointer for TSPI - * @{ - */ -#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ -/** - * @} - */ /* End of name TSPI NULL Pointer */ - -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ - -/** - * @name FIFO Max Num. - * @brief Transfer's/Receive's FIFO Max Num. - * @{ - */ -#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ -#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ -/** - * @} - */ /* End of name FIFO Max Num */ - -/** - * @name TSPIxDR_MASK Macro Definition. - * @brief TSPIxDR_MASK Macro Definition. - * @{ - */ -/* DR */ -#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ -/** - * @} - */ /* End of name TSPIxDR_MASK Macro Definition */ - -/** - * @name TSPI _DATA_LENGTH Macro Definition. - * @brief TSPI DATA LENGTH Macro Definition. - * @{ - */ -#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ -#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ -#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ -#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ -#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ -#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ -#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ -#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ -#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ -#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ -#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ -#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ -#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ -#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ -#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ -#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ -#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ -#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ -#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ -#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ -#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ -#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ -#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ -#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ -#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ -/** - * @} - */ /* End of name TSPI _DATA_LENGTH Macro Definition */ -/** - * @} - */ /* End of group TSPI_Private_typedef */ -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_define TSPI Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group TSPI_Private_define */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_typedef TSPI Private Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief TSPI mask array. -*/ -/*----------------------------------*/ -static uint32_t mask[32] ={ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TSPI_DR_8BIT_MASK, - TSPI_DR_9BIT_MASK, - TSPI_DR_10BIT_MASK, - TSPI_DR_11BIT_MASK, - TSPI_DR_12BIT_MASK, - TSPI_DR_13BIT_MASK, - TSPI_DR_14BIT_MASK, - TSPI_DR_15BIT_MASK, - TSPI_DR_16BIT_MASK, - TSPI_DR_17BIT_MASK, - TSPI_DR_18BIT_MASK, - TSPI_DR_19BIT_MASK, - TSPI_DR_20BIT_MASK, - TSPI_DR_21BIT_MASK, - TSPI_DR_22BIT_MASK, - TSPI_DR_23BIT_MASK, - TSPI_DR_24BIT_MASK, - TSPI_DR_25BIT_MASK, - TSPI_DR_26BIT_MASK, - TSPI_DR_27BIT_MASK, - TSPI_DR_28BIT_MASK, - TSPI_DR_29BIT_MASK, - TSPI_DR_30BIT_MASK, - TSPI_DR_31BIT_MASK -}; - -/** - * @} - */ /* End of group TSPI_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_fuctions TSPI Private Fuctions - * @{ - */ - -#ifdef DEBUG - __INLINE static int32_t check_param_transmit_enable(uint32_t param); - __INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); - __INLINE static int32_t check_param_transmit_master(uint32_t param); - __INLINE static int32_t check_param_transmit_mode(uint32_t param); - __INLINE static int32_t check_param_transmit_sel_select(uint32_t param); - __INLINE static int32_t check_param_frame_range(uint32_t param); - __INLINE static int32_t check_param_idle_imp(uint32_t param); - __INLINE static int32_t check_param_underrun_imp(uint32_t param); - __INLINE static int32_t check_param_tx_fill_level(uint32_t param); - __INLINE static int32_t check_param_rx_fill_level(uint32_t param); - __INLINE static int32_t check_param_tx_fifo_int(uint32_t param); - __INLINE static int32_t check_param_rx_fifo_int(uint32_t param); - __INLINE static int32_t check_param_err_int(uint32_t param); - __INLINE static int32_t check_param_tx_dma_int(uint32_t param); - __INLINE static int32_t check_param_rx_dma_int(uint32_t param); - __INLINE static int32_t check_param_input_clock(uint32_t param); - __INLINE static int32_t check_param_input_divider(uint32_t param); - __INLINE static int32_t check_param_data_direction(uint32_t param); - __INLINE static int32_t check_param_frame_length(uint32_t param); - __INLINE static int32_t check_param_frame_interval(uint32_t param); - __INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); - __INLINE static int32_t check_param_clock_edge_imp(uint32_t param); - __INLINE static int32_t check_param_clock_idle_imp(uint32_t param); - __INLINE static int32_t check_param_min_idle_time(uint32_t param); - __INLINE static int32_t check_param_clock_delay(uint32_t param); - __INLINE static int32_t check_param_negate_delay(uint32_t param); - __INLINE static int32_t check_param_parity_enable(uint32_t param); - __INLINE static int32_t check_param_parity_bit(uint32_t param); -#endif - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Enable's parameter. - * @param param :Transmit Enable's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transmission_Control - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_enable(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TRXE_DISABLE: - case TSPI_TRXE_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Mode's parameter. - * @param param :Transmit Mode's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transmission_Mode - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SPI_MODE: - case TSPI_SIO_MODE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Master/Slave parameter. - * @param param :Transmit Master/Slave parameter (Only support Master mode) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Operation_Select - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_master(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_MASTER_OPEARTION: - case TSPI_SLAVE_OPERATION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transfer Mode's parameter. - * @param param :Transfer Mode's parameter (not support Two Way) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transfer_Mode - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_mode(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TWO_WAY: - case TSPI_TX_ONLY: - case TSPI_RX_ONLY: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Sel Select's parameter. - * @param param :Transmit Sel Select's parameter (not support Two Way) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_CSSEL_Select - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS0_ENABLE: - case TSPI_TSPIxCS1_ENABLE: - case TSPI_TSPIxCS2_ENABLE: - case TSPI_TSPIxCS3_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Frame Range's parameter. - * @param param :TransmitFrame Range's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transfer_Frame_Range - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_range(uint32_t param) - -{ - int32_t result = PARAM_NG; - - if ((TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)){ - result = PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the IDLE Output Value's parameter. - * @param param :IDLE Output Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_IDLE_Output_value - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_idle_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TIDLE_Hiz: - case TSPI_TIDLE_LAST_DATA: - case TSPI_TIDLE_LOW: - case TSPI_TIDLE_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Underrun Occur Output Value's parameter. - * @param param :Underrun Occur Output Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Underrun_Output_value - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_underrun_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TXDEMP_LOW: - case TSPI_TXDEMP_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Fill Level's parameter. - * @param param :Tx Fill Level's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxFillLevel - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_fill_level(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_FILL_LEVEL_0: - case TSPI_TX_FILL_LEVEL_1: - case TSPI_TX_FILL_LEVEL_2: - case TSPI_TX_FILL_LEVEL_3: - case TSPI_TX_FILL_LEVEL_4: - case TSPI_TX_FILL_LEVEL_5: - case TSPI_TX_FILL_LEVEL_6: - case TSPI_TX_FILL_LEVEL_7: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Fill Level's parameter. - * @param param :Rx Fill Level's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxFillLevel - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_fill_level(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_FILL_LEVEL_0: - case TSPI_RX_FILL_LEVEL_1: - case TSPI_RX_FILL_LEVEL_2: - case TSPI_RX_FILL_LEVEL_3: - case TSPI_RX_FILL_LEVEL_4: - case TSPI_RX_FILL_LEVEL_5: - case TSPI_RX_FILL_LEVEL_6: - case TSPI_RX_FILL_LEVEL_7: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx FIFO Interrpt's parameter. - * @param param :Tx FIFO Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_FIFO_INT_DISABLE: - case TSPI_TX_FIFO_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Interrpt's parameter. - * @param param :Tx Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_INT_DISABLE: - case TSPI_TX_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx FIFO Interrpt's parameter. - * @param param :Rx FIFO Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxFIFOInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_FIFO_INT_DISABLE: - case TSPI_RX_FIFO_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Interrpt's parameter. - * @param param :Rx Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_INT_DISABLE: - case TSPI_RX_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Error Interrupt's parameter. - * @param param :Error Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ErrorInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_err_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_ERR_INT_DISABLE: - case TSPI_ERR_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx DMA Interrupt's parameter. - * @param param :Tx DMA Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxDMAInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_dma_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_DMA_INT_DISABLE: - case TSPI_TX_DMA_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx DMA Interrupt's parameter. - * @param param :Rx DMA Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxDMAInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_dma_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_DMA_INT_DISABLE: - case TSPI_RX_DMA_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Input Clock's parameter. - * @param param :Input Clock's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Baudrate_Clock - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_input_clock(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_BR_CLOCK_0: - case TSPI_BR_CLOCK_1: - case TSPI_BR_CLOCK_2: - case TSPI_BR_CLOCK_4: - case TSPI_BR_CLOCK_8: - case TSPI_BR_CLOCK_16: - case TSPI_BR_CLOCK_32: - case TSPI_BR_CLOCK_64: - case TSPI_BR_CLOCK_128: - case TSPI_BR_CLOCK_256: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Baudrate Divider's parameter. - * @param param :Baudrate Divider's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Baudrate_Clock - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_input_divider(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_BR_DIVIDER_16: - case TSPI_BR_DIVIDER_1: - case TSPI_BR_DIVIDER_2: - case TSPI_BR_DIVIDER_3: - case TSPI_BR_DIVIDER_4: - case TSPI_BR_DIVIDER_5: - case TSPI_BR_DIVIDER_6: - case TSPI_BR_DIVIDER_7: - case TSPI_BR_DIVIDER_8: - case TSPI_BR_DIVIDER_9: - case TSPI_BR_DIVIDER_10: - case TSPI_BR_DIVIDER_11: - case TSPI_BR_DIVIDER_12: - case TSPI_BR_DIVIDER_13: - case TSPI_BR_DIVIDER_14: - case TSPI_BR_DIVIDER_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Direction's parameter. - * @param param :Data Direction's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_data_direction(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_DATA_DIRECTION_LSB: - case TSPI_DATA_DIRECTION_MSB: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Length's parameter. - * @param param :Data Length's parameter (Only support 8bit DATA) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_length(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_DATA_LENGTH_8: - case TSPI_DATA_LENGTH_9: - case TSPI_DATA_LENGTH_10: - case TSPI_DATA_LENGTH_11: - case TSPI_DATA_LENGTH_12: - case TSPI_DATA_LENGTH_13: - case TSPI_DATA_LENGTH_14: - case TSPI_DATA_LENGTH_15: - case TSPI_DATA_LENGTH_16: - case TSPI_DATA_LENGTH_17: - case TSPI_DATA_LENGTH_18: - case TSPI_DATA_LENGTH_19: - case TSPI_DATA_LENGTH_20: - case TSPI_DATA_LENGTH_21: - case TSPI_DATA_LENGTH_22: - case TSPI_DATA_LENGTH_23: - case TSPI_DATA_LENGTH_24: - case TSPI_DATA_LENGTH_25: - case TSPI_DATA_LENGTH_26: - case TSPI_DATA_LENGTH_27: - case TSPI_DATA_LENGTH_28: - case TSPI_DATA_LENGTH_29: - case TSPI_DATA_LENGTH_30: - case TSPI_DATA_LENGTH_31: - case TSPI_DATA_LENGTH_32: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Frame Interval's parameter. - * @param param :Frame Interval's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Frame_Interval_Time - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_interval(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_INTERVAL_TIME_0: - case TSPI_INTERVAL_TIME_1: - case TSPI_INTERVAL_TIME_2: - case TSPI_INTERVAL_TIME_3: - case TSPI_INTERVAL_TIME_4: - case TSPI_INTERVAL_TIME_5: - case TSPI_INTERVAL_TIME_6: - case TSPI_INTERVAL_TIME_7: - case TSPI_INTERVAL_TIME_8: - case TSPI_INTERVAL_TIME_9: - case TSPI_INTERVAL_TIME_10: - case TSPI_INTERVAL_TIME_11: - case TSPI_INTERVAL_TIME_12: - case TSPI_INTERVAL_TIME_13: - case TSPI_INTERVAL_TIME_14: - case TSPI_INTERVAL_TIME_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS3 Polarity's parameter. - * @param param :TTSPIxCS3 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS3_NEGATIVE: - case TSPI_TSPIxCS3_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS2 Polarity's parameter. - * @param param :TTSPIxCS2 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS2_NEGATIVE: - case TSPI_TSPIxCS2_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS1 Polarity's parameter. - * @param param :TTSPIxCS1 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS1_NEGATIVE: - case TSPI_TSPIxCS1_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS0 Polarity's parameter. - * @param param :TTSPIxCS0 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS0_NEGATIVE: - case TSPI_TSPIxCS0_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock Polarity's parameter. - * @param param :Serial Clock Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_Polarity - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_1ST_EDGE: - case TSPI_SERIAL_CK_2ND_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock IDLE Polarity's parameter. - * @param param :Serial Clock IDLE Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_IDLE_LOW: - case TSPI_SERIAL_CK_IDLE_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Minimum IDLE Time's parameter. - * @param param :Minimum IDLE Time's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Minimum_IDLE_Time - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_min_idle_time(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_MIN_IDLE_TIME_1: - case TSPI_MIN_IDLE_TIME_2: - case TSPI_MIN_IDLE_TIME_3: - case TSPI_MIN_IDLE_TIME_4: - case TSPI_MIN_IDLE_TIME_5: - case TSPI_MIN_IDLE_TIME_6: - case TSPI_MIN_IDLE_TIME_7: - case TSPI_MIN_IDLE_TIME_8: - case TSPI_MIN_IDLE_TIME_9: - case TSPI_MIN_IDLE_TIME_10: - case TSPI_MIN_IDLE_TIME_11: - case TSPI_MIN_IDLE_TIME_12: - case TSPI_MIN_IDLE_TIME_13: - case TSPI_MIN_IDLE_TIME_14: - case TSPI_MIN_IDLE_TIME_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock Delay's parameter. - * @param param :Serial Clock Delay's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_Delay - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_delay(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_DELAY_1: - case TSPI_SERIAL_CK_DELAY_2: - case TSPI_SERIAL_CK_DELAY_3: - case TSPI_SERIAL_CK_DELAY_4: - case TSPI_SERIAL_CK_DELAY_5: - case TSPI_SERIAL_CK_DELAY_6: - case TSPI_SERIAL_CK_DELAY_7: - case TSPI_SERIAL_CK_DELAY_8: - case TSPI_SERIAL_CK_DELAY_9: - case TSPI_SERIAL_CK_DELAY_10: - case TSPI_SERIAL_CK_DELAY_11: - case TSPI_SERIAL_CK_DELAY_12: - case TSPI_SERIAL_CK_DELAY_13: - case TSPI_SERIAL_CK_DELAY_14: - case TSPI_SERIAL_CK_DELAY_15: - case TSPI_SERIAL_CK_DELAY_16: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Negate Delay's parameter. - * @param param :Negate Delay's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Negate_Delay - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_negate_delay(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_NEGATE_1: - case TSPI_NEGATE_2: - case TSPI_NEGATE_3: - case TSPI_NEGATE_4: - case TSPI_NEGATE_5: - case TSPI_NEGATE_6: - case TSPI_NEGATE_7: - case TSPI_NEGATE_8: - case TSPI_NEGATE_9: - case TSPI_NEGATE_10: - case TSPI_NEGATE_11: - case TSPI_NEGATE_12: - case TSPI_NEGATE_13: - case TSPI_NEGATE_14: - case TSPI_NEGATE_15: - case TSPI_NEGATE_16: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Enable's parameter. - * @param param :Parity Enable's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_parity_enable(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_PARITY_DISABLE: - case TSPI_PARITY_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Bit's parameter. - * @param param :Parity Bit's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_parity_bit(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_PARITY_BIT_ODD: - case TSPI_PARITY_BIT_EVEN: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -#endif -/** - * @} - */ /* End of group TSPI_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Initialize the TSPI object. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_init(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - /* Check the parameter of TTSPIxCR1. */ - assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); - assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); - assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); - assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); - assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); - assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); - /* Check the parameter of TTSPIxCR2 */ - assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); - assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); - assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); - assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); - assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); - assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); - assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); - assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); - assert_param(check_param_err_int(p_obj->init.cnt2.interr)); - assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); - assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); - /* Check the parameter of TTSPIxBR */ - assert_param(check_param_input_clock(p_obj->init.brd.brck)); - assert_param(check_param_input_divider(p_obj->init.brd.brs)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* TSPI Software Reset */ - p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); - p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE); - - /* Wait for 2 clocks of reset completion */ - __NOP(); - __NOP(); - - /* Control1 Register1 Set*/ - p_obj->p_instance->CR1 = 0x00001C01U; - p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ - p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims| p_obj->init.cnt1.trgen); - /* Control2 Register Set */ - p_obj->p_instance->CR2 = 0x00E10100U; - p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ - p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe |p_obj->init.cnt2.inttxwe | \ - p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare ); - - /* Control3 Register is FIFO clear, do nothing */ - - /* Baudrate Register Set */ - p_obj->p_instance->BR = 0U; - p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); - - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = 0x8800C400U; - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = 0U; - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - - /* not created */ - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the TSPI object. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_deinit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Disable the selected TSPI peripheral */ - p_obj->p_instance->CR0 |= TSPI_DISABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data.. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - - /* Transmit data check*/ - if((p_info->tx8.p_data == TSPI_NULL ) || (p_info->tx8.num == 0)) - { - p_obj->errcode = DATABUFEMPERR; - result = TXZ_ERROR; - return (result); - } - - /* FIFO Cear */ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - /* Transmit Data write to D ata Register */ - while (p_info->tx8.num > 0) - { - /* Check the current fill level */ - if(((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) - { - *((__IO uint8_t*)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); - p_info->tx8.num--; - /* check complete transmit */ - if((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - else - { - /* Enable TSPI Transmission Control */ - if(p_info->tx8.num==0){ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - return (result); - } - else { - /* Next transmit data sending */ - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - } - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - - } - /* check complete transmit */ - while((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - /* Check Error Flag */ - tspi_get_error(p_obj, &err); - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - - if(p_obj->errcode == NOERROR) { - //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - }else{ - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - uint32_t count = 0; - uint32_t index = 0; -// uint32_t level = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - /* Transmit data check*/ - if((p_info->rx8.p_data == TSPI_NULL ) || (p_info->rx8.num == 0)) - { - result = TXZ_ERROR; - return (result); - } - count = p_info->rx8.num; - - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - while (timeout > 0) - { - /* Wait until Receive Complete Flag is set to receive data */ - if((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) - { - while (count > 0) { - /* Check the remain data exist */ - if((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0){ - p_info->rx8.p_data[index] = (*((__IO uint8_t*)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); - count--; - index++; - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - } - /* Receive Complete Flag is clear */ - p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; - /* FIFO Cear */ - p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - } - else {timeout--;} - } - /* Timeout management */ - p_obj->errcode = TIMEOUTERR; - - /* Check Error Flag set */ - tspi_get_error(p_obj, &err); - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - - result = TXZ_ERROR; - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - p_obj->transmit.tx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - p_obj->transmit.tx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; - p_obj->transmit.info.tx32.num = p_info->tx32.num; - p_obj->transmit.tx_allign = 32; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /* transmit data length set */ - - /*--- TSPIxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Empty FIFO Num */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - /*--- TSPIxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - return (result); -} - - - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - p_obj->receive.rx_allign = 8; - - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; - p_obj->receive.info.rx32.num = p_info->rx32.num; - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_transmit(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - /* Check the transmit's end flag. */ - if (((status & TSPI_TX_DONE_FLAG ) == TSPI_TX_DONE) || - ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) - { - TXZ_WorkState txDone = TXZ_BUSY; - /* Read FIFO fill level. */ - __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Get the empty num in FIFO. */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - if (tlvl == TRANSFER_FIFO_MAX_NUM) - { - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.tx_allign = 8; - if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.tx_allign = 16; - if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.tx_allign = 32; - if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - } - if (txDone == TXZ_DONE) - { - /*=== Transmit Done!! ===*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /* Only the empty number of FIFO is a transmission data set. */ - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - #if 0 - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - #endif - } - } -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_receive(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.rx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - /* Check the receive's end flag. */ - if (((status & TSPI_RX_DONE_FLAG ) == TSPI_RX_DONE) || - ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) - { - /* Read FIFO fill level. */ - __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); - //__IO uint32_t rlvl = 7; - /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ - if (rlvl > RECEIVE_FIFO_MAX_NUM) - { - rlvl = RECEIVE_FIFO_MAX_NUM; - } - /*------------------------------*/ - /* Data Read */ - /*------------------------------*/ - /* Read FIFO data. */ - if (rlvl != 0) - { - uint32_t i; - for (i=0; ireceive.rx_allign) - { - case 8: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); - break; - case 16: - *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - case 32: - *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - default: - /* no process */ - break; - } - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - tspi_receive_t param; - - switch (p_obj->receive.rx_allign) - { - case 8: - param.rx8.p_data = p_obj->receive.info.rx8.p_data; - param.rx8.num = rlvl; - break; - case 16: - param.rx16.p_data = p_obj->receive.info.rx16.p_data; - param.rx16.num = rlvl; - break; - case 32: - param.rx32.p_data = p_obj->receive.info.rx32.p_data; - param.rx32.num = rlvl; - break; - default: - /* no process */ - break; - } - /* Call the receive handler with SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_error_irq_handler(tspi_t *p_obj) -{ - __IO uint32_t error; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current TSPIxERR. */ - error = p_obj->p_instance->ERR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- TSPIxERR ---*/ - /* Check the transmit error. */ - /* TRGERR */ - if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with FAILURE. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); - } - } - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* UNDERERR */ - if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) - { - err = TXZ_ERROR; - } - /* OVRERR */ - if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) - { - err = TXZ_ERROR; - } - /* PERR */ - if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) - { - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - /* Call the receive handler with FAILURE. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); - } - } - } -} - - -/*--------------------------------------------------*/ -/** - * @brief Data Format setting - * @param p_obj :TSPI object. - * @retval - - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_format(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | - * | 30-24 | - | - | - * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | - * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | - * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | - * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | - * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | - * | 15-8 | - | - | - * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | - * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | - * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | - * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | - * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | - * - * @param p_obj :TSPI object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_status is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI state */ - *p_status = p_obj->p_instance->SR; - if(p_status != TSPI_NULL){ return (result);} - else { - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI ERROR */ - *p_error = p_obj->p_instance->ERR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Error information clear. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 3 | TRGERR | Trigger Error. Use @ref TSPI_TRGErr. | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_error_clear(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_transmit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1). */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_receive(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR |TSPI_OVERRUN_ERR | TSPI_PARITY_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - - -/** - * @} - */ /* End of group TSPI_Exported_functions */ - -/** - * @} - */ /* End of group TSPI */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__TSPI_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.h deleted file mode 100644 index 0a0e8bd13d..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.h +++ /dev/null @@ -1,1320 +0,0 @@ -/** - ******************************************************************************* - * @file txz_tspi.h - * @brief This file provides all the functions prototypes for TSPI driver. - * @version V1.0.0.7 - * $Date:: 2018-01-22 15:26:40 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __TSPI_H -#define __TSPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup TSPI TSPI - * @brief TSPI Driver. - * @{ - */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_define TSPI Exported Define - * @{ - */ -/** - * @defgroup TSPI_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define TSPI_NULL ((void *)0) -/** - * @} - */ /* End of group TSPI_NullPointer */ - -/** - * @defgroup TSPI_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group TSPI_ParameterResult */ - -/** - * @defgroup TSPI_Result Result - * @brief TSPI Result Macro Definition. - * @{ - */ -#define TSPI_RESULT_SUCCESS (0) /*!< Success */ -#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ -/** - * @} - */ /* End of group TSPI_Result */ - -/** - * @defgroup TSPI_SW_Reset SW Reset - * @brief Software Rest Macro Definition. - * @{ - */ -#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */ -#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */ -/** - * @} - */ /* End of group TSPI_SW_Reset */ - - -/** - * @defgroup TSPI_Enable TSPI Enable/Disable Control - * @brief Enable/Disable TSPIE Macro Definition. - * @{ - */ -#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Enable */ - -/** - * @defgroup TSPI_Triger_Control Triger Control - * @brief Enable/Disable TRGEN Macro Definition. - * @{ - */ -#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Control Transmission Control - * @brief Enable/Disable TRXE Macro Definition. - * @{ - */ -#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ -#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Mode Transmission Mode - * @brief TSPIIMS Mode Macro Definisiton. - * @{ - */ -#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ -#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ -/** - * @} - */ /* End of group TSPI_Transmission_Mode */ - - -/** - * @defgroup TSPI_Operation_Select Operation Select - * @brief Master/Slave MSTR Operation Macro Definisiton. - * @{ - */ -#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /*!< MASTER MODE */ -#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ -/** - * @} - */ /* End of group TSPI_Operation_Select */ - - -/** - * @defgroup TSPI_Transfer_Mode Transfer Mode - * @brief Transfer Mode TMMD Macro Definisiton. - * @{ - */ -#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ -#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ -#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ -#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ -/** - * @} - */ /* End of group TSPI_Transfer_Mode */ - - -/** - * @defgroup TSPI_CSSEL_Select CSSEL Select - * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ -#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ -#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ -#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ -/** - * @} - */ /* End of group TSPI_CSSEL_Select */ - -/** - * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range - * @brief Transfer Frame Range Macro Definisiton. - * @{ - */ -#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /*!< Single Transfer Frame :0 */ -#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ -/** - * @} - */ /* End of group TSPI_Transfer_Frame_Range */ -/** - * @defgroup TSPI_IDLE_Output_value IDLE Output Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ -#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ -#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ -#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_IDLE_Output_value */ - -/** - * @defgroup TSPI_RXDLY_value RXDLY Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_RXDLY_40MHz_OVER ((uint32_t)0x00010000) /*!< fsys > 40MHz */ -#define TSPI_RXDLY_40MHz_OR_LESS ((uint32_t)0x00000000) /*!< fsys <= 40MHz */ -/** - * @} - */ /* End of group TSPI_RXDLY_value*/ - - - /** - * @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value - * @brief In case of Under Run Output Value TXDEMP Macro Definisiton. - * @{ - */ -#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ -#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_Underrun_Output_value */ - - -/** - * @defgroup TSPI_TxFillLevel Tx Fill Level - * @brief Transmit Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ -#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ -#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ -#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ -#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ -#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ -#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ -#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ -/*! - * @} - */ /* End of group TSPI_TxFillLevel */ - - -/** - * @defgroup TSPI_RxFillLevel Rx Fill Level - * @brief Receive Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */ -#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ -#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ -#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ -#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ -#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ -#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ -#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ -#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_RxFillLevel */ - - -/** - * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt - * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterrupt */ - - -/** - * @defgroup TSPI_TxInterrupt Tx Interrpt - * @brief Enable/Disable Transmit Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxInterrupt */ - - -/** - * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt - * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterrupt */ - - -/** - * @defgroup TSPI_RxInterrupt Rx Interrpt - * @brief Enable/Disable Receive Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxInterrupt */ - - -/** - * @defgroup TSPI_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ErrorInterrupt */ - - -/** - * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt - * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ -#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxDMAInterrupt */ - - -/** - * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt - * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ -#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxDMAInterrupt */ - - -/** - * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear - * @brief Tx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Tx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear - * @brief Rx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Rx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock - * @brief Baudrate Input Clock Macro Definisiton. - * @{ - */ -#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ -#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ -#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ -#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ -#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ -#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ -#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ -#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ -#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ -#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Clock */ - - -/** - * @defgroup TSPI_Baudrate_Divider Baudrate Divider - * @brief Baudrate IDivider Macro Definisiton. - * @{ - */ -#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ -#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ -#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ -#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ -#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ -#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ -#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ -#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ -#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ -#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ -#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ -#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ -#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ -#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ -#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ -#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Divider */ - - -/** - * @defgroup TSPI_DataDirection Data Direction - * @brief Data Direction Macro Definisiton. - * @{ - */ -#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ -#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ -/*! - * @} - */ /* End of group TSPI_DataDirection */ - - -/** - * @defgroup TSPI_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ -#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ -#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ -#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ -#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ -#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ -#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ -#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ -#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ -#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ -#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ -#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ -#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ -#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ -#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ -#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ -#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ -#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ -#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ -#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ -#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ -#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ -#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ -#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ -#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ -#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ -/** - * @} - */ /* End of group TSPI_DataLength */ - - -/** - * @defgroup TSPI_Frame_Interval_Time Frame Interval time - * @brief Frame Interval time Macro Definisiton. - * @{ - */ -#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Frame_Interval_Time */ - - -/** - * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity - * @brief TSPIxCS3 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS3_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity - * @brief TSPIxCS2 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS2_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity - * @brief TSPIxCS1 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS1_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity - * @brief TSPIxCS0 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS0_Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity - * @brief Serial Clock Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ -#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ -/** - * @} - */ /* End of group Serial Clock Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity - * @brief Serial Clock IDLE Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ -#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ - - -/** - * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time - * @brief Minimum IDLE Time Macro Definisiton. - * @{ - */ -#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Minimum_IDLE_Time */ - - -/** - * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay - * @brief Serial Clock Delay Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_Delay */ - - -/** - * @defgroup TSPI_Negate_Delay Negate Delay - * @brief Negate Delay Macro Definisiton. - * @{ - */ -#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ -#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ -#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ -#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ -#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ -#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ -#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ -#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ -#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ -#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ -#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ -#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ -#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ -#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ -#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Negate_Delay */ - - -/** - * @defgroup TSPI_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ParityEnable */ - - -/** - * @defgroup TSPI_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ -/** - * @} - */ /* End of group TSPI_ParityBit */ - - -/** - * @defgroup TSPI_Status_Setting_flag Status Setting Flag - * @brief Enable/Disable Status Setting Flag Macro Definisiton. - * @{ - */ -#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ -#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ -/** - * @} - */ /* End of group TSPI_Status_Setting_flag */ - - -/** - * @defgroup TSPI_TxState Transmitting State Flag - * @brief Transmitting State Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ -#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_TxState */ - - -/** - * @defgroup TSPI_TxDone Transmitting Complete Flag - * @brief Transmitting Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ -#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ -#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxDone */ - - -/** - * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag - * @brief Transmitting FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ -#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag - * @brief Transmitting FIFO Empty Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_TxFIFOEmptyFlag */ - -/** - * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level - * @brief Current Transmitting FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ -#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ -#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ -#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ -#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ -#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ -#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ -#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_TxReachFillLevel */ - - -/** - * @defgroup TSPI_RxState Receive State Flag - * @brief Receive State Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ -#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_RxState */ - - -/** - * @defgroup TSPI_RxDone Receive Complete Flag - * @brief Receive Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ -#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ -#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxDone */ - - -/** - * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag - * @brief Rx FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ -#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag - * @brief Receiving FIFO Full Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_RxFIFOFullFlag */ - - -/** - * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level - * @brief Current Receive FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ -#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ -#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ -#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ -#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ -#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ -#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ -#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_RxReachFillLevel */ - - -/** - * @defgroup TSPI_TRGErr Triger Error - * @brief Triger Error Macro Definisiton. - * @{ - */ -#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ -#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_TRGErr */ - -/** - * @defgroup TSPI_UnderrunErr Underrun Error - * @brief Underrun Error Macro Definisiton. - * @{ - */ -#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ -#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_UnderrunErr */ - -/** - * @defgroup TSPI_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ -#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_OverrunErr */ - - -/** - * @defgroup TSPI_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ -#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_ParityErr */ - - /** - * @defgroup TSPI_Data_allign Data allign - * @brief Data allign Macro Definisiton. - * @{ - */ -#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ -#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ -#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ -/** - * @} - */ /* End of group TSPI_Data_allign */ - - /** - * @defgroup TSPI_FifoMax FIFO MAX - * @brief FIFO MAX LEVEL - * @{ - */ -#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ -/** - * @} - */ /* End of group TSPI_FifoMax */ - - /** - * @defgroup TSPI_ErrCode Error Code - * @brief Error Code Macro Definisiton. - * @{ - */ -#define NOERROR ((uint32_t)0x00000000) /*!< no error */ -#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ -#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ -#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ -#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ -#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ -#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ -#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ -#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ -#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ -#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ -/** -* @} - */ /* End of group TSPI_ErrCode */ - - /** - * @defgroup TSPI_Buffer_Size Receive Buffer size - * @brief Error Code Macro Definisiton. - * @{ - */ -#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ -/** -* @} - */ /* End of group TSPI_Buffer_Size */ -/** - * @} - */ /* End of group TSPI_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/* No define */ -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @struct tspi_receive8_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive8_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive16_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive16_t; - -/** - * @struct tspi_receive32_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive32_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive_t - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ - tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ - tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ -} tspi_receive_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit8_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit8_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit16_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit16_t; -/*----------------------------------*/ -/** - * @struct tspi_transmit32_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit32_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit_t - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ - tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ - tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ -} tspi_transmit_t; - -/*----------------------------------*/ -/** - * @struct tspi_control1_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t trgen; /*!< TRGEN Transmission Triger Control. - : Use @ref TSPI_Triger_Control */ - uint32_t trxe; /*!< TRXE Transmission Control. - : Use @ref TSPI_Transmission_Control */ - uint32_t tspims; /*!< TSPI/SIO Transmission Mode. - : Use @ref TSPI_Transmission_Mode */ - uint32_t mstr; /*!< Master/Slave Operation Select. - : Use @ref TSPI_Operation_Select */ - uint32_t tmmd; /*!< Transfer Mode Select. - : Use @ref TSPI_Transfer_Mode */ - uint32_t cssel; /*!< CSSEL Select. - : Use @ref TSPI_CSSEL_Select */ - uint32_t fc; /*!< Transfer Frame Value. - : Range ( TSPI_TRANS_RANGE_SINGLE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ -} tspi_control1_t; - -/*----------------------------------*/ -/** - * @struct tspi_control2_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tidle; /*!< IDLE Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t txdemp; /*!< Under Run Occur Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t rxdly; /*!< Fsys Select. - : Use @ref TSPI_RXDLY_value */ - uint32_t til; /*!< Transmit Fill Level. - : Use @ref TSPI_TxFillLevel */ - uint32_t ril; /*!< Receive Fill Level. - : Use @ref TSPI_RxFillLevel */ - uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. - : Use @ref TSPI_TxFIFOInterrupt */ - uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. - : Use @ref TSPI_TxInterrupt */ - uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. - : Use @ref TSPI_RxFIFOInterrupt */ - uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. - : Use @ref TSPI_RxInterrupt */ - uint32_t interr; /*!< Enable/Disable Error Interrupt. - : Use @ref TSPI_ErrorInterrupt */ - uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. - : Use @ref TSPI_TxDMAInterrupt */ - uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. - : Use @ref TSPI_RxDMAInterrupt */ -} tspi_control2_t; - -/*----------------------------------*/ -/** - * @struct tspi_control3_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tfempclr; /*!< Transmit Buffer Clear. - : Use @ref TSPI_Tx_Buffer_Clear */ - uint32_t rffllclr; /*!< Receive Buffer Clear. - : Use @ref TSPI_Rx_Buffer_Clear */ -} tspi_control3_t; - -/*----------------------------------*/ -/** - * @struct tspi_baudrate_t - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t brck; /*!< Baudrate Input Clock. - : Use @ref TSPI_Baudrate_Clock */ - uint32_t brs; /*!< Baudrate Divider. - : Use @ref TSPI_Baudrate_Divider */ -} tspi_baudrate_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr0_t - * @brief Format control0. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t dir; /*!< Data Direction. - : Use @ref TSPI_DataDirection */ - uint32_t fl; /*!< Data Length. - : Use @ref TSPI_DataLength */ - uint32_t fint; /*!< Frame Interval time. - : Use @ref TSPI_Frame_Interval_Time */ - uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS3_Polarity */ - uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS2_Polarity */ - uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS1_Polarity */ - uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS0_Polarity */ - uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. - : Use @ref TSPI_Serial_Clock_Polarity */ - uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. - : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ - uint32_t csint; /*!< Minimum IDLE Time. - : Use @ref TSPI_Minimum_IDLE_Time */ - uint32_t cssckdl; /*!< Serial Clock Delay. - : Use @ref TSPI_Serial_Clock_Delay */ - uint32_t sckcsdl; /*!< Negate Delay. - : Use @ref TSPI_Negate_Delay */ -} tspi_fmtr0_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr1_t - * @brief Format control1. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t reserved; /*!< SIO Slave MOde. - : */ - uint32_t vpe; /*!< Enable/Disable Parity Function. - : Use @ref TSPI_ParityEnable */ - uint32_t vpm; /*!< Odd/Even Parity Bit. - : Use @ref TSPI_ParityBit */ -} tspi_fmtr1_t; - -/*----------------------------------*/ -/** - * @struct tspi_status_t - * @brief Status register. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. - : Use @ref TSPI_Status_Setting_flag */ - uint32_t txrun; /*!< Stop/Active Tx Active Flag. - : Use @ref TSPI_TxState */ - uint32_t txend; /*!< Tx Data Send Complete Flag. - : Use @ref TSPI_TxDone */ - uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag. - : Use @ref TSPI_TxFIFOInterruptFlag */ - uint32_t tfemp; /*!< Tx FIFO Empty Flag. - : Use @ref TSPI_TxFIFOEmptyFlag */ - uint32_t tlvll; /*!< Tx Reach Fill Level - : Use @ref TSPI_TxReachFillLevel */ - uint32_t rxrun; /*!< Stop/Active Rx Active Flag. - : Use @ref TSPI_RxState */ - uint32_t rxend; /*!< Rx Data Receive Complete Flag. - : Use @ref TSPI_RxDone */ - uint32_t intrxff; /*!< Rx FIFO Interrpt Flag - : Use @ref TSPI_RxFIFOInterruptFlag */ - uint32_t rffll; /*!< Rx FIFO Full Flag - : Use @ref TSPI_RxFIFOFullFlag */ - uint32_t rlvl; /*!< Rx Reach Fill Level - : Use @ref TSPI_RxReachFillLevel */ -} tspi_status_t; - -/*----------------------------------*/ -/** - * @struct tspi_error_t - * @brief Error flag. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t udrerr; /*!< Underrun Error. - : Use @ref TSPI_UnderrunErr */ - uint32_t ovrerr; /*!< Overrun Error. - : Use @ref TSPI_OverrunErr */ - uint32_t perr; /*!< Parity Error. - : Use @ref TSPI_ParityErr */ -} tspi_error_t; - - -/*----------------------------------*/ -/** - * @struct tspi_initial_setting_t - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - tspi_control1_t cnt1; /*!< Control1 setting. - : Use @ref tspi_control1_t */ - tspi_control2_t cnt2; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_control3_t cnt3; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_baudrate_t brd; /*!< Baudrate setting. - : Use @ref tspi_baudrate_t */ - tspi_fmtr0_t fmr0; /*!< Format control0 setting. - : Use @ref tspi_fmtr0_t */ - tspi_fmtr1_t fmr1; /*!< Format control1 setting. - : Use @ref tspi_fmtr1_t */ -} tspi_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief TSPI handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct tspi_handle -{ - TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ - tspi_initial_setting_t init; /*!< Initial setting. */ - uint32_t errcode; /*!< ErrorCode */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - tspi_transmit_t info; /*!< Transmit Data Information. */ - uint8_t tx_allign; /*!< Transmit Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - tspi_receive_t info; /*!< Receive Data Information. */ - uint8_t rx_allign; /*!< Receive Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} tspi_t; -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_functions TSPI Exported Functions - * @{ - */ -TXZ_Result tspi_init(tspi_t *p_obj); -TXZ_Result tspi_deinit(tspi_t *p_obj); -TXZ_Result tspi_format(tspi_t *p_obj); -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); -void tspi_irq_handler_transmit(tspi_t *p_obj); -void tspi_irq_handler_receive(tspi_t *p_obj); -void tspi_error_irq_handler(tspi_t *p_obj); -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); -TXZ_Result tspi_error_clear(tspi_t *p_obj); -TXZ_Result tspi_discard_transmit(tspi_t *p_obj); -TXZ_Result tspi_discard_receive(tspi_t *p_obj); -/** - * @} - */ /* End of group TSPI_Exported_functions */ -/** - * @} - */ /* End of group TSPI */ -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TSPI_H */ - - diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c deleted file mode 100644 index b4f9e47483..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c +++ /dev/null @@ -1,198 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "gpio_include.h" - -void pin_function(PinName pin, int function) -{ - int port = 0; - uint8_t bit = 0; - uint8_t func = 0; - uint8_t dir = 0; - uint32_t port_base = 0; - uint32_t mode_base = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Calculate pin function and pin direction - func = PIN_FUNC(function); - dir = PIN_DIR(function); - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(port); - // Initialization PxFR OFF - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_CLR(mode_base, bit); - - // Initialize Input - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - - switch (func) { - case 0: - break; - case 1: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - break; - case 2: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - break; - case 3: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - break; - case 4: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - break; - case 5: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - break; - case 6: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - break; - default: - break; - } - - if (func != 0) { - BITBAND_PORT_SET(mode_base, bit); - } - if (dir == PIN_OUTPUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } else if (dir == PIN_INOUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - int port = 0; - uint8_t bit = 0; - uint8_t val = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Check if function is in range - if (mode > OpenDrain) { - return; - } - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - val = (1 << bit); - - switch (port) { - case PortA: - if (mode == OpenDrain) TSB_PA->OD |= val; - else if (mode == PullUp) TSB_PA->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PA->PDN |= val; - break; - case PortB: - if (mode == OpenDrain) TSB_PB->OD |= val; - else if (mode == PullUp) TSB_PB->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PB->PDN |= val; - break; - case PortC: - if (mode == OpenDrain) TSB_PC->OD |= val; - else if (mode == PullUp) TSB_PC->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PC->PDN |= val; - break; - case PortD: - if (mode == OpenDrain) TSB_PD->OD |= val; - else if (mode == PullUp) TSB_PD->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PD->PDN |= val; - break; - case PortE: - if (mode == OpenDrain) TSB_PE->OD |= val; - else if (mode == PullUp) TSB_PE->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PE->PDN |= val; - break; - case PortF: - if (mode == OpenDrain) TSB_PF->OD |= val; - else if (mode == PullUp) TSB_PF->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PF->PDN |= val; - break; - case PortG: - if (mode == OpenDrain) TSB_PG->OD |= val; - else if (mode == PullUp) TSB_PG->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PG->PDN |= val; - break; - case PortH: - if (mode == PullDown) TSB_PH->PDN |= val; - break; - case PortJ: - if (mode == OpenDrain) TSB_PJ->OD |= val; - else if (mode == PullUp) TSB_PJ->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PJ->PDN |= val; - break; - case PortK: - if (mode == OpenDrain) TSB_PK->OD |= val; - else if (mode == PullUp) TSB_PK->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PK->PDN |= val; - break; - case PortL: - if (mode == OpenDrain) TSB_PL->OD |= val; - else if (mode == PullUp) TSB_PL->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PL->PDN |= val; - break; - case PortM: - if (mode == OpenDrain) TSB_PM->OD |= val; - else if (mode == PullUp) TSB_PM->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PM->PDN |= val; - break; - case PortN: - if (mode == OpenDrain) TSB_PN->OD |= val; - else if (mode == PullUp) TSB_PN->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PN->PDN |= val; - break; - case PortP: - if (mode == OpenDrain) TSB_PP->OD |= val; - else if (mode == PullUp) TSB_PP->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PP->PDN |= val; - break; - case PortR: - if (mode == OpenDrain) TSB_PR->OD |= val; - else if (mode == PullUp) TSB_PR->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PR->PDN |= val; - break; - default: - break; - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/port_api.c deleted file mode 100644 index e4583b9871..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/port_api.c +++ /dev/null @@ -1,159 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(port <= PortR); - - // Store port and port mask for future use - obj->port = port; - obj->mask = mask; - - // Enabling Port Clock Supply - TSB_CG->FSYSENA |= (1 << (obj->port)); - - // Set port function and port direction - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_function(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortR); - - // Set mode for masked pins - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint8_t bit = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortR); - - // Set direction for masked pins - switch (dir) { - case PIN_INPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INPUT); - } - } - break; - case PIN_OUTPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_OUTPUT); - } - } - break; - case PIN_INOUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INOUT); - } - } - break; - default: - break; - } -} - -void port_write(port_t *obj, int value) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortR); - - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - - // Calculate data to write to masked pins - data = (port_data & ~obj->mask) | (value & obj->mask); - - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - if (((data >> bit) & 0x01) == GPIO_PIN_SET) { - BITBAND_PORT_SET(base, bit); - } else { - BITBAND_PORT_CLR(base, bit); - } - } - } -} - -int port_read(port_t *obj) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortR); - - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - - // Calculate data of masked pins - data = port_data & obj->mask; - - return data; -} - -PinName port_pin(PortName port, int pin_n) -{ - PinName pin = NC; - pin = (PinName)((port << 3 ) | pin_n); - return pin; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pwmout_api.c deleted file mode 100644 index 58fb3c8d48..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pwmout_api.c +++ /dev/null @@ -1,192 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pwmout_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -static const PinMap PinMap_PWM[] = { - {PP0, PWM_0, PIN_DATA(4, 1)}, - {PC0, PWM_1, PIN_DATA(4, 1)}, - {PJ0, PWM_2, PIN_DATA(4, 1)}, - {PK2, PWM_3, PIN_DATA(4, 1)}, - {PN0, PWM_4, PIN_DATA(4, 1)}, - {NC, NC, 0} -}; - -static const uint32_t prescale_tbl[] = { - 2, 8, 32, 128, 256, 512, 1024 -}; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - uint16_t counter = 0; - - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel - MBED_ASSERT(pwm != (PWMName)NC); - - switch (pwm) { - case PWM_0: - obj->channel = TSB_T32A1; - TSB_CG_FSYSENA_IPENA27 = ENABLE; - TSB_CG_FSYSENA_IPENA13 = ENABLE; - break; - case PWM_1: - obj->channel = TSB_T32A2; - TSB_CG_FSYSENA_IPENA28 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - break; - case PWM_2: - obj->channel = TSB_T32A3; - TSB_CG_FSYSENA_IPENA29 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - break; - case PWM_3: - obj->channel = TSB_T32A4; - TSB_CG_FSYSENA_IPENA30 = ENABLE; - TSB_CG_FSYSENA_IPENA09 = ENABLE; - break; - case PWM_4: - obj->channel = TSB_T32A5; - TSB_CG_FSYSENA_IPENA31 = ENABLE; - TSB_CG_FSYSENA_IPENA12 = ENABLE; - break; - default: - obj->channel = NULL; - break; - } - - pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM - obj->pin = pin; - obj->period = DEFAULT_PERIOD; - obj->divisor = DEFAULT_CLOCK_DIVISION; - obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP); - obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE); - obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - - counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor); - obj->channel->RGC0 = counter; - obj->channel->RGC1 = counter; - obj->trailing_timing = counter; - obj->leading_timing = counter; -} - -void pwmout_free(pwmout_t* obj) -{ - // Stops and clear count operation - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - pwmout_write(obj, 0); - obj->pin = NC; - obj->channel = NULL; - obj->trailing_timing = 0; - obj->leading_timing = 0; - obj->divisor = 0; -} - -void pwmout_write(pwmout_t* obj, float value) -{ - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again - obj->leading_timing = (obj->trailing_timing - - (obj->trailing_timing * value)); // leading_timing value - obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -float pwmout_read(pwmout_t* obj) -{ - float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - return duty_cycle; -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - float seconds = 0; - int cycles = 0; - uint32_t clkdiv = 0; - int i = 0; - float duty_cycle = 0; - - seconds = (float)(us / 1000000.0f); - - // Select highest timer resolution - for (i = 0; i < 7; ++i) { - cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds); - if (cycles <= MAX_COUNTER_16B) { - clkdiv = i + 1; // range 1:7 - clkdiv <<= 28; - break; - } else { - cycles = MAX_COUNTER_16B; - clkdiv = 7; - clkdiv <<= 28; - } - } - - // Stop timer for setting clock again - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - // Restore the duty-cycle - duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - - obj->trailing_timing = cycles; - obj->leading_timing = (cycles - (cycles * duty_cycle)); - // Change the source clock division and period - obj->channel->MOD = T32A_MODE_32; - obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - obj->channel->RGC0 = obj->leading_timing; - obj->channel->RGC1 = obj->trailing_timing; - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float seconds = 0; - float value = 0; - - seconds = (float)(us / 1000000.0f); - value = (((seconds / obj->period) * 100.0f) / 100.0f); - - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/reset_reason_api.c deleted file mode 100644 index 1d65e9f425..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/reset_reason_api.c +++ /dev/null @@ -1,132 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "reset_reason_api.h" - -#ifdef DEVICE_RESET_REASON - -#include "TMPM3H6.h" -#include - -static uint8_t set_bit_count(uint32_t reg); -static uint8_t bit_pos(uint32_t reg); -static bool bit_status(uint32_t reg, uint8_t bit_no); - -static reset_reason_t reset_reason1[6] = { - RESET_REASON_POWER_ON, - RESET_REASON_UNKNOWN, - RESET_REASON_UNKNOWN, - RESET_REASON_PIN_RESET, - RESET_REASON_WAKE_LOW_POWER, - RESET_REASON_BROWN_OUT -}; - -static reset_reason_t reset_reason2[4] = { - RESET_REASON_SOFTWARE, - RESET_REASON_LOCKUP, - RESET_REASON_WATCHDOG, - RESET_REASON_PLATFORM -}; - -void hal_reset_reason_clear(void) -{ - TSB_RLM->RSTFLG0 = 0; - TSB_RLM->RSTFLG1 = 0; -} - -uint32_t hal_reset_reason_get_raw(void) -{ - uint32_t ret = (((TSB_RLM->RSTFLG1 & 0xFF) << 8) | (TSB_RLM->RSTFLG0 & 0xFF)); - return ret; -} - -reset_reason_t hal_reset_reason_get(void) -{ - char multi_flag = 0; - reset_reason_t ret; - - uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_RLM->RSTFLG0); - uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_RLM->RSTFLG1); - - if (NoOfSetBitCountReg1 != 0x00) { - if (NoOfSetBitCountReg1 > 0x01) { - if (bit_status(TSB_RLM->RSTFLG0, 3)) { - ret = RESET_REASON_POWER_ON; - } else { - ret = RESET_REASON_MULTIPLE; - } - } else { - ret = reset_reason1[bit_pos(TSB_RLM->RSTFLG0)]; - } - } else if (NoOfSetBitCountReg2 != 0x00) { - if (NoOfSetBitCountReg2 > 0x01) { - ret = RESET_REASON_MULTIPLE; - } else { - ret = reset_reason2[bit_pos(TSB_RLM->RSTFLG1)]; - } - } else { - ret = RESET_REASON_UNKNOWN; - } - - return ret; -} - -void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) -{ - cap->reasons = 1 << RESET_REASON_UNKNOWN; - cap->reasons |= 1 << RESET_REASON_POWER_ON; - cap->reasons |= 1 << RESET_REASON_MULTIPLE; -} - -static bool bit_status(uint32_t reg, uint8_t bit_no) -{ - bool status = false; - - if (reg & (1 << bit_no)) { - status = true; - } - - return status; -} - -static uint8_t set_bit_count(uint32_t reg) -{ - uint8_t count = 0; - int8_t index = 0; - - for (index = 0; index < (sizeof(uint32_t) * 8); index++) { - if (reg & (1 << index)) { - count++; - if (count > 0x01) { - break; - } - } - } - - return count; -} - -static uint8_t bit_pos(uint32_t reg) -{ - uint8_t bit_no = 0; - - for (bit_no = 0; bit_no < (sizeof(uint32_t) * 8); bit_no++) { - if (reg & (1 << bit_no)) { - return bit_no; - } - } -} - -#endif // DEVICE_RESET_REASON diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/rtc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/rtc_api.c deleted file mode 100644 index 86c5231d7a..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/rtc_api.c +++ /dev/null @@ -1,226 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "rtc_api.h" -#include "mbed_mktime.h" - -#define RTC_24_HOUR_MODE ((uint8_t)0x01) -#define PAGER_PAGE_ONE ((uint8_t)0x01) -#define PAGER_PAGE_ZERO ((uint8_t)0xEE) -#define RTC_CLK_ENABLE ((uint8_t)0x08) -#define RTC_CLK_DISABLE ((uint8_t)0xE7) -#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) -#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) -#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) -#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) -#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) -#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) -#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) -#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) -#define ELOSC_CFG_CLOCK ((uint64_t)(32768)) -#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro -#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro - -static int rtc_inited = 0; -static int diff_year = 100; //our RTC register only support 2000~2099 -static void external_losc_enable(void); - -void rtc_init(void) -{ - if (!rtc_inited) { - TSB_CG_FSYSENB_IPENB03 = 1; // Enable Sys Clock for RTC - external_losc_enable(); // Enable low-speed oscillator - TSB_RTC->PAGER = 0x00; // Disable clock and alarm - - while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { - // Reset RTC sec counter - } - - TSB_RTC->RESTR = 0xE7; - while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { - // Reset RTC sec counter - } - - TSB_RTC->PAGER |= PAGER_PAGE_ONE; - TSB_RTC->YEARR = 0x03; // Set leap year state - TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode - TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode - TSB_RTC->YEARR = 0x01; // Set year value - TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value - TSB_RTC->DATER = (uint8_t)0x01; // Set date value - TSB_RTC->DAYR = (uint8_t)0x0; // Set day value - TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value - TSB_RTC->MINR = (uint8_t)0x02; // Set minute value - TSB_RTC->SECR = (uint8_t)0x22; // Set second value - TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock - rtc_inited = 1; // Enable RTC initialzed status - } -} - -void rtc_free(void) -{ - rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE -} - -int rtc_isenabled(void) -{ - return rtc_inited; // Return status of RTC peripheral driver -} - -time_t rtc_read(void) -{ - if (!rtc_inited) { - // Return invalid time for now! - return 0; - } - - struct tm timeinfo; - uint8_t read_1 = 0U; - uint8_t read_2 = 0U; - - timeinfo.tm_isdst = 0;//no summer time - - TSB_RTC->PAGER &= PAGER_PAGE_ZERO; - - read_1 = TSB_RTC->SECR; // Get sec value - timeinfo.tm_sec = HEX2DEC(read_1); - - do { // Get minute value - read_1 = TSB_RTC->MINR; - read_2 = TSB_RTC->MINR; - } while (read_1 != read_2); - timeinfo.tm_min = HEX2DEC(read_1); - - do { // Get hour value - read_1 = TSB_RTC->HOURR; - read_2 = TSB_RTC->HOURR; - } while (read_1 != read_2); - timeinfo.tm_hour = HEX2DEC(read_1); - - do { // Get Month date value - read_1 = TSB_RTC->DATER; - read_2 = TSB_RTC->DATER; - } while (read_1 != read_2); - timeinfo.tm_mday = HEX2DEC(read_1); - - do { // Get Month value - read_1 = TSB_RTC->MONTHR; - read_2 = TSB_RTC->MONTHR; - } while (read_1 != read_2); - timeinfo.tm_mon = HEX2DEC(read_1)-1; - - do { // Get weekday value - read_1 = TSB_RTC->DAYR; - read_2 = TSB_RTC->DAYR; - } while (read_1 != read_2); - timeinfo.tm_wday = HEX2DEC(read_1); - - do { // Get year value - read_1 = TSB_RTC->YEARR; - read_2 = TSB_RTC->YEARR; - } while (read_1 != read_2); - timeinfo.tm_year = (HEX2DEC(read_1)+ diff_year); - - time_t t; - - if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { - return 0; - } - return t; -} - -void rtc_write(time_t t) -{ - if (!rtc_inited) { - // Initialize the RTC as not yet initialized - rtc_init(); - } - - struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { - return; - } - - diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100); - TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock - - // Check current year is leap year or not - if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) || - (timeinfo.tm_year % 400) == 0) { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year - TSB_RTC->YEARR = 0x00; - } else if ((timeinfo.tm_year % 4) == 1) { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year - TSB_RTC->YEARR = 0x01; - } else if ((timeinfo.tm_year % 4) == 2) { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year - TSB_RTC->YEARR = 0x02; - } else { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year - TSB_RTC->YEARR = 0x03; - } - - TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0 - - TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value - // Set month value, tm_mon=0 means Jan while 1 is Jan - TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon+1)); - TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value - TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value - TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value - TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value - TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value - - TSB_RTC->RESTR |= RTCRESTR_RSTTMR_R_RUN; - while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { - // Reset RTC sec counter, otherwise the 1st second will not be accurate - } - - // Setting Wait - // When stop mode is selected, CaseA or CaseB is need. - // CaseA: Wait for RTC 1Hz interrupt. - // CaseB: Check the clock register setting. - { - uint8_t flag = 1; - time_t time_read = {0}; - while(flag) { - time_read = rtc_read(); - if( time_read == t) { // Wait for setting successfully - flag = 0; - } - } - } - TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock -} - -static void external_losc_enable(void) -{ - uint32_t work; - if( (TSB_RLM->LOSCCR & 0x01) == 0 ) { //external losc is not enabled. - uint64_t x = (uint64_t)(ELOSC_CFG_WARM_UP_TIME * ELOSC_CFG_CLOCK); - x = (uint64_t)(x / (uint64_t)(1000000)); - work = (uint32_t)x; - work &= (uint32_t)(0xFFFFFFF0); - work <<= 8; - TSB_CG->WUPLCR = work; - TSB_RLM->LOSCCR = RLMLOSCCR_XTEN_RW_ENABLE; - work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK); - TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE); - while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) { - // No processing - } - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/serial_api.c deleted file mode 100644 index 148349dc40..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/serial_api.c +++ /dev/null @@ -1,436 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "serial_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" -#include "objects.h" - -static const PinMap PinMap_UART_TX[] = { - {PM1, SERIAL_0, PIN_DATA(1, 1)}, - {PJ2, SERIAL_1, PIN_DATA(2, 1)}, - {PB2, SERIAL_2, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PM2, SERIAL_0, PIN_DATA(1, 0)}, - {PJ1, SERIAL_1, PIN_DATA(2, 0)}, - {PB3, SERIAL_2, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -#if DEVICE_SERIAL_FC -static const PinMap PinMap_UART_CTS[] = { - {PM3, SERIAL_0, PIN_DATA(1, 0)}, - {PJ3, SERIAL_1, PIN_DATA(1, 0)}, - {PB4, SERIAL_2, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RTS[] = { - {PM4, SERIAL_0, PIN_DATA(1, 1)}, - {PJ4, SERIAL_1, PIN_DATA(1, 1)}, - {PB5, SERIAL_2, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; -#endif - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; -static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct); -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate); -static void uart_swreset(TSB_UART_TypeDef *UARTx); - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart_name != NC); - - obj->index = uart_name; - switch (uart_name) { - case SERIAL_0: - obj->UARTx = TSB_UART0; - TSB_CG_FSYSENA_IPENA23 = ENABLE; - TSB_CG_FSYSENA_IPENA11 = ENABLE; - break; - case SERIAL_1: - obj->UARTx = TSB_UART1; - TSB_CG_FSYSENA_IPENA24 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - TSB_CG_FSYSENA_IPENA09 = ENABLE; - break; - case SERIAL_2: - obj->UARTx = TSB_UART2; - TSB_CG_FSYSENA_IPENA25 = ENABLE; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - break; - default: - error("UART is not available"); - break; - } - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC && rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; - } else { - if (tx != NC) { - obj->uart_config.Mode = UART_ENABLE_TX; - } else { - if (rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX; - } - } - } - - obj->uart_config.BaudRate = 9600; - obj->uart_config.DataBits = 8; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = ParityNone; - obj->uart_config.FlowCtrl = FlowControlNone; - - uart_init(obj->UARTx, &obj->uart_config); - is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - obj->UARTx->TRANS = 0; - obj->UARTx->CR0 = 0; - obj->UARTx->CR1 = 0; - - uart_swreset(obj->UARTx); - - obj->uart_config.BaudRate = 0; - obj->uart_config.DataBits = 0; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = 0; - obj->uart_config.Mode = 0; - obj->uart_config.FlowCtrl = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->uart_config.BaudRate = baudrate; - uart_init(obj->UARTx, &obj->uart_config); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - - obj->uart_config.DataBits = data_bits; - obj->uart_config.StopBits = stop_bits; - obj->uart_config.Parity = parity; - uart_init(obj->UARTx, &obj->uart_config); -} - -void INTUART0TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); -} - -void INTUART0RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); -} - -void INTUART1TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); -} - -void INTUART1RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); -} -void INTUART2TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); -} - -void INTUART2RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch (obj->index) { - case SERIAL_0: - if (irq == RxIrq) { - irq_n = INTUART0RX_IRQn; - } else { - irq_n = INTUART0TX_IRQn; - } - break; - case SERIAL_1: - if (irq == RxIrq) { - irq_n = INTUART1RX_IRQn; - } else { - irq_n = INTUART1TX_IRQn; - } - break; - case SERIAL_2: - if (irq == RxIrq) { - irq_n = INTUART2RX_IRQn; - } else { - irq_n = INTUART2TX_IRQn; - } - break; - default: - break; - } - NVIC_ClearPendingIRQ(irq_n); - if (enable) { - NVIC_EnableIRQ(irq_n); - } else { - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) -{ - int data = 0; - - while (!serial_readable(obj)) { // Wait until Rx buffer is full - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS &= 0x0D; - } - - data = data | (obj->UARTx->DR & 0xFFU); - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS |= UART_ENABLE_TX; - } - - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)) { - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS &= 0x0E; - } - - obj->UARTx->DR = c & 0xFFU; - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS |= UART_ENABLE_RX; - } -} - -int serial_readable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x0000000F) != 0) { - ret = 1; - } - - return ret; -} - -int serial_writable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x8000) == 0) { - ret = 1; - } - - return ret; -} - -void serial_clear(serial_t *obj) -{ - obj->UARTx->FIFOCLR = 0x03; -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - obj->UARTx->TRANS |= 0x08; -} - -void serial_break_clear(serial_t *obj) -{ - obj->UARTx->TRANS &= ~(0x08); -} - -#if DEVICE_SERIAL_FC -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); - UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); - UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts); - MBED_ASSERT((int)uart_name != NC); - - pinmap_pinout(rxflow, PinMap_UART_RTS); - pinmap_pinout(txflow, PinMap_UART_CTS); - pin_mode(txflow, PullUp); - pin_mode(rxflow, PullUp); - - obj->UARTx->CR0 |= (3U << 9); -} -#endif - -static void uart_swreset(TSB_UART_TypeDef *UARTx) -{ - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } - - UARTx->SWRST = UARTxSWRST_SWRST_10; - UARTx->SWRST = UARTxSWRST_SWRST_01; - - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } -} - -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate) -{ - uint32_t clock = 0; - uint32_t k = 0; - uint64_t tx = 0; - uint64_t work = 1; - uint64_t p_range64 = 0; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 1; - - SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency - clock = SystemCoreClock; - - tx = (uint64_t)((uint64_t)clock << 6); - tx /= work; - tx64 = (uint64_t)((uint64_t)clock << 8); - tx64 /= work64; - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - - boud64 = (64U * boudrate); - p_range64 = ((boud64 / 100) * 3); - - for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) { - work = tx + k; - if (work >= (uint64_t)((uint64_t)1 << 6)) { - work -= (uint64_t)((uint64_t)1 << 6); - work >>= 6; - if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { - work64 = work <<6; - work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); - work64 = (tx64 / work64); - if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) { - brddiviser->brn = work; - brddiviser->brk = k; - break; - } - } - } - } -} - -static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct) -{ - uart_boudrate_t UTx_brd = {0}; - uint32_t brk = 0; - uint32_t tmp = 0; - uint32_t parity_check = 0; - uint32_t data_length = 0; - - UARTx->CLK = UART_PLESCALER_1; // Register Setting - uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate); - UTx_brd.ken = UART_DIVISION_ENABLE; - brk = (UTx_brd.brk << 16); - UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn); - parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0); - data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2); - tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length); - UARTx->CR0 = tmp; - UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); - UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); - UARTx->TRANS = InitStruct->Mode; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/sleep.c deleted file mode 100644 index 9cbfbb6ca8..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/sleep.c +++ /dev/null @@ -1,89 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "gpio_include.h" - -static void warming_up_time(void); - -void hal_sleep(void) -{ - // Set low power consumption mode IDLE - TSB_CG->STBYCR = CG_STBY_MODE_IDLE; - __DSB(); // Enter idle mode - __WFI(); -} - -void hal_deepsleep(void) -{ - uint32_t tmp = 0; - - TSB_CG_FSYSENB_IPENB31 = ENABLE; - - TSB_SIWD0->EN = DISABLE; - TSB_SIWD0->CR = 0xB1; - - while ((TSB_FC->SR0 & 0x01) != 0x01) { - // Flash wait - } - - while (TSB_CG_WUPHCR_WUEF) { - // Wait for end of Warming-up for IHOSC1 - } - - TSB_CG_WUPHCR_WUCLK = DISABLE; - warming_up_time(); - TSB_CG->STBYCR = CG_STBY_MODE_STOP1; - TSB_CG_PLL0SEL_PLL0SEL = DISABLE; - - while (TSB_CG_PLL0SEL_PLL0ST) { - // Wait for PLL status of fsys until off state(fosc=0) - } - - TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys - TSB_CG_OSCCR_IHOSC1EN = ENABLE; - TSB_CG_OSCCR_OSCSEL = DISABLE; - - while (TSB_CG_OSCCR_OSCF) { - // Wait for fosc status until IHOSC1 = 0 - } - - tmp = TSB_CG->OSCCR; - tmp &= EXTERNEL_OSC_MASK; - TSB_CG->OSCCR = tmp; - TSB_CG_OSCCR_IHOSC2EN = DISABLE; - - while (TSB_CG_OSCCR_IHOSC2F) { - // Wait for status of OFD until off "0" - } - - __DSB(); - __WFI(); -} - -static void warming_up_time(void) -{ - uint32_t work = 0; - uint64_t x = 0; - - x = (uint64_t)(IHOSC_CFG_WARM_UP_TIME * IHOSC_CFG_CLOCK); - x = (uint64_t)(x / (uint64_t)(1000000)); - - work = (uint32_t)x; - work &= (uint32_t)(0xFFFFFFF0); - work <<= 16; - work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK); - TSB_CG->WUPHCR = work; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/spi_api.c deleted file mode 100644 index e18eeacb0b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/spi_api.c +++ /dev/null @@ -1,558 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "spi_api.h" -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" -#include "txz_tspi.h" - -#define TIMEOUT 1000 -#define INITIAL_SPI_FREQ 1000000 - -#if DEVICE_I2C_ASYNCH -#define SPI_S(obj) (struct spi_s *) (&((obj)->spi)) -#else -#define SPI_S(obj) (struct spi_s *) (obj) -#endif - -#if DEVICE_SPI_ASYNCH -static void spi_irq_handler(spi_t *obj); -static void disable_irq(uint32_t irqn); -static void clear_irq(uint32_t irqn); - -enum { - SPI_TRANSFER_STATE_IDLE = 0U, - SPI_TRANSFER_STATE_BUSY -} SPI_TransferState; - -typedef struct { - IRQn_Type Tx; - IRQn_Type Rx; - IRQn_Type Error; -} spi_irq_t; - -static const spi_irq_t SPI_CH0_IRQN_TBL[1] = { - {INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn} -}; - -static const spi_irq_t SPI_CH1_IRQN_TBL[1] = { - {INTT1RX_IRQn, INTT1TX_IRQn, INTT1ERR_IRQn} -}; -#endif - -static const PinMap PinMap_SPI_SCLK[] = { - {PM0, SPI_0, PIN_DATA(3, 1)}, - {PP0, SPI_1, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PM1, SPI_0, PIN_DATA(3, 1)}, - {PP1, SPI_1, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PM2, SPI_0, PIN_DATA(3, 0)}, - {PP2, SPI_1, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PM3, SPI_0, PIN_DATA(3, 2)}, - {PL6, SPI_1, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPISLAVE_SCLK[] = { - {PM0, SPI_0, PIN_DATA(3, 0)}, - {PP0, SPI_1, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -void spi_init(spi_t *t_obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - struct spi_s *obj = SPI_S(t_obj); - // Check pin parameters - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk); - obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->module!= NC); - - // Identify SPI module to use - switch ((int)obj->module) { - case SPI_0: - obj->p_obj.p_instance = TSB_TSPI0; - TSB_CG_FSYSENA_IPENA18 = ENABLE; - TSB_CG_FSYSENA_IPENA11 = ENABLE; -#if DEVICE_SPI_ASYNCH - obj->irqn = (uint32_t)&SPI_CH0_IRQN_TBL; -#endif - break; - case SPI_1: - obj->p_obj.p_instance = TSB_TSPI1; - TSB_CG_FSYSENA_IPENA19 = ENABLE; - TSB_CG_FSYSENA_IPENA13 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; -#if DEVICE_SPI_ASYNCH - obj->irqn = (uint32_t)&SPI_CH1_IRQN_TBL; -#endif - break; - default: - error("Cannot found SPI module corresponding with input pins."); - break; - } - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - obj->Slave_SCK = sclk; - - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - - //Control 1 configurations - obj->p_obj.init.id = (uint32_t)obj->module; - obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled - obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication - obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode - obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // master mode operation - obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) - obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid - obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // transfer single frame at a time continuously - - //Control 2 configurations - obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; - obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low - obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_40MHz_OVER; - obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level - obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level - obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; - obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; - obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; - obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; - obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; - - //Control 3 configurations - obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear - obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear - - //baudrate settings - spi_frequency(t_obj, (int)INITIAL_SPI_FREQ); - - //Format Control 0 settings - obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first - obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; - obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; - - //Special control on polarity of signal and generation timing - obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; - obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; - obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; - obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; - - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; - obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; - obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; - - //Format Control 1 settings tspi_fmtr1_t - obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; - obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; - - obj->bits = (uint8_t)TSPI_DATA_LENGTH_8; - //initialize SPI - tspi_init(&obj->p_obj); -} - -void spi_free(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - tspi_deinit(&obj->p_obj); - obj->module = (SPIName)NC; -} - -void spi_format(spi_t *t_obj, int bits, int mode, int slave) -{ - struct spi_s *obj = SPI_S(t_obj); - MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode - MBED_ASSERT((bits >= 8) && (bits <= 32)); - - obj->bits = bits; - obj->p_obj.init.fmr0.fl = (bits << 24); - - if ((mode >> 1) & 0x1) { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; - } else { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - } - - if (mode & 0x1) { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; - } else { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - } - - if(slave) { - pinmap_pinout(obj->Slave_SCK, PinMap_SPISLAVE_SCLK); - obj->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation - } - tspi_init(&obj->p_obj); -} - -void spi_frequency(spi_t *t_obj, int hz) -{ - struct spi_s *obj = SPI_S(t_obj); - uint8_t brs = 0; - uint8_t brck = 0; - uint16_t prsck = 1; - uint64_t fscl = 0; - uint64_t tmp_fscl = 0; - uint64_t fx = 0; - uint64_t tmpvar = SystemCoreClock; - - SystemCoreClockUpdate(); - - tmpvar = tmpvar / 2; - - for (prsck = 1; prsck <= 512; prsck *= 2) { - fx = ((uint64_t)tmpvar / prsck); - for (brs = 1; brs <= 16; brs++) { - fscl = fx /brs; - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - obj->p_obj.init.brd.brck = (brck << 4); - if (brs == 16) { - obj->p_obj.init.brd.brs = 0; - } else { - obj->p_obj.init.brd.brs = brs; - } - } - } - brck ++; - } - tspi_init(&obj->p_obj); -} - -int spi_master_write(spi_t *t_obj, int value) -{ - struct spi_s *obj = SPI_S(t_obj); - uint8_t ret_value = 0; - - tspi_transmit_t send_obj; - tspi_receive_t rec_obj; - - // Transmit data - send_obj.tx8.p_data = (uint8_t *)&value; - send_obj.tx8.num = 1; - tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT); - - // Read received data - rec_obj.rx8.p_data = &ret_value; - rec_obj.rx8.num = 1; - tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT); - - return ret_value; -} - -int spi_master_block_write(spi_t *t_obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(t_obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - int ret = 1; - uint32_t status; - - tspi_get_status(&obj->p_obj, &status); - if((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) { - ret = 0; - } - - return ret; -} - -int spi_slave_read(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - uint8_t ret_value = 0; - - ret_value = obj->p_obj.p_instance->DR & 0xFF; - - // Receive Complete Flag is clear. - obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; - obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - - return ret_value; -} - -void spi_slave_write(spi_t *t_obj, int value) -{ - struct spi_s *obj = SPI_S(t_obj); - - // Enable TSPI Transmission Control. - obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - obj->p_obj.p_instance->DR = value & 0xFF; -} - -int spi_busy(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - int ret = 1; - uint32_t status = 0; - - tspi_get_status(&obj->p_obj, &status); - - if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { - ret = 0; - } - - return ret; -} - -uint8_t spi_get_module(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - return (uint8_t)(obj->module); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPISLAVE_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -#if DEVICE_SPI_ASYNCH - -void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, - uint32_t handler, uint32_t event, DMAUsage hint) -{ - struct spi_s *spiobj = SPI_S(obj); - spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn; - bool use_tx = (tx != NULL && tx_length > 0); - bool use_rx = (rx != NULL && rx_length > 0); - - // don't do anything, if the buffers aren't valid - if (!use_tx && !use_rx) { - return; - } - - disable_irq(spiobj->irqn); - - spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - - clear_irq(spiobj->irqn); - - obj->tx_buff.buffer = (void *)tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - obj->rx_buff.buffer = (void *)rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - spiobj->event = 0; - spiobj->state = SPI_TRANSFER_STATE_IDLE; - - NVIC_SetVector(p_irqn->Error, (uint32_t)handler); - NVIC_SetVector(p_irqn->Tx, (uint32_t)handler); - NVIC_SetVector(p_irqn->Rx, (uint32_t)handler); - - // Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt - spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE); - - if (use_tx && use_rx) { - spiobj->max_size = tx_length < rx_length ? rx_length:tx_length; - spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; - } else if(use_tx) { - spiobj->max_size = tx_length; - spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; - } else if(use_rx) { - spiobj->max_size = rx_length; - spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - spiobj->p_obj.p_instance->DR = 0xFF; - } - - spiobj->state = SPI_TRANSFER_STATE_BUSY; - NVIC_EnableIRQ(p_irqn->Error); - NVIC_EnableIRQ(p_irqn->Tx); - NVIC_EnableIRQ(p_irqn->Rx); -} - -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - spi_irq_handler(obj); - return ((spiobj->event & SPI_EVENT_ALL)| SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ; -} - -uint8_t spi_active(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - uint8_t ret_val = 0; - - if (spiobj->state != SPI_TRANSFER_STATE_IDLE) { - ret_val = 1; - } - - return ret_val; -} - -void spi_abort_asynch(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - - disable_irq(spiobj->irqn); - clear_irq(spiobj->irqn); - tspi_init(&spiobj->p_obj); -} - -static void spi_irq_handler(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - - // Check for revceive complete flag. - if((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) && - (spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) { - // Check receiver FIFO level - uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF; - - while((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) { - ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF; - rlvl--; - } - - if(obj->rx_buff.pos == spiobj->max_size) { - spiobj->state = SPI_TRANSFER_STATE_IDLE; - } - // Clear rx buffer - spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE; - } - - // Check for transmit completion flag - if(spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) { - obj->tx_buff.pos++; - spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; - - if(obj->tx_buff.pos == (spiobj->max_size)) { - spiobj->state = SPI_TRANSFER_STATE_IDLE; - } - - if((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) { - spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF); - } else if (obj->tx_buff.pos < spiobj->max_size) { - spiobj->p_obj.p_instance->DR = 0xFF; - } - } - - // Check for error flag - if(spiobj->p_obj.p_instance->ERR) { - spiobj->event = SPI_EVENT_ERROR; - spiobj->state = SPI_TRANSFER_STATE_IDLE; - disable_irq(spiobj->irqn); - spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - clear_irq(spiobj->irqn); - return; - } - - if(spiobj->state == SPI_TRANSFER_STATE_IDLE) { - spiobj->event = SPI_EVENT_COMPLETE; - disable_irq(spiobj->irqn); - spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - clear_irq(spiobj->irqn); - } -} - -static void disable_irq(uint32_t irqn) -{ - spi_irq_t *p_irqn = (spi_irq_t *)irqn; - NVIC_DisableIRQ(p_irqn->Tx); - NVIC_DisableIRQ(p_irqn->Rx); - NVIC_DisableIRQ(p_irqn->Error); -} - -static void clear_irq(uint32_t irqn) -{ - spi_irq_t *p_irqn = (spi_irq_t *)irqn; - NVIC_ClearPendingIRQ(p_irqn->Tx); - NVIC_ClearPendingIRQ(p_irqn->Rx); - NVIC_ClearPendingIRQ(p_irqn->Error); -} - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c deleted file mode 100644 index 822bcb0ef8..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c +++ /dev/null @@ -1,96 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "us_ticker_api.h" -#include "gpio_include.h" - -static bool us_ticker_inited = false; // Is ticker initialized yet? - -const ticker_info_t* us_ticker_get_info(void) -{ - static const ticker_info_t info = { - 1248125, // (39.94 MHz / 32 ) - 32 // 32 bit counter - }; - return &info; -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) { - us_ticker_disable_interrupt(); - return; - } - us_ticker_inited = true; - - TSB_CG_FSYSENA_IPENA26 = TXZ_ENABLE; - TSB_T32A0->MOD = T32A_MODE_32; - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->CRC = T32A_PRSCLx_32; - TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); - - NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -uint32_t us_ticker_read(void) -{ - if (!us_ticker_inited) { - us_ticker_init(); - } - - return (TSB_T32A0->TMRC); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - NVIC_DisableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->RGC1 = timestamp; - NVIC_EnableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INTT32A00C_IRQn); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - // Disable interrupts by NVIC - TSB_T32A0->STC = T32A_INT_MASK; - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - NVIC_DisableIRQ(INTT32A00C_IRQn); -} - -void us_ticker_clear_interrupt(void) -{ - TSB_T32A0->STC = T32A_INT_MASK; - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); -} - -void us_ticker_free(void) -{ - TSB_CG_FSYSENA_IPENA26 = TXZ_DISABLE; - us_ticker_inited = false; - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - // Disable and clear interrupts in NVIC - TSB_T32A0->STC = T32A_INT_MASK; - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - NVIC_DisableIRQ(INTT32A00C_IRQn); -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PeripheralNames.h deleted file mode 100644 index 55bfd7bcb8..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PeripheralNames.h +++ /dev/null @@ -1,130 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SERIAL_0 = 0, - SERIAL_1, - SERIAL_2, - SERIAL_3, - SERIAL_4, - SERIAL_5, - INVALID_SERIAL = (int)NC -} UARTName; - -typedef enum { - ADC_AINA00 = 0, - ADC_AINA01, - ADC_AINA02, - ADC_AINA03, - ADC_AINA04, - ADC_AINA05, - ADC_AINA06, - ADC_AINA07, - ADC_AINA08, - ADC_AINA09, - ADC_AINA10, - ADC_AINA11, - ADC_AINA12, - ADC_AINA13, - ADC_AINA14, - ADC_AINA15, - ADC_AINA16, - ADC_AINA17, - ADC_AINA18, - ADC_AINA19, - ADC_AINA20, - INVALID_ADC = (int)NC -} ADCName; - -typedef enum { - DAC_A0 = 0, - DAC_A1, - INVALID_DAC = (int)NC -} DACName; - -typedef enum { - SPI_0 = 0, - SPI_1, - SPI_2, - SPI_3, - SPI_4, - INVALID_SPI = (int)NC -} SPIName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - I2C_3, - INVALID_I2C = (int)NC -} I2CName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - INVALID_PWM = (int)NC -} PWMName; - -typedef enum { - GPIO_IRQ_00 = 0, - GPIO_IRQ_01, - GPIO_IRQ_02, - GPIO_IRQ_03, - GPIO_IRQ_04, - GPIO_IRQ_05, - GPIO_IRQ_06, - GPIO_IRQ_07, - GPIO_IRQ_08, - GPIO_IRQ_09, - GPIO_IRQ_10, - GPIO_IRQ_11, - GPIO_IRQ_12, - GPIO_IRQ_13, - GPIO_IRQ_14, - GPIO_IRQ_15, - GPIO_IRQ_16, - GPIO_IRQ_17_18, - GPIO_IRQ_19_22, - GPIO_IRQ_23_26, - GPIO_IRQ_27_28, - GPIO_IRQ_29, - GPIO_IRQ_30_31, - INVALID_GPIO_IRQ = (int)NC -} gpio_irqname; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART SERIAL_1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PinNames.h deleted file mode 100644 index 74ea0bff1b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PinNames.h +++ /dev/null @@ -1,145 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INOUT -} PinDirection; - -typedef enum { - // TMPM3HQ Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, - PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, - PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, - PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, - PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, - PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, - PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, - PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, - PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, - PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, PT6, PT7, - PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, - PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, - - // LED - LED1 = PK4, - LED2 = PK5, - LED3 = PK6, - LED4 = PK7, - - // External data bus Pin Names - D0 = PV7, - D1 = PV6, - D2 = PC4, - D3 = PK2, - D4 = PC3, - D5 = PJ0, - D6 = PN0, - D7 = PM6, - D8 = PT0, - D9 = PG2, - D10 = PT1, - D11 = PT3, - D12 = PT4, - D13 = PT2, - D14 = PC1, - D15 = PC0, - - // Analogue out pins - A0 = PF2, - A1 = PF3, - A2 = PF4, - A3 = PF5, - A4 = PF6, - A5 = PF7, - - // DAC - DAC0 = PG0, - DAC1 = PG1, - - // DAP_UART - USBTX = PJ1, - USBRX = PJ2, - MBEDIF_TXD = USBTX, - MBEDIF_RXD = USBRX, - - // Push buttons - SW1 = PV0, - SW2 = PV1, - SW3 = PV2, - SW4 = PV3, - - // Standardized button names - BUTTON1 = SW1, - BUTTON2 = SW2, - BUTTON3 = SW3, - BUTTON4 = SW4, - - // TSPI2 - MOSI = D11, - MISO = D12, - SCLK = D13, - CS = D10, - - // SD Shield TSPI2 - SD_SEL = CS, // Chip select - SD_CLK = SCLK, // SPI clock - SD_MISO = MISO, // Master in Salve out - SD_MOSI = MOSI, // Master out Salve in - - // I2C pins - SDA = D14, - SCL = D15, - I2C_SDA = SDA, - I2C_SCL = SCL, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 0, - PullDown, - PullNone, - OpenDrain, - PullDefault -} PinMode; - -typedef enum { - DISABLE = 0, - ENABLE -} FunctionalState; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PortNames.h deleted file mode 100644 index 95a638dfe4..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PortNames.h +++ /dev/null @@ -1,50 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortC, - PortD, - PortE, - PortF, - PortG, - PortH, - PortJ, - PortK, - PortL, - PortM, - PortN, - PortP, - PortR, - PortT, - PortU, - PortV -} PortName; - -#define IS_GPIO_PORT(param) ((param) <= PortV) // parameter checking for port number - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogin_api.c deleted file mode 100644 index b551d957f6..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogin_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogin_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "gpio_include.h" - -static const PinMap PinMap_ADC[] = { - {PD0, ADC_AINA00, PIN_DATA(0, 0)}, - {PD1, ADC_AINA01, PIN_DATA(0, 0)}, - {PD2, ADC_AINA02, PIN_DATA(0, 0)}, - {PD3, ADC_AINA03, PIN_DATA(0, 0)}, - {PE0, ADC_AINA04, PIN_DATA(0, 0)}, - {PE1, ADC_AINA05, PIN_DATA(0, 0)}, - {PE2, ADC_AINA06, PIN_DATA(0, 0)}, - {PE3, ADC_AINA07, PIN_DATA(0, 0)}, - {PE4, ADC_AINA08, PIN_DATA(0, 0)}, - {PE5, ADC_AINA09, PIN_DATA(0, 0)}, - {PE6, ADC_AINA10, PIN_DATA(0, 0)}, - {PF0, ADC_AINA11, PIN_DATA(0, 0)}, - {PF1, ADC_AINA12, PIN_DATA(0, 0)}, - {PF2, ADC_AINA13, PIN_DATA(0, 0)}, - {PF3, ADC_AINA14, PIN_DATA(0, 0)}, - {PF4, ADC_AINA15, PIN_DATA(0, 0)}, - {PF5, ADC_AINA16, PIN_DATA(0, 0)}, - {PF6, ADC_AINA17, PIN_DATA(0, 0)}, - {PF7, ADC_AINA18, PIN_DATA(0, 0)}, - {PD4, ADC_AINA19, PIN_DATA(0, 0)}, - {PD5, ADC_AINA20, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Check that pin belong to ADC module - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - obj->obj = TSB_ADA; - TSB_CG_FSYSENB_IPENB15 = ENABLE; // ADC CG Fsys Enable - TSB_CG_SPCLKEN_ADCKEN = ENABLE; // ADC Clock Enable - pinmap_pinout(pin, PinMap_ADC); // Set pin function as ADC - obj->obj->CLK = (ADC_SCLK_1 | ADC_SAMPLING_PERIOD_3V); // Set sample hold time and pre-scale clock - obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); - obj->obj->MOD1 = ADC_MOD1_AVDD5_3V; - obj->obj->MOD2 = ADC_MOD2_TMPM3Hx; -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t ADCResultValue = 0; - uint32_t ADCResultStored = 0; - - wait_us(300); // Wait at least 300us to ensure the voltage is stable - obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); // Disable Conversion - obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); // Enable Conversion - obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | - ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); - - while ((obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE) { - // Wait until AD conversion complete - } - - wait_us(30); // Wait for register to update with convert value. - ADCResultStored = (obj->obj->REG0 | obj->adc); // Convert result - - if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { - ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4); - } - - return ADCResultValue; -} - -float analogin_read(analogin_t *obj) -{ - float result = 0.0; - uint16_t value = 0; - - value = analogin_read_u16(obj); - result = ((float)value * (1.0f / (float)ADC_12BIT_RANGE)); - - return result; -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogout_api.c deleted file mode 100644 index c34cd15530..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogout_api.c +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogout_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "gpio_include.h" - -static const PinMap PinMap_DAC[] = { - {DAC0, DAC_A0, PIN_DATA(0, 3)}, - {DAC1, DAC_A1, PIN_DATA(0, 3)}, - {NC, NC, 0} -}; - -void analogout_init(dac_t *obj, PinName pin) -{ - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module - MBED_ASSERT(obj->dac != (DACName)NC); - - pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC - TSB_CG_FSYSENA_IPENA06 = ENABLE; - if (obj->dac == DAC_A0) { // Compute handler - obj->handler = TSB_DA0; - TSB_CG_FSYSENB_IPENB17 = ENABLE; - } else { - if (obj->dac == DAC_A1) { - obj->handler = TSB_DA1; - TSB_CG_FSYSENB_IPENB18 = ENABLE; - } else { - obj->handler = NULL; - } - } - obj->handler->CTL = DAC_STOP; -} - -void analogout_free(dac_t *obj) -{ - obj->handler->CTL = DAC_STOP; -} - -void analogout_write(dac_t *obj, float value) -{ - uint8_t outputcode = 0; - - // Enable DAC - obj->handler->CTL = DAC_START; - - if (value < 0.0f) { - value = 0.0f; - } else { - if (value >= 1.0f) { - value = 1.0f; - } - } - - outputcode = (uint8_t)(value * 255.0f); - obj->handler->REG = outputcode; - wait_ms(3); -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - // Enable DAC - obj->handler->CTL = DAC_START; - obj->handler->REG = (uint8_t)(value & 0xFF); - wait_ms(3); -} - -float analogout_read(dac_t *obj) -{ - float result = 0.0; - uint32_t value = 0; - - value = ((obj->handler->REG) & (0xFF)); - result = ((float)value / 255.0f); - - return result; -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - uint16_t value = 0; - - value = (uint16_t)((obj->handler->REG) & (0xFF)); - - return value; -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/crc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/crc_api.c deleted file mode 100644 index 0250d5e57c..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/crc_api.c +++ /dev/null @@ -1,74 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "crc_api.h" -#include "device.h" - -#ifdef DEVICE_CRC - -static bool reflect_in; -static bool reflect_out; -static uint32_t final_xor; - -void hal_crc_compute_partial_start(const crc_mbed_config_t *config) -{ - TSB_CG_FSYSENB_IPENB20 = 1; - - // Intial Value as initial_xor - TSB_CRC->CLC = config->initial_xor; - reflect_in = config->reflect_in; - reflect_out = config->reflect_out; - final_xor = config->final_xor; - - // Data width setting CRC data width is 8 bits (--01) - // Form setting CRC form is CRC16 (00--) or CRC32 (11--) - TSB_CRC->TYP = config->width == 16 ? 0x01 : 0x0D; -} - -void hal_crc_compute_partial(const uint8_t *data, const size_t size) -{ - if (data && size) { - uint32_t index = 0U; - bool reflect = reflect_in; - for(index = 0U; index < size; index++) { - unsigned int byte = data[index]; - if (reflect) { - byte = __RBIT(byte) >> 24; - } - TSB_CRC->DIN = byte; - } - } -} - -uint32_t hal_crc_get_result(void) -{ - uint32_t result; - - // Note: Please read [CRCCLC] twice and use the result of the 2nd time - result = TSB_CRC->CLC; - result = TSB_CRC->CLC; - if (reflect_out) { - result = __RBIT(result); - if ((TSB_CRC->TYP & 0x0C) == 0) { - result >>= 16; - } - } - result ^= final_xor; - - return (result); -} -#endif // DEVICE_CRC diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device.h deleted file mode 100644 index 53fa475078..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device.h +++ /dev/null @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 32 -#define TRANSACTION_QUEUE_SIZE_SPI 4 - -#include "objects.h" - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TMPM3HQ.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TMPM3HQ.h deleted file mode 100644 index 0aaef3e355..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TMPM3HQ.h +++ /dev/null @@ -1,4539 +0,0 @@ -/** - ******************************************************************************* - * @file TMPM3HQ.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3HQ' Device Series - * @version V1.0.0.1 - * $Date:: 2017-12-27 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER - * @{ - */ - -/** @addtogroup TMPM3HQ - * @{ - */ - -#ifndef __TMPM3HQ_H__ -#define __TMPM3HQ_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** TMPM3HQ Specific Interrupt Numbers *******************************************************************/ - INT00_IRQn = 0, /*!< Interrupt Pin 00 */ - INT01_IRQn = 1, /*!< Interrupt Pin 01 */ - INT02_IRQn = 2, /*!< Interrupt Pin 02 */ - INT03_IRQn = 3, /*!< Interrupt Pin 03 */ - INT04_IRQn = 4, /*!< Interrupt Pin 04 */ - INT05_IRQn = 5, /*!< Interrupt Pin 05 */ - INT06_IRQn = 6, /*!< Interrupt Pin 06 */ - INT07_IRQn = 7, /*!< Interrupt Pin 07 */ - INT08_IRQn = 8, /*!< Interrupt Pin 08 */ - INT09_IRQn = 9, /*!< Interrupt Pin 09 */ - INT10_IRQn = 10, /*!< Interrupt Pin 10 */ - INT11_IRQn = 11, /*!< Interrupt Pin 11 */ - INT12_IRQn = 12, /*!< Interrupt Pin 12 */ - INT13_IRQn = 13, /*!< Interrupt Pin 13 */ - INT14_IRQn = 14, /*!< Interrupt Pin 14 */ - INT15_IRQn = 15, /*!< Interrupt Pin 15 */ - INT16_IRQn = 16, /*!< Interrupt Pin 16 */ - INT17_18_IRQn = 17, /*!< Interrupt Pin 17_18 */ - INT19_22_IRQn = 18, /*!< Interrupt Pin 19_22 */ - INT23_26_IRQn = 19, /*!< Interrupt Pin 23_26 */ - INT27_28_IRQn = 20, /*!< Interrupt Pin 27_28 */ - INT29_IRQn = 21, /*!< Interrupt Pin 29 */ - INT30_31_IRQn = 22, /*!< Interrupt Pin 30_31 */ - INTEMG0_IRQn = 23, /*!< PMD0 EMG interrupt */ - INTOVV0_IRQn = 24, /*!< PMD0 OVV interrupt */ - INTPMD0_IRQn = 25, /*!< PMD0 interrupt */ - INTENC00_IRQn = 26, /*!< Encoder 0 interrupt 0 */ - INTENC01_IRQn = 27, /*!< Encoder 0 interrupt 1 */ - INTADAPDA_IRQn = 28, /*!< ADC conversion triggered by PMD is finished A */ - INTADAPDB_IRQn = 29, /*!< ADC conversion triggered by PMD is finished B */ - INTADACP0_IRQn = 30, /*!< ADC conversion monitoring function interrupt 0 */ - INTADACP1_IRQn = 31, /*!< ADC conversion monitoring function interrupt 1 */ - INTADATRG_IRQn = 32, /*!< ADC conversion triggered by General purpose is finished */ - INTADASGL_IRQn = 33, /*!< ADC conversion triggered by Single program is finished */ - INTADACNT_IRQn = 34, /*!< ADC conversion triggered by Continuity program is finished */ - INTT0RX_IRQn = 35, /*!< TSPI/SIO reception (channel 0) */ - INTT0TX_IRQn = 36, /*!< TSPI/SIO transmit (channel 0) */ - INTT0ERR_IRQn = 37, /*!< TSPI/SIO error (channel 0) */ - INTT1RX_IRQn = 38, /*!< TSPI/SIO reception (channel 1) */ - INTT1TX_IRQn = 39, /*!< TSPI/SIO transmit (channel 1) */ - INTT1ERR_IRQn = 40, /*!< TSPI/SIO error (channel 1) */ - INTT2RX_IRQn = 41, /*!< TSPI/SIO reception (channel 2) */ - INTT2TX_IRQn = 42, /*!< TSPI/SIO transmit (channel 2) */ - INTT2ERR_IRQn = 43, /*!< TSPI/SIO error (channel 2) */ - INTT3RX_IRQn = 44, /*!< TSPI/SIO reception (channel 3) */ - INTT3TX_IRQn = 45, /*!< TSPI/SIO transmit (channel 3) */ - INTT3ERR_IRQn = 46, /*!< TSPI/SIO error (channel 3) */ - INTT4RX_IRQn = 47, /*!< TSPI/SIO reception (channel 4) */ - INTT4TX_IRQn = 48, /*!< TSPI/SIO transmit (channel 4) */ - INTT4ERR_IRQn = 49, /*!< TSPI/SIO error (channel 4) */ - INTI2CWUP_IRQn = 50, /*!< Serial bus interface (WakeUp) interrupt (channel 0) */ - INTI2C0_IRQn = 51, /*!< I2C0 transmission and reception interrupt */ - INTI2C0AL_IRQn = 52, /*!< I2C0 arbitration lost interrupt */ - INTI2C0BF_IRQn = 53, /*!< I2C0 bus free interrupt */ - INTI2C0NA_IRQn = 54, /*!< I2C0 no ack interrupt */ - INTI2C1_IRQn = 55, /*!< I2C1 transmission and reception interrupt */ - INTI2C1AL_IRQn = 56, /*!< I2C1 arbitration lost interrupt */ - INTI2C1BF_IRQn = 57, /*!< I2C1 bus free interrupt */ - INTI2C1NA_IRQn = 58, /*!< I2C1 no ack interrupt */ - INTI2C2_IRQn = 59, /*!< I2C2 transmission and reception interrupt */ - INTI2C2AL_IRQn = 60, /*!< I2C2 arbitration lost interrupt */ - INTI2C2BF_IRQn = 61, /*!< I2C2 bus free interrupt */ - INTI2C2NA_IRQn = 62, /*!< I2C2 no ack interrupt */ - INTI2C3_IRQn = 63, /*!< I2C3 transmission and reception interrupt */ - INTI2C3AL_IRQn = 64, /*!< I2C3 arbitration lost interrupt */ - INTI2C3BF_IRQn = 65, /*!< I2C3 bus free interrupt */ - INTI2C3NA_IRQn = 66, /*!< I2C3 no ack interrupt */ - INTUART0RX_IRQn = 67, /*!< UART reception (channel 0) */ - INTUART0TX_IRQn = 68, /*!< UART transmit (channel 0) */ - INTUART0ERR_IRQn = 69, /*!< UART error (channel 0) */ - INTUART1RX_IRQn = 70, /*!< UART reception (channel 1) */ - INTUART1TX_IRQn = 71, /*!< UART transmit (channel 1) */ - INTUART1ERR_IRQn = 72, /*!< UART error (channel 1) */ - INTUART2RX_IRQn = 73, /*!< UART reception (channel 2) */ - INTUART2TX_IRQn = 74, /*!< UART transmit (channel 2) */ - INTUART2ERR_IRQn = 75, /*!< UART error (channel 2) */ - INTUART3RX_IRQn = 76, /*!< UART reception (channel 3) */ - INTUART3TX_IRQn = 77, /*!< UART transmit (channel 3) */ - INTUART3ERR_IRQn = 78, /*!< UART error (channel 3) */ - INTUART4RX_IRQn = 79, /*!< UART reception (channel 4) */ - INTUART4TX_IRQn = 80, /*!< UART transmit (channel 4) */ - INTUART4ERR_IRQn = 81, /*!< UART error (channel 4) */ - INTUART5RX_IRQn = 82, /*!< UART reception (channel 5) */ - INTUART5TX_IRQn = 83, /*!< UART transmit (channel 5) */ - INTUART5ERR_IRQn = 84, /*!< UART error (channel 5) */ - INTT32A00A_IRQn = 85, /*!< 32bit T32A00A compare match detection 0 / Over flow / under flow*/ - INTT32A00ACAP0_IRQn = 86, /*!< 32bit T32A00A input capture 0 */ - INTT32A00ACAP1_IRQn = 87, /*!< 32bit T32A00A input capture 1 */ - INTT32A00B_IRQn = 88, /*!< 32bit T32A00B compare match detection 0 / Over flow / under flow*/ - INTT32A00BCAP0_IRQn = 89, /*!< 32bit T32A00B input capture 0 */ - INTT32A00BCAP1_IRQn = 90, /*!< 32bit T32A00B input capture 1 */ - INTT32A00C_IRQn = 91, /*!< 32bit T32A00C compare match detection 0 / Over flow / under flow*/ - INTT32A00CCAP0_IRQn = 92, /*!< 32bit T32A00C input capture 0 */ - INTT32A00CCAP1_IRQn = 93, /*!< 32bit T32A00C input capture 1 */ - INTT32A01A_IRQn = 94, /*!< 32bit T32A01A compare match detection 0 / Over flow / under flow*/ - INTT32A01ACAP0_IRQn = 95, /*!< 32bit T32A01A input capture 0 */ - INTT32A01ACAP1_IRQn = 96, /*!< 32bit T32A01A input capture 1 */ - INTT32A01B_IRQn = 97, /*!< 32bit T32A01B compare match detection 0 / Over flow / under flow*/ - INTT32A01BCAP0_IRQn = 98, /*!< 32bit T32A01B input capture 0 */ - INTT32A01BCAP1_IRQn = 99, /*!< 32bit T32A01B input capture 1 */ - INTT32A01C_IRQn = 100, /*!< 32bit T32A01C compare match detection 0 / Over flow / under flow*/ - INTT32A01CCAP0_IRQn = 101, /*!< 32bit T32A01C input capture 0 */ - INTT32A01CCAP1_IRQn = 102, /*!< 32bit T32A01C input capture 1 */ - INTT32A02A_IRQn = 103, /*!< 32bit T32A02A compare match detection 0 / Over flow / under flow*/ - INTT32A02ACAP0_IRQn = 104, /*!< 32bit T32A02A input capture 0 */ - INTT32A02ACAP1_IRQn = 105, /*!< 32bit T32A02A input capture 1 */ - INTT32A02B_IRQn = 106, /*!< 32bit T32A02B compare match detection 0 / Over flow / under flow*/ - INTT32A02BCAP0_IRQn = 107, /*!< 32bit T32A02B input capture 0 */ - INTT32A02BCAP1_IRQn = 108, /*!< 32bit T32A02B input capture 1 */ - INTT32A02C_IRQn = 109, /*!< 32bit T32A02C compare match detection 0 / Over flow / under flow*/ - INTT32A02CCAP0_IRQn = 110, /*!< 32bit T32A02C input capture 0 */ - INTT32A02CCAP1_IRQn = 111, /*!< 32bit T32A02C input capture 1 */ - INTT32A03A_IRQn = 112, /*!< 32bit T32A03A compare match detection 0 / Over flow / under flow*/ - INTT32A03ACAP0_IRQn = 113, /*!< 32bit T32A03A input capture 0 */ - INTT32A03ACAP1_IRQn = 114, /*!< 32bit T32A03A input capture 1 */ - INTT32A03B_IRQn = 115, /*!< 32bit T32A03B compare match detection 0 / Over flow / under flow*/ - INTT32A03BCAP0_IRQn = 116, /*!< 32bit T32A03B input capture 0 */ - INTT32A03BCAP1_IRQn = 117, /*!< 32bit T32A03B input capture 1 */ - INTT32A03C_IRQn = 118, /*!< 32bit T32A03C compare match detection 0 / Over flow / under flow*/ - INTT32A03CCAP0_IRQn = 119, /*!< 32bit T32A03C input capture 0 */ - INTT32A03CCAP1_IRQn = 120, /*!< 32bit T32A03C input capture 1 */ - INTT32A04A_IRQn = 121, /*!< 32bit T32A04A compare match detection 0 / Over flow / under flow*/ - INTT32A04ACAP0_IRQn = 122, /*!< 32bit T32A04A input capture 0 */ - INTT32A04ACAP1_IRQn = 123, /*!< 32bit T32A04A input capture 1 */ - INTT32A04B_IRQn = 124, /*!< 32bit T32A04B compare match detection 0 / Over flow / under flow*/ - INTT32A04BCAP0_IRQn = 125, /*!< 32bit T32A04B input capture 0 */ - INTT32A04BCAP1_IRQn = 126, /*!< 32bit T32A04B input capture 1 */ - INTT32A04C_IRQn = 127, /*!< 32bit T32A04C compare match detection 0 / Over flow / under flow*/ - INTT32A04CCAP0_IRQn = 128, /*!< 32bit T32A04C input capture 0 */ - INTT32A04CCAP1_IRQn = 129, /*!< 32bit T32A04C input capture 1 */ - INTT32A05A_IRQn = 130, /*!< 32bit T32A05A compare match detection 0 / Over flow / under flow*/ - INTT32A05ACAP0_IRQn = 131, /*!< 32bit T32A05A input capture 0 */ - INTT32A05ACAP1_IRQn = 132, /*!< 32bit T32A05A input capture 1 */ - INTT32A05B_IRQn = 133, /*!< 32bit T32A05B compare match detection 0 / Over flow / under flow*/ - INTT32A05BCAP0_IRQn = 134, /*!< 32bit T32A05B input capture 0 */ - INTT32A05BCAP1_IRQn = 135, /*!< 32bit T32A05B input capture 1 */ - INTT32A05C_IRQn = 136, /*!< 32bit T32A05C compare match detection 0 / Over flow / under flow*/ - INTT32A05CCAP0_IRQn = 137, /*!< 32bit T32A05C input capture 0 */ - INTT32A05CCAP1_IRQn = 138, /*!< 32bit T32A05C input capture 1 */ - INTT32A06A_IRQn = 139, /*!< 32bit T32A06A compare match detection 0 / Over flow / under flow*/ - INTT32A06ACAP0_IRQn = 140, /*!< 32bit T32A06A input capture 0 */ - INTT32A06ACAP1_IRQn = 141, /*!< 32bit T32A06A input capture 1 */ - INTT32A06B_IRQn = 142, /*!< 32bit T32A06B compare match detection 0 / Over flow / under flow*/ - INTT32A06BCAP0_IRQn = 143, /*!< 32bit T32A06B input capture 0 */ - INTT32A06BCAP1_IRQn = 144, /*!< 32bit T32A06B input capture 1 */ - INTT32A06C_IRQn = 145, /*!< 32bit T32A06C compare match detection 0 / Over flow / under flow*/ - INTT32A06CCAP0_IRQn = 146, /*!< 32bit T32A06C input capture 0 */ - INTT32A06CCAP1_IRQn = 147, /*!< 32bit T32A06C input capture 1 */ - INTT32A07A_IRQn = 148, /*!< 32bit T32A07A compare match detection 0 / Over flow / under flow*/ - INTT32A07ACAP0_IRQn = 149, /*!< 32bit T32A07A input capture 0 */ - INTT32A07ACAP1_IRQn = 150, /*!< 32bit T32A07A input capture 1 */ - INTT32A07B_IRQn = 151, /*!< 32bit T32A07B compare match detection 0 / Over flow / under flow*/ - INTT32A07BCAP0_IRQn = 152, /*!< 32bit T32A07B input capture 0 */ - INTT32A07BCAP1_IRQn = 153, /*!< 32bit T32A07B input capture 1 */ - INTT32A07C_IRQn = 154, /*!< 32bit T32A07C compare match detection 0 / Over flow / under flow*/ - INTT32A07CCAP0_IRQn = 155, /*!< 32bit T32A07C input capture 0 */ - INTT32A07CCAP1_IRQn = 156, /*!< 32bit T32A07C input capture 1 */ - INTPARI_IRQn = 157, /*!< RAM parity interrupt */ - INTDMAATC_IRQn = 158, /*!< DMAA end of transfer */ - INTDMAAERR_IRQn = 159, /*!< DMAA transfer error */ - INTDMABTC_IRQn = 160, /*!< DMAB end of transfer */ - INTDMABERR_IRQn = 161, /*!< DMAB transfer error */ - INTRTC_IRQn = 162, /*!< Real time clock interrupt */ - INTRMC0_IRQn = 163, /*!< Remote control reception interrupt */ - INTFLCRDY_IRQn = 164, /*!< Code FLASH Ready interrupt */ - INTFLDRDY_IRQn = 165 /*!< Data FLASH Ready interrupt */ -} IRQn_Type; - -/** Processor and Core Peripheral Section */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_TMPM3HQ.h" /* TMPM3HQ System */ - -/** @addtogroup Device_Peripheral_registers - * @{ - */ - -/** Device Specific Peripheral registers structures */ - -/** - * @brief Interrupt control A Register - */ -typedef struct -{ - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(A) 00 */ - uint8_t RESERVED0[31]; - __IO uint8_t IMC00; /*!< Interrupu Mode Control Register(A) 00 */ - __IO uint8_t IMC01; /*!< Interrupu Mode Control Register(A) 01 */ - __IO uint8_t IMC02; /*!< Interrupu Mode Control Register(A) 02 */ - __IO uint8_t IMC03; /*!< Interrupu Mode Control Register(A) 03 */ - uint8_t RESERVED1[12]; - __IO uint8_t IMC16; /*!< Interrupu Mode Control Register(A) 16 */ - __IO uint8_t IMC17; /*!< Interrupu Mode Control Register(A) 17 */ -} TSB_IA_TypeDef; - -/** - * @brief Reset LOSC Management register - */ -typedef struct -{ - __IO uint8_t LOSCCR; /*!< Low OSC Control Register */ - __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ - __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ - __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ - uint8_t RESERVED0[11]; - __IO uint8_t PROTECT; /*!< Protect Register */ -} TSB_RLM_TypeDef; - -/** - * @brief I2C Wakeup control register - */ -typedef struct -{ - __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ - __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ - __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ - __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ -} TSB_I2CS_TypeDef; - -/** - * @brief LVD0 - */ -typedef struct -{ - __IO uint8_t CR; /*!< LVD Control register */ -} TSB_LVD_TypeDef; - -/** - * @brief DMA Controller - */ -typedef struct -{ - __I uint32_t STATUS; /*!< DMA Status Register */ - __O uint32_t CFG; /*!< DMA Configuration Register */ - __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ - __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base -Pointer Register*/ - uint32_t RESERVED0; - __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ - __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ - __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ - __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ - __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ - __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ - __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ - __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ - __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ - __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ - __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ - uint32_t RESERVED1[3]; - __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ -} TSB_DMA_TypeDef; - -/** - * @brief Digital analog converter (DAC) - */ -typedef struct -{ - __IO uint32_t CTL; /*!< DAC Control Register */ - __IO uint32_t REG; /*!< DAC output Register */ -} TSB_DA_TypeDef; - -/** - * @brief Serial Interface (TSPI) - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TSPI Control Register 0 */ - __IO uint32_t CR1; /*!< TSPI Control Register 1 */ - __IO uint32_t CR2; /*!< TSPI Control Register 2 */ - __IO uint32_t CR3; /*!< TSPI Control Register 3 */ - __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ - __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ - __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ - uint32_t RESERVED0[57]; - __IO uint32_t DR; /*!< TSPI Data Register */ - uint32_t RESERVED1[63]; - __IO uint32_t SR; /*!< TSPI Status Register */ - __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ -} TSB_TSPI_TypeDef; - -#if defined ( __CC_ARM ) /* RealView Compiler */ -#pragma anon_unions -#elif (defined (__ICCARM__)) /* ICC Compiler */ -#pragma language=extended -#endif - -/** - * @brief I2C - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control Register 1 */ - __IO uint32_t DBR; /*!< I2C Data Buffer Register */ - __IO uint32_t AR; /*!< I2C Bus address Register */ -union { - __O uint32_t CR2; /*!< I2C Control Register 2 */ - __I uint32_t SR; /*!< I2C Status Register */ - }; - __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ - __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ - __IO uint32_t ST; /*!< I2C Interrupt Register */ - __IO uint32_t OP; /*!< I2C Optiononal Function register */ - __I uint32_t PM; /*!< I2C Bus Monitor register */ - __IO uint32_t AR2; /*!< I2C Second Slave address register */ -} TSB_I2C_TypeDef; - -/** - * @brief ADC - */ -typedef struct -{ - __IO uint32_t CR0; /*!< AD Control Register 0 */ - __IO uint32_t CR1; /*!< AD Control Register 1 */ - __I uint32_t ST; /*!< AD Status Register */ - __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ - __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ - __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ - __IO uint32_t MOD3; /*!< AD Mode Control Register 3 */ - __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ - __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ - __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ - __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ - __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ - uint32_t RESERVED0[3]; - __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ - __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ - __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ - __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ - __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ - __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ - __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ - __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ - __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ - __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ - __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ - __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ - __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ - __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ - __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ - __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ - __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ - __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ - __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ - __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ - __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register*/ - uint32_t RESERVED1[3]; - __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ - __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ - __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ - __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ - __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ - __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ - __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ - __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ - __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ - __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ - __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ - __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ - __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ - __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ - __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ - __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ - __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ - __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ - __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ - __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ - __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ - __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ - __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ - __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ - __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ - __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ - __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ - __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ - __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ - __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ - __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ - __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ - uint32_t RESERVED2[8]; - __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ - __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ - __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ - __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ - __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ - __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ - __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ - __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ - __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ - __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ - __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ - __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ - __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ - __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ - __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ - __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ - __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ - __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ - __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ - __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ - __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ - __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ - __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ - __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ -} TSB_AD_TypeDef; - -/** - * @brief T32A - */ -typedef struct -{ - __IO uint32_t MOD; /*!< T32A Mode Register */ - uint32_t RESERVED0[15]; - __IO uint32_t RUNA; /*!< T32A Run Register A */ - __IO uint32_t CRA; /*!< T32A Counter control Register A */ - __IO uint32_t CAPCRA; /*!< T32A Capture control Register A */ - __IO uint32_t OUTCRA0; /*!< T32A Output control Register A0 */ - __IO uint32_t OUTCRA1; /*!< T32A Output control Register A1 */ - __IO uint32_t STA; /*!< T32A Status Register A */ - __IO uint32_t IMA; /*!< T32A Interrupt mask Register A */ - __I uint32_t TMRA; /*!< T32A Counter capture Register A */ - __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ - __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ - __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ - __I uint32_t CAPA0; /*!< T32A Timer capturer A0 */ - __I uint32_t CAPA1; /*!< T32A Timer capturer A1 */ - __IO uint32_t DMAA; /*!< T32A DMA Request Enabl eRegister A */ - uint32_t RESERVED1[2]; - __IO uint32_t RUNB; /*!< T32A Run Register B */ - __IO uint32_t CRB; /*!< T32A Counter control Register B */ - __IO uint32_t CAPCRB; /*!< T32A Capture control Register B */ - __IO uint32_t OUTCRB0; /*!< T32A Output control Register B0 */ - __IO uint32_t OUTCRB1; /*!< T32A Output control Register B1 */ - __IO uint32_t STB; /*!< T32A Status Register B */ - __IO uint32_t IMB; /*!< T32A Interrupt mask Register B */ - __I uint32_t TMRB; /*!< T32A Counter capture Register B */ - __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ - __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ - __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ - __I uint32_t CAPB0; /*!< T32A Timer capturer B0 */ - __I uint32_t CAPB1; /*!< T32A Timer capturer B1 */ - __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ - uint32_t RESERVED2[2]; - __IO uint32_t RUNC; /*!< T32A Run Register C */ - __IO uint32_t CRC; /*!< T32A Counter control Register C */ - __IO uint32_t CAPCRC; /*!< T32A Capture control Register C */ - __IO uint32_t OUTCRC0; /*!< T32A Output control Register C0 */ - __IO uint32_t OUTCRC1; /*!< T32A Output control Register C1 */ - __IO uint32_t STC; /*!< T32A Status Register C */ - __IO uint32_t IMC; /*!< T32A Interrupt mask Register C */ - __I uint32_t TMRC; /*!< T32A Counter capture Register C */ - __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ - __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ - __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ - __I uint32_t CAPC0; /*!< T32A Timer capturer C0 */ - __I uint32_t CAPC1; /*!< T32A Timer capturer C1 */ - __IO uint32_t DMAC; /*!< T32A DMA Request Enabl eRegister C */ - __IO uint32_t PLSCR; /*!< T32A Pulse count control register */ -} TSB_T32A_TypeDef; - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t SWRST; /*!< UART Software reset register */ - __IO uint32_t CR0; /*!< UART Control register 0 */ - __IO uint32_t CR1; /*!< UART Control register 1 */ - __IO uint32_t CLK; /*!< UART Clock Control register */ - __IO uint32_t BRD; /*!< UART Baud rate register */ - __IO uint32_t TRANS; /*!< UART Transfer enable register */ - __IO uint32_t DR; /*!< UART Data register */ - __IO uint32_t SR; /*!< UART Status register */ - __IO uint32_t FIFOCLR; /*!< UART FIFO Clear register */ - __IO uint32_t ERR; /*!< UART Error register */ -} TSB_UART_TypeDef; - -/** - * @brief SIWD - */ -typedef struct -{ - __IO uint32_t PRO; /*!< SIWD Protect register */ - __IO uint32_t EN; /*!< SIWD Enable register */ - __O uint32_t CR; /*!< SIWD Control register */ - __IO uint32_t MOD; /*!< SIWD Mode register */ - __I uint32_t MONI; /*!< SIWD Monitor register */ - __IO uint32_t OSCCR; /*!< SIWD Oscillation control register */ -} TSB_SIWD_TypeDef; - -/** - * @brief DNF - */ -typedef struct -{ - __IO uint32_t CKCR; /*!< DNF clock Control register */ - __IO uint32_t ENCR; /*!< DNF Enable register */ -} TSB_DNF_TypeDef; - -/** - * @brief TRGSEL - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ - __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ - __IO uint32_t CR2; /*!< TSEL Control register 2 */ - __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ - __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ - __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ - __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ - __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ - __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ - __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ - __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ - __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ - __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ - __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ - __IO uint32_t CR14; /*!< TRGSEL Control register 14 */ - __IO uint32_t CR15; /*!< TRGSEL Control register 15 */ -} TSB_TSEL_TypeDef; - -/** - * @brief RAM Parity - */ -typedef struct -{ - __IO uint32_t CTL; /*!< RAMM Parity control register */ - __I uint32_t ST; /*!< RAMM Parity status register */ - __O uint32_t CLR; /*!< RAMM Parity status clear register */ - __I uint32_t EAD0; /*!< RAMM Parity Error address register 0 */ - __I uint32_t EAD1; /*!< RAMM Parity Error address register 1 */ - __I uint32_t EAD2; /*!< RAMM Parity Error address register 2 */ - __I uint32_t EAD3; /*!< RAMM Parity Error address register 3 */ -} TSB_RPAR_TypeDef; - -/** - * @brief CRC - */ -typedef struct -{ - __IO uint32_t DIN; /*!< CRC input data register */ - uint32_t RESERVED0[4]; - __IO uint32_t TYP; /*!< CRC data type register */ - uint32_t RESERVED1[5]; - __IO uint32_t CLC; /*!< CRC calculation result register */ -} TSB_CRC_TypeDef; - -/** - * @brief CMP - */ -typedef struct -{ - __IO uint32_t CTRLA; /*!< CMP control register A */ -} TSB_CMP_TypeDef; - -/** - * @brief Port A - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PA Data Register */ - __IO uint32_t CR; /*!< PA Control Register */ - __IO uint32_t FR1; /*!< PA Function Register 1 */ - __IO uint32_t FR2; /*!< PA Function Register 2 */ - __IO uint32_t FR3; /*!< PA Function Register 3 */ - __IO uint32_t FR4; /*!< PA Function Register 4 */ - __IO uint32_t FR5; /*!< PA Function Register 5 */ - __IO uint32_t FR6; /*!< PA Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PA Open Drain Control Register */ - __IO uint32_t PUP; /*!< PA Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PA Input Enable Control Register */ -} TSB_PA_TypeDef; - -/** - * @brief Port B - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PB Data Register */ - __IO uint32_t CR; /*!< PB Control Register */ - __IO uint32_t FR1; /*!< PB Function Register 1 */ - __IO uint32_t FR2; /*!< PB Function Register 2 */ - __IO uint32_t FR3; /*!< PB Function Register 3 */ - __IO uint32_t FR4; /*!< PB Function Register 4 */ - __IO uint32_t FR5; /*!< PB Function Register 5 */ - __IO uint32_t FR6; /*!< PB Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PB Open Drain Control Register */ - __IO uint32_t PUP; /*!< PB Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PB Input Enable Control Register */ -} TSB_PB_TypeDef; - -/** - * @brief Port C - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PC Data Register */ - __IO uint32_t CR; /*!< PC Control Register */ - __IO uint32_t FR1; /*!< PC Function Register 1 */ - __IO uint32_t FR2; /*!< PC Function Register 2 */ - __IO uint32_t FR3; /*!< PC Function Register 3 */ - __IO uint32_t FR4; /*!< PC Function Register 4 */ - __IO uint32_t FR5; /*!< PC Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PC Open Drain Control Register */ - __IO uint32_t PUP; /*!< PC Pull-up Control Register */ - __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PC Input Enable Control Register */ -} TSB_PC_TypeDef; - -/** - * @brief Port D - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PD Data Register */ - __IO uint32_t CR; /*!< PD Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PD Open Drain Control Register */ - __IO uint32_t PUP; /*!< PD Pull-up Control Register */ - __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PD Input Enable Control Register */ -} TSB_PD_TypeDef; - -/** - * @brief Port E - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PE Data Register */ - __IO uint32_t CR; /*!< PE Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PE Open Drain Control Register */ - __IO uint32_t PUP; /*!< PE Pull-up Control Register */ - __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PE Input Enable Control Register */ -} TSB_PE_TypeDef; - -/** - * @brief Port F - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PF Data Register */ - __IO uint32_t CR; /*!< PF Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PF Open Drain Control Register */ - __IO uint32_t PUP; /*!< PF Pull-up Control Register */ - __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PF Input Enable Control Register */ -} TSB_PF_TypeDef; - -/** - * @brief Port G - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PG Data Register */ - __IO uint32_t CR; /*!< PG Control Register */ - __IO uint32_t FR1; /*!< PG Function Register 1 */ - __IO uint32_t FR2; /*!< PG Function Register 2 */ - __IO uint32_t FR3; /*!< PG Function Register 3 */ - __IO uint32_t FR4; /*!< PG Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PG Open Drain Control Register */ - __IO uint32_t PUP; /*!< PG Pull-up Control Register */ - __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PG Input Enable Control Register */ -} TSB_PG_TypeDef; - -/** - * @brief Port H - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PH Data Register */ - __IO uint32_t CR; /*!< PH Control Register */ - __IO uint32_t FR1; /*!< PH Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PH Open Drain Control Register */ - __IO uint32_t PUP; /*!< PH Pull-up Control Register */ - __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PH Input Enable Control Register */ -} TSB_PH_TypeDef; - -/** - * @brief Port J - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PJ Data Register */ - __IO uint32_t CR; /*!< PJ Control Register */ - __IO uint32_t FR1; /*!< PJ Function Register 1 */ - __IO uint32_t FR2; /*!< PJ Function Register 2 */ - __IO uint32_t FR3; /*!< PJ Function Register 3 */ - __IO uint32_t FR4; /*!< PJ Function Register 4 */ - __IO uint32_t FR5; /*!< PJ Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PJ Open Drain Control Register */ - __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ - __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PJ Input Enable Control Register */ -} TSB_PJ_TypeDef; - -/** - * @brief Port K - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PK Data Register */ - __IO uint32_t CR; /*!< PK Control Register */ - __IO uint32_t FR1; /*!< PK Function Register 1 */ - __IO uint32_t FR2; /*!< PK Function Register 2 */ - __IO uint32_t FR3; /*!< PK Function Register 3 */ - __IO uint32_t FR4; /*!< PK Function Register 4 */ - __IO uint32_t FR5; /*!< PK Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PK Open Drain Control Register */ - __IO uint32_t PUP; /*!< PK Pull-up Control Register */ - __IO uint32_t PDN; /*!< PK Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PK Input Enable Control Register */ -} TSB_PK_TypeDef; - -/** - * @brief Port L - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PL Data Register */ - __IO uint32_t CR; /*!< PL Control Register */ - __IO uint32_t FR1; /*!< PL Function Register 1 */ - __IO uint32_t FR2; /*!< PL Function Register 2 */ - __IO uint32_t FR3; /*!< PL Function Register 3 */ - __IO uint32_t FR4; /*!< PL Function Register 4 */ - __IO uint32_t FR5; /*!< PL Function Register 4 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PL Open Drain Control Register */ - __IO uint32_t PUP; /*!< PL Pull-up Control Register */ - __IO uint32_t PDN; /*!< PL Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PL Input Enable Control Register */ -} TSB_PL_TypeDef; - -/** - * @brief Port M - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PM Data Register */ - __IO uint32_t CR; /*!< PM Control Register */ - __IO uint32_t FR1; /*!< PM Function Register 1 */ - __IO uint32_t FR2; /*!< PM Function Register 2 */ - __IO uint32_t FR3; /*!< PM Function Register 3 */ - __IO uint32_t FR4; /*!< PM Function Register 4 */ - __IO uint32_t FR5; /*!< PM Function Register 5 */ - __IO uint32_t FR6; /*!< PM Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PM Open Drain Control Register */ - __IO uint32_t PUP; /*!< PM Pull-up Control Register */ - __IO uint32_t PDN; /*!< PM Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PM Input Enable Control Register */ -} TSB_PM_TypeDef; - -/** - * @brief Port N - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PN Data Register */ - __IO uint32_t CR; /*!< PN Control Register */ - __IO uint32_t FR1; /*!< PN Function Register 1 */ - __IO uint32_t FR2; /*!< PN Function Register 2 */ - __IO uint32_t FR3; /*!< PN Function Register 3 */ - __IO uint32_t FR4; /*!< PN Function Register 4 */ - __IO uint32_t FR5; /*!< PN Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PN Open Drain Control Register */ - __IO uint32_t PUP; /*!< PN Pull-up Control Register */ - __IO uint32_t PDN; /*!< PN Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PN Input Enable Control Register */ -} TSB_PN_TypeDef; - -/** - * @brief Port P - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PP Data Register */ - __IO uint32_t CR; /*!< PP Control Register */ - __IO uint32_t FR1; /*!< PP Function Register 1 */ - __IO uint32_t FR2; /*!< PP Function Register 2 */ - __IO uint32_t FR3; /*!< PP Function Register 3 */ - __IO uint32_t FR4; /*!< PP Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PP Open Drain Control Register */ - __IO uint32_t PUP; /*!< PP Pull-up Control Register */ - __IO uint32_t PDN; /*!< PP Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PP Input Enable Control Register */ -} TSB_PP_TypeDef; - -/** - * @brief Port R - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PR Data Register */ - __IO uint32_t CR; /*!< PR Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t FR3; /*!< PR Function Register 3 */ - __IO uint32_t FR4; /*!< PR Function Register 4 */ - uint32_t RESERVED1[4]; - __IO uint32_t OD; /*!< PR Open Drain Control Register */ - __IO uint32_t PUP; /*!< PR Pull-up Control Register */ - __IO uint32_t PDN; /*!< PR Pull-Down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< PR Input Enable Control Register */ -} TSB_PR_TypeDef; - -/** - * @brief Port T - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PT Data Register */ - __IO uint32_t CR; /*!< PT Control Register */ - __IO uint32_t FR1; /*!< PT Function Register 1 */ - __IO uint32_t FR2; /*!< PT Function Register 2 */ - __IO uint32_t FR3; /*!< PT Function Register 3 */ - __IO uint32_t FR4; /*!< PT Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PT Open Drain Control Register */ - __IO uint32_t PUP; /*!< PT Pull-up Control Register */ - __IO uint32_t PDN; /*!< PT Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PT Input Enable Control Register */ -} TSB_PT_TypeDef; - -/** - * @brief Port U - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PU Data Register */ - __IO uint32_t CR; /*!< PU Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PU Open Drain Control Register */ - __IO uint32_t PUP; /*!< PU Pull-up Control Register */ - __IO uint32_t PDN; /*!< PU Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PU Input Enable Control Register */ -} TSB_PU_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PV Data Register */ - __IO uint32_t CR; /*!< PV Control Register */ - __IO uint32_t FR1; /*!< PV Function Register 1 */ - __IO uint32_t FR2; /*!< PV Function Register 2 */ - uint32_t RESERVED0[6]; - __IO uint32_t OD; /*!< PV Open Drain Control Register */ - __IO uint32_t PUP; /*!< PV Pull-up Control Register */ - __IO uint32_t PDN; /*!< PV Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PV Input Enable Control Register */ -} TSB_PV_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint8_t SECR; /*!< RTC Sec setting register */ - __IO uint8_t MINR; /*!< RTC Min settging register */ - __IO uint8_t HOURR; /*!< RTC Hour setting register */ - uint8_t RESERVED0; - __IO uint8_t DAYR; /*!< RTC Day setting register */ - __IO uint8_t DATER; /*!< RTC Date setting register */ - __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ - __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ - __IO uint8_t PAGER; /*!< RTC Page register */ - uint8_t RESERVED1[3]; - __IO uint8_t RESTR; /*!< RTC Reset register */ - uint8_t RESERVED2; - __IO uint8_t PROTECT; /*!< RTC protect register */ - __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ - __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ - __IO uint8_t ADJSIGN; /*!< RTC clock adjust sign register */ -} TSB_RTC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t EN; /*!< RMC Enable Register */ - __IO uint32_t REN; /*!< RMC Receive Enable Register */ - __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ - __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ - __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ - __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ - __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ - __I uint32_t RSTAT; /*!< RMC Receive Status Register */ - __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ - __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ - __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ - __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ -} TSB_RMC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t CR1; /*!< OFD Control Register 1 */ - __IO uint32_t CR2; /*!< OFD Control Register 2 */ - __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ - __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ - __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ - __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ - __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ - __I uint32_t STAT; /*!< OFD Status Register */ - __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ -} TSB_OFD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t PROTECT; /*!< CG Protect Register */ - __IO uint32_t OSCCR; /*!< CG Oscillation Control Register */ - __IO uint32_t SYSCR; /*!< CG System clock control register */ - __IO uint32_t STBYCR; /*!< CG Standby Control Register */ - __IO uint32_t SCOCR; /*!< CG SCOUT Control Register */ - uint32_t RESERVED0[3]; - __IO uint32_t PLL0SEL; /*!< CG PLL select register for fsys */ - uint32_t RESERVED1[3]; - __IO uint32_t WUPHCR; /*!< CG Warmup register for HOSC */ - __IO uint32_t WUPLCR; /*!< CG Low-speed oscillation warm-up register */ - uint32_t RESERVED2[6]; - __IO uint32_t FSYSENA; /*!< CG output control register A for fsys clock */ - __IO uint32_t FSYSENB; /*!< CG output control register B for fsys clock */ - __IO uint32_t FCEN; /*!< CG output control register for fc clock */ - __IO uint32_t SPCLKEN; /*!< CG Output control register for ADC AND TRACE CLOCK*/ -} TSB_CG_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t OSCPRO; /*!< TRM Protect register */ - __IO uint32_t OSCEN; /*!< TRM Enable register */ - __I uint32_t OSCINIT; /*!< TRM Initial trimming level monitor register */ - __IO uint32_t OSCSET; /*!< TRM Trimming level setting register */ -} TSB_TRM_TypeDef; - -/** - * @brief Interrupt control register B - */ -typedef struct -{ - uint8_t RESERVED0[16]; - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(B) 00 */ - uint8_t RESERVED1[79]; - __IO uint8_t IMC000; /*!< Interrupu Mode Control Register(B) 000 */ - __IO uint8_t IMC001; /*!< Interrupu Mode Control Register(B) 001 */ - __IO uint8_t IMC002; /*!< Interrupu Mode Control Register(B) 002 */ - __IO uint8_t IMC003; /*!< Interrupu Mode Control Register(B) 003 */ - __IO uint8_t IMC004; /*!< Interrupu Mode Control Register(B) 004 */ - __IO uint8_t IMC005; /*!< Interrupu Mode Control Register(B) 005 */ - __IO uint8_t IMC006; /*!< Interrupu Mode Control Register(B) 006 */ - __IO uint8_t IMC007; /*!< Interrupu Mode Control Register(B) 007 */ - __IO uint8_t IMC008; /*!< Interrupu Mode Control Register(B) 008 */ - __IO uint8_t IMC009; /*!< Interrupu Mode Control Register(B) 009 */ - __IO uint8_t IMC010; /*!< Interrupu Mode Control Register(B) 010 */ - __IO uint8_t IMC011; /*!< Interrupu Mode Control Register(B) 011 */ - __IO uint8_t IMC012; /*!< Interrupu Mode Control Register(B) 012 */ - __IO uint8_t IMC013; /*!< Interrupu Mode Control Register(B) 013 */ - __IO uint8_t IMC014; /*!< Interrupu Mode Control Register(B) 014 */ - __IO uint8_t IMC015; /*!< Interrupu Mode Control Register(B) 015 */ - __IO uint8_t IMC016; /*!< Interrupu Mode Control Register(B) 016 */ - __IO uint8_t IMC017; /*!< Interrupu Mode Control Register(B) 017 */ - __IO uint8_t IMC018; /*!< Interrupu Mode Control Register(B) 018 */ - __IO uint8_t IMC019; /*!< Interrupu Mode Control Register(B) 019 */ - __IO uint8_t IMC020; /*!< Interrupu Mode Control Register(B) 020 */ - __IO uint8_t IMC021; /*!< Interrupu Mode Control Register(B) 021 */ - __IO uint8_t IMC022; /*!< Interrupu Mode Control Register(B) 022 */ - __IO uint8_t IMC023; /*!< Interrupu Mode Control Register(B) 023 */ - __IO uint8_t IMC024; /*!< Interrupu Mode Control Register(B) 024 */ - __IO uint8_t IMC025; /*!< Interrupu Mode Control Register(B) 025 */ - __IO uint8_t IMC026; /*!< Interrupu Mode Control Register(B) 026 */ - __IO uint8_t IMC027; /*!< Interrupu Mode Control Register(B) 027 */ - __IO uint8_t IMC028; /*!< Interrupu Mode Control Register(B) 028 */ - __IO uint8_t IMC029; /*!< Interrupu Mode Control Register(B) 029 */ - __IO uint8_t IMC030; /*!< Interrupu Mode Control Register(B) 030 */ - __IO uint8_t IMC031; /*!< Interrupu Mode Control Register(B) 031 */ - __IO uint8_t IMC032; /*!< Interrupu Mode Control Register(B) 032 */ - __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ - __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ - __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ - __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ - __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ - __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ - __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ - __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ - __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ - __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ - __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ - __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ - __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ - __IO uint8_t IMC046; /*!< Interrupt Mode Control Register(B) 046 */ - __IO uint8_t IMC047; /*!< Interrupt Mode Control Register(B) 047 */ - __IO uint8_t IMC048; /*!< Interrupt Mode Control Register(B) 048 */ - __IO uint8_t IMC049; /*!< Interrupt Mode Control Register(B) 049 */ - __IO uint8_t IMC050; /*!< Interrupt Mode Control Register(B) 050 */ - __IO uint8_t IMC051; /*!< Interrupt Mode Control Register(B) 051 */ - __IO uint8_t IMC052; /*!< Interrupt Mode Control Register(B) 052 */ - __IO uint8_t IMC053; /*!< Interrupt Mode Control Register(B) 053 */ - __IO uint8_t IMC054; /*!< Interrupt Mode Control Register(B) 054 */ - __IO uint8_t IMC055; /*!< Interrupt Mode Control Register(B) 055 */ - __IO uint8_t IMC056; /*!< Interrupt Mode Control Register(B) 056 */ - __IO uint8_t IMC057; /*!< Interrupt Mode Control Register(B) 057 */ - __IO uint8_t IMC058; /*!< Interrupt Mode Control Register(B) 058 */ - __IO uint8_t IMC059; /*!< Interrupt Mode Control Register(B) 059 */ - __IO uint8_t IMC060; /*!< Interrupt Mode Control Register(B) 060 */ - __IO uint8_t IMC061; /*!< Interrupt Mode Control Register(B) 061 */ - __IO uint8_t IMC062; /*!< Interrupt Mode Control Register(B) 062 */ - __IO uint8_t IMC063; /*!< Interrupt Mode Control Register(B) 063 */ - __IO uint8_t IMC064; /*!< Interrupt Mode Control Register(B) 064 */ - __IO uint8_t IMC065; /*!< Interrupt Mode Control Register(B) 065 */ - __IO uint8_t IMC066; /*!< Interrupu Mode Control Register(B) 066 */ - __IO uint8_t IMC067; /*!< Interrupu Mode Control Register(B) 067 */ - __IO uint8_t IMC068; /*!< Interrupu Mode Control Register(B) 068 */ - __IO uint8_t IMC069; /*!< Interrupu Mode Control Register(B) 069 */ - __IO uint8_t IMC070; /*!< Interrupu Mode Control Register(B) 070 */ - __IO uint8_t IMC071; /*!< Interrupu Mode Control Register(B) 071 */ - __IO uint8_t IMC072; /*!< Interrupu Mode Control Register(B) 072 */ - __IO uint8_t IMC073; /*!< Interrupu Mode Control Register(B) 073 */ - __IO uint8_t IMC074; /*!< Interrupu Mode Control Register(B) 074 */ - __IO uint8_t IMC075; /*!< Interrupu Mode Control Register(B) 075 */ - __IO uint8_t IMC076; /*!< Interrupu Mode Control Register(B) 076 */ - __IO uint8_t IMC077; /*!< Interrupu Mode Control Register(B) 077 */ - __IO uint8_t IMC078; /*!< Interrupu Mode Control Register(B) 078 */ - __IO uint8_t IMC079; /*!< Interrupu Mode Control Register(B) 079 */ - __IO uint8_t IMC080; /*!< Interrupu Mode Control Register(B) 080 */ - __IO uint8_t IMC081; /*!< Interrupu Mode Control Register(B) 081 */ - __IO uint8_t IMC082; /*!< Interrupu Mode Control Register(B) 082 */ - __IO uint8_t IMC083; /*!< Interrupu Mode Control Register(B) 083 */ - __IO uint8_t IMC084; /*!< Interrupu Mode Control Register(B) 084 */ - __IO uint8_t IMC085; /*!< Interrupu Mode Control Register(B) 085 */ - __IO uint8_t IMC086; /*!< Interrupu Mode Control Register(B) 086 */ - __IO uint8_t IMC087; /*!< Interrupu Mode Control Register(B) 087 */ - __IO uint8_t IMC088; /*!< Interrupu Mode Control Register(B) 088 */ - __IO uint8_t IMC089; /*!< Interrupu Mode Control Register(B) 089 */ - __IO uint8_t IMC090; /*!< Interrupu Mode Control Register(B) 090 */ - __IO uint8_t IMC091; /*!< Interrupu Mode Control Register(B) 091 */ - __IO uint8_t IMC092; /*!< Interrupu Mode Control Register(B) 092 */ - __IO uint8_t IMC093; /*!< Interrupu Mode Control Register(B) 093 */ - __IO uint8_t IMC094; /*!< Interrupu Mode Control Register(B) 094 */ -} TSB_IB_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __I uint32_t FLGNMI; /*!< Interrupt Monitor Flag 0 */ - __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 */ - uint32_t RESERVED0; - __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 */ - __I uint32_t FLG4; /*!< NMI Interrupt Monitor Flag 4 */ - __I uint32_t FLG5; /*!< NMI Interrupt Monitor Flag 5 */ -} TSB_IMN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MDEN; /*!< PMD Enable Register */ - __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ - __IO uint32_t MDCR; /*!< PMD Control Register */ - __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ - __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ - __IO uint32_t RATE; /*!< PWM Frequency Register */ - __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ - __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ - __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ - uint32_t RESERVED0; - __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ - __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ - __O uint32_t EMGREL; /*!< PMD EMG Release Register */ - __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ - __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ - __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ - __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ - __IO uint32_t DTR; /*!< PMD Dead Time Register */ - __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ - __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ - __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ - __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ - __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ - __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ - __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ - __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ - __IO uint32_t VPWMPH; /*!< Phase difference setting of the V-phase PWM */ - __IO uint32_t WPWMPH; /*!< Phase difference setting of the W-phase PWM */ - __IO uint32_t MBUFCR; /*!< Update timing of the triple buffer */ - uint32_t RESERVED1; - __IO uint32_t DBGOUTCR; /*!< Debug output control */ -} TSB_PMD_TypeDef; - -/** - * @brief Encoder Input (ENC) - */ -typedef struct -{ - __IO uint32_t TNCR; /*!< ENC Control Register */ - __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ - __IO uint32_t INT; /*!< ENC INT Compare Register */ - __IO uint32_t CNT; /*!< ENC Counter/Capture Register */ - __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ - __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ - __I uint32_t STS; /*!< ENC Status Register */ - __IO uint32_t INPCR; /*!< ENC Input Process Cntrol Register */ - __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ - __I uint32_t INPMON; /*!< ENC Input Moniter Register */ - __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ - __IO uint32_t INTCR; /*!< ENC Interrupt Reqyest Control Register */ - __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ -} TSB_EN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - uint32_t RESERVED0[4]; - __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ - __IO uint32_t SSR; /*!< Flash Security Status Register */ - __O uint32_t KCR; /*!< Flash Key Code Register */ - uint32_t RESERVED1; - __IO uint32_t SR0; /*!< Flash Status Register 0 */ - uint32_t RESERVED2[3]; - __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ - __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ - uint32_t RESERVED3[4]; - __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ - uint32_t RESERVED4; - __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ - __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ - uint32_t RESERVED5[4]; - __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ - uint32_t RESERVED6[37]; - __I uint32_t SR1; /*!< Flash Status Register 1 */ - __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ - uint32_t RESERVED7[14]; - __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ - uint32_t RESERVED8; - __IO uint32_t CR; /*!< Flash Control Register */ - __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ - __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ - uint32_t RESERVED9; - __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ -} TSB_FC_TypeDef; - - -/* Memory map */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x20000000UL) -#define PERI_BASE (0x40000000UL) - - -#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) -#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) -#define TSB_I2CS_BASE (PERI_BASE + 0x003E800UL) -#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) -#define TSB_DMAA_BASE (PERI_BASE + 0x004C000UL) -#define TSB_DMAB_BASE (PERI_BASE + 0x004D000UL) -#define TSB_DA0_BASE (PERI_BASE + 0x0054000UL) -#define TSB_DA1_BASE (PERI_BASE + 0x0055000UL) -#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) -#define TSB_TSPI1_BASE (PERI_BASE + 0x0099000UL) -#define TSB_TSPI2_BASE (PERI_BASE + 0x009A000UL) -#define TSB_TSPI3_BASE (PERI_BASE + 0x009B000UL) -#define TSB_TSPI4_BASE (PERI_BASE + 0x009C000UL) -#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) -#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) -#define TSB_I2C2_BASE (PERI_BASE + 0x00A2000UL) -#define TSB_I2C3_BASE (PERI_BASE + 0x00A3000UL) -#define TSB_ADA_BASE (PERI_BASE + 0x00B8800UL) -#define TSB_T32A0_BASE (PERI_BASE + 0x00BA000UL) -#define TSB_T32A1_BASE (PERI_BASE + 0x00BA100UL) -#define TSB_T32A2_BASE (PERI_BASE + 0x00BA200UL) -#define TSB_T32A3_BASE (PERI_BASE + 0x00BA300UL) -#define TSB_T32A4_BASE (PERI_BASE + 0x00BA400UL) -#define TSB_T32A5_BASE (PERI_BASE + 0x00BA500UL) -#define TSB_T32A6_BASE (PERI_BASE + 0x00BA600UL) -#define TSB_T32A7_BASE (PERI_BASE + 0x00BA700UL) -#define TSB_UART0_BASE (PERI_BASE + 0x00BB000UL) -#define TSB_UART1_BASE (PERI_BASE + 0x00BB100UL) -#define TSB_UART2_BASE (PERI_BASE + 0x00BB200UL) -#define TSB_UART3_BASE (PERI_BASE + 0x00BB300UL) -#define TSB_UART4_BASE (PERI_BASE + 0x00BBD00UL) -#define TSB_UART5_BASE (PERI_BASE + 0x00BBE00UL) -#define TSB_SIWD0_BASE (PERI_BASE + 0x00BB400UL) -#define TSB_DNFA_BASE (PERI_BASE + 0x00BB600UL) -#define TSB_DNFB_BASE (PERI_BASE + 0x00BB700UL) -#define TSB_TSEL0_BASE (PERI_BASE + 0x00BB800UL) -#define TSB_TSEL1_BASE (PERI_BASE + 0x00BB900UL) -#define TSB_RPAR_BASE (PERI_BASE + 0x00BBB00UL) -#define TSB_CRC_BASE (PERI_BASE + 0x00BBC00UL) -#define TSB_CMP_BASE (PERI_BASE + 0x00BC100UL) -#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) -#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) -#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) -#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) -#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) -#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) -#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) -#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) -#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) -#define TSB_PK_BASE (PERI_BASE + 0x00C0900UL) -#define TSB_PL_BASE (PERI_BASE + 0x00C0A00UL) -#define TSB_PM_BASE (PERI_BASE + 0x00C0B00UL) -#define TSB_PN_BASE (PERI_BASE + 0x00C0C00UL) -#define TSB_PP_BASE (PERI_BASE + 0x00C0D00UL) -#define TSB_PR_BASE (PERI_BASE + 0x00C0E00UL) -#define TSB_PT_BASE (PERI_BASE + 0x00C0F00UL) -#define TSB_PU_BASE (PERI_BASE + 0x00C1000UL) -#define TSB_PV_BASE (PERI_BASE + 0x00C1100UL) -#define TSB_RTC_BASE (PERI_BASE + 0x00CC000UL) -#define TSB_RMC0_BASE (PERI_BASE + 0x00E7000UL) -#define TSB_OFD_BASE (PERI_BASE + 0x00F1000UL) -#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) -#define TSB_TRM_BASE (PERI_BASE + 0x00F3200UL) -#define TSB_IB_BASE (PERI_BASE + 0x00F4E00UL) -#define TSB_IMN_BASE (PERI_BASE + 0x00F4F00UL) -#define TSB_PMD0_BASE (PERI_BASE + 0x00F6000UL) -#define TSB_EN0_BASE (PERI_BASE + 0x00F7000UL) -#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) - - -/* Peripheral declaration */ -#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) -#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) -#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) -#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) -#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) -#define TSB_DMAB (( TSB_DMA_TypeDef *) TSB_DMAB_BASE) -#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) -#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) -#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) -#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) -#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) -#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) -#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) -#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) -#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) -#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) -#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) -#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) -#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) -#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) -#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) -#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) -#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) -#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) -#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) -#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) -#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) -#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) -#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) -#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) -#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) -#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) -#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) -#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) -#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) -#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) -#define TSB_TSEL1 (( TSB_TSEL_TypeDef *) TSB_TSEL1_BASE) -#define TSB_RPAR (( TSB_RPAR_TypeDef *) TSB_RPAR_BASE) -#define TSB_CRC (( TSB_CRC_TypeDef *) TSB_CRC_BASE) -#define TSB_CMP (( TSB_CMP_TypeDef *) TSB_CMP_BASE) -#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) -#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) -#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) -#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) -#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) -#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) -#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) -#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) -#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) -#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) -#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) -#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) -#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) -#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) -#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) -#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) -#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) -#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) -#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) -#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) -#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) -#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) -#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) -#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) -#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) -#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) -#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) -#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) - - -/* Bit-Band for Device Specific Peripheral Registers */ -#define BITBAND_OFFSET (0x02000000UL) -#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) -#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) - - - - - - - -/* DMA Controller */ -#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) -#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) -#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) - -#define TSB_DMAB_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAB->STATUS,0))) -#define TSB_DMAB_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAB->CFG,0))) -#define TSB_DMAB_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAB->ERRCLR,0))) - - -/* Digital analog converter (DAC) */ -#define TSB_DA0_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CTL,0))) - -#define TSB_DA1_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CTL,0))) - - -/* Serial Interface (TSPI) */ -#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) -#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) -#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) -#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) -#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) -#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) -#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) -#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) -#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) -#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) -#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) -#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) -#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) -#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) -#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) -#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) -#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) -#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) -#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) -#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) -#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) -#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) -#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) -#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) -#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) -#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) -#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) -#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) -#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) -#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) -#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) -#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) -#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) -#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) -#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) -#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) -#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) -#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) - -#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) -#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) -#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) -#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) -#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) -#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) -#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) -#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) -#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) -#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) -#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) -#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) -#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) -#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) -#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) -#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) -#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) -#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) -#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) -#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) -#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) -#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) -#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) -#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) -#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) -#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) -#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) -#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) -#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) -#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) -#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) -#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) -#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) -#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) -#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) -#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) -#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) -#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) - -#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) -#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) -#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) -#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) -#define TSB_TSPI2_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) -#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) -#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) -#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) -#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) -#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) -#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) -#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) -#define TSB_TSPI2_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,16))) -#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) -#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) -#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) -#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) -#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) -#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) -#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) -#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) -#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) -#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) -#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) -#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) -#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) -#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) -#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) -#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) -#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) -#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) -#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) -#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) -#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) -#define TSB_TSPI2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,0))) -#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) -#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) -#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) - -#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) -#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) -#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) -#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) -#define TSB_TSPI3_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) -#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) -#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) -#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) -#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) -#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) -#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) -#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) -#define TSB_TSPI3_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,16))) -#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) -#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) -#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) -#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) -#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) -#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) -#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) -#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) -#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) -#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) -#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) -#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) -#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) -#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) -#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) -#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) -#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) -#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) -#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) -#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) -#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) -#define TSB_TSPI3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,0))) -#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) -#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) -#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) - -#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) -#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) -#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) -#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) -#define TSB_TSPI4_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) -#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) -#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) -#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) -#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) -#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) -#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) -#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) -#define TSB_TSPI4_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,16))) -#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) -#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) -#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) -#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) -#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) -#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) -#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) -#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) -#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) -#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) -#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) -#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) -#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) -#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) -#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) -#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) -#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) -#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) -#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) -#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) -#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) -#define TSB_TSPI4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,0))) -#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) -#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) -#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) - - -/* I2C */ -#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) -#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) -#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) -#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) -#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) -#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) -#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) -#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) -#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) -#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) -#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) -#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) -#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) -#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) -#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) -#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) -#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) -#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) -#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) -#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) -#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) -#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) -#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) -#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) -#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) -#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) -#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) -#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) -#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) -#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) -#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) -#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) -#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) -#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) -#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) -#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) -#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) -#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) - -#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) -#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) -#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) -#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) -#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) -#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) -#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) -#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) -#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) -#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) -#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) -#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) -#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) -#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) -#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) -#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) -#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) -#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) -#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) -#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) -#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) -#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) -#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) -#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) -#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) -#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) -#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) -#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) -#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) -#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) -#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) -#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) -#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) -#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) -#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) -#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) -#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) -#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) - -#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) -#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) -#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) -#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) -#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) -#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) -#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) -#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) -#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) -#define TSB_I2C2_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) -#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) -#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) -#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) -#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) -#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) -#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) -#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) -#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) -#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) -#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) -#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) -#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) -#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) -#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) -#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) -#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) -#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) -#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) -#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) -#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) -#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) -#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) -#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) -#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) -#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) -#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) -#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) -#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) - -#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) -#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) -#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) -#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) -#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) -#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) -#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) -#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) -#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) -#define TSB_I2C3_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) -#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) -#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) -#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) -#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) -#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) -#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) -#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) -#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) -#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) -#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) -#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) -#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) -#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) -#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) -#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) -#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) -#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) -#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) -#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) -#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) -#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) -#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) -#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) -#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) -#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) -#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) -#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) -#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) - - -/* ADC */ -#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) -#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) -#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) -#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) -#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) -#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) -#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) -#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) -#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) -#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) -#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) -#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) -#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) -#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) -#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) -#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) -#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) -#define TSB_ADA_CMPCR0_COMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) -#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) -#define TSB_ADA_CMPCR1_COMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) -#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) -#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) -#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) -#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) -#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) -#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) -#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) -#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) -#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) -#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) -#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) -#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) -#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) -#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) -#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) -#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) -#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) -#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) -#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) -#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) -#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) -#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) -#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) -#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) -#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) -#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) -#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) -#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) -#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) -#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) -#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) -#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) -#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) -#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) -#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) -#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) -#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) -#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) -#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) -#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) -#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) -#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) -#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) -#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) -#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) -#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) -#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) -#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) -#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) -#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) -#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) -#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) -#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) -#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) -#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) -#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) -#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) -#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) -#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) -#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) -#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) -#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) -#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) -#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) -#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) -#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) -#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) -#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) -#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) -#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) -#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) -#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) -#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) -#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) -#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) -#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) -#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) -#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) -#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) -#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) -#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) -#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) -#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) -#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) -#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) -#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) -#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) -#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) -#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) -#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) -#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) -#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) -#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) -#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) -#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) -#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) -#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) -#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) -#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) -#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) -#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) -#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) -#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) -#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) -#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) -#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) -#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) -#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) -#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) -#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) -#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) -#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) -#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) -#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) -#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) -#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) -#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) -#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) -#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) -#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) -#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) -#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) -#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) -#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) -#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) -#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) -#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) -#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) -#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) -#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) -#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) -#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) -#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) -#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) -#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) -#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) -#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) -#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) -#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) -#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) -#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) -#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) -#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) -#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) -#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) -#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) -#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) -#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) -#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) -#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) -#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) -#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) -#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) -#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) -#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) -#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) -#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) -#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) -#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) -#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) -#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) -#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) -#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) -#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) - - -/* T32A */ -#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) -#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) -#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) -#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) -#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) -#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) -#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) -#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) -#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) -#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) -#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) -#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) -#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) -#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) -#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) -#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) -#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) -#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) -#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) -#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) -#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) -#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) -#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) -#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) -#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) -#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) -#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) -#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) -#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) -#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) -#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) -#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) -#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) -#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) -#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) -#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) -#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) -#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) -#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) -#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) -#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) -#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) -#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) -#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) -#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) -#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) -#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) -#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) -#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) -#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) -#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) -#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) -#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) -#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) - -#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) -#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) -#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) -#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) -#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) -#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) -#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) -#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) -#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) -#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) -#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) -#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) -#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) -#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) -#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) -#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) -#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) -#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) -#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) -#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) -#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) -#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) -#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) -#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) -#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) -#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) -#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) -#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) -#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) -#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) -#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) -#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) -#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) -#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) -#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) -#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) -#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) -#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) -#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) -#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) -#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) -#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) -#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) -#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) -#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) -#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) -#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) -#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) -#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) -#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) -#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) -#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) -#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) -#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) - -#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) -#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) -#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) -#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) -#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) -#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) -#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) -#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) -#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) -#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) -#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) -#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) -#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) -#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) -#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) -#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) -#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) -#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) -#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) -#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) -#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) -#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) -#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) -#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) -#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) -#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) -#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) -#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) -#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) -#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) -#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) -#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) -#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) -#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) -#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) -#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) -#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) -#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) -#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) -#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) -#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) -#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) -#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) -#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) -#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) -#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) -#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) -#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) -#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) -#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) -#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) -#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) -#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) -#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) - -#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) -#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) -#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) -#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) -#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) -#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) -#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) -#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) -#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) -#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) -#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) -#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) -#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) -#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) -#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) -#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) -#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) -#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) -#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) -#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) -#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) -#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) -#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) -#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) -#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) -#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) -#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) -#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) -#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) -#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) -#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) -#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) -#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) -#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) -#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) -#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) -#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) -#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) -#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) -#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) -#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) -#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) -#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) -#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) -#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) -#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) -#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) -#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) -#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) -#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) -#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) -#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) -#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) -#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) - -#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) -#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) -#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) -#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) -#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) -#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) -#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) -#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) -#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) -#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) -#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) -#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) -#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) -#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) -#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) -#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) -#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) -#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) -#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) -#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) -#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) -#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) -#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) -#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) -#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) -#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) -#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) -#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) -#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) -#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) -#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) -#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) -#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) -#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) -#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) -#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) -#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) -#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) -#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) -#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) -#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) -#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) -#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) -#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) -#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) -#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) -#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) -#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) -#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) -#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) -#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) -#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) -#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) -#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) - -#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) -#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) -#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) -#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) -#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) -#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) -#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) -#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) -#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) -#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) -#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) -#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) -#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) -#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) -#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) -#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) -#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) -#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) -#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) -#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) -#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) -#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) -#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) -#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) -#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) -#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) -#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) -#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) -#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) -#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) -#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) -#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) -#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) -#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) -#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) -#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) -#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) -#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) -#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) -#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) -#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) -#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) -#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) -#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) -#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) -#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) -#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) -#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) -#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) -#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) -#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) -#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) -#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) -#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) - -#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) -#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) -#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) -#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) -#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) -#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) -#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) -#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) -#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) -#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) -#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) -#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) -#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) -#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) -#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) -#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) -#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) -#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) -#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) -#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) -#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) -#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) -#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) -#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) -#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) -#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) -#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) -#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) -#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) -#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) -#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) -#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) -#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) -#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) -#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) -#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) -#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) -#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) -#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) -#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) -#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) -#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) -#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) -#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) -#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) -#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) -#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) -#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) -#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) -#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) -#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) -#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) -#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) -#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) - -#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) -#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) -#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) -#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) -#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) -#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) -#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) -#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) -#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) -#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) -#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) -#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) -#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) -#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) -#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) -#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) -#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) -#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) -#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) -#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) -#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) -#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) -#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) -#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) -#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) -#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) -#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) -#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) -#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) -#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) -#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) -#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) -#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) -#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) -#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) -#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) -#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) -#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) -#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) -#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) -#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) -#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) -#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) -#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) -#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) -#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) -#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) -#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) -#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) -#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) -#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) -#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) -#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) -#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) - - -/* UART */ -#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) -#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) -#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) -#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) -#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) -#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) -#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) -#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) -#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) -#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) -#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) -#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) -#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) -#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) -#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) -#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) -#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) -#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) -#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) -#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) -#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) -#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) -#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) -#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) -#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) -#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) -#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) -#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) -#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) -#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) -#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) -#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) -#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) -#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) -#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) -#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) -#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) -#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) -#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) -#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) -#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) -#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) - -#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) -#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) -#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) -#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) -#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) -#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) -#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) -#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) -#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) -#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) -#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) -#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) -#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) -#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) -#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) -#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) -#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) -#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) -#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) -#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) -#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) -#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) -#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) -#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) -#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) -#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) -#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) -#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) -#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) -#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) -#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) -#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) -#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) -#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) -#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) -#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) -#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) -#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) -#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) -#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) -#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) -#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) - -#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) -#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) -#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) -#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) -#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) -#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) -#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) -#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) -#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) -#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) -#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) -#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) -#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) -#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) -#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) -#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) -#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) -#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) -#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) -#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) -#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) -#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) -#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) -#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) -#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) -#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) -#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) -#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) -#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) -#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) -#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) -#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) -#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) -#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) -#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) -#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) -#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) -#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) -#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) -#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) -#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) -#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) - -#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) -#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) -#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) -#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) -#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) -#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) -#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) -#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) -#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) -#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) -#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) -#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) -#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) -#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) -#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) -#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) -#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) -#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) -#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) -#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) -#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) -#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) -#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) -#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) -#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) -#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) -#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) -#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) -#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) -#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) -#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) -#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) -#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) -#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) -#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) -#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) -#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) -#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) -#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) -#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) -#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) -#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) - -#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) -#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) -#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) -#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) -#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) -#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) -#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) -#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) -#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) -#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) -#define TSB_UART4_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,16))) -#define TSB_UART4_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,17))) -#define TSB_UART4_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,18))) -#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) -#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) -#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) -#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) -#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) -#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) -#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) -#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) -#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) -#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) -#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) -#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) -#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) -#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) -#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) -#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) -#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) -#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) -#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) -#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) -#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) -#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) -#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) -#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) -#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) -#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) -#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) -#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) -#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) - -#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) -#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) -#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) -#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) -#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) -#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) -#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) -#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) -#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) -#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) -#define TSB_UART5_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,16))) -#define TSB_UART5_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,17))) -#define TSB_UART5_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,18))) -#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) -#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) -#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) -#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) -#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) -#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) -#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) -#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) -#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) -#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) -#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) -#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) -#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) -#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) -#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) -#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) -#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) -#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) -#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) -#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) -#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) -#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) -#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) -#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) -#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) -#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) -#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) -#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) -#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) - - -/* SIWD */ -#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) -#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) -#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) -#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) -#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) - - -/* DNF */ -#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) -#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) -#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) -#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) -#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) -#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) -#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) -#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) -#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) -#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) -#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) -#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) -#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) -#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) -#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) -#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) - -#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) -#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) -#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) -#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) -#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) -#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) -#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) -#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) -#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) -#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) -#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) -#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) -#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) -#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) -#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) -#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) - - -/* TRGSEL */ -#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) -#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) -#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) -#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) -#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) -#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) -#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) -#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) -#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) -#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) -#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) -#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) -#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) -#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) -#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) -#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) -#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) -#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) -#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) -#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) -#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) -#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) -#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) -#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) -#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) -#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) -#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) -#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) -#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) -#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) -#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) -#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) -#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) -#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) -#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) -#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) -#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) -#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) -#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) -#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) -#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) -#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) -#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) -#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) -#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) -#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) -#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) -#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) -#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) -#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) -#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) -#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) -#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) -#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) -#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) -#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) -#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) -#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) -#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) -#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) -#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) -#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) -#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) -#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) -#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) -#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) -#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) -#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) -#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) -#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) -#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) -#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) -#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) -#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) -#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) -#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) -#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) -#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) -#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) -#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) -#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) -#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) -#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) -#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) -#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) -#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) -#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) -#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) -#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) -#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) -#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) -#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) -#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) -#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) -#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) -#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) -#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) -#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) -#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) -#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) -#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) -#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) -#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) -#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) -#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) -#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) -#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) -#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) -#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) -#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) -#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) -#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) -#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) -#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) -#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) -#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) -#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) -#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) -#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) -#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) -#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) -#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) -#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) -#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) -#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) -#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) -#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) -#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) -#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) -#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) -#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) -#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) -#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) -#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) -#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) -#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) -#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) -#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) -#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) -#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) -#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) -#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) -#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) -#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) -#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) -#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) -#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) -#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) -#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) -#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) -#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) -#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) -#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) -#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) -#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) -#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) -#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) -#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) -#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) -#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) -#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) -#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) -#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) -#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) -#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) -#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) -#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) -#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) -#define TSB_TSEL0_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,0))) -#define TSB_TSEL0_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,1))) -#define TSB_TSEL0_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,2))) -#define TSB_TSEL0_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,8))) -#define TSB_TSEL0_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,9))) -#define TSB_TSEL0_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,10))) -#define TSB_TSEL0_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,16))) -#define TSB_TSEL0_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,17))) -#define TSB_TSEL0_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,18))) -#define TSB_TSEL0_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,24))) -#define TSB_TSEL0_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,25))) -#define TSB_TSEL0_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,26))) -#define TSB_TSEL0_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,0))) -#define TSB_TSEL0_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,1))) -#define TSB_TSEL0_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,2))) -#define TSB_TSEL0_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,8))) -#define TSB_TSEL0_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,9))) -#define TSB_TSEL0_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,10))) -#define TSB_TSEL0_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,16))) -#define TSB_TSEL0_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,17))) -#define TSB_TSEL0_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,18))) -#define TSB_TSEL0_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,24))) -#define TSB_TSEL0_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,25))) -#define TSB_TSEL0_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,26))) - -#define TSB_TSEL1_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,0))) -#define TSB_TSEL1_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,1))) -#define TSB_TSEL1_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,2))) -#define TSB_TSEL1_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,8))) -#define TSB_TSEL1_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,9))) -#define TSB_TSEL1_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,10))) -#define TSB_TSEL1_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,16))) -#define TSB_TSEL1_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,17))) -#define TSB_TSEL1_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,18))) -#define TSB_TSEL1_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,24))) -#define TSB_TSEL1_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,25))) -#define TSB_TSEL1_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,26))) -#define TSB_TSEL1_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,0))) -#define TSB_TSEL1_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,1))) -#define TSB_TSEL1_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,2))) -#define TSB_TSEL1_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,8))) -#define TSB_TSEL1_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,9))) -#define TSB_TSEL1_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,10))) -#define TSB_TSEL1_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,16))) -#define TSB_TSEL1_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,17))) -#define TSB_TSEL1_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,18))) -#define TSB_TSEL1_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,24))) -#define TSB_TSEL1_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,25))) -#define TSB_TSEL1_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,26))) -#define TSB_TSEL1_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,0))) -#define TSB_TSEL1_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,1))) -#define TSB_TSEL1_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,2))) -#define TSB_TSEL1_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,8))) -#define TSB_TSEL1_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,9))) -#define TSB_TSEL1_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,10))) -#define TSB_TSEL1_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,16))) -#define TSB_TSEL1_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,17))) -#define TSB_TSEL1_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,18))) -#define TSB_TSEL1_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,24))) -#define TSB_TSEL1_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,25))) -#define TSB_TSEL1_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,26))) -#define TSB_TSEL1_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,0))) -#define TSB_TSEL1_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,1))) -#define TSB_TSEL1_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,2))) -#define TSB_TSEL1_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,8))) -#define TSB_TSEL1_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,9))) -#define TSB_TSEL1_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,10))) -#define TSB_TSEL1_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,16))) -#define TSB_TSEL1_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,17))) -#define TSB_TSEL1_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,18))) -#define TSB_TSEL1_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,24))) -#define TSB_TSEL1_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,25))) -#define TSB_TSEL1_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,26))) -#define TSB_TSEL1_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,0))) -#define TSB_TSEL1_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,1))) -#define TSB_TSEL1_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,2))) -#define TSB_TSEL1_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,8))) -#define TSB_TSEL1_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,9))) -#define TSB_TSEL1_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,10))) -#define TSB_TSEL1_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,16))) -#define TSB_TSEL1_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,17))) -#define TSB_TSEL1_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,18))) -#define TSB_TSEL1_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,24))) -#define TSB_TSEL1_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,25))) -#define TSB_TSEL1_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,26))) -#define TSB_TSEL1_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,0))) -#define TSB_TSEL1_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,1))) -#define TSB_TSEL1_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,2))) -#define TSB_TSEL1_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,8))) -#define TSB_TSEL1_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,9))) -#define TSB_TSEL1_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,10))) -#define TSB_TSEL1_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,16))) -#define TSB_TSEL1_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,17))) -#define TSB_TSEL1_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,18))) -#define TSB_TSEL1_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,24))) -#define TSB_TSEL1_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,25))) -#define TSB_TSEL1_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,26))) -#define TSB_TSEL1_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,0))) -#define TSB_TSEL1_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,1))) -#define TSB_TSEL1_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,2))) -#define TSB_TSEL1_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,8))) -#define TSB_TSEL1_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,9))) -#define TSB_TSEL1_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,10))) -#define TSB_TSEL1_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,16))) -#define TSB_TSEL1_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,17))) -#define TSB_TSEL1_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,18))) -#define TSB_TSEL1_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,24))) -#define TSB_TSEL1_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,25))) -#define TSB_TSEL1_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,26))) -#define TSB_TSEL1_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,0))) -#define TSB_TSEL1_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,1))) -#define TSB_TSEL1_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,2))) -#define TSB_TSEL1_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,8))) -#define TSB_TSEL1_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,9))) -#define TSB_TSEL1_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,10))) -#define TSB_TSEL1_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,16))) -#define TSB_TSEL1_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,17))) -#define TSB_TSEL1_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,18))) -#define TSB_TSEL1_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,24))) -#define TSB_TSEL1_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,25))) -#define TSB_TSEL1_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,26))) -#define TSB_TSEL1_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,0))) -#define TSB_TSEL1_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,1))) -#define TSB_TSEL1_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,2))) -#define TSB_TSEL1_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,8))) -#define TSB_TSEL1_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,9))) -#define TSB_TSEL1_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,10))) -#define TSB_TSEL1_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,16))) -#define TSB_TSEL1_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,17))) -#define TSB_TSEL1_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,18))) -#define TSB_TSEL1_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,24))) -#define TSB_TSEL1_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,25))) -#define TSB_TSEL1_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,26))) -#define TSB_TSEL1_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,0))) -#define TSB_TSEL1_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,1))) -#define TSB_TSEL1_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,2))) -#define TSB_TSEL1_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,8))) -#define TSB_TSEL1_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,9))) -#define TSB_TSEL1_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,10))) -#define TSB_TSEL1_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,16))) -#define TSB_TSEL1_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,17))) -#define TSB_TSEL1_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,18))) -#define TSB_TSEL1_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,24))) -#define TSB_TSEL1_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,25))) -#define TSB_TSEL1_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,26))) -#define TSB_TSEL1_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,0))) -#define TSB_TSEL1_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,1))) -#define TSB_TSEL1_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,2))) -#define TSB_TSEL1_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,8))) -#define TSB_TSEL1_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,9))) -#define TSB_TSEL1_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,10))) -#define TSB_TSEL1_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,16))) -#define TSB_TSEL1_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,17))) -#define TSB_TSEL1_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,18))) -#define TSB_TSEL1_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,24))) -#define TSB_TSEL1_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,25))) -#define TSB_TSEL1_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,26))) -#define TSB_TSEL1_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,0))) -#define TSB_TSEL1_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,1))) -#define TSB_TSEL1_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,2))) -#define TSB_TSEL1_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,8))) -#define TSB_TSEL1_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,9))) -#define TSB_TSEL1_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,10))) -#define TSB_TSEL1_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,16))) -#define TSB_TSEL1_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,17))) -#define TSB_TSEL1_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,18))) -#define TSB_TSEL1_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,24))) -#define TSB_TSEL1_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,25))) -#define TSB_TSEL1_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,26))) -#define TSB_TSEL1_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,0))) -#define TSB_TSEL1_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,1))) -#define TSB_TSEL1_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,2))) -#define TSB_TSEL1_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,8))) -#define TSB_TSEL1_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,9))) -#define TSB_TSEL1_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,10))) -#define TSB_TSEL1_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,16))) -#define TSB_TSEL1_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,17))) -#define TSB_TSEL1_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,18))) -#define TSB_TSEL1_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,24))) -#define TSB_TSEL1_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,25))) -#define TSB_TSEL1_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,26))) -#define TSB_TSEL1_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,0))) -#define TSB_TSEL1_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,1))) -#define TSB_TSEL1_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,2))) -#define TSB_TSEL1_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,8))) -#define TSB_TSEL1_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,9))) -#define TSB_TSEL1_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,10))) -#define TSB_TSEL1_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,16))) -#define TSB_TSEL1_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,17))) -#define TSB_TSEL1_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,18))) -#define TSB_TSEL1_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,24))) -#define TSB_TSEL1_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,25))) -#define TSB_TSEL1_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,26))) -#define TSB_TSEL1_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,0))) -#define TSB_TSEL1_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,1))) -#define TSB_TSEL1_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,2))) -#define TSB_TSEL1_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,8))) -#define TSB_TSEL1_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,9))) -#define TSB_TSEL1_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,10))) -#define TSB_TSEL1_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,16))) -#define TSB_TSEL1_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,17))) -#define TSB_TSEL1_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,18))) -#define TSB_TSEL1_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,24))) -#define TSB_TSEL1_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,25))) -#define TSB_TSEL1_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,26))) -#define TSB_TSEL1_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,0))) -#define TSB_TSEL1_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,1))) -#define TSB_TSEL1_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,2))) -#define TSB_TSEL1_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,8))) -#define TSB_TSEL1_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,9))) -#define TSB_TSEL1_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,10))) -#define TSB_TSEL1_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,16))) -#define TSB_TSEL1_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,17))) -#define TSB_TSEL1_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,18))) -#define TSB_TSEL1_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,24))) -#define TSB_TSEL1_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,25))) -#define TSB_TSEL1_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,26))) - - -/* RAM Parity */ -#define TSB_RPAR_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,0))) -#define TSB_RPAR_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,1))) -#define TSB_RPAR_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,0))) -#define TSB_RPAR_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,1))) -#define TSB_RPAR_ST_RPARFG2 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,2))) -#define TSB_RPAR_ST_RPARFG3 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,3))) -#define TSB_RPAR_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,0))) -#define TSB_RPAR_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,1))) -#define TSB_RPAR_CLR_RPARCLR2 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,2))) -#define TSB_RPAR_CLR_RPARCLR3 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,3))) - - - -/* CMP */ -#define TSB_CMP_CTRLA_CMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,0))) -#define TSB_CMP_CTRLA_CMPISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,1))) - - -/* Port A */ -#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) -#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) -#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) -#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) -#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) -#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) -#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) -#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) -#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) -#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) -#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) -#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) -#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) -#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) -#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) -#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) -#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) -#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) -#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) -#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) -#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) -#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) -#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) -#define TSB_PA_FR2_PA1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,1))) -#define TSB_PA_FR2_PA2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,2))) -#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) -#define TSB_PA_FR2_PA6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,6))) -#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) -#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) -#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) -#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) -#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) -#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) -#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) -#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) -#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) -#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) -#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) -#define TSB_PA_FR4_PA5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,5))) -#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) -#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) -#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) -#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) -#define TSB_PA_FR6_PA1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,1))) -#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) -#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) -#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) -#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) -#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) -#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) -#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) -#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) -#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) -#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) -#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) -#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) -#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) -#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) -#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) -#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) -#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) -#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) -#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) -#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) -#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) -#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) -#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) -#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) -#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) -#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) -#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) -#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) -#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) -#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) -#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) -#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) -#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) -#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) - - -/* Port B */ -#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) -#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) -#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) -#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) -#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) -#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) -#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) -#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) -#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) -#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) -#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) -#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) -#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) -#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) -#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) -#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) -#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) -#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) -#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) -#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) -#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) -#define TSB_PB_FR2_PB2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,2))) -#define TSB_PB_FR2_PB3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,3))) -#define TSB_PB_FR2_PB4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,4))) -#define TSB_PB_FR2_PB5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,5))) -#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) -#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) -#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) -#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) -#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) -#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) -#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) -#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) -#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) -#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) -#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) -#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) -#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) -#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) -#define TSB_PB_FR5_PB5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,5))) -#define TSB_PB_FR6_PB0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,0))) -#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) -#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) -#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) -#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) -#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) -#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) -#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) -#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) -#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) -#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) -#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) -#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) -#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) -#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) -#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) -#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) -#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) -#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) -#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) -#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) -#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) -#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) -#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) -#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) -#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) -#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) -#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) -#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) -#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) -#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) -#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) -#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) - - -/* Port C */ -#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) -#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) -#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) -#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) -#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) -#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) -#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) -#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) -#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) -#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) -#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) -#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) -#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) -#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) -#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) -#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) -#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) -#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) -#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) -#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) -#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) -#define TSB_PC_FR2_PC3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,3))) -#define TSB_PC_FR2_PC4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,4))) -#define TSB_PC_FR2_PC5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,5))) -#define TSB_PC_FR2_PC6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,6))) -#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) -#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) -#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) -#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) -#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) -#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) -#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) -#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) -#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) -#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) -#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) -#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) -#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) -#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) -#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) -#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) -#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) -#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) -#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) -#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) -#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) -#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) -#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) -#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) -#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) -#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) -#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) -#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) -#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) -#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) -#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) -#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) -#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) -#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) -#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) -#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) -#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) -#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) - - -/* Port D */ -#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) -#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) -#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) -#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) -#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) -#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) -#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) -#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) -#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) -#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) -#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) -#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) -#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) -#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) -#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) -#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) -#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) -#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) -#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) -#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) -#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) -#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) -#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) -#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) -#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) -#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) -#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) -#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) -#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) -#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) -#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) -#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) -#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) -#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) -#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) -#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) - - -/* Port E */ -#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) -#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) -#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) -#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) -#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) -#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) -#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) -#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) -#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) -#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) -#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) -#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) -#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) -#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) -#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) -#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) -#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) -#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) -#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) -#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) -#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) -#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) -#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) -#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) -#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) -#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) -#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) -#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) -#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) -#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) -#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) -#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) -#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) -#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) -#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) -#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) -#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) -#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) -#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) -#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) -#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) -#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) - - -/* Port F */ -#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) -#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) -#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) -#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) -#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) -#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) -#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) -#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) -#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) -#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) -#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) -#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) -#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) -#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) -#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) -#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) -#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) -#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) -#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) -#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) -#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) -#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) -#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) -#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) -#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) -#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) -#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) -#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) -#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) -#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) -#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) -#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) -#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) -#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) -#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) -#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) -#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) -#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) -#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) -#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) -#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) -#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) -#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) -#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) -#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) -#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) -#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) -#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) - - -/* Port G */ -#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) -#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) -#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) -#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) -#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) -#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) -#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) -#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) -#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) -#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) -#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) -#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) -#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) -#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) -#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) -#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) -#define TSB_PG_FR1_PG2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,2))) -#define TSB_PG_FR1_PG3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,3))) -#define TSB_PG_FR1_PG4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,4))) -#define TSB_PG_FR2_PG2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,2))) -#define TSB_PG_FR2_PG3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,3))) -#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) -#define TSB_PG_FR3_PG3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) -#define TSB_PG_FR3_PG4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,4))) -#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) -#define TSB_PG_FR3_PG6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,6))) -#define TSB_PG_FR3_PG7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,7))) -#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) -#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) -#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) -#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) -#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) -#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) -#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) -#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) -#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) -#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) -#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) -#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) -#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) -#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) -#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) -#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) -#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) -#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) -#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) -#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) -#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) -#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) -#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) -#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) -#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) -#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) -#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) -#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) -#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) -#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) -#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) -#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) -#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) -#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) -#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) - - -/* Port H */ -#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) -#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) -#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) -#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) -#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) -#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) -#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) -#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) -#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) -#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) -#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) -#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) -#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) -#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) -#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) -#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) -#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) -#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) -#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) -#define TSB_PH_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) -#define TSB_PH_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) -#define TSB_PH_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) -#define TSB_PH_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) -#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) -#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) -#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) -#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) -#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) -#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) -#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) -#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) -#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) -#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) -#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) -#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) -#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) -#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) -#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) -#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) - - -/* Port J */ -#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) -#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) -#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) -#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) -#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) -#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) -#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) -#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) -#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) -#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) -#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) -#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) -#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) -#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) -#define TSB_PJ_FR1_PJ2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,2))) -#define TSB_PJ_FR1_PJ3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,3))) -#define TSB_PJ_FR1_PJ4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,4))) -#define TSB_PJ_FR2_PJ1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,1))) -#define TSB_PJ_FR2_PJ2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,2))) -#define TSB_PJ_FR2_PJ3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,3))) -#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) -#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) -#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) -#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) -#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) -#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) -#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) -#define TSB_PJ_FR4_PJ0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,0))) -#define TSB_PJ_FR4_PJ1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,1))) -#define TSB_PJ_FR4_PJ2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,2))) -#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) -#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) -#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) -#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) -#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) -#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) -#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) -#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) -#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) -#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) -#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) -#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) -#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) -#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) -#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) -#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) -#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) -#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) -#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) -#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) -#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) -#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) -#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) -#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) -#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) -#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) -#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) -#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) -#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) -#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) - - -/* Port K */ -#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) -#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) -#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) -#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) -#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) -#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) -#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) -#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) -#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) -#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) -#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) -#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) -#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) -#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) -#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) -#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) -#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) -#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) -#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) -#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) -#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) -#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) -#define TSB_PK_FR2_PK2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,2))) -#define TSB_PK_FR2_PK3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,3))) -#define TSB_PK_FR2_PK4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,4))) -#define TSB_PK_FR3_PK2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,2))) -#define TSB_PK_FR3_PK3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,3))) -#define TSB_PK_FR3_PK4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,4))) -#define TSB_PK_FR3_PK5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,5))) -#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) -#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) -#define TSB_PK_FR4_PK2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,2))) -#define TSB_PK_FR4_PK3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,3))) -#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) -#define TSB_PK_FR5_PK0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,0))) -#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) -#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) -#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) -#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) -#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) -#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) -#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) -#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) -#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) -#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) -#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) -#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) -#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) -#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) -#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) -#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) -#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) -#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) -#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) -#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) -#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) -#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) -#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) -#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) -#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) -#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) -#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) -#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) -#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) -#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) -#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) -#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) -#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) - - -/* Port L */ -#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) -#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) -#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) -#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) -#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) -#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) -#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) -#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) -#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) -#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) -#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) -#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) -#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) -#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) -#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) -#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) -#define TSB_PL_FR1_PL0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,0))) -#define TSB_PL_FR1_PL1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,1))) -#define TSB_PL_FR1_PL2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,2))) -#define TSB_PL_FR1_PL3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,3))) -#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) -#define TSB_PL_FR2_PL1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,1))) -#define TSB_PL_FR2_PL2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,2))) -#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) -#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) -#define TSB_PL_FR3_PL1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,1))) -#define TSB_PL_FR3_PL2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,2))) -#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) -#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) -#define TSB_PL_FR3_PL5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,5))) -#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) -#define TSB_PL_FR3_PL7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,7))) -#define TSB_PL_FR4_PL5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,5))) -#define TSB_PL_FR4_PL6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,6))) -#define TSB_PL_FR4_PL7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,7))) -#define TSB_PL_FR5_PL0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,0))) -#define TSB_PL_FR5_PL1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1))) -#define TSB_PL_FR5_PL2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2))) -#define TSB_PL_FR5_PL3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3))) -#define TSB_PL_FR5_PL4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,4))) -#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) -#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) -#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) -#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) -#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) -#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) -#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) -#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) -#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) -#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) -#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) -#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) -#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) -#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) -#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) -#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) -#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) -#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) -#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) -#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) -#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) -#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) -#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) -#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) -#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) -#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) -#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) -#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) -#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) -#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) -#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) -#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) - - -/* Port M */ -#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) -#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) -#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) -#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) -#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) -#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) -#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) -#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) -#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) -#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) -#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) -#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) -#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) -#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) -#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) -#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) -#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) -#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) -#define TSB_PM_FR1_PM2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,2))) -#define TSB_PM_FR1_PM3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,3))) -#define TSB_PM_FR1_PM4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,4))) -#define TSB_PM_FR2_PM1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,1))) -#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) -#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) -#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) -#define TSB_PM_FR3_PM0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,0))) -#define TSB_PM_FR3_PM1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,1))) -#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) -#define TSB_PM_FR3_PM3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,3))) -#define TSB_PM_FR3_PM4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,4))) -#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) -#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) -#define TSB_PM_FR4_PM2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,2))) -#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) -#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) -#define TSB_PM_FR4_PM5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,5))) -#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) -#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) -#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) -#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) -#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) -#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) -#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) -#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) -#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) -#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) -#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) -#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) -#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) -#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) -#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) -#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) -#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) -#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) -#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) -#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) -#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) -#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) -#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) -#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) -#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) -#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) -#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) -#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) -#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) -#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) -#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) -#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) -#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) -#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) -#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) -#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) -#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) -#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) -#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) -#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) -#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) - - -/* Port N */ -#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) -#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) -#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) -#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) -#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) -#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) -#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) -#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) -#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) -#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) -#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) -#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) -#define TSB_PN_FR1_PN0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,0))) -#define TSB_PN_FR1_PN1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,1))) -#define TSB_PN_FR1_PN2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,2))) -#define TSB_PN_FR1_PN3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,3))) -#define TSB_PN_FR1_PN4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,4))) -#define TSB_PN_FR2_PN0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,0))) -#define TSB_PN_FR2_PN1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,1))) -#define TSB_PN_FR2_PN2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,2))) -#define TSB_PN_FR2_PN3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,3))) -#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) -#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) -#define TSB_PN_FR3_PN2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,2))) -#define TSB_PN_FR3_PN3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,3))) -#define TSB_PN_FR3_PN4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,4))) -#define TSB_PN_FR3_PN5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,5))) -#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) -#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) -#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) -#define TSB_PN_FR5_PN3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,3))) -#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) -#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) -#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) -#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) -#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) -#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) -#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) -#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) -#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) -#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) -#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) -#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) -#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) -#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) -#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) -#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) -#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) -#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) -#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) -#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) -#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) -#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) -#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) -#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) - - -/* Port P */ -#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) -#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) -#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) -#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) -#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) -#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) -#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) -#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) -#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) -#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) -#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) -#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) -#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) -#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) -#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) -#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) -#define TSB_PP_FR1_PP3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,3))) -#define TSB_PP_FR1_PP4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,4))) -#define TSB_PP_FR1_PP5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,5))) -#define TSB_PP_FR1_PP6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,6))) -#define TSB_PP_FR1_PP7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,7))) -#define TSB_PP_FR2_PP0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) -#define TSB_PP_FR2_PP1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) -#define TSB_PP_FR2_PP2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) -#define TSB_PP_FR2_PP6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) -#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) -#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) -#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) -#define TSB_PP_FR3_PP6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) -#define TSB_PP_FR4_PP0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,0))) -#define TSB_PP_FR4_PP1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,1))) -#define TSB_PP_FR4_PP2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,2))) -#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) -#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) -#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) -#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) -#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) -#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) -#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) -#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) -#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) -#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) -#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) -#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) -#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) -#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) -#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) -#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) -#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) -#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) -#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) -#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) -#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) -#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) -#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) -#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) -#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) -#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) -#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) -#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) -#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) -#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) -#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) -#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) - - -/* Port R */ -#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) -#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) -#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) -#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) -#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) -#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) -#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) -#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) -#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) -#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) -#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) -#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) -#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) -#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) -#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) -#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) -#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) -#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) -#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) -#define TSB_PR_FR4_PR0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,0))) -#define TSB_PR_FR4_PR1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,1))) -#define TSB_PR_FR4_PR2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,2))) -#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) -#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) -#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) -#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) -#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) -#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) -#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) -#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) -#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) -#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) -#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) -#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) -#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) -#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) -#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) -#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) -#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) -#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) -#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) -#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) -#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) -#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) -#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) -#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) -#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) -#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) -#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) -#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) -#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) -#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) -#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) -#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) - - -/* Port T */ -#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) -#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) -#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) -#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) -#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) -#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) -#define TSB_PT_DATA_PT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,6))) -#define TSB_PT_DATA_PT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,7))) -#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) -#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) -#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) -#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) -#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) -#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) -#define TSB_PT_CR_PT6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,6))) -#define TSB_PT_CR_PT7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,7))) -#define TSB_PT_FR1_PT0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,0))) -#define TSB_PT_FR1_PT1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,1))) -#define TSB_PT_FR1_PT2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,2))) -#define TSB_PT_FR1_PT3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) -#define TSB_PT_FR1_PT4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,4))) -#define TSB_PT_FR2_PT0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,0))) -#define TSB_PT_FR2_PT1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,1))) -#define TSB_PT_FR3_PT1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,1))) -#define TSB_PT_FR3_PT2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,2))) -#define TSB_PT_FR3_PT3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) -#define TSB_PT_FR3_PT4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,4))) -#define TSB_PT_FR3_PT5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,5))) -#define TSB_PT_FR3_PT6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,6))) -#define TSB_PT_FR3_PT7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,7))) -#define TSB_PT_FR4_PT5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,5))) -#define TSB_PT_FR4_PT6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,6))) -#define TSB_PT_FR4_PT7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,7))) -#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) -#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) -#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) -#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) -#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) -#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) -#define TSB_PT_OD_PT6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,6))) -#define TSB_PT_OD_PT7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,7))) -#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) -#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) -#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) -#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) -#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) -#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) -#define TSB_PT_PUP_PT6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,6))) -#define TSB_PT_PUP_PT7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,7))) -#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) -#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) -#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) -#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) -#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) -#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) -#define TSB_PT_PDN_PT6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,6))) -#define TSB_PT_PDN_PT7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,7))) -#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) -#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) -#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) -#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) -#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) -#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) -#define TSB_PT_IE_PT6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,6))) -#define TSB_PT_IE_PT7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,7))) - - -/* Port U */ -#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) -#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) -#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) -#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) -#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) -#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) -#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) -#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) -#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) -#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) -#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) -#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) -#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) -#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) -#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) -#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) -#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) -#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) -#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) -#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) -#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) -#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) -#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) -#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) -#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) -#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) -#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) -#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) -#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) -#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) -#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) -#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) -#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) -#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) -#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) -#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) - - -/* */ -#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) -#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) -#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) -#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) -#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) -#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) -#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) -#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) -#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) -#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) -#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) -#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) -#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) -#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) -#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) -#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) -#define TSB_PV_FR1_PV5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,5))) -#define TSB_PV_FR1_PV6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,6))) -#define TSB_PV_FR1_PV7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,7))) -#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) -#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) -#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) -#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) -#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) -#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) -#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) -#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) -#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) -#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) -#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) -#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) -#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) -#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) -#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) -#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) -#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) -#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) -#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) -#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) -#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) -#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) -#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) -#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) -#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) -#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) -#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) -#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) -#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) -#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) -#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) -#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) -#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) -#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) - - -/* */ -#define TSB_RTC_ADJCTL_AJEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJCTL,0))) -#define TSB_RTC_ADJSIGN_ADJSIGN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJSIGN,0))) - - -/* */ -#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) -#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) -#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) -#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) -#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) -#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) -#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) -#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) -#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) -#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) -#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) -#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) -#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) - - -/* */ -#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) -#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) -#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) -#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) - - -/* */ -#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) -#define TSB_CG_OSCCR_IHOSC2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,3))) -#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) -#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) -#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) -#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) -#define TSB_CG_SCOCR_SCOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SCOCR,0))) -#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) -#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) -#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) -#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) -#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) -#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) -#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) -#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) -#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) -#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) -#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) -#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) -#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) -#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) -#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) -#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) -#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) -#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) -#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) -#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) -#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) -#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) -#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) -#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) -#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) -#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) -#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) -#define TSB_CG_FSYSENA_IPENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,19))) -#define TSB_CG_FSYSENA_IPENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,20))) -#define TSB_CG_FSYSENA_IPENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,21))) -#define TSB_CG_FSYSENA_IPENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,22))) -#define TSB_CG_FSYSENA_IPENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,23))) -#define TSB_CG_FSYSENA_IPENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,24))) -#define TSB_CG_FSYSENA_IPENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,25))) -#define TSB_CG_FSYSENA_IPENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,26))) -#define TSB_CG_FSYSENA_IPENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,27))) -#define TSB_CG_FSYSENA_IPENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,28))) -#define TSB_CG_FSYSENA_IPENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,29))) -#define TSB_CG_FSYSENA_IPENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,30))) -#define TSB_CG_FSYSENA_IPENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,31))) -#define TSB_CG_FSYSENB_IPENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,0))) -#define TSB_CG_FSYSENB_IPENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,1))) -#define TSB_CG_FSYSENB_IPENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,2))) -#define TSB_CG_FSYSENB_IPENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,3))) -#define TSB_CG_FSYSENB_IPENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,4))) -#define TSB_CG_FSYSENB_IPENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,5))) -#define TSB_CG_FSYSENB_IPENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,6))) -#define TSB_CG_FSYSENB_IPENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,7))) -#define TSB_CG_FSYSENB_IPENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,8))) -#define TSB_CG_FSYSENB_IPENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,9))) -#define TSB_CG_FSYSENB_IPENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,10))) -#define TSB_CG_FSYSENB_IPENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,11))) -#define TSB_CG_FSYSENB_IPENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,12))) -#define TSB_CG_FSYSENB_IPENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,13))) -#define TSB_CG_FSYSENB_IPENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,14))) -#define TSB_CG_FSYSENB_IPENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,15))) -#define TSB_CG_FSYSENB_IPENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,16))) -#define TSB_CG_FSYSENB_IPENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,17))) -#define TSB_CG_FSYSENB_IPENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,18))) -#define TSB_CG_FSYSENB_IPENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,19))) -#define TSB_CG_FSYSENB_IPENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,20))) -#define TSB_CG_FSYSENB_IPENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,21))) -#define TSB_CG_FSYSENB_IPENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,22))) -#define TSB_CG_FSYSENB_IPENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,23))) -#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) -#define TSB_CG_FCEN_FCIPEN07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,7))) -#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) -#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) - - -/* */ -#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) - - - -/* */ -#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) -#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) -#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) -#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) -#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) -#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) -#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) -#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) -#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) -#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) -#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) -#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) -#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) -#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) -#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) -#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) -#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) -#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) -#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) -#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) -#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) -#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) -#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) -#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) -#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) -#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) -#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) -#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) -#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) -#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) -#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) -#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) -#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) -#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) -#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) -#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) -#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) -#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) -#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) -#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) -#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) -#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) -#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) -#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) -#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) -#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) -#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) -#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) -#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) -#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) -#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) -#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) -#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) -#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) -#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) -#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) -#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) -#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) -#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) -#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) -#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) -#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) -#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) -#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) -#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) -#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) -#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) -#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) -#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) -#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) -#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) -#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) -#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) -#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) -#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) -#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) -#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) -#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) -#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) -#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) -#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) -#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) -#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) -#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) -#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) -#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) -#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) -#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) -#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) -#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) -#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) -#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) -#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) -#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) -#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) -#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) -#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) -#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) -#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) -#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) -#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) -#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) -#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) - - -/* */ -#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) -#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) -#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) -#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) -#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) -#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) -#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) -#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) -#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) -#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) -#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) -#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) -#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) -#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) -#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) -#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) -#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) -#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) -#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) -#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) -#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) -#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) -#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) -#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) -#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) -#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) -#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) -#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) -#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) -#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) -#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) -#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) -#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) -#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) -#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) -#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) -#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) -#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) -#define TSB_PMD0_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,0))) -#define TSB_PMD0_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,3))) -#define TSB_PMD0_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,4))) -#define TSB_PMD0_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,8))) -#define TSB_PMD0_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,9))) -#define TSB_PMD0_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,10))) -#define TSB_PMD0_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,12))) -#define TSB_PMD0_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,16))) -#define TSB_PMD0_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,17))) -#define TSB_PMD0_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,18))) -#define TSB_PMD0_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,19))) -#define TSB_PMD0_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,20))) -#define TSB_PMD0_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,21))) -#define TSB_PMD0_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,31))) - - -/* Encoder Input (ENC) */ -#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) -#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) -#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) -#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) -#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) -#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) -#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) -#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) -#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) -#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) -#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) -#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) -#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) -#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) -#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) -#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) -#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) -#define TSB_EN0_INPCR_SYNCSPLND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) -#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) -#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) -#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) -#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) -#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) -#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) -#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) -#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) -#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) -#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) -#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) -#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) -#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) -#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) -#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) -#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) -#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) -#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) -#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) -#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) -#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) - -/** @} */ /* End of group Device_Peripheral_registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* __TMPM3HQ_H__ */ - -/** @} */ /* End of group TMPM3HQ */ -/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S deleted file mode 100644 index 853a7a3df5..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S +++ /dev/null @@ -1,613 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3HQ.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3HQ' Device Series -; * @version V1.0.0.0 -; * $Date:: 2017-12-08 #$ -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin 00 - DCD INT01_IRQHandler ; 1: Interrupt Pin 01 - DCD INT02_IRQHandler ; 2: Interrupt Pin 02 - DCD INT03_IRQHandler ; 3: Interrupt Pin 03 - DCD INT04_IRQHandler ; 4: Interrupt Pin 04 - DCD INT05_IRQHandler ; 5: Interrupt Pin 05 - DCD INT06_IRQHandler ; 6: Interrupt Pin 06 - DCD INT07_IRQHandler ; 7: Interrupt Pin 07 - DCD INT08_IRQHandler ; 8: Interrupt Pin 08 - DCD INT09_IRQHandler ; 9: Interrupt Pin 09 - DCD INT10_IRQHandler ; 10: Interrupt Pin 10 - DCD INT11_IRQHandler ; 11: Interrupt Pin 11 - DCD INT12_IRQHandler ; 12: Interrupt Pin 12 - DCD INT13_IRQHandler ; 13: Interrupt Pin 13 - DCD INT14_IRQHandler ; 14: Interrupt Pin 14 - DCD INT15_IRQHandler ; 15: Interrupt Pin 15 - DCD INT16_IRQHandler ; 16: Interrupt Pin 16 - DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 - DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 - DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 - DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 - DCD INT29_IRQHandler ; 21: Interrupt Pin 29 - DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 - DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt - DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) - DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt - DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt - DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) - DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 - DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 - DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 - DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 - DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 - DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 - DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 - DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 - DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 - DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 - DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 - DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 - DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 - DCD INTPARI_IRQHandler ; 157: RAM parity interrupt - DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer - DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error - DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer - DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error - DCD INTRTC_IRQHandler ; 162: Real time clock interrupt - DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt - - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT00_IRQHandler [WEAK] - EXPORT INT01_IRQHandler [WEAK] - EXPORT INT02_IRQHandler [WEAK] - EXPORT INT03_IRQHandler [WEAK] - EXPORT INT04_IRQHandler [WEAK] - EXPORT INT05_IRQHandler [WEAK] - EXPORT INT06_IRQHandler [WEAK] - EXPORT INT07_IRQHandler [WEAK] - EXPORT INT08_IRQHandler [WEAK] - EXPORT INT09_IRQHandler [WEAK] - EXPORT INT10_IRQHandler [WEAK] - EXPORT INT11_IRQHandler [WEAK] - EXPORT INT12_IRQHandler [WEAK] - EXPORT INT13_IRQHandler [WEAK] - EXPORT INT14_IRQHandler [WEAK] - EXPORT INT15_IRQHandler [WEAK] - EXPORT INT16_IRQHandler [WEAK] - EXPORT INT17_18_IRQHandler [WEAK] - EXPORT INT19_22_IRQHandler [WEAK] - EXPORT INT23_26_IRQHandler [WEAK] - EXPORT INT27_28_IRQHandler [WEAK] - EXPORT INT29_IRQHandler [WEAK] - EXPORT INT30_31_IRQHandler [WEAK] - EXPORT INTEMG0_IRQHandler [WEAK] - EXPORT INTOVV0_IRQHandler [WEAK] - EXPORT INTPMD0_IRQHandler [WEAK] - EXPORT INTENC00_IRQHandler [WEAK] - EXPORT INTENC01_IRQHandler [WEAK] - EXPORT INTADAPDA_IRQHandler [WEAK] - EXPORT INTADAPDB_IRQHandler [WEAK] - EXPORT INTADACP0_IRQHandler [WEAK] - EXPORT INTADACP1_IRQHandler [WEAK] - EXPORT INTADATRG_IRQHandler [WEAK] - EXPORT INTADASGL_IRQHandler [WEAK] - EXPORT INTADACNT_IRQHandler [WEAK] - EXPORT INTT0RX_IRQHandler [WEAK] - EXPORT INTT0TX_IRQHandler [WEAK] - EXPORT INTT0ERR_IRQHandler [WEAK] - EXPORT INTT1RX_IRQHandler [WEAK] - EXPORT INTT1TX_IRQHandler [WEAK] - EXPORT INTT1ERR_IRQHandler [WEAK] - EXPORT INTT2RX_IRQHandler [WEAK] - EXPORT INTT2TX_IRQHandler [WEAK] - EXPORT INTT2ERR_IRQHandler [WEAK] - EXPORT INTT3RX_IRQHandler [WEAK] - EXPORT INTT3TX_IRQHandler [WEAK] - EXPORT INTT3ERR_IRQHandler [WEAK] - EXPORT INTT4RX_IRQHandler [WEAK] - EXPORT INTT4TX_IRQHandler [WEAK] - EXPORT INTT4ERR_IRQHandler [WEAK] - EXPORT INTI2CWUP_IRQHandler [WEAK] - EXPORT INTI2C0_IRQHandler [WEAK] - EXPORT INTI2C0AL_IRQHandler [WEAK] - EXPORT INTI2C0BF_IRQHandler [WEAK] - EXPORT INTI2C0NA_IRQHandler [WEAK] - EXPORT INTI2C1_IRQHandler [WEAK] - EXPORT INTI2C1AL_IRQHandler [WEAK] - EXPORT INTI2C1BF_IRQHandler [WEAK] - EXPORT INTI2C1NA_IRQHandler [WEAK] - EXPORT INTI2C2_IRQHandler [WEAK] - EXPORT INTI2C2AL_IRQHandler [WEAK] - EXPORT INTI2C2BF_IRQHandler [WEAK] - EXPORT INTI2C2NA_IRQHandler [WEAK] - EXPORT INTI2C3_IRQHandler [WEAK] - EXPORT INTI2C3AL_IRQHandler [WEAK] - EXPORT INTI2C3BF_IRQHandler [WEAK] - EXPORT INTI2C3NA_IRQHandler [WEAK] - EXPORT INTUART0RX_IRQHandler [WEAK] - EXPORT INTUART0TX_IRQHandler [WEAK] - EXPORT INTUART0ERR_IRQHandler [WEAK] - EXPORT INTUART1RX_IRQHandler [WEAK] - EXPORT INTUART1TX_IRQHandler [WEAK] - EXPORT INTUART1ERR_IRQHandler [WEAK] - EXPORT INTUART2RX_IRQHandler [WEAK] - EXPORT INTUART2TX_IRQHandler [WEAK] - EXPORT INTUART2ERR_IRQHandler [WEAK] - EXPORT INTUART3RX_IRQHandler [WEAK] - EXPORT INTUART3TX_IRQHandler [WEAK] - EXPORT INTUART3ERR_IRQHandler [WEAK] - EXPORT INTUART4RX_IRQHandler [WEAK] - EXPORT INTUART4TX_IRQHandler [WEAK] - EXPORT INTUART4ERR_IRQHandler [WEAK] - EXPORT INTUART5RX_IRQHandler [WEAK] - EXPORT INTUART5TX_IRQHandler [WEAK] - EXPORT INTUART5ERR_IRQHandler [WEAK] - EXPORT INTT32A00A_IRQHandler [WEAK] - EXPORT INTT32A00ACAP0_IRQHandler [WEAK] - EXPORT INTT32A00ACAP1_IRQHandler [WEAK] - EXPORT INTT32A00B_IRQHandler [WEAK] - EXPORT INTT32A00BCAP0_IRQHandler [WEAK] - EXPORT INTT32A00BCAP1_IRQHandler [WEAK] - EXPORT INTT32A00C_IRQHandler [WEAK] - EXPORT INTT32A00CCAP0_IRQHandler [WEAK] - EXPORT INTT32A00CCAP1_IRQHandler [WEAK] - EXPORT INTT32A01A_IRQHandler [WEAK] - EXPORT INTT32A01ACAP0_IRQHandler [WEAK] - EXPORT INTT32A01ACAP1_IRQHandler [WEAK] - EXPORT INTT32A01B_IRQHandler [WEAK] - EXPORT INTT32A01BCAP0_IRQHandler [WEAK] - EXPORT INTT32A01BCAP1_IRQHandler [WEAK] - EXPORT INTT32A01C_IRQHandler [WEAK] - EXPORT INTT32A01CCAP0_IRQHandler [WEAK] - EXPORT INTT32A01CCAP1_IRQHandler [WEAK] - EXPORT INTT32A02A_IRQHandler [WEAK] - EXPORT INTT32A02ACAP0_IRQHandler [WEAK] - EXPORT INTT32A02ACAP1_IRQHandler [WEAK] - EXPORT INTT32A02B_IRQHandler [WEAK] - EXPORT INTT32A02BCAP0_IRQHandler [WEAK] - EXPORT INTT32A02BCAP1_IRQHandler [WEAK] - EXPORT INTT32A02C_IRQHandler [WEAK] - EXPORT INTT32A02CCAP0_IRQHandler [WEAK] - EXPORT INTT32A02CCAP1_IRQHandler [WEAK] - EXPORT INTT32A03A_IRQHandler [WEAK] - EXPORT INTT32A03ACAP0_IRQHandler [WEAK] - EXPORT INTT32A03ACAP1_IRQHandler [WEAK] - EXPORT INTT32A03B_IRQHandler [WEAK] - EXPORT INTT32A03BCAP0_IRQHandler [WEAK] - EXPORT INTT32A03BCAP1_IRQHandler [WEAK] - EXPORT INTT32A03C_IRQHandler [WEAK] - EXPORT INTT32A03CCAP0_IRQHandler [WEAK] - EXPORT INTT32A03CCAP1_IRQHandler [WEAK] - EXPORT INTT32A04A_IRQHandler [WEAK] - EXPORT INTT32A04ACAP0_IRQHandler [WEAK] - EXPORT INTT32A04ACAP1_IRQHandler [WEAK] - EXPORT INTT32A04B_IRQHandler [WEAK] - EXPORT INTT32A04BCAP0_IRQHandler [WEAK] - EXPORT INTT32A04BCAP1_IRQHandler [WEAK] - EXPORT INTT32A04C_IRQHandler [WEAK] - EXPORT INTT32A04CCAP0_IRQHandler [WEAK] - EXPORT INTT32A04CCAP1_IRQHandler [WEAK] - EXPORT INTT32A05A_IRQHandler [WEAK] - EXPORT INTT32A05ACAP0_IRQHandler [WEAK] - EXPORT INTT32A05ACAP1_IRQHandler [WEAK] - EXPORT INTT32A05B_IRQHandler [WEAK] - EXPORT INTT32A05BCAP0_IRQHandler [WEAK] - EXPORT INTT32A05BCAP1_IRQHandler [WEAK] - EXPORT INTT32A05C_IRQHandler [WEAK] - EXPORT INTT32A05CCAP0_IRQHandler [WEAK] - EXPORT INTT32A05CCAP1_IRQHandler [WEAK] - EXPORT INTT32A06A_IRQHandler [WEAK] - EXPORT INTT32A06ACAP0_IRQHandler [WEAK] - EXPORT INTT32A06ACAP1_IRQHandler [WEAK] - EXPORT INTT32A06B_IRQHandler [WEAK] - EXPORT INTT32A06BCAP0_IRQHandler [WEAK] - EXPORT INTT32A06BCAP1_IRQHandler [WEAK] - EXPORT INTT32A06C_IRQHandler [WEAK] - EXPORT INTT32A06CCAP0_IRQHandler [WEAK] - EXPORT INTT32A06CCAP1_IRQHandler [WEAK] - EXPORT INTT32A07A_IRQHandler [WEAK] - EXPORT INTT32A07ACAP0_IRQHandler [WEAK] - EXPORT INTT32A07ACAP1_IRQHandler [WEAK] - EXPORT INTT32A07B_IRQHandler [WEAK] - EXPORT INTT32A07BCAP0_IRQHandler [WEAK] - EXPORT INTT32A07BCAP1_IRQHandler [WEAK] - EXPORT INTT32A07C_IRQHandler [WEAK] - EXPORT INTT32A07CCAP0_IRQHandler [WEAK] - EXPORT INTT32A07CCAP1_IRQHandler [WEAK] - EXPORT INTPARI_IRQHandler [WEAK] - EXPORT INTDMAATC_IRQHandler [WEAK] - EXPORT INTDMAAERR_IRQHandler [WEAK] - EXPORT INTDMABTC_IRQHandler [WEAK] - EXPORT INTDMABERR_IRQHandler [WEAK] - EXPORT INTRTC_IRQHandler [WEAK] - EXPORT INTRMC0_IRQHandler [WEAK] - EXPORT INTFLCRDY_IRQHandler [WEAK] - EXPORT INTFLDRDY_IRQHandler [WEAK] - -INT00_IRQHandler -INT01_IRQHandler -INT02_IRQHandler -INT03_IRQHandler -INT04_IRQHandler -INT05_IRQHandler -INT06_IRQHandler -INT07_IRQHandler -INT08_IRQHandler -INT09_IRQHandler -INT10_IRQHandler -INT11_IRQHandler -INT12_IRQHandler -INT13_IRQHandler -INT14_IRQHandler -INT15_IRQHandler -INT16_IRQHandler -INT17_18_IRQHandler -INT19_22_IRQHandler -INT23_26_IRQHandler -INT27_28_IRQHandler -INT29_IRQHandler -INT30_31_IRQHandler -INTEMG0_IRQHandler -INTOVV0_IRQHandler -INTPMD0_IRQHandler -INTENC00_IRQHandler -INTENC01_IRQHandler -INTADAPDA_IRQHandler -INTADAPDB_IRQHandler -INTADACP0_IRQHandler -INTADACP1_IRQHandler -INTADATRG_IRQHandler -INTADASGL_IRQHandler -INTADACNT_IRQHandler -INTT0RX_IRQHandler -INTT0TX_IRQHandler -INTT0ERR_IRQHandler -INTT1RX_IRQHandler -INTT1TX_IRQHandler -INTT1ERR_IRQHandler -INTT2RX_IRQHandler -INTT2TX_IRQHandler -INTT2ERR_IRQHandler -INTT3RX_IRQHandler -INTT3TX_IRQHandler -INTT3ERR_IRQHandler -INTT4RX_IRQHandler -INTT4TX_IRQHandler -INTT4ERR_IRQHandler -INTI2CWUP_IRQHandler -INTI2C0_IRQHandler -INTI2C0AL_IRQHandler -INTI2C0BF_IRQHandler -INTI2C0NA_IRQHandler -INTI2C1_IRQHandler -INTI2C1AL_IRQHandler -INTI2C1BF_IRQHandler -INTI2C1NA_IRQHandler -INTI2C2_IRQHandler -INTI2C2AL_IRQHandler -INTI2C2BF_IRQHandler -INTI2C2NA_IRQHandler -INTI2C3_IRQHandler -INTI2C3AL_IRQHandler -INTI2C3BF_IRQHandler -INTI2C3NA_IRQHandler -INTUART0RX_IRQHandler -INTUART0TX_IRQHandler -INTUART0ERR_IRQHandler -INTUART1RX_IRQHandler -INTUART1TX_IRQHandler -INTUART1ERR_IRQHandler -INTUART2RX_IRQHandler -INTUART2TX_IRQHandler -INTUART2ERR_IRQHandler -INTUART3RX_IRQHandler -INTUART3TX_IRQHandler -INTUART3ERR_IRQHandler -INTUART4RX_IRQHandler -INTUART4TX_IRQHandler -INTUART4ERR_IRQHandler -INTUART5RX_IRQHandler -INTUART5TX_IRQHandler -INTUART5ERR_IRQHandler -INTT32A00A_IRQHandler -INTT32A00ACAP0_IRQHandler -INTT32A00ACAP1_IRQHandler -INTT32A00B_IRQHandler -INTT32A00BCAP0_IRQHandler -INTT32A00BCAP1_IRQHandler -INTT32A00C_IRQHandler -INTT32A00CCAP0_IRQHandler -INTT32A00CCAP1_IRQHandler -INTT32A01A_IRQHandler -INTT32A01ACAP0_IRQHandler -INTT32A01ACAP1_IRQHandler -INTT32A01B_IRQHandler -INTT32A01BCAP0_IRQHandler -INTT32A01BCAP1_IRQHandler -INTT32A01C_IRQHandler -INTT32A01CCAP0_IRQHandler -INTT32A01CCAP1_IRQHandler -INTT32A02A_IRQHandler -INTT32A02ACAP0_IRQHandler -INTT32A02ACAP1_IRQHandler -INTT32A02B_IRQHandler -INTT32A02BCAP0_IRQHandler -INTT32A02BCAP1_IRQHandler -INTT32A02C_IRQHandler -INTT32A02CCAP0_IRQHandler -INTT32A02CCAP1_IRQHandler -INTT32A03A_IRQHandler -INTT32A03ACAP0_IRQHandler -INTT32A03ACAP1_IRQHandler -INTT32A03B_IRQHandler -INTT32A03BCAP0_IRQHandler -INTT32A03BCAP1_IRQHandler -INTT32A03C_IRQHandler -INTT32A03CCAP0_IRQHandler -INTT32A03CCAP1_IRQHandler -INTT32A04A_IRQHandler -INTT32A04ACAP0_IRQHandler -INTT32A04ACAP1_IRQHandler -INTT32A04B_IRQHandler -INTT32A04BCAP0_IRQHandler -INTT32A04BCAP1_IRQHandler -INTT32A04C_IRQHandler -INTT32A04CCAP0_IRQHandler -INTT32A04CCAP1_IRQHandler -INTT32A05A_IRQHandler -INTT32A05ACAP0_IRQHandler -INTT32A05ACAP1_IRQHandler -INTT32A05B_IRQHandler -INTT32A05BCAP0_IRQHandler -INTT32A05BCAP1_IRQHandler -INTT32A05C_IRQHandler -INTT32A05CCAP0_IRQHandler -INTT32A05CCAP1_IRQHandler -INTT32A06A_IRQHandler -INTT32A06ACAP0_IRQHandler -INTT32A06ACAP1_IRQHandler -INTT32A06B_IRQHandler -INTT32A06BCAP0_IRQHandler -INTT32A06BCAP1_IRQHandler -INTT32A06C_IRQHandler -INTT32A06CCAP0_IRQHandler -INTT32A06CCAP1_IRQHandler -INTT32A07A_IRQHandler -INTT32A07ACAP0_IRQHandler -INTT32A07ACAP1_IRQHandler -INTT32A07B_IRQHandler -INTT32A07BCAP0_IRQHandler -INTT32A07BCAP1_IRQHandler -INTT32A07C_IRQHandler -INTT32A07CCAP0_IRQHandler -INTT32A07CCAP1_IRQHandler -INTPARI_IRQHandler -INTDMAATC_IRQHandler -INTDMAAERR_IRQHandler -INTDMABTC_IRQHandler -INTDMABERR_IRQHandler -INTRTC_IRQHandler -INTRMC0_IRQHandler -INTFLCRDY_IRQHandler -INTFLDRDY_IRQHandler - - B . - - ENDP - - END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct deleted file mode 100644 index 0babcdd896..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct +++ /dev/null @@ -1,49 +0,0 @@ -#! armcc -E - -;; TMPM3HQFDFG scatter file - -;; Vector table starts at 0 -;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) -;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) -;; Initial PC == &__main (with LSB set to indicate Thumb) -;; These two values are provided by the library -;; Other vectors must be provided by the user -;; Code starts after the last possible vector -;; Data starts at 0x20000000 -;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) -;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) - -;; Compatible with ISSM model - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x00080000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 MBED_APP_START MBED_APP_SIZE -{ - ER_IROM1 MBED_APP_START MBED_APP_SIZE - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 0x200002D8 (0x10000 - 0x2D8 - Stack_Size) - { - tmpm3hq_fc.o (+RO) - .ANY (+RW, +ZI) - } - - ARM_LIB_STACK (0x20000000+0x10000) EMPTY -Stack_Size { ; stack - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S deleted file mode 100644 index 41df1a7203..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S +++ /dev/null @@ -1,582 +0,0 @@ -/** - ******************************************************************************* - * @file startup_TMPM3HQ.s - * @brief CMSIS Cortex-M3 Core Device Startup File for the - * TOSHIBA 'TMPM3HQ' Device Series - * @version V5.00 - * @date 2016/03/02 - *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop // Top of Stack - .long Reset_Handler // Reset Handler - .long NMI_Handler // NMI Handler - .long HardFault_Handler // Hard Fault Handler - .long MemManage_Handler // MPU Fault Handler - .long BusFault_Handler // Bus Fault Handler - .long UsageFault_Handler // Usage Fault Handler - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long SVC_Handler // SVCall Handler - .long DebugMon_Handler // Debug Monitor Handler - .long 0 // Reserved - .long PendSV_Handler // PendSV Handler - .long SysTick_Handler // SysTick Handler - - // External interrupts - .long INT00_IRQHandler // 0: Interrupt Pin0 - .long INT01_IRQHandler // 1: Interrupt Pin1 - .long INT02_IRQHandler // 2: Interrupt Pin2 - .long INT03_IRQHandler // 3: Interrupt Pin3 - .long INT04_IRQHandler // 4: Interrupt Pin4 - .long INT05_IRQHandler // 5: Interrupt Pin5 - .long INT06_IRQHandler // 6: Interrupt Pin6 - .long INT07_IRQHandler // 7: Interrupt Pin7 - .long INT08_IRQHandler // 8: Interrupt Pin8 - .long INT09_IRQHandler // 9: Interrupt Pin9 - .long INT10_IRQHandler // 10: Interrupt Pin10 - .long INT11_IRQHandler // 11: Interrupt Pin11 - .long INT12_IRQHandler // 12: Interrupt Pin12 - .long INT13_IRQHandler // 13: Interrupt Pin13 - .long INT14_IRQHandler // 14: Interrupt Pin14 - .long INT15_IRQHandler // 15: Interrupt Pin15 - .long INT16_IRQHandler // 16: Interrupt Pin 16 - .long INT17_18_IRQHandler // 17: Interrupt Pin 17_18 - .long INT19_22_IRQHandler // 18: Interrupt Pin 19_22 - .long INT23_26_IRQHandler // 19: Interrupt Pin 23_26 - .long INT27_28_IRQHandler // 20: Interrupt Pin 27_28 - .long INT29_IRQHandler // 21: Interrupt Pin 29 - .long INT30_31_IRQHandler // 22: Interrupt Pin 30_31 - .long INTEMG0_IRQHandler // 23: PMD0 EMG interrupt - .long INTOVV0_IRQHandler // 24: PMD0 OVV interrupt - .long INTPMD0_IRQHandler // 25: PMD0 interrupt - .long INTENC00_IRQHandler // 26: Encoder 0 interrupt 0 - .long INTENC01_IRQHandler // 27: Encoder 0 interrupt 1 - .long INTADAPDA_IRQHandler // 28: ADC conversion triggered by PMD is finished A - .long INTADAPDB_IRQHandler // 29: ADC conversion triggered by PMD is finished B - .long INTADACP0_IRQHandler // 30: ADC conversion monitoring function interrupt 0 - .long INTADACP1_IRQHandler // 31: ADC conversion monitoring function interrupt 1 - .long INTADATRG_IRQHandler // 32: ADC conversion triggered by General purpose is finished - .long INTADASGL_IRQHandler // 33: ADC conversion triggered by Single program is finished - .long INTADACNT_IRQHandler // 34: ADC conversion triggered by Continuity program is finished - .long INTT0RX_IRQHandler // 35: TSPI/SIO reception (channel 0) - .long INTT0TX_IRQHandler // 36: TSPI/SIO transmit (channel 0) - .long INTT0ERR_IRQHandler // 37: TSPI/SIO error (channel 0) - .long INTT1RX_IRQHandler // 38: TSPI/SIO reception (channel 1) - .long INTT1TX_IRQHandler // 39: TSPI/SIO transmit (channel 1) - .long INTT1ERR_IRQHandler // 40: TSPI/SIO error (channel 1) - .long INTT2RX_IRQHandler // 41: TSPI/SIO reception (channel 2) - .long INTT2TX_IRQHandler // 42: TSPI/SIO transmit (channel 2) - .long INTT2ERR_IRQHandler // 43: TSPI/SIO error (channel 2) - .long INTT3RX_IRQHandler // 44: TSPI/SIO reception (channel 3) - .long INTT3TX_IRQHandler // 45: TSPI/SIO transmit (channel 3) - .long INTT3ERR_IRQHandler // 46: TSPI/SIO error (channel 3) - .long INTT4RX_IRQHandler // 47: TSPI/SIO reception (channel 4) - .long INTT4TX_IRQHandler // 48: TSPI/SIO transmit (channel 4) - .long INTT4ERR_IRQHandler // 49: TSPI/SIO error (channel 4) - .long INTI2CWUP_IRQHandler // 50: Serial bus interface (WakeUp) interrupt (channel 0) - .long INTI2C0_IRQHandler // 51: I2C0 transmission and reception interrupt - .long INTI2C0AL_IRQHandler // 52: I2C0 arbitration lost interrupt - .long INTI2C0BF_IRQHandler // 53: I2C0 bus free interrupt - .long INTI2C0NA_IRQHandler // 54: I2C0 no ack interrupt - .long INTI2C1_IRQHandler // 55: I2C1 transmission and reception interrupt - .long INTI2C1AL_IRQHandler // 56: I2C1 arbitration lost interrupt - .long INTI2C1BF_IRQHandler // 57: I2C1 bus free interrupt - .long INTI2C1NA_IRQHandler // 58: I2C1 no ack interrupt - .long INTI2C2_IRQHandler // 59: I2C2 transmission and reception interrupt - .long INTI2C2AL_IRQHandler // 60: I2C2 arbitration lost interrupt - .long INTI2C2BF_IRQHandler // 61: I2C2 bus free interrupt - .long INTI2C2NA_IRQHandler // 62: I2C2 no ack interrupt - .long INTI2C3_IRQHandler // 63: I2C3 transmission and reception interrupt - .long INTI2C3AL_IRQHandler // 64: I2C3 arbitration lost interrupt - .long INTI2C3BF_IRQHandler // 65: I2C3 bus free interrupt - .long INTI2C3NA_IRQHandler // 66: I2C3 no ack interrupt - .long INTUART0RX_IRQHandler // 67: UART reception (channel 0) - .long INTUART0TX_IRQHandler // 68: UART transmit (channel 0) - .long INTUART0ERR_IRQHandler // 69: UART error (channel 0) - .long INTUART1RX_IRQHandler // 70: UART reception (channel 1) - .long INTUART1TX_IRQHandler // 71: UART transmit (channel 1) - .long INTUART1ERR_IRQHandler // 72: UART error (channel 1) - .long INTUART2RX_IRQHandler // 73: UART reception (channel 2) - .long INTUART2TX_IRQHandler // 74: UART transmit (channel 2) - .long INTUART2ERR_IRQHandler // 75: UART error (channel 2) - .long INTUART3RX_IRQHandler // 76: UART reception (channel 3) - .long INTUART3TX_IRQHandler // 77: UART transmit (channel 3) - .long INTUART3ERR_IRQHandler // 78: UART error (channel 3) - .long INTUART4RX_IRQHandler // 79: UART reception (channel 4) - .long INTUART4TX_IRQHandler // 80: UART transmit (channel 4) - .long INTUART4ERR_IRQHandler // 81: UART error (channel 4) - .long INTUART5RX_IRQHandler // 82: UART reception (channel 5) - .long INTUART5TX_IRQHandler // 83: UART transmit (channel 5) - .long INTUART5ERR_IRQHandler // 84: UART error (channel 5) - .long INTT32A00A_IRQHandler // 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - .long INTT32A00ACAP0_IRQHandler // 86: 32bit T32A00A input capture 0 - .long INTT32A00ACAP1_IRQHandler // 87: 32bit T32A00A input capture 1 - .long INTT32A00B_IRQHandler // 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - .long INTT32A00BCAP0_IRQHandler // 89: 32bit T32A00B input capture 0 - .long INTT32A00BCAP1_IRQHandler // 90: 32bit T32A00B input capture 1 - .long INTT32A00C_IRQHandler // 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - .long INTT32A00CCAP0_IRQHandler // 92: 32bit T32A00C input capture 0 - .long INTT32A00CCAP1_IRQHandler // 93: 32bit T32A00C input capture 1 - .long INTT32A01A_IRQHandler // 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - .long INTT32A01ACAP0_IRQHandler // 95: 32bit T32A01A input capture 0 - .long INTT32A01ACAP1_IRQHandler // 96: 32bit T32A01A input capture 1 - .long INTT32A01B_IRQHandler // 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - .long INTT32A01BCAP0_IRQHandler // 98: 32bit T32A01B input capture 0 - .long INTT32A01BCAP1_IRQHandler // 99: 32bit T32A01B input capture 1 - .long INTT32A01C_IRQHandler // 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - .long INTT32A01CCAP0_IRQHandler // 101: 32bit T32A01C input capture 0 - .long INTT32A01CCAP1_IRQHandler // 102: 32bit T32A01C input capture 1 - .long INTT32A02A_IRQHandler // 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - .long INTT32A02ACAP0_IRQHandler // 104: 32bit T32A02A input capture 0 - .long INTT32A02ACAP1_IRQHandler // 105: 32bit T32A02A input capture 1 - .long INTT32A02B_IRQHandler // 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - .long INTT32A02BCAP0_IRQHandler // 107: 32bit T32A02B input capture 0 - .long INTT32A02BCAP1_IRQHandler // 108: 32bit T32A02B input capture 1 - .long INTT32A02C_IRQHandler // 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - .long INTT32A02CCAP0_IRQHandler // 110: 32bit T32A02C input capture 0 - .long INTT32A02CCAP1_IRQHandler // 111: 32bit T32A02C input capture 1 - .long INTT32A03A_IRQHandler // 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - .long INTT32A03ACAP0_IRQHandler // 113: 32bit T32A03A input capture 0 - .long INTT32A03ACAP1_IRQHandler // 114: 32bit T32A03A input capture 1 - .long INTT32A03B_IRQHandler // 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - .long INTT32A03BCAP0_IRQHandler // 116: 32bit T32A03B input capture 0 - .long INTT32A03BCAP1_IRQHandler // 117: 32bit T32A03B input capture 1 - .long INTT32A03C_IRQHandler // 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - .long INTT32A03CCAP0_IRQHandler // 119: 32bit T32A03C input capture 0 - .long INTT32A03CCAP1_IRQHandler // 120: 32bit T32A03C input capture 1 - .long INTT32A04A_IRQHandler // 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - .long INTT32A04ACAP0_IRQHandler // 122: 32bit T32A04A input capture 0 - .long INTT32A04ACAP1_IRQHandler // 123: 32bit T32A04A input capture 1 - .long INTT32A04B_IRQHandler // 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - .long INTT32A04BCAP0_IRQHandler // 125: 32bit T32A04B input capture 0 - .long INTT32A04BCAP1_IRQHandler // 126: 32bit T32A04B input capture 1 - .long INTT32A04C_IRQHandler // 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - .long INTT32A04CCAP0_IRQHandler // 128: 32bit T32A04C input capture 0 - .long INTT32A04CCAP1_IRQHandler // 129: 32bit T32A04C input capture 1 - .long INTT32A05A_IRQHandler // 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - .long INTT32A05ACAP0_IRQHandler // 131: 32bit T32A05A input capture 0 - .long INTT32A05ACAP1_IRQHandler // 132: 32bit T32A05A input capture 1 - .long INTT32A05B_IRQHandler // 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - .long INTT32A05BCAP0_IRQHandler // 134: 32bit T32A05B input capture 0 - .long INTT32A05BCAP1_IRQHandler // 135: 32bit T32A05B input capture 1 - .long INTT32A05C_IRQHandler // 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - .long INTT32A05CCAP0_IRQHandler // 137: 32bit T32A05C input capture 0 - .long INTT32A05CCAP1_IRQHandler // 138: 32bit T32A05C input capture 1 - .long INTT32A06A_IRQHandler // 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - .long INTT32A06ACAP0_IRQHandler // 140: 32bit T32A06A input capture 0 - .long INTT32A06ACAP1_IRQHandler // 141: 32bit T32A06A input capture 1 - .long INTT32A06B_IRQHandler // 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - .long INTT32A06BCAP0_IRQHandler // 143: 32bit T32A06B input capture 0 - .long INTT32A06BCAP1_IRQHandler // 144: 32bit T32A06B input capture 1 - .long INTT32A06C_IRQHandler // 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - .long INTT32A06CCAP0_IRQHandler // 146: 32bit T32A06C input capture 0 - .long INTT32A06CCAP1_IRQHandler // 147: 32bit T32A06C input capture 1 - .long INTT32A07A_IRQHandler // 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - .long INTT32A07ACAP0_IRQHandler // 149: 32bit T32A07A input capture 0 - .long INTT32A07ACAP1_IRQHandler // 150: 32bit T32A07A input capture 1 - .long INTT32A07B_IRQHandler // 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - .long INTT32A07BCAP0_IRQHandler // 152: 32bit T32A07B input capture 0 - .long INTT32A07BCAP1_IRQHandler // 153: 32bit T32A07B input capture 1 - .long INTT32A07C_IRQHandler // 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - .long INTT32A07CCAP0_IRQHandler // 155: 32bit T32A07C input capture 0 - .long INTT32A07CCAP1_IRQHandler // 156: 32bit T32A07C input capture 1 - .long INTPARI_IRQHandler // 157: RAM parity interrupt - .long INTDMAATC_IRQHandler // 158: DMAA end of transfer - .long INTDMAAERR_IRQHandler // 159: DMAA transfer error - .long INTDMABTC_IRQHandler // 160: DMAB end of transfer - .long INTDMABERR_IRQHandler // 161: DMAB transfer error - .long INTRTC_IRQHandler // 162: Real time clock interrupt - .long INTRMC0_IRQHandler // 163: Remote control reception interrupt - .long INTFLCRDY_IRQHandler // 164: Code FLASH Ready interrupt - .long INTFLDRDY_IRQHandler // 165: Data FLASH Ready interrupt - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler INT00_IRQHandler - def_irq_handler INT01_IRQHandler - def_irq_handler INT02_IRQHandler - def_irq_handler INT03_IRQHandler - def_irq_handler INT04_IRQHandler - def_irq_handler INT05_IRQHandler - def_irq_handler INT06_IRQHandler - def_irq_handler INT07_IRQHandler - def_irq_handler INT08_IRQHandler - def_irq_handler INT09_IRQHandler - def_irq_handler INT10_IRQHandler - def_irq_handler INT11_IRQHandler - def_irq_handler INT12_IRQHandler - def_irq_handler INT13_IRQHandler - def_irq_handler INT14_IRQHandler - def_irq_handler INT15_IRQHandler - def_irq_handler INT16_IRQHandler - def_irq_handler INT17_18_IRQHandler - def_irq_handler INT19_22_IRQHandler - def_irq_handler INT23_26_IRQHandler - def_irq_handler INT27_28_IRQHandler - def_irq_handler INT29_IRQHandler - def_irq_handler INT30_31_IRQHandler - def_irq_handler INTEMG0_IRQHandler - def_irq_handler INTOVV0_IRQHandler - def_irq_handler INTPMD0_IRQHandler - def_irq_handler INTENC00_IRQHandler - def_irq_handler INTENC01_IRQHandler - def_irq_handler INTADAPDA_IRQHandler - def_irq_handler INTADAPDB_IRQHandler - def_irq_handler INTADACP0_IRQHandler - def_irq_handler INTADACP1_IRQHandler - def_irq_handler INTADATRG_IRQHandler - def_irq_handler INTADASGL_IRQHandler - def_irq_handler INTADACNT_IRQHandler - def_irq_handler INTT0RX_IRQHandler - def_irq_handler INTT0TX_IRQHandler - def_irq_handler INTT0ERR_IRQHandler - def_irq_handler INTT1RX_IRQHandler - def_irq_handler INTT1TX_IRQHandler - def_irq_handler INTT1ERR_IRQHandler - def_irq_handler INTT2RX_IRQHandler - def_irq_handler INTT2TX_IRQHandler - def_irq_handler INTT2ERR_IRQHandler - def_irq_handler INTT3RX_IRQHandler - def_irq_handler INTT3TX_IRQHandler - def_irq_handler INTT3ERR_IRQHandler - def_irq_handler INTT4RX_IRQHandler - def_irq_handler INTT4TX_IRQHandler - def_irq_handler INTT4ERR_IRQHandler - def_irq_handler INTI2CWUP_IRQHandler - def_irq_handler INTI2C0_IRQHandler - def_irq_handler INTI2C0AL_IRQHandler - def_irq_handler INTI2C0BF_IRQHandler - def_irq_handler INTI2C0NA_IRQHandler - def_irq_handler INTI2C1_IRQHandler - def_irq_handler INTI2C1AL_IRQHandler - def_irq_handler INTI2C1BF_IRQHandler - def_irq_handler INTI2C1NA_IRQHandler - def_irq_handler INTI2C2_IRQHandler - def_irq_handler INTI2C2AL_IRQHandler - def_irq_handler INTI2C2BF_IRQHandler - def_irq_handler INTI2C2NA_IRQHandler - def_irq_handler INTI2C3_IRQHandler - def_irq_handler INTI2C3AL_IRQHandler - def_irq_handler INTI2C3BF_IRQHandler - def_irq_handler INTI2C3NA_IRQHandler - def_irq_handler INTUART0RX_IRQHandler - def_irq_handler INTUART0TX_IRQHandler - def_irq_handler INTUART0ERR_IRQHandler - def_irq_handler INTUART1RX_IRQHandler - def_irq_handler INTUART1TX_IRQHandler - def_irq_handler INTUART1ERR_IRQHandler - def_irq_handler INTUART2RX_IRQHandler - def_irq_handler INTUART2TX_IRQHandler - def_irq_handler INTUART2ERR_IRQHandler - def_irq_handler INTUART3RX_IRQHandler - def_irq_handler INTUART3TX_IRQHandler - def_irq_handler INTUART3ERR_IRQHandler - def_irq_handler INTUART4RX_IRQHandler - def_irq_handler INTUART4TX_IRQHandler - def_irq_handler INTUART4ERR_IRQHandler - def_irq_handler INTUART5RX_IRQHandler - def_irq_handler INTUART5TX_IRQHandler - def_irq_handler INTUART5ERR_IRQHandler - def_irq_handler INTT32A00A_IRQHandler - def_irq_handler INTT32A00ACAP0_IRQHandler - def_irq_handler INTT32A00ACAP1_IRQHandler - def_irq_handler INTT32A00B_IRQHandler - def_irq_handler INTT32A00BCAP0_IRQHandler - def_irq_handler INTT32A00BCAP1_IRQHandler - def_irq_handler INTT32A00C_IRQHandler - def_irq_handler INTT32A00CCAP0_IRQHandler - def_irq_handler INTT32A00CCAP1_IRQHandler - def_irq_handler INTT32A01A_IRQHandler - def_irq_handler INTT32A01ACAP0_IRQHandler - def_irq_handler INTT32A01ACAP1_IRQHandler - def_irq_handler INTT32A01B_IRQHandler - def_irq_handler INTT32A01BCAP0_IRQHandler - def_irq_handler INTT32A01BCAP1_IRQHandler - def_irq_handler INTT32A01C_IRQHandler - def_irq_handler INTT32A01CCAP0_IRQHandler - def_irq_handler INTT32A01CCAP1_IRQHandler - def_irq_handler INTT32A02A_IRQHandler - def_irq_handler INTT32A02ACAP0_IRQHandler - def_irq_handler INTT32A02ACAP1_IRQHandler - def_irq_handler INTT32A02B_IRQHandler - def_irq_handler INTT32A02BCAP0_IRQHandler - def_irq_handler INTT32A02BCAP1_IRQHandler - def_irq_handler INTT32A02C_IRQHandler - def_irq_handler INTT32A02CCAP0_IRQHandler - def_irq_handler INTT32A02CCAP1_IRQHandler - def_irq_handler INTT32A03A_IRQHandler - def_irq_handler INTT32A03ACAP0_IRQHandler - def_irq_handler INTT32A03ACAP1_IRQHandler - def_irq_handler INTT32A03B_IRQHandler - def_irq_handler INTT32A03BCAP0_IRQHandler - def_irq_handler INTT32A03BCAP1_IRQHandler - def_irq_handler INTT32A03C_IRQHandler - def_irq_handler INTT32A03CCAP0_IRQHandler - def_irq_handler INTT32A03CCAP1_IRQHandler - def_irq_handler INTT32A04A_IRQHandler - def_irq_handler INTT32A04ACAP0_IRQHandler - def_irq_handler INTT32A04ACAP1_IRQHandler - def_irq_handler INTT32A04B_IRQHandler - def_irq_handler INTT32A04BCAP0_IRQHandler - def_irq_handler INTT32A04BCAP1_IRQHandler - def_irq_handler INTT32A04C_IRQHandler - def_irq_handler INTT32A04CCAP0_IRQHandler - def_irq_handler INTT32A04CCAP1_IRQHandler - def_irq_handler INTT32A05A_IRQHandler - def_irq_handler INTT32A05ACAP0_IRQHandler - def_irq_handler INTT32A05ACAP1_IRQHandler - def_irq_handler INTT32A05B_IRQHandler - def_irq_handler INTT32A05BCAP0_IRQHandler - def_irq_handler INTT32A05BCAP1_IRQHandler - def_irq_handler INTT32A05C_IRQHandler - def_irq_handler INTT32A05CCAP0_IRQHandler - def_irq_handler INTT32A05CCAP1_IRQHandler - def_irq_handler INTT32A06A_IRQHandler - def_irq_handler INTT32A06ACAP0_IRQHandler - def_irq_handler INTT32A06ACAP1_IRQHandler - def_irq_handler INTT32A06B_IRQHandler - def_irq_handler INTT32A06BCAP0_IRQHandler - def_irq_handler INTT32A06BCAP1_IRQHandler - def_irq_handler INTT32A06C_IRQHandler - def_irq_handler INTT32A06CCAP0_IRQHandler - def_irq_handler INTT32A06CCAP1_IRQHandler - def_irq_handler INTT32A07A_IRQHandler - def_irq_handler INTT32A07ACAP0_IRQHandler - def_irq_handler INTT32A07ACAP1_IRQHandler - def_irq_handler INTT32A07B_IRQHandler - def_irq_handler INTT32A07BCAP0_IRQHandler - def_irq_handler INTT32A07BCAP1_IRQHandler - def_irq_handler INTT32A07C_IRQHandler - def_irq_handler INTT32A07CCAP0_IRQHandler - def_irq_handler INTT32A07CCAP1_IRQHandler - def_irq_handler INTPARI_IRQHandler - def_irq_handler INTDMAATC_IRQHandler - def_irq_handler INTDMAAERR_IRQHandler - def_irq_handler INTDMABTC_IRQHandler - def_irq_handler INTDMABERR_IRQHandler - def_irq_handler INTRTC_IRQHandler - def_irq_handler INTRMC0_IRQHandler - def_irq_handler INTFLCRDY_IRQHandler - def_irq_handler INTFLDRDY_IRQHandler - - .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld deleted file mode 100644 index bdea5de309..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld +++ /dev/null @@ -1,177 +0,0 @@ -/* Linker script for Toshiba TMPM3HQ */ - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 512K -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - /* 8_byte_aligned((166 + 16) vect * 4 bytes) = 8_byte_aligned(0x2D8) = 0x2D8 */ - RAM (rwx) : ORIGIN = (0x20000000 + 0x2D8), LENGTH = (64K - 0x2D8) -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - *(.ram_func*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S deleted file mode 100644 index cbed3bdbe3..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S +++ /dev/null @@ -1,1107 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3HQ.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3HQ' Device Series -; * @version V1.0.0.0 -; * $Date:: 2017-12-08 #$ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin 00 - DCD INT01_IRQHandler ; 1: Interrupt Pin 01 - DCD INT02_IRQHandler ; 2: Interrupt Pin 02 - DCD INT03_IRQHandler ; 3: Interrupt Pin 03 - DCD INT04_IRQHandler ; 4: Interrupt Pin 04 - DCD INT05_IRQHandler ; 5: Interrupt Pin 05 - DCD INT06_IRQHandler ; 6: Interrupt Pin 06 - DCD INT07_IRQHandler ; 7: Interrupt Pin 07 - DCD INT08_IRQHandler ; 8: Interrupt Pin 08 - DCD INT09_IRQHandler ; 9: Interrupt Pin 09 - DCD INT10_IRQHandler ; 10: Interrupt Pin 10 - DCD INT11_IRQHandler ; 11: Interrupt Pin 11 - DCD INT12_IRQHandler ; 12: Interrupt Pin 12 - DCD INT13_IRQHandler ; 13: Interrupt Pin 13 - DCD INT14_IRQHandler ; 14: Interrupt Pin 14 - DCD INT15_IRQHandler ; 15: Interrupt Pin 15 - DCD INT16_IRQHandler ; 16: Interrupt Pin 16 - DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 - DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 - DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 - DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 - DCD INT29_IRQHandler ; 21: Interrupt Pin 29 - DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 - DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt - DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) - DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt - DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt - DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) - DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 - DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 - DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 - DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 - DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 - DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 - DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 - DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 - DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 - DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 - DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 - DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 - DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 - DCD INTPARI_IRQHandler ; 157: RAM parity interrupt - DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer - DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error - DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer - DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error - DCD INTRTC_IRQHandler ; 162: Real time clock interrupt - DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT00_IRQHandler - B INT00_IRQHandler - - PUBWEAK INT01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT01_IRQHandler - B INT01_IRQHandler - - PUBWEAK INT02_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT02_IRQHandler - B INT02_IRQHandler - - PUBWEAK INT03_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT03_IRQHandler - B INT03_IRQHandler - - PUBWEAK INT04_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT04_IRQHandler - B INT04_IRQHandler - - PUBWEAK INT05_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT05_IRQHandler - B INT05_IRQHandler - - PUBWEAK INT06_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT06_IRQHandler - B INT06_IRQHandler - - PUBWEAK INT07_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT07_IRQHandler - B INT07_IRQHandler - - PUBWEAK INT08_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT08_IRQHandler - B INT08_IRQHandler - - PUBWEAK INT09_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT09_IRQHandler - B INT09_IRQHandler - - PUBWEAK INT10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT10_IRQHandler - B INT10_IRQHandler - - PUBWEAK INT11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT11_IRQHandler - B INT11_IRQHandler - - PUBWEAK INT12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT12_IRQHandler - B INT12_IRQHandler - - PUBWEAK INT13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT13_IRQHandler - B INT13_IRQHandler - - PUBWEAK INT14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT14_IRQHandler - B INT14_IRQHandler - - PUBWEAK INT15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT15_IRQHandler - B INT15_IRQHandler - - PUBWEAK INT16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT16_IRQHandler - B INT16_IRQHandler - - PUBWEAK INT17_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT17_18_IRQHandler - B INT17_18_IRQHandler - - PUBWEAK INT19_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT19_22_IRQHandler - B INT19_22_IRQHandler - - PUBWEAK INT23_26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT23_26_IRQHandler - B INT23_26_IRQHandler - - PUBWEAK INT27_28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT27_28_IRQHandler - B INT27_28_IRQHandler - - PUBWEAK INT29_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT29_IRQHandler - B INT29_IRQHandler - - PUBWEAK INT30_31_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT30_31_IRQHandler - B INT30_31_IRQHandler - - PUBWEAK INTEMG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTEMG0_IRQHandler - B INTEMG0_IRQHandler - - PUBWEAK INTOVV0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTOVV0_IRQHandler - B INTOVV0_IRQHandler - - PUBWEAK INTPMD0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPMD0_IRQHandler - B INTPMD0_IRQHandler - - PUBWEAK INTENC00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC00_IRQHandler - B INTENC00_IRQHandler - - PUBWEAK INTENC01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC01_IRQHandler - B INTENC01_IRQHandler - - PUBWEAK INTADAPDA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDA_IRQHandler - B INTADAPDA_IRQHandler - - PUBWEAK INTADAPDB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDB_IRQHandler - B INTADAPDB_IRQHandler - - PUBWEAK INTADACP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP0_IRQHandler - B INTADACP0_IRQHandler - - PUBWEAK INTADACP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP1_IRQHandler - B INTADACP1_IRQHandler - - PUBWEAK INTADATRG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADATRG_IRQHandler - B INTADATRG_IRQHandler - - PUBWEAK INTADASGL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADASGL_IRQHandler - B INTADASGL_IRQHandler - - PUBWEAK INTADACNT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACNT_IRQHandler - B INTADACNT_IRQHandler - - PUBWEAK INTT0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0RX_IRQHandler - B INTT0RX_IRQHandler - - PUBWEAK INTT0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0TX_IRQHandler - B INTT0TX_IRQHandler - - PUBWEAK INTT0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0ERR_IRQHandler - B INTT0ERR_IRQHandler - - PUBWEAK INTT1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1RX_IRQHandler - B INTT1RX_IRQHandler - - PUBWEAK INTT1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1TX_IRQHandler - B INTT1TX_IRQHandler - - PUBWEAK INTT1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1ERR_IRQHandler - B INTT1ERR_IRQHandler - - PUBWEAK INTT2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2RX_IRQHandler - B INTT2RX_IRQHandler - - PUBWEAK INTT2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2TX_IRQHandler - B INTT2TX_IRQHandler - - PUBWEAK INTT2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2ERR_IRQHandler - B INTT2ERR_IRQHandler - - PUBWEAK INTT3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3RX_IRQHandler - B INTT3RX_IRQHandler - - PUBWEAK INTT3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3TX_IRQHandler - B INTT3TX_IRQHandler - - PUBWEAK INTT3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3ERR_IRQHandler - B INTT3ERR_IRQHandler - - PUBWEAK INTT4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4RX_IRQHandler - B INTT4RX_IRQHandler - - PUBWEAK INTT4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4TX_IRQHandler - B INTT4TX_IRQHandler - - PUBWEAK INTT4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4ERR_IRQHandler - B INTT4ERR_IRQHandler - - PUBWEAK INTI2CWUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2CWUP_IRQHandler - B INTI2CWUP_IRQHandler - - PUBWEAK INTI2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0_IRQHandler - B INTI2C0_IRQHandler - - PUBWEAK INTI2C0AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0AL_IRQHandler - B INTI2C0AL_IRQHandler - - PUBWEAK INTI2C0BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0BF_IRQHandler - B INTI2C0BF_IRQHandler - - PUBWEAK INTI2C0NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0NA_IRQHandler - B INTI2C0NA_IRQHandler - - PUBWEAK INTI2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1_IRQHandler - B INTI2C1_IRQHandler - - PUBWEAK INTI2C1AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1AL_IRQHandler - B INTI2C1AL_IRQHandler - - PUBWEAK INTI2C1BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1BF_IRQHandler - B INTI2C1BF_IRQHandler - - PUBWEAK INTI2C1NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1NA_IRQHandler - B INTI2C1NA_IRQHandler - - PUBWEAK INTI2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2_IRQHandler - B INTI2C2_IRQHandler - - PUBWEAK INTI2C2AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2AL_IRQHandler - B INTI2C2AL_IRQHandler - - PUBWEAK INTI2C2BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2BF_IRQHandler - B INTI2C2BF_IRQHandler - - PUBWEAK INTI2C2NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2NA_IRQHandler - B INTI2C2NA_IRQHandler - - PUBWEAK INTI2C3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3_IRQHandler - B INTI2C3_IRQHandler - - PUBWEAK INTI2C3AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3AL_IRQHandler - B INTI2C3AL_IRQHandler - - PUBWEAK INTI2C3BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3BF_IRQHandler - B INTI2C3BF_IRQHandler - - PUBWEAK INTI2C3NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3NA_IRQHandler - B INTI2C3NA_IRQHandler - - PUBWEAK INTUART0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0RX_IRQHandler - B INTUART0RX_IRQHandler - - PUBWEAK INTUART0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0TX_IRQHandler - B INTUART0TX_IRQHandler - - PUBWEAK INTUART0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0ERR_IRQHandler - B INTUART0ERR_IRQHandler - - PUBWEAK INTUART1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1RX_IRQHandler - B INTUART1RX_IRQHandler - - PUBWEAK INTUART1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1TX_IRQHandler - B INTUART1TX_IRQHandler - - PUBWEAK INTUART1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1ERR_IRQHandler - B INTUART1ERR_IRQHandler - - PUBWEAK INTUART2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2RX_IRQHandler - B INTUART2RX_IRQHandler - - PUBWEAK INTUART2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2TX_IRQHandler - B INTUART2TX_IRQHandler - - PUBWEAK INTUART2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2ERR_IRQHandler - B INTUART2ERR_IRQHandler - - PUBWEAK INTUART3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3RX_IRQHandler - B INTUART3RX_IRQHandler - - PUBWEAK INTUART3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3TX_IRQHandler - B INTUART3TX_IRQHandler - - PUBWEAK INTUART3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3ERR_IRQHandler - B INTUART3ERR_IRQHandler - - PUBWEAK INTUART4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4RX_IRQHandler - B INTUART4RX_IRQHandler - - PUBWEAK INTUART4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4TX_IRQHandler - B INTUART4TX_IRQHandler - - PUBWEAK INTUART4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4ERR_IRQHandler - B INTUART4ERR_IRQHandler - - PUBWEAK INTUART5RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5RX_IRQHandler - B INTUART5RX_IRQHandler - - PUBWEAK INTUART5TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5TX_IRQHandler - B INTUART5TX_IRQHandler - - PUBWEAK INTUART5ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5ERR_IRQHandler - B INTUART5ERR_IRQHandler - - PUBWEAK INTT32A00A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00A_IRQHandler - B INTT32A00A_IRQHandler - - PUBWEAK INTT32A00ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP0_IRQHandler - B INTT32A00ACAP0_IRQHandler - - PUBWEAK INTT32A00ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP1_IRQHandler - B INTT32A00ACAP1_IRQHandler - - PUBWEAK INTT32A00B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00B_IRQHandler - B INTT32A00B_IRQHandler - - PUBWEAK INTT32A00BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP0_IRQHandler - B INTT32A00BCAP0_IRQHandler - - PUBWEAK INTT32A00BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP1_IRQHandler - B INTT32A00BCAP1_IRQHandler - - PUBWEAK INTT32A00C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00C_IRQHandler - B INTT32A00C_IRQHandler - - PUBWEAK INTT32A00CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP0_IRQHandler - B INTT32A00CCAP0_IRQHandler - - PUBWEAK INTT32A00CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP1_IRQHandler - B INTT32A00CCAP1_IRQHandler - - PUBWEAK INTT32A01A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01A_IRQHandler - B INTT32A01A_IRQHandler - - PUBWEAK INTT32A01ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP0_IRQHandler - B INTT32A01ACAP0_IRQHandler - - PUBWEAK INTT32A01ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP1_IRQHandler - B INTT32A01ACAP1_IRQHandler - - PUBWEAK INTT32A01B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01B_IRQHandler - B INTT32A01B_IRQHandler - - PUBWEAK INTT32A01BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP0_IRQHandler - B INTT32A01BCAP0_IRQHandler - - PUBWEAK INTT32A01BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP1_IRQHandler - B INTT32A01BCAP1_IRQHandler - - PUBWEAK INTT32A01C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01C_IRQHandler - B INTT32A01C_IRQHandler - - PUBWEAK INTT32A01CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP0_IRQHandler - B INTT32A01CCAP0_IRQHandler - - PUBWEAK INTT32A01CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP1_IRQHandler - B INTT32A01CCAP1_IRQHandler - - PUBWEAK INTT32A02A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02A_IRQHandler - B INTT32A02A_IRQHandler - - PUBWEAK INTT32A02ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP0_IRQHandler - B INTT32A02ACAP0_IRQHandler - - PUBWEAK INTT32A02ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP1_IRQHandler - B INTT32A02ACAP1_IRQHandler - - PUBWEAK INTT32A02B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02B_IRQHandler - B INTT32A02B_IRQHandler - - PUBWEAK INTT32A02BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP0_IRQHandler - B INTT32A02BCAP0_IRQHandler - - PUBWEAK INTT32A02BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP1_IRQHandler - B INTT32A02BCAP1_IRQHandler - - PUBWEAK INTT32A02C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02C_IRQHandler - B INTT32A02C_IRQHandler - - PUBWEAK INTT32A02CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP0_IRQHandler - B INTT32A02CCAP0_IRQHandler - - PUBWEAK INTT32A02CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP1_IRQHandler - B INTT32A02CCAP1_IRQHandler - - PUBWEAK INTT32A03A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03A_IRQHandler - B INTT32A03A_IRQHandler - - PUBWEAK INTT32A03ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP0_IRQHandler - B INTT32A03ACAP0_IRQHandler - - PUBWEAK INTT32A03ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP1_IRQHandler - B INTT32A03ACAP1_IRQHandler - - PUBWEAK INTT32A03B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03B_IRQHandler - B INTT32A03B_IRQHandler - - PUBWEAK INTT32A03BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP0_IRQHandler - B INTT32A03BCAP0_IRQHandler - - PUBWEAK INTT32A03BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP1_IRQHandler - B INTT32A03BCAP1_IRQHandler - - PUBWEAK INTT32A03C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03C_IRQHandler - B INTT32A03C_IRQHandler - - PUBWEAK INTT32A03CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP0_IRQHandler - B INTT32A03CCAP0_IRQHandler - - PUBWEAK INTT32A03CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP1_IRQHandler - B INTT32A03CCAP1_IRQHandler - - PUBWEAK INTT32A04A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04A_IRQHandler - B INTT32A04A_IRQHandler - - PUBWEAK INTT32A04ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP0_IRQHandler - B INTT32A04ACAP0_IRQHandler - - PUBWEAK INTT32A04ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP1_IRQHandler - B INTT32A04ACAP1_IRQHandler - - PUBWEAK INTT32A04B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04B_IRQHandler - B INTT32A04B_IRQHandler - - PUBWEAK INTT32A04BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP0_IRQHandler - B INTT32A04BCAP0_IRQHandler - - PUBWEAK INTT32A04BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP1_IRQHandler - B INTT32A04BCAP1_IRQHandler - - PUBWEAK INTT32A04C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04C_IRQHandler - B INTT32A04C_IRQHandler - - PUBWEAK INTT32A04CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP0_IRQHandler - B INTT32A04CCAP0_IRQHandler - - PUBWEAK INTT32A04CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP1_IRQHandler - B INTT32A04CCAP1_IRQHandler - - PUBWEAK INTT32A05A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05A_IRQHandler - B INTT32A05A_IRQHandler - - PUBWEAK INTT32A05ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP0_IRQHandler - B INTT32A05ACAP0_IRQHandler - - PUBWEAK INTT32A05ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP1_IRQHandler - B INTT32A05ACAP1_IRQHandler - - PUBWEAK INTT32A05B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05B_IRQHandler - B INTT32A05B_IRQHandler - - PUBWEAK INTT32A05BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP0_IRQHandler - B INTT32A05BCAP0_IRQHandler - - PUBWEAK INTT32A05BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP1_IRQHandler - B INTT32A05BCAP1_IRQHandler - - PUBWEAK INTT32A05C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05C_IRQHandler - B INTT32A05C_IRQHandler - - PUBWEAK INTT32A05CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP0_IRQHandler - B INTT32A05CCAP0_IRQHandler - - PUBWEAK INTT32A05CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP1_IRQHandler - B INTT32A05CCAP1_IRQHandler - - PUBWEAK INTT32A06A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06A_IRQHandler - B INTT32A06A_IRQHandler - - PUBWEAK INTT32A06ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06ACAP0_IRQHandler - B INTT32A06ACAP0_IRQHandler - - PUBWEAK INTT32A06ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06ACAP1_IRQHandler - B INTT32A06ACAP1_IRQHandler - - PUBWEAK INTT32A06B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06B_IRQHandler - B INTT32A06B_IRQHandler - - PUBWEAK INTT32A06BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06BCAP0_IRQHandler - B INTT32A06BCAP0_IRQHandler - - PUBWEAK INTT32A06BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06BCAP1_IRQHandler - B INTT32A06BCAP1_IRQHandler - - PUBWEAK INTT32A06C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06C_IRQHandler - B INTT32A06C_IRQHandler - - PUBWEAK INTT32A06CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06CCAP0_IRQHandler - B INTT32A06CCAP0_IRQHandler - - PUBWEAK INTT32A06CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06CCAP1_IRQHandler - B INTT32A06CCAP1_IRQHandler - - PUBWEAK INTT32A07A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07A_IRQHandler - B INTT32A07A_IRQHandler - - PUBWEAK INTT32A07ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07ACAP0_IRQHandler - B INTT32A07ACAP0_IRQHandler - - PUBWEAK INTT32A07ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07ACAP1_IRQHandler - B INTT32A07ACAP1_IRQHandler - - PUBWEAK INTT32A07B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07B_IRQHandler - B INTT32A07B_IRQHandler - - PUBWEAK INTT32A07BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07BCAP0_IRQHandler - B INTT32A07BCAP0_IRQHandler - - PUBWEAK INTT32A07BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07BCAP1_IRQHandler - B INTT32A07BCAP1_IRQHandler - - PUBWEAK INTT32A07C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07C_IRQHandler - B INTT32A07C_IRQHandler - - PUBWEAK INTT32A07CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07CCAP0_IRQHandler - B INTT32A07CCAP0_IRQHandler - - PUBWEAK INTT32A07CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07CCAP1_IRQHandler - B INTT32A07CCAP1_IRQHandler - - PUBWEAK INTPARI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPARI_IRQHandler - B INTPARI_IRQHandler - - PUBWEAK INTDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAATC_IRQHandler - B INTDMAATC_IRQHandler - - PUBWEAK INTDMAAERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAAERR_IRQHandler - B INTDMAAERR_IRQHandler - - PUBWEAK INTDMABTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMABTC_IRQHandler - B INTDMABTC_IRQHandler - - PUBWEAK INTDMABERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMABERR_IRQHandler - B INTDMABERR_IRQHandler - - PUBWEAK INTRTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRTC_IRQHandler - B INTRTC_IRQHandler - - PUBWEAK INTRMC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC0_IRQHandler - B INTRMC0_IRQHandler - - PUBWEAK INTFLCRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY_IRQHandler - B INTFLCRDY_IRQHandler - - PUBWEAK INTFLDRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLDRDY_IRQHandler - B INTFLDRDY_IRQHandler - - END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf deleted file mode 100644 index bd0d7b2757..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf +++ /dev/null @@ -1,55 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ - -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; } - -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -define symbol __ICFEDIT_region_RAM_start__ = 0x200002D8; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*Heap 1/4 of ram and stack 1/8*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol __BRAM_start__ = 0x20010000; -define symbol __BRAM_end__ = 0x200107FF; -define symbol __DFLASH_start__ = 0x30000000; -define symbol __DFLASH_end__ = 0x30007FFF; -define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ]; -define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -initialize by copy { section RAMCODE }; - -/* Place both in a block */ -define block RamCode { section RAMCODE }; -define block RamCodeInit { section RAMCODE_init }; - -/* Place them in ROM and RAM */ -place in ROM_region { block RamCodeInit }; -place in RAM_region { block RamCode }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in BRAM_region { section .backup_ram }; -place in DFLASH_region { section .data_flash }; diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis.h deleted file mode 100644 index fd6c721725..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis.h +++ /dev/null @@ -1,22 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "TMPM3HQ.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis_nvic.h deleted file mode 100644 index f80e0c1bd5..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis_nvic.h +++ /dev/null @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_FLASH_VECTOR_ADDRESS 0x00000000 -#define NVIC_USER_IRQ_NUMBER 166 -#define NVIC_NUM_VECTORS (16 + 166) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/system_TMPM3HQ.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/system_TMPM3HQ.c deleted file mode 100644 index b984f3b7f1..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/system_TMPM3HQ.c +++ /dev/null @@ -1,340 +0,0 @@ -/** - ******************************************************************************* - * @file system_TMPM3Hy.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the - * TOSHIBA 'TMPM3Hy' Device Series - * @version 0.0.5.0 - * $Date:: 2017-07-01 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#include "TMPM3HQ.h" - -/*-------- <<< Start of configuration section >>> ----------------------------*/ - -/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ -#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ -#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ -#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ - -/* Clock Generator (CG) Configuration */ -#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ -#define SYSCR_Val (0x00000000UL) - -#define STBYCR_Val (0x00000000UL) - -#define CG_6M_MUL_13_328_FPLL (0x001C6535UL<<8U) /* fPLL = 6MHz * 13.328 */ -#define CG_8M_MUL_10_FPLL (0x00246028UL<<8U) /* fPLL = 8MHz * 10 */ -#define CG_10M_MUL_8_FPLL (0x002E6020UL<<8U) /* fPLL = 10MHz * 8 */ -#define CG_12M_MUL_6_656_FPLL (0x0036EA1AUL<<8U) /* fPLL = 12MHz * 6.656 */ -#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */ -#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */ -#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */ -#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */ - -#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) -#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) -#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) - -#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) -#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) - -#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001) - -#if (CLOCK_SETUP) - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) - #define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL -#else - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000) - #define PLL0SEL_Ready CG_10M_MUL_8_FPLL -#endif -#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) -#define PLL0SEL_MASK (0xFFFFFF00UL) - -/*-------- <<< End of configuration section >>> ------------------------------*/ - -/*-------- DEFINES -----------------------------------------------------------*/ -/* Define clocks */ -#define EOSC_6M (6000000UL) -#define EOSC_8M (8000000UL) -#define EOSC_10M (10000000UL) -#define EOSC_12M (12000000UL) -#define IOSC_10M (10000000UL) -#define EXTALH EOSC_12M /* External high-speed oscillator freq */ -#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ -#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */ -#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */ -#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ -#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */ -#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ -#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ -#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ -#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ -#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ -#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ - -/* Configure Warm-up time */ -#define HZ_1M (1000000UL) -#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ -#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ -#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ -#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = warm-up time(us) * EXTALH / 16 */ -#if (CLOCK_SETUP) - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#else - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#endif -/* Determine core clock frequency according to settings */ -/* System clock is high-speed clock*/ -#if (CLOCK_SETUP) - #define CORE_TALH (EXTALH) -#else - #define CORE_TALH (IXTALH) -#endif - -#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ - #if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_13_328_FPLL)) - #define __CORE_CLK EOSC_6M_DIV4_PLLON /* output clock is 79.97MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL)) - #define __CORE_CLK EOSC_6M_DIV8_PLLON /* output clock is 39.98MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 6MHz */ - #elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_10_FPLL)) - #define __CORE_CLK EOSC_8M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL)) - #define __CORE_CLK EOSC_8M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 8MHz */ - #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) - #define __CORE_CLK EOSC_10M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK EOSC_10M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) - #define __CORE_CLK EOSC_12M_DIV4_PLLON /* output clock is 79.88MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) - #define __CORE_CLK EOSC_12M_DIV8_PLLON /* output clock is 39.94MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 12MHz */ - #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) - #define __CORE_CLK IOSC_10M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK IOSC_10M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #else /* input clock not known */ - #define __CORE_CLK (0U) - #error "Core Oscillator Frequency invalid!" - #endif /* End switch input clock */ -#else - #define __CORE_CLK (CORE_TALH) -#endif - -#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ - #define __CORE_SYS (__CORE_CLK) -#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ - #define __CORE_SYS (__CORE_CLK / 2U) -#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ - #define __CORE_SYS (__CORE_CLK / 4U ) -#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ - #define __CORE_SYS (__CORE_CLK / 8U) -#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ - #define __CORE_SYS (__CORE_CLK / 16U) -#else /* Gear -> reserved */ - #define __CORE_SYS (0U) -#endif - - -/* Clock Variable definitions */ -uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Update SystemCoreClock according register values. - */ -void SystemCoreClockUpdate(void) -{ /* Get Core Clock Frequency */ - uint32_t CoreClock = 0U; - uint32_t CoreClockInput = 0U; - uint32_t regval = 0U; - uint32_t oscsel = 0U; - uint32_t pll0sel = 0U; - uint32_t pll0on = 0U; - /* Determine clock frequency according to clock register values */ - /* System clock is high-speed clock */ - regval = TSB_CG->OSCCR; - oscsel = regval & CG_OSCCR_OSCSEL_SET; - if (oscsel) { /* If system clock is External high-speed oscillator freq */ - CoreClock = EXTALH; - } else { /* If system clock is Internal high-speed oscillator freq */ - CoreClock = IXTALH; - } - regval = TSB_CG->PLL0SEL; - pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; - pll0on = regval & CG_PLL0SEL_PLL0ON_SET; - if (pll0sel && pll0on) { /* If PLL enabled */ - if (CoreClock == EOSC_6M) { /* If input is 6MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_13_328_FPLL) { - CoreClockInput = EOSC_6M_DIV4_PLLON; /* output clock is 79.97MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) { - CoreClockInput = EOSC_6M_DIV8_PLLON; /* output clock is 39.98MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_10_FPLL) { - CoreClockInput = EOSC_8M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) { - CoreClockInput = EOSC_8M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { - CoreClockInput = EOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = EOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) { - CoreClockInput = EOSC_12M_DIV4_PLLON; /* output clock is 79.88MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) { - CoreClockInput = EOSC_12M_DIV8_PLLON; /* output clock is 39.94MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { - CoreClockInput = IOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = IOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else { - CoreClockInput = 0U; - } - } else { /* If PLL not used */ - CoreClockInput = CoreClock; - } - - switch (TSB_CG->SYSCR & 7U) { - case 0U: /* Gear -> fc */ - SystemCoreClock = CoreClockInput; - break; - case 1U: /* Gear -> fc/2 */ - SystemCoreClock = CoreClockInput / 2U; - break; - case 2U: /* Gear -> fc/4 */ - SystemCoreClock = CoreClockInput / 4U; - break; - case 3U: /* Gear -> fc/8 */ - if (CoreClockInput >= EOSC_8M) { - SystemCoreClock = CoreClockInput / 8U; - } else { - SystemCoreClock = 0U; - } - break; - case 4U: /* Gear -> fc/16 */ - if (CoreClockInput > EOSC_12M) { - SystemCoreClock = CoreClockInput / 16U; - } else { - SystemCoreClock = 0U; - } - break; - case 5U: - case 6U: - case 7U: - SystemCoreClock = 0U; - break; - default: - SystemCoreClock = 0U; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ -#if (SIWD_SETUP) /* Watchdog Setup */ - /* SIWD Disable */ - TSB_SIWD0->EN = SIWDEN_Val; - TSB_SIWD0->CR = SIWDCR_Val; -#else - /* SIWD Enable (Setting after a Reset) */ -#endif - -#if (CLOCK_SETUP) /* Clock(external) Setup */ - TSB_CG->SYSCR = SYSCR_Val; - - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - while (!TSB_CG_OSCCR_OSCF) { - ; - } /* Confirm CGOSCCR="1" */ - TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; -#else - /* Internal HOSC Enable (Setting after a Reset) */ -#endif - - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; - TSB_CG->PLL0SEL = PLL0SEL_Ready; - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ - TSB_CG->STBYCR = STBYCR_Val; - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Lockup */ - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; - while (!TSB_CG_PLL0SEL_PLL0ST) { - ; - } /*Confirm CGPLL0SEL = "1" */ -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/system_TMPM3HQ.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/system_TMPM3HQ.h deleted file mode 100644 index 0dd2ddcdb5..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/system_TMPM3HQ.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ***************************************************************************** - * @file system_TMPM3Hy.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3Hy' Device Series - * @version V1.0.1.0 - * $Date:: 2017-07-01 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ***************************************************************************** - */ - -#include - -#ifndef __SYSTEM_TMPM3HQ_H -#define __SYSTEM_TMPM3HQ_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/flash_api.c deleted file mode 100644 index dc7981047d..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/flash_api.c +++ /dev/null @@ -1,130 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "flash_api.h" -#include "mbed_critical.h" -#include "tmpm3hq_fc.h" - -#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once -#define SECTOR_SIZE (0x8000) // 32KB each sectors or block -#define FLASH_CHIP_SIZE (0x00080000) // Flash chip size is 512KByte -#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) - -#define SUCCESS (0U) -#define FAIL (-1) -// IHOSC1EN -#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask -#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable -#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable - -static void internal_hosc_enable(void); - -int32_t flash_init(flash_t *obj) -{ - obj->flash_inited = 0; - obj->flash_inited = 1; - internal_hosc_enable(); // Internal HOSC enable - return 0; -} - -int32_t flash_free(flash_t *obj) -{ - obj->flash_inited = 0; - - return 0; -} - -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - int status = FAIL; - - if (obj->flash_inited == 0) { - flash_init(obj); - } - - // We need to prevent flash accesses during erase operation - core_util_critical_section_enter(); - - if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t*)address)) { - status = SUCCESS; - } else { - // Do nothing - } - - core_util_critical_section_exit(); - - return status; -} - -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - int status = SUCCESS; - - address &= MASK_CHIP_ID_FROM_ADD; - - // We need to prevent flash accesses during program operation - core_util_critical_section_enter(); - - if (TXZ_SUCCESS == fc_write_code_flash((uint32_t*)data, (uint32_t*)address, size)) { - // Do nothing - } else { - status = FAIL; - } - - core_util_critical_section_exit(); - - return status; -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { - return SECTOR_SIZE; - } else { - // Do nothing - } - - return MBED_FLASH_INVALID_SIZE; -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - return PROGRAM_WRITE_MAX; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ - return FC_CODE_FLASH_ADDRESS_TOP; -} - -uint32_t flash_get_size(const flash_t *obj) -{ - return FLASH_CHIP_SIZE; -} - -static void internal_hosc_enable(void) -{ - uint32_t work; - work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); - TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0xFF; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_api.c deleted file mode 100644 index ae51ea47b7..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_api.c +++ /dev/null @@ -1,122 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" - -extern const PinMap PinMap_GPIO_IRQ[]; - -void gpio_init(gpio_t *obj, PinName pin) -{ - // Store above pin mask, pin name into GPIO object - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - obj->mask = gpio_set(pin); - obj->port = (PortName)(pin >> 3); - TSB_CG->FSYSENA |= (1 << (obj->port)); -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -uint32_t gpio_set(PinName pin) -{ - // Check that pin is valid - MBED_ASSERT(pin != (PinName)NC); - - // Set pin function as GPIO pin - pin_function(pin, GPIO_DATA); - - // Return pin mask - return (1 << (pin & 0x07)); -} - -// Set gpio object pin direction -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - // Set direction - switch (direction) { - case PIN_INPUT: - pin_function(obj->pin, PIN_INPUT); - break; - - case PIN_OUTPUT: - pin_function(obj->pin, PIN_OUTPUT); - break; - - case PIN_INOUT: - pin_function(obj->pin, PIN_INOUT); - break; - - default: - error("Invalid direction\n"); - break; - } -} - -// Write gpio object pin data -void gpio_write(gpio_t *obj, int value) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base = 0; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - if (value == GPIO_PIN_SET) { - BITBAND_PORT_SET(base, bit); - } else if (value == GPIO_PIN_RESET) { - BITBAND_PORT_CLR(base, bit); - } else { - error("Invalid value\n"); - } -} - -// Read gpio object pin data -int gpio_read(gpio_t *obj) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base = 0; - uint32_t val = 0; - int BitValue = 0; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - BITBAND_PORT_READ(val, base, bit); - - if (val == GPIO_PIN_RESET) { - BitValue = GPIO_PIN_RESET; - } else { - BitValue = GPIO_PIN_SET; - } - - return (BitValue); -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_include.h deleted file mode 100644 index eab27aefc6..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_include.h +++ /dev/null @@ -1,178 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __GPIO_INCLUDE_H -#define __GPIO_INCLUDE_H - -#include -#include -#include "TMPM3HQ.h" -#include "objects.h" -#include "serial_api.h" -#include "txz_driver_def.h" - -enum BitMode { - GPIO_PIN_RESET = 0, - GPIO_PIN_SET, -}; - -enum PortFunction { - GPIO_Mode_DATA = 0x0, // 0x0: PxDATA - GPIO_Mode_CR = 0x04, // 0x4: PxCR - GPIO_Mode_FR1 = 0x08, // 0x8: PxFR1 - GPIO_Mode_FR2 = 0x0C, // 0xC: PxFR2 - GPIO_Mode_FR3 = 0x10, // 0x10: PxFR3 - GPIO_Mode_FR4 = 0x14, // 0x14: PxFR4 - GPIO_Mode_FR5 = 0x18, // 0x18: PxFR5 - GPIO_Mode_FR6 = 0x1C, // 0x1C: PxFR6 - GPIO_Mode_FR7 = 0x20, // 0x20: PxFR7 - GPIO_Mode_OD = 0x28, // 0x28: PxOD - GPIO_Mode_PUP = 0x2C, // 0x2C: PxPUP - GPIO_Mode_PDN = 0x30, // 0x30: PxPDN - GPIO_Mode_IE = 0x38 // 0x38: PxIE -}; - -// GPIO -#define PORT_BASE (0x400C0000UL) // Port Register Base Adress -#define BITBAND_PORT_OFFSET (0x0000100UL) // Port Register Offset Value -#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) // Operational target Port Adress -#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) // Operational target Control Register Adress -#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) // Target Pin Bit set -#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) // Target Pin Bit clear -#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) // Target Pin Bit read -#define GPIO_DATA PIN_DATA(0, 2) -#define CHANNEL_NUM 32 -#define PORT_PIN_NUM 8 -#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0x1F) -#define PIN_POS(X) ((uint32_t)(X) & 0x7) -// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) -#define PIN_FUNC(X) (((X) & 0xFFFF0000) >> 16) -#define PIN_DIR(X) ((X) & 0xFFFF) -// SPI -#define TIMEOUT 1000 -#define INITIAL_SPI_FREQ 1000000 -// I2C -#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080) -#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) -#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) -#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) -#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) -#define I2CxCR2_INIT ((uint32_t)0x00000008) -#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) -#define I2CxCR2_TRX ((uint32_t)0x00000040) -#define I2CxST_I2C ((uint32_t)0x00000001) -#define I2CxST_CLEAR ((uint32_t)0x0000000F) -#define I2CxCR1_ACK ((uint32_t)0x00000010) -#define I2CxSR_BB ((uint32_t)0x00000020) -#define I2CxSR_LRB ((uint32_t)0x00000001) -#define I2CxOP_RSTA ((uint32_t)0x00000008) -#define I2CxOP_SREN ((uint32_t)0x00000002) -#define I2CxOP_MFACK ((uint32_t)0x00000001) -#define I2CxOP_INIT ((uint32_t)0x00000084) -#define I2CxIE_CLEAR ((uint32_t)0x00000000) -#define I2CxPRS_PRCK ((uint32_t)0x0000000F) -#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) -#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) -#define I2CAR_SA_MASK ((uint32_t)0x000000FE) -#define I2CxSR_TRX ((uint32_t)0x00000040) -#define I2CxOP_SAST ((uint32_t)0x00000020) -#define I2CxIE_INTI2C ((uint32_t)0x00000001) -#define I2C_NO_DATA (0) -#define I2C_READ_ADDRESSED (1) -#define I2C_WRITE_ADDRESSED (3) -#define I2C_ACK (1) -#define I2C_TIMEOUT (100000) -// DAC -#define DAC_START ((uint32_t)0x00000001) -#define DAC_STOP ((uint32_t)0x00000000) -// ADC -#define ADC_12BIT_RANGE 0xFFF -#define ADC_SCLK_1 ((uint32_t)0x00000000) -#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) -#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) -#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) -#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) -#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) -#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) -#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) -#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) -#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) -#define ADxST_SNGF_RUN ((uint32_t)0x00000004) -#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) -#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) -#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) -#define ADC_SAMPLING_PERIOD_3V ((uint32_t)0x00000008) -#define ADC_MOD2_TMPM3Hx ((uint32_t)0x00000300) -#define ADC_MOD1_AVDD5_3V ((uint32_t)0x0000B001) -// Timer & PWM -#define T32A_INT_MASK ((uint32_t)0x0000000F) -#define T32A_MODE_32 ((uint32_t)0x00000001) -#define T32A_PRSCLx_32 ((uint32_t)0x30000000) -#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) -#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) -#define T32A_COUNT_STOP ((uint32_t)0x00000004) -#define T32A_COUNT_START ((uint32_t)0x00000002) -#define T32A_RUN_ENABLE ((uint32_t)0x00000001) -#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) -#define T32A_COUNT_DONT_START ((uint32_t)0x00000000) -#define T32A_RUN_DISABLE ((uint32_t)0x00000000) -#define T32A_WBF_ENABLE ((uint32_t)0x00100000) -#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) -#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) -#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) -#define T32A_OCR_DISABLE ((uint32_t)0x00000000) -#define DEFAULT_PERIOD 0.02f // 20ms -#define DEFAULT_CLOCK_DIVISION 32 -#define MAX_COUNTER_16B 0xFFFF -// UART -#define UART_ENABLE_RX ((uint32_t)0x00000001) -#define UART_ENABLE_TX ((uint32_t)0x00000002) -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) -#define UART_PLESCALER_1 ((uint32_t)0x00000000) -#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) -#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) -#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) -#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) -#define UART_RANGE_K_MIN ((uint32_t)0x00000000) -#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) -#define UART_RANGE_N_MIN ((uint32_t)0x00000001) -#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) -#define UART_NUM 6 - -typedef struct { - uint32_t ken; // Enable/Disable Division Definition - uint32_t brk; // Division Value K - uint32_t brn; // Division Value N -} uart_boudrate_t; - -// Sleep -#define CG_STBY_MODE_IDLE 0x0 -#define CG_STBY_MODE_STOP1 0x1 -#define EXTERNEL_OSC_MASK 0xFFFFFFF9 -#define IHOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) -#define IHOSC_CFG_CLOCK ((uint64_t)(10000000)) -#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000) - -#endif // __GPIO_INCLUDE_H diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_irq_api.c deleted file mode 100644 index f1beda4921..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_irq_api.c +++ /dev/null @@ -1,435 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "gpio_include.h" -#include "mbed_critical.h" - -const PinMap PinMap_GPIO_IRQ[] = { - {PC0, GPIO_IRQ_00, PIN_DATA(0, 0)}, - {PC1, GPIO_IRQ_01, PIN_DATA(0, 0)}, - {PC2, GPIO_IRQ_02, PIN_DATA(0, 0)}, - {PB1, GPIO_IRQ_03, PIN_DATA(0, 0)}, - {PJ4, GPIO_IRQ_04, PIN_DATA(0, 0)}, - {PK1, GPIO_IRQ_05, PIN_DATA(0, 0)}, - {PH3, GPIO_IRQ_06, PIN_DATA(0, 0)}, - {PA6, GPIO_IRQ_07, PIN_DATA(0, 0)}, - {PL3, GPIO_IRQ_08, PIN_DATA(0, 0)}, - {PM2, GPIO_IRQ_09, PIN_DATA(0, 0)}, - {PN3, GPIO_IRQ_10, PIN_DATA(0, 0)}, - {PA7, GPIO_IRQ_11, PIN_DATA(0, 0)}, - {PL4, GPIO_IRQ_12, PIN_DATA(0, 0)}, - {PK7, GPIO_IRQ_13, PIN_DATA(0, 0)}, - {PP3, GPIO_IRQ_14, PIN_DATA(0, 0)}, - {PM6, GPIO_IRQ_15, PIN_DATA(0, 0)}, - {PB7, GPIO_IRQ_16, PIN_DATA(0, 0)}, - {PV2, GPIO_IRQ_17_18, PIN_DATA(0, 0)}, - {PH4, GPIO_IRQ_19_22, PIN_DATA(0, 0)}, - {PT0, GPIO_IRQ_23_26, PIN_DATA(0, 0)}, - {PG2, GPIO_IRQ_27_28, PIN_DATA(0, 0)}, - {PT7, GPIO_IRQ_29, PIN_DATA(0, 0)}, - {PU0, GPIO_IRQ_30_31, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; -static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState); -static cg_intactivestate CurrentState; -static void INT_IRQHandler(PinName pin, uint32_t index); - -// Initialize gpio IRQ pin -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - // Get gpio interrupt ID - obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - - // Disable interrupt by CPU - core_util_critical_section_enter(); - - // Calculate port and pin position - obj->port = (PortName)PIN_PORT(pin); - obj->pin = pin; - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_CLR(port_base, bit); - // Enable gpio interrupt function - pinmap_pinout(pin, PinMap_GPIO_IRQ); - - // Get GPIO irq source - switch (obj->irq_id) { - case GPIO_IRQ_00: - obj->irq_src = cg_int_src_01; - break; - case GPIO_IRQ_01: - obj->irq_src = cg_int_src_02; - break; - case GPIO_IRQ_02: - obj->irq_src = cg_int_src_03; - break; - case GPIO_IRQ_03: - obj->irq_src = cg_int_src_04; - break; - case GPIO_IRQ_04: - obj->irq_src = cg_int_src_05; - break; - case GPIO_IRQ_05: - obj->irq_src = cg_int_src_06; - break; - case GPIO_IRQ_06: - obj->irq_src = cg_int_src_07; - break; - case GPIO_IRQ_07: - obj->irq_src = cg_int_src_08; - break; - case GPIO_IRQ_08: - obj->irq_src = cg_int_src_09; - break; - case GPIO_IRQ_09: - obj->irq_src = cg_int_src_0a; - break; - case GPIO_IRQ_10: - obj->irq_src = cg_int_src_0b; - break; - case GPIO_IRQ_11: - obj->irq_src = cg_int_src_0c; - break; - case GPIO_IRQ_12: - obj->irq_src = cg_int_src_0d; - break; - case GPIO_IRQ_13: - obj->irq_src = cg_int_src_0e; - break; - case GPIO_IRQ_14: - obj->irq_src = cg_int_src_0f; - break; - case GPIO_IRQ_15: - obj->irq_src = cg_int_src_10; - break; - case GPIO_IRQ_16: - obj->irq_src = cg_int_src_11; - break; - case GPIO_IRQ_17_18: - obj->irq_src = cg_int_src_12; - break; - case GPIO_IRQ_19_22: - obj->irq_src = cg_int_src_14; - break; - case GPIO_IRQ_23_26: - obj->irq_src = cg_int_src_18; - break; - case GPIO_IRQ_27_28: - obj->irq_src = cg_int_src_1c; - break; - case GPIO_IRQ_29: - obj->irq_src = cg_int_src_1e; - break; - case GPIO_IRQ_30_31: - obj->irq_src = cg_int_src_1f; - break; - default: - break; - } - - // Save irq handler - hal_irq_handler[obj->irq_src] = handler; - - // Save irq id - channel_ids[obj->irq_src] = id; - - // Initialize interrupt event as both edges detection - obj->event = cg_int_active_state_both_edges; - CurrentState = cg_int_active_state_both_edges; - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE); - - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id); - - core_util_critical_section_exit(); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Clear gpio_irq - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Reset interrupt handler - hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; -} - -// Set interrupt event of gpio_irq object -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - //Disable GPIO interrupt on obj - gpio_irq_disable(obj); - if (enable) { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_both_edges)) { - obj->event = cg_int_active_state_both_edges; - } else { - obj->event = cg_int_active_state_rising; - } - } else if (event == IRQ_FALL) { - if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_both_edges)) { - obj->event = cg_int_active_state_both_edges; - } else { - obj->event = cg_int_active_state_falling; - } - } else { - error("Not supported event\n"); - } - } else { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_invalid)) { - obj->event = cg_int_active_state_invalid; - } else { - obj->event = cg_int_active_state_falling; - } - } else if (event == IRQ_FALL) { - if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_invalid)) { - obj->event = cg_int_active_state_invalid; - } else { - obj->event = cg_int_active_state_rising; - } - } else { - error("Not supported event\n"); - } - } - CurrentState = obj->event; - // Calculate port and pin position - bit = PIN_POS(obj->pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - - if (obj->event != cg_int_active_state_invalid ) { - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE); - BITBAND_PORT_CLR(port_base, bit); - } else { - BITBAND_PORT_SET(port_base, bit); - } - //Enable GPIO interrupt on obj - gpio_irq_enable(obj); -} - -// Enable gpio_irq object -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear and Enable gpio_irq object - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - NVIC_EnableIRQ((IRQn_Type)obj->irq_id); -} - -// Disable gpio_irq object -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable gpio_irq object - NVIC_DisableIRQ((IRQn_Type)obj->irq_id); -} - -static void INT_IRQHandler(PinName pin, uint32_t index) -{ - int port = 0; - uint8_t bit = 0; - uint32_t data = 0; - uint32_t port_base = 0; - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - // Clear interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_01 + index), CurrentState, DISABLE); - - port_base = BITBAND_PORT_BASE(port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_READ(data, port_base, bit); - - switch (data) { - // Falling edge detection - case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); - break; - // Rising edge detection - case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); - break; - default: - break; - } - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)(cg_int_src_01 + index)); - - // Enable interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_01 + index), CurrentState, ENABLE); -} - -void INT00_IRQHandler(void) -{ - INT_IRQHandler(PC0, 0); -} - -void INT01_IRQHandler(void) -{ - INT_IRQHandler(PC1, 1); -} - -void INT02_IRQHandler(void) -{ - INT_IRQHandler(PC2, 2); -} - -void INT03_IRQHandler(void) -{ - INT_IRQHandler(PB1, 3); -} - -void INT04_IRQHandler(void) -{ - INT_IRQHandler(PJ4, 4); -} - -void INT05_IRQHandler(void) -{ - INT_IRQHandler(PK1, 5); -} - -void INT06_IRQHandler(void) -{ - INT_IRQHandler(PH3, 6); -} - -void INT07_IRQHandler(void) -{ - INT_IRQHandler(PA6, 7); -} - -void INT08_IRQHandler(void) -{ - INT_IRQHandler(PL3, 8); -} - -void INT09_IRQHandler(void) -{ - INT_IRQHandler(PM2, 9); -} - -void INT10_IRQHandler(void) -{ - INT_IRQHandler(PN3, 10); -} - -void INT11_IRQHandler(void) -{ - INT_IRQHandler(PA7, 11); -} - -void INT12_IRQHandler(void) -{ - INT_IRQHandler(PL4, 12); -} - -void INT13_IRQHandler(void) -{ - INT_IRQHandler(PK7, 13); -} - -void INT14_IRQHandler(void) -{ - INT_IRQHandler(PP3, 14); -} - -void INT15_IRQHandler(void) -{ - INT_IRQHandler(PM6, 15); -} - -void INT16_IRQHandler(void) -{ - INT_IRQHandler(PB7, 16); -} - -void INT17_18_IRQHandler(void) -{ - INT_IRQHandler(PV2, 17); -} - -void INT19_22_IRQHandler(void) -{ - INT_IRQHandler(PH4, 19); -} - -void INT23_26_IRQHandler(void) -{ - INT_IRQHandler(PT0, 23); -} - -void INT27_28_IRQHandler(void) -{ - INT_IRQHandler(PG2, 27); -} - -void INT29_IRQHandler(void) -{ - INT_IRQHandler(PT7, 29); -} - -void INT30_31_IRQHandler(void) -{ - INT_IRQHandler(PU0, 30); -} - -static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState) -{ - __IO uint8_t *p_imc; - - if (intsource < 3U || intsource == 13U) { - if (intsource == 13U) { - intsource = (cg_intsrc)3U; - } - p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } else { - if (intsource > 13U) { - intsource -= 4; - } else { - intsource -= 3; - } - p_imc = (__IO uint8_t *)(&TSB_IB->IMC066 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } - // Dummy read is need - { - __IO uint8_t imc = *p_imc; - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_object.h deleted file mode 100644 index a34e5d2dc8..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/gpio_object.h +++ /dev/null @@ -1,97 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) -#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) -#define GPIO_BIT_ALL ((uint8_t)0xFF) - -typedef enum { - cg_int_src_01 = 0U, - cg_int_src_02, - cg_int_src_03, - cg_int_src_04, - cg_int_src_05, - cg_int_src_06, - cg_int_src_07, - cg_int_src_08, - cg_int_src_09, - cg_int_src_0a, - cg_int_src_0b, - cg_int_src_0c, - cg_int_src_0d, - cg_int_src_0e, - cg_int_src_0f, - cg_int_src_10, - cg_int_src_11, - cg_int_src_12, - cg_int_src_13, - cg_int_src_14, - cg_int_src_15, - cg_int_src_16, - cg_int_src_17, - cg_int_src_18, - cg_int_src_19, - cg_int_src_1a, - cg_int_src_1b, - cg_int_src_1c, - cg_int_src_1d, - cg_int_src_1e, - cg_int_src_1f, - cg_int_src_20 -} cg_intsrc; - -typedef enum { - cg_int_active_state_l = 0x00U, - cg_int_active_state_h = 0x02U, - cg_int_active_state_falling = 0x04U, - cg_int_active_state_rising = 0x06U, - cg_int_active_state_both_edges = 0x08U, - cg_int_active_state_invalid = 0x0AU -} cg_intactivestate; - -typedef struct { - PinName pin; - uint32_t mask; - PortName port; -} gpio_t; - -struct gpio_irq_s { - uint32_t mask; - PortName port; - PinName pin; - uint32_t irq_id; - cg_intactivestate event; - cg_intsrc irq_src; -}; - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return (obj->pin != (PinName)NC); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/i2c_api.c deleted file mode 100644 index 926f650d05..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/i2c_api.c +++ /dev/null @@ -1,688 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" - -#if DEVICE_I2C_ASYNCH -#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) -#else -#define I2C_S(obj) (struct i2c_s *) (obj) -#endif - -static const PinMap PinMap_I2C_SDA[] = { - {PC1, I2C_0, PIN_DATA(1, 2)}, - {PA5, I2C_1, PIN_DATA(1, 2)}, - {PL1, I2C_2, PIN_DATA(3, 2)}, - {PT0, I2C_3, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PC0, I2C_0, PIN_DATA(1, 2)}, - {PA4, I2C_1, PIN_DATA(1, 2)}, - {PL0, I2C_2, PIN_DATA(3, 2)}, - {PT1, I2C_3, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -// Clock setting structure definition -typedef struct { - uint32_t sck; - uint32_t prsck; -} I2C_clock_setting_t; - -// SCK Divider value table -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { - 20, 24, 32, 48, 80, 144, 272, 528 -}; - -I2C_clock_setting_t clk; -static uint32_t start_flag = 0; - -#if DEVICE_I2C_ASYNCH -enum { - I2C_TRANSFER_STATE_IDLE = 0U, - I2C_TRANSFER_STATE_START, - I2C_TRANSFER_STATE_WRITE, - I2C_TRANSFER_STATE_RESTART, - I2C_TRANSFER_STATE_READ, - I2C_TRANSFER_STATE_MAX -} TransferState; - -typedef struct { - IRQn_Type i2c; -} i2c_irq_t; - -static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = { - { INTI2C0_IRQn } -}; - -static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = { - { INTI2C1_IRQn } -}; - -static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = { - { INTI2C2_IRQn } -}; - -static const i2c_irq_t I2C_CH3_IRQN_TBL[1] = { - { INTI2C3_IRQn } -}; -#endif - -static int32_t wait_status(i2c_t *p_obj); -static void i2c_start_bit(i2c_t *obj); - -#if DEVICE_I2C_ASYNCH -static void disable_irq(uint32_t irqn); -static void clear_irq(uint32_t irqn); -static void i2c_irq_handler(i2c_t *obj); -#endif - -// Initialize the I2C peripheral. It sets the default parameters for I2C -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - struct i2c_s *obj_s = I2C_S(obj); - MBED_ASSERT(obj_s != NULL); - - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - - MBED_ASSERT((int)i2c_name != NC); - - switch (i2c_name) { - case I2C_0: - TSB_CG_FSYSENB_IPENB11 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - obj_s->i2c = TSB_I2C0; -#if DEVICE_I2C_ASYNCH - obj_s->irqn = (uint32_t)&I2C_CH0_IRQN_TBL; -#endif - break; - case I2C_1: - TSB_CG_FSYSENB_IPENB12 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - obj_s->i2c = TSB_I2C1; -#if DEVICE_I2C_ASYNCH - obj_s->irqn = (uint32_t)&I2C_CH1_IRQN_TBL; -#endif - break; - case I2C_2: - TSB_CG_FSYSENB_IPENB13 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; - obj_s->i2c = TSB_I2C2; -#if DEVICE_I2C_ASYNCH - obj_s->irqn = (uint32_t)&I2C_CH2_IRQN_TBL; -#endif - break; - case I2C_3: - TSB_CG_FSYSENB_IPENB14 = ENABLE; - TSB_CG_FSYSENA_IPENA15 = ENABLE; - obj_s->i2c = TSB_I2C3; -#if DEVICE_I2C_ASYNCH - obj_s->irqn = (uint32_t)&I2C_CH3_IRQN_TBL; -#endif - break; - default: - error("I2C is not available"); - break; - } -#if DEVICE_I2C_ASYNCH - obj_s->state = I2C_TRANSFER_STATE_IDLE; -#endif - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - pin_mode(sda, PullUp); - - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pin_mode(scl, PullUp); - - i2c_reset(obj); - i2c_frequency(obj, 100000); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->IE = I2CxIE_CLEAR; -} - -// Configure the I2C frequency -void i2c_frequency(i2c_t *obj, int hz) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint64_t sck; - uint64_t tmp_sck; - uint64_t prsck; - uint64_t tmp_prsck; - uint64_t fscl; - uint64_t tmp_fscl; - uint64_t fx; - - SystemCoreClockUpdate(); - - if (hz <= 1000000) { - sck = tmp_sck = 0; - prsck = tmp_prsck = 1; - fscl = tmp_fscl = 0; - for (prsck = 1; prsck <= 32; prsck++) { - fx = ((uint64_t)SystemCoreClock / prsck); - if ((fx < 20000000U) && (fx > 6666666U)) { - for (sck = 0; sck <= 7; sck++) { - fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - tmp_sck = sck; - tmp_prsck = (prsck < 32) ? prsck : 0; - } - } - } - } - clk.sck = (uint32_t)tmp_sck; - clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0; - } - - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); -} - -int i2c_start(i2c_t *obj) -{ - start_flag = 1; // Start Condition - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t timeout = I2C_TIMEOUT; - - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - - while ((obj_s->i2c->SR & I2CxSR_BB) == I2CxSR_BB) { - if (timeout == 0) { - break; - } - timeout--; - } - - return 0; -} - -void i2c_reset(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->i2c->CR2 = I2CxCR2_SWRES_10; - obj_s->i2c->CR2 = I2CxCR2_SWRES_01; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - int32_t pdata = 0; - - if (length > 0) { - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { - while (count < length) { - pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - } - - return result; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - - start_flag = 1; // Start Condition - - if (i2c_byte_write(obj, address) == I2C_ACK) { - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - - return result; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = 0; - - obj_s->i2c->ST = I2CxST_CLEAR; - - if (last) { - obj_s->i2c->OP |= I2CxOP_MFACK; - } else { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } - - obj_s->i2c->DBR = (0 & I2CxDBR_DB_MASK); - - if (wait_status(obj) < 0) { - result = -1; - } else { - result = (int32_t)(obj_s->i2c->DBR & I2CxDBR_DB_MASK); - } - - return result; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = 0; - - obj_s->i2c->ST = I2CxST_CLEAR; - if (start_flag == 1) { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - i2c_start_bit(obj); - start_flag = 0; - } else { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - } - - if (wait_status(obj) < 0) { - return -1; - } - - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - result = 1; - } else { - result = 0; - } - - return result; -} - -static void i2c_start_bit(i2c_t *obj) // Send START command -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t opreg = 0; - - opreg = obj_s->i2c->OP; - opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); - - if ((obj_s->i2c->SR & I2CxSR_BB)) { - opreg |= I2CxOP_SREN; - } - - obj_s->i2c->OP = opreg; - obj_s->i2c->CR2 |= I2CxCR2_START_CONDITION; -} - -static int32_t wait_status(i2c_t *p_obj) -{ - struct i2c_s *obj_s = I2C_S(p_obj); - volatile int32_t timeout; - timeout = I2C_TIMEOUT; - - while (!((obj_s->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) { - if ((timeout--) == 0) { - return (-1); - } - } - - return 0; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - struct i2c_s *obj_s = I2C_S(obj); - if (enable_slave) { - i2c_reset(obj); - obj_s->i2c->OP = I2CxOP_SLAVE_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - obj_s->i2c->CR2 = I2CxCR2_INIT; - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->AR = (obj_s->address & I2CAR_SA_MASK); - obj_s->i2c->IE = I2CxIE_INTI2C; - } else { - i2c_reset(obj); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->ST = I2CxST_CLEAR; - } -} - -int i2c_slave_receive(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = I2C_NO_DATA; - - if ((obj_s->i2c->ST & I2CxST_I2C) && (obj_s->i2c->OP & I2CxOP_SAST)) { - // Detect and clear arbitration lost. - if(!(obj_s->i2c->SR & 0x08)) { - obj_s->i2c->DBR = 0x00; - } - - if ((obj_s->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) { - result = I2C_READ_ADDRESSED; - } else { - result = I2C_WRITE_ADDRESSED; - } - } - - return (result); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t count = 0; - - while (count < length) { - int32_t pdata = i2c_byte_read(obj, 0); - if ((obj_s->i2c->SR & I2CxSR_TRX)) { - return (count); - } else { - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - } - - i2c_slave_mode(obj,1); - - return (count); -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int32_t count = 0; - - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - - i2c_slave_mode(obj,1); - - return (count); -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->address = address & I2CAR_SA_MASK; - i2c_slave_mode(obj,1); -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#if DEVICE_I2C_ASYNCH - -void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, - uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) -{ - struct i2c_s *obj_s = I2C_S(obj); - i2c_irq_t *p_irqn = (i2c_irq_t *)obj_s->irqn; - - if(obj_s->state == I2C_TRANSFER_STATE_IDLE) { - // Disable and clear interrupt flag. - disable_irq(obj_s->irqn); - obj_s->i2c->IE = I2CxIE_CLEAR; - obj_s->i2c->ST = I2CxST_CLEAR; - clear_irq(obj_s->irqn); - - // Store given buffer data and lenght into I2C object and set state as I2C_TRANSFER_STATE_START. - obj_s->address = address; - obj_s->event = 0; - obj_s->stop = stop; - obj->tx_buff.buffer = (void *)tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - obj->rx_buff.buffer = rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - obj_s->state = I2C_TRANSFER_STATE_START; - - // Enable I2C interrupt. - obj_s->i2c->IE = I2CxIE_INTI2C; - - if ((tx_length == 0) && (rx_length != 0)) { - i2c_start_bit(obj); - obj_s->i2c->DBR = ((address | 1U) & I2CxDBR_DB_MASK); - } else { - i2c_start_bit(obj); - obj_s->i2c->DBR = (address & I2CxDBR_DB_MASK); - } - - // Enable I2C interrupr in NVIC. - NVIC_EnableIRQ(p_irqn->i2c); - NVIC_SetVector(p_irqn->i2c, handler); - } -} - -uint32_t i2c_irq_handler_asynch(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - i2c_irq_handler(obj); - return (obj_s->event & I2C_EVENT_ALL); -} - -uint8_t i2c_active(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint8_t ret_val = 0; - - if ((obj_s->i2c->CR2 & 0x08)) { - ret_val = 1; - } - return ret_val; -} - -void i2c_abort_asynch(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - - // Generate Stop condition on I2C bus - i2c_stop(obj); - - // Set state as idle and disable I2C interrupt. - obj_s->state = I2C_TRANSFER_STATE_IDLE; - disable_irq(obj_s->irqn); - clear_irq(obj_s->irqn); - obj_s->i2c->IE = I2CxIE_CLEAR; - - // Given I2C Software Reset - i2c_reset(obj); - - // Re-Store the I2C configuration - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->ST = I2CxST_CLEAR; - -} - -static void disable_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - NVIC_DisableIRQ(p_irqn->i2c); -} - -static void clear_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - NVIC_ClearPendingIRQ(p_irqn->i2c); -} - -static void i2c_irq_handler(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->i2c->ST = I2CxST_CLEAR; - - switch(obj_s->state) { - case I2C_TRANSFER_STATE_START: - // Check ACK for sent slave address. - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - if(obj->tx_buff.length != (unsigned long)0) { // Check Tx buff length. - obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK; - obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t); - obj->tx_buff.pos++; - obj_s->state = I2C_TRANSFER_STATE_WRITE; - } else if(obj->rx_buff.length != 0) { // Check Rx buff length. - if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } else { - obj_s->i2c->OP |= I2CxOP_MFACK; - } - obj_s->i2c->DBR = 0x00; - obj_s->state = I2C_TRANSFER_STATE_READ; - } else { // Return transfer complete because of not given any Tx/Rx data. - obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - } else { // Return "No Slave", Because of Did not get any ACK for sent slave address. - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - case I2C_TRANSFER_STATE_WRITE: - if(obj->tx_buff.pos < obj->tx_buff.length) { - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK; - obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t); - obj->tx_buff.pos++; - } else { - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - } else if(obj->rx_buff.length != 0) { - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - i2c_start_bit(obj); - obj_s->i2c->DBR = ((obj_s->address | 1U) & I2CxDBR_DB_MASK); - obj_s->state = I2C_TRANSFER_STATE_RESTART; - } else { - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - } else { - if(obj_s->stop) { - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - } - obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - case I2C_TRANSFER_STATE_RESTART: - if(!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - // Set ACK/NACK - if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } else { - obj_s->i2c->OP |= I2CxOP_MFACK; - } - obj_s->i2c->DBR = 0x00; - obj_s->state = I2C_TRANSFER_STATE_READ; - } else { - obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - case I2C_TRANSFER_STATE_READ: - if(obj->rx_buff.pos < obj->rx_buff.length) { - *((uint8_t *)obj->rx_buff.buffer) = (uint8_t)obj_s->i2c->DBR & I2CxDBR_DB_MASK; - obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + sizeof(uint8_t); - obj->rx_buff.pos++; - } - if(obj->rx_buff.pos < obj->rx_buff.length) { - // Set ACK/NACK - if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } else { - obj_s->i2c->OP |= I2CxOP_MFACK; - } - obj_s->i2c->DBR = 0x00; - } else { - if(obj_s->stop) { - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - } - obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; - obj_s->state = I2C_TRANSFER_STATE_IDLE; - } - break; - default: - break; - } - if(obj_s->state == I2C_TRANSFER_STATE_IDLE) { - disable_irq(obj_s->irqn); - obj_s->i2c->IE = I2CxIE_CLEAR; - } -} - -#endif // #if DEVICE_I2C_ASYNCH - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/objects.h deleted file mode 100644 index c14c662e80..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/objects.h +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "PortNames.h" -#include "PeripheralNames.h" -#include "txz_tspi.h" -#include "PinNames.h" -#include "TMPM3HQ.h" -#include "gpio_include.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t BaudRate; - uint32_t DataBits; - uint32_t StopBits; - uint32_t Parity; - uint32_t Mode; - uint32_t FlowCtrl; -} uart_inittypedef_t; - -struct port_s { - PortName port; - uint32_t mask; -}; - -typedef struct { - uint8_t PinDATA; - uint8_t PinCR; - uint8_t PinFR[7]; - uint8_t PinOD; - uint8_t PinPUP; - uint8_t PinPDN; - uint8_t PinIE; -} gpio_regtypedef_t; - -typedef struct { - __IO uint32_t DATA; - __IO uint32_t CR; - __IO uint32_t FR[7]; - uint32_t RESERVED0[1]; - __IO uint32_t OD; - __IO uint32_t PUP; - __IO uint32_t PDN; - uint32_t RESERVED1; - __IO uint32_t IE; -} TSB_Port_TypeDef; - -struct serial_s { - PinName pin; - uint32_t index; - TSB_UART_TypeDef *UARTx; - uart_inittypedef_t uart_config; -}; - -struct analogin_s { - PinName pin; - ADCName adc; - TSB_AD_TypeDef *obj; -}; - -struct dac_s { - DACName dac; - TSB_DA_TypeDef *handler; -}; - -struct pwmout_s { - PinName pin; - TSB_T32A_TypeDef *channel; - uint16_t trailing_timing; - uint16_t leading_timing; - uint16_t divisor; - float period; -}; - -struct i2c_s { - uint32_t address; - IRQn_Type IRQn; - TSB_I2C_TypeDef *i2c; -#if DEVICE_I2C_ASYNCH - uint32_t irqn; - uint32_t state; - uint32_t event; - uint32_t stop; -#endif -}; - -struct spi_s { - tspi_t p_obj; - SPIName module; - uint8_t bits; - PinName Slave_SCK; -#if DEVICE_SPI_ASYNCH - uint32_t irqn; - uint32_t event; - uint32_t max_size; - uint32_t state; -#endif -}; - -struct flash_s { - int flash_inited; -}; - -#define HAL_CRC_IS_SUPPORTED(polynomial, width) (((width) == 16 && (polynomial) == 0x1021) || \ - ((width) == 32 && (polynomial) == 0x04C11DB7)) - -extern const gpio_regtypedef_t GPIO_SFRs[]; -extern const uint32_t GPIO_Base[]; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/tmpm3hq_fc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/tmpm3hq_fc.c deleted file mode 100644 index 4a6316f3f1..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/tmpm3hq_fc.c +++ /dev/null @@ -1,623 +0,0 @@ -/** - ******************************************************************************* - * @file tmpm3hq_fc.c - * @brief Flash_Userboot Sample Application. - * @version V1.0.1.0 - * $Date:: 2016-11-28 08:16:17 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. - * - * (C)Copyright TOSHIBA CORPORATION 2016 All rights reserved - ******************************************************************************* - */ -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include -#include "tmpm3hq_fc.h" -#include "TMPM3HQ.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @defgroup Flash_Userboot Flash_Userboot Sample Appli - * @{ - */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ -#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ -#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ -#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */ -#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ -#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ -#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ - -/* FCSR0 register */ -#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area0 */ -#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) /*!< RW, Selects area0 */ -#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFFF8FFF8UL) /*!< RW, Selects area0 */ -#define FC_AREASEL_WRITE_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode */ - -static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { - (0x5E000000UL), /*!< CODE FLASH Page0 */ - (0x5E001000UL), /*!< CODE FLASH Page1 */ - (0x5E002000UL), /*!< CODE FLASH Page2 */ - (0x5E003000UL), /*!< CODE FLASH Page3 */ - (0x5E004000UL), /*!< CODE FLASH Page4 */ - (0x5E005000UL), /*!< CODE FLASH Page5 */ - (0x5E006000UL), /*!< CODE FLASH Page6 */ - (0x5E007000UL), /*!< CODE FLASH Page7 */ - (0x5E008000UL), /*!< CODE FLASH Page8 */ - (0x5E009000UL), /*!< CODE FLASH Page9 */ - (0x5E00A000UL), /*!< CODE FLASH Page10 */ - (0x5E00B000UL), /*!< CODE FLASH Page11 */ - (0x5E00C000UL), /*!< CODE FLASH Page12 */ - (0x5E00D000UL), /*!< CODE FLASH Page13 */ - (0x5E00E000UL), /*!< CODE FLASH Page14 */ - (0x5E00F000UL), /*!< CODE FLASH Page15 */ - (0x5E010000UL), /*!< CODE FLASH Page16 */ - (0x5E011000UL), /*!< CODE FLASH Page17 */ - (0x5E012000UL), /*!< CODE FLASH Page18 */ - (0x5E013000UL), /*!< CODE FLASH Page19 */ - (0x5E014000UL), /*!< CODE FLASH Page20 */ - (0x5E015000UL), /*!< CODE FLASH Page21 */ - (0x5E016000UL), /*!< CODE FLASH Page22 */ - (0x5E017000UL), /*!< CODE FLASH Page23 */ - (0x5E018000UL), /*!< CODE FLASH Page24 */ - (0x5E019000UL), /*!< CODE FLASH Page25 */ - (0x5E01A000UL), /*!< CODE FLASH Page26 */ - (0x5E01B000UL), /*!< CODE FLASH Page27 */ - (0x5E01C000UL), /*!< CODE FLASH Page28 */ - (0x5E01D000UL), /*!< CODE FLASH Page29 */ - (0x5E01E000UL), /*!< CODE FLASH Page30 */ - (0x5E01F000UL) /*!< CODE FLASH Page31 */ -}; - -/** - * @} - */ /* End of group Flash_Userboot_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ -/** - * @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef - * @{ - */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables - * @{ - */ -/** - * @} - */ /* End of group Flash_Userboot_Private_variables */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions - * @{ - */ -__STATIC_INLINE TXZ_Result fc_enable_areasel(void); -__STATIC_INLINE TXZ_Result fc_disable_areasel(void); -static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -static TXZ_Result fc_verify_check(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -static void fc_erase_command(uint32_t* flash_top_address, uint32_t* erase_top_address, fc_erase_kind_t kind); - -/*--------------------------------------------------*/ -/** - * @brief Enables the AREA0. - * @param - - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function write the FCAREASEL regiset. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -__STATIC_INLINE TXZ_Result fc_enable_areasel(void) -{ - TXZ_Result retval = TXZ_ERROR; - - /* Writes the FCKER register the KEYCODE. */ - TSB_FC->KCR = FC_KCR_KEYCODE; - - /* Selects the area0 */ - { - uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; - TSB_FC->AREASEL = reg | FC_AREASEL_AREA0; - } - - /* Confirms the FCAREASEL register the SSF0 was set. */ - while(1){ - uint32_t i = TSB_FC->AREASEL; - if((i & FC_AREASEL_WRITE_MODE) == FC_AREASEL_WRITE_MODE){ - retval = TXZ_SUCCESS; - break; - } - } - - return(retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Disables the AREA0. - * @param - - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function write the FCAREASEL regiset. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -__STATIC_INLINE TXZ_Result fc_disable_areasel(void) -{ - TXZ_Result retval = TXZ_ERROR; - - /* Writes the FCKER register the KEYCODE. */ - TSB_FC->KCR = FC_KCR_KEYCODE; - - /* Selects the area0 */ - { - uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; - TSB_FC->AREASEL = reg | FC_AREASEL_EXPECT_AREA0; - } - - /* Confirms the SSF0 of the FCAREASEL register is not set. */ - while(1){ - uint32_t i = TSB_FC->AREASEL; - if((i & FC_AREASEL_WRITE_MODE) != FC_AREASEL_WRITE_MODE){ - retval = TXZ_SUCCESS; - break; - } - } - - return(retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Writes data of the Flash ROM. - * @param uint32_t* : src_address - * @param uint32_t* : dst_address - * @param uint32_t : size - * @return - - * @note It works in the inner RAM. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size) -{ - TXZ_Result retval; - volatile uint32_t* addr1 = (uint32_t *) (FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); - volatile uint32_t* addr2 = (uint32_t *) (FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); - volatile uint32_t* addr3 = (uint32_t *) ((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP); - uint32_t* source = (uint32_t *) src_address; - - /* Enables the AREA0. Write Mode. */ - retval = fc_enable_areasel(); - - if(retval == TXZ_SUCCESS){ - uint32_t i; - - *addr1 = (0x000000AAUL); /* bus cycle 1 */ - *addr2 = (0x00000055UL); /* bus cycle 2 */ - *addr1 = (0x000000A0UL); /* bus cycle 3 */ - for(i=(0UL); iSR0 & (uint32_t)status; - - /* Confirms the specific status of the flash ROM */ - if(work32 == (uint32_t)status){ - retval = TXZ_DONE; - } - - return (retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Auto write command of the code flash ROM. - * @param uint32_t* : src_address - * @param uint32_t* : dst_address - * @param uint32_t : size - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function writes 16bytes data to the code Flash ROM. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size) -{ - TXZ_Result retval = TXZ_SUCCESS; - - /* Checks the code Flash ROM status */ - if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){ - - uint32_t i; - /* Checks the code Flash ROM status */ - for(i=0;iinit.cnt1.trxe)); - assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); - assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); - assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); - assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); - assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); - /* Check the parameter of TTSPIxCR2 */ - assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); - assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); - assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); - assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); - assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); - assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); - assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); - assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); - assert_param(check_param_err_int(p_obj->init.cnt2.interr)); - assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); - assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); - /* Check the parameter of TTSPIxBR */ - assert_param(check_param_input_clock(p_obj->init.brd.brck)); - assert_param(check_param_input_divider(p_obj->init.brd.brs)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* TSPI Software Reset */ - p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); - p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE); - - /* Wait for 2 clocks of reset completion */ - __NOP(); - __NOP(); - - /* Control1 Register1 Set*/ - p_obj->p_instance->CR1 = 0x00001C01U; - p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ - p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims| p_obj->init.cnt1.trgen); - /* Control2 Register Set */ - p_obj->p_instance->CR2 = 0x00E10100U; - p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ - p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe |p_obj->init.cnt2.inttxwe | \ - p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare ); - - /* Control3 Register is FIFO clear, do nothing */ - - /* Baudrate Register Set */ - p_obj->p_instance->BR = 0U; - p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); - - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = 0x8800C400U; - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = 0U; - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - - /* not created */ - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the TSPI object. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_deinit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Disable the selected TSPI peripheral */ - p_obj->p_instance->CR0 |= TSPI_DISABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data.. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - - /* Transmit data check*/ - if((p_info->tx8.p_data == TSPI_NULL ) || (p_info->tx8.num == 0)) - { - p_obj->errcode = DATABUFEMPERR; - result = TXZ_ERROR; - return (result); - } - - /* FIFO Cear */ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - /* Transmit Data write to D ata Register */ - while (p_info->tx8.num > 0) - { - /* Check the current fill level */ - if(((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) - { - *((__IO uint8_t*)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); - p_info->tx8.num--; - /* check complete transmit */ - if((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - else - { - /* Enable TSPI Transmission Control */ - if(p_info->tx8.num==0){ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - return (result); - } - else { - /* Next transmit data sending */ - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - } - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - - } - /* check complete transmit */ - while((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - /* Check Error Flag */ - tspi_get_error(p_obj, &err); - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - - if(p_obj->errcode == NOERROR) { - //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - }else{ - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - uint32_t count = 0; - uint32_t index = 0; -// uint32_t level = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - /* Transmit data check*/ - if((p_info->rx8.p_data == TSPI_NULL ) || (p_info->rx8.num == 0)) - { - result = TXZ_ERROR; - return (result); - } - count = p_info->rx8.num; - - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - while (timeout > 0) - { - /* Wait until Receive Complete Flag is set to receive data */ - if((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) - { - while (count > 0) { - /* Check the remain data exist */ - if((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0){ - p_info->rx8.p_data[index] = (*((__IO uint8_t*)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); - count--; - index++; - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - } - /* Receive Complete Flag is clear */ - p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; - /* FIFO Cear */ - p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - } - else {timeout--;} - } - /* Timeout management */ - p_obj->errcode = TIMEOUTERR; - - /* Check Error Flag set */ - tspi_get_error(p_obj, &err); - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - - result = TXZ_ERROR; - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - p_obj->transmit.tx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - p_obj->transmit.tx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; - p_obj->transmit.info.tx32.num = p_info->tx32.num; - p_obj->transmit.tx_allign = 32; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /* transmit data length set */ - - /*--- TSPIxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Empty FIFO Num */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - /*--- TSPIxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - return (result); -} - - - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - p_obj->receive.rx_allign = 8; - - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; - p_obj->receive.info.rx32.num = p_info->rx32.num; - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_transmit(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - /* Check the transmit's end flag. */ - if (((status & TSPI_TX_DONE_FLAG ) == TSPI_TX_DONE) || - ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) - { - TXZ_WorkState txDone = TXZ_BUSY; - /* Read FIFO fill level. */ - __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Get the empty num in FIFO. */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - if (tlvl == TRANSFER_FIFO_MAX_NUM) - { - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.tx_allign = 8; - if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.tx_allign = 16; - if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.tx_allign = 32; - if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - } - if (txDone == TXZ_DONE) - { - /*=== Transmit Done!! ===*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /* Only the empty number of FIFO is a transmission data set. */ - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - #if 0 - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - #endif - } - } -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_receive(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.rx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - /* Check the receive's end flag. */ - if (((status & TSPI_RX_DONE_FLAG ) == TSPI_RX_DONE) || - ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) - { - /* Read FIFO fill level. */ - __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); - //__IO uint32_t rlvl = 7; - /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ - if (rlvl > RECEIVE_FIFO_MAX_NUM) - { - rlvl = RECEIVE_FIFO_MAX_NUM; - } - /*------------------------------*/ - /* Data Read */ - /*------------------------------*/ - /* Read FIFO data. */ - if (rlvl != 0) - { - uint32_t i; - for (i=0; ireceive.rx_allign) - { - case 8: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); - break; - case 16: - *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - case 32: - *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - default: - /* no process */ - break; - } - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - tspi_receive_t param; - - switch (p_obj->receive.rx_allign) - { - case 8: - param.rx8.p_data = p_obj->receive.info.rx8.p_data; - param.rx8.num = rlvl; - break; - case 16: - param.rx16.p_data = p_obj->receive.info.rx16.p_data; - param.rx16.num = rlvl; - break; - case 32: - param.rx32.p_data = p_obj->receive.info.rx32.p_data; - param.rx32.num = rlvl; - break; - default: - /* no process */ - break; - } - /* Call the receive handler with SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_error_irq_handler(tspi_t *p_obj) -{ - __IO uint32_t error; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current TSPIxERR. */ - error = p_obj->p_instance->ERR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- TSPIxERR ---*/ - /* Check the transmit error. */ - /* TRGERR */ - if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with FAILURE. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); - } - } - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* UNDERERR */ - if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) - { - err = TXZ_ERROR; - } - /* OVRERR */ - if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) - { - err = TXZ_ERROR; - } - /* PERR */ - if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) - { - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - /* Call the receive handler with FAILURE. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); - } - } - } -} - - -/*--------------------------------------------------*/ -/** - * @brief Data Format setting - * @param p_obj :TSPI object. - * @retval - - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_format(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | - * | 30-24 | - | - | - * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | - * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | - * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | - * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | - * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | - * | 15-8 | - | - | - * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | - * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | - * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | - * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | - * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | - * - * @param p_obj :TSPI object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_status is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI state */ - *p_status = p_obj->p_instance->SR; - if(p_status != TSPI_NULL){ return (result);} - else { - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI ERROR */ - *p_error = p_obj->p_instance->ERR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Error information clear. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 3 | TRGERR | Trigger Error. Use @ref TSPI_TRGErr. | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_error_clear(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_transmit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1). */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_receive(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR |TSPI_OVERRUN_ERR | TSPI_PARITY_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - - -/** - * @} - */ /* End of group TSPI_Exported_functions */ - -/** - * @} - */ /* End of group TSPI */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__TSPI_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/txz_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/txz_tspi.h deleted file mode 100644 index d936625c18..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/periph_driver/txz_tspi.h +++ /dev/null @@ -1,1320 +0,0 @@ -/** - ******************************************************************************* - * @file txz_tspi.h - * @brief This file provides all the functions prototypes for TSPI driver. - * @version V1.0.0.7 - * $Date:: 2018-01-22 15:14:05 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __TSPI_H -#define __TSPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup TSPI TSPI - * @brief TSPI Driver. - * @{ - */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_define TSPI Exported Define - * @{ - */ -/** - * @defgroup TSPI_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define TSPI_NULL ((void *)0) -/** - * @} - */ /* End of group TSPI_NullPointer */ - -/** - * @defgroup TSPI_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group TSPI_ParameterResult */ - -/** - * @defgroup TSPI_Result Result - * @brief TSPI Result Macro Definition. - * @{ - */ -#define TSPI_RESULT_SUCCESS (0) /*!< Success */ -#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ -/** - * @} - */ /* End of group TSPI_Result */ - -/** - * @defgroup TSPI_SW_Reset SW Reset - * @brief Software Rest Macro Definition. - * @{ - */ -#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */ -#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */ -/** - * @} - */ /* End of group TSPI_SW_Reset */ - - -/** - * @defgroup TSPI_Enable TSPI Enable/Disable Control - * @brief Enable/Disable TSPIE Macro Definition. - * @{ - */ -#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Enable */ - -/** - * @defgroup TSPI_Triger_Control Triger Control - * @brief Enable/Disable TRGEN Macro Definition. - * @{ - */ -#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Control Transmission Control - * @brief Enable/Disable TRXE Macro Definition. - * @{ - */ -#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ -#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Mode Transmission Mode - * @brief TSPIIMS Mode Macro Definisiton. - * @{ - */ -#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ -#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ -/** - * @} - */ /* End of group TSPI_Transmission_Mode */ - - -/** - * @defgroup TSPI_Operation_Select Operation Select - * @brief Master/Slave MSTR Operation Macro Definisiton. - * @{ - */ -#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /*!< MASTER MODE */ -#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ -/** - * @} - */ /* End of group TSPI_Operation_Select */ - - -/** - * @defgroup TSPI_Transfer_Mode Transfer Mode - * @brief Transfer Mode TMMD Macro Definisiton. - * @{ - */ -#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ -#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ -#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ -#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ -/** - * @} - */ /* End of group TSPI_Transfer_Mode */ - - -/** - * @defgroup TSPI_CSSEL_Select CSSEL Select - * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ -#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ -#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ -#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ -/** - * @} - */ /* End of group TSPI_CSSEL_Select */ - -/** - * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range - * @brief Transfer Frame Range Macro Definisiton. - * @{ - */ -#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /*!< Single Transfer Frame :0 */ -#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ -/** - * @} - */ /* End of group TSPI_Transfer_Frame_Range */ -/** - * @defgroup TSPI_IDLE_Output_value IDLE Output Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ -#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ -#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ -#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_IDLE_Output_value */ - -/** - * @defgroup TSPI_RXDLY_value RXDLY Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_RXDLY_40MHz_OVER ((uint32_t)0x00010000) /*!< fsys > 40MHz */ -#define TSPI_RXDLY_40MHz_OR_LESS ((uint32_t)0x00000000) /*!< fsys <= 40MHz */ -/** - * @} - */ /* End of group TSPI_RXDLY_value*/ - - - /** - * @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value - * @brief In case of Under Run Output Value TXDEMP Macro Definisiton. - * @{ - */ -#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ -#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_Underrun_Output_value */ - - -/** - * @defgroup TSPI_TxFillLevel Tx Fill Level - * @brief Transmit Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ -#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ -#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ -#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ -#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ -#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ -#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ -#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ -/*! - * @} - */ /* End of group TSPI_TxFillLevel */ - - -/** - * @defgroup TSPI_RxFillLevel Rx Fill Level - * @brief Receive Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */ -#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ -#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ -#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ -#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ -#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ -#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ -#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ -#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_RxFillLevel */ - - -/** - * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt - * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterrupt */ - - -/** - * @defgroup TSPI_TxInterrupt Tx Interrpt - * @brief Enable/Disable Transmit Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxInterrupt */ - - -/** - * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt - * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterrupt */ - - -/** - * @defgroup TSPI_RxInterrupt Rx Interrpt - * @brief Enable/Disable Receive Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxInterrupt */ - - -/** - * @defgroup TSPI_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ErrorInterrupt */ - - -/** - * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt - * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ -#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxDMAInterrupt */ - - -/** - * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt - * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ -#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxDMAInterrupt */ - - -/** - * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear - * @brief Tx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Tx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear - * @brief Rx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Rx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock - * @brief Baudrate Input Clock Macro Definisiton. - * @{ - */ -#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ -#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ -#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ -#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ -#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ -#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ -#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ -#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ -#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ -#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Clock */ - - -/** - * @defgroup TSPI_Baudrate_Divider Baudrate Divider - * @brief Baudrate IDivider Macro Definisiton. - * @{ - */ -#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ -#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ -#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ -#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ -#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ -#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ -#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ -#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ -#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ -#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ -#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ -#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ -#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ -#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ -#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ -#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Divider */ - - -/** - * @defgroup TSPI_DataDirection Data Direction - * @brief Data Direction Macro Definisiton. - * @{ - */ -#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ -#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ -/*! - * @} - */ /* End of group TSPI_DataDirection */ - - -/** - * @defgroup TSPI_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ -#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ -#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ -#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ -#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ -#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ -#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ -#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ -#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ -#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ -#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ -#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ -#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ -#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ -#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ -#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ -#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ -#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ -#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ -#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ -#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ -#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ -#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ -#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ -#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ -#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ -/** - * @} - */ /* End of group TSPI_DataLength */ - - -/** - * @defgroup TSPI_Frame_Interval_Time Frame Interval time - * @brief Frame Interval time Macro Definisiton. - * @{ - */ -#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Frame_Interval_Time */ - - -/** - * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity - * @brief TSPIxCS3 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS3_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity - * @brief TSPIxCS2 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS2_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity - * @brief TSPIxCS1 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS1_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity - * @brief TSPIxCS0 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS0_Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity - * @brief Serial Clock Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ -#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ -/** - * @} - */ /* End of group Serial Clock Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity - * @brief Serial Clock IDLE Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ -#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ - - -/** - * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time - * @brief Minimum IDLE Time Macro Definisiton. - * @{ - */ -#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Minimum_IDLE_Time */ - - -/** - * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay - * @brief Serial Clock Delay Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_Delay */ - - -/** - * @defgroup TSPI_Negate_Delay Negate Delay - * @brief Negate Delay Macro Definisiton. - * @{ - */ -#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ -#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ -#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ -#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ -#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ -#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ -#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ -#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ -#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ -#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ -#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ -#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ -#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ -#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ -#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Negate_Delay */ - - -/** - * @defgroup TSPI_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ParityEnable */ - - -/** - * @defgroup TSPI_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ -/** - * @} - */ /* End of group TSPI_ParityBit */ - - -/** - * @defgroup TSPI_Status_Setting_flag Status Setting Flag - * @brief Enable/Disable Status Setting Flag Macro Definisiton. - * @{ - */ -#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ -#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ -/** - * @} - */ /* End of group TSPI_Status_Setting_flag */ - - -/** - * @defgroup TSPI_TxState Transmitting State Flag - * @brief Transmitting State Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ -#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_TxState */ - - -/** - * @defgroup TSPI_TxDone Transmitting Complete Flag - * @brief Transmitting Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ -#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ -#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxDone */ - - -/** - * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag - * @brief Transmitting FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ -#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag - * @brief Transmitting FIFO Empty Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_TxFIFOEmptyFlag */ - -/** - * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level - * @brief Current Transmitting FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ -#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ -#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ -#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ -#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ -#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ -#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ -#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_TxReachFillLevel */ - - -/** - * @defgroup TSPI_RxState Receive State Flag - * @brief Receive State Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ -#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_RxState */ - - -/** - * @defgroup TSPI_RxDone Receive Complete Flag - * @brief Receive Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ -#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ -#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxDone */ - - -/** - * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag - * @brief Rx FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ -#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag - * @brief Receiving FIFO Full Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_RxFIFOFullFlag */ - - -/** - * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level - * @brief Current Receive FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ -#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ -#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ -#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ -#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ -#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ -#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ -#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_RxReachFillLevel */ - - -/** - * @defgroup TSPI_TRGErr Triger Error - * @brief Triger Error Macro Definisiton. - * @{ - */ -#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ -#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_TRGErr */ - -/** - * @defgroup TSPI_UnderrunErr Underrun Error - * @brief Underrun Error Macro Definisiton. - * @{ - */ -#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ -#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_UnderrunErr */ - -/** - * @defgroup TSPI_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ -#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_OverrunErr */ - - -/** - * @defgroup TSPI_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ -#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_ParityErr */ - - /** - * @defgroup TSPI_Data_allign Data allign - * @brief Data allign Macro Definisiton. - * @{ - */ -#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ -#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ -#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ -/** - * @} - */ /* End of group TSPI_Data_allign */ - - /** - * @defgroup TSPI_FifoMax FIFO MAX - * @brief FIFO MAX LEVEL - * @{ - */ -#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ -/** - * @} - */ /* End of group TSPI_FifoMax */ - - /** - * @defgroup TSPI_ErrCode Error Code - * @brief Error Code Macro Definisiton. - * @{ - */ -#define NOERROR ((uint32_t)0x00000000) /*!< no error */ -#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ -#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ -#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ -#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ -#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ -#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ -#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ -#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ -#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ -#define INITERR ((uint32_t)0x00000000) /*!< transmit mode error */ -/** -* @} - */ /* End of group TSPI_ErrCode */ - - /** - * @defgroup TSPI_Buffer_Size Receive Buffer size - * @brief Error Code Macro Definisiton. - * @{ - */ -#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ -/** -* @} - */ /* End of group TSPI_Buffer_Size */ -/** - * @} - */ /* End of group TSPI_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/* No define */ -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @struct tspi_receive8_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive8_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive16_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive16_t; - -/** - * @struct tspi_receive32_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive32_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive_t - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ - tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ - tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ -} tspi_receive_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit8_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit8_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit16_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit16_t; -/*----------------------------------*/ -/** - * @struct tspi_transmit32_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit32_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit_t - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ - tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ - tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ -} tspi_transmit_t; - -/*----------------------------------*/ -/** - * @struct tspi_control1_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t trgen; /*!< TRGEN Transmission Triger Control. - : Use @ref TSPI_Triger_Control */ - uint32_t trxe; /*!< TRXE Transmission Control. - : Use @ref TSPI_Transmission_Control */ - uint32_t tspims; /*!< TSPI/SIO Transmission Mode. - : Use @ref TSPI_Transmission_Mode */ - uint32_t mstr; /*!< Master/Slave Operation Select. - : Use @ref TSPI_Operation_Select */ - uint32_t tmmd; /*!< Transfer Mode Select. - : Use @ref TSPI_Transfer_Mode */ - uint32_t cssel; /*!< CSSEL Select. - : Use @ref TSPI_CSSEL_Select */ - uint32_t fc; /*!< Transfer Frame Value. - : Range ( TSPI_TRANS_RANGE_SINGLE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ -} tspi_control1_t; - -/*----------------------------------*/ -/** - * @struct tspi_control2_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tidle; /*!< IDLE Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t txdemp; /*!< Under Run Occur Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t rxdly; /*!< Fsys Select. - : Use @ref TSPI_RXDLY_value */ - uint32_t til; /*!< Transmit Fill Level. - : Use @ref TSPI_TxFillLevel */ - uint32_t ril; /*!< Receive Fill Level. - : Use @ref TSPI_RxFillLevel */ - uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. - : Use @ref TSPI_TxFIFOInterrupt */ - uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. - : Use @ref TSPI_TxInterrupt */ - uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. - : Use @ref TSPI_RxFIFOInterrupt */ - uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. - : Use @ref TSPI_RxInterrupt */ - uint32_t interr; /*!< Enable/Disable Error Interrupt. - : Use @ref TSPI_ErrorInterrupt */ - uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. - : Use @ref TSPI_TxDMAInterrupt */ - uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. - : Use @ref TSPI_RxDMAInterrupt */ -} tspi_control2_t; - -/*----------------------------------*/ -/** - * @struct tspi_control3_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tfempclr; /*!< Transmit Buffer Clear. - : Use @ref TSPI_Tx_Buffer_Clear */ - uint32_t rffllclr; /*!< Receive Buffer Clear. - : Use @ref TSPI_Rx_Buffer_Clear */ -} tspi_control3_t; - -/*----------------------------------*/ -/** - * @struct tspi_baudrate_t - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t brck; /*!< Baudrate Input Clock. - : Use @ref TSPI_Baudrate_Clock */ - uint32_t brs; /*!< Baudrate Divider. - : Use @ref TSPI_Baudrate_Divider */ -} tspi_baudrate_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr0_t - * @brief Format control0. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t dir; /*!< Data Direction. - : Use @ref TSPI_DataDirection */ - uint32_t fl; /*!< Data Length. - : Use @ref TSPI_DataLength */ - uint32_t fint; /*!< Frame Interval time. - : Use @ref TSPI_Frame_Interval_Time */ - uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS3_Polarity */ - uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS2_Polarity */ - uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS1_Polarity */ - uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS0_Polarity */ - uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. - : Use @ref TSPI_Serial_Clock_Polarity */ - uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. - : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ - uint32_t csint; /*!< Minimum IDLE Time. - : Use @ref TSPI_Minimum_IDLE_Time */ - uint32_t cssckdl; /*!< Serial Clock Delay. - : Use @ref TSPI_Serial_Clock_Delay */ - uint32_t sckcsdl; /*!< Negate Delay. - : Use @ref TSPI_Negate_Delay */ -} tspi_fmtr0_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr1_t - * @brief Format control1. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t reserved; /*!< SIO Slave MOde. - : */ - uint32_t vpe; /*!< Enable/Disable Parity Function. - : Use @ref TSPI_ParityEnable */ - uint32_t vpm; /*!< Odd/Even Parity Bit. - : Use @ref TSPI_ParityBit */ -} tspi_fmtr1_t; - -/*----------------------------------*/ -/** - * @struct tspi_status_t - * @brief Status register. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. - : Use @ref TSPI_Status_Setting_flag */ - uint32_t txrun; /*!< Stop/Active Tx Active Flag. - : Use @ref TSPI_TxState */ - uint32_t txend; /*!< Tx Data Send Complete Flag. - : Use @ref TSPI_TxDone */ - uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag. - : Use @ref TSPI_TxFIFOInterruptFlag */ - uint32_t tfemp; /*!< Tx FIFO Empty Flag. - : Use @ref TSPI_TxFIFOEmptyFlag */ - uint32_t tlvll; /*!< Tx Reach Fill Level - : Use @ref TSPI_TxReachFillLevel */ - uint32_t rxrun; /*!< Stop/Active Rx Active Flag. - : Use @ref TSPI_RxState */ - uint32_t rxend; /*!< Rx Data Receive Complete Flag. - : Use @ref TSPI_RxDone */ - uint32_t intrxff; /*!< Rx FIFO Interrpt Flag - : Use @ref TSPI_RxFIFOInterruptFlag */ - uint32_t rffll; /*!< Rx FIFO Full Flag - : Use @ref TSPI_RxFIFOFullFlag */ - uint32_t rlvl; /*!< Rx Reach Fill Level - : Use @ref TSPI_RxReachFillLevel */ -} tspi_status_t; - -/*----------------------------------*/ -/** - * @struct tspi_error_t - * @brief Error flag. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t udrerr; /*!< Underrun Error. - : Use @ref TSPI_UnderrunErr */ - uint32_t ovrerr; /*!< Overrun Error. - : Use @ref TSPI_OverrunErr */ - uint32_t perr; /*!< Parity Error. - : Use @ref TSPI_ParityErr */ -} tspi_error_t; - - -/*----------------------------------*/ -/** - * @struct tspi_initial_setting_t - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - tspi_control1_t cnt1; /*!< Control1 setting. - : Use @ref tspi_control1_t */ - tspi_control2_t cnt2; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_control3_t cnt3; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_baudrate_t brd; /*!< Baudrate setting. - : Use @ref tspi_baudrate_t */ - tspi_fmtr0_t fmr0; /*!< Format control0 setting. - : Use @ref tspi_fmtr0_t */ - tspi_fmtr1_t fmr1; /*!< Format control1 setting. - : Use @ref tspi_fmtr1_t */ -} tspi_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief TSPI handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct tspi_handle -{ - TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ - tspi_initial_setting_t init; /*!< Initial setting. */ - uint32_t errcode; /*!< ErrorCode */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - tspi_transmit_t info; /*!< Transmit Data Information. */ - uint8_t tx_allign; /*!< Transmit Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - tspi_receive_t info; /*!< Receive Data Information. */ - uint8_t rx_allign; /*!< Receive Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} tspi_t; -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_functions TSPI Exported Functions - * @{ - */ -TXZ_Result tspi_init(tspi_t *p_obj); -TXZ_Result tspi_deinit(tspi_t *p_obj); -TXZ_Result tspi_format(tspi_t *p_obj); -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); -void tspi_irq_handler_transmit(tspi_t *p_obj); -void tspi_irq_handler_receive(tspi_t *p_obj); -void tspi_error_irq_handler(tspi_t *p_obj); -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); -TXZ_Result tspi_error_clear(tspi_t *p_obj); -TXZ_Result tspi_discard_transmit(tspi_t *p_obj); -TXZ_Result tspi_discard_receive(tspi_t *p_obj); -/** - * @} - */ /* End of group TSPI_Exported_functions */ -/** - * @} - */ /* End of group TSPI */ -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TSPI_H */ - - diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/pinmap.c deleted file mode 100644 index 8b2d6a74be..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/pinmap.c +++ /dev/null @@ -1,218 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "gpio_include.h" - -void pin_function(PinName pin, int function) -{ - int port = 0; - uint8_t bit = 0; - uint8_t func = 0; - uint8_t dir = 0; - uint32_t port_base = 0; - uint32_t mode_base = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Calculate pin function and pin direction - func = PIN_FUNC(function); - dir = PIN_DIR(function); - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(port); - // Initialization PxFR OFF - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - BITBAND_PORT_CLR(mode_base, bit); - - // Initialize Input - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - - switch (func) { - case 0: - break; - case 1: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - break; - case 2: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - break; - case 3: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - break; - case 4: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - break; - case 5: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - break; - case 6: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - break; - case 7: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - break; - default: - break; - } - - if (func != 0) { - BITBAND_PORT_SET(mode_base, bit); - } - if (dir == PIN_OUTPUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } else if (dir == PIN_INOUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - int port = 0; - uint8_t bit = 0; - uint8_t val = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Check if function is in range - if (mode > OpenDrain) { - return; - } - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - val = (1 << bit); - - switch (port) { - case PortA: - if (mode == OpenDrain) TSB_PA->OD |= val; - else if (mode == PullUp) TSB_PA->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PA->PDN |= val; - break; - case PortB: - if (mode == OpenDrain) TSB_PB->OD |= val; - else if (mode == PullUp) TSB_PB->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PB->PDN |= val; - break; - case PortC: - if (mode == OpenDrain) TSB_PC->OD |= val; - else if (mode == PullUp) TSB_PC->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PC->PDN |= val; - break; - case PortD: - if (mode == OpenDrain) TSB_PD->OD |= val; - else if (mode == PullUp) TSB_PD->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PD->PDN |= val; - break; - case PortE: - if (mode == OpenDrain) TSB_PE->OD |= val; - else if (mode == PullUp) TSB_PE->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PE->PDN |= val; - break; - case PortF: - if (mode == OpenDrain) TSB_PF->OD |= val; - else if (mode == PullUp) TSB_PF->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PF->PDN |= val; - break; - case PortG: - if (mode == OpenDrain) TSB_PG->OD |= val; - else if (mode == PullUp) TSB_PG->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PG->PDN |= val; - break; - case PortH: - if (mode == PullDown) TSB_PH->PDN |= val; - break; - case PortJ: - if (mode == OpenDrain) TSB_PJ->OD |= val; - else if (mode == PullUp) TSB_PJ->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PJ->PDN |= val; - break; - case PortK: - if (mode == OpenDrain) TSB_PK->OD |= val; - else if (mode == PullUp) TSB_PK->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PK->PDN |= val; - break; - case PortL: - if (mode == OpenDrain) TSB_PL->OD |= val; - else if (mode == PullUp) TSB_PL->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PL->PDN |= val; - break; - case PortM: - if (mode == OpenDrain) TSB_PM->OD |= val; - else if (mode == PullUp) TSB_PM->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PM->PDN |= val; - break; - case PortN: - if (mode == OpenDrain) TSB_PN->OD |= val; - else if (mode == PullUp) TSB_PN->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PN->PDN |= val; - break; - case PortP: - if (mode == OpenDrain) TSB_PP->OD |= val; - else if (mode == PullUp) TSB_PP->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PP->PDN |= val; - break; - case PortR: - if (mode == OpenDrain) TSB_PR->OD |= val; - else if (mode == PullUp) TSB_PR->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PR->PDN |= val; - break; - case PortT: - if (mode == OpenDrain) TSB_PT->OD |= val; - else if (mode == PullUp) TSB_PT->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PT->PDN |= val; - break; - case PortU: - if (mode == OpenDrain) TSB_PU->OD |= val; - else if (mode == PullUp) TSB_PU->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PU->PDN |= val; - break; - case PortV: - if (mode == OpenDrain) TSB_PV->OD |= val; - else if (mode == PullUp) TSB_PV->PUP |= val; - else if (mode == PullDown || mode == PullDefault) TSB_PV->PDN |= val; - break; - default: - break; - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/port_api.c deleted file mode 100644 index b8c7135673..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/port_api.c +++ /dev/null @@ -1,159 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(port <= PortV); - - // Store port and port mask for future use - obj->port = port; - obj->mask = mask; - - // Enabling Port Clock Supply - TSB_CG->FSYSENA |= (1 << (obj->port)); - - // Set port function and port direction - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_function(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - - // Set mode for masked pins - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint8_t bit = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - - // Set direction for masked pins - switch (dir) { - case PIN_INPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INPUT); - } - } - break; - case PIN_OUTPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_OUTPUT); - } - } - break; - case PIN_INOUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INOUT); - } - } - break; - default: - break; - } -} - -void port_write(port_t *obj, int value) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - - // Calculate data to write to masked pins - data = (port_data & ~obj->mask) | (value & obj->mask); - - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - if (((data >> bit) & 0x01) == GPIO_PIN_SET) { - BITBAND_PORT_SET(base, bit); - } else { - BITBAND_PORT_CLR(base, bit); - } - } - } -} - -int port_read(port_t *obj) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - - // Calculate data of masked pins - data = port_data & obj->mask; - - return data; -} - -PinName port_pin(PortName port, int pin_n) -{ - PinName pin = NC; - pin = (PinName)((port << 3 ) | pin_n); - return pin; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/pwmout_api.c deleted file mode 100644 index b6abc7acb8..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/pwmout_api.c +++ /dev/null @@ -1,204 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pwmout_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -static const PinMap PinMap_PWM[] = { - {PB0, PWM_0, PIN_DATA(5, 1)}, - {PC0, PWM_1, PIN_DATA(4, 1)}, - {PJ0, PWM_2, PIN_DATA(4, 1)}, - {PK2, PWM_3, PIN_DATA(4, 1)}, - {PN0, PWM_4, PIN_DATA(4, 1)}, - {PL5, PWM_5, PIN_DATA(4, 1)}, - {PG2, PWM_6, PIN_DATA(4, 1)}, - {NC, NC, 0} -}; - -static const uint32_t prescale_tbl[] = { - 2, 8, 32, 128, 256, 512, 1024 -}; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - uint16_t counter = 0; - - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel - MBED_ASSERT(pwm != (PWMName)NC); - - switch (pwm) { - case PWM_0: - obj->channel = TSB_T32A1; - TSB_CG_FSYSENA_IPENA25 = ENABLE; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - break; - case PWM_1: - obj->channel = TSB_T32A2; - TSB_CG_FSYSENA_IPENA26 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - break; - case PWM_2: - obj->channel = TSB_T32A3; - TSB_CG_FSYSENA_IPENA27 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - break; - case PWM_3: - obj->channel = TSB_T32A4; - TSB_CG_FSYSENA_IPENA28 = ENABLE; - TSB_CG_FSYSENA_IPENA09 = ENABLE; - break; - case PWM_4: - obj->channel = TSB_T32A5; - TSB_CG_FSYSENA_IPENA29 = ENABLE; - TSB_CG_FSYSENA_IPENA12 = ENABLE; - break; - case PWM_5: - obj->channel = TSB_T32A6; - TSB_CG_FSYSENA_IPENA30 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; - break; - case PWM_6: - obj->channel = TSB_T32A7; - TSB_CG_FSYSENA_IPENA31 = ENABLE; - TSB_CG_FSYSENA_IPENA06 = ENABLE; - break; - default: - obj->channel = NULL; - break; - } - - pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM - obj->pin = pin; - obj->period = DEFAULT_PERIOD; - obj->divisor = DEFAULT_CLOCK_DIVISION; - obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP); - obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE); - obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - - counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor); - obj->channel->RGC0 = counter; - obj->channel->RGC1 = counter; - obj->trailing_timing = counter; - obj->leading_timing = counter; -} - -void pwmout_free(pwmout_t* obj) -{ - // Stops and clear count operation - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - pwmout_write(obj, 0); - obj->pin = NC; - obj->channel = NULL; - obj->trailing_timing = 0; - obj->leading_timing = 0; - obj->divisor = 0; -} - -void pwmout_write(pwmout_t* obj, float value) -{ - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again - obj->leading_timing = (obj->trailing_timing - - (obj->trailing_timing * value)); // leading_timing value - obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -float pwmout_read(pwmout_t* obj) -{ - float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - return duty_cycle; -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - float seconds = 0; - int cycles = 0; - uint32_t clkdiv = 0; - int i = 0; - float duty_cycle = 0; - - seconds = (float)(us / 1000000.0f); - - // Select highest timer resolution - for (i = 0; i < 7; ++i) { - cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds); - if (cycles <= MAX_COUNTER_16B) { - clkdiv = i + 1; // range 1:7 - clkdiv <<= 28; - break; - } else { - cycles = MAX_COUNTER_16B; - clkdiv = 7; - clkdiv <<= 28; - } - } - - // Stop timer for setting clock again - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - // Restore the duty-cycle - duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - - obj->trailing_timing = cycles; - obj->leading_timing = (cycles - (cycles * duty_cycle)); - // Change the source clock division and period - obj->channel->MOD = T32A_MODE_32; - obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - obj->channel->RGC0 = obj->leading_timing; - obj->channel->RGC1 = obj->trailing_timing; - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float seconds = 0; - float value = 0; - - seconds = (float)(us / 1000000.0f); - value = (((seconds / obj->period) * 100.0f) / 100.0f); - - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/reset_reason_api.c deleted file mode 100644 index af5a06f633..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/reset_reason_api.c +++ /dev/null @@ -1,132 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "reset_reason_api.h" - -#ifdef DEVICE_RESET_REASON - -#include "TMPM3HQ.h" -#include - -static uint8_t set_bit_count(uint32_t reg); -static uint8_t bit_pos(uint32_t reg); -static bool bit_status(uint32_t reg, uint8_t bit_no); - -static reset_reason_t reset_reason1[6] = { - RESET_REASON_POWER_ON, - RESET_REASON_UNKNOWN, - RESET_REASON_UNKNOWN, - RESET_REASON_PIN_RESET, - RESET_REASON_WAKE_LOW_POWER, - RESET_REASON_BROWN_OUT -}; - -static reset_reason_t reset_reason2[4] = { - RESET_REASON_SOFTWARE, - RESET_REASON_LOCKUP, - RESET_REASON_WATCHDOG, - RESET_REASON_PLATFORM -}; - -void hal_reset_reason_clear(void) -{ - TSB_RLM->RSTFLG0 = 0; - TSB_RLM->RSTFLG1 = 0; -} - -uint32_t hal_reset_reason_get_raw(void) -{ - uint32_t ret = (((TSB_RLM->RSTFLG1 & 0xFF) << 8) | (TSB_RLM->RSTFLG0 & 0xFF)); - return ret; -} - -reset_reason_t hal_reset_reason_get(void) -{ - char multi_flag = 0; - reset_reason_t ret; - - uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_RLM->RSTFLG0); - uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_RLM->RSTFLG1); - - if (NoOfSetBitCountReg1 != 0x00) { - if (NoOfSetBitCountReg1 > 0x01) { - if (bit_status(TSB_RLM->RSTFLG0, 3)) { - ret = RESET_REASON_POWER_ON; - } else { - ret = RESET_REASON_MULTIPLE; - } - } else { - ret = reset_reason1[bit_pos(TSB_RLM->RSTFLG0)]; - } - } else if (NoOfSetBitCountReg2 != 0x00) { - if (NoOfSetBitCountReg2 > 0x01) { - ret = RESET_REASON_MULTIPLE; - } else { - ret = reset_reason2[bit_pos(TSB_RLM->RSTFLG1)]; - } - } else { - ret = RESET_REASON_UNKNOWN; - } - - return ret; -} - -void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) -{ - cap->reasons = 1 << RESET_REASON_UNKNOWN; - cap->reasons |= 1 << RESET_REASON_POWER_ON; - cap->reasons |= 1 << RESET_REASON_MULTIPLE; -} - -static bool bit_status(uint32_t reg, uint8_t bit_no) -{ - bool status = false; - - if (reg & (1 << bit_no)) { - status = true; - } - - return status; -} - -static uint8_t set_bit_count(uint32_t reg) -{ - uint8_t count = 0; - int8_t index = 0; - - for (index = 0; index < (sizeof(uint32_t) * 8); index++) { - if (reg & (1 << index)) { - count++; - if (count > 0x01) { - break; - } - } - } - - return count; -} - -static uint8_t bit_pos(uint32_t reg) -{ - uint8_t bit_no = 0; - - for (bit_no = 0; bit_no < (sizeof(uint32_t) * 8); bit_no++) { - if (reg & (1 << bit_no)) { - return bit_no; - } - } -} - -#endif // DEVICE_RESET_REASON diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/rtc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/rtc_api.c deleted file mode 100644 index 349db976eb..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/rtc_api.c +++ /dev/null @@ -1,228 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "rtc_api.h" -#include "mbed_mktime.h" - -#define RTC_24_HOUR_MODE ((uint8_t)0x01) -#define PAGER_PAGE_ONE ((uint8_t)0x01) -#define PAGER_PAGE_ZERO ((uint8_t)0xEE) -#define RTC_CLK_ENABLE ((uint8_t)0x08) -#define RTC_CLK_DISABLE ((uint8_t)0xE7) -#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) -#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) -#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) -#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) -#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) -#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) -#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) -#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) -#define ELOSC_CFG_CLOCK ((uint64_t)(32768)) -#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro -#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro - -static int rtc_inited = 0; -static int diff_year = 100; //our RTC register only support 2000~2099 -static void external_losc_enable(void); - -void rtc_init(void) -{ - if (!rtc_inited) { - TSB_CG_FSYSENA_IPENA23 = 1; // Enable Sys Clock for RTC - external_losc_enable(); // Enable low-speed oscillator - - TSB_RTC->PAGER = 0x00; // Disable clock and alarm - - while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { - // Reset RTC sec counter - } - - TSB_RTC->RESTR = 0xE7; - - while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { - // Reset RTC sec counter - } - - TSB_RTC->PAGER |= PAGER_PAGE_ONE; - TSB_RTC->YEARR = 0x03; // Set leap year state - TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode - TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode - TSB_RTC->YEARR = 0x01; // Set year value - TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value - TSB_RTC->DATER = (uint8_t)0x01; // Set date value - TSB_RTC->DAYR = (uint8_t)0x0; // Set day value - TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value - TSB_RTC->MINR = (uint8_t)0x02; // Set minute value - TSB_RTC->SECR = (uint8_t)0x22; // Set second value - TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock - rtc_inited = 1; // Enable RTC initialzed status - } -} - -void rtc_free(void) -{ - rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE -} - -int rtc_isenabled(void) -{ - return rtc_inited; // Return status of RTC peripheral driver -} - -time_t rtc_read(void) -{ - if (!rtc_inited) { - // Return invalid time for now! - return 0; - } - - struct tm timeinfo; - uint8_t read_1 = 0U; - uint8_t read_2 = 0U; - - timeinfo.tm_isdst = 0;//no summer time - - TSB_RTC->PAGER &= PAGER_PAGE_ZERO; - - read_1 = TSB_RTC->SECR; // Get sec value - timeinfo.tm_sec = HEX2DEC(read_1); - - do { // Get minute value - read_1 = TSB_RTC->MINR; - read_2 = TSB_RTC->MINR; - } while (read_1 != read_2); - timeinfo.tm_min = HEX2DEC(read_1); - - do { // Get hour value - read_1 = TSB_RTC->HOURR; - read_2 = TSB_RTC->HOURR; - } while (read_1 != read_2); - timeinfo.tm_hour = HEX2DEC(read_1); - - do { // Get Month date value - read_1 = TSB_RTC->DATER; - read_2 = TSB_RTC->DATER; - } while (read_1 != read_2); - timeinfo.tm_mday = HEX2DEC(read_1); - - do { // Get Month value - read_1 = TSB_RTC->MONTHR; - read_2 = TSB_RTC->MONTHR; - } while (read_1 != read_2); - timeinfo.tm_mon = HEX2DEC(read_1)-1; - - do { // Get weekday value - read_1 = TSB_RTC->DAYR; - read_2 = TSB_RTC->DAYR; - } while (read_1 != read_2); - timeinfo.tm_wday = HEX2DEC(read_1); - - do { // Get year value - read_1 = TSB_RTC->YEARR; - read_2 = TSB_RTC->YEARR; - } while (read_1 != read_2); - timeinfo.tm_year = (HEX2DEC(read_1)+ diff_year); - - time_t t; - - if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { - return 0; - } - return t; -} - -void rtc_write(time_t t) -{ - if (!rtc_inited) { - // Initialize the RTC as not yet initialized - rtc_init(); - } - - struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { - return; - } - - diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100); - TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock - - // Check current year is leap year or not - if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) || - (timeinfo.tm_year % 400) == 0) { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year - TSB_RTC->YEARR = 0x00; - } else if ((timeinfo.tm_year % 4) == 1) { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year - TSB_RTC->YEARR = 0x01; - } else if ((timeinfo.tm_year % 4) == 2) { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year - TSB_RTC->YEARR = 0x02; - } else { - TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year - TSB_RTC->YEARR = 0x03; - } - - TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0 - - TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value - // Set month value, tm_mon=0 means Jan while 1 is Jan - TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon+1)); - TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value - TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value - TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value - TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value - TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value - - TSB_RTC->RESTR |= RTCRESTR_RSTTMR_R_RUN; - while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { - // Reset RTC sec counter, otherwise the 1st second will not be accurate - } - - // Setting Wait - // When stop mode is selected, CaseA or CaseB is need. - // CaseA: Wait for RTC 1Hz interrupt. - // CaseB: Check the clock register setting. - { - uint8_t flag = 1; - time_t time_read = {0}; - while(flag) { - time_read = rtc_read(); - if( time_read == t) { // Wait for setting successfully - flag = 0; - } - } - } - TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock -} - -static void external_losc_enable(void) -{ - uint32_t work; - if( (TSB_RLM->LOSCCR & 0x01) == 0 ) { //external losc is not enabled. - uint64_t x = (uint64_t)(ELOSC_CFG_WARM_UP_TIME * ELOSC_CFG_CLOCK); - x = (uint64_t)(x / (uint64_t)(1000000)); - work = (uint32_t)x; - work &= (uint32_t)(0xFFFFFFF0); - work <<= 8; - TSB_CG->WUPLCR = work; - TSB_RLM->LOSCCR = RLMLOSCCR_XTEN_RW_ENABLE; - work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK); - TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE); - while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) { - // No processing - } - } -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/serial_api.c deleted file mode 100644 index 35ab31b7fa..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/serial_api.c +++ /dev/null @@ -1,514 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "serial_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" -#include "objects.h" - -static const PinMap PinMap_UART_TX[] = { - {PA1, SERIAL_0, PIN_DATA(1, 1)}, - {PJ1, SERIAL_1, PIN_DATA(1, 1)}, - {PB2, SERIAL_2, PIN_DATA(1, 1)}, - {PA6, SERIAL_3, PIN_DATA(2, 1)}, - {PV6, SERIAL_4, PIN_DATA(1, 1)}, - {PN2, SERIAL_5, PIN_DATA(2, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA2, SERIAL_0, PIN_DATA(1, 0)}, - {PJ2, SERIAL_1, PIN_DATA(1, 0)}, - {PB3, SERIAL_2, PIN_DATA(1, 0)}, - {PA7, SERIAL_3, PIN_DATA(2, 0)}, - {PV7, SERIAL_4, PIN_DATA(1, 0)}, - {PN3, SERIAL_5, PIN_DATA(2, 0)}, - {NC, NC, 0} -}; - -#if DEVICE_SERIAL_FC -static const PinMap PinMap_UART_CTS[] = { - {PM3, SERIAL_0, PIN_DATA(1, 0)}, - {PJ3, SERIAL_1, PIN_DATA(1, 0)}, - {PB4, SERIAL_2, PIN_DATA(1, 0)}, - {PC5, SERIAL_4, PIN_DATA(1, 0)}, - {PN0, SERIAL_5, PIN_DATA(2, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RTS[] = { - {PM4, SERIAL_0, PIN_DATA(1, 1)}, - {PJ4, SERIAL_1, PIN_DATA(1, 1)}, - {PB5, SERIAL_2, PIN_DATA(1, 1)}, - {PC6, SERIAL_4, PIN_DATA(1, 1)}, - {PN1, SERIAL_5, PIN_DATA(2, 1)}, - {NC, NC, 0} -}; -#endif - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; -static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct); -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate); -static void uart_swreset(TSB_UART_TypeDef *UARTx); - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart_name != NC); - - obj->index = uart_name; - switch (uart_name) { - case SERIAL_0: - obj->UARTx = TSB_UART0; - TSB_CG_FSYSENB_IPENB05 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - TSB_CG_FSYSENA_IPENA11 = ENABLE; - break; - case SERIAL_1: - obj->UARTx = TSB_UART1; - TSB_CG_FSYSENB_IPENB06 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - break; - case SERIAL_2: - obj->UARTx = TSB_UART2; - TSB_CG_FSYSENB_IPENB07 = ENABLE; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - break; - case SERIAL_3: - obj->UARTx = TSB_UART3; - TSB_CG_FSYSENB_IPENB08 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - break; - case SERIAL_4: - obj->UARTx = TSB_UART4; - TSB_CG_FSYSENB_IPENB09 = ENABLE; - TSB_CG_FSYSENA_IPENA17 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - break; - case SERIAL_5: - obj->UARTx = TSB_UART5; - TSB_CG_FSYSENB_IPENB10 = ENABLE; - TSB_CG_FSYSENA_IPENA12 = ENABLE; - break; - default: - error("UART is not available"); - break; - } - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC && rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; - } else { - if (tx != NC) { - obj->uart_config.Mode = UART_ENABLE_TX; - } else { - if (rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX; - } - } - } - - obj->uart_config.BaudRate = 9600; - obj->uart_config.DataBits = 8; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = ParityNone; - obj->uart_config.FlowCtrl = FlowControlNone; - - uart_init(obj->UARTx, &obj->uart_config); - is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - obj->UARTx->TRANS = 0; - obj->UARTx->CR0 = 0; - obj->UARTx->CR1 = 0; - - uart_swreset(obj->UARTx); - - obj->uart_config.BaudRate = 0; - obj->uart_config.DataBits = 0; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = 0; - obj->uart_config.Mode = 0; - obj->uart_config.FlowCtrl = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->uart_config.BaudRate = baudrate; - uart_init(obj->UARTx, &obj->uart_config); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - - obj->uart_config.DataBits = data_bits; - obj->uart_config.StopBits = stop_bits; - obj->uart_config.Parity = parity; - uart_init(obj->UARTx, &obj->uart_config); -} - -void INTUART0TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); -} - -void INTUART0RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); -} - -void INTUART1TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); -} - -void INTUART1RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); -} - -void INTUART2TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); -} - -void INTUART2RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); -} - -void INTUART3TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], TxIrq); -} - -void INTUART3RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], RxIrq); -} - -void INTUART4TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], TxIrq); -} - -void INTUART4RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], RxIrq); -} - -void INTUART5TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], TxIrq); -} - -void INTUART5RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], RxIrq); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch (obj->index) { - case SERIAL_0: - if (irq == RxIrq) { - irq_n = INTUART0RX_IRQn; - } else { - irq_n = INTUART0TX_IRQn; - } - break; - case SERIAL_1: - if (irq == RxIrq) { - irq_n = INTUART1RX_IRQn; - } else { - irq_n = INTUART1TX_IRQn; - } - break; - case SERIAL_2: - if (irq == RxIrq) { - irq_n = INTUART2RX_IRQn; - } else { - irq_n = INTUART2TX_IRQn; - } - break; - case SERIAL_3: - if (irq == RxIrq) { - irq_n = INTUART3RX_IRQn; - } else { - irq_n = INTUART3TX_IRQn; - } - break; - case SERIAL_4: - if (irq == RxIrq) { - irq_n = INTUART4RX_IRQn; - } else { - irq_n = INTUART4TX_IRQn; - } - break; - case SERIAL_5: - if (irq == RxIrq) { - irq_n = INTUART5RX_IRQn; - } else { - irq_n = INTUART5TX_IRQn; - } - break; - default: - break; - } - NVIC_ClearPendingIRQ(irq_n); - if (enable) { - NVIC_EnableIRQ(irq_n); - } else { - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) -{ - int data = 0; - - while (!serial_readable(obj)) { // Wait until Rx buffer is full - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS &= 0x0D; - } - - data = data | (obj->UARTx->DR & 0xFFU); - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS |= UART_ENABLE_TX; - } - - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)) { - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS &= 0x0E; - } - - obj->UARTx->DR = c & 0xFFU; - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS |= UART_ENABLE_RX; - } -} - -int serial_readable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x0000000F) != 0) { - ret = 1; - } - - return ret; -} - -int serial_writable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x8000) == 0) { - ret = 1; - } - - return ret; -} - -void serial_clear(serial_t *obj) -{ - obj->UARTx->FIFOCLR = 0x03; -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - obj->UARTx->TRANS |= 0x08; -} - -void serial_break_clear(serial_t *obj) -{ - obj->UARTx->TRANS &= ~(0x08); -} - -#if DEVICE_SERIAL_FC -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); - UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); - UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts); - MBED_ASSERT((int)uart_name != NC); - - pinmap_pinout(rxflow, PinMap_UART_RTS); - pinmap_pinout(txflow, PinMap_UART_CTS); - pin_mode(txflow, PullUp); - pin_mode(rxflow, PullUp); - - obj->UARTx->CR0 |= (3U << 9); -} -#endif - -static void uart_swreset(TSB_UART_TypeDef *UARTx) -{ - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } - - UARTx->SWRST = UARTxSWRST_SWRST_10; - UARTx->SWRST = UARTxSWRST_SWRST_01; - - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } -} - -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate) -{ - uint32_t clock = 0; - uint32_t k = 0; - uint64_t tx = 0; - uint64_t work = 1; - uint64_t p_range64 = 0; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 1; - - SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency - clock = SystemCoreClock; - - tx = (uint64_t)((uint64_t)clock << 6); - tx /= work; - tx64 = (uint64_t)((uint64_t)clock << 8); - tx64 /= work64; - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - - boud64 = (64U * boudrate); - p_range64 = ((boud64 / 100) * 3); - - for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) { - work = tx + k; - if (work >= (uint64_t)((uint64_t)1 << 6)) { - work -= (uint64_t)((uint64_t)1 << 6); - work >>= 6; - if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { - work64 = work <<6; - work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); - work64 = (tx64 / work64); - if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) { - brddiviser->brn = work; - brddiviser->brk = k; - break; - } - } - } - } -} - -static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct) -{ - uart_boudrate_t UTx_brd = {0}; - uint32_t brk = 0; - uint32_t tmp = 0; - uint32_t parity_check = 0; - uint32_t data_length = 0; - - UARTx->CLK = UART_PLESCALER_1; // Register Setting - uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate); - UTx_brd.ken = UART_DIVISION_ENABLE; - brk = (UTx_brd.brk << 16); - UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn); - parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0); - data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2); - tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length); - UARTx->CR0 = tmp; - UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); - UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); - UARTx->TRANS = InitStruct->Mode; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/sleep.c deleted file mode 100644 index 6f8d6975b1..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/sleep.c +++ /dev/null @@ -1,85 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "gpio_include.h" - -static void warming_up_time(void); - -void hal_sleep(void) -{ - // Set low power consumption mode IDLE - TSB_CG->STBYCR = CG_STBY_MODE_IDLE; - __DSB(); // Enter idle mode - __WFI(); -} - -void hal_deepsleep(void) -{ - uint32_t tmp = 0; - - TSB_CG_FSYSENB_IPENB31 = ENABLE; - while ((TSB_FC->SR0 & 0x01) != 0x01) { - // Flash wait - } - - while (TSB_CG_WUPHCR_WUEF) { - // Wait for end of Warming-up for IHOSC1 - } - - TSB_CG_WUPHCR_WUCLK = DISABLE; - warming_up_time(); - TSB_CG->STBYCR = CG_STBY_MODE_STOP1; - TSB_CG_PLL0SEL_PLL0SEL = DISABLE; - - while (TSB_CG_PLL0SEL_PLL0ST) { - // Wait for PLL status of fsys until off state(fosc=0) - } - - TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys - TSB_CG_OSCCR_IHOSC1EN = ENABLE; - TSB_CG_OSCCR_OSCSEL = DISABLE; - - while (TSB_CG_OSCCR_OSCF) { - // Wait for fosc status until IHOSC1 = 0 - } - - tmp = TSB_CG->OSCCR; - tmp &= EXTERNEL_OSC_MASK; - TSB_CG->OSCCR = tmp; - TSB_CG_OSCCR_IHOSC2EN = DISABLE; - - while (TSB_CG_OSCCR_IHOSC2F) { - // Wait for status of OFD until off "0" - } - - __DSB(); - __WFI(); -} - -static void warming_up_time(void) -{ - uint32_t work = 0; - uint64_t x = 0; - - x = (uint64_t)(IHOSC_CFG_WARM_UP_TIME * IHOSC_CFG_CLOCK); - x = (uint64_t)(x / (uint64_t)(1000000)); - - work = (uint32_t)x; - work &= (uint32_t)(0xFFFFFFF0); - work <<= 16; - work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK); - TSB_CG->WUPHCR = work; -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/spi_api.c deleted file mode 100644 index 4831c3f58a..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/spi_api.c +++ /dev/null @@ -1,606 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "spi_api.h" -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" -#include "txz_tspi.h" -#define TIMEOUT 1000 -#define INITIAL_SPI_FREQ 1000000 - -#if DEVICE_I2C_ASYNCH -#define SPI_S(obj) (struct spi_s *) (&((obj)->spi)) -#else -#define SPI_S(obj) (struct spi_s *) (obj) -#endif - -#if DEVICE_SPI_ASYNCH -static void spi_irq_handler(spi_t *obj); -static void disable_irq(uint32_t irqn); -static void clear_irq(uint32_t irqn); - -enum { - SPI_TRANSFER_STATE_IDLE = 0U, - SPI_TRANSFER_STATE_BUSY -} SPI_TransferState; - -typedef struct { - IRQn_Type Tx; - IRQn_Type Rx; - IRQn_Type Error; -} spi_irq_t; - -static const spi_irq_t SPI_CH0_IRQN_TBL[1] = { - { INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn } -}; - -static const spi_irq_t SPI_CH1_IRQN_TBL[1] = { - { INTT1RX_IRQn, INTT1TX_IRQn, INTT1ERR_IRQn } -}; - -static const spi_irq_t SPI_CH2_IRQN_TBL[1] = { - { INTT2RX_IRQn, INTT2TX_IRQn, INTT2ERR_IRQn } -}; - -static const spi_irq_t SPI_CH3_IRQN_TBL[1] = { - { INTT3RX_IRQn, INTT3TX_IRQn, INTT3ERR_IRQn } -}; - -static const spi_irq_t SPI_CH4_IRQN_TBL[1] = { - { INTT4RX_IRQn, INTT4TX_IRQn, INTT4ERR_IRQn } -}; -#endif - -static const PinMap PinMap_SPI_SCLK[] = { - {PM0, SPI_0, PIN_DATA(3, 1)}, - {PB2, SPI_1, PIN_DATA(3, 1)}, - {PT2, SPI_2, PIN_DATA(1, 1)}, - {PP5, SPI_3, PIN_DATA(1, 1)}, - {PH4, SPI_4, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PM1, SPI_0, PIN_DATA(3, 1)}, - {PB3, SPI_1, PIN_DATA(3, 1)}, - {PT3, SPI_2, PIN_DATA(1, 1)}, - {PP4, SPI_3, PIN_DATA(1, 1)}, - {PH5, SPI_4, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PM2, SPI_0, PIN_DATA(3, 0)}, - {PB4, SPI_1, PIN_DATA(3, 0)}, - {PT4, SPI_2, PIN_DATA(1, 0)}, - {PP3, SPI_3, PIN_DATA(1, 0)}, - {PH6, SPI_4, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PM3, SPI_0, PIN_DATA(3, 1)}, - {PB5, SPI_1, PIN_DATA(3, 1)}, - {PT1, SPI_2, PIN_DATA(2, 1)}, - {PP6, SPI_3, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPISLAVE_SCLK[] = { - {PM0, SPI_0, PIN_DATA(3, 0)}, - {PB2, SPI_1, PIN_DATA(3, 0)}, - {PT2, SPI_2, PIN_DATA(1, 0)}, - {PP5, SPI_3, PIN_DATA(1, 0)}, - {PH4, SPI_4, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -void spi_init(spi_t *t_obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - struct spi_s *obj = SPI_S(t_obj); - // Check pin parameters - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk); - obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->module!= NC); - - // Identify SPI module to use - switch ((int)obj->module) { - case SPI_0: - obj->p_obj.p_instance = TSB_TSPI0; - TSB_CG_FSYSENA_IPENA11 = ENABLE; - TSB_CG_FSYSENB_IPENB00 = ENABLE; -#if DEVICE_SPI_ASYNCH - obj->irqn = (uint32_t)&SPI_CH0_IRQN_TBL; -#endif - break; - case SPI_1: - obj->p_obj.p_instance = TSB_TSPI1; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - TSB_CG_FSYSENB_IPENB01 = ENABLE; -#if DEVICE_SPI_ASYNCH - obj->irqn = (uint32_t)&SPI_CH1_IRQN_TBL; -#endif - break; - case SPI_2: - obj->p_obj.p_instance = TSB_TSPI2; - TSB_CG_FSYSENA_IPENA15 = ENABLE; - TSB_CG_FSYSENB_IPENB02 = ENABLE; -#if DEVICE_SPI_ASYNCH - obj->irqn = (uint32_t)&SPI_CH2_IRQN_TBL; -#endif - break; - case SPI_3: - obj->p_obj.p_instance = TSB_TSPI3; - TSB_CG_FSYSENA_IPENA13 = ENABLE; - TSB_CG_FSYSENB_IPENB03 = ENABLE; -#if DEVICE_SPI_ASYNCH - obj->irqn = (uint32_t)&SPI_CH3_IRQN_TBL; -#endif - break; - case SPI_4: - obj->p_obj.p_instance = TSB_TSPI4; - TSB_CG_FSYSENA_IPENA07 = ENABLE; - TSB_CG_FSYSENB_IPENB04 = ENABLE; -#if DEVICE_SPI_ASYNCH - obj->irqn = (uint32_t)&SPI_CH4_IRQN_TBL; -#endif - break; - default: - error("Cannot found SPI module corresponding with input pins."); - break; - } - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - obj->Slave_SCK = sclk; - - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - - //Control 1 configurations - obj->p_obj.init.id = (uint32_t)obj->module; - obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled - obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication - obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode - obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // master mode operation - obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) - obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid - obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // transfer single frame at a time continuously - - //Control 2 configurations - obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; - obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low - obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_40MHz_OVER; - obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level - obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level - obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; - obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; - obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; - obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; - obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; - - //Control 3 configurations - obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear - obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear - - //baudrate settings - spi_frequency(t_obj, (int)INITIAL_SPI_FREQ); - - //Format Control 0 settings - obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first - obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; - obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; - - //Special control on polarity of signal and generation timing - obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; - obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; - obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; - obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; - - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; - obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; - obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; - - //Format Control 1 settings tspi_fmtr1_t - obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; - obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; - - obj->bits = (uint8_t)TSPI_DATA_LENGTH_8; - //initialize SPI - tspi_init(&obj->p_obj); -} - -void spi_free(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - tspi_deinit(&obj->p_obj); - obj->module = (SPIName)NC; -} - -void spi_format(spi_t *t_obj, int bits, int mode, int slave) -{ - struct spi_s *obj = SPI_S(t_obj); - MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode - MBED_ASSERT((bits >= 8) && (bits <= 32)); - - obj->bits = bits; - obj->p_obj.init.fmr0.fl = (bits << 24); - - if ((mode >> 1) & 0x1) { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; - } else { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - } - - if (mode & 0x1) { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; - } else { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - } - - if(slave) { - pinmap_pinout(obj->Slave_SCK, PinMap_SPISLAVE_SCLK); - obj->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation - } - tspi_init(&obj->p_obj); -} - -void spi_frequency(spi_t *t_obj, int hz) -{ - struct spi_s *obj = SPI_S(t_obj); - uint8_t brs = 0; - uint8_t brck = 0; - uint16_t prsck = 1; - uint64_t fscl = 0; - uint64_t tmp_fscl = 0; - uint64_t fx = 0; - uint64_t tmpvar = SystemCoreClock; - - SystemCoreClockUpdate(); - - tmpvar = tmpvar / 2; - - for (prsck = 1; prsck <= 512; prsck *= 2) { - fx = ((uint64_t)tmpvar / prsck); - for (brs = 1; brs <= 16; brs++) { - fscl = fx /brs; - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - obj->p_obj.init.brd.brck = (brck << 4); - if (brs == 16) { - obj->p_obj.init.brd.brs = 0; - } else { - obj->p_obj.init.brd.brs = brs; - } - } - } - brck ++; - } - tspi_init(&obj->p_obj); -} - -int spi_master_write(spi_t *t_obj, int value) -{ - struct spi_s *obj = SPI_S(t_obj); - uint8_t ret_value = 0; - - tspi_transmit_t send_obj; - tspi_receive_t rec_obj; - - // Transmit data - send_obj.tx8.p_data = (uint8_t *)&value; - send_obj.tx8.num = 1; - tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT); - - // Read received data - rec_obj.rx8.p_data = &ret_value; - rec_obj.rx8.num = 1; - tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT); - - return ret_value; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - int ret = 1; - uint32_t status = 0; - - tspi_get_status(&obj->p_obj, &status); - - if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { - ret = 0; - } - - return ret; -} - -int spi_slave_receive(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - int ret = 1; - uint32_t status; - - tspi_get_status(&obj->p_obj, &status); - if((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) { - ret = 0; - } - return ret; -} - -int spi_slave_read(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - uint8_t ret_value = 0; - - ret_value = obj->p_obj.p_instance->DR & 0xFF; - - // Receive Complete Flag is clear. - obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; - obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - - return ret_value; -} - -void spi_slave_write(spi_t *t_obj, int value) -{ - struct spi_s *obj = SPI_S(t_obj); - - // Enable TSPI Transmission Control. - obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - obj->p_obj.p_instance->DR = value & 0xFF; -} - -uint8_t spi_get_module(spi_t *t_obj) -{ - struct spi_s *obj = SPI_S(t_obj); - return (uint8_t)(obj->module); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -#if DEVICE_SPI_ASYNCH - -void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, - uint32_t handler, uint32_t event, DMAUsage hint) -{ - struct spi_s *spiobj = SPI_S(obj); - spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn; - bool use_tx = (tx != NULL && tx_length > 0); - bool use_rx = (rx != NULL && rx_length > 0); - - // don't do anything, if the buffers aren't valid - if (!use_tx && !use_rx) { - return; - } - - disable_irq(spiobj->irqn); - - spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - - clear_irq(spiobj->irqn); - - obj->tx_buff.buffer = (void *)tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - obj->rx_buff.buffer = (void *)rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - spiobj->event = 0; - spiobj->state = SPI_TRANSFER_STATE_IDLE; - - - NVIC_SetVector(p_irqn->Error, (uint32_t)handler); - NVIC_SetVector(p_irqn->Tx, (uint32_t)handler); - NVIC_SetVector(p_irqn->Rx, (uint32_t)handler); - - // Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt - spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE); - - if (use_tx && use_rx) { - spiobj->max_size = tx_length < rx_length ? rx_length:tx_length; - spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; - } else if(use_tx) { - spiobj->max_size = tx_length; - spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; - } else if(use_rx) { - spiobj->max_size = rx_length; - spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; - spiobj->p_obj.p_instance->DR = 0xFF; - } - - spiobj->state = SPI_TRANSFER_STATE_BUSY; - NVIC_EnableIRQ(p_irqn->Error); - NVIC_EnableIRQ(p_irqn->Tx); - NVIC_EnableIRQ(p_irqn->Rx); -} - -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - spi_irq_handler(obj); - return ((spiobj->event & SPI_EVENT_ALL)| SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ; -} - -uint8_t spi_active(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - uint8_t ret_val = 0; - - if (spiobj->state != SPI_TRANSFER_STATE_IDLE) { - ret_val = 1; - } - - return ret_val; -} - -void spi_abort_asynch(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - - disable_irq(spiobj->irqn); - clear_irq(spiobj->irqn); - tspi_init(&spiobj->p_obj); -} - -static void spi_irq_handler(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - - // Check for revceive complete flag. - if((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) && - (spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) { - // Check receiver FIFO level - uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF; - - while((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) { - ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF; - rlvl--; - } - - if(obj->rx_buff.pos == spiobj->max_size) { - spiobj->state = SPI_TRANSFER_STATE_IDLE; - } - // Clear rx buffer - spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE; - } - - // Check for transmit completion flag - if(spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) { - obj->tx_buff.pos++; - spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; - - if(obj->tx_buff.pos == (spiobj->max_size)) { - spiobj->state = SPI_TRANSFER_STATE_IDLE; - } - - if((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) { - spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF); - } else if (obj->tx_buff.pos < spiobj->max_size) { - spiobj->p_obj.p_instance->DR = 0xFF; - } - } - - // Check for error flag - if(spiobj->p_obj.p_instance->ERR) { - spiobj->event = SPI_EVENT_ERROR; - spiobj->state = SPI_TRANSFER_STATE_IDLE; - disable_irq(spiobj->irqn); - spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - clear_irq(spiobj->irqn); - return; - } - - if(spiobj->state == SPI_TRANSFER_STATE_IDLE) { - spiobj->event = SPI_EVENT_COMPLETE; - disable_irq(spiobj->irqn); - spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - clear_irq(spiobj->irqn); - } -} - -static void disable_irq(uint32_t irqn) -{ - spi_irq_t *p_irqn = (spi_irq_t *)irqn; - NVIC_DisableIRQ(p_irqn->Tx); - NVIC_DisableIRQ(p_irqn->Rx); - NVIC_DisableIRQ(p_irqn->Error); -} - -static void clear_irq(uint32_t irqn) -{ - spi_irq_t *p_irqn = (spi_irq_t *)irqn; - NVIC_ClearPendingIRQ(p_irqn->Tx); - NVIC_ClearPendingIRQ(p_irqn->Rx); - NVIC_ClearPendingIRQ(p_irqn->Error); -} - -#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/us_ticker.c deleted file mode 100644 index 23d75d405b..0000000000 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/us_ticker.c +++ /dev/null @@ -1,98 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "gpio_include.h" - -static bool us_ticker_inited = false; // Is ticker initialized yet? - -const ticker_info_t* us_ticker_get_info(void) -{ - static const ticker_info_t info = { - 1249200, // PLL output freq is ~40 MHz(39.974 MHz). - 32 // 32 bit counter - }; - return &info; -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) { - us_ticker_disable_interrupt(); - return; - } - us_ticker_inited = true; - - TSB_CG_FSYSENA_IPENA24 = TXZ_ENABLE; - TSB_T32A0->MOD = T32A_MODE_32; - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->CRC = T32A_PRSCLx_32; - TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); - NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -uint32_t us_ticker_read(void) -{ - if (!us_ticker_inited) { - us_ticker_init(); - } - - return (TSB_T32A0->TMRC); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - NVIC_DisableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->RGC1 = timestamp; - NVIC_EnableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INTT32A00C_IRQn); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - // Disable interrupts by NVIC - TSB_T32A0->STC = T32A_INT_MASK; - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - NVIC_DisableIRQ(INTT32A00C_IRQn); -} - -void us_ticker_clear_interrupt(void) -{ - TSB_T32A0->STC = T32A_INT_MASK; - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); -} - -void us_ticker_free(void) -{ - TSB_T32A0->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - us_ticker_inited = false; - TSB_T32A0->STC = 0x0F; - // Clear Pending interrupt in NVIC - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - // Disable interrupt in NVIC - NVIC_DisableIRQ(INTT32A00C_IRQn); - // Disable Clock. - TSB_CG_FSYSENA_IPENA24 = 0; -} diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h index b634626bab..2835015067 100644 --- a/targets/TARGET_TOSHIBA/mbed_rtx.h +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -20,18 +20,6 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H -#if defined(TARGET_TMPM066) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20004000UL) -#endif -#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE -#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE -#endif -#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072 - -#endif - #if defined(TARGET_TMPM46B) #ifndef INITIAL_SP @@ -44,14 +32,6 @@ #endif -#if defined(TARGET_TMPM3H6) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20004000UL) -#endif - -#endif - #if defined(TARGET_TMPM4G9) #ifndef INITIAL_SP @@ -60,12 +40,4 @@ #endif -#if defined(TARGET_TMPM3HQ) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20010000UL) -#endif - -#endif - #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index 1925c27058..56b9d72ec5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -11876,48 +11876,6 @@ "network-default-interface-type": "WIFI" } }, - "TMPM066": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0", - "is_disk_virtual": true, - "extra_labels": [ - "TOSHIBA" - ], - "macros": [ - "__TMPM066__", - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "USTICKER", - "ANALOGIN", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "RESET_REASON", - "SERIAL", - "SLEEP", - "I2C", - "I2CSLAVE", - "STDIO_MESSAGES", - "PWMOUT" - ], - "device_name": "TMPM066FWUG", - "detect_code": [ - "7011" - ], - "release_versions": [ - "5" - ] - }, "SAKURAIO_EVB_01": { "inherits": [ "FAMILY_STM32" @@ -12483,49 +12441,6 @@ ], "bootloader_supported": true }, - "TMPM3H6": { - "inherits": [ - "Target" - ], - "core": "Cortex-M3", - "is_disk_virtual": true, - "extra_labels": [ - "TOSHIBA" - ], - "macros": [ - "__TMPM3H6__" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "USTICKER", - "ANALOGIN", - "ANALOGOUT", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "RESET_REASON", - "SERIAL", - "SLEEP", - "SPI", - "I2C", - "I2CSLAVE", - "STDIO_MESSAGES", - "MPU" - ], - "device_name": "TMPM3H6FWFG", - "detect_code": [ - "7012" - ], - "release_versions": [ - "5" - ] - }, "TMPM4G9": { "inherits": [ "Target" @@ -13118,56 +13033,6 @@ "function": "PSOC6Code.complete" } }, - "TMPM3HQ": { - "inherits": [ - "Target" - ], - "core": "Cortex-M3", - "is_disk_virtual": true, - "extra_labels": [ - "TOSHIBA" - ], - "macros": [ - "__TMPM3HQ__" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "USTICKER", - "ANALOGIN", - "ANALOGOUT", - "CRC", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "RESET_REASON", - "RTC", - "SERIAL", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPI_ASYNCH", - "SPISLAVE", - "I2C", - "I2C_ASYNCH", - "I2CSLAVE", - "STDIO_MESSAGES", - "FLASH", - "MPU" - ], - "device_name": "TMPM3HQFDFG", - "detect_code": [ - "7014" - ], - "release_versions": [ - "5" - ] - }, "GD32_Target": { "inherits": [ "Target"