mirror of https://github.com/ARMmbed/mbed-os.git
Martin Kojtal
GitHub
commit
4f314beeee
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@ -297,14 +297,12 @@ const PinMap PinMap_UART_CTS[] = {
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const PinMap PinMap_SPI_MOSI[] = {
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{PA_5, SPI_1, SYS_GPA_MFPL_PA5MFP_SPI1_MOSI},
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{PB_0, SPI_0, SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1},
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{PB_5, SPI_0, SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0},
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{PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MOSI},
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{PC_3, SPI_2, SYS_GPC_MFPL_PC3MFP_SPI2_MOSI},
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{PC_10, SPI_2, SYS_GPC_MFPH_PC10MFP_SPI2_MOSI},
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{PD_13, SPI_2, SYS_GPD_MFPH_PD13MFP_SPI2_MOSI},
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{PE_3, SPI_1, SYS_GPE_MFPL_PE3MFP_SPI1_MOSI},
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{PE_9, SPI_0, SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1},
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{PE_11, SPI_1, SYS_GPE_MFPH_PE11MFP_SPI1_MOSI},
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{PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0},
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@ -313,7 +311,6 @@ const PinMap PinMap_SPI_MOSI[] = {
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const PinMap PinMap_SPI_MISO[] = {
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{PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_MISO},
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{PB_1, SPI_0, SYS_GPB_MFPL_PB1MFP_SPI0_MISO1},
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{PB_3, SPI_0, SYS_GPB_MFPL_PB3MFP_SPI0_MISO0},
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{PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_MISO},
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{PB_6, SPI_0, SYS_GPB_MFPL_PB6MFP_SPI0_MISO0},
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@ -322,7 +319,6 @@ const PinMap PinMap_SPI_MISO[] = {
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{PC_11, SPI_2, SYS_GPC_MFPH_PC11MFP_SPI2_MISO},
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{PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_MISO},
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{PD_14, SPI_2, SYS_GPD_MFPH_PD14MFP_SPI2_MISO},
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{PE_8, SPI_0, SYS_GPE_MFPH_PE8MFP_SPI0_MISO1},
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{PE_10, SPI_1, SYS_GPE_MFPH_PE10MFP_SPI1_MISO},
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{PE_10, SPI_0, SYS_GPE_MFPH_PE10MFP_SPI0_MISO0},
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@ -101,8 +101,8 @@ typedef enum {
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LED_GREEN = LED3,
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LED_BLUE = LED1,
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// Button naming
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SW1 = PA_15,
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SW2 = PA_14,
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SW2 = PA_15,
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SW3 = PA_14,
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} PinName;
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@ -64,9 +64,8 @@ void mbed_sdk_init(void)
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CLK_SetCoreClock(72000000);
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#if DEVICE_ANALOGIN
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// FIXME: Check voltage reference for EADC
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/* Vref connect to AVDD */
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//SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
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/* Vref connect to internal */
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SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_072V;
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#endif
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/* Update System Core Clock */
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@ -23,76 +23,25 @@
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#include "PeripheralPins.h"
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#include "nu_modutil.h"
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struct nu_adc_var {
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uint32_t en_msk;
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};
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static struct nu_adc_var adc0_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc1_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc2_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc3_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc4_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc5_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc6_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc7_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc8_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc9_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc10_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc11_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc12_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc13_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc14_var = {
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.en_msk = 0
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};
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static struct nu_adc_var adc15_var = {
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.en_msk = 0
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};
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static uint32_t eadc_modinit_mask = 0;
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static const struct nu_modinit_s adc_modinit_tab[] = {
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{ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc0_var},
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{ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc1_var},
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{ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc2_var},
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{ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc3_var},
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{ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc4_var},
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{ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc5_var},
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{ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc6_var},
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{ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc7_var},
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{ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc8_var},
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{ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc9_var},
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{ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc10_var},
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{ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc11_var},
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{ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc12_var},
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{ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc13_var},
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{ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc14_var},
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{ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc15_var},
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{ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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{ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
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};
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void analogin_init(analogin_t *obj, PinName pin)
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@ -107,7 +56,7 @@ void analogin_init(analogin_t *obj, PinName pin)
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EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
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// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
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if (! ((struct nu_adc_var *) modinit->var)->en_msk) {
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if (! eadc_modinit_mask) {
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// Reset this module if no channel enabled
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SYS_ResetModule(modinit->rsetidx);
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@ -116,9 +65,6 @@ void analogin_init(analogin_t *obj, PinName pin)
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// Enable clock of paired channels
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CLK_EnableModuleClock(modinit->clkidx);
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// Power on ADC
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//ADC_POWER_ON(ADC);
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// Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
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EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
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EADC_SetInternalSampleTime(eadc_base, 6);
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@ -130,9 +76,9 @@ void analogin_init(analogin_t *obj, PinName pin)
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pinmap_pinout(pin, PinMap_ADC);
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// Configure the sample module Nmod for analog input channel Nch and software trigger source
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EADC_ConfigSampleModule(EADC, chn, EADC_SOFTWARE_TRIGGER, chn);
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EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn);
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((struct nu_adc_var *) modinit->var)->en_msk |= 1 << chn;
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eadc_modinit_mask |= 1 << chn;
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}
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uint16_t analogin_read_u16(analogin_t *obj)
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@ -141,7 +87,7 @@ uint16_t analogin_read_u16(analogin_t *obj)
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uint32_t chn = NU_MODSUBINDEX(obj->adc);
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EADC_START_CONV(eadc_base, 1 << chn);
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while (EADC_GET_PENDING_CONV(eadc_base) & (1 << chn));
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while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != (1 << chn));
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uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
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// Just 12 bits are effective. Convert to 16 bits.
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// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
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@ -52,22 +52,23 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
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#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
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#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
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#define M451_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
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#else
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#define M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
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#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
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#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
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#endif
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#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
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#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
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#else
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#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
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#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
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#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
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#endif
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static PinName gpio_irq_debounce_arr[] = {
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MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
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};
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#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
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#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
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#endif
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#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
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#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
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#else
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#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
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#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
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#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
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#endif
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int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
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@ -89,13 +90,36 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
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GPIO_T *gpio_base = NU_PORT_BASE(port_index);
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//gpio_set(pin);
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#if M451_GPIO_IRQ_DEBOUNCE_ENABLE
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// Configure de-bounce clock source and sampling cycle time
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GPIO_SET_DEBOUNCE_TIME(M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
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GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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{
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#if MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
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// Suppress compiler warning
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(void) gpio_irq_debounce_arr;
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// Configure de-bounce clock source and sampling cycle time
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GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
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GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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#else
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GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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// Enable de-bounce if the pin is in the de-bounce enable list
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// De-bounce defaults to disabled.
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GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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PinName *debounce_pos = gpio_irq_debounce_arr;
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PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
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for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
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uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
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uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
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if (pin_index == pin_index_debunce &&
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port_index == port_index_debounce) {
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// Configure de-bounce clock source and sampling cycle time
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GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
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GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
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break;
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}
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}
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#endif
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}
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struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
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@ -48,6 +48,7 @@ static void i2c0_vec(void);
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static void i2c1_vec(void);
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static void i2c_irq(i2c_t *obj);
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static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
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static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked);
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static struct nu_i2c_var i2c0_var = {
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.obj = NULL,
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@ -68,8 +69,6 @@ static const struct nu_modinit_s i2c_modinit_tab[] = {
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};
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static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
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static int i2c_do_write(i2c_t *obj, char data, int naklastdata);
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static int i2c_do_read(i2c_t *obj, char *data, int naklastdata);
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static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
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#define NU_I2C_TIMEOUT_STAT_INT 500000
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#define NU_I2C_TIMEOUT_STOP 500000
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@ -97,6 +96,7 @@ static void i2c_rollback_vector_interrupt(i2c_t *obj);
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#define TRANCTRL_STARTED (1)
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#define TRANCTRL_NAKLASTDATA (1 << 1)
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#define TRANCTRL_LASTDATANAKED (1 << 2)
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uint32_t us_ticker_read(void);
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@ -168,7 +168,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
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return I2C_ERROR_BUS_BUSY;
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}
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if (i2c_do_write(obj, i2c_addr2data(address, 1), 0)) {
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if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) {
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE;
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}
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@ -191,7 +191,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
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return I2C_ERROR_BUS_BUSY;
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}
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if (i2c_do_write(obj, i2c_addr2data(address, 0), 0)) {
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if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) {
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i2c_stop(obj);
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
|
|
@ -214,14 +214,22 @@ void i2c_reset(i2c_t *obj)
|
|||
int i2c_byte_read(i2c_t *obj, int last)
|
||||
{
|
||||
char data = 0;
|
||||
|
||||
i2c_do_read(obj, &data, last);
|
||||
i2c_do_tran(obj, &data, 1, 1, last);
|
||||
return data;
|
||||
}
|
||||
|
||||
int i2c_byte_write(i2c_t *obj, int data)
|
||||
{
|
||||
return i2c_do_write(obj, (data & 0xFF), 0);
|
||||
char data_[1];
|
||||
data_[0] = data & 0xFF;
|
||||
|
||||
if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
|
||||
! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
#if DEVICE_I2CSLAVE
|
||||
|
|
@ -352,6 +360,10 @@ int i2c_allow_powerdown(void)
|
|||
|
||||
static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
|
||||
{
|
||||
if (! buf || ! length) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tran_len = 0;
|
||||
|
||||
i2c_disable_int(obj);
|
||||
|
|
@ -369,7 +381,6 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
|
|||
}
|
||||
else {
|
||||
i2c_disable_int(obj);
|
||||
obj->i2c.tran_ctrl = 0;
|
||||
tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
|
||||
obj->i2c.tran_beg = NULL;
|
||||
obj->i2c.tran_pos = NULL;
|
||||
|
|
@ -380,18 +391,6 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
|
|||
return tran_len;
|
||||
}
|
||||
|
||||
static int i2c_do_write(i2c_t *obj, char data, int naklastdata)
|
||||
{
|
||||
char data_[1];
|
||||
data_[0] = data;
|
||||
return i2c_do_tran(obj, data_, 1, 0, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
static int i2c_do_read(i2c_t *obj, char *data, int naklastdata)
|
||||
{
|
||||
return i2c_do_tran(obj, data, 1, 1, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
|
||||
{
|
||||
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
||||
|
|
@ -611,32 +610,30 @@ static void i2c_irq(i2c_t *obj)
|
|||
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
||||
}
|
||||
else {
|
||||
if (status == 0x18) {
|
||||
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
||||
i2c_disable_int(obj);
|
||||
break;
|
||||
}
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 0);
|
||||
}
|
||||
}
|
||||
else {
|
||||
i2c_disable_int(obj);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x30: // Master Transmit Data NACK
|
||||
case 0x20: // Master Transmit Address NACK
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
break;
|
||||
|
||||
case 0x20: // Master Transmit Address NACK
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
break;
|
||||
|
||||
case 0x38: // Master Arbitration Lost
|
||||
i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
||||
break;
|
||||
|
||||
case 0x48: // Master Receive Address NACK
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
break;
|
||||
|
||||
case 0x40: // Master Receive Address ACK
|
||||
case 0x50: // Master Receive Data ACK
|
||||
case 0x58: // Master Receive Data NACK
|
||||
|
|
@ -653,8 +650,7 @@ static void i2c_irq(i2c_t *obj)
|
|||
while (1);
|
||||
}
|
||||
#endif
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
}
|
||||
else {
|
||||
uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
|
||||
|
|
@ -821,6 +817,16 @@ static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
|
|||
obj->i2c.slaveaddr_state = NoData;
|
||||
}
|
||||
|
||||
static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked)
|
||||
{
|
||||
if (lastdatanaked) {
|
||||
obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED;
|
||||
}
|
||||
|
||||
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
||||
i2c_disable_int(obj);
|
||||
}
|
||||
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
|
||||
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
|
||||
|
|
|
|||
|
|
@ -5,6 +5,10 @@
|
|||
"help": "Enable GPIO IRQ debounce",
|
||||
"value": 0
|
||||
},
|
||||
"gpio-irq-debounce-enable-list": {
|
||||
"help": "Comma separated pin list to enable GPIO IRQ debounce",
|
||||
"value": "NC"
|
||||
},
|
||||
"gpio-irq-debounce-clock-source": {
|
||||
"help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
|
||||
"value": "GPIO_DBCTL_DBCLKSRC_LIRC"
|
||||
|
|
|
|||
|
|
@ -709,7 +709,12 @@ static uint8_t spi_get_data_width(spi_t *obj)
|
|||
{
|
||||
SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
|
||||
|
||||
return ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
|
||||
uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
|
||||
if (data_width == 0) {
|
||||
data_width = 32;
|
||||
}
|
||||
|
||||
return data_width;
|
||||
}
|
||||
|
||||
static int spi_is_tx_complete(spi_t *obj)
|
||||
|
|
|
|||
|
|
@ -44,18 +44,23 @@ typedef enum {
|
|||
#endif
|
||||
|
||||
typedef enum {
|
||||
ADC_0_0 = (int) NU_MODNAME(ADC_BASE, 0),
|
||||
ADC_0_1 = (int) NU_MODNAME(ADC_BASE, 1),
|
||||
ADC_0_2 = (int) NU_MODNAME(ADC_BASE, 2),
|
||||
ADC_0_3 = (int) NU_MODNAME(ADC_BASE, 3),
|
||||
ADC_0_4 = (int) NU_MODNAME(ADC_BASE, 4),
|
||||
ADC_0_5 = (int) NU_MODNAME(ADC_BASE, 5),
|
||||
ADC_0_6 = (int) NU_MODNAME(ADC_BASE, 6),
|
||||
ADC_0_7 = (int) NU_MODNAME(ADC_BASE, 7),
|
||||
ADC_0_8 = (int) NU_MODNAME(ADC_BASE, 8),
|
||||
ADC_0_9 = (int) NU_MODNAME(ADC_BASE, 9),
|
||||
ADC_0_10 = (int) NU_MODNAME(ADC_BASE, 10),
|
||||
ADC_0_11 = (int) NU_MODNAME(ADC_BASE, 11)
|
||||
ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0),
|
||||
ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 1),
|
||||
ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 2),
|
||||
ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 3),
|
||||
ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 4),
|
||||
ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 5),
|
||||
ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 6),
|
||||
ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 7),
|
||||
|
||||
ADC_1_0 = (int) NU_MODNAME(EADC_BASE, 8),
|
||||
ADC_1_1 = (int) NU_MODNAME(EADC_BASE, 9),
|
||||
ADC_1_2 = (int) NU_MODNAME(EADC_BASE, 10),
|
||||
ADC_1_3 = (int) NU_MODNAME(EADC_BASE, 11),
|
||||
ADC_1_4 = (int) NU_MODNAME(EADC_BASE, 12),
|
||||
ADC_1_5 = (int) NU_MODNAME(EADC_BASE, 13),
|
||||
ADC_1_6 = (int) NU_MODNAME(EADC_BASE, 14),
|
||||
ADC_1_7 = (int) NU_MODNAME(EADC_BASE, 15),
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
|
|
|
|||
|
|
@ -210,10 +210,14 @@ const PinMap PinMap_ADC[] = {
|
|||
{PE_6, ADC_0_6, SYS_GPE_MFPL_PE6MFP_ADC0_6}, // ADC0_6
|
||||
{PE_7, ADC_0_7, SYS_GPE_MFPL_PE7MFP_ADC0_7}, // ADC0_7
|
||||
|
||||
{PE_8, ADC_0_8, SYS_GPE_MFPH_PE8MFP_ADC1_0}, // ADC0_8/ADC1_0
|
||||
{PE_9, ADC_0_9, SYS_GPE_MFPH_PE9MFP_ADC1_1}, // ADC0_9/ADC1_1
|
||||
{PE_10, ADC_0_10, SYS_GPE_MFPH_PE10MFP_ADC1_2}, // ADC0_10/ADC1_2
|
||||
{PE_11, ADC_0_11, SYS_GPE_MFPH_PE11MFP_ADC1_3}, // ADC0_11/ADC1_3
|
||||
{PE_8, ADC_1_0, SYS_GPE_MFPH_PE8MFP_ADC1_0}, // ADC1_0
|
||||
{PE_9, ADC_1_1, SYS_GPE_MFPH_PE9MFP_ADC1_1}, // ADC1_1
|
||||
{PE_10, ADC_1_2, SYS_GPE_MFPH_PE10MFP_ADC1_2}, // ADC1_2
|
||||
{PE_11, ADC_1_3, SYS_GPE_MFPH_PE11MFP_ADC1_3}, // ADC1_3
|
||||
{PE_12, ADC_1_4, SYS_GPE_MFPH_PE12MFP_ADC1_4}, // ADC1_4
|
||||
{PE_13, ADC_1_5, SYS_GPE_MFPH_PE13MFP_ADC1_5}, // ADC1_5
|
||||
{PE_14, ADC_1_6, SYS_GPE_MFPH_PE14MFP_ADC1_6}, // ADC1_6
|
||||
{PE_15, ADC_1_7, SYS_GPE_MFPH_PE15MFP_ADC1_7}, // ADC1_7
|
||||
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
@ -367,25 +371,16 @@ const PinMap PinMap_UART_CTS[] = {
|
|||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PA_10, SPI_3, SYS_GPA_MFPH_PA10MFP_SPI3_MOSI0},
|
||||
{PA_12, SPI_3, SYS_GPA_MFPH_PA12MFP_SPI3_MOSI1},
|
||||
{PB_5, SPI_2, SYS_GPB_MFPL_PB5MFP_SPI2_MOSI0},
|
||||
{PB_13, SPI_2, SYS_GPB_MFPH_PB13MFP_SPI2_MOSI1},
|
||||
{PC_4, SPI_0, SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1},
|
||||
{PC_7, SPI_0, SYS_GPC_MFPL_PC7MFP_SPI0_MOSI0},
|
||||
{PC_13, SPI_1, SYS_GPC_MFPH_PC13MFP_SPI1_MOSI1},
|
||||
{PC_15, SPI_1, SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0},
|
||||
{PD_9, SPI_3, SYS_GPD_MFPH_PD9MFP_SPI3_MOSI1},
|
||||
{PE_3, SPI_0, SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0},
|
||||
{PE_7, SPI_0, SYS_GPE_MFPL_PE7MFP_SPI0_MOSI0},
|
||||
{PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI1},
|
||||
{PF_0, SPI_1, SYS_GPF_MFPL_PF0MFP_SPI1_MOSI0},
|
||||
{PF_1, SPI_2, SYS_GPF_MFPL_PF1MFP_SPI2_MOSI1},
|
||||
{PF_5, SPI_3, SYS_GPF_MFPL_PF5MFP_SPI3_MOSI0},
|
||||
{PG_8, SPI_2, SYS_GPG_MFPH_PG8MFP_SPI2_MOSI0},
|
||||
{PH_8, SPI_2, SYS_GPH_MFPH_PH8MFP_SPI2_MOSI0},
|
||||
{PH_10, SPI_2, SYS_GPH_MFPH_PH10MFP_SPI2_MOSI1},
|
||||
{PI_6, SPI_3, SYS_GPI_MFPL_PI6MFP_SPI3_MOSI0},
|
||||
{PI_8, SPI_3, SYS_GPI_MFPH_PI8MFP_SPI3_MOSI1},
|
||||
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
@ -393,25 +388,16 @@ const PinMap PinMap_SPI_MOSI[] = {
|
|||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{PA_2, SPI_3, SYS_GPA_MFPL_PA2MFP_SPI3_MISO0},
|
||||
{PA_9, SPI_3, SYS_GPA_MFPH_PA9MFP_SPI3_MISO0},
|
||||
{PA_11, SPI_3, SYS_GPA_MFPH_PA11MFP_SPI3_MISO1},
|
||||
{PB_4, SPI_2, SYS_GPB_MFPL_PB4MFP_SPI2_MISO0},
|
||||
{PB_12, SPI_2, SYS_GPB_MFPH_PB12MFP_SPI2_MISO1},
|
||||
{PC_3, SPI_0, SYS_GPC_MFPL_PC3MFP_SPI0_MISO1},
|
||||
{PC_6, SPI_0, SYS_GPC_MFPL_PC6MFP_SPI0_MISO0},
|
||||
{PC_14, SPI_1, SYS_GPC_MFPH_PC14MFP_SPI1_MISO1},
|
||||
{PD_0, SPI_1, SYS_GPD_MFPL_PD0MFP_SPI1_MISO0},
|
||||
{PD_8, SPI_3, SYS_GPD_MFPH_PD8MFP_SPI3_MISO1},
|
||||
{PD_15, SPI_1, SYS_GPD_MFPH_PD15MFP_SPI1_MISO0},
|
||||
{PE_2, SPI_0, SYS_GPE_MFPL_PE2MFP_SPI0_MISO0},
|
||||
{PE_6, SPI_0, SYS_GPE_MFPL_PE6MFP_SPI0_MISO0},
|
||||
{PE_10, SPI_0, SYS_GPE_MFPH_PE10MFP_SPI0_MISO1},
|
||||
{PF_4, SPI_3, SYS_GPF_MFPL_PF4MFP_SPI3_MISO0},
|
||||
{PG_7, SPI_2, SYS_GPG_MFPL_PG7MFP_SPI2_MISO0},
|
||||
{PH_7, SPI_2, SYS_GPH_MFPL_PH7MFP_SPI2_MISO0},
|
||||
{PH_9, SPI_2, SYS_GPH_MFPH_PH9MFP_SPI2_MISO1},
|
||||
{PI_5, SPI_3, SYS_GPI_MFPL_PI5MFP_SPI3_MISO0},
|
||||
{PI_7, SPI_3, SYS_GPI_MFPL_PI7MFP_SPI3_MISO1},
|
||||
{PI_12, SPI_2, SYS_GPI_MFPH_PI12MFP_SPI2_MISO1},
|
||||
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -77,6 +77,8 @@ void mbed_sdk_init(void)
|
|||
#if DEVICE_ANALOGIN
|
||||
/* Vref connect to AVDD */
|
||||
SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
|
||||
/* Switch ADC0 to EADC mode */
|
||||
SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_ADCMODESEL_Msk) | SYS_VREFCTL_ADCMODESEL_EADC;
|
||||
#endif
|
||||
|
||||
/* Update System Core Clock */
|
||||
|
|
|
|||
|
|
@ -23,60 +23,26 @@
|
|||
#include "PeripheralPins.h"
|
||||
#include "nu_modutil.h"
|
||||
|
||||
struct nu_adc_var {
|
||||
uint32_t en_msk;
|
||||
};
|
||||
|
||||
static struct nu_adc_var adc0_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc1_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc2_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc3_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc4_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc5_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc6_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc7_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc8_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc9_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc10_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static struct nu_adc_var adc11_var = {
|
||||
.en_msk = 0
|
||||
};
|
||||
static uint32_t eadc_modinit_mask = 0;
|
||||
|
||||
static const struct nu_modinit_s adc_modinit_tab[] = {
|
||||
{ADC_0_0, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc0_var},
|
||||
{ADC_0_1, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc1_var},
|
||||
{ADC_0_2, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc2_var},
|
||||
{ADC_0_3, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc3_var},
|
||||
{ADC_0_4, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc4_var},
|
||||
{ADC_0_5, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc5_var},
|
||||
{ADC_0_6, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc6_var},
|
||||
{ADC_0_7, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc7_var},
|
||||
{ADC_0_8, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc8_var},
|
||||
{ADC_0_9, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc9_var},
|
||||
{ADC_0_10, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc10_var},
|
||||
{ADC_0_11, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc11_var}
|
||||
{ADC_0_0, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_0_1, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_0_2, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_0_3, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_0_4, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_0_5, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_0_6, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_0_7, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
|
||||
{ADC_1_0, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_1_1, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_1_2, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_1_3, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_1_4, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_1_5, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_1_6, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
|
||||
{ADC_1_7, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL}
|
||||
};
|
||||
|
||||
void analogin_init(analogin_t *obj, PinName pin)
|
||||
|
|
@ -88,8 +54,10 @@ void analogin_init(analogin_t *obj, PinName pin)
|
|||
MBED_ASSERT(modinit != NULL);
|
||||
MBED_ASSERT(modinit->modname == obj->adc);
|
||||
|
||||
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
|
||||
|
||||
// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
|
||||
if (! ((struct nu_adc_var *) modinit->var)->en_msk) {
|
||||
if (! eadc_modinit_mask) {
|
||||
// Reset this module if no channel enabled
|
||||
SYS_ResetModule(modinit->rsetidx);
|
||||
|
||||
|
|
@ -98,33 +66,29 @@ void analogin_init(analogin_t *obj, PinName pin)
|
|||
// Enable clock of paired channels
|
||||
CLK_EnableModuleClock(modinit->clkidx);
|
||||
|
||||
// Power on ADC
|
||||
ADC_POWER_ON(ADC);
|
||||
// Make EADC_module ready to convert
|
||||
EADC_Open(eadc_base, 0);
|
||||
}
|
||||
|
||||
ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
|
||||
uint32_t chn = NU_MODSUBINDEX(obj->adc);
|
||||
|
||||
// Wire pinout
|
||||
pinmap_pinout(pin, PinMap_ADC);
|
||||
|
||||
// Enable channel 0
|
||||
ADC_Open(adc_base,
|
||||
ADC_INPUT_MODE_SINGLE_END,
|
||||
ADC_OPERATION_MODE_SINGLE,
|
||||
1 << chn); // ADC_CH_0_MASK~ADC_CH_11_MASK
|
||||
// Configure the sample module Nmod for analog input channel Nch and software trigger source
|
||||
EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn % 8);
|
||||
|
||||
((struct nu_adc_var *) modinit->var)->en_msk |= 1 << chn;
|
||||
eadc_modinit_mask |= 1 << chn;
|
||||
}
|
||||
|
||||
uint16_t analogin_read_u16(analogin_t *obj)
|
||||
{
|
||||
ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
|
||||
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
|
||||
uint32_t chn = NU_MODSUBINDEX(obj->adc);
|
||||
|
||||
ADC_START_CONV(adc_base);
|
||||
while (adc_base->CTL & ADC_CTL_SWTRG_Msk);
|
||||
uint16_t conv_res_12 = ADC_GET_CONVERSION_DATA(adc_base, chn);
|
||||
EADC_START_CONV(eadc_base, 1 << chn);
|
||||
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != (1 << chn));
|
||||
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
|
||||
// Just 12 bits are effective. Convert to 16 bits.
|
||||
// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
|
||||
// conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/**************************************************************************//**
|
||||
* @file clk.c
|
||||
* @version V1.00
|
||||
* $Revision: 29 $
|
||||
* $Date: 14/09/26 2:10p $
|
||||
* $Revision: 35 $
|
||||
* $Date: 16/03/04 3:42p $
|
||||
* @brief NUC472/NUC442 CLK driver source file
|
||||
*
|
||||
* @note
|
||||
|
|
@ -84,7 +84,13 @@ void CLK_PowerDown(void)
|
|||
*/
|
||||
void CLK_Idle(void)
|
||||
{
|
||||
CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk );
|
||||
/* Set the processor uses sleep as its low power mode */
|
||||
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Set chip in idle mode because of WFI command */
|
||||
CLK->PWRCTL &= ~(CLK_PWRCTL_PDEN_Msk );
|
||||
|
||||
/* Chip enter idle mode after CPU run WFI instruction */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
|
|
@ -162,8 +168,8 @@ uint32_t CLK_GetPLLClockFreq(void)
|
|||
|
||||
u32PllReg = CLK->PLLCTL;
|
||||
|
||||
if((u32PllReg & CLK_PLLCTL_PLLREMAP_Msk))
|
||||
return 0;
|
||||
if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
|
||||
return 0; /* PLL is in power down mode or fix low */
|
||||
|
||||
if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
|
||||
u32PLLSrc = __HIRC;
|
||||
|
|
@ -187,8 +193,8 @@ uint32_t CLK_GetPLLClockFreq(void)
|
|||
u32NF = (u32PllReg & CLK_PLLCTL_FBDIV_Msk) + 2;
|
||||
u32NR = ( (u32PllReg & CLK_PLLCTL_INDIV_Msk)>>CLK_PLLCTL_INDIV_Pos ) + 2;
|
||||
|
||||
u32Freq = u32PLLSrc * u32NF / u32NR / u32NO ;
|
||||
|
||||
/* u32PLLSrc is shifted 2 bits to avoid overflow */
|
||||
u32Freq = (((u32PLLSrc >> 2) * u32NF) / (u32NR * u32NO) << 2);
|
||||
return u32Freq;
|
||||
}
|
||||
|
||||
|
|
@ -272,7 +278,7 @@ void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
|||
* |\ref EBI_MODULE | x | x |
|
||||
* |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
|
||||
* |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL2 |\ref CLK_CLKDIV0_USB(x) |
|
||||
* |\ref EMAC_MODULE |\ref CLK_CLKSEL0_EMACSEL_PLL |\ref CLK_CLKDIV3_EMAC(x) |
|
||||
* |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) |
|
||||
* |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HXT |\ref CLK_CLKDIV0_SDH(x) |
|
||||
* |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_PLL |\ref CLK_CLKDIV0_SDH(x) |
|
||||
* |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HCLK |\ref CLK_CLKDIV0_SDH(x) |
|
||||
|
|
@ -282,15 +288,16 @@ void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
|||
* |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_PLL2 |\ref CLK_CLKDIV3_CAP(x) |
|
||||
* |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HCLK |\ref CLK_CLKDIV3_CAP(x) |
|
||||
* |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HIRC |\ref CLK_CLKDIV3_CAP(x) |
|
||||
* |\ref SENCLK_MODULE | x | x |
|
||||
* |\ref SEN_MODULE | x | x |
|
||||
* |\ref USBD_MODULE | x | x |
|
||||
* |\ref CRPT_MODULE | x | x |
|
||||
* |\ref ECAP1_MODULE | x | x |
|
||||
* |\ref ECAP0_MODULE | x | x |
|
||||
* |\ref EADC_MODULE | x | x |
|
||||
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref OPA_MODULE | x | x |
|
||||
* |\ref TAMPER_MODULE | x | x |
|
||||
* |\ref TAMPER_MODULE | x | x |
|
||||
* |\ref QEI1_MODULE | x | x |
|
||||
* |\ref QEI0_MODULE | x | x |
|
||||
* |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HXT | x |
|
||||
|
|
@ -352,9 +359,15 @@ void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
|||
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
|
||||
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK |\ref CLK_CLKDIV1_SC0(x) |
|
||||
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
|
||||
* |\ref PS2_MODULE | x | x |
|
||||
* |\ref I2S1_MODULE | x | x |
|
||||
* |\ref I2S0_MODULE | x | x |
|
||||
* |\ref PS2_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x |
|
||||
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x |
|
||||
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PLL | x |
|
||||
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PCLK | x |
|
||||
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HIRC | x |
|
||||
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x |
|
||||
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x |
|
||||
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK | x |
|
||||
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) |
|
||||
|
|
@ -488,7 +501,6 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
|
|||
* - \ref SDH_MODULE
|
||||
* - \ref CRC_MODULE
|
||||
* - \ref CAP_MODULE
|
||||
* - \ref SENCLK_MODULE
|
||||
* - \ref USBD_MODULE
|
||||
* - \ref CRPT_MODULE
|
||||
* - \ref WDT_MODULE
|
||||
|
|
@ -536,7 +548,6 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
|
|||
* - \ref PWM1CH45_MODULE
|
||||
* - \ref QEI0_MODULE
|
||||
* - \ref QEI1_MODULE
|
||||
* - \ref TAMPER_MODULE
|
||||
* - \ref ECAP0_MODULE
|
||||
* - \ref ECAP1_MODULE
|
||||
* - \ref EPWM0_MODULE
|
||||
|
|
@ -547,7 +558,7 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
|
|||
*/
|
||||
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
|
||||
{
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_AHPBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -561,7 +572,6 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
|
|||
* - \ref SDH_MODULE
|
||||
* - \ref CRC_MODULE
|
||||
* - \ref CAP_MODULE
|
||||
* - \ref SENCLK_MODULE
|
||||
* - \ref USBD_MODULE
|
||||
* - \ref CRPT_MODULE
|
||||
* - \ref WDT_MODULE
|
||||
|
|
@ -609,7 +619,6 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
|
|||
* - \ref PWM1CH45_MODULE
|
||||
* - \ref QEI0_MODULE
|
||||
* - \ref QEI1_MODULE
|
||||
* - \ref TAMPER_MODULE
|
||||
* - \ref ECAP0_MODULE
|
||||
* - \ref ECAP1_MODULE
|
||||
* - \ref EPWM0_MODULE
|
||||
|
|
@ -620,7 +629,7 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
|
|||
*/
|
||||
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
|
||||
{
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_AHPBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -633,32 +642,101 @@ void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
|
|||
*/
|
||||
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
|
||||
{
|
||||
uint32_t u32Register,u32ClkSrc,u32NF,u32NR;
|
||||
uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
|
||||
uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
|
||||
|
||||
if(u32PllClkSrc==CLK_PLLCTL_PLLSRC_HIRC) {
|
||||
CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PD_Msk) | (CLK_PLLCTL_PLLSRC_HIRC);
|
||||
u32Register = 1<<CLK_PLLCTL_PLLSRC_Pos;
|
||||
u32ClkSrc = __HIRC;
|
||||
} else {
|
||||
CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PD_Msk);
|
||||
u32Register = 0<<CLK_PLLCTL_PLLSRC_Pos;
|
||||
u32ClkSrc = __HXT;
|
||||
/* Disable PLL first to avoid unstable when setting PLL */
|
||||
CLK_DisablePLL();
|
||||
|
||||
/* PLL source clock is from HXT */
|
||||
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
|
||||
/* Enable HXT clock */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
|
||||
|
||||
/* Wait for HXT clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
|
||||
|
||||
/* Select PLL source clock from HXT */
|
||||
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
|
||||
u32PllSrcClk = __HXT;
|
||||
|
||||
/* u32NR start from 2 */
|
||||
u32NR = 2;
|
||||
}
|
||||
|
||||
if(u32PllFreq<FREQ_50MHZ) {
|
||||
u32PllFreq <<=2;
|
||||
u32Register |= (0x3<<CLK_PLLCTL_OUTDV_Pos);
|
||||
/* PLL source clock is from HIRC */
|
||||
else {
|
||||
/* Enable HIRC clock */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
|
||||
|
||||
/* Wait for HIRC clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
|
||||
/* Select PLL source clock from HIRC */
|
||||
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
|
||||
u32PllSrcClk = __HIRC;
|
||||
|
||||
/* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
|
||||
u32NR = 4;
|
||||
}
|
||||
|
||||
/* Select "NO" according to request frequency */
|
||||
if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ)) {
|
||||
u32NO = 0;
|
||||
} else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ)) {
|
||||
u32NO = 1;
|
||||
u32PllFreq = u32PllFreq << 1;
|
||||
} else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ)) {
|
||||
u32NO = 3;
|
||||
u32PllFreq = u32PllFreq << 2;
|
||||
} else {
|
||||
u32PllFreq <<=1;
|
||||
u32Register |= (0x1<<CLK_PLLCTL_OUTDV_Pos);
|
||||
/* Wrong frequency request. Just return default setting. */
|
||||
goto lexit;
|
||||
}
|
||||
u32NF = u32PllFreq / 1000000;
|
||||
u32NR = u32ClkSrc / 1000000;
|
||||
while( u32NR>(0xF+2) || u32NF>(0xFF+2) ) {
|
||||
u32NR = u32NR>>1;
|
||||
u32NF = u32NF>>1;
|
||||
|
||||
/* Find best solution */
|
||||
u32Min = (uint32_t) - 1;
|
||||
u32MinNR = 0;
|
||||
u32MinNF = 0;
|
||||
for(; u32NR <= 33; u32NR++) {
|
||||
u32Tmp = u32PllSrcClk / u32NR;
|
||||
if((u32Tmp > 1600000) && (u32Tmp < 16000000)) {
|
||||
for(u32NF = 2; u32NF <= 513; u32NF++) {
|
||||
u32Tmp2 = u32Tmp * u32NF;
|
||||
if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000)) {
|
||||
u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
|
||||
if(u32Tmp3 < u32Min) {
|
||||
u32Min = u32Tmp3;
|
||||
u32MinNR = u32NR;
|
||||
u32MinNF = u32NF;
|
||||
|
||||
/* Break when get good results */
|
||||
if(u32Min == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
CLK->PLLCTL = u32Register | ((u32NR - 2)<<9) | (u32NF - 2) ;
|
||||
|
||||
/* Enable and apply new PLL setting. */
|
||||
CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
|
||||
|
||||
/* Wait for PLL clock stable */
|
||||
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
|
||||
|
||||
/* Return actual PLL output clock frequency */
|
||||
return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
|
||||
|
||||
lexit:
|
||||
|
||||
/* Apply default PLL setting and return */
|
||||
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
|
||||
CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* 84MHz */
|
||||
else
|
||||
CLK->PLLCTL = CLK_PLLCTL_50MHz_HIRC; /* 50MHz */
|
||||
|
||||
/* Wait for PLL clock stable */
|
||||
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
|
||||
|
||||
return CLK_GetPLLClockFreq();
|
||||
|
|
@ -670,7 +748,7 @@ uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
|
|||
*/
|
||||
void CLK_DisablePLL(void)
|
||||
{
|
||||
CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
|
||||
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -703,6 +781,7 @@ void CLK_SysTickDelay(uint32_t us)
|
|||
|
||||
/* Waiting for down-count to zero */
|
||||
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
|
||||
SysTick->CTRL = 0 ;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -718,21 +797,66 @@ void CLK_SysTickDelay(uint32_t us)
|
|||
* @return 0 clock is not stable
|
||||
* 1 clock is stable
|
||||
*
|
||||
* @details To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)
|
||||
* @details To wait for clock ready by specified CLKSTATUS bit or timeout (~300ms)
|
||||
*/
|
||||
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
|
||||
{
|
||||
int32_t i32TimeOutCnt;
|
||||
|
||||
i32TimeOutCnt = __HSI / 200; /* About 5ms */
|
||||
int32_t i32TimeOutCnt = 2160000;
|
||||
|
||||
while((CLK->STATUS & u32ClkMask) != u32ClkMask) {
|
||||
if(i32TimeOutCnt-- <= 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable System Tick counter
|
||||
* @param[in] u32ClkSrc is System Tick clock source. Including:
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HXT
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_LXT
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK
|
||||
* @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
|
||||
* @return None
|
||||
* @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
|
||||
{
|
||||
/* Set System Tick counter disabled */
|
||||
SysTick->CTRL = 0;
|
||||
|
||||
/* Set System Tick clock source */
|
||||
if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
|
||||
SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
|
||||
else
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
|
||||
|
||||
/* Set System Tick reload value */
|
||||
SysTick->LOAD = u32Count;
|
||||
|
||||
/* Clear System Tick current value and counter flag */
|
||||
SysTick->VAL = 0;
|
||||
|
||||
/* Set System Tick interrupt enabled and counter enabled */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable System Tick counter
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function disable System Tick counter.
|
||||
*/
|
||||
void CLK_DisableSysTick(void)
|
||||
{
|
||||
/* Set System Tick counter disabled */
|
||||
SysTick->CTRL = 0;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* @file CLK.h
|
||||
* @version V1.0
|
||||
* $Revision 1 $
|
||||
* $Date: 14/10/06 1:50p $
|
||||
* $Date: 15/11/19 10:06a $
|
||||
* @brief NUC472/NUC442 CLK Header File
|
||||
*
|
||||
* @note
|
||||
|
|
@ -30,11 +30,18 @@ extern "C"
|
|||
@{
|
||||
*/
|
||||
|
||||
#define FREQ_50MHZ 50000000
|
||||
#define FREQ_24MHZ 24000000
|
||||
#define FREQ_22MHZ 22000000
|
||||
#define FREQ_32KHZ 32767
|
||||
#define FREQ_10KHZ 10000
|
||||
#define FREQ_500MHZ 500000000
|
||||
#define FREQ_250MHZ 250000000
|
||||
#define FREQ_200MHZ 200000000
|
||||
#define FREQ_125MHZ 125000000
|
||||
#define FREQ_72MHZ 72000000
|
||||
#define FREQ_50MHZ 50000000
|
||||
#define FREQ_25MHZ 25000000
|
||||
#define FREQ_24MHZ 24000000
|
||||
#define FREQ_22MHZ 22000000
|
||||
#define FREQ_32KHZ 32000
|
||||
#define FREQ_10KHZ 10000
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
|
@ -69,9 +76,7 @@ extern "C"
|
|||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PLL2CTL constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_PLL2CTL_USPLL(x) (((x)-1) << CLK_PLL2CTL_PLL2DIV_Pos) /*!< USBPLL clock frequency = (480 MHz) / 2 / (USB_N + 1). It could be 1~256, Max. PLL frequency :480MHz / 2 when XTL12M. \hideinitializer */
|
||||
#define CLK_PLL2CTL_USBPLL_DIS (0x00UL<<CLK_PLL2CTL_PLL2CKEN_Pos) /*!< USB PHY PLL (480MHz) Disable \hideinitializer */
|
||||
#define CLK_PLL2CTL_PLL2CKEN (0x01UL<<CLK_PLL2CTL_PLL2CKEN_Pos) /*!< USB PHY PLL (480MHz) Enable \hideinitializer */
|
||||
#define CLK_PLL2CTL_PLL2DIV(x) (((x)-1) << CLK_PLL2CTL_PLL2DIV_Pos) /*!< USBPLL clock frequency = (480 MHz) / 2 / (USB_N + 1). It could be 1~256, Max. PLL frequency :480MHz / 2 when XTL12M. \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL0 constant definitions. (Write-protection) */
|
||||
|
|
@ -80,7 +85,7 @@ extern "C"
|
|||
#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL output \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 10KHz RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_USBPLL (0x04UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as USBPLL clock \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_PLL2 (0x04UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as USBPLL clock \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
|
||||
|
|
@ -88,20 +93,24 @@ extern "C"
|
|||
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL/2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock/2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
|
||||
|
||||
#define CLK_CLKSEL0_PCLKSEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
|
||||
#define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_USBHSEL_PLL2 (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_EMACSEL_PLL (0x01UL<<10) /*!< Setting clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL0_USBHSEL_PLL2 (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_CAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
|
||||
#define CLK_CLKSEL0_CAPSEL_PLL2 (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_CAPSEL_PLL (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL0_CAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
|
||||
#define CLK_CLKSEL0_CAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_ICAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
|
||||
#define CLK_CLKSEL0_ICAPSEL_PLL (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL0_ICAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
|
||||
#define CLK_CLKSEL0_ICAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_SDHSEL_HXT (0x00UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
|
||||
#define CLK_CLKSEL0_SDHSEL_PLL (0x01UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_SDHSEL_HCLK (0x02UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
|
||||
|
|
@ -110,6 +119,7 @@ extern "C"
|
|||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL1 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL1_WDTSEL_HXT (0x0UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external XTAL \hideinitializer */
|
||||
#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external XTAL 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 \hideinitializer */
|
||||
#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as internal 10KHz RC clock \hideinitializer */
|
||||
|
|
@ -119,6 +129,11 @@ extern "C"
|
|||
#define CLK_CLKSEL1_ADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as PCLK \hideinitializer */
|
||||
#define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as internal 22.1184MHz RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_EADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as external XTAL \hideinitializer */
|
||||
#define CLK_CLKSEL1_EADCSEL_PLL (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL1_EADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as PCLK \hideinitializer */
|
||||
#define CLK_CLKSEL1_EADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as internal 22.1184MHz RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL1_SPI0SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK \hideinitializer */
|
||||
|
||||
|
|
@ -280,15 +295,15 @@ extern "C"
|
|||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKDIV3 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKDIV3_CAP(x) (((x)-1) << CLK_CLKDIV3_ICAPDIV_Pos) /*!< CLKDIV Setting for CAP Engine clock divider. It could be 1~256 \hideinitializer */
|
||||
#define CLK_CLKDIV3_VASENSOR(x) (((x)-1) << CLK_CLKDIV3_VASENSORDIV_Pos) /*!< CLKDIV Setting for Video Pixel clock divider. It could be 1~256 \hideinitializer */
|
||||
#define CLK_CLKDIV3_CAP(x) (((x)-1) << CLK_CLKDIV3_CAPDIV_Pos) /*!< CLKDIV Setting for CAP Engine clock divider. It could be 1~256 \hideinitializer */
|
||||
#define CLK_CLKDIV3_VSENSE(x) (((x)-1) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV Setting for Video Pixel clock divider. It could be 1~256 \hideinitializer */
|
||||
#define CLK_CLKDIV3_EMAC(x) (((x)-1) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV Setting for EMAC_MDCLK clock divider. It could be 1~256 \hideinitializer */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* MODULE constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define MODULE_AHPBCLK(x) ((x >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index \hideinitializer */
|
||||
#define MODULE_APBCLK(x) ((x >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKSEL(x) ((x >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
|
||||
|
|
@ -297,6 +312,16 @@ extern "C"
|
|||
#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
|
||||
#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
|
||||
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index \hideinitializer */
|
||||
#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
|
||||
|
||||
#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
|
||||
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
|
||||
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */
|
||||
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
|
||||
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
|
||||
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
|
||||
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
|
||||
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */
|
||||
/*--------------------------------------------------------------------------------------------------------------------------------------*/
|
||||
/* AHBCLK/APBCLK(2) | CLKSEL(2) | CLKSEL_Msk(3) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
|
||||
/*--------------------------------------------------------------------------------------------------------------------------------------*/
|
||||
|
|
@ -304,15 +329,15 @@ extern "C"
|
|||
#define ISP_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos) /*!< ISP Module \hideinitializer */
|
||||
#define EBI_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBICKEN_Pos) /*!< EBI Module \hideinitializer */
|
||||
#define USBH_MODULE ((0UL<<30)|(0<<28)|(1<<25) |( 8<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_AHBCLK_USBHCKEN_Pos) /*!< USBH Module \hideinitializer */
|
||||
#define EMAC_MODULE ((0UL<<30)|(0<<28)|(1<<25) |(10<<20)|(3<<18)|(0xFF<<10) |(16<<5)|CLK_AHBCLK_EMACCKEN_Pos) /*!< EMAC Module \hideinitializer */
|
||||
#define EMAC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|(10<<20)|(3<<18)|(0xFF<<10) |(16<<5)|CLK_AHBCLK_EMACCKEN_Pos) /*!< EMAC Module \hideinitializer */
|
||||
#define SDH_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(20<<20)|(0<<18)|(0xFF<<10) |(24<<5)|CLK_AHBCLK_SDHCKEN_Pos) /*!< SDH Module \hideinitializer */
|
||||
#define CRC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRCCKEN_Pos) /*!< CRC Module \hideinitializer */
|
||||
#define CAP_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(16<<20)|(3<<18)|(0xFF<<10) |( 0<<5)|CLK_AHBCLK_ICAPCKEN_Pos) /*!< CAP Module \hideinitializer */
|
||||
#define SENCLK_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(3<<18)|(0xFF<<10) |( 8<<5)|CLK_AHBCLK_SENCLKCKEN_Pos) /*!< Sensor Clock Module \hideinitializer */
|
||||
#define CAP_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(16<<20)|(3<<18)|(0xFF<<10) |( 0<<5)|CLK_AHBCLK_CAPCKEN_Pos) /*!< CAP Module \hideinitializer */
|
||||
#define SEN_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(3<<18)|(0xFF<<10) |( 8<<5)|CLK_AHBCLK_SENCKEN_Pos) /*!< Sensor Clock Module \hideinitializer */
|
||||
#define USBD_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_USBDCKEN_Pos) /*!< USBD Module \hideinitializer */
|
||||
#define CRPT_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRPTCKEN_Pos) /*!< CRYPTO Module \hideinitializer */
|
||||
|
||||
#define WDT_MODULE ((1UL<<30)|(3<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Watchdog Timer Module \hideinitializer */
|
||||
#define WDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Watchdog Timer Module \hideinitializer */
|
||||
#define WWDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(30<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Window Watchdog Timer Module \hideinitializer */
|
||||
#define RTC_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_RTCCKEN_Pos) /*!< RTC Module \hideinitializer */
|
||||
#define TMR0_MODULE ((1UL<<30)|(1<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR0CKEN_Pos) /*!< Timer0 Module \hideinitializer */
|
||||
|
|
@ -358,13 +383,12 @@ extern "C"
|
|||
#define PWM1CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH45CKEN_Pos) /*!< PWM1CH45 Module \hideinitializer */
|
||||
#define QEI0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI0CKEN_Pos) /*!< QEI0 Module \hideinitializer */
|
||||
#define QEI1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI1CKEN_Pos) /*!< QEI1 Module \hideinitializer */
|
||||
#define TAMPER_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_TAMPERCKEN_Pos) /*!< TAMPER Module \hideinitializer */
|
||||
#define ECAP0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP0CKEN_Pos) /*!< ECAP0 Module \hideinitializer */
|
||||
#define ECAP1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP1CKEN_Pos) /*!< ECAP1 Module \hideinitializer */
|
||||
#define EPWM0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM0CKEN_Pos) /*!< EPWM0 Module \hideinitializer */
|
||||
#define EPWM1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM1CKEN_Pos) /*!< EPWM1 Module \hideinitializer */
|
||||
#define OPA_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_OPACKEN_Pos) /*!< OPA Module \hideinitializer */
|
||||
#define EADC_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EADCCKEN_Pos) /*!< EADC Module \hideinitializer */
|
||||
#define EADC_MODULE ((2UL<<30)|(1<<28)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK1_EADCCKEN_Pos) /*!< EADC Module \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_CONSTANTS */
|
||||
|
||||
|
|
@ -395,6 +419,8 @@ uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
|
|||
void CLK_DisablePLL(void);
|
||||
void CLK_SysTickDelay(uint32_t us);
|
||||
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
|
||||
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
|
||||
void CLK_DisableSysTick(void);
|
||||
|
||||
/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
|
||||
|
||||
|
|
|
|||
|
|
@ -58,22 +58,23 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
|
|||
|
||||
#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
|
||||
|
||||
#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
|
||||
#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
|
||||
#else
|
||||
#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
|
||||
#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
|
||||
#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
|
||||
#endif
|
||||
|
||||
#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
|
||||
#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
|
||||
#else
|
||||
#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
|
||||
#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
|
||||
#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
|
||||
#endif
|
||||
static PinName gpio_irq_debounce_arr[] = {
|
||||
MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
|
||||
};
|
||||
|
||||
#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
|
||||
#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
|
||||
#endif
|
||||
|
||||
#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
|
||||
#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
|
||||
#else
|
||||
#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
|
||||
#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
|
||||
#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
|
||||
#endif
|
||||
|
||||
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
|
||||
|
|
@ -95,13 +96,36 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
|
|||
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
|
||||
//gpio_set(pin);
|
||||
|
||||
#if NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
|
||||
// Configure de-bounce clock source and sampling cycle time
|
||||
GPIO_SET_DEBOUNCE_TIME(NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
|
||||
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||
{
|
||||
#if MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
|
||||
// Suppress compiler warning
|
||||
(void) gpio_irq_debounce_arr;
|
||||
|
||||
// Configure de-bounce clock source and sampling cycle time
|
||||
GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
|
||||
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||
#else
|
||||
GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||
// Enable de-bounce if the pin is in the de-bounce enable list
|
||||
|
||||
// De-bounce defaults to disabled.
|
||||
GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||
|
||||
PinName *debounce_pos = gpio_irq_debounce_arr;
|
||||
PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
|
||||
for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
|
||||
uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
|
||||
uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
|
||||
|
||||
if (pin_index == pin_index_debunce &&
|
||||
port_index == port_index_debounce) {
|
||||
// Configure de-bounce clock source and sampling cycle time
|
||||
GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
|
||||
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ static void i2c3_vec(void);
|
|||
static void i2c4_vec(void);
|
||||
static void i2c_irq(i2c_t *obj);
|
||||
static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
|
||||
static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked);
|
||||
|
||||
static struct nu_i2c_var i2c0_var = {
|
||||
.obj = NULL,
|
||||
|
|
@ -86,8 +87,6 @@ static const struct nu_modinit_s i2c_modinit_tab[] = {
|
|||
};
|
||||
|
||||
static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
|
||||
static int i2c_do_write(i2c_t *obj, char data, int naklastdata);
|
||||
static int i2c_do_read(i2c_t *obj, char *data, int naklastdata);
|
||||
static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
|
||||
#define NU_I2C_TIMEOUT_STAT_INT 500000
|
||||
#define NU_I2C_TIMEOUT_STOP 500000
|
||||
|
|
@ -114,6 +113,7 @@ static void i2c_rollback_vector_interrupt(i2c_t *obj);
|
|||
|
||||
#define TRANCTRL_STARTED (1)
|
||||
#define TRANCTRL_NAKLASTDATA (1 << 1)
|
||||
#define TRANCTRL_LASTDATANAKED (1 << 2)
|
||||
|
||||
uint32_t us_ticker_read(void);
|
||||
|
||||
|
|
@ -185,7 +185,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
|||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
if (i2c_do_write(obj, i2c_addr2data(address, 1), 0)) {
|
||||
if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) {
|
||||
i2c_stop(obj);
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
|
|
@ -208,7 +208,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
|||
return I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
if (i2c_do_write(obj, i2c_addr2data(address, 0), 0)) {
|
||||
if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) {
|
||||
i2c_stop(obj);
|
||||
return I2C_ERROR_NO_SLAVE;
|
||||
}
|
||||
|
|
@ -231,14 +231,22 @@ void i2c_reset(i2c_t *obj)
|
|||
int i2c_byte_read(i2c_t *obj, int last)
|
||||
{
|
||||
char data = 0;
|
||||
|
||||
i2c_do_read(obj, &data, last);
|
||||
i2c_do_tran(obj, &data, 1, 1, last);
|
||||
return data;
|
||||
}
|
||||
|
||||
int i2c_byte_write(i2c_t *obj, int data)
|
||||
{
|
||||
return i2c_do_write(obj, (data & 0xFF), 0);
|
||||
char data_[1];
|
||||
data_[0] = data & 0xFF;
|
||||
|
||||
if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
|
||||
! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
#if DEVICE_I2CSLAVE
|
||||
|
|
@ -369,6 +377,10 @@ int i2c_allow_powerdown(void)
|
|||
|
||||
static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
|
||||
{
|
||||
if (! buf || ! length) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tran_len = 0;
|
||||
|
||||
i2c_disable_int(obj);
|
||||
|
|
@ -386,7 +398,6 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
|
|||
}
|
||||
else {
|
||||
i2c_disable_int(obj);
|
||||
obj->i2c.tran_ctrl = 0;
|
||||
tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
|
||||
obj->i2c.tran_beg = NULL;
|
||||
obj->i2c.tran_pos = NULL;
|
||||
|
|
@ -397,18 +408,6 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
|
|||
return tran_len;
|
||||
}
|
||||
|
||||
static int i2c_do_write(i2c_t *obj, char data, int naklastdata)
|
||||
{
|
||||
char data_[1];
|
||||
data_[0] = data;
|
||||
return i2c_do_tran(obj, data_, 1, 0, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
static int i2c_do_read(i2c_t *obj, char *data, int naklastdata)
|
||||
{
|
||||
return i2c_do_tran(obj, data, 1, 1, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
|
||||
}
|
||||
|
||||
static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
|
||||
{
|
||||
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
||||
|
|
@ -641,33 +640,30 @@ static void i2c_irq(i2c_t *obj)
|
|||
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
||||
}
|
||||
else {
|
||||
if (status == 0x18) {
|
||||
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
||||
i2c_disable_int(obj);
|
||||
break;
|
||||
}
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 0);
|
||||
}
|
||||
}
|
||||
else {
|
||||
i2c_disable_int(obj);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x30: // Master Transmit Data NACK
|
||||
case 0x20: // Master Transmit Address NACK
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
break;
|
||||
|
||||
case 0x20: // Master Transmit Address NACK
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
break;
|
||||
|
||||
case 0x38: // Master Arbitration Lost
|
||||
i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
||||
break;
|
||||
|
||||
case 0x48: // Master Receive Address NACK
|
||||
// Go Master Stop.
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
break;
|
||||
|
||||
case 0x40: // Master Receive Address ACK
|
||||
case 0x50: // Master Receive Data ACK
|
||||
case 0x58: // Master Receive Data NACK
|
||||
|
|
@ -684,8 +680,7 @@ static void i2c_irq(i2c_t *obj)
|
|||
while (1);
|
||||
}
|
||||
#endif
|
||||
// Go Master Repeat Start
|
||||
i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
||||
i2c_fsm_tranfini(obj, 1);
|
||||
}
|
||||
else {
|
||||
uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
|
||||
|
|
@ -852,6 +847,15 @@ static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
|
|||
obj->i2c.slaveaddr_state = NoData;
|
||||
}
|
||||
|
||||
static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked)
|
||||
{
|
||||
if (lastdatanaked) {
|
||||
obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED;
|
||||
}
|
||||
|
||||
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
||||
i2c_disable_int(obj);
|
||||
}
|
||||
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,10 @@
|
|||
"help": "Enable GPIO IRQ debounce",
|
||||
"value": 0
|
||||
},
|
||||
"gpio-irq-debounce-enable-list": {
|
||||
"help": "Comma separated pin list to enable GPIO IRQ debounce",
|
||||
"value": "NC"
|
||||
},
|
||||
"gpio-irq-debounce-clock-source": {
|
||||
"help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
|
||||
"value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
|
||||
|
|
|
|||
|
|
@ -702,7 +702,12 @@ static uint8_t spi_get_data_width(spi_t *obj)
|
|||
{
|
||||
SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
|
||||
|
||||
return ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
|
||||
uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
|
||||
if (data_width == 0) {
|
||||
data_width = 32;
|
||||
}
|
||||
|
||||
return data_width;
|
||||
}
|
||||
|
||||
static int spi_is_tx_complete(spi_t *obj)
|
||||
|
|
|
|||
Loading…
Reference in New Issue