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Update Cypress psoc6pdl asset to 2.0.0.6211

pull/14062/head
Dustin Crossman 2020-12-01 14:59:25 -08:00 committed by Dustin Crossman
parent 5a3af0039f
commit 4ef34ccdb7
1092 changed files with 209100 additions and 17932 deletions
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/LICENSE Normal file → Executable file
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13
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md Normal file → Executable file
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@ -4,7 +4,7 @@
The Cypress PDL simplifies software development for PSoC 6 family of devices.
The PDL integrates device header files, startup code, and
peripheral drivers into a single package. The drivers abstract the hardware functions into a set of
easy-to-use APIs. These are fully documented in the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html).
easy-to-use APIs. These are fully documented in the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html).
This version of the PDL is compatible with ModusToolbox. It is not compatible
with PSoC Creator. The most recent PSoC Creator-compatible version of the PDL
@ -19,20 +19,20 @@ is [available here](https://www.cypress.com/documentation/software-and-drivers/p
The PDL reduces the need to understand register usage and bit structures,
thus easing software development for the extensive set of peripherals in the
PSoC 6 series.
See the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for more detailed information.
See the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html) for more detailed information.
See the [PDL Release Notes](./RELEASE.md) for release-specific information.
### Peripheral Drivers
The PDL provides a high-level API to configure, initialize, and use a peripheral driver.
The drivers are designed for peripheral IP blocks.
See [PDL API Reference](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/modules.html) for the list of drivers.
See [PDL API Reference](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/modules.html) for the list of drivers.
### Quick Start
See the [PDL API Reference Manual Getting Started section](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/page_getting_started.html) for quick start instructions.
See the [PDL API Reference Manual Getting Started section](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/page_getting_started.html) for quick start instructions.
### More information
* [Peripheral Driver Library Release Notes](./RELEASE.md)
* [Peripheral Driver Library API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html)
* [Peripheral Driver Library API Reference Manual](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html)
* [ModusToolbox Software Environment, Quick Start Guide, Documentation, and Videos](https://www.cypress.com/products/modustoolbox-software-environment)
* [ModusToolbox Device Configurator Tool Guide](https://www.cypress.com/ModusToolboxDeviceConfig)
* [AN210781 Getting Started with PSoC 6 MCU with Bluetooth Low Energy (BLE) Connectivity](http://www.cypress.com/an210781)
@ -40,5 +40,8 @@ See the [PDL API Reference Manual Getting Started section](https://cypresssemico
* [PSoC 6 MCU Datasheets](https://www.cypress.com/search/all?f%5b0%5d=meta_type%3Atechnical_documents&f%5b1%5d=resource_meta_type%3A575&f%5b2%5d=field_related_products%3A114026)
* [Cypress Semiconductor](http://www.cypress.com)
### Note
New versions of PDL from 2.0 onwards will now be available in [mtb-pdl-cat1](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html) repo and [psoc6pdl](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) repo will no longer be updated in future.
---
© Cypress Semiconductor Corporation, 2020.

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md Normal file → Executable file
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@ -1,47 +1,101 @@
# PSoC 6 Peripheral Driver Library v1.6.1
# PSoC 6 Peripheral Driver Library v2.0.0
Please refer to the [README.md](./README.md) and the
[PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html)
[PDL API Reference Manual](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html)
for a complete description of the Peripheral Driver Library.
Some restrictions apply to the PSoC 64 devices configuration. Please refer to [PRA (Protected Register Access)](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__pra.html) driver documentation for the details.
Some restrictions apply to the PSoC 64 devices configuration. Please refer to [PRA (Protected Register Access)](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__pra.html) driver documentation for the details.
## New Features
Added support of the PSoC 64 CYB06xx7 devices.
* MISRA-C compliance for the PDL has been upgraded to MISRA-C:2012.
## Updated Personalities
## Personalities with patch version updates
* HvIlo - Changed ILO frequency from 32 kHz to 32.768 kHz, and ILO accuracy from 30% to 10% to reflect the actual values.
* Csd - Fixed the CSD resource display condition on the Peripherals tab of the Device Configurator, to display this resource for all MPNs containing the CSD HW block.
* SysClock - Renamed cy_stc_pra_system_config_t member from altHFfreq to altHFclkFreq.
* SYSANALOG - Added PASSv2 support.
* CTB - Added PASSv2 support
* CSD - Updated Operation Clock Divider default value. Fixed CapSense Configurator launch command parameters.
* CTDAC - Added PASSv2 support.
* PDM PCM - Updated High Pass Filter Gain default value.
* TCPWM - Added support for CY8C61x4 and CY8C62x4 devices.
* SAR - Added PASSv2 support
* SEGLCD - Fixed SegLCD Configurator launch command parameters
* SMARTIO - Fixed Smart I/O Configurator launch command parameters
* UART - Fixed DRC fractional divider value calculation
* POWER - Allow deep sleep latency upto 1000 milliseconds
## Added Drivers
## Updated Drivers
* [SysClk 2.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html)
* [SysPm 5.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html)
* [PRA 2.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__pra.html)
* [SysInt 1.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysint.html)
* [Prot 1.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html)
* [ble_clk 3.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html)
* [Startup 2.90](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html)
* [BLECLK 3.60](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ble__clk.html)
* [CANFD 1.20](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__canfd.html)
* [CRYPTO 2.40](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__crypto.html)
* [CTB 2.0](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ctb.html)
* [DMA 2.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__dma.html)
* [DMAC 1.20](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__dmac.html)
* [FLASH 3.50](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__flash.html)
* [GPIO 1.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__gpio.html)
* [I2S 2.20](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__i2s.html)
* [IPC 1.50](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ipc.html)
* [LPCOMP 1.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__lpcomp.html)
* [LVD 1.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__lvd.html)
* [MCWDT 1.40](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__mcwdt.html)
* [PDMPCM 2.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__pdm__pcm.html)
* [PRA 2.10](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__pra.html)
* [PROFILE 1.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__energy__profiler.html)
* [PROT 1.50](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__prot.html)
* [RTC 2.40](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__rtc.html)
* [SAR 2.0](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sar.html)
* [SCB 2.60](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__scb.html)
* [SDHOST 1.60](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sd__host.html)
* [SEGLCD 1.10](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__seglcd.html)
* [SMIF 2.0](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__smif.html)
* [SYSANALOG 2.0](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysanalog.html)
* [SYSCLK 3.0](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysclk.html)
* [SYSINT 1.50](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysint.html)
* [SYSLIB 2.70](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syslib.html)
* [SYSPM 5.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syspm.html)
* [SYSTICK 1.30](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__arm__system__timer.html)
* [TCPWM 1.20](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__tcpwm.html)
### Drivers with patch version updates
Minor documentation changes:
* [CSD 1.10.2](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__csd.html)
* [CTDAC 2.0.2](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ctdac.html)
* [EFUSE 1.10.4](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__efuse.html)
* [SMARTIO 1.0.2](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__smartio.html)
* [TRIGMUX 1.20.3](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__trigmux.html)
* [USBFS 2.20.2](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html)
* [WDT 1.30.1](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__wdt.html)
* IPC 1.40.2
* SysLib 2.60.1
* Crypto 2.30.4
### Obsoleted part numbers
The ModusToolbox Device Configurator can not create the designs targeting the obsolete PSoC 6 part numbers.
Below is a list of PSoC 6 part numbers obsoleted in psoc6pdl release-v1.6.0, with the suggested next best alternative:
| Obsoleted part number | Next best alternative |
| :--- | :---- |
| CY8C624AAZI-D44 | CY8C624AAZI-S2D44 |
| CY8C624AFNI-D43 | CY8C624AFNI-S2D43 |
| CY8C624ABZI-D04 | CY8C624ABZI-S2D04 |
| CY8C624ABZI-D14 | CY8C624ABZI-S2D14 |
| CY8C624AAZI-D14 | CY8C624AAZI-S2D14 |
| CY8C6248AZI-D14 | CY8C6248AZI-S2D14 |
| CY8C6248BZI-D44 | CY8C6248BZI-S2D44 |
| CY8C6248AZI-D44 | CY8C6248AZI-S2D44 |
| CY8C6248FNI-D43 | CY8C6248FNI-S2D43 |
| CY8C624ALQI-D42 | N/A |
## Known Issues
## Defect Fixes
See the Changelog section of each Driver in the [PDL API Reference](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/modules.html) for all fixes and updates.
A non-blocking flash write initiated by the Cortex-M4 application failed to complete because the Cortex-M0+ CPU is in deep sleep mode. The issue is fixed in the PSoC 6 Cortex M0+ prebuilt image (psoc6cm0p). Update existing applications to use this new image. Please refer to the Changelog section of the SysPm driver for more details.
See the Changelog section of each Driver in the [PDL API Reference](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/modules.html) for all fixes and updates.
## Supported Software and Tools
@ -49,10 +103,10 @@ This version of PDL was validated for compatibility with the following Software
| Software and Tools | Version |
| :--- | :---- |
| [Cypress Core Library](https://github.com/cypresssemiconductorco/core-lib) | 1.1.2 |
| [Cypress HAL](https://github.com/cypresssemiconductorco/psoc6hal) | 1.2.0 |
| CMSIS-Core(M) | 5.2.1 |
| GCC Compiler | 9.2.1 |
| [Cypress Core Library](https://github.com/cypresssemiconductorco/core-lib) | 1.1.4 |
| [Cypress HAL](https://github.com/cypresssemiconductorco/psoc6hal) | 1.4.0 |
| CMSIS-Core(M) | 5.4.0 |
| GCC Compiler | 9.3.1 |
| IAR Compiler | 8.42.2 |
| ARM Compiler 6 | 6.13 |
| FreeRTOS | 10.0.1 |
@ -60,7 +114,7 @@ This version of PDL was validated for compatibility with the following Software
## More information
* [Peripheral Driver Library README.md](./README.md)
* [Peripheral Driver Library API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html)
* [Peripheral Driver Library API Reference Manual](https://cypresssemiconductorco.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html)
* [ModusToolbox Software Environment, Quick Start Guide, Documentation, and Videos](https://www.cypress.com/products/modustoolbox-software-environment)
* [ModusToolbox Device Configurator Tool Guide](https://www.cypress.com/ModusToolboxDeviceConfig)
* [AN210781 Getting Started with PSoC 6 MCU with Bluetooth Low Energy (BLE) Connectivity](http://www.cypress.com/an210781)

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c4588azi_h675.h Normal file → Executable file
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@ -5,7 +5,7 @@
* CY8C4588AZI-H675 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C4588AZI-H675 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +504,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c4588azi_h676.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C4588AZI-H676 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C4588AZI-H676 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +504,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_80_tqfp.h"

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c4588azi_h685.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C4588AZI-H685 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C4588AZI-H685 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +504,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c4588azi_h686.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C4588AZI-H686 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C4588AZI-H686 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +504,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_80_tqfp.h"

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6016bzi_f04.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6036bzi_f04.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6116bzi_f54.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6117bzi_f34.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6117fdi_f02.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6117wi_f34.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6136bzi_f14.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6136bzi_f34.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6136fdi_f42.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6136fti_f42.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6137bzi_f14.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6137bzi_f34.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6137bzi_f54.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6137fdi_f02.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6137wi_f54.h Normal file → Executable file
View File

16
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144azi_s4f12.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144AZI-S4F12 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -268,6 +268,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -289,6 +298,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

16
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144azi_s4f62.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144AZI-S4F62 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -268,6 +268,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -289,6 +298,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

19
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f82.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144azi_s4f82.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144AZI-S4F82 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -271,6 +271,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -292,6 +304,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

19
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f83.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144azi_s4f83.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144AZI-S4F83 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -271,6 +271,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -292,6 +304,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_80_tqfp.h"

19
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f92.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144azi_s4f92.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144AZI-S4F92 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -271,6 +271,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -292,6 +304,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

19
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f93.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144azi_s4f93.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144AZI-S4F93 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -271,6 +271,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -292,6 +304,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_80_tqfp.h"

16
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144lqi_s4f12.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144LQI-S4F12 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -268,6 +268,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -289,6 +298,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

16
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144lqi_s4f62.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144LQI-S4F62 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -268,6 +268,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -289,6 +298,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

19
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f82.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144lqi_s4f82.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144LQI-S4F82 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -271,6 +271,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -292,6 +304,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

19
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f92.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6144lqi_s4f92.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6144LQI-S4F92 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -93,7 +93,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -271,6 +271,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -292,6 +304,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f02.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145azi_s3f02.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145azi_s3f12.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f42.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145azi_s3f42.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145azi_s3f62.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f72.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145azi_s3f72.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f11.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145fni_s3f11.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f41.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145fni_s3f41.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f71.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145fni_s3f71.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f02.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145lqi_s3f02.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145lqi_s3f12.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f42.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145lqi_s3f42.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145lqi_s3f62.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f72.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6145lqi_s3f72.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148azi_s2f44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6148azi_s2f44.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148bzi_s2f44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6148bzi_s2f44.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148fni_s2f43.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6148fni_s2f43.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f04.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c614aazi_s2f04.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f14.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c614aazi_s2f14.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c614aazi_s2f44.h Normal file → Executable file
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f04.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c614abzi_s2f04.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c614abzi_s2f44.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f03.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c614afni_s2f03.h Normal file → Executable file
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f43.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c614afni_s2f43.h Normal file → Executable file
View File

24
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244azi_s4d12.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244AZI-S4D12 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244AZI-S4D12 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +501,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

24
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244azi_s4d62.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244AZI-S4D62 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244AZI-S4D62 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +501,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244azi_s4d82.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244AZI-S4D82 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244AZI-S4D82 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -474,6 +474,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -495,6 +507,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244azi_s4d83.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244AZI-S4D83 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244AZI-S4D83 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -474,6 +474,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -495,6 +507,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_80_tqfp.h"

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244azi_s4d92.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244AZI-S4D92 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244AZI-S4D92 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -474,6 +474,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -495,6 +507,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_64_tqfp.h"

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244azi_s4d93.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244AZI-S4D93 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244AZI-S4D93 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -474,6 +474,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -495,6 +507,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#include "psoc6_04_config.h"
#include "gpio_psoc6_04_80_tqfp.h"

24
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244lqi_s4d12.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244LQI-S4D12 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244LQI-S4D12 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +501,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

24
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244lqi_s4d62.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244LQI-S4D62 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244LQI-S4D62 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -471,6 +471,15 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -492,6 +501,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244lqi_s4d82.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244LQI-S4D82 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244LQI-S4D82 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -474,6 +474,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -495,6 +507,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

27
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6244lqi_s4d92.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6244LQI-S4D92 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.275
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -124,7 +124,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -233,7 +233,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6244LQI-S4D92 interrupts that can be routed to the CM0+ NVIC */
@ -276,7 +276,7 @@ typedef enum {
cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */
pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */
pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_ctbs_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */
pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */
pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */
scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */
@ -389,7 +389,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
@ -474,6 +474,18 @@ typedef enum {
#define CY_IP_MXLPCOMP 1u
#define CY_IP_MXLPCOMP_INSTANCES 1u
#define CY_IP_MXLPCOMP_VERSION 1u
#define CY_IP_MXS40PASS 1u
#define CY_IP_MXS40PASS_INSTANCES 1u
#define CY_IP_MXS40PASS_VERSION 2u
#define CY_IP_MXS40PASS_SAR 1u
#define CY_IP_MXS40PASS_SAR_INSTANCES 2u
#define CY_IP_MXS40PASS_SAR_VERSION 2u
#define CY_IP_MXS40PASS_CTDAC 1u
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
#define CY_IP_MXS40PASS_CTDAC_VERSION 2u
#define CY_IP_MXS40PASS_CTB 1u
#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
#define CY_IP_MXS40PASS_CTB_VERSION 2u
#define CY_IP_MXPERI 1u
#define CY_IP_MXPERI_INSTANCES 1u
#define CY_IP_MXPERI_VERSION 2u
@ -495,6 +507,9 @@ typedef enum {
#define CY_IP_MXS40SRSS_MCWDT 1u
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
#define CY_IP_MXTCPWM 1u
#define CY_IP_MXTCPWM_INSTANCES 1u
#define CY_IP_MXTCPWM_VERSION 2u
#define CY_IP_MXUSBFS 1u
#define CY_IP_MXUSBFS_INSTANCES 1u
#define CY_IP_MXUSBFS_VERSION 1u

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245azi_s3d02.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245AZI-S3D02 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245AZI-S3D02 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245azi_s3d12.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245AZI-S3D12 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245AZI-S3D12 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245azi_s3d42.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245AZI-S3D42 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245AZI-S3D42 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245azi_s3d62.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245AZI-S3D62 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245AZI-S3D62 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245azi_s3d72.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245AZI-S3D72 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245AZI-S3D72 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245fni_s3d11.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245FNI-S3D11 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245FNI-S3D11 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245fni_s3d41.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245FNI-S3D41 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245FNI-S3D41 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245fni_s3d71.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245FNI-S3D71 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245FNI-S3D71 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245lqi_s3d02.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245LQI-S3D02 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245LQI-S3D02 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245lqi_s3d12.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245LQI-S3D12 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245LQI-S3D12 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245lqi_s3d42.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245LQI-S3D42 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245LQI-S3D42 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245lqi_s3d62.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245LQI-S3D62 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245LQI-S3D62 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6245lqi_s3d72.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6245LQI-S3D72 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -230,7 +230,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6245LQI-S3D72 interrupts that can be routed to the CM0+ NVIC */
@ -383,7 +383,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6246bzi_d04.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6246BZI-D04 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6246BZI-D04 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247bfi_d54.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247BFI-D54 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247BFI-D54 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247bzi_aud54.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247BZI-AUD54 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247BZI-AUD54 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247bzi_d34.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247BZI-D34 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247BZI-D34 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247bzi_d44.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247BZI-D44 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247BZI-D44 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247bzi_d54.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247BZI-D54 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247BZI-D54 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247fdi_d02.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247FDI-D02 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247FDI-D02 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247fdi_d32.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247FDI-D32 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247FDI-D32 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247fdi_d52.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247FDI-D52 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247FDI-D52 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247fti_d52.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247FTI-D52 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247FTI-D52 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6247wi_d54.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6247WI-D54 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -255,7 +255,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6247WI-D54 interrupts that can be routed to the CM0+ NVIC */
@ -418,7 +418,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248azi_d14.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248AZI-D14 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248AZI-D14 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248azi_d44.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248AZI-D44 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248AZI-D44 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248azi_s2d14.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248AZI-S2D14 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248AZI-S2D14 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248azi_s2d44.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248AZI-S2D44 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248AZI-S2D44 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248bzi_d44.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248BZI-D44 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248BZI-D44 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248bzi_s2d44.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248BZI-S2D44 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248BZI-S2D44 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248fni_d43.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248FNI-D43 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248FNI-D43 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c6248fni_s2d43.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C6248FNI-S2D43 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C6248FNI-S2D43 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c624aazi_d14.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C624AAZI-D14 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C624AAZI-D14 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c624aazi_d44.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C624AAZI-D44 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C624AAZI-D44 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h → targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/COMPONENT_CAT1A/include/cy8c624aazi_s2d14.h Normal file → Executable file
View File

@ -5,7 +5,7 @@
* CY8C624AAZI-S2D14 device header
*
* \note
* Generator version: 1.6.0.225
* Generator version: 1.6.0.237
*
********************************************************************************
* \copyright
@ -45,7 +45,7 @@
typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
@ -261,7 +261,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* CY8C624AAZI-S2D14 interrupts that can be routed to the CM0+ NVIC */
@ -445,7 +445,7 @@ typedef enum {
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */

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