mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_F103RB] Update mapping file.
Solve compilation error with flash.pull/161/head
bcostm
parent
a3d0a9bd96
commit
4ee89986b7
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f10x.h
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* @author MCD Application Team
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* @version V3.5.0
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* @date 11-March-2011
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* @version V3.6.2
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* @date 28-February-2013
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F10x Connectivity line,
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@ -67,7 +67,7 @@
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#ifdef __cplusplus
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extern "C" {
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#endif
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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@ -79,11 +79,11 @@
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
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/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
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/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
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#define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */
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/* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
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/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
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#define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */
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/* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
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/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
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/* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
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/* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
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/* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
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/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
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#endif
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@ -111,14 +111,14 @@
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#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
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#endif
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#if !defined USE_STDPERIPH_DRIVER
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#if !defined (USE_STDPERIPH_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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#define USE_STDPERIPH_DRIVER
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#endif
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#endif /* USE_STDPERIPH_DRIVER */
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/**
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* @brief In the following line adjust the value of External High Speed oscillator (HSE)
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@ -135,23 +135,26 @@
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#endif /* STM32F10X_CL */
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#endif /* HSE_VALUE */
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/**
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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Timeout value
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*/
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#if !defined (HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#endif /* HSE_STARTUP_TIMEOUT */
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#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @brief STM32F10x Standard Peripheral Library version number
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*/
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
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#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
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|(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
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|(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
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|(__STM32F10X_STDPERIPH_VERSION_RC))
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@ -168,12 +171,13 @@
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* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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#ifdef STM32F10X_XL
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#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
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#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
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#else
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#define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
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#define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
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#endif /* STM32F10X_XL */
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @brief STM32F10x Interrupt Number Definition, according to the selected device
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@ -231,7 +235,7 @@ typedef enum IRQn
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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#endif /* STM32F10X_LD */
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#ifdef STM32F10X_LD_VL
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@ -252,7 +256,7 @@ typedef enum IRQn
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
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TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
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TIM7_IRQn = 55 /*!< TIM7 Interrupt */
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TIM7_IRQn = 55 /*!< TIM7 Interrupt */
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#endif /* STM32F10X_LD_VL */
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#ifdef STM32F10X_MD
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@ -280,7 +284,7 @@ typedef enum IRQn
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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#endif /* STM32F10X_MD */
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#ifdef STM32F10X_MD_VL
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@ -306,7 +310,7 @@ typedef enum IRQn
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
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TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
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TIM7_IRQn = 55 /*!< TIM7 Interrupt */
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TIM7_IRQn = 55 /*!< TIM7 Interrupt */
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#endif /* STM32F10X_MD_VL */
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#ifdef STM32F10X_HD
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@ -382,16 +386,16 @@ typedef enum IRQn
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TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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UART4_IRQn = 52, /*!< UART4 global Interrupt */
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UART5_IRQn = 53, /*!< UART5 global Interrupt */
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UART5_IRQn = 53, /*!< UART5 global Interrupt */
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TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
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TIM7_IRQn = 55, /*!< TIM7 Interrupt */
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TIM7_IRQn = 55, /*!< TIM7 Interrupt */
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DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
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DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
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DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
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DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
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DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
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mapped at position 60 only if the MISC_REMAP bit in
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the AFIO_MAPR2 register is set) */
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the AFIO_MAPR2 register is set) */
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#endif /* STM32F10X_HD_VL */
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#ifdef STM32F10X_XL
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@ -483,7 +487,7 @@ typedef enum IRQn
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CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
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CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
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OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
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#endif /* STM32F10X_CL */
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#endif /* STM32F10X_CL */
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} IRQn_Type;
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/**
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@ -2036,7 +2040,7 @@ typedef struct
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#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
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#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
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#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
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#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
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#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
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#endif
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@ -3628,7 +3632,7 @@ typedef struct
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#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
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#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
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#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */
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#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */
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#endif
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/***************** Bit definition for DAC_SWTRIGR register ******************/
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#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
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#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
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#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
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#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
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#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
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#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
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#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
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#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
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#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
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#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
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#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
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#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
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#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
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#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
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#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
||||
|
|
@ -7803,7 +7844,7 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/******************* Bit definition for FLASH_ACR register ******************/
|
||||
#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
|
||||
#define FLASH_ACR_LATENCY ((uint8_t)0x07) /*!< LATENCY[2:0] bits (Latency) */
|
||||
#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */
|
||||
#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */
|
||||
#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */
|
||||
|
|
@ -7815,6 +7856,11 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_KEYR register ******************/
|
||||
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
|
||||
|
||||
/****************** FLASH Keys **********************************************/
|
||||
#define RDP_Key ((uint16_t)0x00A5)
|
||||
#define FLASH_KEY1 ((uint32_t)0x45670123)
|
||||
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
|
||||
|
||||
/***************** Bit definition for FLASH_OPTKEYR register ****************/
|
||||
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
|
||||
|
||||
|
|
@ -8336,7 +8382,7 @@ typedef struct
|
|||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F10x_H */
|
||||
|
||||
|
|
@ -8348,4 +8394,4 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
Loading…
Reference in New Issue