mirror of https://github.com/ARMmbed/mbed-os.git
commit
4dcefa604a
|
@ -43,7 +43,6 @@ void set_compare(uint16_t count);
|
||||||
extern volatile uint32_t SlaveCounter;
|
extern volatile uint32_t SlaveCounter;
|
||||||
extern volatile uint32_t oc_int_part;
|
extern volatile uint32_t oc_int_part;
|
||||||
extern volatile uint16_t oc_rem_part;
|
extern volatile uint16_t oc_rem_part;
|
||||||
extern volatile uint16_t cnt_val;
|
|
||||||
|
|
||||||
// Used to increment the slave counter
|
// Used to increment the slave counter
|
||||||
void timer_update_irq_handler(void)
|
void timer_update_irq_handler(void)
|
||||||
|
@ -60,7 +59,7 @@ void timer_update_irq_handler(void)
|
||||||
// Used for mbed timeout (channel 1) and HAL tick (channel 2)
|
// Used for mbed timeout (channel 1) and HAL tick (channel 2)
|
||||||
void timer_oc_irq_handler(void)
|
void timer_oc_irq_handler(void)
|
||||||
{
|
{
|
||||||
cnt_val = TIM_MST->CNT;
|
uint16_t cval = TIM_MST->CNT;
|
||||||
TimMasterHandle.Instance = TIM_MST;
|
TimMasterHandle.Instance = TIM_MST;
|
||||||
|
|
||||||
// Channel 1 for mbed timeout
|
// Channel 1 for mbed timeout
|
||||||
|
@ -72,7 +71,7 @@ void timer_oc_irq_handler(void)
|
||||||
} else {
|
} else {
|
||||||
if (oc_int_part > 0) {
|
if (oc_int_part > 0) {
|
||||||
set_compare(0xFFFF);
|
set_compare(0xFFFF);
|
||||||
oc_rem_part = cnt_val; // To finish the counter loop the next time
|
oc_rem_part = cval; // To finish the counter loop the next time
|
||||||
oc_int_part--;
|
oc_int_part--;
|
||||||
} else {
|
} else {
|
||||||
us_ticker_irq_handler();
|
us_ticker_irq_handler();
|
||||||
|
@ -129,8 +128,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
|
||||||
// Output compare channel 2 interrupt for HAL tick
|
// Output compare channel 2 interrupt for HAL tick
|
||||||
NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
|
NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
|
||||||
NVIC_EnableIRQ(TIM_MST_UP_IRQ);
|
NVIC_EnableIRQ(TIM_MST_UP_IRQ);
|
||||||
|
NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
|
||||||
NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
|
NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
|
||||||
NVIC_EnableIRQ(TIM_MST_OC_IRQ);
|
NVIC_EnableIRQ(TIM_MST_OC_IRQ);
|
||||||
|
NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
|
||||||
|
|
||||||
// Enable interrupts
|
// Enable interrupts
|
||||||
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
|
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
|
||||||
|
|
|
@ -43,7 +43,6 @@ void set_compare(uint16_t count);
|
||||||
extern volatile uint32_t SlaveCounter;
|
extern volatile uint32_t SlaveCounter;
|
||||||
extern volatile uint32_t oc_int_part;
|
extern volatile uint32_t oc_int_part;
|
||||||
extern volatile uint16_t oc_rem_part;
|
extern volatile uint16_t oc_rem_part;
|
||||||
extern volatile uint16_t cnt_val;
|
|
||||||
|
|
||||||
// Used to increment the slave counter
|
// Used to increment the slave counter
|
||||||
void timer_update_irq_handler(void)
|
void timer_update_irq_handler(void)
|
||||||
|
@ -60,7 +59,7 @@ void timer_update_irq_handler(void)
|
||||||
// Used for mbed timeout (channel 1) and HAL tick (channel 2)
|
// Used for mbed timeout (channel 1) and HAL tick (channel 2)
|
||||||
void timer_oc_irq_handler(void)
|
void timer_oc_irq_handler(void)
|
||||||
{
|
{
|
||||||
cnt_val = TIM_MST->CNT;
|
uint16_t cval = TIM_MST->CNT;
|
||||||
TimMasterHandle.Instance = TIM_MST;
|
TimMasterHandle.Instance = TIM_MST;
|
||||||
|
|
||||||
// Channel 1 for mbed timeout
|
// Channel 1 for mbed timeout
|
||||||
|
@ -72,7 +71,7 @@ void timer_oc_irq_handler(void)
|
||||||
} else {
|
} else {
|
||||||
if (oc_int_part > 0) {
|
if (oc_int_part > 0) {
|
||||||
set_compare(0xFFFF);
|
set_compare(0xFFFF);
|
||||||
oc_rem_part = cnt_val; // To finish the counter loop the next time
|
oc_rem_part = cval; // To finish the counter loop the next time
|
||||||
oc_int_part--;
|
oc_int_part--;
|
||||||
} else {
|
} else {
|
||||||
us_ticker_irq_handler();
|
us_ticker_irq_handler();
|
||||||
|
@ -131,8 +130,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
|
||||||
// Output compare channel 2 interrupt for HAL tick
|
// Output compare channel 2 interrupt for HAL tick
|
||||||
NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
|
NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
|
||||||
NVIC_EnableIRQ(TIM_MST_UP_IRQ);
|
NVIC_EnableIRQ(TIM_MST_UP_IRQ);
|
||||||
|
NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
|
||||||
NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
|
NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
|
||||||
NVIC_EnableIRQ(TIM_MST_OC_IRQ);
|
NVIC_EnableIRQ(TIM_MST_OC_IRQ);
|
||||||
|
NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
|
||||||
|
|
||||||
// Enable interrupts
|
// Enable interrupts
|
||||||
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
|
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
|
||||||
|
|
|
@ -41,7 +41,6 @@ static int us_ticker_inited = 0;
|
||||||
volatile uint32_t SlaveCounter = 0;
|
volatile uint32_t SlaveCounter = 0;
|
||||||
volatile uint32_t oc_int_part = 0;
|
volatile uint32_t oc_int_part = 0;
|
||||||
volatile uint16_t oc_rem_part = 0;
|
volatile uint16_t oc_rem_part = 0;
|
||||||
volatile uint16_t cnt_val = 0;
|
|
||||||
|
|
||||||
void set_compare(uint16_t count) {
|
void set_compare(uint16_t count) {
|
||||||
TimMasterHandle.Instance = TIM_MST;
|
TimMasterHandle.Instance = TIM_MST;
|
||||||
|
@ -59,15 +58,24 @@ void us_ticker_init(void) {
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t us_ticker_read() {
|
uint32_t us_ticker_read() {
|
||||||
uint32_t counter;
|
uint32_t counter, counter2;
|
||||||
if (!us_ticker_inited) us_ticker_init();
|
if (!us_ticker_inited) us_ticker_init();
|
||||||
|
// A situation might appear when Master overflows right after Slave is read and before the
|
||||||
//Current value of TIM_MST->CNT is stored in cnt_val and is
|
// new (overflowed) value of Master is read. Which would make the code below consider the
|
||||||
//updated in interrupt context
|
// previous (incorrect) value of Slave and the new value of Master, which would return a
|
||||||
|
// value in the past. Avoid this by computing consecutive values of the timer until they
|
||||||
|
// are properly ordered.
|
||||||
counter = (uint32_t)(SlaveCounter << 16);
|
counter = (uint32_t)(SlaveCounter << 16);
|
||||||
counter += cnt_val;
|
counter += TIM_MST->CNT;
|
||||||
|
while (1) {
|
||||||
return counter;
|
counter2 = (uint32_t)(SlaveCounter << 16);
|
||||||
|
counter2 += TIM_MST->CNT;
|
||||||
|
if (counter2 > counter) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
counter = counter2;
|
||||||
|
}
|
||||||
|
return counter2;
|
||||||
}
|
}
|
||||||
|
|
||||||
void us_ticker_set_interrupt(timestamp_t timestamp) {
|
void us_ticker_set_interrupt(timestamp_t timestamp) {
|
||||||
|
|
Loading…
Reference in New Issue