Merge pull request #11367 from kyle-cypress/pr/cypress-5.14-rollup

Cypress 5.14 rollup

TESTS/mbed_hal/qspi/flash_configs/S25FL128S_config.h

@@ -0,0 +1,191 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_FLASH_S25FL128S_H
+#define MBED_QSPI_FLASH_S25FL128S_H
+
+#define QSPI_FLASH_CHIP_STRING "Cypress S25FL128S"
+#define QSPI_FLASH_CYPRESS_S25FL128S
+
+// Command for reading configuration register
+#define QSPI_CMD_RDCR0                         0x35  // To read Quad (QE) enable bit
+// Command for writing status/configuration register
+#define QSPI_CMD_WRSR                          0x01 // To write Qual (QE) enable bit
+// Command for reading status register
+#define QSPI_CMD_RDSR                          0x05 // To read WIP bit of status register 1
+
+
+
+// Command for reading security register
+#define QSPI_CMD_RDSCUR                         0x2B
+
+// Command for setting Reset Enable
+#define QSPI_CMD_RSTEN                          0x66
+// Command for setting Reset
+#define QSPI_CMD_RST                            0xF0 //0x99
+
+// Command for setting write enable
+#define QSPI_CMD_WREN                           0x06
+// Command for setting write disable
+#define QSPI_CMD_WRDI                           0x04
+
+// WRSR operations max time [us] (datasheet max time + 15%)
+#define QSPI_WRSR_MAX_TIME                      575000   // 575 ms
+// general wait max time [us]
+#define QSPI_WAIT_MAX_TIME                      100000  // 100 ms
+
+
+// Commands for writing (page programming)
+#define QSPI_CMD_WRITE_1IO                      0x02    // 1-1-1 mode
+#define QSPI_CMD_WRITE_1I4O                     0x32    // 1-1-4 mode // 1-4-4 is not supported by S25FL512S
+
+// write operations max time [us] (datasheet max time + 15%)
+#define QSPI_PAGE_PROG_MAX_TIME                 800   // 800 us
+
+#define QSPI_PAGE_SIZE                          512     // 512B
+#define QSPI_SECTOR_SIZE                        262144  // 256kB
+#define QSPI_SECTOR_COUNT                       64      // 16 MB
+
+// Commands for reading
+#define QSPI_CMD_READ_1IO_FAST                  0x0B   // 1-1-1 mode
+#define QSPI_CMD_READ_1IO                       0x03   // 1-1-1 mode
+#define QSPI_CMD_READ_2IO                       0xBB   // 1-2-2 mode    - dual I/O
+#define QSPI_CMD_READ_1I2O                      0x3B   // 1-1-2 mode    - dual output
+#define QSPI_CMD_READ_4IO                       0xEB   // 1-4-4 mode    - quad I/O
+#define QSPI_CMD_READ_1I4O                      0x6B   // 1-1-4 mode    - quad output
+
+// Alt (mode) value for quad I/O read
+#define QSPI_ALT_READ_4IO                       0x01 // 1-4-4 mode only
+
+#define QSPI_READ_1IO_DUMMY_CYCLE               0
+#define QSPI_READ_FAST_DUMMY_CYCLE              8
+#define QSPI_READ_2IO_DUMMY_CYCLE               4 // dual I/O
+#define QSPI_READ_1I2O_DUMMY_CYCLE              8 // dual output
+#define QSPI_READ_4IO_DUMMY_CYCLE               6 // quad I/O - 2 cycles for Mode or Alt (4 bits per cycle x 2 cycles = 1 byte) + 4 dummy cycles
+#define QSPI_READ_1I4O_DUMMY_CYCLE              8 // quad output
+
+// Commands for erasing
+#define QSPI_CMD_ERASE_SECTOR                   0xD8    // 256kB
+#define QSPI_CMD_ERASE_CHIP                     0x60    // or 0xC7
+
+// erase operations max time [us] (datasheet max time + 15%)
+#define QSPI_ERASE_SECTOR_MAX_TIME              750000      // 1.15*650 ~ 750 ms
+
+// max frequency for basic rw operation (for fast mode)
+#define QSPI_COMMON_MAX_FREQUENCY               50000000
+
+#define QSPI_STATUS_REG_SIZE                    1
+#define QSPI_CONFIG_REG_0_SIZE                  1
+#define QSPI_SECURITY_REG_SIZE                  1
+#define QSPI_MAX_REG_SIZE                       2
+
+// status register
+#define STATUS_BIT_WIP   (1 << 0)   // write in progress bit
+#define STATUS_BIT_WEL   (1 << 1)   // write enable latch
+#define STATUS_BIT_BP0   (1 << 2)   //
+#define STATUS_BIT_BP1   (1 << 3)   //
+#define STATUS_BIT_BP2   (1 << 4)   //
+#define STATUS_BIT_BP3   (1 << 5)   //
+#define STATUS_BIT_QE    (1 << 1)   // Quad Enable
+#define STATUS_BIT_SRWD  (1 << 7)   // status register write protect
+
+// configuration register 0
+// bit 0, 1, 2, 4, 5, 7 reserved
+#define CONFIG0_BIT_TB   (1 << 3)   // Top/Bottom area protect
+#define CONFIG0_BIT_DC   (1 << 6)   // Dummy Cycle
+
+// configuration register 1
+// bit 0, 2, 3, 4, 5, 6, 7 reserved
+#define CONFIG1_BIT_LH   (1 << 1)   // 0 = Ultra Low power mode, 1 = High performance mode
+
+
+
+#define EXTENDED_SPI_ENABLE()                                               \
+                                                                            \
+    const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
+    uint8_t reg_data[reg_size] = { 0 };                                     \
+                                                                            \
+    if (read_register(STATUS_REG, reg_data,                                 \
+            QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+    if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE,         \
+            QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) {              \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    if (write_enable(qspi) != QSPI_STATUS_OK) {                             \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    reg_data[1] |= STATUS_BIT_QE;                                            \
+    if (write_register(QSPI_CMD_WRSR, reg_data,                             \
+            reg_size, qspi) != QSPI_STATUS_OK) {                            \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    WAIT_FOR(WRSR_MAX_TIME, qspi);                                          \
+                                                                            \
+    memset(reg_data, 0, QSPI_STATUS_REG_SIZE);                              \
+    if (read_register(CONFIG_REG0, reg_data,                                 \
+            QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    return ((reg_data[0] & STATUS_BIT_QE) != 0 ?                            \
+            QSPI_STATUS_OK : QSPI_STATUS_ERROR)
+
+
+
+#define EXTENDED_SPI_DISABLE()                                              \
+                                                                            \
+    const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
+    uint8_t reg_data[reg_size] = { 0 };                                     \
+                                                                            \
+    if (read_register(STATUS_REG, reg_data,                                 \
+            QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE,         \
+            QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) {              \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    if (write_enable(qspi) != QSPI_STATUS_OK) {                             \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    reg_data[1] &= ~(STATUS_BIT_QE);                                        \
+                                                                            \
+    if (write_register(QSPI_CMD_WRSR, reg_data,                             \
+            reg_size, qspi) != QSPI_STATUS_OK) {                            \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    WAIT_FOR(WRSR_MAX_TIME, qspi);                                          \
+                                                                            \
+    reg_data[0] = 0;                                                        \
+    if (read_register(CONFIG_REG0, reg_data,                                \
+        QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                    \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    return ((reg_data[0] & STATUS_BIT_QE) == 0 ?                            \
+            QSPI_STATUS_OK : QSPI_STATUS_ERROR)
+
+
+#endif // MBED_QSPI_FLASH_S25FL128S_H

TESTS/mbed_hal/qspi/flash_configs/S25FS512S_config.h

@@ -0,0 +1,191 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_FLASH_S25FS512S_H
+#define MBED_QSPI_FLASH_S25FS512S_H
+
+#define QSPI_FLASH_CHIP_STRING "Cypress S25FS512S"
+#define QSPI_FLASH_CYPRESS_S25FS512S
+
+// Command for reading configuration register
+#define QSPI_CMD_RDCR0                         0x35  // To read Quad (QE) enable bit
+// Command for writing status/configuration register
+#define QSPI_CMD_WRSR                          0x01 // To write Qual (QE) enable bit
+// Command for reading status register
+#define QSPI_CMD_RDSR                          0x05 // To read WIP bit of status register 1
+
+
+
+// Command for reading security register
+#define QSPI_CMD_RDSCUR                         0x2B
+
+// Command for setting Reset Enable
+#define QSPI_CMD_RSTEN                          0x66
+// Command for setting Reset
+#define QSPI_CMD_RST                            0xF0 //0x99
+
+// Command for setting write enable
+#define QSPI_CMD_WREN                           0x06
+// Command for setting write disable
+#define QSPI_CMD_WRDI                           0x04
+
+// WRSR operations max time [us] (datasheet max time + 15%)
+#define QSPI_WRSR_MAX_TIME                      2300000   // 2.3 seconds
+// general wait max time [us]
+#define QSPI_WAIT_MAX_TIME                      100000  // 100ms
+
+
+// Commands for writing (page programming)
+#define QSPI_CMD_WRITE_1IO                      0x02    // 1-1-1 mode
+#define QSPI_CMD_WRITE_1I4O                     0x32    // 1-1-4 mode // 1-4-4 is not supported by S25FS512S
+
+// write operations max time [us] (datasheet max time + 15%)
+#define QSPI_PAGE_PROG_MAX_TIME                 2300   // 2.3ms
+
+#define QSPI_PAGE_SIZE                          256     // 256B
+#define QSPI_SECTOR_SIZE                        262144  // 256kB
+#define QSPI_SECTOR_COUNT                       256     // 64 MB
+
+// Commands for reading
+#define QSPI_CMD_READ_1IO_FAST                  0x0B   // 1-1-1 mode
+#define QSPI_CMD_READ_1IO                       0x03   // 1-1-1 mode
+#define QSPI_CMD_READ_2IO                       0xBB   // 1-2-2 mode    - dual I/O
+#define QSPI_CMD_READ_1I2O                      0x3B   // 1-1-2 mode    - dual output
+#define QSPI_CMD_READ_4IO                       0xEB   // 1-4-4 mode    - quad I/O
+#define QSPI_CMD_READ_1I4O                      0x6B   // 1-1-4 mode    - quad output
+
+// Alt (mode) value for quad I/O read
+#define QSPI_ALT_READ_4IO                       0x01 // 1-4-4 mode only
+
+#define QSPI_READ_1IO_DUMMY_CYCLE               0
+#define QSPI_READ_FAST_DUMMY_CYCLE              8
+#define QSPI_READ_2IO_DUMMY_CYCLE               4 // dual I/O
+#define QSPI_READ_1I2O_DUMMY_CYCLE              8 // dual output
+#define QSPI_READ_4IO_DUMMY_CYCLE               6 // quad I/O - 2 cycles for Mode or Alt (4 bits per cycle x 2 cycles = 1 byte) + 4 dummy cycles
+#define QSPI_READ_1I4O_DUMMY_CYCLE              8 // quad output
+
+// Commands for erasing
+#define QSPI_CMD_ERASE_SECTOR                   0xD8    // 256kB
+#define QSPI_CMD_ERASE_CHIP                     0x60    // or 0xC7
+
+// erase operations max time [us] (datasheet max time + 15%)
+#define QSPI_ERASE_SECTOR_MAX_TIME              850000      // 1.15*725 ~ 850 ms
+
+// max frequency for basic rw operation (for fast mode)
+#define QSPI_COMMON_MAX_FREQUENCY               50000000
+
+#define QSPI_STATUS_REG_SIZE                    1
+#define QSPI_CONFIG_REG_0_SIZE                  1
+#define QSPI_SECURITY_REG_SIZE                  1
+#define QSPI_MAX_REG_SIZE                       2
+
+// status register
+#define STATUS_BIT_WIP   (1 << 0)   // write in progress bit
+#define STATUS_BIT_WEL   (1 << 1)   // write enable latch
+#define STATUS_BIT_BP0   (1 << 2)   //
+#define STATUS_BIT_BP1   (1 << 3)   //
+#define STATUS_BIT_BP2   (1 << 4)   //
+#define STATUS_BIT_BP3   (1 << 5)   //
+#define STATUS_BIT_QE    (1 << 1)   // Quad Enable
+#define STATUS_BIT_SRWD  (1 << 7)   // status register write protect
+
+// configuration register 0
+// bit 0, 1, 2, 4, 5, 7 reserved
+#define CONFIG0_BIT_TB   (1 << 3)   // Top/Bottom area protect
+#define CONFIG0_BIT_DC   (1 << 6)   // Dummy Cycle
+
+// configuration register 1
+// bit 0, 2, 3, 4, 5, 6, 7 reserved
+#define CONFIG1_BIT_LH   (1 << 1)   // 0 = Ultra Low power mode, 1 = High performance mode
+
+
+
+#define EXTENDED_SPI_ENABLE()                                               \
+                                                                            \
+    const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
+    uint8_t reg_data[reg_size] = { 0 };                                     \
+                                                                            \
+    if (read_register(STATUS_REG, reg_data,                                 \
+            QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+    if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE,         \
+            QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) {              \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    if (write_enable(qspi) != QSPI_STATUS_OK) {                             \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    reg_data[1] |= STATUS_BIT_QE;                                            \
+    if (write_register(QSPI_CMD_WRSR, reg_data,                             \
+            reg_size, qspi) != QSPI_STATUS_OK) {                            \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    WAIT_FOR(WRSR_MAX_TIME, qspi);                                          \
+                                                                            \
+    memset(reg_data, 0, QSPI_STATUS_REG_SIZE);                              \
+    if (read_register(CONFIG_REG0, reg_data,                                 \
+            QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    return ((reg_data[0] & STATUS_BIT_QE) != 0 ?                            \
+            QSPI_STATUS_OK : QSPI_STATUS_ERROR)
+
+
+
+#define EXTENDED_SPI_DISABLE()                                              \
+                                                                            \
+    const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
+    uint8_t reg_data[reg_size] = { 0 };                                     \
+                                                                            \
+    if (read_register(STATUS_REG, reg_data,                                 \
+            QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE,         \
+            QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) {              \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    if (write_enable(qspi) != QSPI_STATUS_OK) {                             \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    reg_data[1] &= ~(STATUS_BIT_QE);                                        \
+                                                                            \
+    if (write_register(QSPI_CMD_WRSR, reg_data,                             \
+            reg_size, qspi) != QSPI_STATUS_OK) {                            \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    WAIT_FOR(WRSR_MAX_TIME, qspi);                                          \
+                                                                            \
+    reg_data[0] = 0;                                                        \
+    if (read_register(CONFIG_REG0, reg_data,                                \
+        QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {                    \
+        return QSPI_STATUS_ERROR;                                           \
+    }                                                                       \
+                                                                            \
+    return ((reg_data[0] & STATUS_BIT_QE) == 0 ?                            \
+            QSPI_STATUS_OK : QSPI_STATUS_ERROR)
+
+
+#endif // MBED_QSPI_FLASH_S25FS512S_H

TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

@@ -66,8 +66,24 @@
 #elif defined(TARGET_LPC546XX)
 #include "NXP/LPC546XX/flash_config.h"
 
-#elif (defined(TARGET_CY8CPROTO_062_4343W) || defined(TARGET_CY8CKIT_062_WIFI_BT) || defined(TARGET_CY8CKIT_062_BLE))
+#elif(  defined(TARGET_CY8CKIT_062_BLE) ||          \
+        defined(TARGET_CY8CKIT_062_WIFI_BT) ||      \
+        defined(TARGET_CY8CKIT_062S2_43012) ||      \
+        defined(TARGET_CY8CKIT_062S2_4343W) ||      \
+        defined(TARGET_CY8CKIT_064S2_4343W) ||      \
+        defined(TARGET_CY8CPROTO_062_4343W) ||      \
+        defined(TARGET_CY8CPROTO_062S2_43012) ||    \
+        defined(TARGET_CY8CPROTO_062S3_4343W) ||    \
+        defined(TARGET_CYW943012P6EVB_01) ||        \
+        defined(TARGET_CYW9P62S1_43438EVB_01))
 #include "S25FL512S_config.h"
 
+#elif   defined(TARGET_CYW9P62S1_43012EVB_01)
+#include "S25FS128S_config.h"
+
+#elif   defined(TARGET_CY8CPROTO_064_SB)
+#include "S25FL128S_config.h"
+
 #endif
 #endif // MBED_FLASH_CONFIGS_H
+

features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp

@@ -18,31 +18,59 @@
 #if DEVICE_SERIAL && DEVICE_SERIAL_FC
 
 #include "CyH4TransportDriver.h"
-#include "cycfg_pins.h"
 
 namespace ble {
 namespace vendor {
 namespace cypress_ble {
 
-CyH4TransportDriver::CyH4TransportDriver(PinName tx, PinName rx, PinName cts, PinName rts, int baud, PinName bt_host_wake_name, PinName bt_device_wake_name) :
+
+CyH4TransportDriver::CyH4TransportDriver(PinName tx, PinName rx, PinName cts, PinName rts, int baud, PinName bt_host_wake_name, PinName bt_device_wake_name, uint8_t host_wake_irq, uint8_t dev_wake_irq) :
     uart(tx, rx, baud), cts(cts), rts(rts),
     bt_host_wake_name(bt_host_wake_name),
     bt_device_wake_name(bt_device_wake_name),
     bt_host_wake(bt_host_wake_name, PIN_INPUT, PullNone, 0),
-    bt_device_wake(bt_device_wake_name, PIN_OUTPUT, PullDefault, 1)
+    bt_device_wake(bt_device_wake_name, PIN_OUTPUT, PullDefault, 1),
+    host_wake_irq_event(host_wake_irq),
+    dev_wake_irq_event(dev_wake_irq)
 {
+    enabled_powersave = true;
+}
+
+CyH4TransportDriver::CyH4TransportDriver(PinName tx, PinName rx, PinName cts, PinName rts, int baud) :
+    uart(tx, rx, baud),
+    cts(cts),
+    rts(rts),
+    bt_host_wake_name(NC),
+    bt_device_wake_name(NC),
+    bt_host_wake(bt_host_wake_name),
+    bt_device_wake(bt_device_wake_name)
+{
+    enabled_powersave = false;
+    sleep_manager_lock_deep_sleep();
+    holding_deep_sleep_lock = true;
+}
+
+CyH4TransportDriver::~CyH4TransportDriver()
+{
+    if (holding_deep_sleep_lock)
+    {
+       sleep_manager_unlock_deep_sleep();
+       holding_deep_sleep_lock = false;
+    }
 }
 
 void CyH4TransportDriver::bt_host_wake_irq_handler(void)
 {
-	sleep_manager_lock_deep_sleep();
-	CyH4TransportDriver::on_controller_irq();
-	sleep_manager_unlock_deep_sleep();
+    sleep_manager_lock_deep_sleep();
+    CyH4TransportDriver::on_controller_irq();
+    sleep_manager_unlock_deep_sleep();
 }
 
 void CyH4TransportDriver::initialize()
 {
+#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER)
 	InterruptIn *host_wake_pin;
+#endif
 
     uart.format(
         /* bits */ 8,
@@ -64,11 +92,21 @@ void CyH4TransportDriver::initialize()
 #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER)
     //Register IRQ for Host WAKE
     host_wake_pin = new InterruptIn(bt_host_wake_name);
-    host_wake_pin->fall(callback(this, &CyH4TransportDriver::bt_host_wake_irq_handler));
+    if (host_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) {
+       host_wake_pin->fall(callback(this, &CyH4TransportDriver::bt_host_wake_irq_handler));
+    } else {
+       host_wake_pin->rise(callback(this, &CyH4TransportDriver::bt_host_wake_irq_handler));
+    }
 
 #endif
-    bt_device_wake = 0;
-    wait_ms(500);
+    if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) {
+       if (bt_device_wake_name != NC)
+           bt_device_wake = WAKE_EVENT_ACTIVE_LOW;
+    } else {
+       if (bt_device_wake_name != NC)
+           bt_device_wake = WAKE_EVENT_ACTIVE_HIGH;
+    }
+    rtos::ThisThread::sleep_for(500);
 }
 
 void CyH4TransportDriver::terminate() {  }
@@ -105,7 +143,11 @@ void CyH4TransportDriver::on_controller_irq()
 void CyH4TransportDriver::assert_bt_dev_wake()
 {
 #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER)
-    bt_device_wake = 0;
+    if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) {
+       bt_device_wake = WAKE_EVENT_ACTIVE_LOW;
+    } else {
+       bt_device_wake = WAKE_EVENT_ACTIVE_HIGH;
+    }
 #endif
 }
 
@@ -113,12 +155,55 @@ void CyH4TransportDriver::deassert_bt_dev_wake()
 {
 #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER)
 	//De-assert bt_device_wake
-	bt_device_wake = 1;
+    if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) {
+       bt_device_wake = WAKE_EVENT_ACTIVE_HIGH;
+    } else {
+       bt_device_wake = WAKE_EVENT_ACTIVE_LOW;
+    }
 #endif
 }
 
+bool CyH4TransportDriver::get_enabled_powersave()
+{
+    return (enabled_powersave);
+}
+
+uint8_t CyH4TransportDriver::get_host_wake_irq_event()
+{
+    return (host_wake_irq_event);
+}
+
+uint8_t CyH4TransportDriver::get_dev_wake_irq_event()
+{
+    return (dev_wake_irq_event);
+}
+
+
 } // namespace cypress_ble
 } // namespace vendor
 } // namespace ble
 
+ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_default_h4_transport_driver()
+{
+#if (defined(CYBSP_BT_HOST_WAKE) && defined(CYBSP_BT_DEVICE_WAKE))
+    static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver(
+       /* TX */ CYBSP_BT_UART_TX, /* RX */ CYBSP_BT_UART_RX,
+       /* cts */ CYBSP_BT_UART_CTS, /* rts */ CYBSP_BT_UART_RTS, DEF_BT_BAUD_RATE,
+       CYBSP_BT_HOST_WAKE, CYBSP_BT_DEVICE_WAKE
+    );
+
+#else
+    static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver(
+        /* TX */ CYBSP_BT_UART_TX, /* RX */ CYBSP_BT_UART_RX,
+        /* cts */ CYBSP_BT_UART_CTS, /* rts */ CYBSP_BT_UART_RTS, DEF_BT_BAUD_RATE);
+#endif
+    return s_transport_driver;
+}
+
+MBED_WEAK
+ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver()
+{
+    return (ble_cordio_get_default_h4_transport_driver());
+}
+
 #endif

features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h

@@ -25,7 +25,6 @@
 #include "CordioHCITransportDriver.h"
 #include "drivers/DigitalInOut.h"
 
-
 namespace ble {
 namespace vendor {
 namespace cypress_ble {
@@ -41,12 +40,14 @@ public:
      * Initialize the transport driver.
      *
      */
-	CyH4TransportDriver(PinName tx, PinName rx, PinName cts, PinName rts, int baud, PinName bt_host_wake_name, PinName bt_device_wake_name);
+	CyH4TransportDriver(PinName tx, PinName rx, PinName cts, PinName rts, int baud, PinName bt_host_wake_name, PinName bt_device_wake_name,
+                            uint8_t host_wake_irq = 0, uint8_t dev_wake_irq = 0);
+        CyH4TransportDriver(PinName tx, PinName rx, PinName cts, PinName rts, int baud);
 
     /**
      * Destructor
      */
-    virtual ~CyH4TransportDriver() { }
+    virtual ~CyH4TransportDriver();
 
     /**
      * @see CordioHCITransportDriver::initialize
@@ -65,7 +66,10 @@ public:
 
     void bt_host_wake_irq_handler();
 
-private:
+    bool get_enabled_powersave();
+    uint8_t get_host_wake_irq_event();
+    uint8_t get_dev_wake_irq_event();
+
 private:
     void on_controller_irq();
     void assert_bt_dev_wake();
@@ -80,13 +84,28 @@ private:
     PinName rts;
     PinName bt_host_wake_name;
     PinName bt_device_wake_name;
+
     DigitalInOut bt_host_wake;
     DigitalInOut bt_device_wake;
+
+    bool     enabled_powersave;
+    uint8_t  host_wake_irq_event;
+    uint8_t  dev_wake_irq_event;
+
+    bool     holding_deep_sleep_lock;
+
 };
 
 } // namespace cypress
 } // namespace vendor
 } // namespace ble
 
+#define DEF_BT_BAUD_RATE    (115200)
+
+#define WAKE_EVENT_ACTIVE_HIGH ( 1 )      /* Interrupt Rising Edge  */
+#define WAKE_EVENT_ACTIVE_LOW  ( 0 )      /* Interrupt Falling Edge */
+
+ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_default_h4_transport_driver();
+ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver();
 #endif
 #endif /* CY_H4TRANSPORT_DRIVER_H_ */

features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp

@@ -25,7 +25,6 @@
 #include <stdbool.h>
 #include "hci_mbed_os_adaptation.h"
 #include "CyH4TransportDriver.h"
-#include "cycfg_pins.h"
 
 extern const int brcm_patch_ram_length;
 extern const uint8_t brcm_patchram_buf[];
@@ -57,10 +56,16 @@ class HCIDriver : public cordio::CordioHCIDriver {
 public:
     HCIDriver(
         cordio::CordioHCITransportDriver& transport_driver,
-        PinName bt_power_name
+        PinName bt_power_name,
+	bool ps_enabled,
+	uint8_t host_wake_irq,
+	uint8_t dev_wake_irq
     ) : cordio::CordioHCIDriver(transport_driver),
         bt_power_name(bt_power_name),
         bt_power(bt_power_name, PIN_OUTPUT, PullUp, 0),
+	is_powersave_enabled(ps_enabled),
+	host_wake_irq(host_wake_irq),
+	dev_wake_irq(dev_wake_irq),
         service_pack_index(0),
         service_pack_ptr(0),
         service_pack_length(0),
@@ -77,7 +82,7 @@ public:
     virtual void do_initialize()
     {
         bt_power = 1;
-        wait_ms(500);
+        rtos::ThisThread::sleep_for(500);
     }
 
     virtual void do_terminate() { }
@@ -290,7 +295,7 @@ private:
         service_pack_next = &HCIDriver::terminate_service_pack_transfert;;
         service_pack_index = 0;
         service_pack_transfered = false;
-        wait_ms(1000);
+        rtos::ThisThread::sleep_for(1000);
         send_service_pack_command();
     }
 
@@ -343,11 +348,23 @@ private:
             uint8_t *pBuf;
             if ((pBuf = hciCmdAlloc(HCI_VS_CMD_SET_SLEEP_MODE, 12)) != NULL)
             {
-                  pBuf[HCI_CMD_HDR_LEN] = 0x00; // no sleep
+                  if (is_powersave_on()) {
+                     pBuf[HCI_CMD_HDR_LEN] = 0x01; // sleep
+		  } else {
+                     pBuf[HCI_CMD_HDR_LEN] = 0x00; // no sleep
+		  }
                   pBuf[HCI_CMD_HDR_LEN + 1] = 0x00; // no idle threshold host (N/A)
                   pBuf[HCI_CMD_HDR_LEN + 2] = 0x00; // no idle threshold HC (N/A)
-                  pBuf[HCI_CMD_HDR_LEN + 3] = 0x00; // BT WAKE
-                  pBuf[HCI_CMD_HDR_LEN + 4] = 0x00; // HOST WAKE
+                  if (is_powersave_on()) {
+                     pBuf[HCI_CMD_HDR_LEN + 3] = dev_wake_irq; // BT WAKE
+		  } else {
+                     pBuf[HCI_CMD_HDR_LEN + 3] = 0x00; // BT WAKE
+		  }
+                  if (is_powersave_on()) {
+                      pBuf[HCI_CMD_HDR_LEN + 4] = host_wake_irq; // HOST WAKE
+		  } else {
+                     pBuf[HCI_CMD_HDR_LEN + 3] = 0x00; // BT WAKE
+		  }
                   pBuf[HCI_CMD_HDR_LEN + 5] = 0x00; // Sleep during SCO
                   pBuf[HCI_CMD_HDR_LEN + 6] = 0x00; // Combining sleep mode and SCM
                   pBuf[HCI_CMD_HDR_LEN + 7] = 0x00; // Tristate TX
@@ -406,8 +423,18 @@ private:
         }
     }
 
+    bool is_powersave_on(void)
+    {
+       return (is_powersave_enabled);
+    }
+
     PinName bt_power_name;
     DigitalInOut bt_power;
+
+    bool is_powersave_enabled;
+    uint8_t host_wake_irq;
+    uint8_t dev_wake_irq;
+
     size_t service_pack_index;
     const uint8_t* service_pack_ptr;
     int service_pack_length;
@@ -420,15 +447,16 @@ private:
 } // namespace vendor
 } // namespace ble
 
-ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
-    static ble::vendor::cypress_ble::CyH4TransportDriver transport_driver(
-        /* TX */ CY_BT_UART_TX, /* RX */ CY_BT_UART_RX,
-        /* cts */ CY_BT_UART_CTS, /* rts */ CY_BT_UART_RTS, 115200,
-		CY_BT_PIN_HOST_WAKE, CY_BT_PIN_DEVICE_WAKE
-    );
+ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver()
+{
+    static ble::vendor::cypress_ble::CyH4TransportDriver& transport_driver =
+          ble_cordio_get_h4_transport_driver();
     static ble::vendor::cypress::HCIDriver hci_driver(
         transport_driver,
-        /* bt_power */ CY_BT_PIN_POWER
+        /* bt_power */ CYBSP_BT_POWER,
+	transport_driver.get_enabled_powersave(),
+	transport_driver.get_host_wake_irq_event(),
+	transport_driver.get_dev_wake_irq_event()
     );
     return hci_driver;
 }

features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/TARGET_PSOC6/cy_bt_cordio_cfg.cpp

@@ -0,0 +1,125 @@
+/*******************************************************************************
+* \file cy_bt_cordio_cfg.cpp
+* \version 1.0
+*
+*
+* Low Power Assist BT Pin configuration implementation.
+*
+********************************************************************************
+* \copyright
+* Copyright 2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdio.h>
+#include "CordioBLE.h"
+#include "CordioHCIDriver.h"
+#include "hci_api.h"
+#include "hci_cmd.h"
+#include "hci_core.h"
+#include "bstream.h"
+#include "assert.h"
+#include <stdbool.h>
+#include "hci_mbed_os_adaptation.h"
+#include "CyH4TransportDriver.h"
+#include "cycfg.h"
+
+/* Sanity Checks for Pin Configuration. Fail compilation if Sanity Check is enabled
+ * and configuration is incorrect
+ */
+
+#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER)
+
+#if ((defined(CYCFG_BT_LP_ENABLED)) && (CYCFG_BT_LP_ENABLED != 0))
+
+#if (!defined(CY_BT_SKIP_CONFIGURATION_CHECKS))
+#if ((!defined(CYCFG_BT_HOST_WAKE_GPIO)) || (!defined(CYCFG_BT_DEV_WAKE_GPIO)))
+#error "configurator host-wake and dev-wake pins must be configured when deep-sleep is enabled"
+#endif
+static_assert(((CYCFG_BT_HOST_WAKE_GPIO != NC) && (CYCFG_BT_DEV_WAKE_GPIO != NC)), \
+       "configurator host-wake and dev-wake pins must not be NC (no connect) when deep-sleep is enabled");
+#endif /* (!defined(CY_BT_SKIP_CONFIGURATION_CHECKS)) */
+
+#else  /* ((defined(CYCFG_BT_LP_ENABLED)) && (CYCFG_BT_LP_ENABLED != 0)) */
+
+#if (!defined(CY_BT_SKIP_CONFIGURATION_CHECKS))
+#if ((!defined(CYBSP_BT_HOST_WAKE)) || (!defined(CYBSP_BT_DEVICE_WAKE)))
+#error "BSP configuration host-wake and dev-wake pin must be configured when deep-sleep is enabled"
+#endif
+static_assert(((CYBSP_BT_HOST_WAKE != NC)  && (CYBSP_BT_DEVICE_WAKE != NC)), \
+       "BSP configuration host-wake and dev-wake pin must not be NC (no connect) when deep-sleep is enabled");
+#endif /* (!defined(CY_BT_SKIP_CONFIGURATION_CHECKS)) */
+
+#endif /* ((defined(CYCFG_BT_LP_ENABLED)) && (CYCFG_BT_LP_ENABLED != 0)) */
+
+#endif /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */
+
+
+/*******************************************************************************
+* Function Name: ble_cordio_get_h4_transport_driver
+********************************************************************************
+*
+* Strong implementation of function which calls CyH4TransportDriver constructor and return it
+*
+* \param none
+*
+* \return
+* Returns the transport driver object
+*******************************************************************************/
+ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver()
+{
+#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER)
+
+#if (defined(CYCFG_BT_LP_ENABLED))
+    if (CYCFG_BT_LP_ENABLED) {
+       static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver(
+          /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX),
+          /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX),
+          /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS),
+          /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), DEF_BT_BAUD_RATE,
+          cyhal_gpio_to_rtos(CYCFG_BT_HOST_WAKE_GPIO),
+          cyhal_gpio_to_rtos(CYCFG_BT_DEV_WAKE_GPIO),
+          CYCFG_BT_HOST_WAKE_IRQ_EVENT,
+          CYCFG_BT_DEV_WAKE_POLARITY
+       );
+       return s_transport_driver;
+    } else { /* CYCFG_BT_LP_ENABLED */
+       static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver(
+          /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX),
+          /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX),
+          /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS),
+          /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), DEF_BT_BAUD_RATE);
+       return s_transport_driver;
+    }
+#else  /* (defined(CYCFG_BT_LP_ENABLED)) */
+    static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver(
+       /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX),
+       /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX),
+       /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS),
+       /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), DEF_BT_BAUD_RATE,
+       cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE)
+    );
+    return s_transport_driver;
+#endif /* (defined(CYCFG_BT_LP_ENABLED)) */
+
+#else /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */
+    static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver(
+       /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX),
+       /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX),
+       /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS),
+       /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), DEF_BT_BAUD_RATE);
+    return s_transport_driver;
+#endif /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */
+}

features/netsocket/emac-drivers/TARGET_WHD/interface/CyDhcpServer.cpp

@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "CyDhcpServer.h"
+#include "cy_utils.h"
+#include "Callback.h"
+#include "def.h"
+#include "whd_types.h"
+
+#ifdef DHCP_EXTENSIVE_DEBUG
+extern "C" void dhcp_server_print_header_info(dhcp_packet_t *header, uint32_t datalen, const char *title);
+#endif
+
+/* UDP port numbers for DHCP server and client */
+#define IP_PORT_DHCP_SERVER                         (67)
+#define IP_PORT_DHCP_CLIENT                         (68)
+
+/* BOOTP operations */
+#define BOOTP_OP_REQUEST                            (1)
+#define BOOTP_OP_REPLY                              (2)
+
+/* DCHP message types */
+#define DHCP_MSG_TYPE_DISCOVER                      (1)
+#define DHCP_MSG_TYPE_OFFER                         (2)
+#define DHCP_MSG_TYPE_REQUEST                       (3)
+#define DHCP_MSG_TYPE_DECLINE                       (4)
+#define DHCP_MSG_TYPE_ACK                           (5)
+#define DHCP_MSG_TYPE_NACK                          (6)
+#define DHCP_MSG_TYPE_RELEASE                       (7)
+#define DHCP_MSG_TYPE_INFORM                        (8)
+#define DHCP_MSG_TYPE_INVALID                       (255)
+
+#define DHCP_MSG_MAGIC_COOKIE                       (0x63825363)
+
+#define DHCP_STACK_SIZE                             (8*1024)
+
+/********************* Options manipulation functions ***********************************/
+static void addOption(dhcp_packet_t *dhcp, uint32_t &index, uint8_t optype)
+{
+    if (index + sizeof(dhcp_packet_t) - 1 + 1 >= DHCP_PACKET_SIZE) {
+        printf("DHCP ERROR: Option index %d (Optype: %d) written to exceeds size of the packet", (int)index, (int)optype);
+        return;
+    }
+
+    dhcp->Options[index++] = optype;
+
+    return;
+}
+
+static void addOption(dhcp_packet_t *dhcp, uint32_t &index, uint8_t optype, uint8_t value)
+{
+    if (index + sizeof(dhcp_packet_t) - 1 + 3 >= DHCP_PACKET_SIZE) {
+        printf("DHCP ERROR: Option index %d (Optype: %d) written to exceeds size of the packet", (int)index, (int)optype);
+        return;
+    }
+
+    dhcp->Options[index++] = optype;
+    dhcp->Options[index++] = 0x01;
+    dhcp->Options[index++] = value;
+
+    return;
+}
+
+static void addOption(dhcp_packet_t *dhcp, uint32_t &index, uint8_t optype, uint16_t value)
+{
+    if (index + sizeof(dhcp_packet_t) - 1 + 4 >= DHCP_PACKET_SIZE) {
+        printf("DHCP ERROR: Option index %d (Optype: %d) written to exceeds size of the packet", (int)index, (int)optype);
+        return;
+    }
+
+    dhcp->Options[index++] = optype;
+    dhcp->Options[index++] = 0x02;
+    dhcp->Options[index++] = static_cast<uint8_t>((value >> 0) & 0xFF);
+    dhcp->Options[index++] = static_cast<uint8_t>((value >> 8) & 0xFF);
+
+    return;
+}
+
+static void addOption(dhcp_packet_t *dhcp, uint32_t &index, uint8_t optype, uint32_t value)
+{
+    if (index + sizeof(dhcp_packet_t) - 1 + 6 >= DHCP_PACKET_SIZE) {
+        printf("DHCP ERROR: Option index %d (Optype: %d) written to exceeds size of the packet", (int)index, (int)optype);
+        return;
+    }
+
+    dhcp->Options[index++] = optype;
+    dhcp->Options[index++] = 0x04;
+    dhcp->Options[index++] = static_cast<uint8_t>((value >> 0) & 0xFF);
+    dhcp->Options[index++] = static_cast<uint8_t>((value >> 8) & 0xFF);
+    dhcp->Options[index++] = static_cast<uint8_t>((value >> 16) & 0xFF);
+    dhcp->Options[index++] = static_cast<uint8_t>((value >> 24) & 0xFF);
+
+    return;
+}
+
+static void addOption(dhcp_packet_t *dhcp, uint32_t &index, uint8_t optype, uint8_t *value, uint32_t size)
+{
+    if (index + sizeof(dhcp_packet_t) - 1 + 2 + size >= DHCP_PACKET_SIZE) {
+        printf("DHCP ERROR: Option index %d (Optype: %d) written to exceeds size of the packet", (int)index, (int)optype);
+        return;
+    }
+
+    dhcp->Options[index++] = optype;
+    dhcp->Options[index++] = size;
+    memcpy(&dhcp->Options[index], value, size);
+    index += size;
+
+    return;
+}
+
+static const uint8_t *findOption(const dhcp_packet_t *request, uint8_t option_num)
+{
+    const uint8_t *option_ptr = request->Options;
+    while ((option_ptr[0] != DHCP_END_OPTION_CODE) &&
+            (option_ptr[0] != option_num) &&
+            (option_ptr < ((const uint8_t *)request) + DHCP_PACKET_SIZE)) {
+        option_ptr += option_ptr[1] + 2;
+    }
+
+    /* Was the option found? */
+    if (option_ptr[0] == option_num) {
+        return &option_ptr[2];
+    }
+    return NULL;
+}
+
+static void addCommonOptions(dhcp_packet_t *dhcp, uint32_t &index, const uint32_t server_addr, const uint32_t netmask)
+{
+    /* Prepare the Web proxy auto discovery URL */
+    char wpad_sample_url[] = "http://xxx.xxx.xxx.xxx/wpad.dat";
+    char ip_str[16];
+    ipv4_to_string(ip_str, htonl(server_addr));
+    memcpy(&wpad_sample_url[7], &ip_str[0], 15);
+
+    /* Server identifier */
+    addOption(dhcp, index, DHCP_SERVER_IDENTIFIER_OPTION_CODE, server_addr);
+    /* Lease Time */
+    addOption(dhcp, index, DHCP_LEASETIME_OPTION_CODE, static_cast<uint32_t>(0x00015180));
+    /* Subnet Mask */
+    addOption(dhcp, index, DHCP_SUBNETMASK_OPTION_CODE, htonl(netmask));
+    /* Web proxy auto discovery URL */
+    addOption(dhcp, index, DHCP_WPAD_OPTION_CODE, (uint8_t *)&wpad_sample_url[0], strlen(wpad_sample_url));
+    /* Router (gateway) */
+    addOption(dhcp, index, DHCP_ROUTER_OPTION_CODE, htonl(server_addr));
+    /* DNS server */
+    addOption(dhcp, index, DHCP_DNS_SERVER_OPTION_CODE, htonl(server_addr));
+    /* Interface MTU */
+    addOption(dhcp, index, DHCP_MTU_OPTION_CODE, static_cast<uint16_t>(WHD_PAYLOAD_MTU));
+}
+
+static void sendPacket(UDPSocket *socket, dhcp_packet_t *dhcp, uint32_t size)
+{
+    nsapi_size_or_error_t err;
+    uint32_t broadcast_ip = 0xFFFFFFFF;
+    char string_addr[16];
+    ipv4_to_string(string_addr, htonl(broadcast_ip));
+
+    err = socket->sendto(string_addr, IP_PORT_DHCP_CLIENT, reinterpret_cast<uint8_t *>(dhcp), size);
+    if (err < 0) {
+        printf("DHCP ERROR: Packet send failure with error %d.", err);
+    } else if (err != (int)size) {
+        printf("DHCP ERROR: Could not send entire packet. Only %d bytes were sent.", err);
+    }
+}
+
+/********************* Cache utility functions ***********************************/
+void CyDhcpServer::setAddress(const cy_mac_addr_t &mac_id, const cy_ip_addr_t &addr)
+{
+    uint32_t a;
+    uint32_t first_empty_slot;
+    uint32_t cached_slot;
+    char empty_cache[NSAPI_IPv6_SIZE] = "";
+
+    /* Search for empty slot in cache */
+    for (a = 0, first_empty_slot = DHCP_IP_ADDRESS_CACHE_MAX, cached_slot = DHCP_IP_ADDRESS_CACHE_MAX; a < DHCP_IP_ADDRESS_CACHE_MAX; a++) {
+        /* Check for matching MAC address */
+        if (memcmp(&_mac_addr_cache[a], &mac_id, sizeof(mac_id)) == 0) {
+            /* Cached device found */
+            cached_slot = a;
+            break;
+        } else if (first_empty_slot == DHCP_IP_ADDRESS_CACHE_MAX && memcmp(&_mac_addr_cache[a], &empty_cache, sizeof(cy_mac_addr_t)) == 0) {
+            /* Device not found in cache. Return the first empty slot */
+            first_empty_slot = a;
+        }
+    }
+
+    if (cached_slot != DHCP_IP_ADDRESS_CACHE_MAX) {
+        /* Update IP address of cached device */
+        _ip_addr_cache[cached_slot] = addr;
+    } else if (first_empty_slot != DHCP_IP_ADDRESS_CACHE_MAX) {
+        /* Add device to the first empty slot */
+        _mac_addr_cache[first_empty_slot] = mac_id;
+        _ip_addr_cache[first_empty_slot] = addr;
+    } else {
+        /* Cache is full. Add device to slot 0 */
+        _mac_addr_cache[0] = mac_id;
+        _ip_addr_cache [0] = addr;
+    }
+}
+
+bool CyDhcpServer::lookupAddress(const cy_mac_addr_t &mac_id, cy_ip_addr_t &addr)
+{
+    /* Check whether device is already cached */
+    for (uint32_t a = 0; a < DHCP_IP_ADDRESS_CACHE_MAX; a++) {
+        if (memcmp(&_mac_addr_cache[a], &mac_id, sizeof(mac_id)) == 0) {
+            addr = _ip_addr_cache[a];
+            return true;
+        }
+    }
+    return false;
+}
+
+void CyDhcpServer::freeAddress(const cy_mac_addr_t &mac_id)
+{
+    /* Check whether device is already cached */
+    for (uint32_t a = 0; a < DHCP_IP_ADDRESS_CACHE_MAX; a++) {
+        if (memcmp(&_mac_addr_cache[a], &mac_id, sizeof(mac_id)) == 0) {
+            memset(&_mac_addr_cache[a], 0, sizeof(_mac_addr_cache[a]));
+            memset(&_ip_addr_cache[a], 0, sizeof(_ip_addr_cache[a]));
+        }
+    }
+}
+
+void CyDhcpServer::handleDiscover(dhcp_packet_t *dhcp)
+{
+#ifdef DHCP_EXTENSIVE_DEBUG
+    dhcp_server_print_header_info(dhcp, DHCP_PACKET_SIZE, "\n\nDHCP DISCOVER RECEIVED");
+#endif
+
+    uint32_t index;
+    cy_mac_addr_t client_mac;
+    cy_ip_addr_t client_ip;
+
+    memcpy(&client_mac, dhcp->ClientHwAddr, sizeof(client_mac));
+    if (!lookupAddress(client_mac, client_ip)) {
+        client_ip = _available_addr;
+    }
+
+    memset(&dhcp->Legacy, 0, sizeof(dhcp->Legacy));
+    memset(&dhcp->Options[0], 0, DHCP_PACKET_SIZE - sizeof(dhcp_packet_t) + 3);
+
+    dhcp->Opcode = BOOTP_OP_REPLY;
+    dhcp->YourIpAddr = htonl(client_ip.addrv4.addr);
+    dhcp->MagicCookie = htonl(static_cast<uint32_t>(DHCP_MSG_MAGIC_COOKIE));
+
+    /* Add options */
+    index = 0;
+    addOption(dhcp, index, DHCP_MESSAGETYPE_OPTION_CODE, static_cast<uint8_t>(DHCP_MSG_TYPE_OFFER));
+    addCommonOptions(dhcp, index, _server_addr.addrv4.addr, _netmask.addrv4.addr);
+    addOption(dhcp, index, static_cast<uint8_t>(DHCP_END_OPTION_CODE));
+
+    uint32_t size = sizeof(dhcp_packet_t) + index - 1;
+    CY_ASSERT(size <= DHCP_PACKET_SIZE);
+
+#ifdef DHCP_EXTENSIVE_DEBUG
+    dhcp_server_print_header_info(dhcp, size, "\n\nDHCP OFFER SENT");
+#endif
+    sendPacket(&_socket, dhcp, size);
+}
+
+void CyDhcpServer::handleRequest(dhcp_packet_t *dhcp)
+{
+#ifdef DHCP_EXTENSIVE_DEBUG
+    dhcp_server_print_header_info(dhcp, DHCP_PACKET_SIZE, "\n\nDHCP REQUEST RECEIVED");
+#endif
+
+    cy_mac_addr_t client_mac;
+    cy_ip_addr_t client_ip;
+    cy_ip_addr_t req_ip;
+    bool increment = false;
+    uint32_t index;
+
+    /* Check that the REQUEST is for this server */
+    uint32_t *server_id_req = (uint32_t *)findOption(dhcp, DHCP_SERVER_IDENTIFIER_OPTION_CODE);
+    if ((server_id_req == NULL) || ((server_id_req != NULL) && (_server_addr.addrv4.addr != *server_id_req))) {
+        return; /* Server ID was not found or does not match local IP address */
+    }
+
+    /* Locate the requested address in the options and keep requested address */
+    req_ip.addrv4.addr = ntohl(*(uint32_t *)findOption(dhcp, DHCP_REQUESTED_IP_ADDRESS_OPTION_CODE));
+
+    memcpy(&client_mac, dhcp->ClientHwAddr, sizeof(client_mac));
+    if (!lookupAddress(client_mac, client_ip)) {
+        client_ip = _available_addr;
+        increment = true;
+    }
+
+    memset(&dhcp->Legacy, 0, sizeof(dhcp->Legacy));
+    memset(&dhcp->Options[0], 0, DHCP_PACKET_SIZE - sizeof(dhcp_packet_t) + 3);
+
+    dhcp->Opcode = BOOTP_OP_REPLY;
+    dhcp->MagicCookie = htonl(static_cast<uint32_t>(DHCP_MSG_MAGIC_COOKIE));
+
+    index = 0;
+    /* Check if the requested IP address matches one we have assigned */
+    if (req_ip.addrv4.addr != client_ip.addrv4.addr) {
+        /* Request is not for the assigned IP - force client to take next available IP by sending NAK */
+        addOption(dhcp, index, DHCP_MESSAGETYPE_OPTION_CODE, static_cast<uint8_t>(DHCP_MSG_TYPE_NACK));
+        addOption(dhcp, index, DHCP_SERVER_IDENTIFIER_OPTION_CODE, _server_addr.addrv4.addr);
+        printf("\n\nDHCP_THREAD: %d REQUEST NAK\n", __LINE__);
+    } else {
+        dhcp->YourIpAddr = htonl(client_ip.addrv4.addr);
+
+        addOption(dhcp, index, DHCP_MESSAGETYPE_OPTION_CODE, static_cast<uint8_t>(DHCP_MSG_TYPE_ACK));
+        addCommonOptions(dhcp, index, _server_addr.addrv4.addr, _netmask.addrv4.addr);
+
+        if (increment) {
+            uint32_t ip_mask = ~(_netmask.addrv4.addr);
+            uint32_t subnet = _server_addr.addrv4.addr & _netmask.addrv4.addr;
+            do {
+                _available_addr.addrv4.addr = subnet | ((_available_addr.addrv4.addr + 1) & ip_mask);
+            } while (_available_addr.addrv4.addr == _server_addr.addrv4.addr);
+        }
+        setAddress(client_mac, client_ip);
+    }
+    addOption(dhcp, index, static_cast<uint8_t>(DHCP_END_OPTION_CODE));
+
+    uint32_t size = sizeof(dhcp_packet_t) + index - 1;
+    CY_ASSERT(size <= DHCP_PACKET_SIZE);
+
+#ifdef DHCP_EXTENSIVE_DEBUG
+    dhcp_server_print_header_info(dhcp, DHCP_PACKET_SIZE, "\n\nDHCP REQUEST REPLY SENT");
+#endif
+    sendPacket(&_socket, dhcp, size);
+}
+
+void CyDhcpServer::runServer(void)
+{
+    nsapi_size_or_error_t err_or_size;
+
+    _running = true;
+
+    /* Create receive DHCP socket */
+    _socket.open(_nstack);
+    _socket.bind((uint16_t)IP_PORT_DHCP_SERVER);
+
+    /* Save the current netmask to be sent in DHCP packets as the 'subnet mask option' */
+    _server_addr.addrv4.addr = string_to_ipv4(_niface->get_ip_address());
+    _netmask.addrv4.addr = string_to_ipv4(_niface->get_netmask());
+
+#ifdef DHCP_EXTENSIVE_DEBUG
+    printf("DHCP Server started.\n");
+    printf("DHCP Server: IP     : %s\n", _niface->get_ip_address());
+    printf("DHCP Server: Netmask: %s\n", _niface->get_netmask());
+    printf("DHCP Server: Gateway: %s\n", _niface->get_gateway());
+    printf("DHCP Server: MAC    : %s\n\n", _niface->get_mac_address());
+#endif
+
+    /* Calculate the first available IP address which will be served - based on the netmask and the local IP */
+    uint32_t ip_mask = ~(_netmask.addrv4.addr);
+    uint32_t subnet = _server_addr.addrv4.addr & _netmask.addrv4.addr;
+    _available_addr.addrv4.addr = subnet | ((_server_addr.addrv4.addr + 1) & ip_mask);
+
+    while (_running) {
+        /* Sleep until data is received from socket. */
+        err_or_size = _socket.recv(_buff, DHCP_PACKET_SIZE);
+        /* Options field in DHCP header is variable length. We are looking for option "DHCP Message Type" that is 3 octets in size (code, length and type) */
+        /* If the return value is <0, it is an error; if it is >=0, it is the received length */
+        if (err_or_size < 0 || err_or_size < (int32_t)sizeof(dhcp_packet_t)) {
+            continue;
+        }
+
+        dhcp_packet_t *dhcp = reinterpret_cast<dhcp_packet_t *>(_buff);
+        /* Check if the option in the dhcp header is "DHCP Message Type", code value for option "DHCP Message Type" is 53 as per rfc2132 */
+        if (dhcp->Options[0] != DHCP_MESSAGETYPE_OPTION_CODE) {
+            printf("%d: %s received option code wrong: %d != %d\n", __LINE__, __func__, dhcp->Options[0], DHCP_MESSAGETYPE_OPTION_CODE);
+            continue;
+        }
+
+        uint8_t msg_type = dhcp->Options[2];
+        switch (msg_type) {
+            case DHCP_MSG_TYPE_DISCOVER:
+                handleDiscover(dhcp);
+                break;
+            case DHCP_MSG_TYPE_REQUEST:
+                handleRequest(dhcp);
+                break;
+            default:
+                printf("DHCP ERROR: Unhandled dhcp packet type, %d", msg_type);
+                break;
+        }
+    }
+}
+
+void CyDhcpServer::threadWrapper(CyDhcpServer *obj)
+{
+    obj->runServer();
+}
+
+CyDhcpServer::CyDhcpServer(NetworkStack *nstack, NetworkInterface *niface)
+    : _nstack(nstack),
+      _niface(niface),
+      _thread(osPriorityNormal, DHCP_STACK_SIZE, NULL, "DHCPserver") {}
+
+CyDhcpServer::~CyDhcpServer()
+{
+    stop();
+}
+
+cy_rslt_t CyDhcpServer::start(void)
+{
+    cy_rslt_t result = CY_RSLT_SUCCESS;
+    if (!_running) {
+        CY_ASSERT(_nstack != NULL);
+
+        /* Clear cache */
+        memset(_mac_addr_cache, 0, sizeof(_mac_addr_cache));
+        memset(_ip_addr_cache, 0, sizeof(_ip_addr_cache));
+
+        /* Start DHCP server */
+        if (osOK != _thread.start(mbed::callback(threadWrapper, this))) {
+            result = CY_DHCP_THREAD_CREATION_FAILED;
+        }
+    }
+    return result;
+}
+
+cy_rslt_t CyDhcpServer::stop(void)
+{
+    cy_rslt_t result = CY_RSLT_SUCCESS;
+    if (_running) {
+        _running = false;
+        if (NSAPI_ERROR_OK != _socket.close()) {
+            printf("DHCP ERROR: DHCP socket closure failed.\n");
+            result = CY_DHCP_STOP_FAILED;
+        }
+        if (osOK != _thread.join()) {
+            printf("DHCP ERROR: DHCP thread join failed.\n");
+            result = CY_DHCP_STOP_FAILED;
+        }
+    }
+    return result;
+}

features/netsocket/emac-drivers/TARGET_WHD/interface/CyDhcpServer.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef WHD_DHCP_SERVER_H
+#define WHD_DHCP_SERVER_H
+
+#include "cy_result.h"
+#include "cy_syslib.h"
+#include "cynetwork_utils.h"
+#include "UDPSocket.h"
+#include "netsocket/NetworkInterface.h"
+#include "netsocket/NetworkStack.h"
+#include "rtos.h"
+
+/* DHCP data structure */
+typedef struct {
+    uint8_t  Opcode;            /* packet opcode type */
+    uint8_t  HwType;            /* hardware addr type */
+    uint8_t  HwLen;             /* hardware addr length */
+    uint8_t  Hops;              /* gateway hops */
+    uint32_t TransactionId;     /* transaction ID */
+    uint16_t SecsElapsed;       /* seconds since boot began */
+    uint16_t Flags;
+    uint32_t ClientIpAddr;      /* client IP address */
+    uint32_t YourIpAddr;        /* 'your' IP address */
+    uint32_t ServerIpAddr;      /* server IP address */
+    uint32_t GatewayIpAddr;     /* gateway IP address */
+    uint8_t  ClientHwAddr[16];  /* client hardware address */
+    uint8_t  Legacy[192];       /* SName, File */
+    uint32_t MagicCookie;
+    uint8_t  Options[3];        /* options area */
+    /* as of RFC2131 it is variable length */
+} dhcp_packet_t;
+
+#define DHCP_SUBNETMASK_OPTION_CODE                 (1)
+#define DHCP_ROUTER_OPTION_CODE                     (3)
+#define DHCP_DNS_SERVER_OPTION_CODE                 (6)
+#define DHCP_HOST_NAME_OPTION_CODE                  (12)
+#define DHCP_MTU_OPTION_CODE                        (26)
+#define DHCP_REQUESTED_IP_ADDRESS_OPTION_CODE       (50)
+#define DHCP_LEASETIME_OPTION_CODE                  (51)
+#define DHCP_MESSAGETYPE_OPTION_CODE                (53)
+#define DHCP_SERVER_IDENTIFIER_OPTION_CODE          (54)
+#define DHCP_PARAM_REQUEST_LIST_OPTION_CODE         (55)
+#define DHCP_WPAD_OPTION_CODE                       (252)
+#define DHCP_END_OPTION_CODE                        (255)
+
+#define DHCP_IP_ADDRESS_CACHE_MAX                   (5)
+#define ADDITIONAL_OPTION_BYTES                     (272)
+#define DHCP_PACKET_SIZE                            (sizeof(dhcp_packet_t) + ADDITIONAL_OPTION_BYTES)
+
+/** DHCP thread could not be started */
+#define CY_DHCP_THREAD_CREATION_FAILED  CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_BASE, 0)
+
+/** Error while trying to stop the DHCP server */
+#define CY_DHCP_STOP_FAILED  CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_BASE, 1)
+
+/**
+ *  Implementation of a DHCP sever
+ */
+class CyDhcpServer {
+public:
+    /**
+     * Create a DHCP server.
+     */
+    CyDhcpServer(NetworkStack *nstack, NetworkInterface *niface);
+
+    /**
+     * Delete the DHCP server.
+     */
+    virtual ~CyDhcpServer();
+
+    /**
+     *  Start a DHCP server instance.
+     * @return CY_RSLT_SUCCESS on success otherwise error.
+     */
+    cy_rslt_t start(void);
+
+    /**
+     *  Stop a DHCP server instance.
+     * @return CY_RSLT_SUCCESS on success otherwise error.
+     */
+    cy_rslt_t stop(void);
+
+private:
+    NetworkStack *_nstack = NULL;
+    NetworkInterface *_niface = NULL;
+    UDPSocket _socket;
+    Thread _thread;
+    bool _running = false;
+
+    cy_ip_addr_t _available_addr;
+    cy_ip_addr_t _server_addr;
+    cy_ip_addr_t _netmask;
+
+    cy_mac_addr_t _mac_addr_cache[DHCP_IP_ADDRESS_CACHE_MAX];
+    cy_ip_addr_t _ip_addr_cache[DHCP_IP_ADDRESS_CACHE_MAX];
+    uint8_t _buff[DHCP_PACKET_SIZE];
+
+    static void threadWrapper(CyDhcpServer *obj);
+    void runServer(void);
+
+    void setAddress(const cy_mac_addr_t &mac_id, const cy_ip_addr_t &addr);
+    bool lookupAddress(const cy_mac_addr_t &mac_id, cy_ip_addr_t &addr);
+    void freeAddress(const cy_mac_addr_t &mac_id);
+
+    void handleDiscover(dhcp_packet_t *dhcp);
+    void handleRequest(dhcp_packet_t *dhcp);
+};
+
+#endif /* WHD_DHCP_SERVER_H */

features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSTAInterface.cpp

@@ -36,19 +36,18 @@
                           ((((unsigned char*)a)[5])==(((unsigned char*)b)[5])))
 
 struct whd_scan_userdata {
-    Semaphore *sema;
+    rtos::Semaphore *sema;
     WiFiAccessPoint *aps;
     std::vector<whd_scan_result_t> *result_buff;
     unsigned count;
     unsigned offset;
-    whd_interface_t ifp;
     bool scan_in_progress;
 };
 
 static whd_scan_userdata interal_scan_data;
 static whd_scan_result_t internal_scan_result;
 
-extern "C" void whd_emac_wifi_link_state_changed(bool state_up, whd_interface_t ifp);
+extern "C" void whd_emac_wifi_link_state_changed(whd_interface_t ifp, whd_bool_t state_up);
 
 
 int whd_toerror(whd_result_t res)
@@ -182,8 +181,8 @@ nsapi_error_t WhdSTAInterface::set_credentials(const char *ssid, const char *pas
 {
     if ((ssid == NULL) ||
             (strlen(ssid) == 0) ||
-            (pass == NULL && ( security != NSAPI_SECURITY_NONE && security != NSAPI_SECURITY_WPA2_ENT)) ||
-            (strlen(pass) == 0 && ( security != NSAPI_SECURITY_NONE && security != NSAPI_SECURITY_WPA2_ENT)) ||
+            (pass == NULL && (security != NSAPI_SECURITY_NONE && security != NSAPI_SECURITY_WPA2_ENT)) ||
+            (strlen(pass) == 0 && (security != NSAPI_SECURITY_NONE && security != NSAPI_SECURITY_WPA2_ENT)) ||
             (strlen(pass) > 63 && (security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA || security == NSAPI_SECURITY_WPA_WPA2))
        ) {
         return NSAPI_ERROR_PARAMETER;
@@ -256,7 +255,7 @@ nsapi_error_t WhdSTAInterface::connect()
     }
 
     if (whd_wifi_is_ready_to_transceive(_whd_emac.ifp) == WHD_SUCCESS) {
-        whd_emac_wifi_link_state_changed(true, _whd_emac.ifp);
+        whd_emac_wifi_link_state_changed(_whd_emac.ifp, WHD_TRUE);
     }
 
     // bring up
@@ -351,7 +350,7 @@ static void whd_scan_handler(whd_scan_result_t **result_ptr,
         }
     }
 
-    if (data->count > 0) {
+    if (data->count > 0 && data->aps != NULL) {
         // get ap stats
         nsapi_wifi_ap ap;
 
@@ -388,7 +387,6 @@ int WhdSTAInterface::scan(WiFiAccessPoint *aps, unsigned count)
     interal_scan_data.aps = aps;
     interal_scan_data.count = count;
     interal_scan_data.offset = 0;
-    interal_scan_data.ifp = _whd_emac.ifp;
     interal_scan_data.scan_in_progress = true;
     interal_scan_data.result_buff = new std::vector<whd_scan_result_t>();
     whd_result_t whd_res;
@@ -400,12 +398,8 @@ int WhdSTAInterface::scan(WiFiAccessPoint *aps, unsigned count)
     if (whd_res != WHD_SUCCESS) {
         res = whd_toerror(whd_res);
     } else {
-        int tok = interal_scan_data.sema->wait();
-        if (tok < 1) {
-            res = NSAPI_ERROR_WOULD_BLOCK;
-        } else {
-            res = interal_scan_data.offset;
-        }
+        interal_scan_data.sema->acquire();
+        res = interal_scan_data.offset;
     }
 
     delete interal_scan_data.sema;
@@ -415,6 +409,9 @@ int WhdSTAInterface::scan(WiFiAccessPoint *aps, unsigned count)
 
 int WhdSTAInterface::is_interface_connected(void)
 {
+    if (!_whd_emac.ifp) {
+        return WHD_INTERFACE_NOT_UP;
+    }
     _whd_emac.ifp->role = WHD_STA_ROLE;
     if ((whd_wifi_is_ready_to_transceive(_whd_emac.ifp) == WHD_SUCCESS)) {
         return WHD_SUCCESS;
@@ -489,6 +486,13 @@ int WhdSTAInterface::wifi_set_ioctl_value(uint32_t ioctl, uint32_t value)
     return res;
 }
 
+int WhdSTAInterface::wifi_get_ifp(whd_interface_t *ifp)
+{
+    int res = WHD_SUCCESS;
+    *ifp = _whd_emac.ifp;
+    return res;
+}
+
 int WhdSTAInterface::wifi_set_up(void)
 {
     int res = WHD_SUCCESS;
@@ -502,3 +506,10 @@ int WhdSTAInterface::wifi_set_down(void)
     res = whd_wifi_set_down(_whd_emac.ifp);
     return res;
 }
+
+int WhdSTAInterface::wifi_set_coex_config(whd_coex_config_t *coex_config)
+{
+    int res = WHD_SUCCESS;
+    res = whd_wifi_set_coex_config(_whd_emac.ifp, coex_config);
+    return res;
+}

features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSTAInterface.h

@@ -161,12 +161,18 @@ public:
     /* set ioctl value */
     int wifi_set_ioctl_value(uint32_t ioctl, uint32_t value) ;
 
+    /* get WHD ifp value */
+    int wifi_get_ifp(whd_interface_t *ifp);
+
     /* set wifi interface up */
     int wifi_set_up(void);
 
     /* set wifi interface down */
     int wifi_set_down(void);
 
+    /* set wifi coex configuration */
+    int wifi_set_coex_config(whd_coex_config_t *coex_config);
+
     /** Set Offload Manager Information
      *  NOTE: Only allowed while disconnected
      *
@@ -211,5 +217,4 @@ private:
     OlmInterface *_olm;
 };
 
-extern int wiced_leave_ap(int interface);
 #endif

features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSoftAPInterface.cpp

@@ -1,5 +1,5 @@
-/* Wiced implementation of NetworkInterfaceAPI
- * Copyright (c) 2017-2019 ARM Limited
+/*
+ * Copyright (c) 2018-2019 ARM Limited
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -15,6 +15,7 @@
  * limitations under the License.
  */
 
+
 #include "nsapi.h"
 #include "lwipopts.h"
 #include "WhdSoftAPInterface.h"
@@ -29,11 +30,33 @@
 extern int whd_toerror(whd_result_t res);
 extern nsapi_security_t whd_tosecurity(whd_security_t sec);
 extern whd_security_t whd_fromsecurity(nsapi_security_t sec);
-extern "C" void whd_emac_wifi_link_state_changed(bool state_up, whd_interface_t ifp);
+extern "C" void whd_emac_wifi_link_state_changed(whd_interface_t ifp, whd_bool_t state_up);
 
+static const whd_event_num_t ap_events[] = { WLC_E_LINK, WLC_E_IF, WLC_E_DEAUTH, WLC_E_DEAUTH_IND, WLC_E_DISASSOC, WLC_E_DISASSOC_IND, WLC_E_ASSOC_IND, WLC_E_REASSOC_IND, WLC_E_NONE };
+
+static void *whd_default_handle_softap_events(whd_interface_t ifp, const whd_event_header_t *event_header,
+                                              const uint8_t *event_data, void *handler_user_data)
+{
+    whd_driver_t whd_driver = ifp->whd_driver;
+
+    UNUSED_PARAMETER(event_header);
+    UNUSED_PARAMETER(event_data);
+    UNUSED_PARAMETER(handler_user_data);
+
+    WHD_IOCTL_LOG_ADD_EVENT(whd_driver, event_header->event_type, event_header->flags, event_header->reason);
+
+    if ((event_header->event_type == (whd_event_num_t)WLC_E_LINK) ||
+            (event_header->event_type == WLC_E_IF)) {
+        if (osSemaphoreGetCount(whd_driver->ap_info.whd_wifi_sleep_flag) < 1) {
+            osStatus_t result = osSemaphoreRelease(whd_driver->ap_info.whd_wifi_sleep_flag);
+            if (result != osOK) {
+                printf("Release whd_wifi_sleep_flag ERROR: %d", result);
+            }
+        }
+    }
+    return handler_user_data;
+}
 
-static const whd_event_num_t ap_client_events[] = { WLC_E_DEAUTH, WLC_E_DEAUTH_IND, WLC_E_DISASSOC, WLC_E_DISASSOC_IND, WLC_E_ASSOC_IND, WLC_E_REASSOC_IND, WLC_E_NONE };
-static uint16_t ap_event_entry = 2;
 
 WhdSoftAPInterface::WhdSoftAPInterface(WHD_EMAC &emac, OnboardNetworkStack &stack)
     : EMACInterface(emac, stack),
@@ -44,18 +67,24 @@ WhdSoftAPInterface::WhdSoftAPInterface(WHD_EMAC &emac, OnboardNetworkStack &stac
 
 
 int WhdSoftAPInterface::start(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel,
-                              bool start_dhcp_server, const whd_custom_ie_info_t *ie_info)
+                              bool start_dhcp_server, const whd_custom_ie_info_t *ie_info, bool ap_sta_concur)
 {
     nsapi_error_t        err;
 
-    /* set up our interface */
-    if (!_interface) {
-        nsapi_error_t err = _stack.add_ethernet_interface(_emac, true, &_interface);
-        if (err != NSAPI_ERROR_OK) {
-            _interface = NULL;
-            return err;
+    // power up primary emac interface first
+    if (ap_sta_concur) {
+        WHD_EMAC &emac_prime = WHD_EMAC::get_instance(WHD_STA_ROLE);
+        if (!emac_prime.power_up()) {
+            printf("Primary interface power up ERROR!\n");
+            return NSAPI_ERROR_DEVICE_ERROR;
         }
-        _interface->attach(_connection_status_cb);
+    }
+
+    // set concurrency mode and power up secondary, the bsp init is done by primary emac
+    _whd_emac.ap_sta_concur = ap_sta_concur;
+    if (!_whd_emac.power_up()) {
+        printf("Secondary interface power up ERROR!\n");
+        return NSAPI_ERROR_DEVICE_ERROR;
     }
 
     // setup ssid
@@ -75,6 +104,27 @@ int WhdSoftAPInterface::start(const char *ssid, const char *pass, nsapi_security
         return err;
     }
 
+    // update default softap interface event handler
+    err = unregister_event_handler();
+    if (err != NSAPI_ERROR_OK) {
+        printf("unregister_event_handler() ERROR: %d\n", err);
+        return err;
+    }
+    err = register_event_handler(whd_default_handle_softap_events);
+    if (err != NSAPI_ERROR_OK) {
+        printf("register_event_handler() ERROR: %d\n", err);
+        return err;
+    }
+
+    if (!_interface) {
+        nsapi_error_t err = _stack.add_ethernet_interface(_whd_emac, true, &_interface);
+        if (err != NSAPI_ERROR_OK) {
+            _interface = NULL;
+            return err;
+        }
+        _interface->attach(_connection_status_cb);
+    }
+
     if (ie_info) {
         err = whd_wifi_manage_custom_ie(_whd_emac.ifp, WHD_ADD_CUSTOM_IE, (const uint8_t *)ie_info->oui,
                                         ie_info->subtype, (const void *)ie_info->data, ie_info->length, ie_info->which_packets);
@@ -94,10 +144,9 @@ int WhdSoftAPInterface::start(const char *ssid, const char *pass, nsapi_security
     set_dhcp(false);
 
     if (whd_wifi_is_ready_to_transceive(_whd_emac.ifp) == WHD_SUCCESS) {
-        whd_emac_wifi_link_state_changed(true, _whd_emac.ifp);
+        whd_emac_wifi_link_state_changed(_whd_emac.ifp, WHD_TRUE);
     }
 
-    // bring up
     err = _interface->bringup(_dhcp,
                               _ip_address[0] ? _ip_address : 0,
                               _netmask[0] ? _netmask : 0,
@@ -106,6 +155,13 @@ int WhdSoftAPInterface::start(const char *ssid, const char *pass, nsapi_security
     if (err != NSAPI_ERROR_OK) {
         printf("bringup() ERROR: %d\n", err);
     }
+
+    if (start_dhcp_server) {
+        _dhcp_server = std::make_unique<CyDhcpServer>(get_stack(), this);
+        if (CY_RSLT_SUCCESS != _dhcp_server->start()) {
+            err = NSAPI_ERROR_DHCP_FAILURE;
+        }
+    }
     return err;
 }
 
@@ -113,6 +169,10 @@ int WhdSoftAPInterface::start(const char *ssid, const char *pass, nsapi_security
 
 int WhdSoftAPInterface::stop(void)
 {
+    if (_dhcp_server && CY_RSLT_SUCCESS != _dhcp_server->stop()) {
+        return NSAPI_ERROR_DHCP_FAILURE;
+    }
+    _dhcp_server.reset();
     return whd_wifi_stop_ap(_whd_emac.ifp);
 }
 
@@ -130,10 +190,11 @@ int WhdSoftAPInterface::get_associated_client_list(void *client_list_buffer, uin
 
 int WhdSoftAPInterface::register_event_handler(whd_event_handler_t softap_event_handler)
 {
-    return whd_management_set_event_handler(_whd_emac.ifp, ap_client_events, softap_event_handler, NULL, &ap_event_entry);
+    uint16_t ap_events_entry = _whd_emac.ifp->event_reg_list[WHD_AP_EVENT_ENTRY];
+    return whd_management_set_event_handler(_whd_emac.ifp, ap_events, softap_event_handler, NULL, &ap_events_entry);
 }
 
 int WhdSoftAPInterface::unregister_event_handler(void)
 {
-    return whd_wifi_deregister_event_handler(_whd_emac.ifp, ap_event_entry);
+    return whd_wifi_deregister_event_handler(_whd_emac.ifp, _whd_emac.ifp->event_reg_list[WHD_AP_EVENT_ENTRY]);
 }

features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSoftAPInterface.h

@@ -1,5 +1,5 @@
-/* WHD SoftAP implementation of SoftAPInterface
- * Copyright (c) 2017-2019 ARM Limited
+/*
+ * Copyright (c) 2018-2019 ARM Limited
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -15,13 +15,15 @@
  * limitations under the License.
  */
 
+
 #ifndef WHD_SOFTAP_INTERFACE_H
 #define WHD_SOFTAP_INTERFACE_H
 
 #include "netsocket/EMACInterface.h"
 #include "netsocket/OnboardNetworkStack.h"
 #include "whd_emac.h"
-
+#include "CyDhcpServer.h"
+#include <memory>
 
 /**
  * Vendor IE details
@@ -70,14 +72,15 @@ public:
      *  @param pass                 Security passphrase for connection to SoftAP
      *  @param security             Type of encryption for connection
      *  @param channel              Channel for SoftAP
-     *  @param start_dhcp_server    start dhcp server for connection
-     *  @param[in]          Optional Custom IE
+     *  @param start_dhcp_server    Start dhcp server for connection
+     *  @param whd_custom_ie        Optional Custom IE
+     *  @param ap_sta_concur        Enable STA+AP concurrency mode
      *
      *  @return          0 on success, or error code on failure
      *                  see @a nsapi_error
      */
     int start(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel,
-              bool start_dhcp_server = true, const whd_custom_ie_info_t *ie_info = NULL);
+              bool start_dhcp_server = true, const whd_custom_ie_info_t *ie_info = NULL, bool ap_sta_concur = false);
 
     /**
      * Remove Wi-Fi custom IE
@@ -131,6 +134,7 @@ public:
 
 protected:
     WHD_EMAC &_whd_emac;
+    std::unique_ptr<CyDhcpServer> _dhcp_server;
 };
 
 #endif

features/netsocket/emac-drivers/TARGET_WHD/interface/whd_emac.cpp

@@ -27,34 +27,35 @@
 #include "mbed_shared_queues.h"
 #include "whd_wlioctl.h"
 #include "whd_buffer_api.h"
-#include "cybsp_api_wifi.h"
+#include "cybsp_wifi.h"
 #include "emac_eapol.h"
 #include "cy_result.h"
 
+#define NULL_MAC(a)  ( ( ( ( (unsigned char *)a )[0] ) == 0 ) && \
+                       ( ( ( (unsigned char *)a )[1] ) == 0 ) && \
+                       ( ( ( (unsigned char *)a )[2] ) == 0 ) && \
+                       ( ( ( (unsigned char *)a )[3] ) == 0 ) && \
+                       ( ( ( (unsigned char *)a )[4] ) == 0 ) && \
+                       ( ( ( (unsigned char *)a )[5] ) == 0 ) )
+
 extern "C"
 {
     eapol_packet_handler_t emac_eapol_packet_handler = NULL;
+    void whd_emac_wifi_link_state_changed(whd_interface_t ifp, whd_bool_t state_up);
 } // extern "C"
 
-WHD_EMAC::WHD_EMAC(whd_interface_role_t role)
+WHD_EMAC::WHD_EMAC(whd_interface_role_t role, const uint8_t *mac_addr)
     : interface_type(role)
 {
+    if (mac_addr) {
+        set_hwaddr(mac_addr);
+    }
 }
 
-WHD_EMAC::WHD_EMAC()
-    : interface_type(WHD_STA_ROLE)
+WHD_EMAC &WHD_EMAC::get_instance(whd_interface_role_t role, const uint8_t *mac_addr)
 {
-}
-
-WHD_EMAC &WHD_EMAC::get_instance()
-{
-    return get_instance(WHD_STA_ROLE);
-}
-
-WHD_EMAC &WHD_EMAC::get_instance(whd_interface_role_t role)
-{
-    static WHD_EMAC emac_sta(WHD_STA_ROLE);
-    static WHD_EMAC emac_ap(WHD_AP_ROLE);
+    static WHD_EMAC emac_sta(WHD_STA_ROLE, mac_addr);
+    static WHD_EMAC emac_ap(WHD_AP_ROLE, mac_addr);
     return role == WHD_AP_ROLE ? emac_ap : emac_sta;
 }
 
@@ -96,33 +97,51 @@ void WHD_EMAC::power_down()
 bool WHD_EMAC::power_up()
 {
     if (!powered_up) {
-        if (CY_RSLT_SUCCESS != cybsp_wifi_init()) {
-            return false;
+        cy_rslt_t res = CY_RSLT_SUCCESS;
+        if (ap_sta_concur && interface_type == WHD_AP_ROLE) {
+            WHD_EMAC &emac_prime = WHD_EMAC::get_instance(WHD_STA_ROLE);
+            if (NULL_MAC(unicast_addr.octet)) {
+                emac_prime.get_hwaddr(unicast_addr.octet);
+                // Generated mac will set locally administered bit 1 of first byte
+                unicast_addr.octet[0] |= (1 << 1);
+            }
+            // Note: This assumes that the primary interface initializes the
+            // wifi driver and turns on the wifi chip.
+            res = cybsp_wifi_init_secondary(&ifp /* Out */, &unicast_addr);
+        } else {
+            res = cybsp_wifi_init_primary(&ifp /* OUT */);
         }
-        drvp = *(cybsp_get_wifi_driver());
-        if (WHD_SUCCESS != whd_wifi_on(drvp, &ifp /* OUT */)) {
+
+        if (CY_RSLT_SUCCESS == res) {
+            drvp = cybsp_get_wifi_driver();
+            powered_up = true;
+            ifp->whd_link_update_callback = whd_emac_wifi_link_state_changed;
+            if (link_state && emac_link_state_cb) {
+                emac_link_state_cb(link_state);
+            }
+        } else {
             return false;
         }
-        powered_up = true;
-        if (link_state && emac_link_state_cb) {
-            emac_link_state_cb(link_state);
-        }
     }
     return true;
 }
 
 bool WHD_EMAC::get_hwaddr(uint8_t *addr) const
 {
-    whd_mac_t mac;
-    whd_result_t res = whd_wifi_get_mac_address(ifp, &mac);
-    MBED_ASSERT(res == WHD_SUCCESS);
-    memcpy(addr, mac.octet, sizeof(mac.octet));
+    if (!NULL_MAC(unicast_addr.octet)) {
+        memcpy(addr, unicast_addr.octet, sizeof(unicast_addr.octet));
+    } else {
+        whd_mac_t mac;
+        whd_result_t res = whd_wifi_get_mac_address(ifp, &mac);
+        MBED_ASSERT(res == WHD_SUCCESS);
+        memcpy(addr, mac.octet, sizeof(mac.octet));
+    }
     return true;
 }
 
 void WHD_EMAC::set_hwaddr(const uint8_t *addr)
 {
-    /* No-op at this stage */
+    memcpy(unicast_addr.octet, addr, sizeof(unicast_addr.octet));
 }
 
 uint8_t WHD_EMAC::get_hwaddr_size() const
@@ -175,7 +194,16 @@ bool WHD_EMAC::link_out(emac_mem_buf_t *buf)
 
 void WHD_EMAC::get_ifname(char *name, uint8_t size) const
 {
-    memcpy(name, "whd", size);
+    switch (interface_type) {
+        case WHD_STA_ROLE:
+            memcpy(name, "st", size);
+            break;
+        case WHD_AP_ROLE:
+            memcpy(name, "ap", size);
+            break;
+        default:
+            memcpy(name, "wh", size);
+    }
 }
 
 void WHD_EMAC::set_activity_cb(mbed::Callback<void(bool)> cb)
@@ -252,7 +280,7 @@ extern "C"
         }
     }
 
-    void whd_emac_wifi_link_state_changed(bool state_up, whd_interface_t ifp)
+    void whd_emac_wifi_link_state_changed(whd_interface_t ifp, whd_bool_t state_up)
     {
         WHD_EMAC &emac = WHD_EMAC::get_instance(ifp->role);
 

features/netsocket/emac-drivers/TARGET_WHD/interface/whd_emac.h

@@ -28,12 +28,9 @@
 
 class WHD_EMAC : public EMAC {
 public:
-    WHD_EMAC();
-    WHD_EMAC(whd_interface_role_t itype);
+    WHD_EMAC(whd_interface_role_t itype = WHD_STA_ROLE, const uint8_t *mac_addr = NULL);
 
-    static WHD_EMAC &get_instance();
-
-    static WHD_EMAC &get_instance(whd_interface_role_t role);
+    static WHD_EMAC &get_instance(whd_interface_role_t role = WHD_STA_ROLE, const uint8_t *mac_addr = NULL);
 
     /**
      * Return maximum transmission unit
@@ -167,16 +164,13 @@ public:
     EMACMemoryManager *memory_manager;
     bool powered_up = false;
     bool link_state = false;
+    bool ap_sta_concur = false;
     whd_interface_role_t interface_type;
     whd_driver_t drvp = NULL;
     whd_interface_t ifp = NULL;
+    whd_mac_t unicast_addr;
     whd_mac_t multicast_addr;
-    struct whd_resource_source *resource_ops = NULL;
-    whd_buffer_funcs_t *buffer_ops = NULL;
-    whd_netif_funcs_t *netif_ops = NULL;
-    whd_init_config_t *whd_init_config = NULL;
     mbed::Callback<void(bool)> activity_cb;
-
 };
 
 #endif /* WHD_EMAC_H_ */

features/netsocket/emac-drivers/TARGET_WHD/utils/cydhcp_server_debug.cpp

@@ -0,0 +1,405 @@
+#include "CyDhcpServer.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+typedef struct DHCP_options_table_s {
+    uint8_t     code;
+    uint32_t    length;         /* 0x80000000 means variable */
+    const char   *name;
+} dhcp_options_table_t;
+
+static dhcp_options_table_t dhcp_options_lookup_table[] = {
+    {  0,   0,  "Pad" },
+    {  1,   4,  "Subnet Mask" },
+    {  2,   4,  "Time Offset" },
+    {  3,   0,  "Router" },
+    {  4,   0,  "Time Server" },
+    {  5,   0,  "Name Server" },
+    {  6,   0,  "Domain Server" },
+    {  7,   0,  "Log Server" },
+    {  8,   0,  "Quotes Server" },
+    {  9,   0,  "LPR Server" },
+    { 10,   0,  "Impress Server" },
+    { 11,   0,  "RLP Server" },
+    { 12,   0,  "Hostname" },
+    { 13,   2,  "Boot File Size" },
+    { 14,   0,  "Merit Dump File" },
+    { 15,   0,  "Domain Name" },
+    { 16,   0,  "Swap Server" },
+    { 17,   0,  "Root Path" },
+    { 18,   0,  "Extension File" },
+    { 19,   1,  "Forward On/Off" },
+    { 20,   1,  "SrcRte On/Off" },
+    { 21,   0,  "Policy Filter" },
+    { 22,   2,  "Max DG Assembly" },
+    { 23,   1,  "Default IP TTL" },
+    { 24,   4,  "MTU Timeout" },
+    { 25,   0,  "MTU Plateau" },
+    { 26,   2,  "MTU Interface" },
+    { 27,   1,  "MTU Subnet" },
+    { 28,   4,  "Broadcast Address" },
+    { 29,   1,  "Mask Discovery" },
+    { 30,   1,  "Mask Supplier" },
+    { 31,   1,  "Router Discovery" },
+    { 32,   4,  "Router Request" },
+    { 33,   0,  "Static Route" },
+    { 34,   1,  "Trailers" },
+    { 35,   4,  "ARP Timeout" },
+    { 36,   1,  "Ethernet" },
+    { 37,   1,  "Default TCP TTL" },
+    { 38,   4,  "Keepalive Time" },
+    { 39,   1,  "Keepalive Data" },
+    { 40,   0,  "NIS Domain" },
+    { 41,   0,  "NIS Servers" },
+    { 42,   0,  "NTP Servers" },
+    { 43,   0,  "Vendor Specific" },
+    { 44,   0,  "NETBIOS Name Srv" },
+    { 45,   0,  "NETBIOS Dist Srv" },
+    { 46,   1,  "NETBIOS Node Type" },
+    { 47,   0,  "NETBIOS Scope" },
+    { 48,   0,  "X Window Font" },
+    { 49,   0,  "X Window Manager" },
+    { 50,   4,  "Address Request" },
+    { 51,   4,  "Address Time" },
+    { 52,   1,  "Overload" },
+    { 53,   1,  "DHCP Msg Type" },
+    { 54,   4,  "DHCP Server Id" },
+    { 55,   0,  "Parameter List" },
+    { 56,   0,  "DHCP Message" },
+    { 57,   2,  "DHCP Max Msg Size" },
+    { 58,   4,  "Renewal Time" },
+    { 59,   4,  "Rebinding Time" },
+    { 60,   0,  "Class Id" },
+    { 61,   0,  "Client Id" },
+    { 62,   0,  "NetWare/IP Domain" },
+    { 63,   0,  "NetWare/IP Option" },
+    { 64,   0,  "NIS-Domain-Name" },
+    { 65,   0,  "NIS-Server-Addr" },
+    { 66,   0,  "Server-Name" },
+    { 67,   0,  "Bootfile-Name" },
+    { 68,   0,  "Home-Agent-Addrs" },
+    { 69,   0,  "SMTP-Server" },
+    { 70,   0,  "POP3-Server" },
+    { 71,   0,  "NNTP-Server" },
+    { 72,   0,  "WWW-Server" },
+    { 73,   0,  "Finger-Server" },
+    { 74,   0,  "IRC-Server" },
+    { 75,   0,  "StreetTalk-Server" },
+    { 76,   0,  "STDA-Server" },
+    { 77,   0,  "User-Class" },
+    { 78,   0,  "Directory Agent" },
+    { 79,   0,  "Service Scope" },
+    { 80,   0,  "Rapid Commit" },
+    { 81,   0,  "Client FQDN" },
+    { 82,   0,  "Relay Agent Information" },
+    { 83,   0,  "iSNS" },
+    { 85,   0,  "NDS Servers" },
+    { 86,   0,  "NDS Tree Name" },
+    { 87,   0,  "NDS Context" },
+    { 88,   0x80000000, "BCMCS Controller Domain Name list" },
+    { 89,   0x80000000, "BCMCS Controller IPv4 address option" },
+    { 90,   0,  "Authentication" },
+    { 91,   0x80000000, "client-last-transaction-time option" },
+    { 92,   0x80000000, "associated-ip option" },
+    { 93,   0,  "Client System" },
+    { 94,   0,  "Client NDI" },
+    { 95,   0,  "LDAP" },
+    { 97,   0,  "UUID/GUID" },
+    { 98,   0,  "User-Auth" },
+    { 99,   0x80000000, "GEOCONF_CIVIC" },
+    {100,   0,  "PCode" },
+    {101,   0,  "TCode" },
+    {109,   16, "OPTION_DHCP4O6_S46_SADDR" },
+    {112,   0,  "Netinfo Address" },
+    {113,   0,  "Netinfo Tag" },
+    {114,   0,  "URL" },
+    {116,   0,  "Auto-Config" },
+    {117,   0,  "Name Service Search" },
+    {118,   4,  "Subnet Selection Option" },
+    {119,   0,  "Domain Search" },
+    {120,   0,  "SIP Servers DHCP Option" },
+    {121,   0,  "Classless Static Route Option" },
+    {122,   0,  "CCC" },
+    {123,   16, "GeoConf Option" },
+    {124,   0,  "V-I Vendor Class" },
+    {125,   0,  "V-I Vendor-Specific Information" },
+    {128,   0,  "Etherboot signature. 6 bytes: E4:45:74:68:00:00" },
+    {129,   4,  "Call Server IP address" },
+    {130,   0x80000000, "Ethernet interface. Variable" },
+    {131,   0,  "Remote statistics server IP address" },
+    {132,   0,  "IEEE 802.1Q VLAN ID" },
+    {133,   0,  "IEEE 802.1D/p Layer 2 Priority" },
+    {134,   0,  "Diffserv Code Point (DSCP) for" },
+    {135,   0,  "HTTP Proxy for phone-specific" },
+    {136,   0,  "OPTION_PANA_AGENT" },
+    {137,   0,  "OPTION_V4_LOST" },
+    {138,   0,  "OPTION_CAPWAP_AC_V4" },
+    {139,   0,  "OPTION-IPv4_Address-MoS" },
+    {140,   0,  "OPTION-IPv4_FQDN-MoS" },
+    {141,   0,  "SIP UA Configuration Service Domains" },
+    {142,   0,  "OPTION-IPv4_Address-ANDSF" },
+    {143,   0,  "OPTION_V4_SZTP_REDIRECT" },
+    {144,   16, "GeoLoc" },
+    {145,   1,  "FORCERENEW_NONCE_CAPABLE" },
+    {146,   0,  "RDNSS Selection" },
+    {151,   0x80000000, "N+1	status-code" },
+    {152,   4,  "base-time" },
+    {153,   4,  "start-time-of-state" },
+    {154,   4,  "query-start-time" },
+    {155,   4,  "query-end-time" },
+    {156,   1,  "dhcp-state" },
+    {157,   1,  "data-source" },
+    {158,   0x80000000, " Variable; the minimum length is 5. OPTION_V4_PCP_SERVER" },
+    {159,   4,  "OPTION_V4_PORTPARAMS" },
+    {160,   0,  "DHCP Captive-Portal" },
+    {161,   0x80000000, "(variable) OPTION_MUD_URL_V4" },
+    {208,   4,  "PXELINUX Magic" },
+    {209,   0,  "Configuration File" },
+    {210,   0,  "Path Prefix" },
+    {211,   4,  "Reboot Time" },
+    {212,   0x80000000, "18+ N	OPTION_6RD" },
+    {213,   0,  "OPTION_V4_ACCESS_DOMAIN" },
+    {220,   0,  "Subnet Allocation Option" },
+};
+
+#define isprint(c)   ((c) >= 0x20 && (c) < 0x7f)
+int hex_dump_print(const void *data_ptr, uint16_t length, int show_ascii)
+{
+    uint8_t *data = (uint8_t *)data_ptr;
+    uint8_t *char_ptr;
+    int i, count;
+    if ((data == NULL) || (length == 0)) {
+        return -1;
+    }
+    count = 0;
+    char_ptr = data;
+    while (length > 0) {
+        i = 0;
+        while ((length > 0) && (i < 16)) {
+            printf(" %02x", *data);
+            i++;
+            data++;
+            length--;
+            count++;
+        }
+
+        if (show_ascii != 0) {
+            int fill = 16 - i;
+            /* fill in for < 16 */
+            while (fill > 0) {
+                printf("   ");
+                fill--;
+            }
+            /* space between numbers and chars */
+            printf("    ");
+            while (i > 0) {
+                printf("%c", (isprint(*char_ptr) ? *char_ptr : '.'));
+                char_ptr++;
+                i--;
+            }
+        }
+        printf("\n");
+    }
+    return count;
+}
+
+
+void dhcp_server_print_header_info(dhcp_packet_t *header, uint32_t datalen, const char *title)
+{
+    uint8_t *ptr;
+    if (title != NULL) {
+        printf("%s:\n", title);
+    }
+
+    printf("Opcode         :%2d    : %s\n", header->Opcode, (header->Opcode == 1) ? "Request" : (header->Opcode == 2) ? "Reply" : "Unknown");
+    printf("HwType         :%2d    : %s\n", header->HwType, (header->HwType == 1) ? "Ethernet" : "Unknown");
+    printf("HwLength       :      : %d\n", header->HwLen);
+    printf("Hops           :      : %d\n", header->Hops);
+    printf("TransactionId  :      : 0x%lx\n", header->TransactionId);
+    printf("Elapsed time   :      : %d\n", header->SecsElapsed);
+    printf("Flags          :      : 0x%08x\n", header->Flags);
+    uint8_t *ip_ptr = (uint8_t *)&header->ClientIpAddr;
+    printf("from client IP :      : %d.%d.%d.%d\n", ip_ptr[0], ip_ptr[1], ip_ptr[2], ip_ptr[3]);
+    ip_ptr = (uint8_t *)&header->YourIpAddr;
+    printf("from us YOUR IP:      : %d.%d.%d.%d\n", ip_ptr[0], ip_ptr[1], ip_ptr[2], ip_ptr[3]);
+    ip_ptr = (uint8_t *)&header->ServerIpAddr;
+    printf("DHCP server IP :      : %d.%d.%d.%d\n", ip_ptr[0], ip_ptr[1], ip_ptr[2], ip_ptr[3]);
+    ip_ptr = (uint8_t *)&header->GatewayIpAddr;
+    printf("gateway IP     :      : %d.%d.%d.%d\n", ip_ptr[0], ip_ptr[1], ip_ptr[2], ip_ptr[3]);
+
+    printf("Client MAC     :      :");
+    hex_dump_print(header->ClientHwAddr, 16, 0);
+    ip_ptr = (uint8_t *)&header->MagicCookie;
+    printf("Magic          :      : %2x %2x %2x %2x\n", ip_ptr[0], ip_ptr[1], ip_ptr[2], ip_ptr[3]);
+
+    printf("Options        :\n");
+    ptr = (uint8_t *)header->Options;
+    printf("Hex Dump:\n");
+    hex_dump_print(ptr, 64, 1);
+    printf("\n");
+
+    while ((ptr != NULL) && (*ptr != DHCP_END_OPTION_CODE) && ((uint32_t)(ptr - &header->Options[0]) < datalen)) {
+        int len;
+        switch (*ptr) {
+            case DHCP_SUBNETMASK_OPTION_CODE:           // (1)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d  SUBNET MASK : ", DHCP_SUBNETMASK_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 1);
+                ptr += len;
+                break;
+            case DHCP_ROUTER_OPTION_CODE:               // (3)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d  ROUTER : ", DHCP_ROUTER_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 0);
+                ptr += len;
+                break;
+            case DHCP_DNS_SERVER_OPTION_CODE:           // (6)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d  DNS SERVER : ", DHCP_DNS_SERVER_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 0);
+                ptr += len;
+                break;
+            case DHCP_HOST_NAME_OPTION_CODE:
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d  HOST NAME : ", DHCP_HOST_NAME_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 1);
+                ptr += len;
+                break;
+            case DHCP_MTU_OPTION_CODE:                  // (26)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d  MTU : ", DHCP_MTU_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 0);
+                ptr += len;
+                break;
+            case DHCP_REQUESTED_IP_ADDRESS_OPTION_CODE: // (50)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d  REQUESTED IP : ", DHCP_REQUESTED_IP_ADDRESS_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 0);
+                ptr += len;
+                break;
+            case DHCP_LEASETIME_OPTION_CODE:            // (51)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d   LEASE TIME : ", DHCP_LEASETIME_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 0);
+                ptr += len;
+                break;
+            case DHCP_MESSAGETYPE_OPTION_CODE: {        // (53)
+                ptr++;
+                len = *ptr++;
+                int code = *ptr;
+                printf(" Code:%d Length:%d  MESSAGE : ", DHCP_MESSAGETYPE_OPTION_CODE, len);
+                switch (code) {
+                    case 1:
+                        printf("  %d -- DHCP DISCOVER\n", code);
+                        break;
+                    case 2:
+                        printf("  %d -- DHCP OFFER\n", code);
+                        break;
+                    case 3:
+                        printf("  %d -- DHCP REQUEST\n", code);
+                        break;
+                    case 4:
+                        printf("  %d -- DHCP DECLINE\n", code);
+                        break;
+                    case 5:
+                        printf("  %d -- DHCP ACK\n", code);
+                        break;
+                    case 6:
+                        printf("  %d -- DHCP NACK\n", code);
+                        break;
+                    case 7:
+                        printf("  %d -- DHCP RELEASE\n", code);
+                        break;
+                    case 8:
+                        printf("  %d -- DHCP INFORM\n", code);
+                        break;
+                    default:
+                        printf("  %d -- INVALID\n", code);
+                        break;
+                }
+                ptr += len;
+                break;
+            }
+            case DHCP_SERVER_IDENTIFIER_OPTION_CODE:    // (54)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d  SERVER ID : ", DHCP_SERVER_IDENTIFIER_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 0);
+                ptr += len;
+                break;
+            case DHCP_PARAM_REQUEST_LIST_OPTION_CODE:
+//          9.8. Parameter Request List
+//
+//             This option is used by a DHCP client to request values for specified
+//             configuration parameters.  The list of requested parameters is
+//             specified as n octets, where each octet is a valid DHCP option code
+//             as defined in this document.
+//
+//             The client MAY list the options in order of preference.  The DHCP
+//             server is not required to return the options in the requested order,
+//             but MUST try to insert the requested options in the order requested
+//             by the client.
+//
+//             The code for this option is 55.  Its minimum length is 1.
+//
+//              Code   Len   Option Codes
+//             +-----+-----+-----+-----+---
+//             |  55 |  n  |  c1 |  c2 | ...
+//             +-----+-----+-----+-----+---
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d    PARAM REQ : ", DHCP_PARAM_REQUEST_LIST_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 0);
+                {
+                    int i;
+                    for (i = 0; i < len; i++) {
+                        uint8_t sub_code;
+                        sub_code = *ptr++;
+
+                        uint32_t lookup_index;
+                        uint32_t max_lookup = (sizeof(dhcp_options_lookup_table) / sizeof(dhcp_options_lookup_table[0]));
+                        for (lookup_index = 0; lookup_index < max_lookup; lookup_index++) {
+                            if (dhcp_options_lookup_table[lookup_index].code == sub_code) {
+                                uint32_t length = dhcp_options_lookup_table[lookup_index].length;
+                                if (length != 0) {
+                                    /* length is variable, in the length field ? */
+                                    length = *ptr;
+                                }
+                                printf("  Code:%3d : %s\n", dhcp_options_lookup_table[lookup_index].code, dhcp_options_lookup_table[lookup_index].name);
+                                break;
+                            }
+                        }
+                        if (lookup_index >= max_lookup) {
+                            printf("  Code:%3d : UNKNOWN\n", dhcp_options_lookup_table[lookup_index].code);
+                        }
+                    }
+                }
+                break;
+            case DHCP_WPAD_OPTION_CODE:                 // (252)
+                ptr++;
+                len = *ptr++;
+                printf(" Code:%d Length:%d WPAD : ", DHCP_WPAD_OPTION_CODE, len);
+                hex_dump_print(ptr, len, 1);
+                ptr += len;
+                break;
+
+            default:
+                ptr++;
+                break;
+        }
+    }
+}
+
+#if defined(__cplusplus)
+}
+#endif

features/netsocket/emac-drivers/TARGET_WHD/utils/cynetwork_utils.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cynetwork_utils.h"
+
+uint8_t unsigned_to_decimal_string(uint32_t value, char *output, uint8_t min_length, uint8_t max_length)
+{
+    uint8_t digits_left;
+    char buffer[] = "0000000000";
+
+    if (output == NULL) {
+        return 0;
+    }
+
+    max_length = (uint8_t) MIN(max_length, sizeof(buffer));
+    digits_left = max_length;
+    while ((value != 0) && (digits_left != 0)) {
+        --digits_left;
+        buffer[digits_left] = (char)((value % 10) + '0');
+        value = value / 10;
+    }
+
+    digits_left = (uint8_t) MIN((max_length - min_length), digits_left);
+    memcpy(output, &buffer[digits_left], (size_t)(max_length - digits_left));
+
+    /* Add terminating null */
+    output[(max_length - digits_left)] = '\x00';
+
+    return (uint8_t)(max_length - digits_left);
+}
+
+void ipv4_to_string(char buffer[16], uint32_t ipv4_address)
+{
+    uint8_t *ip = (uint8_t *)&ipv4_address;
+
+    /* unsigned_to_decimal_string() null-terminates the string
+     * Save the original last character and replace it */
+    char last_char = buffer[16];
+    unsigned_to_decimal_string(ip[0], &buffer[0], 3, 3);
+    buffer[3] = '.';
+    unsigned_to_decimal_string(ip[1], &buffer[4], 3, 3);
+    buffer[7] = '.';
+    unsigned_to_decimal_string(ip[2], &buffer[8], 3, 3);
+    buffer[11] = '.';
+    unsigned_to_decimal_string(ip[3], &buffer[12], 3, 3);
+    buffer[16] = last_char;
+}
+
+uint32_t string_to_ipv4(const char *buffer)
+{
+    uint32_t temp = 0;
+    int char_count = 0;
+    const char *ptr = buffer;
+
+    while ((ptr != NULL)  && (*ptr != 0) && (char_count++ < 16)) {
+        uint8_t byte = 0;
+        while ((*ptr != 0) && (*ptr != '.') && (char_count++ < 16)) {
+            byte *= 10;
+            if ((*ptr >= '0') && (*ptr <= '9')) {
+                byte += (*ptr - '0');
+            } else {
+                break;
+            }
+            ptr++;
+        }
+        temp <<= 8;
+        temp |= byte;
+        if (*ptr == '.') {
+            ptr++;  /* skip '.' */
+        }
+    }
+    return temp;
+}
+

features/netsocket/emac-drivers/TARGET_WHD/utils/cynetwork_utils.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifndef MIN
+extern int MIN(/*@sef@*/ int x, /*@sef@*/ int y);  /* LINT : This tells lint that  the parameter must be side-effect free. i.e. evaluation does not change any values (since it is being evaulated more than once */
+#define MIN(x,y) ((x) < (y) ? (x) : (y))
+#endif /* ifndef MIN */
+
+#define FX_IPTYPE_IPV4                  (0)
+#define FX_IPTYPE_IPV6                  (1)
+
+typedef union {
+    uint32_t addr;
+    uint8_t addrs[4];
+} cy_ip_addr_v4_t;
+
+typedef struct {
+    uint32_t addr[4];
+} cy_ip_addr_v6_t;
+
+typedef struct {
+    uint8_t type;
+    union {
+        cy_ip_addr_v4_t addrv4;
+        cy_ip_addr_v6_t addrv6;
+    };
+} cy_ip_addr_t;
+
+/**
+ * Structure for storing a MAC address (Wi-Fi Media Access Control address).
+ */
+typedef struct {
+    uint8_t octet[6]; /**< Unique 6-byte MAC address */
+} cy_mac_addr_t;
+
+/**
+ * Converts a unsigned long int to a decimal string
+ *
+ * @param value[in]      : The unsigned long to be converted
+ * @param output[out]    : The buffer which will receive the decimal string
+ * @param min_length[in] : the minimum number of characters to output (zero padding will apply if required).
+ * @param max_length[in] : the maximum number of characters to output (up to 10 ). There must be space for terminating NULL.
+ *
+ * @note: A terminating NULL is added. Wnsure that there is space in the buffer for this.
+ *
+ * @return the number of characters returned (excluding terminating null)
+ *
+ */
+uint8_t unsigned_to_decimal_string(uint32_t value, char *output, uint8_t min_length, uint8_t max_length);
+
+/**
+ *  Convert a IPv4 address to a string
+ *
+ *  @note: String is 16 bytes including terminating null
+ *
+ * @param[out] buffer       : Buffer which will recieve the IPv4 string
+ * @param[in]  ipv4_address : IPv4 address to convert
+ */
+void ipv4_to_string(char buffer[16], uint32_t ipv4_address);
+
+/**
+ *  Convert a IPv4 address to a string
+ *
+ *  @note: String is 16 bytes including terminating null
+ *
+ * @param[in] buffer         : Buffer which has the IPv4 string
+ * @return  ipv4_address (0 on failure)
+ */
+uint32_t string_to_ipv4(const char *buffer);
+
+#if defined(__cplusplus)
+}
+#endif

targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h

@@ -19,14 +19,83 @@
 #ifndef MBED_PINNAMESTYPES_H
 #define MBED_PINNAMESTYPES_H
 
-#include "cmsis.h"
 #include "cyhal_gpio.h"
+#include "cybsp_types.h"
 
+// Pin Modes
 #define PullNone CYHAL_GPIO_DRIVE_STRONG
-#define PullDefault CYHAL_GPIO_DRIVE_ANALOG
+#define PullDefault CYHAL_GPIO_DRIVE_NONE
 #define PullDown CYHAL_GPIO_DRIVE_PULLDOWN
 #define PullUp CYHAL_GPIO_DRIVE_PULLUP
 
+// Arduino Headers
+#ifdef CYBSP_A0
+#define A0 CYBSP_A0
+#endif
+#ifdef CYBSP_A1
+#define A1 CYBSP_A1
+#endif
+#ifdef CYBSP_A2
+#define A2 CYBSP_A2
+#endif
+#ifdef CYBSP_A3
+#define A3 CYBSP_A3
+#endif
+#ifdef CYBSP_A4
+#define A4 CYBSP_A4
+#endif
+#ifdef CYBSP_A5
+#define A5 CYBSP_A5
+#endif
+#ifdef CYBSP_D0
+#define D0 CYBSP_D0
+#endif
+#ifdef CYBSP_D1
+#define D1 CYBSP_D1
+#endif
+#ifdef CYBSP_D2
+#define D2 CYBSP_D2
+#endif
+#ifdef CYBSP_D3
+#define D3 CYBSP_D3
+#endif
+#ifdef CYBSP_D4
+#define D4 CYBSP_D4
+#endif
+#ifdef CYBSP_D5
+#define D5 CYBSP_D5
+#endif
+#ifdef CYBSP_D6
+#define D6 CYBSP_D6
+#endif
+#ifdef CYBSP_D7
+#define D7 CYBSP_D7
+#endif
+#ifdef CYBSP_D8
+#define D8 CYBSP_D8
+#endif
+#ifdef CYBSP_D9
+#define D9 CYBSP_D9
+#endif
+#ifdef CYBSP_D10
+#define D10 CYBSP_D10
+#endif
+#ifdef CYBSP_D11
+#define D11 CYBSP_D11
+#endif
+#ifdef CYBSP_D12
+#define D12 CYBSP_D12
+#endif
+#ifdef CYBSP_D13
+#define D13 CYBSP_D13
+#endif
+#ifdef CYBSP_D14
+#define D14 CYBSP_D14
+#endif
+#ifdef CYBSP_D15
+#define D15 CYBSP_D15
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -37,6 +106,11 @@ typedef enum {
 } PinDirection;
 
 typedef cyhal_gpio_drive_mode_t PinMode;
+typedef cyhal_gpio_t PinName;
+static inline PinName cyhal_gpio_to_rtos(cyhal_gpio_t pin)
+{
+    return pin;
+}
 
 #ifdef __cplusplus
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -1,8 +1,8 @@
 /*******************************************************************************
-* File Name: cycfg_clocks.c
+* File Name: cycfg.timestamp
 *
 * Description:
-* Clock configuration
+* Sentinel file for determining if generated source is up to date.
 * This file was automatically generated and should not be modified.
 * 
 ********************************************************************************
@@ -22,20 +22,3 @@
 * limitations under the License.
 ********************************************************************************/
 
-#include "cycfg_clocks.h"
-
-
-void init_cycfg_clocks(void)
-{
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -24,22 +24,52 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_BT_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
 
 void init_cycfg_clocks(void)
 {
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -27,14 +27,14 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
 #define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
 #define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
 #define CYBSP_BT_UART_CLK_DIV_NUM 1U
@@ -45,6 +45,16 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_clocks(void);
 
 #if defined(__cplusplus)

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -56,6 +56,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
 	.txFifoTriggerLevel = 63UL,
 	.txFifoIntEnableMask = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
 {
 	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -64,51 +72,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 12,
-	.enableMsbFirst = false,
-	.dataWidth = 9UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = true,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
-	.rtsRxFifoLevel = 63,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
-cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
-cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
-uint32_t CYBSP_RADIO_rca = 0u;
-const cy_stc_sd_host_init_config_t CYBSP_RADIO_config = 
-{
-	.emmc = false,
-	.dmaType = CY_SD_HOST_DMA_SDMA,
-	.enableLedControl = false,
-};
-cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg = 
-{
-	.lowVoltageSignaling = false,
-	.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
-	.cardType = &CYBSP_RADIO_cardType,
-	.rca = &CYBSP_RADIO_rca,
-	.cardCapacity = &CYBSP_RADIO_cardCapacity,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -116,6 +87,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT_config = 
 {
 	.c0Match = 32768U,
@@ -129,6 +108,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -141,6 +128,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
@@ -148,8 +143,24 @@ void init_cycfg_peripherals(void)
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -29,9 +29,12 @@
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_uart.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_scb_ezi2c.h"
-#include "cy_sd_host.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 
@@ -39,7 +42,7 @@
 extern "C" {
 #endif
 
-#define CYBSP_CAPSENSE_ENABLED 1U
+#define CYBSP_CSD_ENABLED 1U
 #define CY_CAPSENSE_CORE 4u
 #define CY_CAPSENSE_CPU_CLK 144000000u
 #define CY_CAPSENSE_PERI_CLK 72000000u
@@ -49,10 +52,10 @@ extern "C" {
 #define Cmod_PORT GPIO_PRT7
 #define CintA_PORT GPIO_PRT7
 #define CintB_PORT GPIO_PRT7
-#define Button0_Rx0_PORT GPIO_PRT8
-#define Button0_Tx_PORT GPIO_PRT1
-#define Button1_Rx0_PORT GPIO_PRT8
-#define Button1_Tx_PORT GPIO_PRT1
+#define Button0_Rx0_PORT GPIO_PRT1
+#define Button0_Tx_PORT GPIO_PRT8
+#define Button1_Rx0_PORT GPIO_PRT1
+#define Button1_Tx_PORT GPIO_PRT8
 #define LinearSlider0_Sns0_PORT GPIO_PRT8
 #define LinearSlider0_Sns1_PORT GPIO_PRT8
 #define LinearSlider0_Sns2_PORT GPIO_PRT8
@@ -61,10 +64,10 @@ extern "C" {
 #define Cmod_PIN 7u
 #define CintA_PIN 1u
 #define CintB_PIN 2u
-#define Button0_Rx0_PIN 1u
-#define Button0_Tx_PIN 0u
-#define Button1_Rx0_PIN 2u
-#define Button1_Tx_PIN 0u
+#define Button0_Rx0_PIN 0u
+#define Button0_Tx_PIN 1u
+#define Button1_Rx0_PIN 0u
+#define Button1_Tx_PIN 2u
 #define LinearSlider0_Sns0_PIN 3u
 #define LinearSlider0_Sns1_PIN 4u
 #define LinearSlider0_Sns2_PIN 5u
@@ -73,20 +76,14 @@ extern "C" {
 #define Cmod_PORT_NUM 7u
 #define CintA_PORT_NUM 7u
 #define CintB_PORT_NUM 7u
-#define CYBSP_CAPSENSE_HW CSD0
-#define CYBSP_CAPSENSE_IRQ csd_interrupt_IRQn
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
 #define CYBSP_BT_UART_ENABLED 1U
 #define CYBSP_BT_UART_HW SCB2
 #define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
 #define CYBSP_CSD_COMM_ENABLED 1U
 #define CYBSP_CSD_COMM_HW SCB3
 #define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
-#define CYBSP_RADIO_ENABLED 1U
-#define CYBSP_RADIO_HW SDHC0
-#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -119,16 +116,25 @@ extern "C" {
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
-extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
-extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
-extern uint32_t CYBSP_RADIO_rca;
-extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
-extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_SW2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_SW2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_G_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED5_RGB_G_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED9_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED9_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config = 
 {
 	.outVal = 1,
@@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = 
 {
 	.outVal = 1,
@@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = 
 {
 	.outVal = 1,
@@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = 
 {
 	.outVal = 1,
@@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = 
 {
 	.outVal = 1,
@@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = 
 {
 	.outVal = 1,
@@ -200,155 +208,19 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_R_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED5_RGB_R_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SW4_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_SW4_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED8_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED8_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CMD_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_CMD_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_CLK_HSIOM,
+	.hsiom = CYBSP_CSD_RX_HSIOM,
 	.intEdge = CY_GPIO_INTR_DISABLE,
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -360,6 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_RX_PORT_NUM,
+		.channel_num = CYBSP_CSD_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = 
 {
 	.outVal = 1,
@@ -376,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = 
 {
 	.outVal = 1,
@@ -392,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_TX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = 
 {
 	.outVal = 1,
@@ -408,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = 
 {
 	.outVal = 1,
@@ -424,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_CTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = 
 {
 	.outVal = 1,
@@ -440,22 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = 
-{
-	.outVal = 0,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_POWER_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_POWER_PORT_NUM,
+		.channel_num = CYBSP_BT_POWER_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = 
 {
 	.outVal = 0,
@@ -472,59 +376,19 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = 
 {
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RTS_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_RTS_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_CTS_HSIOM,
+	.outVal = 0,
+	.driveMode = CY_GPIO_DM_ANALOG,
+	.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
 	.intEdge = CY_GPIO_INTR_DISABLE,
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -536,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -552,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -568,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -584,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -600,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
 {
 	.outVal = 1,
@@ -616,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDCK_PORT_NUM,
+		.channel_num = CYBSP_SWDCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
 {
 	.outVal = 1,
@@ -632,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINA_PORT_NUM,
+		.channel_num = CYBSP_CINA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
 {
 	.outVal = 1,
@@ -648,22 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_B_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED5_RGB_B_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINB_PORT_NUM,
+		.channel_num = CYBSP_CINB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -680,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -696,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -712,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -728,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -744,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -760,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -776,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -792,92 +760,159 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_G_PORT, CYBSP_LED5_RGB_G_PIN, &CYBSP_LED5_RGB_G_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
+#endif //defined (CY_USING_HAL)
 
-
-	Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_R_PORT, CYBSP_LED5_RGB_R_PIN, &CYBSP_LED5_RGB_R_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SW4_PORT, CYBSP_SW4_PIN, &CYBSP_SW4_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT0_PORT, CYBSP_SDHC0_DAT0_PIN, &CYBSP_SDHC0_DAT0_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT1_PORT, CYBSP_SDHC0_DAT1_PIN, &CYBSP_SDHC0_DAT1_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT2_PORT, CYBSP_SDHC0_DAT2_PIN, &CYBSP_SDHC0_DAT2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT3_PORT, CYBSP_SDHC0_DAT3_PIN, &CYBSP_SDHC0_DAT3_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_CMD_PORT, CYBSP_SDHC0_CMD_PIN, &CYBSP_SDHC0_CMD_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_CLK_PORT, CYBSP_SDHC0_CLK_PIN, &CYBSP_SDHC0_CLK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RTS_PORT, CYBSP_DEBUG_UART_RTS_PIN, &CYBSP_DEBUG_UART_RTS_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_CTS_PORT, CYBSP_DEBUG_UART_CTS_PIN, &CYBSP_DEBUG_UART_CTS_config);
+	Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_B_PORT, CYBSP_LED5_RGB_B_PIN, &CYBSP_LED5_RGB_B_config);
-
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -0,0 +1,916 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS0_ENABLED 1U
+#define CYBSP_QSPI_SS0_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS0_PORT_NUM 11U
+#define CYBSP_QSPI_SS0_PIN 2U
+#define CYBSP_QSPI_SS0_NUM 2U
+#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA3_ENABLED 1U
+#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA3_PORT_NUM 11U
+#define CYBSP_QSPI_DATA3_PIN 3U
+#define CYBSP_QSPI_DATA3_NUM 3U
+#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA2_ENABLED 1U
+#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA2_PORT_NUM 11U
+#define CYBSP_QSPI_DATA2_PIN 4U
+#define CYBSP_QSPI_DATA2_NUM 4U
+#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA1_ENABLED 1U
+#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA1_PORT_NUM 11U
+#define CYBSP_QSPI_DATA1_PIN 5U
+#define CYBSP_QSPI_DATA1_NUM 5U
+#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA0_ENABLED 1U
+#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA0_PORT_NUM 11U
+#define CYBSP_QSPI_DATA0_PIN 6U
+#define CYBSP_QSPI_DATA0_NUM 6U
+#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U
+#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SPI_CLOCK_PORT_NUM 11U
+#define CYBSP_QSPI_SPI_CLOCK_PIN 7U
+#define CYBSP_QSPI_SPI_CLOCK_NUM 7U
+#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_RX_ENABLED 1U
+#define CYBSP_CSD_RX_PORT GPIO_PRT1
+#define CYBSP_CSD_RX_PORT_NUM 1U
+#define CYBSP_CSD_RX_PIN 0U
+#define CYBSP_CSD_RX_NUM 0U
+#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PORT_NUM 3U
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_0_HSIOM
+	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PORT_NUM 3U
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_1_HSIOM
+	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PORT_NUM 3U
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_2_HSIOM
+	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PORT_NUM 3U
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_3_HSIOM
+	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_POWER_ENABLED 1U
+#define CYBSP_BT_POWER_PORT GPIO_PRT3
+#define CYBSP_BT_POWER_PORT_NUM 3U
+#define CYBSP_BT_POWER_PIN 4U
+#define CYBSP_BT_POWER_NUM 4U
+#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_4_HSIOM
+	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U
+#define CYBSP_BT_DEVICE_WAKE_PIN 5U
+#define CYBSP_BT_DEVICE_WAKE_NUM 5U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_3_pin_5_HSIOM
+	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U
+#define CYBSP_BT_HOST_WAKE_PIN 0U
+#define CYBSP_BT_HOST_WAKE_NUM 0U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -24,10 +24,10 @@
 
 #include "cycfg_qspi_memslot.h"
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
+    .command = 0xECU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,10 +78,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xD8U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,10 +114,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
+    .command = 0x34U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,52 +186,52 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
     .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 520U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 134000U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 340U
+    .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
     /* The base address the memory slave is mapped to in the PSoC memory map.
@@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
     .baseAddress = 0x18000000U,
     /* The size allocated in the PSoC memory map, for the memory slave device.
     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
+    .memMappedSize = 0x4000000U,
     /* If this memory device is one of the devices in the dual quad SPI configuration.
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL512S_SlaveSlot_0
+   &S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -28,19 +28,19 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
 extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -40,21 +40,11 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00
-#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01
-#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02
-#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03
-#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD
-#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
 #define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
 #define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
 #define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
-#define ioss_0_port_5_pin_2_HSIOM P5_2_SCB5_UART_RTS
-#define ioss_0_port_5_pin_3_HSIOM P5_3_SCB5_UART_CTS
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@@ -62,8 +52,8 @@ void init_cycfg_routing(void);
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -0,0 +1,570 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 144UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
+#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_PLL1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_INIT 1
+#define CY_CFG_PWR_USING_PMIC 0
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
+#define CY_CFG_PWR_USING_ULP 0
+
+static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = 
+{
+	.fllMult = 500U,
+	.refDiv = 20U,
+	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+	.enableOutputDiv = true,
+	.lockTolerance = 10U,
+	.igain = 9U,
+	.pgain = 5U,
+	.settlingCount = 8U,
+	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+	.cco_Freq = 355U,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
+{
+	.feedbackDiv = 36,
+	.referenceDiv = 1,
+	.outputDiv = 2,
+	.lfMode = false,
+	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = 
+{
+	.feedbackDiv = 30,
+	.referenceDiv = 1,
+	.outputDiv = 5,
+	.lfMode = false,
+	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+
+__WEAK void cycfg_ClockStartupError(uint32_t error)
+{
+    (void)error; /* Suppress the compiler warning */
+    while(1);
+}
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
+{
+    Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkBakInit()
+{
+    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkFastInit()
+{
+    Cy_SysClk_ClkFastSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_FllInit()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+{
+    Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
+}
+__STATIC_INLINE void Cy_SysClk_IloInit()
+{
+    /* The WDT is unlocked in the default startup code */
+    Cy_SysClk_IloEnable();
+    Cy_SysClk_IloHibernateOn(true);
+}
+__STATIC_INLINE void Cy_SysClk_ClkLfInit()
+{
+    /* The WDT is unlocked in the default startup code */
+    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+{
+    Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+{
+    Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+{
+    Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+{
+    Cy_SysClk_ClkPeriSetDivider(1U);
+}
+__STATIC_INLINE void Cy_SysClk_Pll0Init()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_Pll1Init()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
+{
+    Cy_SysClk_ClkSlowSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
+{
+    Cy_SysClk_ClkTimerDisable();
+     Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
+    Cy_SysClk_ClkTimerSetDivider(0U);
+    Cy_SysClk_ClkTimerEnable();
+}
+__STATIC_INLINE void Cy_SysClk_WcoInit()
+{
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+    }
+}
+__STATIC_INLINE void init_cycfg_power(void)
+{
+     /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+     #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+     if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+     {
+         Cy_SysLib_ResetBackupDomain();
+         Cy_SysClk_IloDisable();
+         Cy_SysClk_IloInit();
+     }
+     #else /* Dedicated Supply */
+     Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
+     #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+     /* Configure core regulator */
+     #if CY_CFG_PWR_USING_LDO
+     Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+     Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
+     #else
+     Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+     #endif /* CY_CFG_PWR_USING_LDO */
+     /* Configure PMIC */
+     Cy_SysPm_UnlockPmic();
+     #if CY_CFG_PWR_USING_PMIC
+     Cy_SysPm_PmicEnableOutput();
+     #else
+     Cy_SysPm_PmicDisableOutput();
+     #endif /* CY_CFG_PWR_USING_PMIC */
+}
+
+
+void init_cycfg_system(void)
+{
+	/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+	Cy_SysLib_SetWaitStates(false, 150UL);
+	#ifdef CY_CFG_PWR_ENABLED
+	    #ifdef CY_CFG_PWR_INIT
+	    init_cycfg_power();
+	    #else
+	    #warning Power system will not be configured. Update power personality to v1.20 or later.
+	    #endif /* CY_CFG_PWR_INIT */
+	#endif /* CY_CFG_PWR_ENABLED */
+	
+	/* Reset the core clock path to default and disable all the FLLs/PLLs */
+	Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+	Cy_SysClk_ClkFastSetDivider(0U);
+	Cy_SysClk_ClkPeriSetDivider(1U);
+	Cy_SysClk_ClkSlowSetDivider(0U);
+	for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+	{
+	    (void)Cy_SysClk_PllDisable(pll);
+	}
+	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+	
+	if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+	    (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+	{
+	    Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+	}
+	
+	Cy_SysClk_FllDisable();
+	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+	Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+	#ifdef CY_IP_MXBLESS
+	(void)Cy_BLE_EcoReset();
+	#endif
+	
+	
+	/* Enable all source clocks */
+	#ifdef CY_CFG_SYSCLK_PILO_ENABLED
+	Cy_SysClk_PiloInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_WCO_ENABLED
+	Cy_SysClk_WcoInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+	Cy_SysClk_ClkLfInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+	Cy_SysClk_AltHfInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_ECO_ENABLED
+	Cy_SysClk_EcoInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+	Cy_SysClk_ExtClkInit();
+	#endif
+	
+	/* Configure CPU clock dividers */
+	#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+	Cy_SysClk_ClkFastInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+	Cy_SysClk_ClkPeriInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+	Cy_SysClk_ClkSlowInit();
+	#endif
+	
+	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+	    /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+	    Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+	    Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+	#else
+	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+	        Cy_SysClk_ClkPath1Init();
+	    #endif
+	#endif
+	
+	/* Configure Path Clocks */
+	#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+	Cy_SysClk_ClkPath0Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+	Cy_SysClk_ClkPath2Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+	Cy_SysClk_ClkPath3Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+	Cy_SysClk_ClkPath4Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+	Cy_SysClk_ClkPath5Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+	Cy_SysClk_ClkPath6Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+	Cy_SysClk_ClkPath7Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+	Cy_SysClk_ClkPath8Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+	Cy_SysClk_ClkPath9Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+	Cy_SysClk_ClkPath10Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+	Cy_SysClk_ClkPath11Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+	Cy_SysClk_ClkPath12Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+	Cy_SysClk_ClkPath13Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+	Cy_SysClk_ClkPath14Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+	Cy_SysClk_ClkPath15Init();
+	#endif
+	
+	/* Configure and enable FLL */
+	#ifdef CY_CFG_SYSCLK_FLL_ENABLED
+	Cy_SysClk_FllInit();
+	#endif
+	
+	Cy_SysClk_ClkHf0Init();
+	
+	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+	        /* Apply the ClkPath1 user setting */
+	        Cy_SysClk_ClkPath1Init();
+	    #endif
+	#endif
+	
+	/* Configure and enable PLLs */
+	#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+	Cy_SysClk_Pll0Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+	Cy_SysClk_Pll1Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+	Cy_SysClk_Pll2Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+	Cy_SysClk_Pll3Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+	Cy_SysClk_Pll4Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+	Cy_SysClk_Pll5Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+	Cy_SysClk_Pll6Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+	Cy_SysClk_Pll7Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+	Cy_SysClk_Pll8Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+	Cy_SysClk_Pll9Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+	Cy_SysClk_Pll10Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+	Cy_SysClk_Pll11Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+	Cy_SysClk_Pll12Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+	Cy_SysClk_Pll13Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+	Cy_SysClk_Pll14Init();
+	#endif
+	
+	/* Configure HF clocks */
+	#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+	Cy_SysClk_ClkHf1Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+	Cy_SysClk_ClkHf2Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+	Cy_SysClk_ClkHf3Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+	Cy_SysClk_ClkHf4Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+	Cy_SysClk_ClkHf5Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+	Cy_SysClk_ClkHf6Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+	Cy_SysClk_ClkHf7Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+	Cy_SysClk_ClkHf8Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+	Cy_SysClk_ClkHf9Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+	Cy_SysClk_ClkHf10Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+	Cy_SysClk_ClkHf11Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+	Cy_SysClk_ClkHf12Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+	Cy_SysClk_ClkHf13Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+	Cy_SysClk_ClkHf14Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+	Cy_SysClk_ClkHf15Init();
+	#endif
+	
+	/* Configure miscellaneous clocks */
+	#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+	Cy_SysClk_ClkTimerInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+	Cy_SysClk_ClkAltSysTickInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+	Cy_SysClk_ClkPumpInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+	Cy_SysClk_ClkBakInit();
+	#endif
+	
+	/* Configure default enabled clocks */
+	#ifdef CY_CFG_SYSCLK_ILO_ENABLED
+	Cy_SysClk_IloInit();
+	#else
+	Cy_SysClk_IloDisable();
+	#endif
+	
+	#ifndef CY_CFG_SYSCLK_IMO_ENABLED
+	#error the IMO must be enabled for proper chip operation
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_MFO_ENABLED
+	Cy_SysClk_MfoInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+	Cy_SysClk_ClkMfInit();
+	#endif
+	
+	/* Set accurate flash wait states */
+	#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+	Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+	#endif
+	
+	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -28,6 +28,9 @@
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
 #include "cy_systick.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_gpio.h"
 #include "cy_syspm.h"
 
@@ -43,23 +46,22 @@ extern "C" {
 #define srss_0_clock_0_fll_0_ENABLED 1U
 #define srss_0_clock_0_hfclk_0_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF0 0UL
-#define srss_0_clock_0_hfclk_1_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF1 1UL
 #define srss_0_clock_0_hfclk_2_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF2 2UL
 #define srss_0_clock_0_hfclk_3_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_hfclk_4_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF4 4UL
 #define srss_0_clock_0_ilo_0_ENABLED 1U
 #define srss_0_clock_0_imo_0_ENABLED 1U
 #define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
 #define srss_0_clock_0_pathmux_0_ENABLED 1U
 #define srss_0_clock_0_pathmux_1_ENABLED 1U
 #define srss_0_clock_0_pathmux_2_ENABLED 1U
-#define srss_0_clock_0_pathmux_3_ENABLED 1U
-#define srss_0_clock_0_pathmux_4_ENABLED 1U
 #define srss_0_clock_0_periclk_0_ENABLED 1U
 #define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_pll_1_ENABLED 1U
 #define srss_0_clock_0_slowclk_0_ENABLED 1U
 #define srss_0_clock_0_timerclk_0_ENABLED 1U
 #define srss_0_clock_0_wco_0_ENABLED 1U
@@ -80,6 +82,16 @@ extern "C" {
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_system(void);
 
 #if defined(__cplusplus)

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg

@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense

@@ -0,0 +1,402 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0 build 531-->
+<Configuration app="Capsense" major="2" minor="0">
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
+<Design version="11" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v2">
     <ToolInfo version="1.0.0"/>
     <Devices>
         <Device mpn="CY8C624ABZI-D44">
@@ -8,7 +8,7 @@
                     <Param id="dbgMode" value="SWD"/>
                     <Param id="traceEnable" value="false"/>
                 </Block>
-                <Block location="csd[0].csd[0]" alias="CYBSP_CAPSENSE" template="mxs40csd" version="2.0">
+                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
                     <Param id="CapSenseEnable" value="true"/>
                     <Param id="CapSenseCore" value="4"/>
                     <Param id="SensorCount" value="12"/>
@@ -64,36 +64,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_SW2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[0].pin[5]" alias="CYBSP_LED5_RGB_G" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS0" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -154,7 +124,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_RX" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -164,96 +134,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED5_RGB_R" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[4]" alias="CYBSP_SW4" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[0]" alias="CYBSP_SDHC0_DAT0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[1]" alias="CYBSP_SDHC0_DAT1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[2]" alias="CYBSP_SDHC0_DAT2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[3]" alias="CYBSP_SDHC0_DAT3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[4]" alias="CYBSP_SDHC0_CMD" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[5]" alias="CYBSP_SDHC0_CLK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
                     <Param id="initialState" value="1"/>
@@ -304,7 +184,17 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                    <Param id="initialState" value="0"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="0"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -314,56 +204,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="0"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[2]" alias="CYBSP_DEBUG_UART_RTS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[3]" alias="CYBSP_DEBUG_UART_CTS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
                     <Param id="initialState" value="1"/>
@@ -434,16 +274,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[7].pin[3]" alias="CYBSP_LED5_RGB_B" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
@@ -524,11 +354,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="peri[0].div_16[0]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="52"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
                 <Block location="peri[0].div_16[1]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="78"/>
                     <Param id="fracDivider" value="0"/>
@@ -598,59 +423,6 @@
                     <Param id="EnableWakeup" value="false"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="12"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="9"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="true"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_HIGH"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
-                <Block location="sdhc[0]" alias="CYBSP_RADIO" template="mxs40sdhost" version="1.0">
-                    <Param id="cardType" value="nonEmmc"/>
-                    <Param id="dmaType" value="CY_SD_HOST_DMA_SDMA"/>
-                    <Param id="enableLedControl" value="false"/>
-                    <Param id="busWidth" value="CY_SD_HOST_BUS_WIDTH_4_BIT"/>
-                    <Param id="lowVoltageSignaling" value="false"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
                     <Param id="configurator" value="0"/>
                     <Param id="isrAlignment" value="false"/>
@@ -683,6 +455,10 @@
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="2"/>
                 </Block>
+                <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="2"/>
+                    <Param id="divider" value="1"/>
+                </Block>
                 <Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="1"/>
@@ -702,6 +478,9 @@
                 <Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
                     <Param id="sourceClock" value="imo"/>
                 </Block>
+                <Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
                 <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
                     <Param id="divider" value="2"/>
                 </Block>
@@ -711,6 +490,12 @@
                     <Param id="desiredFrequency" value="144.000"/>
                     <Param id="optimization" value="MinPower"/>
                 </Block>
+                <Block location="srss[0].clock[0].pll[1]" alias="" template="mxs40pll" version="1.0">
+                    <Param id="lowFrequencyMode" value="false"/>
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="48.000"/>
+                    <Param id="optimization" value="MinPower"/>
+                </Block>
                 <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
                     <Param id="divider" value="1"/>
                 </Block>
@@ -739,6 +524,22 @@
                     <Param id="CascadeC1C2" value="false"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
+                    <Param id="pwrEstimator" value="0"/>
+                    <Param id="pwrMode" value="LDO_1_1"/>
+                    <Param id="actPwrMode" value="LP"/>
+                    <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
+                    <Param id="pmicEnable" value="false"/>
+                    <Param id="backupSrc" value="VDDD"/>
+                    <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
+                    <Param id="deepsleepLatency" value="0"/>
+                    <Param id="vddaMv" value="3300"/>
+                    <Param id="vdddMv" value="3300"/>
+                    <Param id="vBackupMv" value="3300"/>
+                    <Param id="vddNsMv" value="3300"/>
+                    <Param id="vddio0Mv" value="3300"/>
+                    <Param id="vddio1Mv" value="3300"/>
+                </Block>
                 <Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
                     <Param id="format" value="0"/>
                     <Param id="dst" value="false"/>
@@ -790,30 +591,6 @@
                     <Port name="ioss[0].port[0].pin[1].analog[0]"/>
                     <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[1]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[2]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[3]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_cmd[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
-                    <Port name="sdhc[0].clk_card[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
                     <Port name="scb[2].uart_rx[0]"/>
@@ -830,22 +607,6 @@
                     <Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
                     <Port name="scb[2].uart_cts[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
-                    <Port name="scb[5].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
-                    <Port name="scb[5].uart_tx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[2].digital_out[0]"/>
-                    <Port name="scb[5].uart_rts[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[3].digital_in[0]"/>
-                    <Port name="scb[5].uart_cts[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
                     <Port name="scb[3].i2c_scl[0]"/>
@@ -878,10 +639,6 @@
                     <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
                     <Port name="smif[0].spi_clk[0]"/>
                 </Net>
-                <Net>
-                    <Port name="peri[0].div_16[0].clk[0]"/>
-                    <Port name="scb[5].clock[0]"/>
-                </Net>
                 <Net>
                     <Port name="peri[0].div_16[1].clk[0]"/>
                     <Port name="scb[2].clock[0]"/>
@@ -890,10 +647,6 @@
                     <Port name="peri[0].div_8[1].clk[0]"/>
                     <Port name="scb[3].clock[0]"/>
                 </Net>
-                <Net>
-                    <Port name="sdhc[0].clk_hf[0]"/>
-                    <Port name="srss[0].clock[0].hfclk[4].root_clk[0]"/>
-                </Net>
                 <Net>
                     <Port name="smif[0].clk_hf[0]"/>
                     <Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
@@ -912,6 +665,9 @@
                     <Arm>
                         <Port name="ioss[0].port[7].pin[2].analog[0]"/>
                     </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
                     <Arm>
                         <Port name="ioss[0].port[8].pin[1].analog[0]"/>
                     </Arm>
@@ -921,9 +677,6 @@
                     <Arm>
                         <Port name="ioss[0].port[8].pin[2].analog[0]"/>
                     </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
-                    </Arm>
                     <Arm>
                         <Port name="ioss[0].port[8].pin[3].analog[0]"/>
                     </Arm>
@@ -942,6 +695,10 @@
                 </Mux>
             </Netlist>
         </Device>
+        <Device mpn="CYW43012WKWBG">
+            <BlockConfig/>
+            <Netlist/>
+        </Device>
     </Devices>
     <Libraries>
         <Library name="bt_sdk" version="1.1"/>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.h

@@ -1,621 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_SW2_ENABLED 1U
-#define CYBSP_SW2_PORT GPIO_PRT0
-#define CYBSP_SW2_PIN 4U
-#define CYBSP_SW2_NUM 4U
-#define CYBSP_SW2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SW2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_SW2_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED5_RGB_G_ENABLED 1U
-#define CYBSP_LED5_RGB_G_PORT GPIO_PRT0
-#define CYBSP_LED5_RGB_G_PIN 5U
-#define CYBSP_LED5_RGB_G_NUM 5U
-#define CYBSP_LED5_RGB_G_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED5_RGB_G_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_5_HSIOM
-	#define ioss_0_port_0_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED5_RGB_G_HSIOM ioss_0_port_0_pin_5_HSIOM
-#define CYBSP_LED5_RGB_G_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED9_ENABLED 1U
-#define CYBSP_LED9_PORT GPIO_PRT11
-#define CYBSP_LED9_PIN 1U
-#define CYBSP_LED9_NUM 1U
-#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED9_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
-	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED9_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define CYBSP_LED9_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SS0_ENABLED 1U
-#define CYBSP_QSPI_SS0_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS0_PIN 2U
-#define CYBSP_QSPI_SS0_NUM 2U
-#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA3_ENABLED 1U
-#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA3_PIN 3U
-#define CYBSP_QSPI_DATA3_NUM 3U
-#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA2_ENABLED 1U
-#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA2_PIN 4U
-#define CYBSP_QSPI_DATA2_NUM 4U
-#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA1_ENABLED 1U
-#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA1_PIN 5U
-#define CYBSP_QSPI_DATA1_NUM 5U
-#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA0_ENABLED 1U
-#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA0_PIN 6U
-#define CYBSP_QSPI_DATA0_NUM 6U
-#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U
-#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SPI_CLOCK_PIN 7U
-#define CYBSP_QSPI_SPI_CLOCK_NUM 7U
-#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED5_RGB_R_ENABLED 1U
-#define CYBSP_LED5_RGB_R_PORT GPIO_PRT1
-#define CYBSP_LED5_RGB_R_PIN 1U
-#define CYBSP_LED5_RGB_R_NUM 1U
-#define CYBSP_LED5_RGB_R_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED5_RGB_R_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
-	#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED5_RGB_R_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define CYBSP_LED5_RGB_R_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_SW4_ENABLED 1U
-#define CYBSP_SW4_PORT GPIO_PRT1
-#define CYBSP_SW4_PIN 4U
-#define CYBSP_SW4_NUM 4U
-#define CYBSP_SW4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_SW4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_4_HSIOM
-	#define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SW4_HSIOM ioss_0_port_1_pin_4_HSIOM
-#define CYBSP_SW4_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED8_ENABLED 1U
-#define CYBSP_LED8_PORT GPIO_PRT1
-#define CYBSP_LED8_PIN 5U
-#define CYBSP_LED8_NUM 5U
-#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED8_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_SDHC0_DAT0_ENABLED 1U
-#define CYBSP_SDHC0_DAT0_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT0_PIN 0U
-#define CYBSP_SDHC0_DAT0_NUM 0U
-#define CYBSP_SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_0_HSIOM
-	#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define CYBSP_SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_DAT1_ENABLED 1U
-#define CYBSP_SDHC0_DAT1_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT1_PIN 1U
-#define CYBSP_SDHC0_DAT1_NUM 1U
-#define CYBSP_SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_1_HSIOM
-	#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define CYBSP_SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_DAT2_ENABLED 1U
-#define CYBSP_SDHC0_DAT2_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT2_PIN 2U
-#define CYBSP_SDHC0_DAT2_NUM 2U
-#define CYBSP_SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_2_HSIOM
-	#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define CYBSP_SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_DAT3_ENABLED 1U
-#define CYBSP_SDHC0_DAT3_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT3_PIN 3U
-#define CYBSP_SDHC0_DAT3_NUM 3U
-#define CYBSP_SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_3_HSIOM
-	#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define CYBSP_SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_CMD_ENABLED 1U
-#define CYBSP_SDHC0_CMD_PORT GPIO_PRT2
-#define CYBSP_SDHC0_CMD_PIN 4U
-#define CYBSP_SDHC0_CMD_NUM 4U
-#define CYBSP_SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_CMD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_4_HSIOM
-	#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define CYBSP_SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_CLK_ENABLED 1U
-#define CYBSP_SDHC0_CLK_PORT GPIO_PRT2
-#define CYBSP_SDHC0_CLK_PIN 5U
-#define CYBSP_SDHC0_CLK_NUM 5U
-#define CYBSP_SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_CLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_5_HSIOM
-	#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define CYBSP_SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_BT_UART_RX_ENABLED 1U
-#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RX_PIN 0U
-#define CYBSP_BT_UART_RX_NUM 0U
-#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_0_HSIOM
-	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_TX_ENABLED 1U
-#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_TX_PIN 1U
-#define CYBSP_BT_UART_TX_NUM 1U
-#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_1_HSIOM
-	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_RTS_ENABLED 1U
-#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RTS_PIN 2U
-#define CYBSP_BT_UART_RTS_NUM 2U
-#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_2_HSIOM
-	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_CTS_ENABLED 1U
-#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_CTS_PIN 3U
-#define CYBSP_BT_UART_CTS_NUM 3U
-#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_3_HSIOM
-	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_POWER_ENABLED 1U
-#define CYBSP_BT_POWER_PORT GPIO_PRT3
-#define CYBSP_BT_POWER_PIN 4U
-#define CYBSP_BT_POWER_NUM 4U
-#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_4_HSIOM
-	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_HOST_WAKE_ENABLED 1U
-#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
-#define CYBSP_BT_HOST_WAKE_PIN 5U
-#define CYBSP_BT_HOST_WAKE_NUM 5U
-#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_3_pin_5_HSIOM
-	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
-#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define CYBSP_BT_DEVICE_WAKE_PIN 0U
-#define CYBSP_BT_DEVICE_WAKE_NUM 0U
-#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_4_pin_0_HSIOM
-	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_RTS_ENABLED 1U
-#define CYBSP_DEBUG_UART_RTS_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RTS_PIN 2U
-#define CYBSP_DEBUG_UART_RTS_NUM 2U
-#define CYBSP_DEBUG_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_2_HSIOM
-	#define ioss_0_port_5_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RTS_HSIOM ioss_0_port_5_pin_2_HSIOM
-#define CYBSP_DEBUG_UART_RTS_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_CTS_ENABLED 1U
-#define CYBSP_DEBUG_UART_CTS_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_CTS_PIN 3U
-#define CYBSP_DEBUG_UART_CTS_NUM 3U
-#define CYBSP_DEBUG_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_3_HSIOM
-	#define ioss_0_port_5_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_CTS_HSIOM ioss_0_port_5_pin_3_HSIOM
-#define CYBSP_DEBUG_UART_CTS_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_LED5_RGB_B_ENABLED 1U
-#define CYBSP_LED5_RGB_B_PORT GPIO_PRT7
-#define CYBSP_LED5_RGB_B_PIN 3U
-#define CYBSP_LED5_RGB_B_NUM 3U
-#define CYBSP_LED5_RGB_B_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED5_RGB_B_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_3_HSIOM
-	#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED5_RGB_B_HSIOM ioss_0_port_7_pin_3_HSIOM
-#define CYBSP_LED5_RGB_B_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SW2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_G_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_R_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SW4_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CMD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_B_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.c

@@ -1,464 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.c
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_system.h"
-
-#define CY_CFG_SYSCLK_ECO_ERROR 1
-#define CY_CFG_SYSCLK_ALTHF_ERROR 2
-#define CY_CFG_SYSCLK_PLL_ERROR 3
-#define CY_CFG_SYSCLK_FLL_ERROR 4
-#define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
-#define CY_CFG_SYSCLK_FLL_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 144UL
-#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
-#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_ILO_ENABLED 1
-#define CY_CFG_SYSCLK_IMO_ENABLED 1
-#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
-#define CY_CFG_SYSCLK_PLL0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
-#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
-#define CY_CFG_SYSCLK_WCO_ENABLED 1
-
-static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = 
-{
-	.fllMult = 500U,
-	.refDiv = 20U,
-	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
-	.enableOutputDiv = true,
-	.lockTolerance = 10U,
-	.igain = 9U,
-	.pgain = 5U,
-	.settlingCount = 8U,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
-	.cco_Freq = 355U,
-};
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
-{
-	.feedbackDiv = 36,
-	.referenceDiv = 1,
-	.outputDiv = 2,
-	.lfMode = false,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-};
-
-__WEAK void cycfg_ClockStartupError(uint32_t error)
-{
-    (void)error; /* Suppress the compiler warning */
-    while(1);
-}
-__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
-{
-    Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
-}
-__STATIC_INLINE void Cy_SysClk_ClkBakInit()
-{
-    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
-}
-__STATIC_INLINE void Cy_SysClk_ClkFastInit()
-{
-    Cy_SysClk_ClkFastSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_FllInit()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
-{
-    Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
-}
-__STATIC_INLINE void Cy_SysClk_IloInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_IloEnable();
-    Cy_SysClk_IloHibernateOn(true);
-}
-__STATIC_INLINE void Cy_SysClk_ClkLfInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
-{
-    Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
-{
-    Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
-{
-    Cy_SysClk_ClkPeriSetDivider(1U);
-}
-__STATIC_INLINE void Cy_SysClk_Pll0Init()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
-{
-    Cy_SysClk_ClkSlowSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
-{
-    Cy_SysClk_ClkTimerDisable();
-     Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
-    Cy_SysClk_ClkTimerSetDivider(0U);
-    Cy_SysClk_ClkTimerEnable();
-}
-__STATIC_INLINE void Cy_SysClk_WcoInit()
-{
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
-    }
-}
-
-
-void init_cycfg_system(void)
-{
-	/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
-	Cy_SysLib_SetWaitStates(false, 150UL);
-	#ifdef CY_CFG_PWR_ENABLED
-	    #ifdef CY_CFG_PWR_INIT
-	    init_cycfg_power();
-	    #else
-	    #warning Power system will not be configured. Update power personality to v1.20 or later.
-	    #endif /* CY_CFG_PWR_INIT */
-	#endif /* CY_CFG_PWR_ENABLED */
-	
-	/* Reset the core clock path to default and disable all the FLLs/PLLs */
-	Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-	Cy_SysClk_ClkFastSetDivider(0U);
-	Cy_SysClk_ClkPeriSetDivider(1U);
-	Cy_SysClk_ClkSlowSetDivider(0U);
-	for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
-	{
-	    (void)Cy_SysClk_PllDisable(pll);
-	}
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
-	
-	if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
-	    (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
-	{
-	    Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	}
-	
-	Cy_SysClk_FllDisable();
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
-	Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
-	#ifdef CY_IP_MXBLESS
-	(void)Cy_BLE_EcoReset();
-	#endif
-	
-	
-	/* Enable all source clocks */
-	#ifdef CY_CFG_SYSCLK_PILO_ENABLED
-	Cy_SysClk_PiloInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_WCO_ENABLED
-	Cy_SysClk_WcoInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
-	Cy_SysClk_ClkLfInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
-	Cy_SysClk_AltHfInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_ECO_ENABLED
-	Cy_SysClk_EcoInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
-	Cy_SysClk_ExtClkInit();
-	#endif
-	
-	/* Configure CPU clock dividers */
-	#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
-	Cy_SysClk_ClkFastInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
-	Cy_SysClk_ClkPeriInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
-	Cy_SysClk_ClkSlowInit();
-	#endif
-	
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
-	    Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
-	    Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	#else
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-	
-	/* Configure Path Clocks */
-	#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
-	Cy_SysClk_ClkPath0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
-	Cy_SysClk_ClkPath2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
-	Cy_SysClk_ClkPath3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
-	Cy_SysClk_ClkPath4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
-	Cy_SysClk_ClkPath5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
-	Cy_SysClk_ClkPath6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
-	Cy_SysClk_ClkPath7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
-	Cy_SysClk_ClkPath8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
-	Cy_SysClk_ClkPath9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
-	Cy_SysClk_ClkPath10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
-	Cy_SysClk_ClkPath11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
-	Cy_SysClk_ClkPath12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
-	Cy_SysClk_ClkPath13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
-	Cy_SysClk_ClkPath14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
-	Cy_SysClk_ClkPath15Init();
-	#endif
-	
-	/* Configure and enable FLL */
-	#ifdef CY_CFG_SYSCLK_FLL_ENABLED
-	Cy_SysClk_FllInit();
-	#endif
-	
-	Cy_SysClk_ClkHf0Init();
-	
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        /* Apply the ClkPath1 user setting */
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-	
-	/* Configure and enable PLLs */
-	#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
-	Cy_SysClk_Pll0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
-	Cy_SysClk_Pll1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
-	Cy_SysClk_Pll2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
-	Cy_SysClk_Pll3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
-	Cy_SysClk_Pll4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
-	Cy_SysClk_Pll5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
-	Cy_SysClk_Pll6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
-	Cy_SysClk_Pll7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
-	Cy_SysClk_Pll8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
-	Cy_SysClk_Pll9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
-	Cy_SysClk_Pll10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
-	Cy_SysClk_Pll11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
-	Cy_SysClk_Pll12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
-	Cy_SysClk_Pll13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
-	Cy_SysClk_Pll14Init();
-	#endif
-	
-	/* Configure HF clocks */
-	#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
-	Cy_SysClk_ClkHf1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
-	Cy_SysClk_ClkHf2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
-	Cy_SysClk_ClkHf3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
-	Cy_SysClk_ClkHf4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
-	Cy_SysClk_ClkHf5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
-	Cy_SysClk_ClkHf6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
-	Cy_SysClk_ClkHf7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
-	Cy_SysClk_ClkHf8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
-	Cy_SysClk_ClkHf9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
-	Cy_SysClk_ClkHf10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
-	Cy_SysClk_ClkHf11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
-	Cy_SysClk_ClkHf12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
-	Cy_SysClk_ClkHf13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
-	Cy_SysClk_ClkHf14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
-	Cy_SysClk_ClkHf15Init();
-	#endif
-	
-	/* Configure miscellaneous clocks */
-	#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
-	Cy_SysClk_ClkTimerInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
-	Cy_SysClk_ClkAltSysTickInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
-	Cy_SysClk_ClkPumpInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
-	Cy_SysClk_ClkBakInit();
-	#endif
-	
-	/* Configure default enabled clocks */
-	#ifdef CY_CFG_SYSCLK_ILO_ENABLED
-	Cy_SysClk_IloInit();
-	#else
-	Cy_SysClk_IloDisable();
-	#endif
-	
-	#ifndef CY_CFG_SYSCLK_IMO_ENABLED
-	#error the IMO must be enabled for proper chip operation
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_MFO_ENABLED
-	Cy_SysClk_MfoInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
-	Cy_SysClk_ClkMfInit();
-	#endif
-	
-	/* Set accurate flash wait states */
-	#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
-	Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
-	#endif
-	
-	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
-	SystemCoreClockUpdate();
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.h

@@ -1,68 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.h
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_SYSTEM_H)
-#define CYCFG_SYSTEM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_systick.h"
-#include "cy_gpio.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define cpuss_0_dap_0_ENABLED 1U
-#define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
-#define srss_0_clock_0_bakclk_0_ENABLED 1U
-#define srss_0_clock_0_fastclk_0_ENABLED 1U
-#define srss_0_clock_0_fll_0_ENABLED 1U
-#define srss_0_clock_0_hfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF0 0UL
-#define srss_0_clock_0_hfclk_2_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF2 2UL
-#define srss_0_clock_0_hfclk_4_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF4 4UL
-#define srss_0_clock_0_ilo_0_ENABLED 1U
-#define srss_0_clock_0_imo_0_ENABLED 1U
-#define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
-#define srss_0_clock_0_pathmux_0_ENABLED 1U
-#define srss_0_clock_0_pathmux_1_ENABLED 1U
-#define srss_0_clock_0_periclk_0_ENABLED 1U
-#define srss_0_clock_0_pll_0_ENABLED 1U
-#define srss_0_clock_0_slowclk_0_ENABLED 1U
-#define srss_0_clock_0_timerclk_0_ENABLED 1U
-#define srss_0_clock_0_wco_0_ENABLED 1U
-
-void init_cycfg_system(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_SYSTEM_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/qspi_config.cfg

@@ -1,2 +0,0 @@
-set SMIF_BANKS {
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h

@@ -20,39 +20,8 @@
 #ifndef MBED_PINNAMES_H
 #define MBED_PINNAMES_H
 
-#include "cmsis.h"
 #include "PinNamesTypes.h"
-#include "PortNames.h"
 #include "cyhal_pin_package.h"
-#include "cyhal_utils.h"
-
-typedef cyhal_gpio_t PinName;
-
-// Arduino connector namings
-#define A0 P10_0
-#define A1 P10_1
-#define A2 P10_2
-#define A3 P10_3
-#define A4 P10_4
-#define A5 P10_5
-
-#define D0 P5_0
-#define D1 P5_1
-#define D2 P5_2
-#define D3 P5_3
-#define D4 P5_4
-#define D5 P5_5
-#define D6 P5_6
-#define D7 P0_2
-#define D8 P13_0
-#define D9 P13_1
-#define D10 P12_3
-#define D11 P12_0
-#define D12 P12_1
-#define D13 P12_2
-#define D14 P6_1
-#define D15 P6_0
-
 
 // Generic signal names
 
@@ -64,46 +33,23 @@ typedef cyhal_gpio_t PinName;
 #define UART_RTS P5_2
 #define UART_CTS P5_3
 
-#define SPI_MOSI P12_0
-#define SPI_MISO P12_1
-#define SPI_CLK P12_2
-#define SPI_CS P12_4
-
-#define UART_RX P5_0
-#define UART_TX P5_1
-#define UART_RTS P5_2
-#define UART_CTS P5_3
-
-#define BT_UART_RX P3_0
-#define BT_UART_TX P3_1
-#define BT_UART_CTS P3_3
-#define BT_UART_RTS P3_2
-
-#define BT_PIN_POWER P3_4
-#define BT_PIN_HOST_WAKE P3_5
-#define BT_PIN_DEVICE_WAKE P4_0
-// Reset pin unavailable
-
-#define SWITCH2 P0_4
-#define LED1 P13_7
-#define LED2 NC
-#define LED3 NC
-#define LED4 NC
+#define LED1 P1_1
+#define LED2 P0_5
+#define LED3 P7_3
+#define LED4 P1_5
+#define LED5 P11_1
 #define LED_RED LED1
+#define LED_GREEN LED2
+#define LED_BLUE LED3
 
+// Reset pin unavailable
+#define SWITCH2 P0_4
+#define SWITCH4 P1_4
 #define USER_BUTTON SWITCH2
 #define BUTTON1 USER_BUTTON
+#define BUTTON2 SWITCH4
 
-#define PDM_DATA P10_5
-#define PDM_CLK P10_4
-#define THERM_OUT_1 P10_1
-#define THERM_OUT_2 P10_2
-#define THERM_OUT THERM_OUT_1
-#define THERM_VDD P10_3
-#define THERM_GND P10_0
-
-#define CARD_DETECT_1 P13_5
-#define CARD_DETECT_2 P12_1
+#define CARD_DETECT_1 P13_7
 #define CARD_DETECT CARD_DETECT_1
 #define SD_CMD P12_4
 #define SD_CLK P12_5
@@ -132,23 +78,7 @@ typedef cyhal_gpio_t PinName;
 #define STDIO_UART_CTS UART_CTS
 #define STDIO_UART_RTS UART_RTS
 
-#define CY_STDIO_UART_RX STDIO_UART_RX
-#define CY_STDIO_UART_TX STDIO_UART_TX
-#define CY_STDIO_UART_CTS STDIO_UART_CTS
-#define CY_STDIO_UART_RTS STDIO_UART_RTS
-
-#define CY_BT_UART_RX BT_UART_RX
-#define CY_BT_UART_TX BT_UART_TX
-#define CY_BT_UART_CTS BT_UART_CTS
-#define CY_BT_UART_RTS BT_UART_RTS
-
-#define CY_BT_PIN_POWER BT_PIN_POWER
-#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
-#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
-
 #define USBTX UART_TX
 #define USBRX UART_RX
 
-#define CY_WIFI_HOST_WAKE P2_7
-
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c

@@ -0,0 +1,100 @@
+/***************************************************************************//**
+* \file CY8CKIT-062S2-43012/cybsp.c
+*
+* Description:
+* Provides APIs for interacting with the hardware contained on the Cypress
+* CY8CKIT-062S2-43012 pioneer kit.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cybsp.h"
+#include "cyhal_utils.h"
+#include "cycfg.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+cy_rslt_t cybsp_init(void)
+{
+    cy_rslt_t result;
+
+    result = cyhal_hwmgr_init();
+    init_cycfg_system();
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        result = cybsp_register_sysclk_pm_callback();
+    }
+
+#ifndef __MBED__
+    if (CY_RSLT_SUCCESS == result)
+    {
+        /* Initialize User LEDs */
+        /* Reserves: CYBSP_USER_LED1 */
+        result |= cybsp_led_init(CYBSP_USER_LED1);
+        /* Reserves: CYBSP_USER_LED2 */
+        result |= cybsp_led_init(CYBSP_USER_LED2);
+        /* Reserves: CYBSP_USER_LED3 */
+        result |= cybsp_led_init(CYBSP_USER_LED3);
+        /* Reserves: CYBSP_USER_LED4 */
+        result |= cybsp_led_init(CYBSP_USER_LED4);
+        /* Reserves: CYBSP_USER_LED5 */
+        result |= cybsp_led_init(CYBSP_USER_LED5);
+        /* Initialize User Buttons */
+        /* Reserves: CYBSP_USER_BTN1 */
+        result |= cybsp_btn_init(CYBSP_USER_BTN1);
+        /* Reserves: CYBSP_USER_BTN2 */
+        result |= cybsp_btn_init(CYBSP_USER_BTN2);
+
+        CY_ASSERT(CY_RSLT_SUCCESS == result);
+
+        /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
+        if (CY_RSLT_SUCCESS == result)
+        {
+           /* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RTS, CYBSP_DEBUG_UART_CTS
+            *    corresponding SCB instance and one of available clock dividers */
+            result = cybsp_retarget_init();
+        }
+    }
+#endif /* __MBED__ */
+
+#if defined(CYBSP_WIFI_CAPABLE)
+    /* Initialize SDIO interface.
+       NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done
+       when starting up WiFi. */
+    if (CY_RSLT_SUCCESS == result)
+    {
+       /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
+       *    CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */
+        result = cybsp_wifi_sdio_init();
+    }
+#endif /* defined(CYBSP_WIFI_CAPABLE) */
+
+    /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
+    *   user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
+    *   (cyreservedresources.list) to make sure no resources are reserved by both. */
+    return result;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h

@@ -0,0 +1,46 @@
+/***************************************************************************//**
+* \file CY8CKIT-062S2-43012/cybsp.h
+*
+* Description:
+* Provides APIs for interacting with the hardware contained on the Cypress
+* CY8CKIT-062S2-43012 pioneer kit.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#pragma once
+
+#include "cybsp_types.h"
+#include "cybsp_core.h"
+#if defined(CYBSP_WIFI_CAPABLE)
+#include "cybsp_wifi_sdio.h"
+#endif
+#ifndef __MBED__
+#include "cybsp_retarget.h"
+#include "cybsp_serial_flash.h"
+#include "cybsp_rgb_led.h"
+#endif /* __MBED__ */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+#if defined(__cplusplus)
+}
+#endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.c

@@ -1,67 +0,0 @@
-/***************************************************************************//**
-* \file CY8CKIT-062S2-43012/cybsp_cy8ckit_062s2_43012.c
-*
-* Description:
-* Provides APIs for interacting with the hardware contained on the Cypress
-* CY8CKIT-062S2-43012 pioneer kit.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdlib.h>
-#include "cybsp_cy8ckit_062s2_43012.h"
-#include "cyhal_utils.h"
-#include "cyhal_implementation.h"
-#include "cycfg.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-cy_rslt_t cybsp_init(void)
-{
-    cy_rslt_t result = CY_RSLT_SUCCESS;
-
-    init_cycfg_system();
-
-#ifndef __MBED__
-    /* Initialize User LEDs */
-    result |= cybsp_led_init(CYBSP_USER_LED1);
-    result |= cybsp_led_init(CYBSP_USER_LED2);
-    result |= cybsp_led_init(CYBSP_USER_LED3);
-    result |= cybsp_led_init(CYBSP_USER_LED4);
-    result |= cybsp_led_init(CYBSP_USER_LED5);
-    /* Initialize User Buttons */
-    result |= cybsp_btn_init(CYBSP_USER_BTN1);
-    result |= cybsp_btn_init(CYBSP_USER_BTN2);
-
-    CY_ASSERT(CY_RSLT_SUCCESS == result);
-
-    /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
-    if (CY_RSLT_SUCCESS == result)
-    {
-        result = cybsp_retarget_init();
-    }
-#endif
-
-    return result;
-}
-
-#if defined(__cplusplus)
-}
-#endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_cy8ckit_062s2_43012.h

@@ -1,74 +0,0 @@
-/***************************************************************************//**
-* \file CY8CKIT-062S2-43012/cybsp_cy8ckit_062s2_43012.h
-*
-* Description:
-* Provides APIs for interacting with the hardware contained on the Cypress
-* CY8CKIT-062S2-43012 pioneer kit.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/**
-* \addtogroup group_bsp_cy8ckit_062s2_43012 CY8CKIT-062S2-43012
-* \ingroup group_bsp
-* \{
-* The CY8CKIT-062S2-43012 PSoC 6 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC 6 MCUs.
-* It comes with a Murata LBEE5KL1DX module, based on the CYW43012 combo device, industry-leading CapSense for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. This kit is designed with a snap-away form-factor, allowing the user to separate the different components and features that come with this kit and use independently.
-* In addition, support for Digilent's Pmod interface is also provided with this kit.
-*
-* <div class="category">Kit Features:</div>
-* <ul>
-* <li>Support of up to 2MB Flash and 1MB SRAM</li>
-* <li>Dedicated SDHC to interface with WICED wireless devices.</li>
-* <li>Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm Cortex-M0+ as the secondary processor for low-power operations.</li>
-* <li>Supports Full-Speed USB, capacitive-sensing with CapSense, a PDM-PCM digital microphone interface, a Quad-SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks.</li>
-* </ul>
-*
-* <div class="category">Kit Contents:</div>
-* <ul>
-* <li>PSoC 6 Wi-Fi BT Pioneer Board</li>
-* <li>USB Type-A to Micro-B cable</li>
-* <li>Quick Start Guide</li>
-* </ul>
-*
-* \defgroup group_bsp_cy8ckit_062s2_43012_macros Macros
-* \defgroup group_bsp_cy8ckit_062s2_43012_functions Functions
-* \defgroup group_bsp_cy8ckit_062s2_43012_enums Enumerated Types
-*/
-
-
-#pragma once
-
-#include "cybsp_api_core.h"
-#ifdef __MBED__
-#include "cybsp_api_wifi.h"
-#else 
-#include "cybsp_retarget.h"
-#include "cybsp_serial_flash.h"
-#endif /* __MBED__ */
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-
-#if defined(__cplusplus)
-}
-#endif
-
-/** \} group_bsp_cy8ckit_062s2_43012 */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h

@@ -23,14 +23,6 @@
 * limitations under the License.
 *******************************************************************************/
 
-/**
-* \addtogroup group_bsp_cy8ckit_062s2_43012 CY8CKIT-062S2-43012
-* \ingroup group_bsp
-* \{
-* \defgroup group_bsp_cy8ckit_062s2_43012_macros Macros
-* \defgroup group_bsp_cy8ckit_062s2_43012_enums Enumerated Types
-*/
-
 #pragma once
 
 #include "cyhal.h"
@@ -39,9 +31,8 @@
 extern "C" {
 #endif
 
-
 /**
-* \addtogroup group_bsp_cy8ckit_062s2_43012_macros
+* \addtogroup group_bsp_pins Pin Mappings
 * \{
 */
 
@@ -98,18 +89,25 @@ extern "C" {
 #define CYBSP_WCO_OUT          P0_1
 
 /** Pin: WIFI SDIO D0 */
+/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D0     P2_0
 /** Pin: WIFI SDIO D1 */
+/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D1     P2_1
 /** Pin: WIFI SDIO D2 */
+/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D2     P2_2
 /** Pin: WIFI SDIO D3 */
+/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D3     P2_3
 /** Pin: WIFI SDIO CMD */
+/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */
 #define CYBSP_WIFI_SDIO_CMD    P2_4
 /** Pin: WIFI SDIO CLK */
+/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */
 #define CYBSP_WIFI_SDIO_CLK    P2_5
 /** Pin: WIFI ON */
+/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */
 #define CYBSP_WIFI_WL_REG_ON   P2_6
 /** Pin: WIFI Host Wakeup */
 #define CYBSP_WIFI_HOST_WAKE   P4_1
@@ -125,17 +123,21 @@ extern "C" {
 /** Pin: BT Power */
 #define CYBSP_BT_POWER         P3_4
 /** Pin: BT Host Wakeup */
-#define CYBSP_BT_HOST_WAKE     P3_5
+#define CYBSP_BT_HOST_WAKE     P4_0
 /** Pin: BT Device Wakeup */
-#define CYBSP_BT_DEVICE_WAKE   P4_0
+#define CYBSP_BT_DEVICE_WAKE   P3_5
 
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
 #define CYBSP_DEBUG_UART_RX    P5_0
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
 #define CYBSP_DEBUG_UART_TX    P5_1
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[2], scb[5] */
 #define CYBSP_DEBUG_UART_RTS   P5_2
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[3], scb[5] */
 #define CYBSP_DEBUG_UART_CTS   P5_3
 
 /** Pin: I2C SCL */
@@ -150,8 +152,8 @@ extern "C" {
 /** Pin: SWDCK */
 #define CYBSP_SWDCK            P6_7
 
-/** Pin: CapSesnse TX */
-#define CYBSP_CSD_TX           P1_0
+/** Pin: CapSesnse RX */
+#define CYBSP_CSD_RX           P1_0
 /** Pin: CapSesnse CINA */
 #define CYBSP_CINA             P7_1
 /** Pin: CapSesnse CINB */
@@ -218,10 +220,10 @@ extern "C" {
 #define SW4                    P1_4
 
 
-/** \} group_bsp_cy8ckit_062s2_43012_macros */
+/** \} group_bsp_cy8ckit_pins */
 
 /**
-* \addtogroup group_bsp_cy8ckit_062s2_43012_enums
+* \addtogroup group_bsp_enums Enumerated Types
 * \{
 */
 
@@ -247,10 +249,15 @@ typedef enum
     CYBSP_LED_RGB_GREEN = LED5_RGB_G,
     CYBSP_LED_RGB_BLUE = LED5_RGB_B,
 
+    /* Corresponds to: ioss[0].port[11].pin[1] */
     CYBSP_USER_LED1 = LED9_R,
+    /* Corresponds to: ioss[0].port[1].pin[5] */
     CYBSP_USER_LED2 = LED8_O,
+    /* Corresponds to: ioss[0].port[1].pin[1] */
     CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
+    /* Corresponds to: ioss[0].port[0].pin[5] */
     CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
+    /* Corresponds to: ioss[0].port[7].pin[3] */
     CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
     CYBSP_USER_LED = CYBSP_USER_LED1,
 } cybsp_led_t;
@@ -259,16 +266,16 @@ typedef enum
 /** Enum defining the different user buttons available on the board. */
 typedef enum
 {
+    /* Corresponds to: ioss[0].port[0].pin[4] */
     CYBSP_USER_BTN1 = SW2,
+    /* Corresponds to: ioss[0].port[1].pin[4] */
     CYBSP_USER_BTN2 = SW4,
     CYBSP_USER_BTN = CYBSP_USER_BTN1,
 } cybsp_btn_t;
 
 
-/** \} group_bsp_cy8ckit_062s2_43012_enums */
+/** \} group_bsp_enums */
 
 #if defined(__cplusplus)
 }
 #endif
-
-/** \} group_bsp_cy8ckit_062s2_43012 */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -0,0 +1,24 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -24,18 +24,37 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
 
 void init_cycfg_clocks(void)
 {
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -38,9 +41,13 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_clocks(void);
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -24,6 +24,14 @@
 
 #include "cycfg_peripherals.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BLE_obj = 
+	{
+		.type = CYHAL_RSC_BLESS,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 cy_stc_csd_context_t cy_csd_0_context = 
 {
 	.lockKey = CY_CSD_NONE_KEY,
@@ -36,34 +44,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 8,
-	.enableMsbFirst = false,
-	.dataWidth = 8UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = false,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rtsRxFifoLevel = 0UL,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -71,6 +59,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = 
 {
 	.c0Match = 32768U,
@@ -84,6 +80,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT0_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -96,13 +100,38 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
 {
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BLE_obj);
+#endif //defined (CY_USING_HAL)
+
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -26,11 +26,14 @@
 #define CYCFG_PERIPHERALS_H
 
 #include "cycfg_notices.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_ezi2c.h"
-#include "cy_scb_uart.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 
@@ -85,9 +88,6 @@ extern "C" {
 #define CYBSP_CSD_COMM_ENABLED 1U
 #define CYBSP_CSD_COMM_HW SCB3
 #define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -118,12 +118,26 @@ extern "C" {
 #define CYBSP_RTC_10_YEAR_OFFSET (4U)
 #define CYBSP_RTC_YEAR_OFFSET (0U)
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BLE_obj;
+#endif //defined (CY_USING_HAL)
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_RED_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_BTN2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_BTN2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_BLUE_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = 
 {
 	.outVal = 1,
@@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = 
 {
 	.outVal = 1,
@@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = 
 {
 	.outVal = 1,
@@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = 
 {
 	.outVal = 1,
@@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = 
 {
 	.outVal = 1,
@@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = 
 {
 	.outVal = 1,
@@ -200,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED9_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED9_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
 {
 	.outVal = 1,
@@ -232,70 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_GREEN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED8_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED8_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_TX_PORT_NUM,
+		.channel_num = CYBSP_CSD_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -312,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -328,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -344,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -360,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
 {
 	.outVal = 1,
@@ -376,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDCK_PORT_NUM,
+		.channel_num = CYBSP_SWDCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
 {
 	.outVal = 1,
@@ -392,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINA_PORT_NUM,
+		.channel_num = CYBSP_CINA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
 {
 	.outVal = 1,
@@ -408,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINB_PORT_NUM,
+		.channel_num = CYBSP_CINB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -424,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -440,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -456,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -472,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -488,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -504,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -520,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -536,60 +592,124 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
-
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -0,0 +1,720 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PORT_NUM 11U
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PORT_NUM 11U
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PORT_NUM 11U
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PORT_NUM 11U
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PORT_NUM 11U
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PORT_NUM 11U
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PORT_NUM 1U
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -24,10 +24,10 @@
 
 #include "cycfg_qspi_memslot.h"
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
+    .command = 0xECU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xD8U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
+    .command = 0x34U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
     .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 520U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 134000U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 340U
+    .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
     /* The base address the memory slave is mapped to in the PSoC memory map.
@@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
     .baseAddress = 0x18000000U,
     /* The size allocated in the PSoC memory map, for the memory slave device.
     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
+    .memMappedSize = 0x4000000U,
     /* If this memory device is one of the devices in the dual quad SPI configuration.
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
 };
 
-const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
-   &S25FL512S_SlaveSlot_0
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
@@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
     /* The version of the SMIF driver. */
     .minorVersion = CY_SMIF_DRV_VERSION_MINOR
 };
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -28,22 +28,23 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
-extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
 
 
 #endif /*CY_SMIF_MEMCONFIG_H*/
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -40,9 +40,7 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@@ -50,11 +48,11 @@ void init_cycfg_routing(void);
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -83,6 +83,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
 	.cco_Freq = 355U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 4U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
 {
 	.feedbackDiv = 30,
@@ -523,4 +563,24 @@ void init_cycfg_system(void)
 	
 	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
 	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -29,6 +29,9 @@
 #include "cy_sysclk.h"
 #include "cy_ble_clk.h"
 #include "cy_systick.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_gpio.h"
 #include "cy_syspm.h"
 
@@ -81,6 +84,22 @@ extern "C" {
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_system(void);
 
 #if defined(__cplusplus)

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg

@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense

@@ -0,0 +1,409 @@
+<?xml version="1.0"?>
+<Configuration major="2" minor="0">
+    <!--
+       File Name: cycfg_capsense.cycapsense 
+
+       Description: 
+       CapSense middleware configuration 
+       This file should not be modified. It was automatically generated by 
+       CapSense Configurator 2.0.0 build 351 
+-->
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -0,0 +1,567 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
+    <ToolInfo version="1.0.0"/>
+    <Devices>
+        <Device mpn="CY8C6347BZI-BLD53">
+            <BlockConfig>
+                <Block location="bless[0]" alias="CYBSP_BLE" template="mxs40ble" version="1.1">
+                    <Param id="BleSharing" value="0"/>
+                    <Param id="ExtPaLnaEnable" value="false"/>
+                </Block>
+                <Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
+                    <Param id="dbgMode" value="SWD"/>
+                    <Param id="traceEnable" value="false"/>
+                </Block>
+                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
+                    <Param id="CapSenseEnable" value="true"/>
+                    <Param id="CapSenseCore" value="4"/>
+                    <Param id="SensorCount" value="12"/>
+                    <Param id="CapacitorCount" value="3"/>
+                    <Param id="SensorName0" value="Cmod"/>
+                    <Param id="SensorName1" value="CintA"/>
+                    <Param id="SensorName2" value="CintB"/>
+                    <Param id="SensorName3" value="Button0_Rx0"/>
+                    <Param id="SensorName4" value="Button0_Tx"/>
+                    <Param id="SensorName5" value="Button1_Rx0"/>
+                    <Param id="SensorName6" value="Button1_Tx"/>
+                    <Param id="SensorName7" value="LinearSlider0_Sns0"/>
+                    <Param id="SensorName8" value="LinearSlider0_Sns1"/>
+                    <Param id="SensorName9" value="LinearSlider0_Sns2"/>
+                    <Param id="SensorName10" value="LinearSlider0_Sns3"/>
+                    <Param id="SensorName11" value="LinearSlider0_Sns4"/>
+                    <Param id="CapSenseConfigurator" value="0"/>
+                    <Param id="CapSenseTuner" value="0"/>
+                    <Param id="CsdAdcEnable" value="false"/>
+                    <Param id="numChannels" value="1"/>
+                    <Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
+                    <Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
+                    <Param id="acqTime" value="10"/>
+                    <Param id="autoCalibrInterval" value="30"/>
+                    <Param id="vref" value="-1"/>
+                    <Param id="operClkDivider" value="1"/>
+                    <Param id="azTime" value="5"/>
+                    <Param id="csdInitTime" value="25"/>
+                    <Param id="inFlash" value="true"/>
+                    <Param id="CsdIdacEnable" value="false"/>
+                    <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
+                    <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
+                    <Param id="csdIdacInitTime" value="25"/>
+                    <Param id="idacInFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[0]" alias="CYBSP_WCO_IN" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[1]" alias="CYBSP_WCO_OUT" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[1]" alias="CYBSP_EZI2C_SDA" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWDCK" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[1]" alias="CYBSP_CINA" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[2]" alias="CYBSP_CINB" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[1]" alias="CYBSP_CSD_BTN0" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[2]" alias="CYBSP_CSD_BTN1" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[3]" alias="CYBSP_CSD_SLD0" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[4]" alias="CYBSP_CSD_SLD1" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[5]" alias="CYBSP_CSD_SLD2" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[6]" alias="CYBSP_CSD_SLD3" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[7]" alias="CYBSP_CSD_SLD4" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="256"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="8"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
+                    <Param id="DataRate" value="100"/>
+                    <Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
+                    <Param id="SlaveAddress1" value="8"/>
+                    <Param id="SlaveAddress2" value="9"/>
+                    <Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
+                    <Param id="EnableWakeup" value="false"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
+                    <Param id="configurator" value="0"/>
+                    <Param id="isrAlignment" value="false"/>
+                    <Param id="isrUnderflow" value="false"/>
+                    <Param id="isrCmdOverflow" value="false"/>
+                    <Param id="isrDataOverflow" value="false"/>
+                    <Param id="rxTriggerLevel" value="0"/>
+                    <Param id="txTriggerLevel" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
+                <Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
+                    <Param id="sourceClock" value="lfclk"/>
+                </Block>
+                <Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
+                    <Param id="sourceClock" value="wco"/>
+                </Block>
+                <Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="100.000"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="0"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="0"/>
+                    <Param id="divider" value="2"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
+                    <Param id="hibernate" value="true"/>
+                </Block>
+                <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
+                    <Param id="trim" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
+                    <Param id="sourceClock" value="wco"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
+                    <Param id="lowFrequencyMode" value="false"/>
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="48.000"/>
+                    <Param id="optimization" value="MinPower"/>
+                </Block>
+                <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                    <Param id="timerDivider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
+                    <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
+                    <Param id="clockLostDetection" value="false"/>
+                    <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
+                    <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
+                    <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
+                    <Param id="accuracyPpm" value="150"/>
+                </Block>
+                <Block location="srss[0].mcwdt[0]" alias="CYBSP_MCWDT0" template="mxs40mcwdt" version="1.0">
+                    <Param id="C0ClearOnMatch" value="FREE_RUNNING"/>
+                    <Param id="C0Match" value="32768"/>
+                    <Param id="C0Mode" value="CY_MCWDT_MODE_NONE"/>
+                    <Param id="C1ClearOnMatch" value="FREE_RUNNING"/>
+                    <Param id="C1Match" value="32768"/>
+                    <Param id="C1Mode" value="CY_MCWDT_MODE_NONE"/>
+                    <Param id="C2Mode" value="CY_MCWDT_MODE_NONE"/>
+                    <Param id="C2Period" value="16"/>
+                    <Param id="CascadeC0C1" value="true"/>
+                    <Param id="CascadeC1C2" value="false"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
+                    <Param id="pwrEstimator" value="0"/>
+                    <Param id="pwrMode" value="LDO_1_1"/>
+                    <Param id="actPwrMode" value="LP"/>
+                    <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
+                    <Param id="pmicEnable" value="false"/>
+                    <Param id="backupSrc" value="VDDD"/>
+                    <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
+                    <Param id="deepsleepLatency" value="0"/>
+                    <Param id="vddaMv" value="3300"/>
+                    <Param id="vdddMv" value="3300"/>
+                    <Param id="vBackupMv" value="3300"/>
+                    <Param id="vddNsMv" value="3300"/>
+                    <Param id="vddio0Mv" value="3300"/>
+                    <Param id="vddio1Mv" value="3300"/>
+                </Block>
+                <Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
+                    <Param id="format" value="0"/>
+                    <Param id="dst" value="false"/>
+                    <Param id="dstFormat" value="CY_RTC_DST_RELATIVE"/>
+                    <Param id="sec" value="0"/>
+                    <Param id="min" value="0"/>
+                    <Param id="hrFormat" value="CY_RTC_24_HOURS"/>
+                    <Param id="hr" value="12"/>
+                    <Param id="amPmPeriodOfDay" value="CY_RTC_AM"/>
+                    <Param id="dayOfTheWeek" value="CY_RTC_SUNDAY"/>
+                    <Param id="dayOfTheMonth" value="1"/>
+                    <Param id="month" value="CY_RTC_JANUARY"/>
+                    <Param id="year" value="0"/>
+                    <Param id="dstStartMonth" value="CY_RTC_MARCH"/>
+                    <Param id="dstStartDay" value="22"/>
+                    <Param id="dstStartWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
+                    <Param id="dstStartDayOfWeek" value="CY_RTC_SUNDAY"/>
+                    <Param id="dstStartHour" value="0"/>
+                    <Param id="dstStopMonth" value="CY_RTC_OCTOBER"/>
+                    <Param id="dstStopDay" value="22"/>
+                    <Param id="dstStopWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
+                    <Param id="dstStopDayOfWeek" value="CY_RTC_SUNDAY"/>
+                    <Param id="dstStopHour" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+            </BlockConfig>
+            <Netlist>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
+                    <Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
+                    <Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
+                </Net>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
+                    <Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
+                </Net>
+                <Net>
+                    <Port name="csd[0].csd[0].clock[0]"/>
+                    <Port name="peri[0].div_8[0].clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
+                    <Port name="scb[3].i2c_scl[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[6].pin[1].digital_inout[0]"/>
+                    <Port name="scb[3].i2c_sda[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
+                    <Port name="smif[0].spi_select0[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
+                    <Port name="smif[0].spi_data3[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
+                    <Port name="smif[0].spi_data2[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
+                    <Port name="smif[0].spi_data1[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
+                    <Port name="smif[0].spi_data0[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
+                    <Port name="smif[0].spi_clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_8[1].clk[0]"/>
+                    <Port name="scb[3].clock[0]"/>
+                </Net>
+                <Net>
+                    <Port name="smif[0].clk_hf[0]"/>
+                    <Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="smif[0].clk_if[0]"/>
+                    <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
+                </Net>
+                <Mux name="sense" location="csd[0].csd[0]">
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[7].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[2].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[2].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[3].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[4].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[5].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[6].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[7].analog[0]"/>
+                    </Arm>
+                </Mux>
+            </Netlist>
+        </Device>
+    </Devices>
+    <Libraries>
+        <Library name="psoc6sw" version="1.2"/>
+    </Libraries>
+    <ConfiguratorData/>
+</Design>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h

@@ -1,429 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_RED_ENABLED 1U
-#define CYBSP_LED_RED_PORT GPIO_PRT0
-#define CYBSP_LED_RED_PIN 3U
-#define CYBSP_LED_RED_NUM 3U
-#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_RED_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_3_HSIOM
-	#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_BTN2_ENABLED 1U
-#define CYBSP_BTN2_PORT GPIO_PRT0
-#define CYBSP_BTN2_PIN 4U
-#define CYBSP_BTN2_NUM 4U
-#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_BTN2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_BLUE_ENABLED 1U
-#define CYBSP_LED_BLUE_PORT GPIO_PRT11
-#define CYBSP_LED_BLUE_PIN 1U
-#define CYBSP_LED_BLUE_NUM 1U
-#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
-	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SS_ENABLED 1U
-#define CYBSP_QSPI_SS_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS_PIN 2U
-#define CYBSP_QSPI_SS_NUM 2U
-#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D3_ENABLED 1U
-#define CYBSP_QSPI_D3_PORT GPIO_PRT11
-#define CYBSP_QSPI_D3_PIN 3U
-#define CYBSP_QSPI_D3_NUM 3U
-#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D2_ENABLED 1U
-#define CYBSP_QSPI_D2_PORT GPIO_PRT11
-#define CYBSP_QSPI_D2_PIN 4U
-#define CYBSP_QSPI_D2_NUM 4U
-#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D1_ENABLED 1U
-#define CYBSP_QSPI_D1_PORT GPIO_PRT11
-#define CYBSP_QSPI_D1_PIN 5U
-#define CYBSP_QSPI_D1_NUM 5U
-#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D0_ENABLED 1U
-#define CYBSP_QSPI_D0_PORT GPIO_PRT11
-#define CYBSP_QSPI_D0_PIN 6U
-#define CYBSP_QSPI_D0_NUM 6U
-#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SCK_ENABLED 1U
-#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SCK_PIN 7U
-#define CYBSP_QSPI_SCK_NUM 7U
-#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_LED9_ENABLED 1U
-#define CYBSP_LED9_PORT GPIO_PRT13
-#define CYBSP_LED9_PIN 7U
-#define CYBSP_LED9_NUM 7U
-#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED9_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_7_HSIOM
-	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED_GREEN_ENABLED 1U
-#define CYBSP_LED_GREEN_PORT GPIO_PRT1
-#define CYBSP_LED_GREEN_PIN 1U
-#define CYBSP_LED_GREEN_NUM 1U
-#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
-	#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED8_ENABLED 1U
-#define CYBSP_LED8_PORT GPIO_PRT1
-#define CYBSP_LED8_PIN 5U
-#define CYBSP_LED8_NUM 5U
-#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED8_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg

@@ -1,2 +0,0 @@
-set SMIF_BANKS {
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c

@@ -91,7 +91,9 @@ const PinMap PinMap_I2C_SCL[] = {
     {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
     {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
     {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
+    {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
     {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
+    {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
     {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
     {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
     {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
@@ -106,7 +108,9 @@ const PinMap PinMap_I2C_SDA[] = {
     {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
     {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
     {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
+    {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
     {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
+    {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
     {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
     {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
     {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
@@ -125,7 +129,9 @@ const PinMap PinMap_SPI_MOSI[] = {
     {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
     {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
     {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
+    {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
     {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
+    {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
     {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
     {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
     {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@@ -140,7 +146,9 @@ const PinMap PinMap_SPI_MISO[] = {
     {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
     {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
     {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
+    {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
     {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
+    {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
     {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
     {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
     {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@@ -155,9 +163,10 @@ const PinMap PinMap_SPI_SCLK[] = {
     {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
     {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
     {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
+    {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
     {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
+    {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
     {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
-
     {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
     {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
     {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
@@ -170,7 +179,9 @@ const PinMap PinMap_SPI_SSEL[] = {
     {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
     {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
     {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
+    {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
     {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
+    {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
     {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
     {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
     {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@@ -360,7 +371,6 @@ const PinMap PinMap_ADC[] = {
 #if DEVICE_ANALOGOUT
 const PinMap PinMap_DAC[] = {
     {P9_6,  DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)},  // CTDAC connects to the P10_5 pin through the AMUXA bus
     {NC,    NC,     0}
 };
 #endif // DEVICE_ANALOGIN

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PinNames.h

@@ -20,38 +20,8 @@
 #ifndef MBED_PINNAMES_H
 #define MBED_PINNAMES_H
 
-#include "cmsis.h"
 #include "PinNamesTypes.h"
-#include "PortNames.h"
 #include "cyhal_pin_package.h"
-#include "cyhal_utils.h"
-
-typedef cyhal_gpio_t PinName;
-
-// Arduino connector namings
-#define A0 P10_0
-#define A1 P10_1
-#define A2 P10_2
-#define A3 P10_3
-#define A4 P10_4
-#define A5 P10_5
-
-#define D0 P5_0
-#define D1 P5_1
-#define D2 P5_2
-#define D3 P5_3
-#define D4 P5_4
-#define D5 P5_5
-#define D6 P5_6
-#define D7 P0_2
-#define D8 P13_0
-#define D9 P13_1
-#define D10 P12_3
-#define D11 P12_0
-#define D12 P12_1
-#define D13 P12_2
-#define D14 P6_1
-#define D15 P6_0
 
 // Generic signal names
 
@@ -68,17 +38,16 @@ typedef cyhal_gpio_t PinName;
 #define UART_RTS P5_2
 #define UART_CTS P5_3
 
-#define SWITCH2 P0_4
 #define LED1 P0_3
 #define LED2 P1_1
 #define LED3 P11_1
 #define LED4 P1_5
 #define LED5 P13_7
-
 #define LED_RED LED1
 #define LED_BLUE LED3
 #define LED_GREEN LED2
 
+#define SWITCH2 P0_4
 #define USER_BUTTON SWITCH2
 #define BUTTON1 USER_BUTTON
 
@@ -102,11 +71,6 @@ typedef cyhal_gpio_t PinName;
 #define STDIO_UART_CTS UART_CTS
 #define STDIO_UART_RTS UART_RTS
 
-#define CY_STDIO_UART_RX STDIO_UART_RX
-#define CY_STDIO_UART_TX STDIO_UART_TX
-#define CY_STDIO_UART_CTS STDIO_UART_CTS
-#define CY_STDIO_UART_RTS STDIO_UART_RTS
-
 #define USBTX UART_TX
 #define USBRX UART_RX
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c

@@ -0,0 +1,82 @@
+/***************************************************************************//**
+* \file CY8CKIT-062-BLE/cybsp.c
+*
+* Description:
+* Provides basic hardware initialization for the CY8CKIT-062-BLE pioneer kit.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cybsp.h"
+#include "cycfg_system.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+cy_rslt_t cybsp_init(void)
+{
+    cy_rslt_t result;
+
+    result = cyhal_hwmgr_init();
+    init_cycfg_system();
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        result = cybsp_register_sysclk_pm_callback();
+    }
+
+#ifndef __MBED__
+    if (CY_RSLT_SUCCESS == result)
+    {
+        /* Initialize User LEDs */
+        /* Reserves: CYBSP_USER_LED1 */
+        result |= cybsp_led_init(CYBSP_USER_LED1);
+        /* Reserves: CYBSP_USER_LED2 */
+        result |= cybsp_led_init(CYBSP_USER_LED2);
+        /* Reserves: CYBSP_USER_LED3 */
+        result |= cybsp_led_init(CYBSP_USER_LED3);
+        /* Reserves: CYBSP_USER_LED4 */
+        result |= cybsp_led_init(CYBSP_USER_LED4);
+        /* Reserves: CYBSP_USER_LED5 */
+        result |= cybsp_led_init(CYBSP_USER_LED5);
+        /* Initialize User Buttons */
+        /* Reserves: CYBSP_USER_BTN1 */
+        result |= cybsp_btn_init(CYBSP_USER_BTN1);
+        CY_ASSERT(CY_RSLT_SUCCESS == result);
+
+        /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
+        if (CY_RSLT_SUCCESS == result)
+        {
+           /* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance and one of available
+            *   clock dividers */
+            result = cybsp_retarget_init();
+        }
+    }
+#endif /* __MBED__ */
+
+    /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
+    *   user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
+    *   (cyreservedresources.list) to make sure no resources are reserved by both. */
+    return result;
+}
+
+#if defined(__cplusplus)
+}
+#endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h

@@ -1,5 +1,5 @@
 /***************************************************************************//**
-* \file cybsp_cy8ckit_062_ble.c
+* \file CY8CKIT-062-BLE/cybsp.h
 *
 * Description:
 * Provides APIs for interacting with the hardware contained on the Cypress
@@ -23,45 +23,20 @@
 * limitations under the License.
 *******************************************************************************/
 
-#include <stdlib.h>
-#include "cybsp_cy8ckit_062_ble.h"
-#include "cyhal_implementation.h"
-#include "cycfg.h"
+#pragma once
+
+#include "cybsp_types.h"
+#include "cybsp_core.h"
+#ifndef __MBED__
+#include "cybsp_retarget.h"
+#include "cybsp_serial_flash.h"
+#include "cybsp_rgb_led.h"
+#endif /* __MBED__ */
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
-cy_rslt_t cybsp_init(void)
-{
-	init_cycfg_system();
-
-    cy_rslt_t result = CY_RSLT_SUCCESS;
-
-#ifndef __MBED__
-    /* Initialize User LEDs */
-    result |= cybsp_led_init(CYBSP_USER_LED1);
-    result |= cybsp_led_init(CYBSP_USER_LED2);
-    result |= cybsp_led_init(CYBSP_USER_LED3);
-    result |= cybsp_led_init(CYBSP_USER_LED4);
-    result |= cybsp_led_init(CYBSP_USER_LED5);
-    /* Initialize User Buttons */
-    result |= cybsp_btn_init(CYBSP_USER_BTN1);
-
-    CY_ASSERT(CY_RSLT_SUCCESS == result);
-#endif
-
-#if defined(CYBSP_RETARGET_ENABLED)
-    /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
-    if (CY_RSLT_SUCCESS == result)
-    {
-        result = cybsp_retarget_init();
-    }
-#endif
-
-    return result;
-}
-
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h

@@ -23,27 +23,65 @@
 * limitations under the License.
 *******************************************************************************/
 
-/**
-* \addtogroup group_bsp_cy8ckit_062_ble CY8CKIT-062-BLE
-* \ingroup group_bsp
-* \{
-* \defgroup group_bsp_cy8ckit_062_ble_macros Macros
-* \defgroup group_bsp_cy8ckit_062_ble_enums Enumerated Types
-*/
-
 #pragma once
 
-#include "cyhal.h"
+#include "cyhal_pin_package.h"
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
 /**
-* \addtogroup group_bsp_cy8ckit_062_ble_macros
+* \addtogroup group_bsp_pins Pin Mappings
 * \{
 */
 
+// Arduino connector namings
+/** Arduino A0 */
+#define CYBSP_A0 P10_0
+/** Arduino A1 */
+#define CYBSP_A1 P10_1
+/** Arduino A2 */
+#define CYBSP_A2 P10_2
+/** Arduino A3 */
+#define CYBSP_A3 P10_3
+/** Arduino A4 */
+#define CYBSP_A4 P10_4
+/** Arduino A5 */
+#define CYBSP_A5 P10_5
+/** Arduino D0 */
+#define CYBSP_D0 P5_0
+/** Arduino D1 */
+#define CYBSP_D1 P5_1
+/** Arduino D2 */
+#define CYBSP_D2 P5_2
+/** Arduino D3 */
+#define CYBSP_D3 P5_3
+/** Arduino D4 */
+#define CYBSP_D4 P5_4
+/** Arduino D5 */
+#define CYBSP_D5 P5_5
+/** Arduino D6 */
+#define CYBSP_D6 P5_6
+/** Arduino D7 */
+#define CYBSP_D7 P0_2
+/** Arduino D8 */
+#define CYBSP_D8 P13_0
+/** Arduino D9 */
+#define CYBSP_D9 P13_1
+/** Arduino D10 */
+#define CYBSP_D10 P12_3
+/** Arduino D11 */
+#define CYBSP_D11 P12_0
+/** Arduino D12 */
+#define CYBSP_D12 P12_1
+/** Arduino D13 */
+#define CYBSP_D13 P12_2
+/** Arduino D14 */
+#define CYBSP_D14 P6_1
+/** Arduino D15 */
+#define CYBSP_D15 P6_0
+
 // Generic signal names
 /** Pin: WCO input */
 #define CYBSP_WCO_IN           P0_0
@@ -51,8 +89,10 @@ extern "C" {
 #define CYBSP_WCO_OUT          P0_1
 
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
 #define CYBSP_DEBUG_UART_RX    P5_0
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
 #define CYBSP_DEBUG_UART_TX    P5_1
 
 /** Pin: I2C SCL */
@@ -103,25 +143,25 @@ extern "C" {
 /** Pin: QUAD SPI SCK */
 #define CYBSP_QSPI_SCK         P11_7
 
-/** \} group_bsp_cy8ckit_062_ble_macros */
+/** \} group_bsp_pins */
 
 /**
-* \addtogroup group_bsp_cy8ckit_062_ble_enums
+* \addtogroup group_bsp_enums Enumerated Types
 * \{
 */
 
 /** Enum defining the different states for the LED. */
 typedef enum
 {
-	CYBSP_LED_STATE_ON        	= 0,
-	CYBSP_LED_STATE_OFF        	= 1,
+    CYBSP_LED_STATE_ON          = 0,
+    CYBSP_LED_STATE_OFF         = 1,
 } cybsp_led_state_t;
 
 /** Enum defining the different states for a button. */
 typedef enum
 {
-	CYBSP_BTN_PRESSED  	      	= 0,
-	CYBSP_BTN_OFF	          	= 1,
+    CYBSP_BTN_PRESSED           = 0,
+    CYBSP_BTN_OFF               = 1,
 } cybsp_btn_state_t;
 
 /** Enum defining the different LED pins on the board. */
@@ -133,10 +173,15 @@ typedef enum
     CYBSP_LED_RGB_GREEN = P1_1,
     CYBSP_LED_RGB_BLUE = P11_1,
 
+    /* Corresponds to: ioss[0].port[1].pin[5] */
     CYBSP_USER_LED1 = CYBSP_LED8,
+    /* Corresponds to: ioss[0].port[13].pin[7] */
     CYBSP_USER_LED2 = CYBSP_LED9,
+    /* Corresponds to: ioss[0].port[0].pin[3] */
     CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
+    /* Corresponds to: ioss[0].port[1].pin[1] */
     CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
+    /* Corresponds to: ioss[0].port[11].pin[1] */
     CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
     CYBSP_USER_LED = CYBSP_USER_LED1,
 } cybsp_led_t;
@@ -146,14 +191,13 @@ typedef enum
 {
     CYBSP_SW2 = P0_4,
 
+    /* Corresponds to: ioss[0].port[0].pin[4] */
     CYBSP_USER_BTN1 = CYBSP_SW2,
     CYBSP_USER_BTN = CYBSP_USER_BTN1,
 } cybsp_btn_t;
 
-/** \} group_bsp_cy8ckit_062_ble_enums */
+/** \} group_bsp_enums */
 
 #if defined(__cplusplus)
 }
 #endif
-
-/** \} group_bsp_cy8ckit_062_ble */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct

@@ -3,7 +3,7 @@
 ; to pass a scatter file through a C preprocessor.
 
 ;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.scat
+;* \file cy8c6xx7_cm4_dual.sct
 ;* \version 2.50
 ;*
 ;* Linker file for the ARMCC.
@@ -173,7 +173,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
     RW_RAM_DATA +0
     {
         * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
+        * (+RW, +ZI)
     }
 
     ; Place variables in the section that should not be initialized during the

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -28,6 +28,7 @@ void init_cycfg_all(void)
 {
 	init_cycfg_system();
 	init_cycfg_clocks();
+	init_cycfg_dmas();
 	init_cycfg_routing();
 	init_cycfg_peripherals();
 	init_cycfg_pins();

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -0,0 +1,24 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -0,0 +1,105 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_USB_CLK_DIV_HW,
+		.channel_num = CYBSP_USB_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_SDIO_DIV_HW,
+		.channel_num = CYBSP_SDIO_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t peri_0_div_8_4_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = peri_0_div_8_4_HW,
+		.channel_num = peri_0_div_8_4_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
+#endif //defined (CY_USING_HAL)
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -41,12 +44,28 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_CLK_DIV_NUM 3U
+#define peri_0_div_8_4_ENABLED 1U
+#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_4_NUM 4U
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_clocks(void);
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c

@@ -62,6 +62,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 0U,
+		.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_16CYC,
@@ -100,6 +108,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 0U,
+		.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_4CYC,
@@ -138,6 +154,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 1U,
+		.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_IM,
@@ -176,4 +200,31 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 1U,
+		.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 
+
+void init_cycfg_dmas(void)
+{
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
+#endif //defined (CY_USING_HAL)
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h

@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_dma.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -34,34 +37,47 @@ extern "C" {
 
 #define cpuss_0_dw0_0_chan_0_ENABLED 1U
 #define cpuss_0_dw0_0_chan_0_HW DW0
-#define cpuss_0_dw0_0_chan_0_CHANNEL 0
+#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
 #define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
 #define cpuss_0_dw0_0_chan_1_ENABLED 1U
 #define cpuss_0_dw0_0_chan_1_HW DW0
-#define cpuss_0_dw0_0_chan_1_CHANNEL 1
+#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
 #define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
 #define cpuss_0_dw1_0_chan_1_ENABLED 1U
 #define cpuss_0_dw1_0_chan_1_HW DW1
-#define cpuss_0_dw1_0_chan_1_CHANNEL 1
+#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
 #define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
 #define cpuss_0_dw1_0_chan_3_ENABLED 1U
 #define cpuss_0_dw1_0_chan_3_HW DW1
-#define cpuss_0_dw1_0_chan_3_CHANNEL 3
+#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
 #define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
 
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
+#endif //defined (CY_USING_HAL)
 
+void init_cycfg_dmas(void);
 
 #if defined(__cplusplus)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -70,6 +70,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
 	.txFifoTriggerLevel = 63UL,
 	.txFifoIntEnableMask = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
 {
 	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -78,34 +86,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 8,
-	.enableMsbFirst = false,
-	.dataWidth = 8UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = false,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rtsRxFifoLevel = 0UL,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -113,6 +101,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = 
 {
 	.c0Match = 32768U,
@@ -126,6 +122,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT0_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -138,6 +142,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = 
 {
 	.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
@@ -155,19 +167,44 @@ const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
 	.enableLpm = false,
 	.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USBUART_obj = 
+	{
+		.type = CYHAL_RSC_USB,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
 {
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -29,8 +29,12 @@
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_uart.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_scb_ezi2c.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 #include "cy_usbfs_dev_drv.h"
@@ -81,9 +85,6 @@ extern "C" {
 #define CYBSP_CSD_COMM_ENABLED 1U
 #define CYBSP_CSD_COMM_HW SCB3
 #define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -113,7 +114,6 @@ extern "C" {
 #define CYBSP_RTC_100_YEAR_OFFSET (8U)
 #define CYBSP_RTC_10_YEAR_OFFSET (4U)
 #define CYBSP_RTC_YEAR_OFFSET (0U)
-#define CYBSP_SDIO_ENABLED 1U
 #define CYBSP_USBUART_ENABLED 1U
 #define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
 #define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
@@ -126,12 +126,29 @@ extern "C" {
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_RED_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_BTN2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_BTN2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_BLUE_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = 
 {
 	.outVal = 1,
@@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = 
 {
 	.outVal = 1,
@@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = 
 {
 	.outVal = 1,
@@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = 
 {
 	.outVal = 1,
@@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = 
 {
 	.outVal = 1,
@@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = 
 {
 	.outVal = 1,
@@ -200,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED9_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED9_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = 
 {
 	.outVal = 1,
@@ -232,6 +232,14 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = ioss_0_port_14_pin_0_PORT_NUM,
+		.channel_num = ioss_0_port_14_pin_0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = 
 {
 	.outVal = 1,
@@ -248,6 +256,14 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = ioss_0_port_14_pin_1_PORT_NUM,
+		.channel_num = ioss_0_port_14_pin_1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
 {
 	.outVal = 1,
@@ -264,150 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_GREEN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED8_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED8_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config = 
-{
-	.outVal = 0,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_WIFI_WL_REG_ON_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_TX_PORT_NUM,
+		.channel_num = CYBSP_CSD_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = 
 {
 	.outVal = 0,
@@ -424,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = 
 {
 	.outVal = 1,
@@ -440,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = 
 {
 	.outVal = 1,
@@ -456,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_TX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = 
 {
 	.outVal = 1,
@@ -472,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = 
 {
 	.outVal = 1,
@@ -488,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_CTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = 
 {
 	.outVal = 1,
@@ -504,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_POWER_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_POWER_PORT_NUM,
+		.channel_num = CYBSP_BT_POWER_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = 
 {
 	.outVal = 0,
@@ -520,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = 
 {
 	.outVal = 0,
@@ -536,38 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -584,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -600,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -616,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -632,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
 {
 	.outVal = 1,
@@ -648,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDCK_PORT_NUM,
+		.channel_num = CYBSP_SWDCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
 {
 	.outVal = 1,
@@ -664,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINA_PORT_NUM,
+		.channel_num = CYBSP_CINA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
 {
 	.outVal = 1,
@@ -680,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINB_PORT_NUM,
+		.channel_num = CYBSP_CINB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -696,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -712,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -728,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -744,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -760,6 +760,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -776,6 +784,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -792,6 +808,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -808,94 +832,174 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&ioss_0_port_14_pin_0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&ioss_0_port_14_pin_1_obj);
+#endif //defined (CY_USING_HAL)
 
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -0,0 +1,998 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PORT_NUM 11U
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PORT_NUM 11U
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PORT_NUM 11U
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PORT_NUM 11U
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PORT_NUM 11U
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PORT_NUM 11U
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define ioss_0_port_14_pin_0_ENABLED 1U
+#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
+#define ioss_0_port_14_pin_0_PORT_NUM 14U
+#define ioss_0_port_14_pin_0_PIN 0U
+#define ioss_0_port_14_pin_0_NUM 0U
+#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_0_HSIOM
+	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_PORT_PIN P14_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define ioss_0_port_14_pin_1_ENABLED 1U
+#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
+#define ioss_0_port_14_pin_1_PORT_NUM 14U
+#define ioss_0_port_14_pin_1_PIN 1U
+#define ioss_0_port_14_pin_1_NUM 1U
+#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_1_HSIOM
+	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_PORT_PIN P14_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PORT_NUM 1U
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
+#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
+#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U
+#define CYBSP_WIFI_HOST_WAKE_PIN 7U
+#define CYBSP_WIFI_HOST_WAKE_NUM 7U
+#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_2_pin_7_HSIOM
+	#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
+#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PORT_NUM 3U
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_0_HSIOM
+	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PORT_NUM 3U
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_1_HSIOM
+	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PORT_NUM 3U
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_2_HSIOM
+	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PORT_NUM 3U
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_3_HSIOM
+	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_POWER_ENABLED 1U
+#define CYBSP_BT_POWER_PORT GPIO_PRT3
+#define CYBSP_BT_POWER_PORT_NUM 3U
+#define CYBSP_BT_POWER_PIN 4U
+#define CYBSP_BT_POWER_NUM 4U
+#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_4_HSIOM
+	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_3_pin_5_HSIOM
+	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -24,10 +24,10 @@
 
 #include "cycfg_qspi_memslot.h"
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
+    .command = 0xECU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xD8U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
+    .command = 0x34U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
     .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 520U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 134000U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 340U
+    .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
     /* The base address the memory slave is mapped to in the PSoC memory map.
@@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
     .baseAddress = 0x18000000U,
     /* The size allocated in the PSoC memory map, for the memory slave device.
     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
+    .memMappedSize = 0x4000000U,
     /* If this memory device is one of the devices in the dual quad SPI configuration.
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
 };
 
-const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
-   &S25FL512S_SlaveSlot_0
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
@@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
     /* The version of the SMIF driver. */
     .minorVersion = CY_SMIF_DRV_VERSION_MINOR
 };
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -28,22 +28,23 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0;
-extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
 
 
 #endif /*CY_SMIF_MEMCONFIG_H*/
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -24,22 +24,10 @@
 
 #include "cycfg_routing.h"
 
-#include "cy_trigmux.h"
-
-#include "stdbool.h"
-
 #include "cy_device_headers.h"
 
 void init_cycfg_routing(void)
 {
-	Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
 	HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
 		HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
 		HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -42,19 +42,11 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
 #define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
 #define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
-#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
-#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
-#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI
-#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI
-#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
 #define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
 #define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
 #define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@@ -63,27 +55,14 @@ void init_cycfg_routing(void);
 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
 
-#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
-#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
-#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
-#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
-#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
-#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
-#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
-#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
-#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
-#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
-#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
-#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
-
 #if defined(__cplusplus)
 }
 #endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -83,6 +83,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
 	.cco_Freq = 355U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 4U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
 {
 	.feedbackDiv = 30,
@@ -523,4 +563,24 @@ void init_cycfg_system(void)
 	
 	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
 	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_systick.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg

@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense

@@ -0,0 +1,409 @@
+<?xml version="1.0"?>
+<Configuration major="2" minor="0">
+    <!--
+       File Name: cycfg_capsense.cycapsense 
+
+       Description: 
+       CapSense middleware configuration 
+       This file should not be modified. It was automatically generated by 
+       CapSense Configurator 2.0.0 build 185 
+-->
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -2,13 +2,121 @@
 <Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
     <ToolInfo version="1.0.0"/>
     <Devices>
-        <Device mpn="CY8C624ABZI-D44">
+        <Device mpn="CY8C6247BZI-D54">
             <BlockConfig>
                 <Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
                     <Param id="dbgMode" value="SWD"/>
                     <Param id="traceEnable" value="false"/>
                 </Block>
-                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="1.1">
+                <Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="1"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="true"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
+                    <Param id="X_SRC_INCREMENT_0" value="0"/>
+                    <Param id="X_DST_INCREMENT_0" value="1"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
+                    <Param id="Y_DST_INCREMENT_0" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="1"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="true"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
+                    <Param id="X_SRC_INCREMENT_0" value="1"/>
+                    <Param id="X_DST_INCREMENT_0" value="0"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
+                    <Param id="Y_DST_INCREMENT_0" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="0"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="false"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
+                    <Param id="X_SRC_INCREMENT_0" value="2"/>
+                    <Param id="X_DST_INCREMENT_0" value="0"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="10"/>
+                    <Param id="Y_DST_INCREMENT_0" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="0"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="false"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
+                    <Param id="X_SRC_INCREMENT_0" value="0"/>
+                    <Param id="X_DST_INCREMENT_0" value="2"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
+                    <Param id="Y_DST_INCREMENT_0" value="10"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
                     <Param id="CapSenseEnable" value="true"/>
                     <Param id="CapSenseCore" value="4"/>
                     <Param id="SensorCount" value="12"/>
@@ -39,10 +147,8 @@
                     <Param id="csdInitTime" value="25"/>
                     <Param id="inFlash" value="true"/>
                     <Param id="CsdIdacEnable" value="false"/>
-                    <Param id="CsdIdacAEnable" value="false"/>
-                    <Param id="IdacAbusOnly" value="false"/>
-                    <Param id="CsdIdacBEnable" value="false"/>
-                    <Param id="IdacBbusOnly" value="false"/>
+                    <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
+                    <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
                     <Param id="csdIdacInitTime" value="25"/>
                     <Param id="idacInFlash" value="true"/>
                 </Block>
@@ -66,16 +172,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -86,7 +182,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_DATA3" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -96,7 +192,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_DATA2" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -106,7 +202,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_DATA1" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -116,7 +212,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_DATA0" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -136,8 +232,18 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                <Block location="ioss[0].port[14].pin[0]" alias="" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[14].pin[1]" alias="" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -156,59 +262,9 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_DAT0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_DAT1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_DAT2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_DAT3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
+                <Block location="ioss[0].port[2].pin[7]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="0"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
                     <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
@@ -286,26 +342,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
                     <Param id="initialState" value="1"/>
@@ -456,18 +492,28 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="256"/>
+                <Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="1000"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="1"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
                 <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="4"/>
+                    <Param id="intDivider" value="8"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="36"/>
+                <Block location="peri[0].div_8[3]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="256"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[4]" alias="" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="109"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
@@ -475,7 +521,7 @@
                     <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
                     <Param id="IrdaLowPower" value="false"/>
                     <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="12"/>
+                    <Param id="Oversample" value="8"/>
                     <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
                     <Param id="DataWidth" value="8"/>
                     <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
@@ -525,61 +571,8 @@
                     <Param id="EnableWakeup" value="false"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="12"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="9"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="false"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_HIGH"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
-                <Block location="sdhc[0]" alias="CYBSP_RADIO" template="mxs40sdhost" version="1.0">
-                    <Param id="cardType" value="nonEmmc"/>
-                    <Param id="dmaType" value="CY_SD_HOST_DMA_SDMA"/>
-                    <Param id="enableLedControl" value="false"/>
-                    <Param id="busWidth" value="CY_SD_HOST_BUS_WIDTH_4_BIT"/>
-                    <Param id="lowVoltageSignaling" value="false"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
-                    <Param id="configurator" value=""/>
+                    <Param id="configurator" value="0"/>
                     <Param id="isrAlignment" value="false"/>
                     <Param id="isrUnderflow" value="false"/>
                     <Param id="isrCmdOverflow" value="false"/>
@@ -589,6 +582,9 @@
                     <Param id="inFlash" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
+                <Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
+                    <Param id="sourceClock" value="lfclk"/>
+                </Block>
                 <Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
                     <Param id="sourceClock" value="wco"/>
                 </Block>
@@ -603,19 +599,23 @@
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="1"/>
                 </Block>
+                <Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
+                    <Param id="divider" value="1"/>
+                </Block>
                 <Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="2"/>
                 </Block>
-                <Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="0"/>
+                <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
                     <Param id="divider" value="1"/>
                 </Block>
                 <Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
                     <Param id="hibernate" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
-                    <Param id="trim" value="1"/>
+                    <Param id="trim" value="0.25"/>
                 </Block>
                 <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
                     <Param id="sourceClock" value="wco"/>
@@ -635,15 +635,22 @@
                 <Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
                     <Param id="sourceClock" value="imo"/>
                 </Block>
-                <Block location="srss[0].clock[0].pathmux[5]" alias="" template="mxs40pathmux" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                </Block>
                 <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
-                    <Param id="divider" value="2"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
+                    <Param id="lowFrequencyMode" value="false"/>
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="48.000"/>
+                    <Param id="optimization" value="MinPower"/>
                 </Block>
                 <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
                     <Param id="divider" value="1"/>
                 </Block>
+                <Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                    <Param id="timerDivider" value="1"/>
+                </Block>
                 <Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
                     <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
                     <Param id="clockLostDetection" value="false"/>
@@ -706,6 +713,29 @@
                     <Param id="dstStopHour" value="0"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
+                    <Param id="configurator" value="0"/>
+                    <Param id="UsbCore" value="4"/>
+                    <Param id="epMask" value="0"/>
+                    <Param id="bufSize" value="512"/>
+                    <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
+                    <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
+                    <Param id="enableLpm" value="false"/>
+                    <Param id="lpmIntr" value="0x0U"/>
+                    <Param id="ArbIntr" value="0x0U"/>
+                    <Param id="ep0CntrIntr" value="0x2U"/>
+                    <Param id="busResetIntr" value="0x2U"/>
+                    <Param id="sofIntr" value="0x1U"/>
+                    <Param id="ep0Intr" value="0x1U"/>
+                    <Param id="ep1Intr" value="0x1U"/>
+                    <Param id="ep2Intr" value="0x1U"/>
+                    <Param id="ep3Intr" value="0x1U"/>
+                    <Param id="ep4Intr" value="0x1U"/>
+                    <Param id="ep5Intr" value="0x1U"/>
+                    <Param id="ep6Intr" value="0x1U"/>
+                    <Param id="ep7Intr" value="0x1U"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
             </BlockConfig>
             <Netlist>
                 <Net>
@@ -722,7 +752,7 @@
                 </Net>
                 <Net>
                     <Port name="csd[0].csd[0].clock[0]"/>
-                    <Port name="peri[0].div_8[0].clk[0]"/>
+                    <Port name="peri[0].div_8[3].clk[0]"/>
                 </Net>
                 <Net>
                     <Port name="ioss[0].port[0].pin[0].analog[0]"/>
@@ -732,30 +762,6 @@
                     <Port name="ioss[0].port[0].pin[1].analog[0]"/>
                     <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[1]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[2]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[3]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_cmd[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
-                    <Port name="sdhc[0].clk_card[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
                     <Port name="scb[2].uart_rx[0]"/>
@@ -772,14 +778,6 @@
                     <Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
                     <Port name="scb[2].uart_cts[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
-                    <Port name="scb[5].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
-                    <Port name="scb[5].uart_tx[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
                     <Port name="scb[3].i2c_scl[0]"/>
@@ -812,18 +810,25 @@
                     <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
                     <Port name="smif[0].spi_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[0].aux[0]"/>
+                    <Port name="usb[0].usb_dp_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[1].aux[0]"/>
+                    <Port name="usb[0].usb_dm_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_16[0].clk[0]"/>
+                    <Port name="usb[0].clock_dev_brs[0]"/>
+                </Net>
                 <Net>
                     <Port name="peri[0].div_8[1].clk[0]"/>
                     <Port name="scb[3].clock[0]"/>
                 </Net>
                 <Net>
-                    <Port name="peri[0].div_8[2].clk[0]"/>
+                    <Port name="peri[0].div_8[4].clk[0]"/>
                     <Port name="scb[2].clock[0]"/>
-                    <Port name="scb[5].clock[0]"/>
-                </Net>
-                <Net>
-                    <Port name="sdhc[0].clk_hf[0]"/>
-                    <Port name="srss[0].clock[0].hfclk[4].root_clk[0]"/>
                 </Net>
                 <Net>
                     <Port name="smif[0].clk_hf[0]"/>
@@ -833,6 +838,10 @@
                     <Port name="smif[0].clk_if[0]"/>
                     <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
+                    <Port name="usb[0].clk_usb_dev[0]"/>
+                </Net>
                 <Mux name="sense" location="csd[0].csd[0]">
                     <Arm>
                         <Port name="ioss[0].port[7].pin[7].analog[0]"/>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h

@@ -1,631 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_RED_ENABLED 1U
-#define CYBSP_LED_RED_PORT GPIO_PRT0
-#define CYBSP_LED_RED_PIN 3U
-#define CYBSP_LED_RED_NUM 3U
-#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_RED_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_3_HSIOM
-	#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_BTN2_ENABLED 1U
-#define CYBSP_BTN2_PORT GPIO_PRT0
-#define CYBSP_BTN2_PIN 4U
-#define CYBSP_BTN2_NUM 4U
-#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_BTN2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_BLUE_ENABLED 1U
-#define CYBSP_LED_BLUE_PORT GPIO_PRT11
-#define CYBSP_LED_BLUE_PIN 1U
-#define CYBSP_LED_BLUE_NUM 1U
-#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
-	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SS_ENABLED 1U
-#define CYBSP_QSPI_SS_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS_PIN 2U
-#define CYBSP_QSPI_SS_NUM 2U
-#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D3_ENABLED 1U
-#define CYBSP_QSPI_D3_PORT GPIO_PRT11
-#define CYBSP_QSPI_D3_PIN 3U
-#define CYBSP_QSPI_D3_NUM 3U
-#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D2_ENABLED 1U
-#define CYBSP_QSPI_D2_PORT GPIO_PRT11
-#define CYBSP_QSPI_D2_PIN 4U
-#define CYBSP_QSPI_D2_NUM 4U
-#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D1_ENABLED 1U
-#define CYBSP_QSPI_D1_PORT GPIO_PRT11
-#define CYBSP_QSPI_D1_PIN 5U
-#define CYBSP_QSPI_D1_NUM 5U
-#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D0_ENABLED 1U
-#define CYBSP_QSPI_D0_PORT GPIO_PRT11
-#define CYBSP_QSPI_D0_PIN 6U
-#define CYBSP_QSPI_D0_NUM 6U
-#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SCK_ENABLED 1U
-#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SCK_PIN 7U
-#define CYBSP_QSPI_SCK_NUM 7U
-#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_LED9_ENABLED 1U
-#define CYBSP_LED9_PORT GPIO_PRT13
-#define CYBSP_LED9_PIN 7U
-#define CYBSP_LED9_NUM 7U
-#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED9_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_7_HSIOM
-	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
-#define ioss_0_port_14_pin_0_ENABLED 1U
-#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_0_PIN 0U
-#define ioss_0_port_14_pin_0_NUM 0U
-#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_14_pin_0_HSIOM
-	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
-#define ioss_0_port_14_pin_1_ENABLED 1U
-#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_1_PIN 1U
-#define ioss_0_port_14_pin_1_NUM 1U
-#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_14_pin_1_HSIOM
-	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED_GREEN_ENABLED 1U
-#define CYBSP_LED_GREEN_PORT GPIO_PRT1
-#define CYBSP_LED_GREEN_PIN 1U
-#define CYBSP_LED_GREEN_NUM 1U
-#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
-	#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED8_ENABLED 1U
-#define CYBSP_LED8_PORT GPIO_PRT1
-#define CYBSP_LED8_PIN 5U
-#define CYBSP_LED8_NUM 5U
-#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED8_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WIFI_SDIO_D0_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D0_PIN 0U
-#define CYBSP_WIFI_SDIO_D0_NUM 0U
-#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_0_HSIOM
-	#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D1_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D1_PIN 1U
-#define CYBSP_WIFI_SDIO_D1_NUM 1U
-#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_1_HSIOM
-	#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D2_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D2_PIN 2U
-#define CYBSP_WIFI_SDIO_D2_NUM 2U
-#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_2_HSIOM
-	#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D3_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D3_PIN 3U
-#define CYBSP_WIFI_SDIO_D3_NUM 3U
-#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_3_HSIOM
-	#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CMD_PIN 4U
-#define CYBSP_WIFI_SDIO_CMD_NUM 4U
-#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_4_HSIOM
-	#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CLK_PIN 5U
-#define CYBSP_WIFI_SDIO_CLK_NUM 5U
-#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_5_HSIOM
-	#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U
-#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT2
-#define CYBSP_WIFI_WL_REG_ON_PIN 6U
-#define CYBSP_WIFI_WL_REG_ON_NUM 6U
-#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_2_pin_6_HSIOM
-	#define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_2_pin_6_HSIOM
-#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
-#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
-#define CYBSP_WIFI_HOST_WAKE_PIN 7U
-#define CYBSP_WIFI_HOST_WAKE_NUM 7U
-#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_2_pin_7_HSIOM
-	#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
-#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_BT_UART_RX_ENABLED 1U
-#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RX_PIN 0U
-#define CYBSP_BT_UART_RX_NUM 0U
-#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_0_HSIOM
-	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_TX_ENABLED 1U
-#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_TX_PIN 1U
-#define CYBSP_BT_UART_TX_NUM 1U
-#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_1_HSIOM
-	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_RTS_ENABLED 1U
-#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RTS_PIN 2U
-#define CYBSP_BT_UART_RTS_NUM 2U
-#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_2_HSIOM
-	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_CTS_ENABLED 1U
-#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_CTS_PIN 3U
-#define CYBSP_BT_UART_CTS_NUM 3U
-#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_3_HSIOM
-	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_POWER_ENABLED 1U
-#define CYBSP_BT_POWER_PORT GPIO_PRT3
-#define CYBSP_BT_POWER_PIN 4U
-#define CYBSP_BT_POWER_NUM 4U
-#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_4_HSIOM
-	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_HOST_WAKE_ENABLED 1U
-#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
-#define CYBSP_BT_HOST_WAKE_PIN 5U
-#define CYBSP_BT_HOST_WAKE_NUM 5U
-#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_3_pin_5_HSIOM
-	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
-#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define CYBSP_BT_DEVICE_WAKE_PIN 0U
-#define CYBSP_BT_DEVICE_WAKE_NUM 0U
-#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_4_pin_0_HSIOM
-	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */