mirror of https://github.com/ARMmbed/mbed-os.git
EFM32: update emlib for EFM32PG
amq
parent
012682a244
commit
4c230763db
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@ -1,35 +1,39 @@
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/**************************************************************************//**
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* @file efm32pg1b100f128gm32.h
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/***************************************************************************//**
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* @file
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* @brief CMSIS Cortex-M Peripheral Access Layer Header File
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* for EFM32PG1B100F128GM32
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* @version 5.1.2
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******************************************************************************
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* @section License
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* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
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******************************************************************************
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*******************************************************************************
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* # License
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* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.@n
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.@n
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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* has no obligation to support this Software. Silicon Laboratories, Inc. is
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* providing the Software "AS IS", with no express or implied warranties of any
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* kind, including, but not limited to, any implied warranties of
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* merchantability or fitness for any particular purpose or warranties against
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* infringement of any proprietary rights of a third party.
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*
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* Silicon Laboratories, Inc. will not be liable for any consequential,
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* incidental, or special damages, or any other relief, or for any claim by
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* any third party, arising from your use of this Software.
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*
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*****************************************************************************/
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******************************************************************************/
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#if defined(__ICCARM__)
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#pragma system_include /* Treat file as system include file. */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* Treat file as system include file. */
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#endif
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#ifndef EFM32PG1B100F128GM32_H
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#define EFM32PG1B100F128GM32_H
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@ -38,73 +42,72 @@
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extern "C" {
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#endif
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/**************************************************************************//**
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/***************************************************************************//**
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* @addtogroup Parts
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* @{
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*****************************************************************************/
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******************************************************************************/
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/**************************************************************************//**
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/***************************************************************************//**
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* @defgroup EFM32PG1B100F128GM32 EFM32PG1B100F128GM32
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* @{
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*****************************************************************************/
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******************************************************************************/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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typedef enum IRQn{
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/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
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NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
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NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
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EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
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WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
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LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
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GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
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TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
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USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
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USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
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ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
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ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
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IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
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I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
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GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
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TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
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USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
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USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
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LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
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PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
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CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
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MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
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CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
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LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
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RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
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CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
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FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
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EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
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WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
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LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
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GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
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TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
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USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
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USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
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ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
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ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
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IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
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I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
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GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
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TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
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USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
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USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
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LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
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PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
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CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
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MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
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CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
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LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
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RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
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CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
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FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
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} IRQn_Type;
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/**************************************************************************//**
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* @defgroup EFM32PG1B100F128GM32_Core EFM32PG1B100F128GM32 Core
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/***************************************************************************//**
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* @defgroup EFM32PG1B100F128GM32_Core Core
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* @{
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* @brief Processor and Core Peripheral Section
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*****************************************************************************/
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#define __MPU_PRESENT 1 /**< Presence of MPU */
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#define __FPU_PRESENT 1 /**< Presence of FPU */
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#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
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#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
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#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
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******************************************************************************/
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#define __MPU_PRESENT 1U /**< Presence of MPU */
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#define __FPU_PRESENT 1U /**< Presence of FPU */
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#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
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#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
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#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
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/** @} End of group EFM32PG1B100F128GM32_Core */
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/**************************************************************************//**
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* @defgroup EFM32PG1B100F128GM32_Part EFM32PG1B100F128GM32 Part
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/***************************************************************************//**
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* @defgroup EFM32PG1B100F128GM32_Part Part
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* @{
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******************************************************************************/
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@ -115,8 +118,8 @@ typedef enum IRQn
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#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
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#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
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#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
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#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
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#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
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@ -131,63 +134,64 @@ typedef enum IRQn
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#define PART_NUMBER "EFM32PG1B100F128GM32" /**< Part Number */
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/** Memory Base addresses and limits */
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#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
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#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
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#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
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#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
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#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
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#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
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#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
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#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
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#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
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#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
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#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
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#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
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#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
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#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
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#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
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#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
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#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
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#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
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#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
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#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
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#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
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#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
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#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
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#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
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#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
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#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
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#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
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#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
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#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
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#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
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#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
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#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
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#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
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#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
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#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
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#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
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#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
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#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
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#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
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#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
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#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
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#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
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#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
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#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
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#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
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#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
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#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
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#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
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#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
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#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
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#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
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#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
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#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
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#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
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#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
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#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
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#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
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#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
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#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
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#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
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#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
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#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
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#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
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#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
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#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
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#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
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#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
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#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
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#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
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#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
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#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
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#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
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/** Bit banding area */
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#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
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#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
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#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
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#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
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/** Flash and SRAM limits for EFM32PG1B100F128GM32 */
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#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
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#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
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#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
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#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
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#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
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#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
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#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
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#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
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#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
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#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
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#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
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/** AF channels connect the different on-chip peripherals with the af-mux */
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#define AFCHAN_MAX 72
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#define AFCHANLOC_MAX 32
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#define AFCHAN_MAX 72U
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/** AF channel maximum location number */
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#define AFCHANLOC_MAX 32U
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/** Analog AF channels */
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#define AFACHAN_MAX 61
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#define AFACHAN_MAX 61U
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/* Part number capabilities */
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@ -211,43 +215,43 @@ typedef enum IRQn
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#define IDAC_COUNT 1 /**< 1 IDACs available */
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#define WDOG_PRESENT /**< WDOG is available in this part */
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#define WDOG_COUNT 1 /**< 1 WDOGs available */
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#define MSC_PRESENT
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#define MSC_COUNT 1
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#define EMU_PRESENT
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#define EMU_COUNT 1
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#define RMU_PRESENT
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#define RMU_COUNT 1
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#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B100F128GM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_TypeDefs EFM32PG1B100F128GM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +288,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128GM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_Base EFM32PG1B100F128GM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +325,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128GM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_Declaration EFM32PG1B100F128GM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +360,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128GM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_Offsets EFM32PG1B100F128GM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +378,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128GM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_BitFields EFM32PG1B100F128GM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_UNLOCK EFM32PG1B100F128GM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +402,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128GM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128GM32_Alternate_Function EFM32PG1B100F128GM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B100F128GM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +417,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b100f128im32.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B100F128IM32
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B100F128IM32_H
|
||||
#define EFM32PG1B100F128IM32_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32 EFM32PG1B100F128IM32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Core EFM32PG1B100F128IM32 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B100F128IM32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Part EFM32PG1B100F128IM32 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B100F128IM32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B100F128IM32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,43 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B100F128IM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_TypeDefs EFM32PG1B100F128IM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +288,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128IM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_Base EFM32PG1B100F128IM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +325,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128IM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_Declaration EFM32PG1B100F128IM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +360,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128IM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_Offsets EFM32PG1B100F128IM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +378,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128IM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_BitFields EFM32PG1B100F128IM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_UNLOCK EFM32PG1B100F128IM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +402,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F128IM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F128IM32_Alternate_Function EFM32PG1B100F128IM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B100F128IM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +417,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b100f256gm32.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B100F256GM32
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B100F256GM32_H
|
||||
#define EFM32PG1B100F256GM32_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32 EFM32PG1B100F256GM32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Core EFM32PG1B100F256GM32 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B100F256GM32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Part EFM32PG1B100F256GM32 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B100F256GM32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B100F256GM32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,43 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B100F256GM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_TypeDefs EFM32PG1B100F256GM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +288,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256GM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_Base EFM32PG1B100F256GM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +325,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256GM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_Declaration EFM32PG1B100F256GM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +360,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256GM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_Offsets EFM32PG1B100F256GM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +378,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256GM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_BitFields EFM32PG1B100F256GM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_UNLOCK EFM32PG1B100F256GM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +402,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256GM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256GM32_Alternate_Function EFM32PG1B100F256GM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B100F256GM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +417,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b100f256im32.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B100F256IM32
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B100F256IM32_H
|
||||
#define EFM32PG1B100F256IM32_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32 EFM32PG1B100F256IM32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Core EFM32PG1B100F256IM32 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B100F256IM32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Part EFM32PG1B100F256IM32 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B100F256IM32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B100F256IM32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,43 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B100F256IM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_TypeDefs EFM32PG1B100F256IM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +288,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256IM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_Base EFM32PG1B100F256IM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +325,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256IM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_Declaration EFM32PG1B100F256IM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +360,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256IM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_Offsets EFM32PG1B100F256IM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +378,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256IM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_BitFields EFM32PG1B100F256IM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_UNLOCK EFM32PG1B100F256IM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +402,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B100F256IM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B100F256IM32_Alternate_Function EFM32PG1B100F256IM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B100F256IM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +417,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b200f128gm32.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B200F128GM32
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B200F128GM32_H
|
||||
#define EFM32PG1B200F128GM32_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32 EFM32PG1B200F128GM32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Core EFM32PG1B200F128GM32 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B200F128GM32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Part EFM32PG1B200F128GM32 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B200F128GM32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B200F128GM32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,45 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
#define DCDC_PRESENT /**< DCDC is available in this part */
|
||||
#define DCDC_COUNT 1 /**< 1 DCDC available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B200F128GM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_TypeDefs EFM32PG1B200F128GM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +290,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_Base EFM32PG1B200F128GM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +327,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_Declaration EFM32PG1B200F128GM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +362,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_Offsets EFM32PG1B200F128GM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +380,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_BitFields EFM32PG1B200F128GM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_UNLOCK EFM32PG1B200F128GM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +404,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM32_Alternate_Function EFM32PG1B200F128GM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B200F128GM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +419,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b200f128gm48.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B200F128GM48
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B200F128GM48_H
|
||||
#define EFM32PG1B200F128GM48_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48 EFM32PG1B200F128GM48
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Core EFM32PG1B200F128GM48 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B200F128GM48_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Part EFM32PG1B200F128GM48 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B200F128GM48" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B200F128GM48 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,45 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
#define DCDC_PRESENT /**< DCDC is available in this part */
|
||||
#define DCDC_COUNT 1 /**< 1 DCDC available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B200F128GM48_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_TypeDefs EFM32PG1B200F128GM48 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +290,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM48_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_Base EFM32PG1B200F128GM48 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +327,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM48_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_Declaration EFM32PG1B200F128GM48 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +362,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM48_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_Offsets EFM32PG1B200F128GM48 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +380,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM48_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_BitFields EFM32PG1B200F128GM48 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_UNLOCK EFM32PG1B200F128GM48 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +404,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128GM48_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128GM48_Alternate_Function EFM32PG1B200F128GM48 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B200F128GM48_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +419,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b200f128im32.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B200F128IM32
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B200F128IM32_H
|
||||
#define EFM32PG1B200F128IM32_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32 EFM32PG1B200F128IM32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Core EFM32PG1B200F128IM32 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B200F128IM32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Part EFM32PG1B200F128IM32 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B200F128IM32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B200F128IM32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,45 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
#define DCDC_PRESENT /**< DCDC is available in this part */
|
||||
#define DCDC_COUNT 1 /**< 1 DCDC available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B200F128IM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_TypeDefs EFM32PG1B200F128IM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +290,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128IM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_Base EFM32PG1B200F128IM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +327,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128IM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_Declaration EFM32PG1B200F128IM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +362,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128IM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_Offsets EFM32PG1B200F128IM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +380,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128IM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_BitFields EFM32PG1B200F128IM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_UNLOCK EFM32PG1B200F128IM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +404,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F128IM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F128IM32_Alternate_Function EFM32PG1B200F128IM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B200F128IM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +419,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b200f256gm32.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B200F256GM32
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B200F256GM32_H
|
||||
#define EFM32PG1B200F256GM32_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32 EFM32PG1B200F256GM32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Core EFM32PG1B200F256GM32 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256GM32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Part EFM32PG1B200F256GM32 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B200F256GM32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B200F256GM32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,45 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
#define DCDC_PRESENT /**< DCDC is available in this part */
|
||||
#define DCDC_COUNT 1 /**< 1 DCDC available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256GM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_TypeDefs EFM32PG1B200F256GM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +290,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_Base EFM32PG1B200F256GM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +327,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_Declaration EFM32PG1B200F256GM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +362,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_Offsets EFM32PG1B200F256GM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +380,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_BitFields EFM32PG1B200F256GM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_UNLOCK EFM32PG1B200F256GM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +404,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM32_Alternate_Function EFM32PG1B200F256GM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B200F256GM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +419,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b200f256gm48.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B200F256GM48
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B200F256GM48_H
|
||||
#define EFM32PG1B200F256GM48_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48 EFM32PG1B200F256GM48
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Core EFM32PG1B200F256GM48 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256GM48_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Part EFM32PG1B200F256GM48 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B200F256GM48" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B200F256GM48 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,45 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
#define DCDC_PRESENT /**< DCDC is available in this part */
|
||||
#define DCDC_COUNT 1 /**< 1 DCDC available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256GM48_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_TypeDefs EFM32PG1B200F256GM48 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +290,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM48_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_Base EFM32PG1B200F256GM48 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +327,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM48_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_Declaration EFM32PG1B200F256GM48 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +362,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM48_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_Offsets EFM32PG1B200F256GM48 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +380,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM48_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_BitFields EFM32PG1B200F256GM48 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_UNLOCK EFM32PG1B200F256GM48 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +404,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256GM48_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256GM48_Alternate_Function EFM32PG1B200F256GM48 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B200F256GM48_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +419,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b200f256im32.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B200F256IM32
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B200F256IM32_H
|
||||
#define EFM32PG1B200F256IM32_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32 EFM32PG1B200F256IM32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Core EFM32PG1B200F256IM32 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256IM32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Part EFM32PG1B200F256IM32 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B200F256IM32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B200F256IM32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,45 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
#define DCDC_PRESENT /**< DCDC is available in this part */
|
||||
#define DCDC_COUNT 1 /**< 1 DCDC available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256IM32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_TypeDefs EFM32PG1B200F256IM32 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +290,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_Base EFM32PG1B200F256IM32 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +327,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_Declaration EFM32PG1B200F256IM32 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +362,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_Offsets EFM32PG1B200F256IM32 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +380,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM32_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_BitFields EFM32PG1B200F256IM32 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_UNLOCK EFM32PG1B200F256IM32 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +404,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM32_Alternate_Function EFM32PG1B200F256IM32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B200F256IM32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +419,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b200f256im48.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
|
||||
* for EFM32PG1B200F256IM48
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32PG1B200F256IM48_H
|
||||
#define EFM32PG1B200F256IM48_H
|
||||
|
|
@ -38,73 +42,72 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48 EFM32PG1B200F256IM48
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
typedef enum IRQn{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
|
||||
/****** EFM32PG1B Peripheral Interrupt Numbers ********************************************/
|
||||
|
||||
EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 33 EFM32 FPUEH Interrupt */
|
||||
EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
|
||||
WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
|
||||
LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
|
||||
IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
|
||||
I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
|
||||
USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
|
||||
LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
|
||||
PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
|
||||
CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
|
||||
MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
|
||||
CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
|
||||
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
|
||||
RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
|
||||
CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
|
||||
FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Core EFM32PG1B200F256IM48 Core
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Core Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1 /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
******************************************************************************/
|
||||
#define __MPU_PRESENT 1U /**< Presence of MPU */
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
|
||||
#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256IM48_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Part EFM32PG1B200F256IM48 Part
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Part Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
|
|
@ -115,8 +118,8 @@ typedef enum IRQn
|
|||
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
|
||||
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
|
||||
|
|
@ -131,63 +134,64 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32PG1B200F256IM48" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
|
||||
#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
|
||||
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
|
||||
#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
|
||||
#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
|
||||
#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
|
||||
#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
|
||||
#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
|
||||
#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
|
||||
#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
|
||||
#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
|
||||
#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
|
||||
#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
|
||||
#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
|
||||
#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
|
||||
#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
|
||||
#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
|
||||
#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
|
||||
#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
|
||||
#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
|
||||
#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
|
||||
#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
|
||||
#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
|
||||
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
|
||||
#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32PG1B200F256IM48 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
|
||||
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
|
||||
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
|
||||
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 72
|
||||
#define AFCHANLOC_MAX 32
|
||||
#define AFCHAN_MAX 72U
|
||||
/** AF channel maximum location number */
|
||||
#define AFCHANLOC_MAX 32U
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 61
|
||||
#define AFACHAN_MAX 61U
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
|
|
@ -211,43 +215,45 @@ typedef enum IRQn
|
|||
#define IDAC_COUNT 1 /**< 1 IDACs available */
|
||||
#define WDOG_PRESENT /**< WDOG is available in this part */
|
||||
#define WDOG_COUNT 1 /**< 1 WDOGs available */
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define CRYPTO_PRESENT
|
||||
#define CRYPTO_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define LDMA_PRESENT
|
||||
#define LDMA_COUNT 1
|
||||
#define FPUEH_PRESENT
|
||||
#define FPUEH_COUNT 1
|
||||
#define GPCRC_PRESENT
|
||||
#define GPCRC_COUNT 1
|
||||
#define CRYOTIMER_PRESENT
|
||||
#define CRYOTIMER_COUNT 1
|
||||
#define RTCC_PRESENT
|
||||
#define RTCC_COUNT 1
|
||||
#define BOOTLOADER_PRESENT
|
||||
#define BOOTLOADER_COUNT 1
|
||||
#define MSC_PRESENT /**< MSC is available in this part */
|
||||
#define MSC_COUNT 1 /**< 1 MSC available */
|
||||
#define EMU_PRESENT /**< EMU is available in this part */
|
||||
#define EMU_COUNT 1 /**< 1 EMU available */
|
||||
#define RMU_PRESENT /**< RMU is available in this part */
|
||||
#define RMU_COUNT 1 /**< 1 RMU available */
|
||||
#define CMU_PRESENT /**< CMU is available in this part */
|
||||
#define CMU_COUNT 1 /**< 1 CMU available */
|
||||
#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
|
||||
#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
|
||||
#define GPIO_PRESENT /**< GPIO is available in this part */
|
||||
#define GPIO_COUNT 1 /**< 1 GPIO available */
|
||||
#define PRS_PRESENT /**< PRS is available in this part */
|
||||
#define PRS_COUNT 1 /**< 1 PRS available */
|
||||
#define LDMA_PRESENT /**< LDMA is available in this part */
|
||||
#define LDMA_COUNT 1 /**< 1 LDMA available */
|
||||
#define FPUEH_PRESENT /**< FPUEH is available in this part */
|
||||
#define FPUEH_COUNT 1 /**< 1 FPUEH available */
|
||||
#define GPCRC_PRESENT /**< GPCRC is available in this part */
|
||||
#define GPCRC_COUNT 1 /**< 1 GPCRC available */
|
||||
#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
|
||||
#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
|
||||
#define RTCC_PRESENT /**< RTCC is available in this part */
|
||||
#define RTCC_COUNT 1 /**< 1 RTCC available */
|
||||
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
|
||||
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
|
||||
#define DCDC_PRESENT /**< DCDC is available in this part */
|
||||
#define DCDC_COUNT 1 /**< 1 DCDC available */
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include "system_efm32pg1b.h" /* System Header File */
|
||||
|
||||
/** @} End of group EFM32PG1B200F256IM48_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_TypeDefs EFM32PG1B200F256IM48 Peripheral TypeDefs
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_TypeDefs Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_msc.h"
|
||||
#include "efm32pg1b_emu.h"
|
||||
|
|
@ -284,10 +290,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM48_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_Base EFM32PG1B200F256IM48 Peripheral Memory Map
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_Base Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
|
||||
|
|
@ -321,10 +327,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM48_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_Declaration EFM32PG1B200F256IM48 Peripheral Declarations
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_Declaration Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
|
|
@ -356,10 +362,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM48_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_Offsets EFM32PG1B200F256IM48 Peripheral Offsets
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Peripheral_Offsets Peripheral Offsets
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
||||
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
||||
|
|
@ -374,19 +380,18 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM48_Peripheral_Offsets */
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_BitFields EFM32PG1B200F256IM48 Bit Fields
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_BitFields Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include "efm32pg1b_prs_signals.h"
|
||||
#include "efm32pg1b_dmareq.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_UNLOCK EFM32PG1B200F256IM48 Unlock Codes
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_UNLOCK Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
||||
|
|
@ -399,17 +404,10 @@ typedef enum IRQn
|
|||
|
||||
/** @} End of group EFM32PG1B200F256IM48_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B200F256IM48_Alternate_Function EFM32PG1B200F256IM48 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32pg1b_af_ports.h"
|
||||
#include "efm32pg1b_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32PG1B200F256IM48_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
|
|
@ -421,7 +419,7 @@ typedef enum IRQn
|
|||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_acmp.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_ACMP register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ACMP
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ACMP ACMP
|
||||
* @{
|
||||
* @brief EFM32PG1B_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** ACMP Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t INPUTSEL; /**< Input Selection Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
|
@ -47,21 +52,23 @@ typedef struct
|
|||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
|
||||
__IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
|
||||
__IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */
|
||||
__IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */
|
||||
|
||||
uint32_t RESERVED1[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
} ACMP_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ACMP_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_ACMP
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_ACMP_BitFields ACMP Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for ACMP CTRL */
|
||||
#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */
|
||||
|
|
@ -99,7 +106,7 @@ typedef struct
|
|||
#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */
|
||||
#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus selected by VASEL */
|
||||
#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus Selected By VASEL */
|
||||
#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */
|
||||
#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */
|
||||
#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
|
|
@ -108,15 +115,15 @@ typedef struct
|
|||
#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */
|
||||
#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_PWRSEL_VREGVDD 0x00000001UL /**< Mode VREGVDD for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_PWRSEL_DVDD 0x00000001UL /**< Mode DVDD for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */
|
||||
#define ACMP_CTRL_PWRSEL_VREGVDD (_ACMP_CTRL_PWRSEL_VREGVDD << 12) /**< Shifted mode VREGVDD for ACMP_CTRL */
|
||||
#define ACMP_CTRL_PWRSEL_DVDD (_ACMP_CTRL_PWRSEL_DVDD << 12) /**< Shifted mode DVDD for ACMP_CTRL */
|
||||
#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP accuracy mode */
|
||||
#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP Accuracy Mode */
|
||||
#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */
|
||||
#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */
|
||||
#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
|
|
@ -311,6 +318,8 @@ typedef struct
|
|||
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
|
||||
|
|
@ -326,8 +335,6 @@ typedef struct
|
|||
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
|
||||
|
|
@ -477,6 +484,8 @@ typedef struct
|
|||
#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
|
||||
|
|
@ -492,8 +501,6 @@ typedef struct
|
|||
#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
|
||||
|
|
@ -645,6 +652,8 @@ typedef struct
|
|||
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
|
||||
|
|
@ -660,8 +669,6 @@ typedef struct
|
|||
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
|
||||
|
|
@ -811,6 +818,8 @@ typedef struct
|
|||
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
|
||||
|
|
@ -826,8 +835,6 @@ typedef struct
|
|||
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
|
||||
|
|
@ -1078,52 +1085,52 @@ typedef struct
|
|||
/* Bit fields for ACMP APORTREQ */
|
||||
#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */
|
||||
#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */
|
||||
#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
|
||||
#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */
|
||||
#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */
|
||||
#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */
|
||||
#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
|
||||
#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */
|
||||
#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */
|
||||
#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */
|
||||
#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
|
||||
#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */
|
||||
#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */
|
||||
#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */
|
||||
#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
|
||||
#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */
|
||||
#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */
|
||||
#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
|
||||
#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
|
||||
#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */
|
||||
#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */
|
||||
#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
|
||||
#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
|
||||
#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */
|
||||
#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */
|
||||
#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
|
||||
#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
|
||||
#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */
|
||||
#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */
|
||||
#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
|
||||
#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
|
||||
#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */
|
||||
#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */
|
||||
#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
|
||||
#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
|
||||
#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */
|
||||
#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */
|
||||
#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
|
||||
#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
|
||||
#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
|
||||
#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */
|
||||
#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */
|
||||
#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
|
||||
|
|
@ -1132,52 +1139,52 @@ typedef struct
|
|||
/* Bit fields for ACMP APORTCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
|
||||
#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
|
||||
#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */
|
||||
#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
|
||||
|
|
@ -1360,6 +1367,6 @@ typedef struct
|
|||
#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */
|
||||
#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_ACMP */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,58 +1,63 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_adc.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_ADC register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ADC
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ADC ADC
|
||||
* @{
|
||||
* @brief EFM32PG1B_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** ADC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */
|
||||
__IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */
|
||||
__IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register Continued */
|
||||
__IOM uint32_t SCANCTRL; /**< Scan Control Register */
|
||||
__IOM uint32_t SCANCTRLX; /**< Scan Control Register continued */
|
||||
__IOM uint32_t SCANCTRLX; /**< Scan Control Register Continued */
|
||||
__IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */
|
||||
__IOM uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */
|
||||
__IOM uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */
|
||||
__IOM uint32_t SCANINPUTSEL; /**< Input Selection Register for Scan Mode */
|
||||
__IOM uint32_t SCANNEGSEL; /**< Negative Input Select Register for Scan */
|
||||
__IOM uint32_t CMPTHR; /**< Compare Threshold Register */
|
||||
__IOM uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation. */
|
||||
__IOM uint32_t BIASPROG; /**< Bias Programming Register for Various Analog Blocks Used in ADC Operation */
|
||||
__IOM uint32_t CAL; /**< Calibration Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
|
|
@ -62,11 +67,11 @@ typedef struct
|
|||
__IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
|
||||
__IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
|
||||
__IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
|
||||
uint32_t RESERVED1[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[4U]; /**< Reserved for future use **/
|
||||
__IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */
|
||||
__IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */
|
||||
|
||||
uint32_t RESERVED2[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[3U]; /**< Reserved for future use **/
|
||||
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
|
||||
__IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
|
||||
__IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */
|
||||
|
|
@ -76,10 +81,12 @@ typedef struct
|
|||
__IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */
|
||||
} ADC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ADC_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_ADC
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_ADC_BitFields ADC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for ADC CTRL */
|
||||
#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
|
||||
|
|
@ -111,7 +118,7 @@ typedef struct
|
|||
#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */
|
||||
#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */
|
||||
#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK Enable Mode When ADCCLKMODE=1 */
|
||||
#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */
|
||||
#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */
|
||||
#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
|
||||
|
|
@ -465,17 +472,17 @@ typedef struct
|
|||
#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_BUVDD 0x000000E1UL /**< Mode BUVDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_DVDD 0x000000E2UL /**< Mode DVDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_PAVDD 0x000000E3UL /**< Mode PAVDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_DECOUPLE 0x000000E4UL /**< Mode DECOUPLE for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_IOVDD 0x000000E5UL /**< Mode IOVDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_IOVDD1 0x000000E6UL /**< Mode IOVDD1 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_R5VOUT 0x000000F5UL /**< Mode R5VOUT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
|
||||
|
|
@ -644,17 +651,17 @@ typedef struct
|
|||
#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_BUVDD (_ADC_SINGLECTRL_POSSEL_BUVDD << 8) /**< Shifted mode BUVDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_DVDD (_ADC_SINGLECTRL_POSSEL_DVDD << 8) /**< Shifted mode DVDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_PAVDD (_ADC_SINGLECTRL_POSSEL_PAVDD << 8) /**< Shifted mode PAVDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_DECOUPLE (_ADC_SINGLECTRL_POSSEL_DECOUPLE << 8) /**< Shifted mode DECOUPLE for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_IOVDD (_ADC_SINGLECTRL_POSSEL_IOVDD << 8) /**< Shifted mode IOVDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_IOVDD1 (_ADC_SINGLECTRL_POSSEL_IOVDD1 << 8) /**< Shifted mode IOVDD1 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_R5VOUT (_ADC_SINGLECTRL_POSSEL_R5VOUT << 8) /**< Shifted mode R5VOUT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
|
||||
|
|
@ -1048,7 +1055,7 @@ typedef struct
|
|||
#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */
|
||||
#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */
|
||||
#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */
|
||||
#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */
|
||||
#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
|
||||
#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
|
||||
#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
|
||||
#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
|
||||
|
|
@ -1115,7 +1122,7 @@ typedef struct
|
|||
#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */
|
||||
#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
|
||||
#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
|
||||
#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */
|
||||
#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
|
||||
#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
|
||||
#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
|
||||
#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
|
||||
|
|
@ -1231,7 +1238,7 @@ typedef struct
|
|||
#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */
|
||||
#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */
|
||||
#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */
|
||||
#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */
|
||||
#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
|
||||
#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
|
||||
#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
|
||||
#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
|
||||
|
|
@ -1298,7 +1305,7 @@ typedef struct
|
|||
#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */
|
||||
#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
|
||||
#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
|
||||
#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */
|
||||
#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
|
||||
#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
|
||||
#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
|
||||
#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
|
||||
|
|
@ -1735,12 +1742,12 @@ typedef struct
|
|||
#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF flag */
|
||||
#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF Flag */
|
||||
#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */
|
||||
#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */
|
||||
#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy setting for the system bias during ADC operation */
|
||||
#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy Setting for the System Bias During ADC Operation */
|
||||
#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */
|
||||
#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */
|
||||
#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
|
||||
|
|
@ -1765,7 +1772,7 @@ typedef struct
|
|||
#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
|
||||
#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */
|
||||
#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative Single-ended Offset Calibration is Enabled */
|
||||
#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */
|
||||
#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */
|
||||
#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
|
||||
|
|
@ -1782,7 +1789,7 @@ typedef struct
|
|||
#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
|
||||
#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */
|
||||
#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration Mode is Enabled */
|
||||
#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */
|
||||
#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */
|
||||
#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
|
||||
|
|
@ -2043,52 +2050,52 @@ typedef struct
|
|||
/* Bit fields for ADC APORTREQ */
|
||||
#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */
|
||||
#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */
|
||||
#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
|
||||
#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */
|
||||
#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */
|
||||
#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */
|
||||
#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
|
||||
#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */
|
||||
#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */
|
||||
#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */
|
||||
#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is Requested */
|
||||
#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */
|
||||
#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */
|
||||
#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */
|
||||
#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
|
||||
#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */
|
||||
#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */
|
||||
#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
|
||||
#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
|
||||
#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */
|
||||
#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */
|
||||
#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
|
||||
#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
|
||||
#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */
|
||||
#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */
|
||||
#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
|
||||
#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
|
||||
#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */
|
||||
#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */
|
||||
#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
|
||||
#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
|
||||
#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */
|
||||
#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */
|
||||
#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
|
||||
#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
|
||||
#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */
|
||||
#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */
|
||||
#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */
|
||||
#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
|
||||
#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
|
||||
#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */
|
||||
#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */
|
||||
#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
|
||||
|
|
@ -2097,52 +2104,52 @@ typedef struct
|
|||
/* Bit fields for ADC APORTCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
|
||||
#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
|
||||
#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
|
||||
#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */
|
||||
#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
|
||||
|
|
@ -2167,7 +2174,7 @@ typedef struct
|
|||
/* Bit fields for ADC SINGLEFIFOCLEAR */
|
||||
#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */
|
||||
#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */
|
||||
#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */
|
||||
#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO Content */
|
||||
#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */
|
||||
#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */
|
||||
#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */
|
||||
|
|
@ -2176,7 +2183,7 @@ typedef struct
|
|||
/* Bit fields for ADC SCANFIFOCLEAR */
|
||||
#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */
|
||||
#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */
|
||||
#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */
|
||||
#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO Content */
|
||||
#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */
|
||||
#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */
|
||||
#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */
|
||||
|
|
@ -2226,6 +2233,6 @@ typedef struct
|
|||
#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
|
||||
#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_ADC */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,102 +1,108 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_af_pins.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_AF_PINS register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_AF_Pins
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_Alternate_Function Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_AF_Pins Alternate Function Pins
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** AF pin number for location number i */
|
||||
#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1)
|
||||
#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1)
|
||||
#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1)
|
||||
#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1)
|
||||
#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1)
|
||||
#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1)
|
||||
#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1)
|
||||
#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1)
|
||||
#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1)
|
||||
#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1)
|
||||
#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1)
|
||||
#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1)
|
||||
#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1)
|
||||
#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1)
|
||||
#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
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#define AF_TIMER0_CC3_PIN(i) (-1)
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#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
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#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
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#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
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#define AF_TIMER0_CDTI3_PIN(i) (-1)
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#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
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#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
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#define AF_TIMER1_CDTI0_PIN(i) (-1)
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#define AF_TIMER1_CDTI1_PIN(i) (-1)
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#define AF_TIMER1_CDTI2_PIN(i) (-1)
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#define AF_TIMER1_CDTI3_PIN(i) (-1)
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#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
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#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
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#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
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#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
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#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
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#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
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#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
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#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
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||||
#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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||||
#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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||||
#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
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#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
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#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1)
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#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1)
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#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1)
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#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1)
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#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1)
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#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) /**< Pin number for AF_CMU_CLK0 location number i */
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#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_CMU_CLK1 location number i */
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#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) /**< Pin number for AF_PRS_CH0 location number i */
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#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) /**< Pin number for AF_PRS_CH1 location number i */
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#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Pin number for AF_PRS_CH2 location number i */
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#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) /**< Pin number for AF_PRS_CH3 location number i */
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#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) /**< Pin number for AF_PRS_CH4 location number i */
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#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) /**< Pin number for AF_PRS_CH5 location number i */
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#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) /**< Pin number for AF_PRS_CH6 location number i */
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#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) /**< Pin number for AF_PRS_CH7 location number i */
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#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) /**< Pin number for AF_PRS_CH8 location number i */
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#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) /**< Pin number for AF_PRS_CH9 location number i */
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#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) /**< Pin number for AF_PRS_CH10 location number i */
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#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) /**< Pin number for AF_PRS_CH11 location number i */
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#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */
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#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */
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#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */
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#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */
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#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */
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#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */
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#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */
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#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */
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#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */
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#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */
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#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */
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#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */
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#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */
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#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */
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#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */
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#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */
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#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART0_TX location number i */
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#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART0_RX location number i */
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#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART0_CLK location number i */
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#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART0_CS location number i */
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#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART0_CTS location number i */
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#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART0_RTS location number i */
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||||
#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART1_TX location number i */
|
||||
#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART1_RX location number i */
|
||||
#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART1_CLK location number i */
|
||||
#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */
|
||||
#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART1_CTS location number i */
|
||||
#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART1_RTS location number i */
|
||||
#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LEUART0_TX location number i */
|
||||
#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LEUART0_RX location number i */
|
||||
#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */
|
||||
#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
|
||||
#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */
|
||||
#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */
|
||||
#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_I2C0_SDA location number i */
|
||||
#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_I2C0_SCL location number i */
|
||||
#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP0_OUT location number i */
|
||||
#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP1_OUT location number i */
|
||||
#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_DBG_TDI location number i */
|
||||
#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */
|
||||
#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) /**< Pin number for AF_DBG_SWV location number i */
|
||||
#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */
|
||||
#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_AF_Pins */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,102 +1,108 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_af_ports.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_AF_PORTS register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_AF_Ports
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_Alternate_Function Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_AF_Ports Alternate Function Ports
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** AF port number for location number i */
|
||||
#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
|
||||
#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
|
||||
#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1)
|
||||
#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
|
||||
#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
|
||||
#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1)
|
||||
#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)
|
||||
#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)
|
||||
#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1)
|
||||
#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1)
|
||||
#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1)
|
||||
#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1)
|
||||
#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)
|
||||
#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)
|
||||
#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_TIMER0_CC3_PORT(i) (-1)
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#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_TIMER0_CDTI3_PORT(i) (-1)
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#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_TIMER1_CDTI0_PORT(i) (-1)
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#define AF_TIMER1_CDTI1_PORT(i) (-1)
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#define AF_TIMER1_CDTI2_PORT(i) (-1)
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#define AF_TIMER1_CDTI3_PORT(i) (-1)
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#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
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#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
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#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
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#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1)
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#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1)
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#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1)
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#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1)
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#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1)
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#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK0 location number i */
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#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK1 location number i */
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#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) /**< Port number for AF_PRS_CH0 location number i */
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#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH1 location number i */
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#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH2 location number i */
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#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) /**< Port number for AF_PRS_CH3 location number i */
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#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH4 location number i */
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#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */
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#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) /**< Port number for AF_PRS_CH6 location number i */
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#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH7 location number i */
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#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH8 location number i */
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#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) /**< Port number for AF_PRS_CH9 location number i */
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||||
#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH10 location number i */
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#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH11 location number i */
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#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER0_CC0 location number i */
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#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */
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#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */
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#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */
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#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */
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#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */
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#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */
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#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */
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#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER1_CC0 location number i */
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#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC1 location number i */
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#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC2 location number i */
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#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC3 location number i */
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||||
#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */
|
||||
#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */
|
||||
#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */
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||||
#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */
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||||
#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART0_TX location number i */
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||||
#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RX location number i */
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||||
#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CLK location number i */
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||||
#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CS location number i */
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||||
#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CTS location number i */
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||||
#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RTS location number i */
|
||||
#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART1_TX location number i */
|
||||
#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */
|
||||
#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CLK location number i */
|
||||
#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CS location number i */
|
||||
#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CTS location number i */
|
||||
#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RTS location number i */
|
||||
#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LEUART0_TX location number i */
|
||||
#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LEUART0_RX location number i */
|
||||
#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */
|
||||
#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */
|
||||
#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_PCNT0_S0IN location number i */
|
||||
#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT0_S1IN location number i */
|
||||
#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_I2C0_SDA location number i */
|
||||
#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_I2C0_SCL location number i */
|
||||
#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP0_OUT location number i */
|
||||
#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP1_OUT location number i */
|
||||
#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */
|
||||
#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */
|
||||
#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) /**< Port number for AF_DBG_SWV location number i */
|
||||
#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */
|
||||
#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_AF_Ports */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,81 +1,86 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_cmu.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_CMU register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CMU
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CMU CMU
|
||||
* @{
|
||||
* @brief EFM32PG1B_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** CMU Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< CMU Control Register */
|
||||
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
|
||||
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
|
||||
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
|
||||
__IOM uint32_t HFXOCTRL; /**< HFXO Control Register */
|
||||
__IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */
|
||||
__IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */
|
||||
__IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */
|
||||
__IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */
|
||||
__IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */
|
||||
__IOM uint32_t LFXOCTRL; /**< LFXO Control Register */
|
||||
__IOM uint32_t ULFRCOCTRL; /**< ULFRCO Control Register */
|
||||
|
||||
uint32_t RESERVED3[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED3[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t CALCTRL; /**< Calibration Control Register */
|
||||
__IOM uint32_t CALCNT; /**< Calibration Counter Register */
|
||||
uint32_t RESERVED4[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED4[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
uint32_t RESERVED5[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED5[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */
|
||||
__IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */
|
||||
uint32_t RESERVED6[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED6[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */
|
||||
__IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */
|
||||
__IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */
|
||||
|
||||
uint32_t RESERVED7[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED7[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */
|
||||
uint32_t RESERVED8[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED8[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
|
|
@ -83,54 +88,56 @@ typedef struct
|
|||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */
|
||||
|
||||
uint32_t RESERVED9[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED9[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
|
||||
|
||||
uint32_t RESERVED10[7]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
|
||||
uint32_t RESERVED11[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED10[7U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */
|
||||
uint32_t RESERVED11[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
|
||||
|
||||
uint32_t RESERVED12[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED12[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */
|
||||
uint32_t RESERVED13[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED13[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */
|
||||
|
||||
uint32_t RESERVED14[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED14[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */
|
||||
__IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */
|
||||
|
||||
uint32_t RESERVED15[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED15[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */
|
||||
|
||||
uint32_t RESERVED16[2]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
|
||||
uint32_t RESERVED17[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED16[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */
|
||||
uint32_t RESERVED17[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
|
||||
uint32_t RESERVED18[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */
|
||||
uint32_t RESERVED18[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */
|
||||
|
||||
uint32_t RESERVED19[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED19[3U]; /**< Reserved for future use **/
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
uint32_t RESERVED20[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED20[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
|
||||
|
||||
uint32_t RESERVED21[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED21[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ADCCTRL; /**< ADC Control Register */
|
||||
|
||||
uint32_t RESERVED22[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED22[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED23[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED23[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
} CMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CMU_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_CMU
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_CMU_BitFields CMU Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for CMU CTRL */
|
||||
#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */
|
||||
|
|
@ -240,7 +247,7 @@ typedef struct
|
|||
#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */
|
||||
#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */
|
||||
#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */
|
||||
#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */
|
||||
#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
|
||||
#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
|
||||
#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
|
||||
#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
|
||||
|
|
@ -284,7 +291,7 @@ typedef struct
|
|||
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */
|
||||
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */
|
||||
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */
|
||||
#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */
|
||||
#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
|
||||
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
|
||||
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
|
||||
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
|
||||
|
|
@ -301,17 +308,17 @@ typedef struct
|
|||
#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */
|
||||
#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
|
||||
#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
|
||||
#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */
|
||||
#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */
|
||||
#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */
|
||||
#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */
|
||||
#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
|
||||
#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
|
||||
#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */
|
||||
#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */
|
||||
#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */
|
||||
#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */
|
||||
#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
|
||||
#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
|
||||
#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */
|
||||
#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */
|
||||
#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */
|
||||
#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */
|
||||
#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
|
||||
|
|
@ -353,17 +360,17 @@ typedef struct
|
|||
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */
|
||||
#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low Power Mode Control */
|
||||
#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */
|
||||
#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */
|
||||
#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off. */
|
||||
#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off */
|
||||
#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */
|
||||
#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */
|
||||
#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off. */
|
||||
#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off */
|
||||
#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */
|
||||
#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */
|
||||
#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
|
||||
|
|
@ -388,12 +395,12 @@ typedef struct
|
|||
#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */
|
||||
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
|
||||
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */
|
||||
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */
|
||||
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
|
||||
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */
|
||||
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
|
||||
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */
|
||||
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */
|
||||
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
|
||||
|
|
@ -455,7 +462,7 @@ typedef struct
|
|||
#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */
|
||||
#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
|
||||
#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
|
||||
#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */
|
||||
#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */
|
||||
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */
|
||||
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */
|
||||
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
|
||||
|
|
@ -983,7 +990,7 @@ typedef struct
|
|||
#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */
|
||||
#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */
|
||||
#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required By Hardware */
|
||||
#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */
|
||||
#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */
|
||||
#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
|
||||
|
|
@ -993,22 +1000,22 @@ typedef struct
|
|||
#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
|
||||
#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */
|
||||
#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization Ready */
|
||||
#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
|
||||
#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
|
||||
#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */
|
||||
#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO Oscillation Amplitude is Too High */
|
||||
#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */
|
||||
#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */
|
||||
#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */
|
||||
#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */
|
||||
#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */
|
||||
#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */
|
||||
#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */
|
||||
#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */
|
||||
#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO Regulator Shunt Current Too Low */
|
||||
#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */
|
||||
#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */
|
||||
#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
|
||||
|
|
@ -1425,7 +1432,7 @@ typedef struct
|
|||
#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x20UL /**< Bit mask for CMU_ACMP1 */
|
||||
#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
|
||||
#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
|
||||
#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CryoTimer Clock Enable */
|
||||
#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CRYOTIMER Clock Enable */
|
||||
#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 6 /**< Shift value for CMU_CRYOTIMER */
|
||||
#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x40UL /**< Bit mask for CMU_CRYOTIMER */
|
||||
#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
|
||||
|
|
@ -1584,12 +1591,12 @@ typedef struct
|
|||
/* Bit fields for CMU SYNCBUSY */
|
||||
#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
|
||||
#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */
|
||||
#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
|
||||
#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */
|
||||
#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
|
||||
#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
|
||||
#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
|
||||
#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
|
||||
#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
|
||||
#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */
|
||||
#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
|
||||
#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
|
||||
#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
|
||||
|
|
@ -1691,7 +1698,7 @@ typedef struct
|
|||
#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
|
||||
#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */
|
||||
#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
|
||||
#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */
|
||||
#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */
|
||||
#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */
|
||||
#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */
|
||||
#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
|
||||
|
|
@ -1771,6 +1778,6 @@ typedef struct
|
|||
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
|
||||
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_CMU */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_cryotimer.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_CRYOTIMER register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CRYOTIMER
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CRYOTIMER CRYOTIMER
|
||||
* @{
|
||||
* @brief EFM32PG1B_CRYOTIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** CRYOTIMER Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t PERIODSEL; /**< Interrupt Duration */
|
||||
__IM uint32_t CNT; /**< Counter Value */
|
||||
|
|
@ -50,10 +55,12 @@ typedef struct
|
|||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} CRYOTIMER_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CRYOTIMER_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_CRYOTIMER
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_CRYOTIMER_BitFields CRYOTIMER Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for CRYOTIMER CTRL */
|
||||
#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */
|
||||
|
|
@ -118,7 +125,7 @@ typedef struct
|
|||
/* Bit fields for CRYOTIMER EM4WUEN */
|
||||
#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */
|
||||
#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */
|
||||
#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
|
||||
#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
|
||||
|
|
@ -127,7 +134,7 @@ typedef struct
|
|||
/* Bit fields for CRYOTIMER IF */
|
||||
#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */
|
||||
#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */
|
||||
#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */
|
||||
#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */
|
||||
#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */
|
||||
|
|
@ -160,6 +167,6 @@ typedef struct
|
|||
#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */
|
||||
#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_CRYOTIMER */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,110 +1,117 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_crypto.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_CRYPTO register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CRYPTO
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CRYPTO CRYPTO
|
||||
* @{
|
||||
* @brief EFM32PG1B_CRYPTO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** CRYPTO Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t WAC; /**< Wide Arithmetic Configuration */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t DSTATUS; /**< Data Status Register */
|
||||
__IM uint32_t CSTATUS; /**< Control Status Register */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t KEY; /**< KEY Register Access */
|
||||
__IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */
|
||||
uint32_t RESERVED2[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t SEQCTRL; /**< Sequence Control */
|
||||
__IOM uint32_t SEQCTRLB; /**< Sequence Control B */
|
||||
uint32_t RESERVED3[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED3[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< AES Interrupt Flags */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t SEQ0; /**< Sequence register 0 */
|
||||
__IOM uint32_t SEQ0; /**< Sequence Register 0 */
|
||||
__IOM uint32_t SEQ1; /**< Sequence Register 1 */
|
||||
__IOM uint32_t SEQ2; /**< Sequence Register 2 */
|
||||
__IOM uint32_t SEQ3; /**< Sequence Register 3 */
|
||||
__IOM uint32_t SEQ4; /**< Sequence Register 4 */
|
||||
uint32_t RESERVED4[7]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED4[7U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DATA0; /**< DATA0 Register Access */
|
||||
__IOM uint32_t DATA1; /**< DATA1 Register Access */
|
||||
__IOM uint32_t DATA2; /**< DATA2 Register Access */
|
||||
__IOM uint32_t DATA3; /**< DATA3 Register Access */
|
||||
uint32_t RESERVED5[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED5[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */
|
||||
uint32_t RESERVED6[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED6[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */
|
||||
__IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */
|
||||
uint32_t RESERVED7[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED7[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */
|
||||
__IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */
|
||||
__IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */
|
||||
__IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */
|
||||
__IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */
|
||||
uint32_t RESERVED8[12]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED8[12U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DDATA0; /**< DDATA0 Register Access */
|
||||
__IOM uint32_t DDATA1; /**< DDATA1 Register Access */
|
||||
__IOM uint32_t DDATA2; /**< DDATA2 Register Access */
|
||||
__IOM uint32_t DDATA3; /**< DDATA3 Register Access */
|
||||
__IOM uint32_t DDATA4; /**< DDATA4 Register Access */
|
||||
uint32_t RESERVED9[7]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED9[7U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */
|
||||
uint32_t RESERVED10[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED10[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */
|
||||
__IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */
|
||||
__IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 access. */
|
||||
uint32_t RESERVED11[13]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 Access */
|
||||
uint32_t RESERVED11[13U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t QDATA0; /**< QDATA0 Register Access */
|
||||
__IOM uint32_t QDATA1; /**< QDATA1 Register Access */
|
||||
uint32_t RESERVED12[7]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED12[7U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */
|
||||
uint32_t RESERVED13[6]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED13[6U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */
|
||||
__IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */
|
||||
} CRYPTO_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_CRYPTO_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_CRYPTO
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_CRYPTO_BitFields CRYPTO Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for CRYPTO CTRL */
|
||||
#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */
|
||||
|
|
@ -645,12 +652,12 @@ typedef struct
|
|||
#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */
|
||||
#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
|
||||
#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
|
||||
#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is active */
|
||||
#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is Active */
|
||||
#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */
|
||||
#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */
|
||||
#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
|
||||
#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
|
||||
#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is active */
|
||||
#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is Active */
|
||||
#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */
|
||||
#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */
|
||||
#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
|
||||
|
|
@ -793,12 +800,12 @@ typedef struct
|
|||
#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */
|
||||
#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
|
||||
#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
|
||||
#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve A */
|
||||
#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve a */
|
||||
#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */
|
||||
#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */
|
||||
#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
|
||||
#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
|
||||
#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve A */
|
||||
#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve a */
|
||||
#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */
|
||||
#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */
|
||||
#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
|
||||
|
|
@ -830,7 +837,7 @@ typedef struct
|
|||
/* Bit fields for CRYPTO IF */
|
||||
#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */
|
||||
#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */
|
||||
#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction done */
|
||||
#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction Done */
|
||||
#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
|
||||
#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
|
||||
#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */
|
||||
|
|
@ -1191,6 +1198,6 @@ typedef struct
|
|||
#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */
|
||||
#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_CRYPTO */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,95 +1,100 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_devinfo.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_DEVINFO register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_DEVINFO
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_DEVINFO Device Information and Calibration
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/** DEVINFO Register Declaration */
|
||||
typedef struct {
|
||||
__IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */
|
||||
uint32_t RESERVED0[9]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[9U]; /**< Reserved for future use **/
|
||||
__IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
|
||||
__IM uint32_t EUI48H; /**< OUI */
|
||||
__IM uint32_t CUSTOMINFO; /**< Custom information */
|
||||
__IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */
|
||||
uint32_t RESERVED1[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
|
||||
__IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
|
||||
__IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
|
||||
__IM uint32_t PART; /**< Part description */
|
||||
__IM uint32_t DEVINFOREV; /**< Device information page revision */
|
||||
__IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
|
||||
uint32_t RESERVED2[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
|
||||
__IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
|
||||
__IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
|
||||
__IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
|
||||
uint32_t RESERVED3[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED3[4U]; /**< Reserved for future use **/
|
||||
__IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
|
||||
uint32_t RESERVED4[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED4[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
|
||||
uint32_t RESERVED5[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED5[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
|
||||
__IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
|
||||
__IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
|
||||
uint32_t RESERVED6[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED6[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
|
||||
__IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
|
||||
__IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
|
||||
uint32_t RESERVED7[11]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED7[11U]; /**< Reserved for future use **/
|
||||
__IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
|
||||
uint32_t RESERVED8[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED8[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
|
||||
uint32_t RESERVED9[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED9[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
|
||||
__IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
|
||||
__IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
|
||||
uint32_t RESERVED10[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED10[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
|
||||
__IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
|
||||
__IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
|
||||
uint32_t RESERVED11[11]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED11[11U]; /**< Reserved for future use **/
|
||||
__IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
|
||||
__IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
|
||||
__IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
|
||||
uint32_t RESERVED12[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED12[3U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
|
||||
__IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
|
||||
uint32_t RESERVED13[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED13[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
|
||||
__IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
|
||||
__IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
|
||||
|
|
@ -99,10 +104,12 @@ typedef struct
|
|||
__IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */
|
||||
} DEVINFO_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_DEVINFO_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_DEVINFO
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_DEVINFO_BitFields DEVINFO Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for DEVINFO CAL */
|
||||
#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
|
||||
|
|
@ -186,7 +193,6 @@ typedef struct
|
|||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */
|
||||
|
|
@ -201,9 +207,20 @@ typedef struct
|
|||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL /**< Mode EFR32ZG14P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
|
||||
|
|
@ -222,8 +239,9 @@ typedef struct
|
|||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL /**< Mode EFM32GG12B for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
|
||||
|
|
@ -237,7 +255,6 @@ typedef struct
|
|||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */
|
||||
|
|
@ -252,9 +269,20 @@ typedef struct
|
|||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P << 16) /**< Shifted mode EFR32ZG14P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
|
||||
|
|
@ -273,8 +301,9 @@ typedef struct
|
|||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B << 16) /**< Shifted mode EFM32GG12B for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
|
||||
#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
|
||||
|
|
@ -789,6 +818,6 @@ typedef struct
|
|||
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
|
||||
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_DEVINFO */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,44 +1,49 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_dma_descriptor.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_DMA_DESCRIPTOR
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_DMA_DESCRIPTOR DMA Descriptor
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** DMA_DESCRIPTOR Register Declaration */
|
||||
typedef struct {
|
||||
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
|
||||
/* pointer and referenced memory are declared volatile. */
|
||||
__IOM uint32_t CTRL; /**< DMA control register */
|
||||
|
|
@ -48,5 +53,3 @@ typedef struct
|
|||
} DMA_DESCRIPTOR_TypeDef; /**< @} */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,43 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_dmareq.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_DMAREQ register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_DMAREQ_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_DMAREQ DMAREQ
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_DMAREQ_BitFields DMAREQ Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
|
||||
#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
|
||||
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
|
||||
|
|
@ -71,6 +78,6 @@
|
|||
#define DMAREQ_CRYPTO_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO_DATA1WR */
|
||||
#define DMAREQ_CRYPTO_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO_DATA1RD */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_DMAREQ */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,65 +1,70 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_emu.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_EMU register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_EMU
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_EMU EMU
|
||||
* @{
|
||||
* @brief EFM32PG1B_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** EMU Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IOM uint32_t RAM0CTRL; /**< Memory Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t EM4CTRL; /**< EM4 Control Register */
|
||||
__IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */
|
||||
__IM uint32_t TEMP; /**< Value of last temperature measurement */
|
||||
__IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */
|
||||
__IM uint32_t TEMP; /**< Value of Last Temperature Measurement */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
|
||||
__IOM uint32_t PWRCFG; /**< Power Configuration Register */
|
||||
__IOM uint32_t PWRCTRL; /**< Power Control Register. */
|
||||
__IOM uint32_t PWRCTRL; /**< Power Control Register */
|
||||
__IOM uint32_t DCDCCTRL; /**< DCDC Control */
|
||||
|
||||
uint32_t RESERVED1[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
|
||||
__IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
|
||||
__IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
|
||||
|
|
@ -68,33 +73,35 @@ typedef struct
|
|||
__IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */
|
||||
__IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
|
||||
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
|
||||
__IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
|
||||
|
||||
uint32_t RESERVED3[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED3[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */
|
||||
|
||||
uint32_t RESERVED4[5]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED4[5U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
|
||||
__IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
|
||||
__IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
|
||||
__IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
|
||||
|
||||
uint32_t RESERVED5[49]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED5[49U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */
|
||||
|
||||
uint32_t RESERVED6[10]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED6[10U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t TESTLOCK; /**< Test Lock Register */
|
||||
|
||||
uint32_t RESERVED7[2]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BIASTESTCTRL; /**< Test Control Register for regulator and BIAS */
|
||||
uint32_t RESERVED7[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BIASTESTCTRL; /**< Test Control Register for Regulator and BIAS */
|
||||
} EMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_EMU_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_EMU
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_EMU_BitFields EMU Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
|
|
@ -108,32 +115,32 @@ typedef struct
|
|||
/* Bit fields for EMU STATUS */
|
||||
#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
|
||||
#define _EMU_STATUS_MASK 0x0010011FUL /**< Mask for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */
|
||||
#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */
|
||||
#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
|
||||
#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
|
||||
#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */
|
||||
#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */
|
||||
#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
|
||||
#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
|
||||
#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */
|
||||
#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */
|
||||
#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
|
||||
#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
|
||||
#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */
|
||||
#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */
|
||||
#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
|
||||
#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
|
||||
#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */
|
||||
#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */
|
||||
#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
|
||||
#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
|
||||
#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
|
||||
#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */
|
||||
#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel */
|
||||
#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */
|
||||
#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */
|
||||
#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
|
||||
|
|
@ -203,17 +210,17 @@ typedef struct
|
|||
#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
|
||||
#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
|
||||
#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
|
||||
#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */
|
||||
#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */
|
||||
#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
|
||||
#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
|
||||
#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
|
||||
#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
|
||||
#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */
|
||||
#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */
|
||||
#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
|
||||
#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
|
||||
#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
|
||||
#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
|
||||
#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */
|
||||
#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */
|
||||
#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
|
||||
#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
|
||||
#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
|
||||
|
|
@ -244,7 +251,7 @@ typedef struct
|
|||
#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
|
||||
#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
|
||||
#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
|
||||
#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */
|
||||
#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */
|
||||
#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
|
||||
#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
|
||||
#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
|
||||
|
|
@ -311,32 +318,32 @@ typedef struct
|
|||
#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
|
||||
#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */
|
||||
#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */
|
||||
#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
|
||||
#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
|
||||
#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */
|
||||
#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */
|
||||
#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
|
||||
#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
|
||||
#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */
|
||||
#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */
|
||||
#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
|
||||
#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
|
||||
#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */
|
||||
#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */
|
||||
#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
|
||||
#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
|
||||
#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */
|
||||
#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */
|
||||
#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
|
||||
#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
|
||||
#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
|
||||
#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */
|
||||
#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */
|
||||
#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
|
||||
#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
|
||||
#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
|
||||
|
|
@ -732,7 +739,7 @@ typedef struct
|
|||
/* Bit fields for EMU DCDCMISCCTRL */
|
||||
#define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL /**< Default value for EMU_DCDCMISCCTRL */
|
||||
#define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL /**< Mask for EMU_DCDCMISCCTRL */
|
||||
#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */
|
||||
#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */
|
||||
#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
|
||||
#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
|
||||
#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
|
||||
|
|
@ -847,7 +854,7 @@ typedef struct
|
|||
#define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL /**< Bit mask for EMU_LPINITWAIT */
|
||||
#define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
|
||||
#define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
|
||||
#define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN mode precharge enable */
|
||||
#define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN Mode Precharge Enable */
|
||||
#define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11 /**< Shift value for EMU_COMPENPRCHGEN */
|
||||
#define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL /**< Bit mask for EMU_COMPENPRCHGEN */
|
||||
#define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCTIMING */
|
||||
|
|
@ -868,7 +875,7 @@ typedef struct
|
|||
/* Bit fields for EMU DCDCLPVCTRL */
|
||||
#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
|
||||
#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
|
||||
#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */
|
||||
#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */
|
||||
#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
|
||||
#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
|
||||
#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
|
||||
|
|
@ -889,7 +896,7 @@ typedef struct
|
|||
#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSEL */
|
||||
#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
|
||||
#define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
|
||||
#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */
|
||||
#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */
|
||||
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
|
||||
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
|
||||
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
|
||||
|
|
@ -914,7 +921,7 @@ typedef struct
|
|||
/* Bit fields for EMU DCDCSYNC */
|
||||
#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
|
||||
#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
|
||||
#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */
|
||||
#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */
|
||||
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
|
||||
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
|
||||
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
|
||||
|
|
@ -1027,7 +1034,7 @@ typedef struct
|
|||
#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
|
||||
#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
|
||||
#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
|
||||
#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */
|
||||
#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */
|
||||
#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
|
||||
#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
|
||||
#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
|
||||
|
|
@ -1100,6 +1107,6 @@ typedef struct
|
|||
#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */
|
||||
#define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_EMU */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,55 +1,62 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_fpueh.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_FPUEH register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_FPUEH
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_FPUEH FPUEH
|
||||
* @{
|
||||
* @brief EFM32PG1B_FPUEH Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** FPUEH Register Declaration */
|
||||
typedef struct {
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} FPUEH_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_FPUEH_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_FPUEH
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_FPUEH_BitFields FPUEH Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for FPUEH IF */
|
||||
#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
|
||||
|
|
@ -187,6 +194,6 @@ typedef struct
|
|||
#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_FPUEH */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_gpcrc.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_GPCRC register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_GPCRC
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_GPCRC GPCRC
|
||||
* @{
|
||||
* @brief EFM32PG1B_GPCRC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** GPCRC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IOM uint32_t INIT; /**< CRC Init Value */
|
||||
|
|
@ -52,10 +57,12 @@ typedef struct
|
|||
__IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
|
||||
} GPCRC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_GPCRC_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_GPCRC
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_GPCRC_BitFields GPCRC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for GPCRC CTRL */
|
||||
#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
|
||||
|
|
@ -180,6 +187,6 @@ typedef struct
|
|||
#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
|
||||
#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_GPCRC */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,48 +1,53 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_gpio.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_GPIO register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_GPIO
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_GPIO GPIO
|
||||
* @{
|
||||
* @brief EFM32PG1B_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
GPIO_P_TypeDef P[6]; /**< Port configuration bits */
|
||||
******************************************************************************/
|
||||
/** GPIO Register Declaration */
|
||||
typedef struct {
|
||||
GPIO_P_TypeDef P[6U]; /**< Port configuration bits */
|
||||
|
||||
uint32_t RESERVED0[184]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[184U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
|
||||
__IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
|
||||
__IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */
|
||||
|
|
@ -54,26 +59,28 @@ typedef struct
|
|||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t EM4WUEN; /**< EM4 wake up Enable Register */
|
||||
__IOM uint32_t EM4WUEN; /**< EM4 Wake Up Enable Register */
|
||||
|
||||
uint32_t RESERVED1[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED2[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INSENSE; /**< Input Sense Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
} GPIO_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_GPIO_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_GPIO
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_GPIO_BitFields GPIO Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for GPIO P_CTRL */
|
||||
#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */
|
||||
#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */
|
||||
#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive strength for port */
|
||||
#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive Strength for Port */
|
||||
#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */
|
||||
#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */
|
||||
#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
|
||||
|
|
@ -86,12 +93,12 @@ typedef struct
|
|||
#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */
|
||||
#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
|
||||
#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
|
||||
#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */
|
||||
#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data in Disable */
|
||||
#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */
|
||||
#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */
|
||||
#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
|
||||
#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
|
||||
#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate drive strength for port */
|
||||
#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate Drive Strength for Port */
|
||||
#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */
|
||||
#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */
|
||||
#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
|
||||
|
|
@ -104,7 +111,7 @@ typedef struct
|
|||
#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */
|
||||
#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
|
||||
#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
|
||||
#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data In Disable */
|
||||
#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data in Disable */
|
||||
#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */
|
||||
#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */
|
||||
#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
|
||||
|
|
@ -1347,6 +1354,6 @@ typedef struct
|
|||
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
|
||||
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_GPIO */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,56 +1,59 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_gpio_p.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_GPIO_P register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief GPIO_P EFM32PG1B GPIO P
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/***************************************************************************//**
|
||||
* @brief GPIO_P GPIO P Register
|
||||
* @ingroup EFM32PG1B_GPIO
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Port Control Register */
|
||||
__IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
|
||||
__IOM uint32_t MODEH; /**< Port Pin Mode High Register */
|
||||
__IOM uint32_t DOUT; /**< Port Data Out Register */
|
||||
uint32_t RESERVED0[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
|
||||
__IM uint32_t DIN; /**< Port Data In Register */
|
||||
__IM uint32_t DIN; /**< Port Data in Register */
|
||||
__IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
__IOM uint32_t OVTDIS; /**< Over Voltage Disable for all modes */
|
||||
uint32_t RESERVED2[1]; /**< Reserved future */
|
||||
uint32_t RESERVED1[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */
|
||||
uint32_t RESERVED2[1U]; /**< Reserved future */
|
||||
} GPIO_P_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_i2c.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_I2C register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_I2C
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_I2C I2C
|
||||
* @{
|
||||
* @brief EFM32PG1B_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** I2C Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATE; /**< State Register */
|
||||
|
|
@ -61,10 +66,12 @@ typedef struct
|
|||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
} I2C_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_I2C_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_I2C
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_I2C_BitFields I2C Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for I2C CTRL */
|
||||
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
|
||||
|
|
@ -84,7 +91,7 @@ typedef struct
|
|||
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
|
||||
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
|
||||
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */
|
||||
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
|
|
@ -160,12 +167,12 @@ typedef struct
|
|||
/* Bit fields for I2C CMD */
|
||||
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
|
||||
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
|
||||
#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
|
||||
#define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */
|
||||
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
|
||||
#define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */
|
||||
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
|
|
@ -180,12 +187,12 @@ typedef struct
|
|||
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
|
||||
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */
|
||||
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
|
||||
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */
|
||||
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
|
|
@ -271,12 +278,12 @@ typedef struct
|
|||
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
|
||||
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
|
||||
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */
|
||||
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
|
||||
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */
|
||||
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
|
|
@ -389,12 +396,12 @@ typedef struct
|
|||
/* Bit fields for I2C IF */
|
||||
#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
|
||||
#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
|
||||
#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
|
||||
#define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */
|
||||
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
|
||||
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */
|
||||
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
|
|
@ -412,7 +419,7 @@ typedef struct
|
|||
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
|
||||
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define _I2C_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
|
||||
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
|
||||
|
|
@ -469,7 +476,7 @@ typedef struct
|
|||
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
|
||||
#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */
|
||||
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
|
|
@ -916,6 +923,6 @@ typedef struct
|
|||
#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_I2C */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,66 +1,73 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_idac.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_IDAC register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_IDAC
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_IDAC IDAC
|
||||
* @{
|
||||
* @brief EFM32PG1B_IDAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** IDAC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CURPROG; /**< Current Programming Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */
|
||||
|
||||
uint32_t RESERVED1[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
uint32_t RESERVED3[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED3[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
|
||||
__IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
|
||||
} IDAC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_IDAC_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_IDAC
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_IDAC_BitFields IDAC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for IDAC CTRL */
|
||||
#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
|
||||
|
|
@ -233,7 +240,7 @@ typedef struct
|
|||
/* Bit fields for IDAC DUTYCONFIG */
|
||||
#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
|
||||
#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
|
||||
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */
|
||||
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
|
||||
|
|
@ -287,12 +294,12 @@ typedef struct
|
|||
/* Bit fields for IDAC APORTREQ */
|
||||
#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
|
||||
#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */
|
||||
#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */
|
||||
#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
|
||||
|
|
@ -301,17 +308,17 @@ typedef struct
|
|||
/* Bit fields for IDAC APORTCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
|
||||
#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
|
||||
#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_IDAC */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,49 +1,54 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_ldma.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_LDMA register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LDMA
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LDMA LDMA
|
||||
* @{
|
||||
* @brief EFM32PG1B_LDMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** LDMA Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< DMA Control Register */
|
||||
__IM uint32_t STATUS; /**< DMA Status Register */
|
||||
__IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
|
||||
uint32_t RESERVED0[5]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[5U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
|
||||
__IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
|
||||
__IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
|
||||
|
|
@ -53,20 +58,22 @@ typedef struct
|
|||
__IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
|
||||
__IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
|
||||
__IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
|
||||
uint32_t RESERVED1[7]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[7U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED2[4]; /**< Reserved registers */
|
||||
LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */
|
||||
uint32_t RESERVED2[4U]; /**< Reserved registers */
|
||||
LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */
|
||||
} LDMA_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LDMA_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_LDMA
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_LDMA_BitFields LDMA Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LDMA CTRL */
|
||||
#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */
|
||||
|
|
@ -556,6 +563,6 @@ typedef struct
|
|||
#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_LDMA */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,43 +1,48 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_ldma_ch.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_LDMA_CH register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief LDMA_CH EFM32PG1B LDMA CH
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/***************************************************************************//**
|
||||
* @brief LDMA_CH LDMA CH Register
|
||||
* @ingroup EFM32PG1B_LDMA
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */
|
||||
__IOM uint32_t CFG; /**< Channel Configuration Register */
|
||||
__IOM uint32_t LOOP; /**< Channel Loop Counter Register */
|
||||
|
|
@ -45,9 +50,7 @@ typedef struct
|
|||
__IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */
|
||||
__IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */
|
||||
__IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */
|
||||
uint32_t RESERVED0[5]; /**< Reserved future */
|
||||
uint32_t RESERVED0[5U]; /**< Reserved future */
|
||||
} LDMA_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_letimer.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_LETIMER register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LETIMER
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LETIMER LETIMER
|
||||
* @{
|
||||
* @brief EFM32PG1B_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** LETIMER Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
|
@ -53,21 +58,23 @@ typedef struct
|
|||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED1[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED2[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t PRSSEL; /**< PRS Input Select Register */
|
||||
} LETIMER_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LETIMER_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_LETIMER
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_LETIMER_BitFields LETIMER Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LETIMER CTRL */
|
||||
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
|
||||
|
|
@ -123,7 +130,7 @@ typedef struct
|
|||
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
|
||||
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */
|
||||
#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 is Top Value */
|
||||
#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
|
||||
#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
|
||||
#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
|
|
@ -615,6 +622,6 @@ typedef struct
|
|||
#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_LETIMER */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_leuart.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_LEUART register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LEUART
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LEUART LEUART
|
||||
* @{
|
||||
* @brief EFM32PG1B_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** LEUART Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
|
@ -60,17 +65,19 @@ typedef struct
|
|||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
uint32_t RESERVED1[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INPUT; /**< LEUART Input Register */
|
||||
} LEUART_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_LEUART_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_LEUART
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_LEUART_BitFields LEUART Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LEUART CTRL */
|
||||
#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
|
||||
|
|
@ -108,12 +115,12 @@ typedef struct
|
|||
#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
|
||||
#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */
|
||||
#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */
|
||||
#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
|
||||
#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
|
||||
#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */
|
||||
#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */
|
||||
#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
|
||||
#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
|
||||
#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
|
|
@ -324,7 +331,7 @@ typedef struct
|
|||
#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
|
||||
#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
|
||||
#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
|
||||
#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
|
||||
#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
|
|
@ -830,6 +837,6 @@ typedef struct
|
|||
#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_LEUART */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,55 +1,60 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_msc.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_MSC register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_MSC
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_MSC MSC
|
||||
* @{
|
||||
* @brief EFM32PG1B_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** MSC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Memory System Control Register */
|
||||
__IOM uint32_t READCTRL; /**< Read Control Register */
|
||||
__IOM uint32_t WRITECTRL; /**< Write Control Register */
|
||||
__IOM uint32_t WRITECMD; /**< Write Command Register */
|
||||
__IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t WDATA; /**< Write Data Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
||||
uint32_t RESERVED1[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[4U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
|
|
@ -59,20 +64,22 @@ typedef struct
|
|||
__IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
|
||||
__IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
|
||||
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
|
||||
|
||||
uint32_t RESERVED3[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED3[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t STARTUP; /**< Startup Control */
|
||||
|
||||
uint32_t RESERVED4[5]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED4[5U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
} MSC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_MSC_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_MSC
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_MSC_BitFields MSC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for MSC CTRL */
|
||||
#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
|
||||
|
|
@ -87,7 +94,7 @@ typedef struct
|
|||
#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
|
||||
#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */
|
||||
#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */
|
||||
#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
|
||||
#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
|
||||
#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
|
|
@ -157,7 +164,7 @@ typedef struct
|
|||
/* Bit fields for MSC WRITECMD */
|
||||
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
|
||||
#define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
|
||||
#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */
|
||||
#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
|
||||
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
|
||||
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
|
|
@ -182,17 +189,17 @@ typedef struct
|
|||
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
|
||||
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
|
||||
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */
|
||||
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
|
||||
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
|
||||
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
|
||||
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
|
||||
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */
|
||||
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
|
||||
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
|
||||
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
|
|
@ -281,7 +288,7 @@ typedef struct
|
|||
#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
|
||||
#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */
|
||||
#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */
|
||||
#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
|
||||
#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
|
||||
#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
|
|
@ -496,6 +503,6 @@ typedef struct
|
|||
#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
|
||||
#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_MSC */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_pcnt.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_PCNT register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_PCNT
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_PCNT PCNT
|
||||
* @{
|
||||
* @brief EFM32PG1B_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** PCNT Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
|
@ -50,23 +55,25 @@ typedef struct
|
|||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED1[4]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED2[7]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[7U]; /**< Reserved for future use **/
|
||||
__IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
|
||||
__IOM uint32_t INPUT; /**< PCNT Input Register */
|
||||
__IOM uint32_t OVSCFG; /**< Oversampling Config Register */
|
||||
} PCNT_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_PCNT_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_PCNT
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_PCNT_BitFields PCNT Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for PCNT CTRL */
|
||||
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
|
||||
|
|
@ -119,7 +126,7 @@ typedef struct
|
|||
#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */
|
||||
#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */
|
||||
#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count Direction Determined By S1 */
|
||||
#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */
|
||||
#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */
|
||||
#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
|
|
@ -198,12 +205,12 @@ typedef struct
|
|||
#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */
|
||||
#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS Gate Enable */
|
||||
#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */
|
||||
#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */
|
||||
#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */
|
||||
#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS Polarity Select */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
|
|
@ -240,7 +247,7 @@ typedef struct
|
|||
#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */
|
||||
#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High Frequency Value Select */
|
||||
#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */
|
||||
#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */
|
||||
#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
|
|
@ -320,7 +327,7 @@ typedef struct
|
|||
#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
|
||||
#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */
|
||||
#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered Compare Interrupt Read Flag */
|
||||
#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
|
||||
#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
|
||||
#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
|
|
@ -701,6 +708,6 @@ typedef struct
|
|||
#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
|
||||
#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_PCNT */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,68 +1,75 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_prs.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_PRS register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_PRS
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_PRS PRS
|
||||
* @{
|
||||
* @brief EFM32PG1B_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** PRS Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t SWPULSE; /**< Software Pulse Register */
|
||||
__IOM uint32_t SWLEVEL; /**< Software Level Register */
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
__IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
|
||||
__IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */
|
||||
__IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */
|
||||
uint32_t RESERVED2[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t PEEK; /**< PRS Channel Values */
|
||||
|
||||
uint32_t RESERVED3[3]; /**< Reserved registers */
|
||||
PRS_CH_TypeDef CH[12]; /**< Channel registers */
|
||||
uint32_t RESERVED3[3U]; /**< Reserved registers */
|
||||
PRS_CH_TypeDef CH[12U]; /**< Channel registers */
|
||||
} PRS_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_PRS_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_PRS
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_PRS_BitFields PRS Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for PRS SWPULSE */
|
||||
#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
|
||||
|
|
@ -944,12 +951,12 @@ typedef struct
|
|||
#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */
|
||||
#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */
|
||||
#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */
|
||||
#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */
|
||||
#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */
|
||||
#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_PRS */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,49 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_prs_ch.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_PRS_CH register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief PRS_CH EFM32PG1B PRS CH
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/***************************************************************************//**
|
||||
* @brief PRS_CH PRS CH Register
|
||||
* @ingroup EFM32PG1B_PRS
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Channel Control Register */
|
||||
} PRS_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,43 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_prs_signals.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_PRS_SIGNALS register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_PRS_Signals
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_PRS
|
||||
* @{
|
||||
* @addtogroup EFM32PG1B_PRS_Signals PRS Signals
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */
|
||||
#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */
|
||||
#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */
|
||||
|
|
@ -76,6 +83,22 @@
|
|||
#define PRS_TIMER1_CC1 ((29 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */
|
||||
#define PRS_TIMER1_CC2 ((29 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */
|
||||
#define PRS_TIMER1_CC3 ((29 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */
|
||||
#define PRS_RAC_ACTIVE ((32 << 8) + 0) /**< PRS RAC is active */
|
||||
#define PRS_RAC_TX ((32 << 8) + 1) /**< PRS RAC is in TX */
|
||||
#define PRS_RAC_RX ((32 << 8) + 2) /**< PRS RAC is in RX */
|
||||
#define PRS_RAC_LNAEN ((32 << 8) + 3) /**< PRS LNA enable */
|
||||
#define PRS_RAC_PAEN ((32 << 8) + 4) /**< PRS PA enable */
|
||||
#define PRS_PROTIMER_LBTS ((35 << 8) + 5) /**< PRS Listen Before Talk Success */
|
||||
#define PRS_PROTIMER_LBTR ((35 << 8) + 6) /**< PRS Listen Before Talk Retry */
|
||||
#define PRS_PROTIMER_LBTF ((35 << 8) + 7) /**< PRS Listen Before Talk Failure */
|
||||
#define PRS_MODEM_FRAMEDET ((38 << 8) + 0) /**< PRS Frame detected */
|
||||
#define PRS_MODEM_PREDET ((38 << 8) + 1) /**< PRS Receive preamble detected */
|
||||
#define PRS_MODEM_TIMDET ((38 << 8) + 2) /**< PRS Receive timing detected */
|
||||
#define PRS_MODEM_FRAMESENT ((38 << 8) + 3) /**< PRS Entire frame transmitted */
|
||||
#define PRS_MODEM_SYNCSENT ((38 << 8) + 4) /**< PRS Syncword transmitted */
|
||||
#define PRS_MODEM_PRESENT ((38 << 8) + 5) /**< PRS Preamble transmitted */
|
||||
#define PRS_MODEM_ANT0 ((39 << 8) + 5) /**< PRS Antenna 0 select */
|
||||
#define PRS_MODEM_ANT1 ((39 << 8) + 6) /**< PRS Antenna 1 select */
|
||||
#define PRS_RTCC_CCV0 ((41 << 8) + 1) /**< PRS RTCC Compare 0 */
|
||||
#define PRS_RTCC_CCV1 ((41 << 8) + 2) /**< PRS RTCC Compare 1 */
|
||||
#define PRS_RTCC_CCV2 ((41 << 8) + 3) /**< PRS RTCC Compare 2 */
|
||||
|
|
@ -100,11 +123,12 @@
|
|||
#define PRS_PCNT0_TCC ((54 << 8) + 0) /**< PRS Triggered compare match */
|
||||
#define PRS_PCNT0_UFOF ((54 << 8) + 1) /**< PRS Counter overflow or underflow */
|
||||
#define PRS_PCNT0_DIR ((54 << 8) + 2) /**< PRS Counter direction */
|
||||
#define PRS_RFSENSE_WU ((59 << 8) + 0) /**< PRS RFSENSE Output */
|
||||
#define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */
|
||||
#define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */
|
||||
#define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */
|
||||
#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_PRS */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_rmu.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_RMU register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_RMU
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_RMU RMU
|
||||
* @{
|
||||
* @brief EFM32PG1B_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** RMU Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IM uint32_t RSTCAUSE; /**< Reset Cause Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
|
|
@ -47,10 +52,12 @@ typedef struct
|
|||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
} RMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_RMU_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_RMU
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_RMU_BitFields RMU Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for RMU CTRL */
|
||||
#define _RMU_CTRL_RESETVALUE 0x00004224UL /**< Default value for RMU_CTRL */
|
||||
|
|
@ -111,7 +118,7 @@ typedef struct
|
|||
/* Bit fields for RMU RSTCAUSE */
|
||||
#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
|
||||
#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
|
||||
#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power on Reset */
|
||||
#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
|
||||
#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
|
||||
#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
|
|
@ -186,6 +193,6 @@ typedef struct
|
|||
#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
|
||||
#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_RMU */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_romtable.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_ROMTABLE register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ROMTABLE
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ROMTABLE ROM Table, Chip Revision Information
|
||||
* @{
|
||||
* @brief Chip Information, Revision numbers
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** ROMTABLE Register Declaration */
|
||||
typedef struct {
|
||||
__IM uint32_t PID4; /**< JEP_106_BANK */
|
||||
__IM uint32_t PID5; /**< Unused */
|
||||
__IM uint32_t PID6; /**< Unused */
|
||||
|
|
@ -51,10 +56,12 @@ typedef struct
|
|||
__IM uint32_t CID0; /**< Unused */
|
||||
} ROMTABLE_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_ROMTABLE_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_ROMTABLE
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_ROMTABLE_BitFields ROM Table Bit Field definitions
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/* Bit fields for EFM32PG1B_ROMTABLE */
|
||||
#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
|
||||
#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
|
||||
|
|
@ -67,6 +74,6 @@ typedef struct
|
|||
#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
|
||||
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_ROMTABLE */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,72 +1,79 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_rtcc.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_RTCC register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_RTCC
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_RTCC RTCC
|
||||
* @{
|
||||
* @brief EFM32PG1B_RTCC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** RTCC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
|
||||
__IOM uint32_t CNT; /**< Counter Value Register */
|
||||
__IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
|
||||
__IOM uint32_t TIME; /**< Time of day register */
|
||||
__IOM uint32_t DATE; /**< Date register */
|
||||
__IOM uint32_t TIME; /**< Time of Day Register */
|
||||
__IOM uint32_t DATE; /**< Date Register */
|
||||
__IM uint32_t IF; /**< RTCC Interrupt Flags */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IM uint32_t STATUS; /**< Status register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
__IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */
|
||||
__IOM uint32_t POWERDOWN; /**< Retention RAM Power-down Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IOM uint32_t EM4WUEN; /**< Wake Up Enable */
|
||||
|
||||
RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */
|
||||
RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */
|
||||
|
||||
uint32_t RESERVED0[37]; /**< Reserved registers */
|
||||
RTCC_RET_TypeDef RET[32]; /**< RetentionReg */
|
||||
uint32_t RESERVED0[37U]; /**< Reserved registers */
|
||||
RTCC_RET_TypeDef RET[32U]; /**< RetentionReg */
|
||||
} RTCC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_RTCC_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_RTCC
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_RTCC_BitFields RTCC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for RTCC CTRL */
|
||||
#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */
|
||||
|
|
@ -81,12 +88,12 @@ typedef struct
|
|||
#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */
|
||||
#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */
|
||||
#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 Top Value Enable */
|
||||
#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */
|
||||
#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */
|
||||
#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */
|
||||
#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 Top Value Enable */
|
||||
#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */
|
||||
#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */
|
||||
#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
|
||||
|
|
@ -127,7 +134,7 @@ typedef struct
|
|||
#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */
|
||||
#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter Prescaler Mode */
|
||||
#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */
|
||||
#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */
|
||||
#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
|
||||
|
|
@ -136,12 +143,12 @@ typedef struct
|
|||
#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */
|
||||
#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */
|
||||
#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator Failure Detection Enable */
|
||||
#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */
|
||||
#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */
|
||||
#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */
|
||||
#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main Counter Mode */
|
||||
#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */
|
||||
#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */
|
||||
#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
|
||||
|
|
@ -150,7 +157,7 @@ typedef struct
|
|||
#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */
|
||||
#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */
|
||||
#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */
|
||||
#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap Year Correction Disabled */
|
||||
#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */
|
||||
#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */
|
||||
#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
|
||||
|
|
@ -227,7 +234,7 @@ typedef struct
|
|||
#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */
|
||||
#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
|
||||
#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */
|
||||
#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
|
||||
#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
|
||||
#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */
|
||||
#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */
|
||||
#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
|
||||
|
|
@ -268,37 +275,37 @@ typedef struct
|
|||
#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
|
||||
#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */
|
||||
#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator Failure Interrupt Flag */
|
||||
#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
|
||||
#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
|
||||
#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */
|
||||
#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main Counter Tick */
|
||||
#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
|
||||
#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
|
||||
#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */
|
||||
#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute Tick */
|
||||
#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
|
||||
#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
|
||||
#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */
|
||||
#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour Tick */
|
||||
#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
|
||||
#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
|
||||
#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */
|
||||
#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day Tick */
|
||||
#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
|
||||
#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
|
||||
#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */
|
||||
#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of Week Overflow */
|
||||
#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
|
||||
#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
|
||||
#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */
|
||||
#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */
|
||||
#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month Tick */
|
||||
#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
|
||||
#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
|
||||
#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
|
||||
|
|
@ -488,7 +495,7 @@ typedef struct
|
|||
/* Bit fields for RTCC CMD */
|
||||
#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */
|
||||
#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */
|
||||
#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */
|
||||
#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS Register */
|
||||
#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */
|
||||
#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */
|
||||
#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */
|
||||
|
|
@ -506,7 +513,7 @@ typedef struct
|
|||
/* Bit fields for RTCC POWERDOWN */
|
||||
#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */
|
||||
#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */
|
||||
#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
|
||||
#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM Power-down */
|
||||
#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */
|
||||
#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */
|
||||
#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */
|
||||
|
|
@ -531,7 +538,7 @@ typedef struct
|
|||
/* Bit fields for RTCC EM4WUEN */
|
||||
#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */
|
||||
#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */
|
||||
#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
|
||||
#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
|
||||
#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */
|
||||
#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */
|
||||
#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */
|
||||
|
|
@ -602,7 +609,7 @@ typedef struct
|
|||
#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
|
||||
#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
|
||||
#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
|
||||
#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */
|
||||
#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture Compare Channel Comparison Base */
|
||||
#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */
|
||||
#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */
|
||||
#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
|
||||
|
|
@ -615,7 +622,7 @@ typedef struct
|
|||
#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */
|
||||
#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
|
||||
#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
|
||||
#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */
|
||||
#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare Selection */
|
||||
#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */
|
||||
#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */
|
||||
#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
|
||||
|
|
@ -676,7 +683,7 @@ typedef struct
|
|||
#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */
|
||||
#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
|
||||
#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
|
||||
#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
|
||||
#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
|
||||
#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */
|
||||
#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */
|
||||
#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
|
||||
|
|
@ -690,6 +697,6 @@ typedef struct
|
|||
#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */
|
||||
#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_RTCC */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,43 +1,48 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_rtcc_cc.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_RTCC_CC register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief RTCC_CC EFM32PG1B RTCC CC
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/***************************************************************************//**
|
||||
* @brief RTCC_CC RTCC CC Register
|
||||
* @ingroup EFM32PG1B_RTCC
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< CC Channel Control Register */
|
||||
__IOM uint32_t CCV; /**< Capture/Compare Value Register */
|
||||
__IOM uint32_t TIME; /**< Capture/Compare Time Register */
|
||||
|
|
@ -45,5 +50,3 @@ typedef struct
|
|||
} RTCC_CC_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,49 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_rtcc_ret.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_RTCC_RET register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief RTCC_RET EFM32PG1B RTCC RET
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t REG; /**< Retention register */
|
||||
/***************************************************************************//**
|
||||
* @brief RTCC_RET RTCC RET Register
|
||||
* @ingroup EFM32PG1B_RTCC
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t REG; /**< Retention Register */
|
||||
} RTCC_RET_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,45 +1,50 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_timer.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_TIMER register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_TIMER
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_TIMER TIMER
|
||||
* @{
|
||||
* @brief EFM32PG1B_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** TIMER Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
|
@ -50,15 +55,15 @@ typedef struct
|
|||
__IOM uint32_t TOP; /**< Counter Top Value Register */
|
||||
__IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
|
||||
__IOM uint32_t CNT; /**< Counter Value Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
uint32_t RESERVED1[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED1[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED2[8]; /**< Reserved registers */
|
||||
TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */
|
||||
uint32_t RESERVED2[8U]; /**< Reserved registers */
|
||||
TIMER_CC_TypeDef CC[4U]; /**< Compare/Capture Channel */
|
||||
|
||||
__IOM uint32_t DTCTRL; /**< DTI Control Register */
|
||||
__IOM uint32_t DTTIME; /**< DTI Time Control Register */
|
||||
|
|
@ -69,10 +74,12 @@ typedef struct
|
|||
__IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */
|
||||
} TIMER_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_TIMER_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_TIMER
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_TIMER_BitFields TIMER Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for TIMER CTRL */
|
||||
#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
|
||||
|
|
@ -188,7 +195,7 @@ typedef struct
|
|||
#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
|
||||
#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
|
||||
#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
|
||||
#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
|
||||
#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
|
||||
#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
|
|
@ -1293,7 +1300,7 @@ typedef struct
|
|||
#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
|
||||
#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
|
||||
#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
|
||||
#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
|
||||
#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
|
||||
#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
|
|
@ -1570,6 +1577,6 @@ typedef struct
|
|||
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
|
||||
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_TIMER */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,43 +1,48 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_timer_cc.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_TIMER_CC register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief TIMER_CC EFM32PG1B TIMER CC
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/***************************************************************************//**
|
||||
* @brief TIMER_CC TIMER CC Register
|
||||
* @ingroup EFM32PG1B_TIMER
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< CC Channel Control Register */
|
||||
__IOM uint32_t CCV; /**< CC Channel Value Register */
|
||||
__IM uint32_t CCVP; /**< CC Channel Value Peek Register */
|
||||
|
|
@ -45,5 +50,3 @@ typedef struct
|
|||
} TIMER_CC_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,48 +1,53 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_usart.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_USART register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_USART
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_USART USART
|
||||
* @{
|
||||
* @brief EFM32PG1B_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** USART Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t FRAME; /**< USART Frame Format Register */
|
||||
__IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */
|
||||
__IOM uint32_t TRIGCTRL; /**< USART Trigger Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< USART Status Register */
|
||||
__IOM uint32_t CLKDIV; /**< Clock Control Register */
|
||||
|
|
@ -61,23 +66,25 @@ typedef struct
|
|||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t IRCTRL; /**< IrDA Control Register */
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INPUT; /**< USART Input Register */
|
||||
__IOM uint32_t I2SCTRL; /**< I2S Control Register */
|
||||
__IOM uint32_t TIMING; /**< Timing Register */
|
||||
__IOM uint32_t CTRLX; /**< Control Register Extended */
|
||||
__IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */
|
||||
__IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */
|
||||
__IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */
|
||||
__IOM uint32_t TIMECMP0; /**< Used to Generate Interrupts and Various Delays */
|
||||
__IOM uint32_t TIMECMP1; /**< Used to Generate Interrupts and Various Delays */
|
||||
__IOM uint32_t TIMECMP2; /**< Used to Generate Interrupts and Various Delays */
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
__IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
|
||||
} USART_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_USART_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_USART
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_USART_BitFields USART Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for USART CTRL */
|
||||
#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
|
||||
|
|
@ -128,7 +135,7 @@ typedef struct
|
|||
#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
|
||||
#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
|
||||
#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
|
||||
#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */
|
||||
#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
|
||||
#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
|
||||
#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
|
|
@ -142,7 +149,7 @@ typedef struct
|
|||
#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
|
||||
#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
|
||||
#define USART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */
|
||||
#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
|
||||
#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
|
||||
#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
|
|
@ -165,7 +172,7 @@ typedef struct
|
|||
#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
|
||||
#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
|
||||
#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */
|
||||
#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
|
||||
#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
|
||||
#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
|
|
@ -205,17 +212,17 @@ typedef struct
|
|||
#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
|
||||
#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
|
||||
#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */
|
||||
#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
|
||||
#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
|
||||
#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
|
||||
#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */
|
||||
#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
|
||||
#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
|
||||
#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
|
||||
#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */
|
||||
#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
|
||||
#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
|
||||
#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
|
|
@ -225,7 +232,7 @@ typedef struct
|
|||
#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
|
||||
#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
|
||||
#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
|
||||
#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */
|
||||
#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
|
||||
#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
|
||||
#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
|
||||
|
|
@ -320,32 +327,32 @@ typedef struct
|
|||
#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
|
||||
#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */
|
||||
#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */
|
||||
#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
|
||||
#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
|
||||
#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */
|
||||
#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */
|
||||
#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
|
||||
#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
|
||||
#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */
|
||||
#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */
|
||||
#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
|
||||
#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
|
||||
#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */
|
||||
#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */
|
||||
#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
|
||||
#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
|
||||
#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */
|
||||
#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */
|
||||
#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
|
||||
#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
|
||||
#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
|
||||
#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */
|
||||
#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */
|
||||
#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
|
||||
#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
|
||||
#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
|
||||
|
|
@ -516,7 +523,7 @@ typedef struct
|
|||
#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
|
||||
#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
|
||||
#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
|
||||
#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */
|
||||
#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */
|
||||
#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
|
||||
#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
|
||||
#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
|
||||
|
|
@ -533,7 +540,7 @@ typedef struct
|
|||
#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
|
||||
#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
|
||||
#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
|
||||
#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
|
||||
#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */
|
||||
#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
|
||||
#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
|
||||
#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
|
||||
|
|
@ -676,7 +683,7 @@ typedef struct
|
|||
#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
|
||||
#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
|
||||
#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
|
||||
#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
|
||||
#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
|
||||
#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
|
||||
#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
|
||||
#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
|
||||
|
|
@ -717,7 +724,7 @@ typedef struct
|
|||
#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
|
||||
#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
|
||||
#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
|
||||
#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
|
||||
#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */
|
||||
#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
|
||||
#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
|
||||
#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
|
||||
|
|
@ -746,7 +753,7 @@ typedef struct
|
|||
#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
|
||||
#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
|
||||
#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
|
||||
#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
|
||||
#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */
|
||||
#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
|
||||
#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
|
||||
#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
|
||||
|
|
@ -832,7 +839,7 @@ typedef struct
|
|||
#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
|
||||
#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
|
||||
#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
|
||||
#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
|
||||
#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */
|
||||
#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
|
||||
#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
|
||||
#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
|
||||
|
|
@ -847,17 +854,17 @@ typedef struct
|
|||
#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
|
||||
#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
|
||||
#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
|
||||
#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */
|
||||
#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */
|
||||
#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
|
||||
#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
|
||||
#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
|
||||
#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
|
||||
#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */
|
||||
#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */
|
||||
#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
|
||||
#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
|
||||
#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
|
||||
#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
|
||||
#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */
|
||||
#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */
|
||||
#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
|
||||
#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
|
||||
#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
|
||||
|
|
@ -1261,12 +1268,12 @@ typedef struct
|
|||
#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
|
||||
#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
|
||||
#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
|
||||
#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
|
||||
#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */
|
||||
#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
|
||||
#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
|
||||
#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
|
||||
#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
|
||||
#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
|
||||
#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */
|
||||
#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
|
||||
#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
|
||||
#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
|
||||
|
|
@ -1379,7 +1386,7 @@ typedef struct
|
|||
/* Bit fields for USART CTRLX */
|
||||
#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
|
||||
#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */
|
||||
#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */
|
||||
#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */
|
||||
#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
|
||||
#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
|
||||
#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
|
||||
|
|
@ -1389,7 +1396,7 @@ typedef struct
|
|||
#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
|
||||
#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
|
||||
#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
|
||||
#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */
|
||||
#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */
|
||||
#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
|
||||
#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
|
||||
#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
|
||||
|
|
@ -1967,6 +1974,6 @@ typedef struct
|
|||
#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
|
||||
#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_USART */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,63 +1,70 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_wdog.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_WDOG register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_WDOG
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32PG1B_WDOG WDOG
|
||||
* @{
|
||||
* @brief EFM32PG1B_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
******************************************************************************/
|
||||
/** WDOG Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
WDOG_PCH_TypeDef PCH[2]; /**< PCH */
|
||||
WDOG_PCH_TypeDef PCH[2U]; /**< PCH */
|
||||
|
||||
uint32_t RESERVED0[2]; /**< Reserved for future use **/
|
||||
uint32_t RESERVED0[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Watchdog Interrupt Flags */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} WDOG_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32PG1B_WDOG_BitFields
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32PG1B_WDOG
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
* @defgroup EFM32PG1B_WDOG_BitFields WDOG Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for WDOG CTRL */
|
||||
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
|
||||
|
|
@ -82,7 +89,7 @@ typedef struct
|
|||
#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
|
||||
#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
|
||||
#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration Lock */
|
||||
#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
|
||||
#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
|
||||
#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
|
|
@ -206,7 +213,7 @@ typedef struct
|
|||
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
|
||||
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
|
||||
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
|
||||
#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */
|
||||
#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS Missing Event Will Trigger a Watchdog Reset */
|
||||
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
|
||||
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
|
||||
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
|
||||
|
|
@ -328,6 +335,6 @@ typedef struct
|
|||
#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
|
||||
#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32PG1B_WDOG */
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,49 @@
|
|||
/**************************************************************************//**
|
||||
* @file efm32pg1b_wdog_pch.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32PG1B_WDOG_PCH register and bit field definitions
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief WDOG_PCH EFM32PG1B WDOG PCH
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/***************************************************************************//**
|
||||
* @brief WDOG_PCH WDOG PCH Register
|
||||
* @ingroup EFM32PG1B_WDOG
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t PRSCTRL; /**< PRS Control Register */
|
||||
} WDOG_PCH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/**************************************************************************//**
|
||||
* @file em_device.h
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
|
||||
* microcontroller devices
|
||||
*
|
||||
|
|
@ -9,37 +9,34 @@
|
|||
* @verbatim
|
||||
* Example: Add "-DEFM32G890F128" to your build options, to define part
|
||||
* Add "#include "em_device.h" to your source files
|
||||
*
|
||||
*
|
||||
* @endverbatim
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef EM_DEVICE_H
|
||||
#define EM_DEVICE_H
|
||||
|
|
|
|||
|
|
@ -1,34 +1,32 @@
|
|||
/***************************************************************************//**
|
||||
* @file system_efm32pg1b.c
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "em_device.h"
|
||||
|
|
@ -39,6 +37,7 @@
|
|||
|
||||
/** LFRCO frequency, tuned to below frequency during manufacturing. */
|
||||
#define EFM32_LFRCO_FREQ (32768UL)
|
||||
/** ULFRCO frequency */
|
||||
#define EFM32_ULFRCO_FREQ (1000UL)
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -54,20 +53,22 @@
|
|||
/* SW footprint. */
|
||||
|
||||
#ifndef EFM32_HFRCO_MAX_FREQ
|
||||
/** Maximum HFRCO frequency */
|
||||
#define EFM32_HFRCO_MAX_FREQ (38000000UL)
|
||||
#endif
|
||||
|
||||
#ifndef EFM32_HFXO_FREQ
|
||||
/** HFXO frequency */
|
||||
#define EFM32_HFXO_FREQ (40000000UL)
|
||||
#endif
|
||||
|
||||
#ifndef EFM32_HFRCO_STARTUP_FREQ
|
||||
/** HFRCO startup frequency */
|
||||
#define EFM32_HFRCO_STARTUP_FREQ (19000000UL)
|
||||
#endif
|
||||
|
||||
|
||||
/* Do not define variable if HF crystal oscillator not present */
|
||||
#if (EFM32_HFXO_FREQ > 0UL)
|
||||
#if (EFM32_HFXO_FREQ > 0U)
|
||||
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
|
||||
/** System HFXO clock. */
|
||||
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
|
||||
|
|
@ -75,17 +76,17 @@ static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
|
|||
#endif
|
||||
|
||||
#ifndef EFM32_LFXO_FREQ
|
||||
/** LFXO frequency */
|
||||
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
|
||||
#endif
|
||||
/* Do not define variable if LF crystal oscillator not present */
|
||||
#if (EFM32_LFXO_FREQ > 0UL)
|
||||
#if (EFM32_LFXO_FREQ > 0U)
|
||||
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
|
||||
/** System LFXO clock. */
|
||||
static uint32_t SystemLFXOClock = 32768UL;
|
||||
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
|
||||
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
************************** GLOBAL VARIABLES *******************************
|
||||
******************************************************************************/
|
||||
|
|
@ -97,8 +98,7 @@ static uint32_t SystemLFXOClock = 32768UL;
|
|||
* @details
|
||||
* Required CMSIS global variable that must be kept up-to-date.
|
||||
*/
|
||||
uint32_t SystemCoreClock;
|
||||
|
||||
uint32_t SystemCoreClock = EFM32_HFRCO_STARTUP_FREQ;
|
||||
|
||||
/**
|
||||
* @brief
|
||||
|
|
@ -112,7 +112,6 @@ uint32_t SystemCoreClock;
|
|||
*/
|
||||
uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
************************** GLOBAL FUNCTIONS *******************************
|
||||
******************************************************************************/
|
||||
|
|
@ -140,9 +139,9 @@ uint32_t SystemCoreClockGet(void)
|
|||
uint32_t presc;
|
||||
|
||||
ret = SystemHFClockGet();
|
||||
presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >>
|
||||
_CMU_HFCOREPRESC_PRESC_SHIFT;
|
||||
ret /= (presc + 1);
|
||||
presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
|
||||
>> _CMU_HFCOREPRESC_PRESC_SHIFT;
|
||||
ret /= presc + 1U;
|
||||
|
||||
/* Keep CMSIS system clock variable up-to-date */
|
||||
SystemCoreClock = ret;
|
||||
|
|
@ -150,7 +149,6 @@ uint32_t SystemCoreClockGet(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get the maximum core clock frequency.
|
||||
|
|
@ -163,11 +161,13 @@ uint32_t SystemCoreClockGet(void)
|
|||
******************************************************************************/
|
||||
uint32_t SystemMaxCoreClockGet(void)
|
||||
{
|
||||
return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
|
||||
EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
|
||||
#if (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ)
|
||||
return EFM32_HFRCO_MAX_FREQ;
|
||||
#else
|
||||
return EFM32_HFXO_FREQ;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get the current HFCLK frequency.
|
||||
|
|
@ -182,15 +182,14 @@ uint32_t SystemHFClockGet(void)
|
|||
{
|
||||
uint32_t ret;
|
||||
|
||||
switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
|
||||
{
|
||||
switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) {
|
||||
case CMU_HFCLKSTATUS_SELECTED_LFXO:
|
||||
#if (EFM32_LFXO_FREQ > 0)
|
||||
#if (EFM32_LFXO_FREQ > 0U)
|
||||
ret = SystemLFXOClock;
|
||||
#else
|
||||
/* We should not get here, since core should not be clocked. May */
|
||||
/* be caused by a misconfiguration though. */
|
||||
ret = 0;
|
||||
ret = 0U;
|
||||
#endif
|
||||
break;
|
||||
|
||||
|
|
@ -199,15 +198,21 @@ uint32_t SystemHFClockGet(void)
|
|||
break;
|
||||
|
||||
case CMU_HFCLKSTATUS_SELECTED_HFXO:
|
||||
#if (EFM32_HFXO_FREQ > 0)
|
||||
#if (EFM32_HFXO_FREQ > 0U)
|
||||
ret = SystemHFXOClock;
|
||||
#else
|
||||
/* We should not get here, since core should not be clocked. May */
|
||||
/* be caused by a misconfiguration though. */
|
||||
ret = 0;
|
||||
ret = 0U;
|
||||
#endif
|
||||
break;
|
||||
|
||||
#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2)
|
||||
case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2:
|
||||
ret = SystemHfrcoFreq / 2;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
|
||||
ret = SystemHfrcoFreq;
|
||||
break;
|
||||
|
|
@ -217,8 +222,7 @@ uint32_t SystemHFClockGet(void)
|
|||
>> _CMU_HFPRESC_PRESC_SHIFT));
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get high frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
|
|
@ -227,19 +231,18 @@ uint32_t SystemHFClockGet(void)
|
|||
*
|
||||
* @return
|
||||
* HFXO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
uint32_t SystemHFXOClockGet(void)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_HFXO_FREQ > 0)
|
||||
#if (EFM32_HFXO_FREQ > 0U)
|
||||
return SystemHFXOClock;
|
||||
#else
|
||||
return 0;
|
||||
return 0U;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Set high frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
|
|
@ -253,26 +256,25 @@ uint32_t SystemHFXOClockGet(void)
|
|||
*
|
||||
* @param[in] freq
|
||||
* HFXO frequency in Hz used for target.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
void SystemHFXOClockSet(uint32_t freq)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_HFXO_FREQ > 0)
|
||||
#if (EFM32_HFXO_FREQ > 0U)
|
||||
SystemHFXOClock = freq;
|
||||
|
||||
/* Update core clock frequency if HFXO is used to clock core */
|
||||
if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO)
|
||||
{
|
||||
if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
|
||||
== CMU_HFCLKSTATUS_SELECTED_HFXO) {
|
||||
/* The function will update the global variable */
|
||||
SystemCoreClockGet();
|
||||
(void)SystemCoreClockGet();
|
||||
}
|
||||
#else
|
||||
(void)freq; /* Unused parameter */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Initialize the system.
|
||||
*
|
||||
|
|
@ -283,18 +285,38 @@ void SystemHFXOClockSet(uint32_t freq)
|
|||
* This function is invoked during system init, before the main() routine
|
||||
* and any data has been initialized. For this reason, it cannot do any
|
||||
* initialization of variables etc.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t)&__Vectors;
|
||||
#endif
|
||||
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
/* Set floating point coprosessor access mode. */
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
SCB->CPACR |= ((3UL << 10 * 2) /* set CP10 Full Access */
|
||||
| (3UL << 11 * 2)); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#if defined(UNALIGNED_SUPPORT_DISABLE)
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1)
|
||||
/****************************
|
||||
* Fix for errata DCDC_E206
|
||||
* Enable bypass switch as errata workaround. The bypass current limit will be
|
||||
* disabled again in CHIP_Init() to avoid added current consumption. */
|
||||
|
||||
EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT;
|
||||
EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK)
|
||||
| EMU_DCDCCTRL_DCDCMODE_BYPASS;
|
||||
*(volatile uint32_t *)(0x400E3074) &= ~(0x1UL << 0);
|
||||
*(volatile uint32_t *)(0x400E3060) &= ~(0x1UL << 28);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get low frequency RC oscillator clock frequency for target system.
|
||||
*
|
||||
|
|
@ -303,7 +325,7 @@ void SystemInit(void)
|
|||
*
|
||||
* @return
|
||||
* LFRCO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
uint32_t SystemLFRCOClockGet(void)
|
||||
{
|
||||
/* Currently we assume that this frequency is properly tuned during */
|
||||
|
|
@ -312,8 +334,7 @@ uint32_t SystemLFRCOClockGet(void)
|
|||
return EFM32_LFRCO_FREQ;
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get ultra low frequency RC oscillator clock frequency for target system.
|
||||
*
|
||||
|
|
@ -322,15 +343,14 @@ uint32_t SystemLFRCOClockGet(void)
|
|||
*
|
||||
* @return
|
||||
* ULFRCO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
uint32_t SystemULFRCOClockGet(void)
|
||||
{
|
||||
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
|
||||
return EFM32_ULFRCO_FREQ;
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get low frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
|
|
@ -339,19 +359,18 @@ uint32_t SystemULFRCOClockGet(void)
|
|||
*
|
||||
* @return
|
||||
* LFXO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
uint32_t SystemLFXOClockGet(void)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_LFXO_FREQ > 0)
|
||||
#if (EFM32_LFXO_FREQ > 0U)
|
||||
return SystemLFXOClock;
|
||||
#else
|
||||
return 0;
|
||||
return 0U;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Set low frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
|
|
@ -365,18 +384,18 @@ uint32_t SystemLFXOClockGet(void)
|
|||
*
|
||||
* @param[in] freq
|
||||
* LFXO frequency in Hz used for target.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
void SystemLFXOClockSet(uint32_t freq)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_LFXO_FREQ > 0)
|
||||
#if (EFM32_LFXO_FREQ > 0U)
|
||||
SystemLFXOClock = freq;
|
||||
|
||||
/* Update core clock frequency if LFXO is used to clock core */
|
||||
if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO)
|
||||
{
|
||||
if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
|
||||
== CMU_HFCLKSTATUS_SELECTED_LFXO) {
|
||||
/* The function will update the global variable */
|
||||
SystemCoreClockGet();
|
||||
(void)SystemCoreClockGet();
|
||||
}
|
||||
#else
|
||||
(void)freq; /* Unused parameter */
|
||||
|
|
|
|||
|
|
@ -1,34 +1,32 @@
|
|||
/***************************************************************************//**
|
||||
* @file system_efm32pg1b.h
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
|
||||
* @version 5.1.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.@n
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.@n
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
|
||||
* has no obligation to support this Software. Silicon Laboratories, Inc. is
|
||||
* providing the Software "AS IS", with no express or implied warranties of any
|
||||
* kind, including, but not limited to, any implied warranties of
|
||||
* merchantability or fitness for any particular purpose or warranties against
|
||||
* infringement of any proprietary rights of a third party.
|
||||
*
|
||||
* Silicon Laboratories, Inc. will not be liable for any consequential,
|
||||
* incidental, or special damages, or any other relief, or for any claim by
|
||||
* any third party, arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef SYSTEM_EFM32_H
|
||||
#define SYSTEM_EFM32_H
|
||||
|
|
@ -39,6 +37,25 @@ extern "C" {
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32 EFM32
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
****************************** TYPEDEFS ***********************************
|
||||
******************************************************************************/
|
||||
|
||||
/* Interrupt vectortable entry */
|
||||
typedef union {
|
||||
void (*pFunc)(void);
|
||||
void *topOfStack;
|
||||
} tVectorEntry;
|
||||
|
||||
/*******************************************************************************
|
||||
************************** GLOBAL VARIABLES *******************************
|
||||
******************************************************************************/
|
||||
|
|
@ -46,51 +63,59 @@ extern "C" {
|
|||
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
|
||||
|
||||
#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
|
||||
#define __Vectors __vector_table
|
||||
#endif
|
||||
extern const tVectorEntry __Vectors[];
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
***************************** PROTOTYPES **********************************
|
||||
******************************************************************************/
|
||||
|
||||
void Reset_Handler(void);
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
void Reset_Handler(void); /**< Reset Handler */
|
||||
void NMI_Handler(void); /**< NMI Handler */
|
||||
void HardFault_Handler(void); /**< Hard Fault Handler */
|
||||
void MemManage_Handler(void); /**< MPU Fault Handler */
|
||||
void BusFault_Handler(void); /**< Bus Fault Handler */
|
||||
void UsageFault_Handler(void); /**< Usage Fault Handler */
|
||||
void SVC_Handler(void); /**< SVCall Handler */
|
||||
void DebugMon_Handler(void); /**< Debug Monitor Handler */
|
||||
void PendSV_Handler(void); /**< PendSV Handler */
|
||||
void SysTick_Handler(void); /**< SysTick Handler */
|
||||
|
||||
void EMU_IRQHandler(void);
|
||||
void WDOG0_IRQHandler(void);
|
||||
void LDMA_IRQHandler(void);
|
||||
void GPIO_EVEN_IRQHandler(void);
|
||||
void TIMER0_IRQHandler(void);
|
||||
void USART0_RX_IRQHandler(void);
|
||||
void USART0_TX_IRQHandler(void);
|
||||
void ACMP0_IRQHandler(void);
|
||||
void ADC0_IRQHandler(void);
|
||||
void IDAC0_IRQHandler(void);
|
||||
void I2C0_IRQHandler(void);
|
||||
void GPIO_ODD_IRQHandler(void);
|
||||
void TIMER1_IRQHandler(void);
|
||||
void USART1_RX_IRQHandler(void);
|
||||
void USART1_TX_IRQHandler(void);
|
||||
void LEUART0_IRQHandler(void);
|
||||
void PCNT0_IRQHandler(void);
|
||||
void CMU_IRQHandler(void);
|
||||
void MSC_IRQHandler(void);
|
||||
void LETIMER0_IRQHandler(void);
|
||||
void RTCC_IRQHandler(void);
|
||||
void CRYOTIMER_IRQHandler(void);
|
||||
void EMU_IRQHandler(void); /**< EMU IRQ Handler */
|
||||
void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
|
||||
void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
|
||||
void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
|
||||
void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
|
||||
void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
|
||||
void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
|
||||
void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
|
||||
void ADC0_IRQHandler(void); /**< ADC0 IRQ Handler */
|
||||
void IDAC0_IRQHandler(void); /**< IDAC0 IRQ Handler */
|
||||
void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
|
||||
void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
|
||||
void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
|
||||
void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */
|
||||
void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */
|
||||
void LEUART0_IRQHandler(void); /**< LEUART0 IRQ Handler */
|
||||
void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */
|
||||
void CMU_IRQHandler(void); /**< CMU IRQ Handler */
|
||||
void MSC_IRQHandler(void); /**< MSC IRQ Handler */
|
||||
void CRYPTO_IRQHandler(void); /**< CRYPTO IRQ Handler */
|
||||
void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
|
||||
void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */
|
||||
void CRYOTIMER_IRQHandler(void); /**< CRYOTIMER IRQ Handler */
|
||||
|
||||
#if (__FPU_PRESENT == 1)
|
||||
void FPUEH_IRQHandler(void);
|
||||
void FPUEH_IRQHandler(void); /**< FPUEH IRQ Handler */
|
||||
#endif
|
||||
|
||||
uint32_t SystemCoreClockGet(void);
|
||||
|
||||
/**************************************************************************//**
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Update CMSIS SystemCoreClock variable.
|
||||
*
|
||||
|
|
@ -103,10 +128,10 @@ uint32_t SystemCoreClockGet(void);
|
|||
* API, this variable will be kept updated. This function is only provided
|
||||
* for CMSIS compliance and if a user modifies the the core clock outside
|
||||
* the CMU API.
|
||||
*****************************************************************************/
|
||||
******************************************************************************/
|
||||
static __INLINE void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClockGet();
|
||||
(void)SystemCoreClockGet();
|
||||
}
|
||||
|
||||
uint32_t SystemMaxCoreClockGet(void);
|
||||
|
|
@ -123,6 +148,9 @@ uint32_t SystemULFRCOClockGet(void);
|
|||
uint32_t SystemLFXOClockGet(void);
|
||||
void SystemLFXOClockSet(uint32_t freq);
|
||||
|
||||
/** @} End of group */
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue