From 4a0718c6972a909d430f4964bfe2e73f8ffcda85 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Thu, 26 Nov 2020 13:02:08 +0000 Subject: [PATCH] MAX32620HSP: Remove source files This target was not supported by Mbed OS 6 --- .../TARGET_MAX32620/PeripheralPins.c | 186 ---- .../TARGET_MAX32620/PeripheralPins.h | 63 -- .../TARGET_Maxim/TARGET_MAX32620/PortNames.h | 54 -- .../TARGET_MAX32620HSP/PeripheralNames.h | 90 -- .../TARGET_MAX32620HSP/PinNames.h | 214 ----- .../TARGET_MAX32620HSP/low_level_init.c | 51 - .../TOOLCHAIN_ARM_STD/libexactLE.ar | Bin 781356 -> 0 bytes .../TOOLCHAIN_GCC_ARM/libexactLE.a | Bin 257674 -> 0 bytes .../TOOLCHAIN_IAR/libexactLE.a | Bin 784070 -> 0 bytes .../TARGET_MAX32620/analogin_api.c | 151 --- targets/TARGET_Maxim/TARGET_MAX32620/device.h | 40 - .../device/TOOLCHAIN_ARM_STD/MAX32620.sct | 34 - .../TOOLCHAIN_ARM_STD/startup_MAX32620.S | 281 ------ .../device/TOOLCHAIN_GCC_ARM/max32620.ld | 183 ---- .../TOOLCHAIN_GCC_ARM/startup_max32620.S | 269 ------ .../device/TOOLCHAIN_IAR/MAX32620.icf | 33 - .../device/TOOLCHAIN_IAR/startup_MAX32620.S | 421 -------- .../TARGET_MAX32620/device/adc_regs.h | 252 ----- .../TARGET_MAX32620/device/aes_regs.h | 163 ---- .../TARGET_MAX32620/device/clkman_regs.h | 426 --------- .../TARGET_MAX32620/device/cmsis.h | 40 - .../TARGET_MAX32620/device/cmsis_nvic.h | 42 - .../TARGET_MAX32620/device/crc_regs.h | 106 -- .../TARGET_MAX32620/device/device_nvic.c | 25 - .../TARGET_MAX32620/device/flc_regs.h | 224 ----- .../TARGET_MAX32620/device/gpio_regs.h | 638 ------------ .../TARGET_MAX32620/device/i2cm_regs.h | 205 ---- .../TARGET_MAX32620/device/i2cs_regs.h | 242 ----- .../TARGET_MAX32620/device/icc_regs.h | 112 --- .../TARGET_MAX32620/device/ioman_regs.h | 904 ------------------ .../TARGET_MAX32620/device/maa_regs.h | 161 ---- .../TARGET_MAX32620/device/max32620.h | 766 --------------- .../TARGET_MAX32620/device/owm_regs.h | 153 --- .../TARGET_MAX32620/device/pmu_regs.h | 148 --- .../TARGET_MAX32620/device/pt_regs.h | 314 ------ .../TARGET_MAX32620/device/pwrman_regs.h | 371 ------- .../TARGET_MAX32620/device/pwrseq_regs.h | 322 ------- .../TARGET_MAX32620/device/rtc_regs.h | 241 ----- .../TARGET_MAX32620/device/spi_regs.h | 243 ----- .../TARGET_MAX32620/device/spib_regs.h | 238 ----- .../TARGET_MAX32620/device/spix_regs.h | 201 ---- .../TARGET_MAX32620/device/system_max32620.c | 212 ---- .../TARGET_MAX32620/device/system_max32620.h | 78 -- .../TARGET_MAX32620/device/tmr_regs.h | 203 ---- .../TARGET_MAX32620/device/tpu_regs.h | 98 -- .../TARGET_MAX32620/device/trim_regs.h | 106 -- .../TARGET_MAX32620/device/uart_regs.h | 226 ----- .../TARGET_MAX32620/device/usb_regs.h | 296 ------ .../TARGET_MAX32620/device/wdt_regs.h | 238 ----- .../TARGET_Maxim/TARGET_MAX32620/gpio_api.c | 100 -- .../TARGET_MAX32620/gpio_irq_api.c | 286 ------ .../TARGET_MAX32620/gpio_object.h | 72 -- .../TARGET_Maxim/TARGET_MAX32620/i2c_api.c | 457 --------- .../TARGET_Maxim/TARGET_MAX32620/objects.h | 125 --- targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c | 117 --- .../TARGET_Maxim/TARGET_MAX32620/port_api.c | 95 -- .../TARGET_Maxim/TARGET_MAX32620/pwmout_api.c | 228 ----- .../TARGET_Maxim/TARGET_MAX32620/rtc_api.c | 313 ------ .../TARGET_Maxim/TARGET_MAX32620/serial_api.c | 511 ---------- targets/TARGET_Maxim/TARGET_MAX32620/sleep.c | 219 ----- .../TARGET_Maxim/TARGET_MAX32620/spi_api.c | 615 ------------ .../TARGET_MAX32620/spi_multi_api.h | 67 -- .../TARGET_Maxim/TARGET_MAX32620/us_ticker.c | 306 ------ 63 files changed, 13575 deletions(-) delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PeripheralNames.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/low_level_init.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/libexactLE.ar delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_GCC_ARM/libexactLE.a delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_IAR/libexactLE.a delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/analogin_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/max32620.ld delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/adc_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/aes_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/clkman_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/crc_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/device_nvic.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/flc_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/gpio_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/i2cm_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/i2cs_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/icc_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/maa_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/max32620.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/owm_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/pt_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/pwrman_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/pwrseq_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/rtc_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/spi_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/spib_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/spix_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/tmr_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/tpu_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/trim_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/uart_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/usb_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/device/wdt_regs.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/objects.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/port_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/sleep.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/spi_multi_api.h delete mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c b/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c deleted file mode 100644 index 4e312ea780..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c +++ /dev/null @@ -1,186 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "device.h" -#include "PeripheralPins.h" -#include "ioman_regs.h" - -/* - * To select a peripheral function on Maxim microcontrollers, multiple - * configurations must be made. The mbed PinMap structure only includes one - * data member to hold this information. To extend the configuration storage, - * the "function" data member is used as a pointer to a pin_function_t - * structure. This structure is defined in objects.h. The definitions below - * include the creation of the pin_function_t structures and the assignment of - * the pointers to the "function" data members. - */ - -#ifdef TOOLCHAIN_ARM_STD -#pragma diag_suppress 1296 -#endif - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, - { P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, - { P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_I2C_SCL[] = { - { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, - { P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, - { P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK}) }, - { NC, NC, 0 } -}; - -/************UART***************/ -/* -*/ -const PinMap PinMap_UART_TX[] = { - { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_UART_RX[] = { - { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_UART_CTS[] = { - { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_CTS_MAP | MXC_F_IOMAN_UART_ACK_CTS_IO_ACK)}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_UART_RTS[] = { - { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART_ACK_RTS_MAP | MXC_F_IOMAN_UART_ACK_RTS_IO_ACK)}) }, - { NC, NC, 0 } -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, - { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, - { P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, - { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_SPI_MOSI[] = { - { P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, - { P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, - { P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, - { P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_SPI_MISO[] = { - { P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, - { P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK}) }, - { P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, - { P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK)}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_SPI_SSEL[] = { - { P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK}) }, - { P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK}) }, - { P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK)}) }, - { P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ | MXC_F_IOMAN_SPIM_REQ_SR0_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK | MXC_F_IOMAN_SPIM_ACK_SR0_IO_ACK)}) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_SPI_QUAD[] = { - { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ, MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK}) }, - { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ, MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK}) }, - { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ | MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ), (MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK | MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK)}) }, - { NC, NC, 0 } -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, {P6_0, PWM_0, 1}, - { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, - { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, - { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, - { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, - { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, - { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, - { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, - { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, - { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, - { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, - { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, - { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, - { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, - { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, - { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, - { NC, NC, 0 } -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - { AIN_0, ADC, 0 }, - { AIN_1, ADC, 0 }, - { AIN_2, ADC, 0 }, - { AIN_3, ADC, 0 }, - { NC, NC, 0 } -}; diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.h b/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.h deleted file mode 100644 index b0be1060db..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.h +++ /dev/null @@ -1,63 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************I2C***************/ -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -/************UART***************/ -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_CTS[]; -extern const PinMap PinMap_UART_RTS[]; - -/************SPI***************/ -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; -extern const PinMap PinMap_SPI_QUAD[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h b/targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h deleted file mode 100644 index e44f78c4c3..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h +++ /dev/null @@ -1,54 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1, - Port2 = 2, - Port3 = 3, - Port4 = 4, - Port5 = 5, - Port6 = 6, -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PeripheralNames.h b/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PeripheralNames.h deleted file mode 100644 index 8e65efe61c..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PeripheralNames.h +++ /dev/null @@ -1,90 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = MXC_BASE_UART0, - UART_1 = MXC_BASE_UART1, - UART_2 = MXC_BASE_UART2, - UART_3 = MXC_BASE_UART3, - STDIO_UART = UART_0 -} UARTName; - -typedef enum { - I2C_0 = MXC_BASE_I2CM0, - I2C_1 = MXC_BASE_I2CM1, - I2C_2 = MXC_BASE_I2CM2 -} I2CName; - -typedef enum { - SPI_0 = MXC_BASE_SPI0, - SPI_1 = MXC_BASE_SPI1, - SPI_2 = MXC_BASE_SPI2 -} SPIName; - -typedef enum { - PWM_0 = MXC_BASE_PT0, - PWM_1 = MXC_BASE_PT1, - PWM_2 = MXC_BASE_PT2, - PWM_3 = MXC_BASE_PT3, - PWM_4 = MXC_BASE_PT4, - PWM_5 = MXC_BASE_PT5, - PWM_6 = MXC_BASE_PT6, - PWM_7 = MXC_BASE_PT7, - PWM_8 = MXC_BASE_PT8, - PWM_9 = MXC_BASE_PT9, - PWM_10 = MXC_BASE_PT10, - PWM_11 = MXC_BASE_PT11, - PWM_12 = MXC_BASE_PT12, - PWM_13 = MXC_BASE_PT13, - PWM_14 = MXC_BASE_PT14, - PWM_15 = MXC_BASE_PT15 -} PWMName; - -typedef enum { - ADC = MXC_BASE_ADC -} ADCName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h deleted file mode 100644 index c6030ef13d..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h +++ /dev/null @@ -1,214 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "gpio_regs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, - PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL -} PinDirection; - -#define PORT_SHIFT 12 -#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) -#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) - -#define NOT_CONNECTED (int)0xFFFFFFFF - -typedef enum { - P0_0 = (0 << PORT_SHIFT) | 0, - P0_1 = (0 << PORT_SHIFT) | 1, - P0_2 = (0 << PORT_SHIFT) | 2, - P0_3 = (0 << PORT_SHIFT) | 3, - P0_4 = (0 << PORT_SHIFT) | 4, - P0_5 = (0 << PORT_SHIFT) | 5, - P0_6 = (0 << PORT_SHIFT) | 6, - P0_7 = (0 << PORT_SHIFT) | 7, - - P1_0 = (1 << PORT_SHIFT) | 0, - P1_1 = (1 << PORT_SHIFT) | 1, - P1_2 = (1 << PORT_SHIFT) | 2, - P1_3 = (1 << PORT_SHIFT) | 3, - P1_4 = (1 << PORT_SHIFT) | 4, - P1_5 = (1 << PORT_SHIFT) | 5, - P1_6 = (1 << PORT_SHIFT) | 6, - P1_7 = (1 << PORT_SHIFT) | 7, - - P2_0 = (2 << PORT_SHIFT) | 0, - P2_1 = (2 << PORT_SHIFT) | 1, - P2_2 = (2 << PORT_SHIFT) | 2, - P2_3 = (2 << PORT_SHIFT) | 3, - P2_4 = (2 << PORT_SHIFT) | 4, - P2_5 = (2 << PORT_SHIFT) | 5, - P2_6 = (2 << PORT_SHIFT) | 6, - P2_7 = (2 << PORT_SHIFT) | 7, - - P3_0 = (3 << PORT_SHIFT) | 0, - P3_1 = (3 << PORT_SHIFT) | 1, - P3_2 = (3 << PORT_SHIFT) | 2, - P3_3 = (3 << PORT_SHIFT) | 3, - P3_4 = (3 << PORT_SHIFT) | 4, - P3_5 = (3 << PORT_SHIFT) | 5, - P3_6 = (3 << PORT_SHIFT) | 6, - P3_7 = (3 << PORT_SHIFT) | 7, - - P4_0 = (4 << PORT_SHIFT) | 0, - P4_1 = (4 << PORT_SHIFT) | 1, - P4_2 = (4 << PORT_SHIFT) | 2, - P4_3 = (4 << PORT_SHIFT) | 3, - P4_4 = (4 << PORT_SHIFT) | 4, - P4_5 = (4 << PORT_SHIFT) | 5, - P4_6 = (4 << PORT_SHIFT) | 6, - P4_7 = (4 << PORT_SHIFT) | 7, - - P5_0 = (5 << PORT_SHIFT) | 0, - P5_1 = (5 << PORT_SHIFT) | 1, - P5_2 = (5 << PORT_SHIFT) | 2, - P5_3 = (5 << PORT_SHIFT) | 3, - P5_4 = (5 << PORT_SHIFT) | 4, - P5_5 = (5 << PORT_SHIFT) | 5, - P5_6 = (5 << PORT_SHIFT) | 6, - P5_7 = (5 << PORT_SHIFT) | 7, - - P6_0 = (6 << PORT_SHIFT) | 0, - - // Analog input pins - AIN_0 = (0xA << PORT_SHIFT) | 0, - AIN_1 = (0xA << PORT_SHIFT) | 1, - AIN_2 = (0xA << PORT_SHIFT) | 2, - AIN_3 = (0xA << PORT_SHIFT) | 3, - - // LEDs - LED_RED = P2_0, - LED1 = LED_RED, - LED2 = NOT_CONNECTED, - LED3 = NOT_CONNECTED, - LED4 = NOT_CONNECTED, - - // Push button - SW1 = P2_1, - SW2 = NOT_CONNECTED, - SW3 = NOT_CONNECTED, - // Standardized button names - BUTTON1 = SW1, - - // USB bridge connected UART pins - USBTX = P0_1, - USBRX = P0_0, - STDIO_UART_TX = USBTX, - STDIO_UART_RX = USBRX, - - // I2C pins - I2C0_SCL = NOT_CONNECTED, - I2C0_SDA = NOT_CONNECTED, - - I2C1_SCL = P3_5, - I2C1_SDA = P3_4, - - I2C2_SCL = P6_0, - I2C2_SDA = P5_7, - - // UART pins - UART0_RX = P0_0, - UART0_TX = P0_1, - UART0_CTS = NOT_CONNECTED, - UART0_RTS = NOT_CONNECTED, - - UART1_RX = P2_0, - UART1_TX = P2_1, - UART1_CTS = NOT_CONNECTED, - UART1_RTS = NOT_CONNECTED, - - UART2_RX = NOT_CONNECTED, - UART2_TX = NOT_CONNECTED, - UART2_CTS = NOT_CONNECTED, - UART2_RTS = NOT_CONNECTED, - - UART3_RX = NOT_CONNECTED, - UART3_TX = NOT_CONNECTED, - UART3_CTS = NOT_CONNECTED, - UART3_RTS = NOT_CONNECTED, - - // SPI pins - SPI0_SCK = P0_4, - SPI0_MOSI = P0_5, - SPI0_MISO = P0_6, - SPI0_SS = P0_7, - - SPI1_SCK = P1_0, - SPI1_MOSI = P1_1, - SPI1_MISO = P1_2, - SPI1_SS = P1_3, - - SPI2_SCK = NOT_CONNECTED, - SPI2_MOSI = NOT_CONNECTED, - SPI2_MISO = NOT_CONNECTED, - SPI2_SS = NOT_CONNECTED, - - // BTLE Radio HCI - HCI_SCK = P5_0, - HCI_MOSI = P5_1, - HCI_MISO = P5_2, - HCI_CSN = P5_3, - HCI_IRQ = P5_6, - HCI_RST = P4_2, - - // Not connected - NC = NOT_CONNECTED -} PinName; - -typedef enum { - PullUp, - PullDown, - OpenDrain, - PullNone, - PullDefault = PullUp -} PinMode; - -typedef enum { - LED_ON = 0, - LED_OFF = 1 -} LedStates; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/low_level_init.c b/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/low_level_init.c deleted file mode 100644 index 24ad45eb1c..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/low_level_init.c +++ /dev/null @@ -1,51 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "cmsis.h" -#include "pwrman_regs.h" - -//****************************************************************************** -// This function will get called early in system initialization -void low_level_init(void) -{ - /* HSP platform does not have an external HW reset. During development, - * debug triggered resets do not reset the entire system properly. This - * work-around ensures a proper system reset. - */ - if (*((volatile uint32_t*)MXC_SYS_MEM_BASE) != 0xDEADBEEF) { - *((volatile uint32_t*)MXC_SYS_MEM_BASE) = 0xDEADBEEF; - MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET; - } else { - *((volatile uint32_t*)MXC_SYS_MEM_BASE) = 0; - } -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/libexactLE.ar b/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/libexactLE.ar deleted file mode 100644 index ee465787e02a471433054278bcdc7797bfefb2b9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 781356 zcmeFa3w&I~eJ?(HR*&^swq@CX0b|zkVr0P9!?Gd z?n;&%3bHX^9!a3(pOTigPRqTeNtzlGdLb9CO`5bMpR~1;++5mn8?{Xv8YiutSJhr_ z_#gO{ zO}O-X88bf4*ydZ`+1204*u}b@{tjbbxTmn|$Ez8;2$!qwF;>uJ?qRN6*XMhfE7x_p zk-2hRKlL%!JeRTh^DO7p@?&P?yFOIG4E_4pi_G{1yWAyjGPm#Z;<{~uxeK}ONiz5O zT+j70_n&`r?(3~4=AP#&S^ph&-q#1aSc$ssTg6Jw=lU%8#p^#`8JvBCm1tM#ikBI` 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z{rC&lbpJgG-a>)*hR%}j;%bVIHdq;71D%EUAb6C*O5O{)%P=pUzF+E%6d!HbTWe-g5c=pu3fzFxI>Sz8~WAK}y~n@0pD@dN@2n??AU3cZ7duEc@>#x(%AI o>%Z~!#PND;@tuO<$QbX_u|B%}Xafe4H;3+vV~)2TM2adc = MXC_ADC; - obj->adc_pin = pin; - - if (initialized == 0) { - // Enable AFE power - MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; - - // Enable the clock - MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE; - - // Enable clock gate - MXC_CLKMAN->clk_gate_ctrl2 |= MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER; - - // Enable interface clock - obj->adc->ctrl |= MXC_F_ADC_CTRL_ADC_CLK_EN; - - if ((MXC_TRIM->reg11_adc_trim0 == 0xFFFFFFFF) && (MXC_TRIM->reg12_adc_trim1 == 0xFFFFFFFF)) { - // Set default trim for untrimmed parts. - MXC_TRIM->reg11_adc_trim0 = 0x02000200; - MXC_TRIM->reg12_adc_trim1 = 0x02000200; - } - - // Clear ADC ready interrupt (wite 1 to clr) - obj->adc->intr = (obj->adc->intr & 0xFFFF) | MXC_F_ADC_INTR_ADC_REF_READY_IF; - - // Using internal reference of 1.20V - - // Enable ADC power bypass the buffer - obj->adc->ctrl |= (MXC_F_ADC_CTRL_ADC_PU | MXC_F_ADC_CTRL_ADC_REFBUF_PU | - MXC_F_ADC_CTRL_ADC_CHGPUMP_PU | MXC_F_ADC_CTRL_BUF_BYPASS); - - // Wait for ADC ready - while (!(obj->adc->intr & MXC_F_ADC_INTR_ADC_REF_READY_IF)); - - initialized = 1; - } -} - -//****************************************************************************** -float analogin_read(analogin_t *obj) -{ - // Convert integer to float - return (((float)analogin_read_u16(obj)/(float)ADC_FULL_SCALE)); -} - -//****************************************************************************** -uint16_t analogin_read_u16(analogin_t *obj) -{ - // Set the pin to take readings from - uint32_t adc_input = PINNAME_TO_PIN(obj->adc_pin); - - // Select the channel - obj->adc->ctrl &= ~MXC_F_ADC_CTRL_ADC_CHSEL; - obj->adc->ctrl |= (adc_input << MXC_F_ADC_CTRL_ADC_CHSEL_POS) & MXC_F_ADC_CTRL_ADC_CHSEL; - - // We want unity gain, to get full 0-Vref range - // So, both ref and adc input scale should be enabled - obj->adc->ctrl |= MXC_F_ADC_CTRL_ADC_SCALE | MXC_F_ADC_CTRL_ADC_REFSCL; - - // Not using internal buffer, disable anyway - obj->adc->ctrl &= ~MXC_F_ADC_CTRL_BUF_PU; - obj->adc->ctrl |= MXC_F_ADC_CTRL_BUF_BYPASS; - - // Normal LSB justified data alignment - - // Not using limits - - // Clear ADC done flag (wite 1 to clr) - obj->adc->intr = (obj->adc->intr & 0xFFFF) | MXC_F_ADC_INTR_ADC_DONE_IF; - - // Start the conversion - obj->adc->ctrl |= MXC_F_ADC_CTRL_CPU_ADC_START; - - // Wait for ADC done - while (!(obj->adc->intr & MXC_F_ADC_INTR_ADC_DONE_IF)); - - // Get sample from the fifo - uint16_t sample = obj->adc->data; - - // Check for overflow, hardware will report overflow as 0 - if (obj->adc->status & MXC_F_ADC_STATUS_ADC_OVERFLOW) { - sample = (uint16_t)ADC_FULL_SCALE; - } - - return sample; -} - -//****************************************************************************** -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device.h b/targets/TARGET_Maxim/TARGET_MAX32620/device.h deleted file mode 100644 index aff4765924..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H -#include "objects.h" - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct deleted file mode 100644 index 20e9ae5796..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct +++ /dev/null @@ -1,34 +0,0 @@ -#! armcc -E -; MAX32620 -; 2MB FLASH (0x200000) @ 0x000000000 -; 256KB RAM (0x40000) @ 0x20000000 - - - -; MAX32620: 2MB FLASH (0x200000) + 256KB RAM (0x40000) - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x800 -# endif -#endif - -#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x200000 { ; load region size_region - ER_IROM1 0x00000000 0x200000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; [RAM] Vector table dynamic copy: 65 vectors * 4 bytes = 260 (0x104) + 4 - ; for 8 byte alignment - RW_IRAM1 (0x20000000+0x108) (0x40000-0x108-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x20000000+0x40000) EMPTY -Stack_Size { ; stack - } -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S deleted file mode 100644 index befbe80ef5..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S +++ /dev/null @@ -1,281 +0,0 @@ -;******************************************************************************* -; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. -; -; Permission is hereby granted, free of charge, to any person obtaining a -; copy of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice shall be included -; in all copies or substantial portions of the Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES -; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -; OTHER DEALINGS IN THE SOFTWARE. -; -; Except as contained in this notice, the name of Maxim Integrated -; Products, Inc. shall not be used except as stated in the Maxim Integrated -; Products, Inc. Branding Policy. -; -; The mere transfer of this software does not imply any licenses -; of trade secrets, proprietary technology, copyrights, patents, -; trademarks, maskwork rights, or any other form of intellectual -; property whatsoever. Maxim Integrated Products, Inc. retains all -; ownership rights. -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Maxim 32620 Externals interrupts - DCD CLKMAN_IRQHandler ; 16:01 CLKMAN - DCD PWRMAN_IRQHandler ; 17:02 PWRMAN - DCD FLC_IRQHandler ; 18:03 Flash Controller - DCD RTC0_IRQHandler ; 19:04 RTC INT0 - DCD RTC1_IRQHandler ; 20:05 RTC INT1 - DCD RTC2_IRQHandler ; 21:06 RTC INT2 - DCD RTC3_IRQHandler ; 22:07 RTC INT3 - DCD PMU_IRQHandler ; 23:08 PMU - DCD USB_IRQHandler ; 24:09 USB - DCD AES_IRQHandler ; 25:10 AES - DCD MAA_IRQHandler ; 26:11 MAA - DCD WDT0_IRQHandler ; 27:12 WATCHDOG0 - DCD WDT0_P_IRQHandler ; 28:13 WATCHDOG0 PRE-WINDOW - DCD WDT1_IRQHandler ; 29:14 WATCHDOG1 - DCD WDT1_P_IRQHandler ; 30:15 WATCHDOG1 PRE-WINDOW - DCD GPIO_P0_IRQHandler ; 31:16 GPIO Port 0 - DCD GPIO_P1_IRQHandler ; 32:17 GPIO Port 1 - DCD GPIO_P2_IRQHandler ; 33:18 GPIO Port 2 - DCD GPIO_P3_IRQHandler ; 34:19 GPIO Port 3 - DCD GPIO_P4_IRQHandler ; 35:20 GPIO Port 4 - DCD GPIO_P5_IRQHandler ; 36:21 GPIO Port 5 - DCD GPIO_P6_IRQHandler ; 37:22 GPIO Port 6 - DCD TMR0_IRQHandler ; 38:23 Timer32-0 - DCD TMR16_0_IRQHandler ; 39:24 Timer16-s0 - DCD TMR1_IRQHandler ; 40:25 Timer32-1 - DCD TMR16_1_IRQHandler ; 41:26 Timer16-s1 - DCD TMR2_IRQHandler ; 42:27 Timer32-2 - DCD TMR16_2_IRQHandler ; 43:28 Timer16-s2 - DCD TMR3_IRQHandler ; 44:29 Timer32-3 - DCD TMR16_3_IRQHandler ; 45:30 Timer16-s3 - DCD TMR4_IRQHandler ; 46:31 Timer32-4 - DCD TMR16_4_IRQHandler ; 47:32 Timer16-s4 - DCD TMR5_IRQHandler ; 48:33 Timer32-5 - DCD TMR16_5_IRQHandler ; 49:34 Timer16-s5 - DCD UART0_IRQHandler ; 50:35 UART0 - DCD UART1_IRQHandler ; 51:36 UART1 - DCD UART2_IRQHandler ; 52:37 UART0 - DCD UART3_IRQHandler ; 53:38 UART1 - DCD PT_IRQHandler ; 54:39 PT - DCD I2CM0_IRQHandler ; 55:40 I2C Master 0 - DCD I2CM1_IRQHandler ; 56:41 I2C Master 1 - DCD I2CM2_IRQHandler ; 57:42 I2C Master 2 - DCD I2CS_IRQHandler ; 58:43 I2C Slave - DCD SPI0_IRQHandler ; 59:44 SPI0 - DCD SPI1_IRQHandler ; 60:45 SPI1 - DCD SPI2_IRQHandler ; 61:46 SPI2 - DCD SPIB_IRQHandler ; 62:47 SPI Bridge - DCD OWM_IRQHandler ; 63:48 1-Wire Master - DCD AFE_IRQHandler ; 64:49 AFE - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B NMI_Handler - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B HardFault_Handler - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B MemManage_Handler - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B BusFault_Handler - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B UsageFault_Handler - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B SVC_Handler - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B DebugMon_Handler - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B PendSV_Handler - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B SysTick_Handler - ENDP - -Default_Handler PROC - - EXPORT CLKMAN_IRQHandler [WEAK] - EXPORT PWRMAN_IRQHandler [WEAK] - EXPORT FLC_IRQHandler [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT RTC1_IRQHandler [WEAK] - EXPORT RTC2_IRQHandler [WEAK] - EXPORT RTC3_IRQHandler [WEAK] - EXPORT PMU_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] - EXPORT MAA_IRQHandler [WEAK] - EXPORT WDT0_IRQHandler [WEAK] - EXPORT WDT0_P_IRQHandler [WEAK] - EXPORT WDT1_IRQHandler [WEAK] - EXPORT WDT1_P_IRQHandler [WEAK] - EXPORT GPIO_P0_IRQHandler [WEAK] - EXPORT GPIO_P1_IRQHandler [WEAK] - EXPORT GPIO_P2_IRQHandler [WEAK] - EXPORT GPIO_P3_IRQHandler [WEAK] - EXPORT GPIO_P4_IRQHandler [WEAK] - EXPORT GPIO_P5_IRQHandler [WEAK] - EXPORT GPIO_P6_IRQHandler [WEAK] - EXPORT TMR0_IRQHandler [WEAK] - EXPORT TMR16_0_IRQHandler [WEAK] - EXPORT TMR1_IRQHandler [WEAK] - EXPORT TMR16_1_IRQHandler [WEAK] - EXPORT TMR2_IRQHandler [WEAK] - EXPORT TMR16_2_IRQHandler [WEAK] - EXPORT TMR3_IRQHandler [WEAK] - EXPORT TMR16_3_IRQHandler [WEAK] - EXPORT TMR4_IRQHandler [WEAK] - EXPORT TMR16_4_IRQHandler [WEAK] - EXPORT TMR5_IRQHandler [WEAK] - EXPORT TMR16_5_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PT_IRQHandler [WEAK] - EXPORT I2CM0_IRQHandler [WEAK] - EXPORT I2CM1_IRQHandler [WEAK] - EXPORT I2CM2_IRQHandler [WEAK] - EXPORT I2CS_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT SPIB_IRQHandler [WEAK] - EXPORT OWM_IRQHandler [WEAK] - EXPORT AFE_IRQHandler [WEAK] - -CLKMAN_IRQHandler -PWRMAN_IRQHandler -FLC_IRQHandler -RTC0_IRQHandler -RTC1_IRQHandler -RTC2_IRQHandler -RTC3_IRQHandler -PMU_IRQHandler -USB_IRQHandler -AES_IRQHandler -MAA_IRQHandler -WDT0_IRQHandler -WDT0_P_IRQHandler -WDT1_IRQHandler -WDT1_P_IRQHandler -GPIO_P0_IRQHandler -GPIO_P1_IRQHandler -GPIO_P2_IRQHandler -GPIO_P3_IRQHandler -GPIO_P4_IRQHandler -GPIO_P5_IRQHandler -GPIO_P6_IRQHandler -TMR0_IRQHandler -TMR16_0_IRQHandler -TMR1_IRQHandler -TMR16_1_IRQHandler -TMR2_IRQHandler -TMR16_2_IRQHandler -TMR3_IRQHandler -TMR16_3_IRQHandler -TMR4_IRQHandler -TMR16_4_IRQHandler -TMR5_IRQHandler -TMR16_5_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PT_IRQHandler -I2CM0_IRQHandler -I2CM1_IRQHandler -I2CM2_IRQHandler -I2CS_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -SPIB_IRQHandler -OWM_IRQHandler -AFE_IRQHandler - - B . - ENDP - ALIGN - END diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/max32620.ld b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/max32620.ld deleted file mode 100644 index d0488703b5..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/max32620.ld +++ /dev/null @@ -1,183 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2M - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S deleted file mode 100644 index d844878c8b..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S +++ /dev/null @@ -1,269 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - - .syntax unified - .arch armv7-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00004000 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* Externals interrupts */ - .long CLKMAN_IRQHandler /* 16:01 CLKMAN */ - .long PWRMAN_IRQHandler /* 17:02 PWRMAN */ - .long FLC_IRQHandler /* 18:03 Flash Controller */ - .long RTC0_IRQHandler /* 19:04 RTC INT0 */ - .long RTC1_IRQHandler /* 20:05 RTC INT1 */ - .long RTC2_IRQHandler /* 21:06 RTC INT2 */ - .long RTC3_IRQHandler /* 22:07 RTC INT3 */ - .long PMU_IRQHandler /* 23:08 PMU */ - .long USB_IRQHandler /* 24:09 USB */ - .long AES_IRQHandler /* 25:10 AES */ - .long MAA_IRQHandler /* 26:11 MAA */ - .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */ - .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ - .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */ - .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ - .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ - .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ - .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ - .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ - .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ - .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ - .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ - .long TMR0_IRQHandler /* 38:23 Timer32-0 */ - .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ - .long TMR1_IRQHandler /* 40:25 Timer32-1 */ - .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ - .long TMR2_IRQHandler /* 42:27 Timer32-2 */ - .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ - .long TMR3_IRQHandler /* 44:29 Timer32-3 */ - .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ - .long TMR4_IRQHandler /* 46:31 Timer32-4 */ - .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ - .long TMR5_IRQHandler /* 48:33 Timer32-5 */ - .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ - .long UART0_IRQHandler /* 50:35 UART0 */ - .long UART1_IRQHandler /* 51:36 UART1 */ - .long UART2_IRQHandler /* 52:37 UART0 */ - .long UART3_IRQHandler /* 53:38 UART1 */ - .long PT_IRQHandler /* 54:39 PT */ - .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */ - .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */ - .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */ - .long I2CS_IRQHandler /* 58:43 I2C Slave */ - .long SPI0_IRQHandler /* 59:44 SPI0 */ - .long SPI1_IRQHandler /* 60:45 SPI1 */ - .long SPI2_IRQHandler /* 61:46 SPI2 */ - .long SPIB_IRQHandler /* 62:47 SPI Bridge */ - .long OWM_IRQHandler /* 63:48 1-Wire Master */ - .long AFE_IRQHandler /* 64:49 AFE */ - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* In order to have the same boot sequence with all Toolchains, we must call - * SystemInit before initalizing the data segments, and calling the static - * initalization. */ - ldr r0, =SystemInit - blx r0 - -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.Lflash_to_ram_loop: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .Lflash_to_ram_loop - -.Lflash_to_ram_loop_end: - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */ - def_irq_default_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */ - def_irq_default_handler FLC_IRQHandler /* 18:03 Flash Controller */ - def_irq_default_handler RTC0_IRQHandler /* 19:04 RTC INT0 */ - def_irq_default_handler RTC1_IRQHandler /* 20:05 RTC INT1 */ - def_irq_default_handler RTC2_IRQHandler /* 21:06 RTC INT2 */ - def_irq_default_handler RTC3_IRQHandler /* 22:07 RTC INT3 */ - def_irq_default_handler PMU_IRQHandler /* 23:08 PMU */ - def_irq_default_handler USB_IRQHandler /* 24:09 USB */ - def_irq_default_handler AES_IRQHandler /* 25:10 AES */ - def_irq_default_handler MAA_IRQHandler /* 26:11 MAA */ - def_irq_default_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */ - def_irq_default_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ - def_irq_default_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */ - def_irq_default_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ - def_irq_default_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ - def_irq_default_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ - def_irq_default_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ - def_irq_default_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ - def_irq_default_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ - def_irq_default_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ - def_irq_default_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ - def_irq_default_handler TMR0_IRQHandler /* 38:23 Timer32-0 */ - def_irq_default_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ - def_irq_default_handler TMR1_IRQHandler /* 40:25 Timer32-1 */ - def_irq_default_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ - def_irq_default_handler TMR2_IRQHandler /* 42:27 Timer32-2 */ - def_irq_default_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ - def_irq_default_handler TMR3_IRQHandler /* 44:29 Timer32-3 */ - def_irq_default_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ - def_irq_default_handler TMR4_IRQHandler /* 46:31 Timer32-4 */ - def_irq_default_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ - def_irq_default_handler TMR5_IRQHandler /* 48:33 Timer32-5 */ - def_irq_default_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ - def_irq_default_handler PT_IRQHandler /* 50:35 PT */ - def_irq_default_handler UART0_IRQHandler /* 51:36 UART0 */ - def_irq_default_handler UART1_IRQHandler /* 52:37 UART1 */ - def_irq_default_handler UART2_IRQHandler /* 53:38 UART0 */ - def_irq_default_handler UART3_IRQHandler /* 54:39 UART1 */ - def_irq_default_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */ - def_irq_default_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */ - def_irq_default_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */ - def_irq_default_handler I2CS_IRQHandler /* 58:43 I2C Slave */ - def_irq_default_handler SPI0_IRQHandler /* 59:44 SPI0 */ - def_irq_default_handler SPI1_IRQHandler /* 60:45 SPI1 */ - def_irq_default_handler SPI2_IRQHandler /* 61:46 SPI2 */ - def_irq_default_handler SPIB_IRQHandler /* 62:47 SPI Bridge */ - def_irq_default_handler OWM_IRQHandler /* 63:48 SPI Bridge */ - def_irq_default_handler AFE_IRQHandler /* 64:49 AFE */ - - .end - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf deleted file mode 100644 index 3caee498c9..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf +++ /dev/null @@ -1,33 +0,0 @@ -/* [ROM] */ -define symbol __intvec_start__ = 0x0; -define symbol __region_ROM_start__ = 0x0; -define symbol __region_ROM_end__ = 0x001FFFFF; - -/* [RAM] Vector table dynamic copy: 65 vectors * 4 bytes = 260 (0x104) bytes + 4 for 8 byte align */ -define symbol __NVIC_start__ = 0x00000000; -define symbol __NVIC_end__ = 0x00000108; /* to be aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x20000000; -define symbol __region_RAM_end__ = 0x2003FFFF; - -/* Memory regions */ -define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; - -/* Stack and Heap */ -if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; -} - -define symbol __size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; -define symbol __size_heap__ = 0x4000; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S deleted file mode 100644 index 6e465e3be0..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S +++ /dev/null @@ -1,421 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) /* Top of Stack */ - DCD Reset_Handler /* Reset Handler */ - DCD NMI_Handler /* NMI Handler */ - DCD HardFault_Handler /* Hard Fault Handler */ - DCD MemManage_Handler /* MPU Fault Handler */ - DCD BusFault_Handler /* Bus Fault Handler */ - DCD UsageFault_Handler /* Usage Fault Handler */ - DCD 0 /* Reserved */ - DCD 0 /* Reserved */ - DCD 0 /* Reserved */ - DCD 0 /* Reserved */ - DCD SVC_Handler /* SVCall Handler */ - DCD DebugMon_Handler /* Debug Monitor Handler */ - DCD 0 /* Reserved */ - DCD PendSV_Handler /* PendSV Handler */ - DCD SysTick_Handler /* SysTick Handler */ - - /* Maxim 32620 NVIC Index */ - DCD CLKMAN_IRQHandler /* 16:01 CLKMAN */ - DCD PWRMAN_IRQHandler /* 17:02 PWRMAN */ - DCD FLC_IRQHandler /* 18:03 Flash Controller */ - DCD RTC0_IRQHandler /* 19:04 RTC INT0 */ - DCD RTC1_IRQHandler /* 20:05 RTC INT1 */ - DCD RTC2_IRQHandler /* 21:06 RTC INT2 */ - DCD RTC3_IRQHandler /* 22:07 RTC INT3 */ - DCD PMU_IRQHandler /* 23:08 PMU */ - DCD USB_IRQHandler /* 24:09 USB */ - DCD AES_IRQHandler /* 25:10 AES */ - DCD MAA_IRQHandler /* 26:11 MAA */ - DCD WDT0_IRQHandler /* 27:12 WATCHDOG0 */ - DCD WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ - DCD WDT1_IRQHandler /* 29:14 WATCHDOG1 */ - DCD WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ - DCD GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ - DCD GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ - DCD GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ - DCD GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ - DCD GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ - DCD GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ - DCD GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ - DCD TMR0_IRQHandler /* 38:23 Timer32-0 */ - DCD TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ - DCD TMR1_IRQHandler /* 40:25 Timer32-1 */ - DCD TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ - DCD TMR2_IRQHandler /* 42:27 Timer32-2 */ - DCD TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ - DCD TMR3_IRQHandler /* 44:29 Timer32-3 */ - DCD TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ - DCD TMR4_IRQHandler /* 46:31 Timer32-4 */ - DCD TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ - DCD TMR5_IRQHandler /* 48:33 Timer32-5 */ - DCD TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ - DCD UART0_IRQHandler /* 50:35 UART0 */ - DCD UART1_IRQHandler /* 51:36 UART1 */ - DCD UART2_IRQHandler /* 52:37 UART0 */ - DCD UART3_IRQHandler /* 53:38 UART1 */ - DCD PT_IRQHandler /* 54:39 PT */ - DCD I2CM0_IRQHandler /* 55:40 I2C Master 0 */ - DCD I2CM1_IRQHandler /* 56:41 I2C Master 1 */ - DCD I2CM2_IRQHandler /* 57:42 I2C Master 2 */ - DCD I2CS_IRQHandler /* 58:43 I2C Slave */ - DCD SPI0_IRQHandler /* 59:44 SPI0 */ - DCD SPI1_IRQHandler /* 60:45 SPI1 */ - DCD SPI2_IRQHandler /* 61:46 SPI2 */ - DCD SPIB_IRQHandler /* 62:47 SPI Bridge */ - DCD OWM_IRQHandler /* 63:48 1-Wire Master */ - DCD AFE_IRQHandler /* 64:49 AFE */ - - THUMB - ;; Dummy Exception Handlers (infinite loops which can be modified) - ;; Generate with: - ;; awk '/DCD/ {print "\t\t\tPUBWEAK " $2 "\n" "\t\t\tSECTION .text:CODE:REORDER:NOROOT(1)\n" $2 "\n" "\t\t\tB\t\t" $2 "\n"}' - ;; Paste in DCD lines above, redirect output to file, then read it in below - ;; Note that Reset_Handler is NOROOT(2) while others are NOROOT(1), which is not handled by script - - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK CLKMAN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CLKMAN_IRQHandler - B CLKMAN_IRQHandler - - PUBWEAK PWRMAN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWRMAN_IRQHandler - B PWRMAN_IRQHandler - - PUBWEAK FLC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLC_IRQHandler - B FLC_IRQHandler - - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC0_IRQHandler - B RTC0_IRQHandler - - PUBWEAK RTC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC1_IRQHandler - B RTC1_IRQHandler - - PUBWEAK RTC2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC2_IRQHandler - B RTC2_IRQHandler - - PUBWEAK RTC3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC3_IRQHandler - B RTC3_IRQHandler - - PUBWEAK PMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PMU_IRQHandler - B PMU_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - PUBWEAK MAA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MAA_IRQHandler - B MAA_IRQHandler - - PUBWEAK WDT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT0_IRQHandler - B WDT0_IRQHandler - - PUBWEAK WDT0_P_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT0_P_IRQHandler - B WDT0_P_IRQHandler - - PUBWEAK WDT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT1_IRQHandler - B WDT1_IRQHandler - - PUBWEAK WDT1_P_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT1_P_IRQHandler - B WDT1_P_IRQHandler - - PUBWEAK GPIO_P0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_P0_IRQHandler - B GPIO_P0_IRQHandler - - PUBWEAK GPIO_P1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_P1_IRQHandler - B GPIO_P1_IRQHandler - - PUBWEAK GPIO_P2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_P2_IRQHandler - B GPIO_P2_IRQHandler - - PUBWEAK GPIO_P3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_P3_IRQHandler - B GPIO_P3_IRQHandler - - PUBWEAK GPIO_P4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_P4_IRQHandler - B GPIO_P4_IRQHandler - - PUBWEAK GPIO_P5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_P5_IRQHandler - B GPIO_P5_IRQHandler - - PUBWEAK GPIO_P6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_P6_IRQHandler - B GPIO_P6_IRQHandler - - PUBWEAK TMR0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR0_IRQHandler - B TMR0_IRQHandler - - PUBWEAK TMR16_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR16_0_IRQHandler - B TMR16_0_IRQHandler - - PUBWEAK TMR1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR1_IRQHandler - B TMR1_IRQHandler - - PUBWEAK TMR16_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR16_1_IRQHandler - B TMR16_1_IRQHandler - - PUBWEAK TMR2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR2_IRQHandler - B TMR2_IRQHandler - - PUBWEAK TMR16_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR16_2_IRQHandler - B TMR16_2_IRQHandler - - PUBWEAK TMR3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR3_IRQHandler - B TMR3_IRQHandler - - PUBWEAK TMR16_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR16_3_IRQHandler - B TMR16_3_IRQHandler - - PUBWEAK TMR4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR4_IRQHandler - B TMR4_IRQHandler - - PUBWEAK TMR16_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR16_4_IRQHandler - B TMR16_4_IRQHandler - - PUBWEAK TMR5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR5_IRQHandler - B TMR5_IRQHandler - - PUBWEAK TMR16_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TMR16_5_IRQHandler - B TMR16_5_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK PT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PT_IRQHandler - B PT_IRQHandler - - PUBWEAK I2CM0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2CM0_IRQHandler - B I2CM0_IRQHandler - - PUBWEAK I2CM1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2CM1_IRQHandler - B I2CM1_IRQHandler - - PUBWEAK I2CM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2CM2_IRQHandler - B I2CM2_IRQHandler - - PUBWEAK I2CS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2CS_IRQHandler - B I2CS_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK SPIB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIB_IRQHandler - B SPIB_IRQHandler - - PUBWEAK OWM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OWM_IRQHandler - B OWM_IRQHandler - - PUBWEAK AFE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AFE_IRQHandler - B AFE_IRQHandler - - END - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/adc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/adc_regs.h deleted file mode 100644 index e633dbc316..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/adc_regs.h +++ /dev/null @@ -1,252 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_ADC_REGS_H_ -#define _MXC_ADC_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t ctrl; /* 0x0000 ADC Control */ - __IO uint32_t status; /* 0x0004 ADC Status */ - __IO uint32_t data; /* 0x0008 ADC Output Data */ - __IO uint32_t intr; /* 0x000C ADC Interrupt Control Register */ - __IO uint32_t limit[4]; /* 0x0010-0x001C ADC Limit 0..3 */ - __IO uint32_t afe_ctrl; /* 0x0020 AFE Control Register */ - __IO uint32_t ro_cal0; /* 0x0024 RO Trim Calibration Register 0 */ - __IO uint32_t ro_cal1; /* 0x0028 RO Trim Calibration Register 1 */ - __IO uint32_t ro_cal2; /* 0x002C RO Trim Calibration Register 2 */ -} mxc_adc_regs_t; - - -/* - Register offsets for module ADC. -*/ - -#define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) -#define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) -#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) -#define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) -#define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) -#define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) -#define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) -#define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) -#define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) -#define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) -#define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) - - -/* - Field positions and masks for module ADC. -*/ - -#define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 -#define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) -#define MXC_F_ADC_CTRL_ADC_PU_POS 1 -#define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) -#define MXC_F_ADC_CTRL_BUF_PU_POS 2 -#define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) -#define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 -#define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) -#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 -#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) -#define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 -#define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) -#define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 -#define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) -#define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 -#define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) -#define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 -#define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) -#define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 -#define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) -#define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 -#define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) -#define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 -#define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) -#define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 -#define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) -#define MXC_F_ADC_CTRL_ADC_XREF_POS 16 -#define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) -#define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 -#define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) -#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 -#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) - -#define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 -#define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) -#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 -#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) -#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 -#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) -#define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 -#define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) - -#define MXC_F_ADC_DATA_ADC_DATA_POS 0 -#define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) - -#define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 -#define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) -#define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 -#define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) -#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 -#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) -#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 -#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) -#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 -#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) -#define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 -#define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) -#define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 -#define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) -#define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 -#define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) -#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 -#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) -#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 -#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) -#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 -#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) -#define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 -#define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) -#define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 -#define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) - -#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 -#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) -#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 -#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) -#define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 -#define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) -#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 -#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) -#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 -#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) - -#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 -#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) -#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 -#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) -#define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 -#define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) -#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 -#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) -#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 -#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) - -#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 -#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) -#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 -#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) -#define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 -#define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) -#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 -#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) -#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 -#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) - -#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 -#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) -#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 -#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) -#define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 -#define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) -#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 -#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) -#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 -#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) - -#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 -#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) -#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 -#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) - -#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 -#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) -#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 -#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) -#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 -#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) -#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 -#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) -#define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 -#define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) -#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 -#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) -#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 -#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) - -#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 -#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) -#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 -#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) -#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 -#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) - -#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 -#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_ADC_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/aes_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/aes_regs.h deleted file mode 100644 index 035349ba8a..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/aes_regs.h +++ /dev/null @@ -1,163 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_AES_REGS_H_ -#define _MXC_AES_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t ctrl; /* 0x0000 AES Control and Status */ - __I uint32_t rsv004; /* 0x0004 */ - __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */ -} mxc_aes_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t inp[4]; /* 0x0000-0x000C AES Input (128 bits) */ - __IO uint32_t key[8]; /* 0x0010-0x002C AES Symmetric Key (up to 256 bits) */ - __IO uint32_t out[4]; /* 0x0030-0x003C AES Output Data (128 bits) */ - __IO uint32_t expkey[8]; /* 0x0040-0x005C AES Expanded Key Data (256 bits) */ -} mxc_aes_mem_regs_t; - - -/* - Register offsets for module AES. -*/ - -#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) -#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) -#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) -#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) -#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) -#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) -#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) -#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) -#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) -#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) -#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) -#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) -#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) -#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) -#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) -#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) -#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) -#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) -#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) -#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) -#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) -#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) -#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) -#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) -#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) - - -/* - Field positions and masks for module AES. -*/ - -#define MXC_F_AES_CTRL_START_POS 0 -#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) -#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 -#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) -#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 -#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) -#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 -#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) -#define MXC_F_AES_CTRL_INTEN_POS 5 -#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) -#define MXC_F_AES_CTRL_INTFL_POS 6 -#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) - - - -/* - Field values and shifted values for module AES. -*/ - -#define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) -#define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) - -#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) -#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) - -#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) -#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) - -#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) -#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) - -#define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) -#define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) -#define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) - -#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) -#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) -#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_AES_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/clkman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/clkman_regs.h deleted file mode 100644 index cc1b5b3c8d..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/clkman_regs.h +++ /dev/null @@ -1,426 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_CLKMAN_REGS_H_ -#define _MXC_CLKMAN_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */ - __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */ - __IO uint32_t intfl; /* 0x0008 Interrupt Flags */ - __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */ - __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */ - __IO uint32_t i2c_timer_ctrl; /* 0x0014 I2C Timer Control */ - __IO uint32_t cm4_start_clk_en0; /* 0x0018 CM4 Start Clock on Interrupt Enable 0 */ - __IO uint32_t cm4_start_clk_en1; /* 0x001C CM4 Start Clock on Interrupt Enable 1 */ - __I uint32_t rsv020[8]; /* 0x0020-0x003C */ - __IO uint32_t sys_clk_ctrl_0_cm4; /* 0x0040 Control Settings for CLK0 - Cortex M4 Clock */ - __IO uint32_t sys_clk_ctrl_1_sync; /* 0x0044 Control Settings for CLK1 - Synchronizer Clock */ - __IO uint32_t sys_clk_ctrl_2_spix; /* 0x0048 Control Settings for CLK2 - SPI XIP Clock */ - __IO uint32_t sys_clk_ctrl_3_prng; /* 0x004C Control Settings for CLK3 - PRNG Clock */ - __IO uint32_t sys_clk_ctrl_4_wdt0; /* 0x0050 Control Settings for CLK4 - Watchdog Timer 0 */ - __IO uint32_t sys_clk_ctrl_5_wdt1; /* 0x0054 Control Settings for CLK5 - Watchdog Timer 1 */ - __IO uint32_t sys_clk_ctrl_6_gpio; /* 0x0058 Control Settings for CLK6 - Clock for GPIO Ports */ - __IO uint32_t sys_clk_ctrl_7_pt; /* 0x005C Control Settings for CLK7 - Source Clock for All Pulse Trains */ - __IO uint32_t sys_clk_ctrl_8_uart; /* 0x0060 Control Settings for CLK8 - Source Clock for All UARTs */ - __IO uint32_t sys_clk_ctrl_9_i2cm; /* 0x0064 Control Settings for CLK9 - Source Clock for All I2C Masters */ - __IO uint32_t sys_clk_ctrl_10_i2cs; /* 0x0068 Control Settings for CLK10 - Source Clock for I2C Slave */ - __IO uint32_t sys_clk_ctrl_11_spi0; /* 0x006C Control Settings for CLK11 - SPI Master 0 */ - __IO uint32_t sys_clk_ctrl_12_spi1; /* 0x0070 Control Settings for CLK12 - SPI Master 1 */ - __IO uint32_t sys_clk_ctrl_13_spi2; /* 0x0074 Control Settings for CLK13 - SPI Master 2 */ - __IO uint32_t sys_clk_ctrl_14_spib; /* 0x0078 Control Settings for CLK14 - SPI Bridge Clock */ - __IO uint32_t sys_clk_ctrl_15_owm; /* 0x007C Control Settings for CLK15 - 1-Wire Master Clock */ - __I uint32_t rsv080[32]; /* 0x0080-0x00FC */ - __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */ - __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */ - __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */ - __I uint32_t rsv10C[13]; /* 0x010C-0x013C */ - __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */ - __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */ - __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */ -} mxc_clkman_regs_t; - - -/* - Register offsets for module CLKMAN. -*/ - -#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) -#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) -#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) -#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) -#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) -#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) -#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) -#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) -#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) -#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) -#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) -#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) -#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) -#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) -#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) - - -/* - Field positions and masks for module CLKMAN. -*/ - -#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 -#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) -#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 -#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) - -#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 -#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 -#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 -#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 -#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 -#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 -#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 -#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 -#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 -#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) -#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 -#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) - -#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 -#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) - -#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 -#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) - -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 -#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) - -#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 -#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) - -#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 -#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) - -#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 -#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 -#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) - -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 -#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) - -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 -#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) - -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 -#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) - - - -/* - Field values and shifted values for module CLKMAN. -*/ - -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) -#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) - -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) -#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) - -#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) -#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) - -#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) -#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) - -#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL)) -#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) -#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) -#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) - -#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) -#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) -#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) -#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) - -#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL)) -#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) -#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) -#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) - -#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) -#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) -#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) -#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) - -#define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL)) -#define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL)) - -#define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) -#define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_CLKMAN_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h deleted file mode 100644 index 6bd3ab1b35..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h +++ /dev/null @@ -1,40 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "max32620.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.h deleted file mode 100644 index 5639fd178c..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.h +++ /dev/null @@ -1,42 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -extern void (*ramVectorTable[MXC_IRQ_COUNT])(void); - -#define NVIC_NUM_VECTORS (MXC_IRQ_COUNT) -#define NVIC_RAM_VECTOR_ADDRESS (ramVectorTable) // Vectors positioned at start of RAM - -#endif /* MBED_CMSIS_NVIC_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/crc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/crc_regs.h deleted file mode 100644 index 55e3d1ab3e..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/crc_regs.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_CRC_REGS_H_ -#define _MXC_CRC_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t reseed; /* 0x0000 CRC-16/CRC-32 Reseed Controls */ - __IO uint32_t seed16; /* 0x0004 Reseed Value for CRC-16 Calculations */ - __IO uint32_t seed32; /* 0x0008 Reseed Value for CRC-32 Calculations */ -} mxc_crc_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t value16[512]; /* 0x0000-0x07FC Write Next CRC-16 Data Value / Read CRC-16 Result Value */ - __IO uint32_t value32[512]; /* 0x0800-0x0FFC Write Next CRC-32 Data Value / Read CRC-32 Result Value */ -} mxc_crc_data_regs_t; - - -/* - Register offsets for module CRC. -*/ - -#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL) -#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL) -#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL) -#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL) -#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL) - - -/* - Field positions and masks for module CRC. -*/ - -#define MXC_F_CRC_RESEED_CRC16_POS 0 -#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS)) -#define MXC_F_CRC_RESEED_CRC32_POS 1 -#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_CRC_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/device_nvic.c b/targets/TARGET_Maxim/TARGET_MAX32620/device/device_nvic.c deleted file mode 100644 index 0bea877fd7..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/device_nvic.c +++ /dev/null @@ -1,25 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "cmsis.h" -#include "mbed_toolchain.h" - -/* RAM vector_table needs to be aligned with the size of the vector table */ -/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */ -/* Vector Table Offset which requires the next-power-of-two alignment. This */ -/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */ -MBED_ALIGN(512) -void (*ramVectorTable[MXC_IRQ_COUNT])(void); diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/flc_regs.h deleted file mode 100644 index e39bcf1832..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/flc_regs.h +++ /dev/null @@ -1,224 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_FLC_REGS_H_ -#define _MXC_FLC_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) -#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) -#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t faddr; /* 0x0000 Flash Operation Address */ - __IO uint32_t fckdiv; /* 0x0004 Flash Clock Pulse Divisor */ - __IO uint32_t ctrl; /* 0x0008 Flash Control Register */ - __I uint32_t rsv00C[6]; /* 0x000C-0x0020 */ - __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */ - __I uint32_t rsv028[2]; /* 0x0028-0x002C */ - __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */ - __I uint32_t rsv034[7]; /* 0x0034-0x004C */ - __IO uint32_t perform; /* 0x0050 Flash Performance Settings */ - __I uint32_t rsv054[11]; /* 0x0054-0x007C */ - __IO uint32_t status; /* 0x0080 Security Status Flags */ - __I uint32_t rsv084; /* 0x0084 */ - __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */ - __I uint32_t rsv08C[4]; /* 0x008C-0x0098 */ - __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */ - __I uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */ - __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */ - __I uint32_t rsv104[15]; /* 0x0104-0x013C */ - __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */ - __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */ - __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */ - __I uint32_t rsv14C[9]; /* 0x014C-0x016C */ - __IO uint32_t bl_ctrl; /* 0x0170 Bootloader Control Register */ - __IO uint32_t twk; /* 0x0174 FLC TWK Cycle Count */ - __I uint32_t rsv178; /* 0x0178 */ - __IO uint32_t slm; /* 0x017C Sleep Mode Register */ -} mxc_flc_regs_t; - - -/* - Register offsets for module FLC. -*/ - -#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) -#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) -#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) -#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) -#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) -#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) -#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) -#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) -#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) -#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) -#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) -#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) -#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) -#define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) -#define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) -#define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) - - -/* - Field positions and masks for module FLC. -*/ - -#define MXC_F_FLC_FADDR_FADDR_POS 0 -#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) - -#define MXC_F_FLC_FCKDIV_FCKDIV_POS 0 -#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) - -#define MXC_F_FLC_CTRL_WRITE_POS 0 -#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) -#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 -#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) -#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 -#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) -#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 -#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) -#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 -#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) -#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 -#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) -#define MXC_F_FLC_CTRL_PENDING_POS 24 -#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) -#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 -#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) -#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 -#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) -#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 -#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) - -#define MXC_F_FLC_INTR_STARTED_IF_POS 0 -#define MXC_F_FLC_INTR_STARTED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_STARTED_IF_POS)) -#define MXC_F_FLC_INTR_FAILED_IF_POS 1 -#define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) -#define MXC_F_FLC_INTR_STARTED_IE_POS 8 -#define MXC_F_FLC_INTR_STARTED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_STARTED_IE_POS)) -#define MXC_F_FLC_INTR_FAILED_IE_POS 9 -#define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) - -#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 -#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) -#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 -#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) - -#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 -#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) -#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 -#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) -#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 -#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) -#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 -#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) -#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 -#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) - -#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 -#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) -#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 -#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) -#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 -#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) - -#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 -#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) -#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 -#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) -#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 -#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) -#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 -#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) - -#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 -#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) -#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 -#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) -#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 -#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) - -#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 -#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) -#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 -#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) -#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 -#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) -#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 -#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) - -#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 -#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) -#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 -#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) -#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 -#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) -#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 -#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_FLC_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/gpio_regs.h deleted file mode 100644 index b2259b7434..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/gpio_regs.h +++ /dev/null @@ -1,638 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_GPIO_REGS_H_ -#define _MXC_GPIO_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t rst_mode[7]; /* 0x0000-0x0018 Port P[0..6] Default (Power-On Reset) Output Drive Mode */ - __I uint32_t rsv01C[9]; /* 0x001C-0x003C */ - __IO uint32_t free[7]; /* 0x0040-0x0058 Port P[0..6] Free for GPIO Operation Flags */ - __I uint32_t rsv05C[9]; /* 0x005C-0x007C */ - __IO uint32_t out_mode[7]; /* 0x0080-0x0098 Port P[0..6] Output Drive Mode */ - __I uint32_t rsv09C[9]; /* 0x009C-0x00BC */ - __IO uint32_t out_val[7]; /* 0x00C0-0x00D8 Port P[0..6] GPIO Output Value */ - __I uint32_t rsv0DC[9]; /* 0x00DC-0x00FC */ - __IO uint32_t func_sel[7]; /* 0x0100-0x0118 Port P[0..6] GPIO Function Select */ - __I uint32_t rsv11C[9]; /* 0x011C-0x013C */ - __IO uint32_t in_mode[7]; /* 0x0140-0x0158 Port P[0..6] GPIO Input Monitoring Mode */ - __I uint32_t rsv15C[9]; /* 0x015C-0x017C */ - __IO uint32_t in_val[7]; /* 0x0180-0x0198 Port P[0..6] GPIO Input Value */ - __I uint32_t rsv19C[9]; /* 0x019C-0x01BC */ - __IO uint32_t int_mode[7]; /* 0x01C0-0x01D8 Port P[0..6] Interrupt Detection Mode */ - __I uint32_t rsv1DC[9]; /* 0x01DC-0x01FC */ - __IO uint32_t intfl[7]; /* 0x0200-0x0218 Port P[0..6] Interrupt Flags */ - __I uint32_t rsv21C[9]; /* 0x021C-0x023C */ - __IO uint32_t inten[7]; /* 0x0240-0x0258 Port P[0..6] Interrupt Enables */ -} mxc_gpio_regs_t; - - -/* - Register offsets for module GPIO. -*/ - -#define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) -#define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) -#define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) -#define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) -#define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) -#define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) -#define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) -#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) -#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) -#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) -#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) -#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) -#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) -#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) -#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) -#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) -#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) -#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) -#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) -#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) -#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) -#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) -#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) -#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) -#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) -#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) -#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) -#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) -#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) -#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) -#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) -#define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) -#define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) -#define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) -#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) -#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) -#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) -#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) -#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) -#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) -#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) -#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) -#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) -#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) -#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) -#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) -#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) -#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) -#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) -#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) -#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) -#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) -#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) -#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) -#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) -#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) -#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) -#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) -#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) -#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) -#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) -#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) -#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) -#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) -#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) -#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) -#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) -#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) -#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) -#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) - - -/* - Field positions and masks for module GPIO. -*/ - -#define MXC_F_GPIO_RST_MODE_PIN0_POS 0 -#define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) -#define MXC_F_GPIO_RST_MODE_PIN1_POS 4 -#define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) -#define MXC_F_GPIO_RST_MODE_PIN2_POS 8 -#define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) -#define MXC_F_GPIO_RST_MODE_PIN3_POS 12 -#define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) -#define MXC_F_GPIO_RST_MODE_PIN4_POS 16 -#define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) -#define MXC_F_GPIO_RST_MODE_PIN5_POS 20 -#define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) -#define MXC_F_GPIO_RST_MODE_PIN6_POS 24 -#define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) -#define MXC_F_GPIO_RST_MODE_PIN7_POS 28 -#define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) - -#define MXC_F_GPIO_FREE_PIN0_POS 0 -#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) -#define MXC_F_GPIO_FREE_PIN1_POS 1 -#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) -#define MXC_F_GPIO_FREE_PIN2_POS 2 -#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) -#define MXC_F_GPIO_FREE_PIN3_POS 3 -#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) -#define MXC_F_GPIO_FREE_PIN4_POS 4 -#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) -#define MXC_F_GPIO_FREE_PIN5_POS 5 -#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) -#define MXC_F_GPIO_FREE_PIN6_POS 6 -#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) -#define MXC_F_GPIO_FREE_PIN7_POS 7 -#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) - -#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 -#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) -#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 -#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) -#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 -#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) -#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 -#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) -#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 -#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) -#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 -#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) -#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 -#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) -#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 -#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) - -#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 -#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) -#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 -#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) -#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 -#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) -#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 -#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) -#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 -#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) -#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 -#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) -#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 -#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) -#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 -#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) - -#define MXC_F_GPIO_FUNC_SEL_P0_PIN0_POS 0 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN0_POS)) -#define MXC_F_GPIO_FUNC_SEL_P0_PIN1_POS 4 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN1_POS)) -#define MXC_F_GPIO_FUNC_SEL_P0_PIN2_POS 8 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN2_POS)) -#define MXC_F_GPIO_FUNC_SEL_P0_PIN3_POS 12 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN3_POS)) -#define MXC_F_GPIO_FUNC_SEL_P0_PIN4_POS 16 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN4_POS)) -#define MXC_F_GPIO_FUNC_SEL_P0_PIN5_POS 20 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN5_POS)) -#define MXC_F_GPIO_FUNC_SEL_P0_PIN6_POS 24 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN6_POS)) -#define MXC_F_GPIO_FUNC_SEL_P0_PIN7_POS 28 -#define MXC_F_GPIO_FUNC_SEL_P0_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN7_POS)) - -#define MXC_F_GPIO_FUNC_SEL_P1_PIN0_POS 0 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN0_POS)) -#define MXC_F_GPIO_FUNC_SEL_P1_PIN1_POS 4 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN1_POS)) -#define MXC_F_GPIO_FUNC_SEL_P1_PIN2_POS 8 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN2_POS)) -#define MXC_F_GPIO_FUNC_SEL_P1_PIN3_POS 12 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN3_POS)) -#define MXC_F_GPIO_FUNC_SEL_P1_PIN4_POS 16 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN4_POS)) -#define MXC_F_GPIO_FUNC_SEL_P1_PIN5_POS 20 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN5_POS)) -#define MXC_F_GPIO_FUNC_SEL_P1_PIN6_POS 24 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN6_POS)) -#define MXC_F_GPIO_FUNC_SEL_P1_PIN7_POS 28 -#define MXC_F_GPIO_FUNC_SEL_P1_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN7_POS)) - -#define MXC_F_GPIO_FUNC_SEL_P2_PIN0_POS 0 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN0_POS)) -#define MXC_F_GPIO_FUNC_SEL_P2_PIN1_POS 4 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN1_POS)) -#define MXC_F_GPIO_FUNC_SEL_P2_PIN2_POS 8 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN2_POS)) -#define MXC_F_GPIO_FUNC_SEL_P2_PIN3_POS 12 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN3_POS)) -#define MXC_F_GPIO_FUNC_SEL_P2_PIN4_POS 16 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN4_POS)) -#define MXC_F_GPIO_FUNC_SEL_P2_PIN5_POS 20 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN5_POS)) -#define MXC_F_GPIO_FUNC_SEL_P2_PIN6_POS 24 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN6_POS)) -#define MXC_F_GPIO_FUNC_SEL_P2_PIN7_POS 28 -#define MXC_F_GPIO_FUNC_SEL_P2_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN7_POS)) - -#define MXC_F_GPIO_FUNC_SEL_P3_PIN0_POS 0 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN0_POS)) -#define MXC_F_GPIO_FUNC_SEL_P3_PIN1_POS 4 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN1_POS)) -#define MXC_F_GPIO_FUNC_SEL_P3_PIN2_POS 8 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN2_POS)) -#define MXC_F_GPIO_FUNC_SEL_P3_PIN3_POS 12 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN3_POS)) -#define MXC_F_GPIO_FUNC_SEL_P3_PIN4_POS 16 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN4_POS)) -#define MXC_F_GPIO_FUNC_SEL_P3_PIN5_POS 20 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN5_POS)) -#define MXC_F_GPIO_FUNC_SEL_P3_PIN6_POS 24 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN6_POS)) -#define MXC_F_GPIO_FUNC_SEL_P3_PIN7_POS 28 -#define MXC_F_GPIO_FUNC_SEL_P3_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN7_POS)) - -#define MXC_F_GPIO_FUNC_SEL_P4_PIN0_POS 0 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN0_POS)) -#define MXC_F_GPIO_FUNC_SEL_P4_PIN1_POS 4 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN1_POS)) -#define MXC_F_GPIO_FUNC_SEL_P4_PIN2_POS 8 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN2_POS)) -#define MXC_F_GPIO_FUNC_SEL_P4_PIN3_POS 12 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN3_POS)) -#define MXC_F_GPIO_FUNC_SEL_P4_PIN4_POS 16 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN4_POS)) -#define MXC_F_GPIO_FUNC_SEL_P4_PIN5_POS 20 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN5_POS)) -#define MXC_F_GPIO_FUNC_SEL_P4_PIN6_POS 24 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN6_POS)) -#define MXC_F_GPIO_FUNC_SEL_P4_PIN7_POS 28 -#define MXC_F_GPIO_FUNC_SEL_P4_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN7_POS)) - -#define MXC_F_GPIO_FUNC_SEL_P5_PIN0_POS 0 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN0_POS)) -#define MXC_F_GPIO_FUNC_SEL_P5_PIN1_POS 4 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN1_POS)) -#define MXC_F_GPIO_FUNC_SEL_P5_PIN2_POS 8 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN2_POS)) -#define MXC_F_GPIO_FUNC_SEL_P5_PIN3_POS 12 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN3_POS)) -#define MXC_F_GPIO_FUNC_SEL_P5_PIN4_POS 16 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN4_POS)) -#define MXC_F_GPIO_FUNC_SEL_P5_PIN5_POS 20 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN5_POS)) -#define MXC_F_GPIO_FUNC_SEL_P5_PIN6_POS 24 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN6_POS)) -#define MXC_F_GPIO_FUNC_SEL_P5_PIN7_POS 28 -#define MXC_F_GPIO_FUNC_SEL_P5_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN7_POS)) - -#define MXC_F_GPIO_FUNC_SEL_P6_PIN0_POS 0 -#define MXC_F_GPIO_FUNC_SEL_P6_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P6_PIN0_POS)) - -#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 -#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) -#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 -#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) -#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 -#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) -#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 -#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) -#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 -#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) -#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 -#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) -#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 -#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) -#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 -#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) - -#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 -#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) -#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 -#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) -#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 -#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) -#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 -#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) -#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 -#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) -#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 -#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) -#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 -#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) -#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 -#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) - -#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 -#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) -#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 -#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) -#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 -#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) -#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 -#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) -#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 -#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) -#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 -#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) -#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 -#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) -#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 -#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) - -#define MXC_F_GPIO_INTFL_PIN0_POS 0 -#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) -#define MXC_F_GPIO_INTFL_PIN1_POS 1 -#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) -#define MXC_F_GPIO_INTFL_PIN2_POS 2 -#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) -#define MXC_F_GPIO_INTFL_PIN3_POS 3 -#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) -#define MXC_F_GPIO_INTFL_PIN4_POS 4 -#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) -#define MXC_F_GPIO_INTFL_PIN5_POS 5 -#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) -#define MXC_F_GPIO_INTFL_PIN6_POS 6 -#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) -#define MXC_F_GPIO_INTFL_PIN7_POS 7 -#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) - -#define MXC_F_GPIO_INTEN_PIN0_POS 0 -#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) -#define MXC_F_GPIO_INTEN_PIN1_POS 1 -#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) -#define MXC_F_GPIO_INTEN_PIN2_POS 2 -#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) -#define MXC_F_GPIO_INTEN_PIN3_POS 3 -#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) -#define MXC_F_GPIO_INTEN_PIN4_POS 4 -#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) -#define MXC_F_GPIO_INTEN_PIN5_POS 5 -#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) -#define MXC_F_GPIO_INTEN_PIN6_POS 6 -#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) -#define MXC_F_GPIO_INTEN_PIN7_POS 7 -#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) - - - -/* - Field values and shifted values for module GPIO. -*/ - -#define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) - -#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) - -#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) - -#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) - -#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) - -#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) - -#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) - -#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) - -#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x00000001UL)) - -#define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) - -#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) -#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) -#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) -#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) -#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) -#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) -#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) -#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) -#define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) - -#define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_V_GPIO_IN_MODE_PIN0_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN0_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN0_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN0_POS)) - -#define MXC_V_GPIO_IN_MODE_PIN1_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN1_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN1_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN1_POS)) - -#define MXC_V_GPIO_IN_MODE_PIN2_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN2_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN2_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN2_POS)) - -#define MXC_V_GPIO_IN_MODE_PIN3_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN3_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN3_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN3_POS)) - -#define MXC_V_GPIO_IN_MODE_PIN4_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN4_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN4_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN4_POS)) - -#define MXC_V_GPIO_IN_MODE_PIN5_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN5_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN5_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN5_POS)) - -#define MXC_V_GPIO_IN_MODE_PIN6_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN6_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN6_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN6_POS)) - -#define MXC_V_GPIO_IN_MODE_PIN7_NORMAL ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_IN_MODE_PIN7_INVERTED ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ONE ((uint32_t)(0x00000003UL)) - -#define MXC_S_GPIO_IN_MODE_PIN7_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN7_POS)) - -#define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_V_GPIO_INT_MODE_PIN0_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN0_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN0_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN0_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN0_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN0_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN0_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN0_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN0_POS)) - -#define MXC_V_GPIO_INT_MODE_PIN1_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN1_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN1_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN1_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN1_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN1_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN1_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN1_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN1_POS)) - -#define MXC_V_GPIO_INT_MODE_PIN2_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN2_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN2_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN2_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN2_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN2_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN2_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN2_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN2_POS)) - -#define MXC_V_GPIO_INT_MODE_PIN3_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN3_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN3_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN3_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN3_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN3_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN3_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN3_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN3_POS)) - -#define MXC_V_GPIO_INT_MODE_PIN4_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN4_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN4_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN4_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN4_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN4_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN4_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN4_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN4_POS)) - -#define MXC_V_GPIO_INT_MODE_PIN5_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN5_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN5_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN5_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN5_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN5_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN5_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN5_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN5_POS)) - -#define MXC_V_GPIO_INT_MODE_PIN6_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN6_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN6_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN6_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN6_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN6_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN6_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN6_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN6_POS)) - -#define MXC_V_GPIO_INT_MODE_PIN7_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_GPIO_INT_MODE_PIN7_FALLING_EDGE ((uint32_t)(0x00000001UL)) -#define MXC_V_GPIO_INT_MODE_PIN7_RISING_EDGE ((uint32_t)(0x00000002UL)) -#define MXC_V_GPIO_INT_MODE_PIN7_ANY_EDGE ((uint32_t)(0x00000003UL)) -#define MXC_V_GPIO_INT_MODE_PIN7_LOW_LVL ((uint32_t)(0x00000004UL)) -#define MXC_V_GPIO_INT_MODE_PIN7_HIGH_LVL ((uint32_t)(0x00000005UL)) - -#define MXC_S_GPIO_INT_MODE_PIN7_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN7_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN7_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_GPIO_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/i2cm_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/i2cm_regs.h deleted file mode 100644 index 85c8df2593..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/i2cm_regs.h +++ /dev/null @@ -1,205 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_I2CM_REGS_H_ -#define _MXC_I2CM_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -#define MXC_S_I2CM_TRANS_TAG_START 0x000 -#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100 -#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200 -#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400 -#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500 -#define MXC_S_I2CM_TRANS_TAG_STOP 0x700 -#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100 -#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200 - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t fs_clk_div; /* 0x0000 I2C Master Full Speed SCL Clock Settings */ - __I uint32_t rsv004[2]; /* 0x0004-0x0008 */ - __IO uint32_t timeout; /* 0x000C I2C Master Timeout and Auto-Stop Settings */ - __IO uint32_t ctrl; /* 0x0010 I2C Master Control Register */ - __IO uint32_t trans; /* 0x0014 I2C Master Transaction Start and Status Flags */ - __IO uint32_t intfl; /* 0x0018 I2C Master Interrupt Flags */ - __IO uint32_t inten; /* 0x001C I2C Master Interrupt Enable/Disable Controls */ - __I uint32_t rsv020[2]; /* 0x0020-0x0024 */ - __IO uint32_t bb; /* 0x0028 I2C Master Bit-Bang Control Register */ -} mxc_i2cm_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint16_t trans[1024]; /* 0x0000-0x07FC I2C Master 0 Transaction FIFO */ - __IO uint16_t rslts[1024]; /* 0x0800-0x0FFC I2C Master 0 Results FIFO */ -} mxc_i2cm_fifo_regs_t; - - -/* - Register offsets for module I2CM. -*/ - -#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) -#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) -#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) -#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) -#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) -#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) -#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) -#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) -#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) - - -/* - Field positions and masks for module I2CM. -*/ - -#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0 -#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS)) -#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8 -#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)) -#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20 -#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS)) - -#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 -#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) -#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 -#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) - -#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 -#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) -#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 -#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) -#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 -#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) - -#define MXC_F_I2CM_TRANS_TX_START_POS 0 -#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) -#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 -#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) -#define MXC_F_I2CM_TRANS_TX_DONE_POS 2 -#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) -#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 -#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) -#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 -#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) -#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 -#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) - -#define MXC_F_I2CM_INTFL_TX_DONE_POS 0 -#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) -#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 -#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) -#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 -#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) -#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 -#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) -#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 -#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) -#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 -#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) -#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 -#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) -#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 -#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) -#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 -#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) -#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 -#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) - -#define MXC_F_I2CM_INTEN_TX_DONE_POS 0 -#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) -#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 -#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) -#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 -#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) -#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 -#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) -#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 -#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) -#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 -#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) -#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6 -#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS)) -#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 -#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) -#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 -#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) -#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 -#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) - -#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 -#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) -#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 -#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) -#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 -#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) -#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 -#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) -#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 -#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_I2CM_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/i2cs_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/i2cs_regs.h deleted file mode 100644 index 7a4e4e8be5..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/i2cs_regs.h +++ /dev/null @@ -1,242 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_I2CS_REGS_H_ -#define _MXC_I2CS_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t clk_div; /* 0x0000 I2C Slave Clock Divisor Control */ - __IO uint32_t dev_id; /* 0x0004 I2C Slave Device ID Register */ - __IO uint32_t intfl; /* 0x0008 I2CS Interrupt Flags */ - __IO uint32_t inten; /* 0x000C I2CS Interrupt Enable/Disable Controls */ - __IO uint32_t data_byte[32]; /* 0x0010-0x008C I2CS Data Byte */ -} mxc_i2cs_regs_t; - - -/* - Register offsets for module I2CS. -*/ - -#define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL) -#define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL) -#define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL) -#define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL) -#define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL) - - -/* - Field positions and masks for module I2CS. -*/ - -#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0 -#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)) - -#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0 -#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)) -#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12 -#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS)) -#define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14 -#define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS)) - -#define MXC_F_I2CS_INTFL_BYTE0_POS 0 -#define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS)) -#define MXC_F_I2CS_INTFL_BYTE1_POS 1 -#define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS)) -#define MXC_F_I2CS_INTFL_BYTE2_POS 2 -#define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS)) -#define MXC_F_I2CS_INTFL_BYTE3_POS 3 -#define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS)) -#define MXC_F_I2CS_INTFL_BYTE4_POS 4 -#define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS)) -#define MXC_F_I2CS_INTFL_BYTE5_POS 5 -#define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS)) -#define MXC_F_I2CS_INTFL_BYTE6_POS 6 -#define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS)) -#define MXC_F_I2CS_INTFL_BYTE7_POS 7 -#define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS)) -#define MXC_F_I2CS_INTFL_BYTE8_POS 8 -#define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS)) -#define MXC_F_I2CS_INTFL_BYTE9_POS 9 -#define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS)) -#define MXC_F_I2CS_INTFL_BYTE10_POS 10 -#define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS)) -#define MXC_F_I2CS_INTFL_BYTE11_POS 11 -#define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS)) -#define MXC_F_I2CS_INTFL_BYTE12_POS 12 -#define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS)) -#define MXC_F_I2CS_INTFL_BYTE13_POS 13 -#define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS)) -#define MXC_F_I2CS_INTFL_BYTE14_POS 14 -#define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS)) -#define MXC_F_I2CS_INTFL_BYTE15_POS 15 -#define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS)) -#define MXC_F_I2CS_INTFL_BYTE16_POS 16 -#define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS)) -#define MXC_F_I2CS_INTFL_BYTE17_POS 17 -#define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS)) -#define MXC_F_I2CS_INTFL_BYTE18_POS 18 -#define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS)) -#define MXC_F_I2CS_INTFL_BYTE19_POS 19 -#define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS)) -#define MXC_F_I2CS_INTFL_BYTE20_POS 20 -#define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS)) -#define MXC_F_I2CS_INTFL_BYTE21_POS 21 -#define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS)) -#define MXC_F_I2CS_INTFL_BYTE22_POS 22 -#define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS)) -#define MXC_F_I2CS_INTFL_BYTE23_POS 23 -#define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS)) -#define MXC_F_I2CS_INTFL_BYTE24_POS 24 -#define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS)) -#define MXC_F_I2CS_INTFL_BYTE25_POS 25 -#define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS)) -#define MXC_F_I2CS_INTFL_BYTE26_POS 26 -#define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS)) -#define MXC_F_I2CS_INTFL_BYTE27_POS 27 -#define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS)) -#define MXC_F_I2CS_INTFL_BYTE28_POS 28 -#define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS)) -#define MXC_F_I2CS_INTFL_BYTE29_POS 29 -#define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS)) -#define MXC_F_I2CS_INTFL_BYTE30_POS 30 -#define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS)) -#define MXC_F_I2CS_INTFL_BYTE31_POS 31 -#define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS)) - -#define MXC_F_I2CS_INTEN_BYTE0_POS 0 -#define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS)) -#define MXC_F_I2CS_INTEN_BYTE1_POS 1 -#define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS)) -#define MXC_F_I2CS_INTEN_BYTE2_POS 2 -#define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS)) -#define MXC_F_I2CS_INTEN_BYTE3_POS 3 -#define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS)) -#define MXC_F_I2CS_INTEN_BYTE4_POS 4 -#define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS)) -#define MXC_F_I2CS_INTEN_BYTE5_POS 5 -#define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS)) -#define MXC_F_I2CS_INTEN_BYTE6_POS 6 -#define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS)) -#define MXC_F_I2CS_INTEN_BYTE7_POS 7 -#define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS)) -#define MXC_F_I2CS_INTEN_BYTE8_POS 8 -#define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS)) -#define MXC_F_I2CS_INTEN_BYTE9_POS 9 -#define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS)) -#define MXC_F_I2CS_INTEN_BYTE10_POS 10 -#define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS)) -#define MXC_F_I2CS_INTEN_BYTE11_POS 11 -#define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS)) -#define MXC_F_I2CS_INTEN_BYTE12_POS 12 -#define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS)) -#define MXC_F_I2CS_INTEN_BYTE13_POS 13 -#define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS)) -#define MXC_F_I2CS_INTEN_BYTE14_POS 14 -#define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS)) -#define MXC_F_I2CS_INTEN_BYTE15_POS 15 -#define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS)) -#define MXC_F_I2CS_INTEN_BYTE16_POS 16 -#define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS)) -#define MXC_F_I2CS_INTEN_BYTE17_POS 17 -#define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS)) -#define MXC_F_I2CS_INTEN_BYTE18_POS 18 -#define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS)) -#define MXC_F_I2CS_INTEN_BYTE19_POS 19 -#define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS)) -#define MXC_F_I2CS_INTEN_BYTE20_POS 20 -#define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS)) -#define MXC_F_I2CS_INTEN_BYTE21_POS 21 -#define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS)) -#define MXC_F_I2CS_INTEN_BYTE22_POS 22 -#define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS)) -#define MXC_F_I2CS_INTEN_BYTE23_POS 23 -#define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS)) -#define MXC_F_I2CS_INTEN_BYTE24_POS 24 -#define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS)) -#define MXC_F_I2CS_INTEN_BYTE25_POS 25 -#define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS)) -#define MXC_F_I2CS_INTEN_BYTE26_POS 26 -#define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS)) -#define MXC_F_I2CS_INTEN_BYTE27_POS 27 -#define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS)) -#define MXC_F_I2CS_INTEN_BYTE28_POS 28 -#define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS)) -#define MXC_F_I2CS_INTEN_BYTE29_POS 29 -#define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS)) -#define MXC_F_I2CS_INTEN_BYTE30_POS 30 -#define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS)) -#define MXC_F_I2CS_INTEN_BYTE31_POS 31 -#define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS)) - -#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0 -#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)) -#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8 -#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS)) -#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9 -#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_I2CS_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/icc_regs.h deleted file mode 100644 index e181d1e899..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/icc_regs.h +++ /dev/null @@ -1,112 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_ICC_REGS_H_ -#define _MXC_ICC_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t id; /* 0x0000 Cache ID Register (INTERNAL USE ONLY) */ - __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration Register */ - __I uint32_t rsv008[62]; /* 0x0008-0x00FC */ - __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */ - __I uint32_t rsv104[383]; /* 0x0104-0x06FC */ - __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */ -} mxc_icc_regs_t; - - -/* - Register offsets for module ICC. -*/ - -#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) -#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) -#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) -#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) - - -/* - Field positions and masks for module ICC. -*/ - -#define MXC_F_ICC_ID_RTL_VERSION_POS 0 -#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) -#define MXC_F_ICC_ID_PART_NUM_POS 6 -#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) -#define MXC_F_ICC_ID_CACHE_ID_POS 10 -#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) - -#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 -#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) -#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 -#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) - -#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 -#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) -#define MXC_F_ICC_CTRL_STAT_READY_POS 16 -#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_ICC_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h deleted file mode 100644 index 427ca5e4da..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h +++ /dev/null @@ -1,904 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_IOMAN_REGS_H_ -#define _MXC_IOMAN_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - -/* - Enum type definitions for register fields in this module -*/ - -/** - * @brief Pin mapping define values common to all modules - */ -typedef enum { - /** Pin Mapping 'A' */ - MXC_E_IOMAN_MAPPING_A = 0, - /** Pin Mapping 'B' */ - MXC_E_IOMAN_MAPPING_B -} ioman_mapping_t; - - -/* - Bitfield structs for registers in this module -*/ - -typedef struct { - uint32_t wud_req_p0 : 8; - uint32_t wud_req_p1 : 8; - uint32_t wud_req_p2 : 8; - uint32_t wud_req_p3 : 8; -} mxc_ioman_wud_req0_t; - -typedef struct { - uint32_t wud_req_p4 : 8; - uint32_t wud_req_p5 : 8; - uint32_t wud_req_p6 : 1; - uint32_t : 15; -} mxc_ioman_wud_req1_t; - -typedef struct { - uint32_t wud_ack_p0 : 8; - uint32_t wud_ack_p1 : 8; - uint32_t wud_ack_p2 : 8; - uint32_t wud_ack_p3 : 8; -} mxc_ioman_wud_ack0_t; - -typedef struct { - uint32_t wud_ack_p4 : 8; - uint32_t wud_ack_p5 : 8; - uint32_t wud_ack_p6 : 1; - uint32_t : 15; -} mxc_ioman_wud_ack1_t; - -typedef struct { - uint32_t ali_req_p0 : 8; - uint32_t ali_req_p1 : 8; - uint32_t ali_req_p2 : 8; - uint32_t ali_req_p3 : 8; -} mxc_ioman_ali_req0_t; - -typedef struct { - uint32_t ali_req_p4 : 8; - uint32_t ali_req_p5 : 8; - uint32_t ali_req_p6 : 1; - uint32_t : 15; -} mxc_ioman_ali_req1_t; - -typedef struct { - uint32_t ali_ack_p0 : 8; - uint32_t ali_ack_p1 : 8; - uint32_t ali_ack_p2 : 8; - uint32_t ali_ack_p3 : 8; -} mxc_ioman_ali_ack0_t; - -typedef struct { - uint32_t ali_ack_p4 : 8; - uint32_t ali_ack_p5 : 8; - uint32_t ali_ack_p6 : 1; - uint32_t : 15; -} mxc_ioman_ali_ack1_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_req : 1; - uint32_t : 3; - uint32_t ss0_io_req : 1; - uint32_t ss1_io_req : 1; - uint32_t ss2_io_req : 1; - uint32_t : 1; - uint32_t quad_io_req : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 15; -} mxc_ioman_spix_req_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_ack : 1; - uint32_t : 3; - uint32_t ss0_io_ack : 1; - uint32_t ss1_io_ack : 1; - uint32_t ss2_io_ack : 1; - uint32_t : 1; - uint32_t quad_io_ack : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 15; -} mxc_ioman_spix_ack_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_req : 1; - uint32_t cts_io_req : 1; - uint32_t rts_io_req : 1; - uint32_t : 25; -} mxc_ioman_uart0_req_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_ack : 1; - uint32_t cts_io_ack : 1; - uint32_t rts_io_ack : 1; - uint32_t : 25; -} mxc_ioman_uart0_ack_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_req : 1; - uint32_t cts_io_req : 1; - uint32_t rts_io_req : 1; - uint32_t : 25; -} mxc_ioman_uart1_req_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_ack : 1; - uint32_t cts_io_ack : 1; - uint32_t rts_io_ack : 1; - uint32_t : 25; -} mxc_ioman_uart1_ack_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_req : 1; - uint32_t cts_io_req : 1; - uint32_t rts_io_req : 1; - uint32_t : 25; -} mxc_ioman_uart2_req_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_ack : 1; - uint32_t cts_io_ack : 1; - uint32_t rts_io_ack : 1; - uint32_t : 25; -} mxc_ioman_uart2_ack_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_req : 1; - uint32_t cts_io_req : 1; - uint32_t rts_io_req : 1; - uint32_t : 25; -} mxc_ioman_uart3_req_t; - -typedef struct { - uint32_t io_map : 1; - uint32_t cts_map : 1; - uint32_t rts_map : 1; - uint32_t : 1; - uint32_t io_ack : 1; - uint32_t cts_io_ack : 1; - uint32_t rts_io_ack : 1; - uint32_t : 25; -} mxc_ioman_uart3_ack_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_req : 1; - uint32_t : 27; -} mxc_ioman_i2cm0_req_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_ack : 1; - uint32_t : 27; -} mxc_ioman_i2cm0_ack_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_req : 1; - uint32_t : 27; -} mxc_ioman_i2cm1_req_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_ack : 1; - uint32_t : 27; -} mxc_ioman_i2cm1_ack_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_req : 1; - uint32_t : 27; -} mxc_ioman_i2cm2_req_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_ack : 1; - uint32_t : 27; -} mxc_ioman_i2cm2_ack_t; - -typedef struct { - uint32_t io_sel : 2; - uint32_t : 2; - uint32_t mapping_req : 1; - uint32_t : 27; -} mxc_ioman_i2cs_req_t; - -typedef struct { - uint32_t io_sel : 2; - uint32_t : 2; - uint32_t mapping_ack : 1; - uint32_t : 27; -} mxc_ioman_i2cs_ack_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_req : 1; - uint32_t : 3; - uint32_t ss0_io_req : 1; - uint32_t ss1_io_req : 1; - uint32_t ss2_io_req : 1; - uint32_t ss3_io_req : 1; - uint32_t ss4_io_req : 1; - uint32_t : 7; - uint32_t quad_io_req : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 7; -} mxc_ioman_spim0_req_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_ack : 1; - uint32_t : 3; - uint32_t ss0_io_ack : 1; - uint32_t ss1_io_ack : 1; - uint32_t ss2_io_ack : 1; - uint32_t ss3_io_ack : 1; - uint32_t ss4_io_ack : 1; - uint32_t : 7; - uint32_t quad_io_ack : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 7; -} mxc_ioman_spim0_ack_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_req : 1; - uint32_t : 3; - uint32_t ss0_io_req : 1; - uint32_t ss1_io_req : 1; - uint32_t ss2_io_req : 1; - uint32_t : 9; - uint32_t quad_io_req : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 7; -} mxc_ioman_spim1_req_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_ack : 1; - uint32_t : 3; - uint32_t ss0_io_ack : 1; - uint32_t ss1_io_ack : 1; - uint32_t ss2_io_ack : 1; - uint32_t : 9; - uint32_t quad_io_ack : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 7; -} mxc_ioman_spim1_ack_t; - -typedef struct { - uint32_t mapping_req : 1; - uint32_t : 3; - uint32_t core_io_req : 1; - uint32_t : 3; - uint32_t ss0_io_req : 1; - uint32_t ss1_io_req : 1; - uint32_t ss2_io_req : 1; - uint32_t : 5; - uint32_t sr0_io_req : 1; - uint32_t sr1_io_req : 1; - uint32_t : 2; - uint32_t quad_io_req : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 7; -} mxc_ioman_spim2_req_t; - -typedef struct { - uint32_t mapping_ack : 1; - uint32_t : 3; - uint32_t core_io_ack : 1; - uint32_t : 3; - uint32_t ss0_io_ack : 1; - uint32_t ss1_io_ack : 1; - uint32_t ss2_io_ack : 1; - uint32_t : 5; - uint32_t sr0_io_req : 1; - uint32_t sr1_io_req : 1; - uint32_t : 2; - uint32_t quad_io_ack : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 7; -} mxc_ioman_spim2_ack_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_req : 1; - uint32_t : 3; - uint32_t quad_io_req : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 19; -} mxc_ioman_spib_req_t; - -typedef struct { - uint32_t : 4; - uint32_t core_io_ack : 1; - uint32_t : 3; - uint32_t quad_io_ack : 1; - uint32_t : 3; - uint32_t fast_mode : 1; - uint32_t : 19; -} mxc_ioman_spib_ack_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_req : 1; - uint32_t epu_io_req : 1; - uint32_t : 26; -} mxc_ioman_owm_req_t; - -typedef struct { - uint32_t : 4; - uint32_t mapping_ack : 1; - uint32_t epu_io_ack : 1; - uint32_t : 26; -} mxc_ioman_owm_ack_t; - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */ - __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 (P4/P5/P6) */ - __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */ - __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6) */ - __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 (P0/P1/P2/P3) */ - __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 (P4/P5/P6) */ - __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */ - __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 (P4/P5/P6) */ - __IO uint32_t ali_connect0; /* 0x0020 Analog I/O Connection Control Register 0 */ - __IO uint32_t ali_connect1; /* 0x0024 Analog I/O Connection Control Register 1 */ - __IO uint32_t spix_req; /* 0x0028 SPIX I/O Mode Request */ - __IO uint32_t spix_ack; /* 0x002C SPIX I/O Mode Acknowledge */ - __IO uint32_t uart0_req; /* 0x0030 UART0 I/O Mode Request */ - __IO uint32_t uart0_ack; /* 0x0034 UART0 I/O Mode Acknowledge */ - __IO uint32_t uart1_req; /* 0x0038 UART1 I/O Mode Request */ - __IO uint32_t uart1_ack; /* 0x003C UART1 I/O Mode Acknowledge */ - __IO uint32_t uart2_req; /* 0x0040 UART2 I/O Mode Request */ - __IO uint32_t uart2_ack; /* 0x0044 UART2 I/O Mode Acknowledge */ - __IO uint32_t uart3_req; /* 0x0048 UART3 I/O Mode Request */ - __IO uint32_t uart3_ack; /* 0x004C UART3 I/O Mode Acknowledge */ - __IO uint32_t i2cm0_req; /* 0x0050 I2C Master 0 I/O Request */ - __IO uint32_t i2cm0_ack; /* 0x0054 I2C Master 0 I/O Acknowledge */ - __IO uint32_t i2cm1_req; /* 0x0058 I2C Master 1 I/O Request */ - __IO uint32_t i2cm1_ack; /* 0x005C I2C Master 1 I/O Acknowledge */ - __IO uint32_t i2cm2_req; /* 0x0060 I2C Master 2 I/O Request */ - __IO uint32_t i2cm2_ack; /* 0x0064 I2C Master 2 I/O Acknowledge */ - __IO uint32_t i2cs_req; /* 0x0068 I2C Slave I/O Request */ - __IO uint32_t i2cs_ack; /* 0x006C I2C Slave I/O Acknowledge */ - __IO uint32_t spim0_req; /* 0x0070 SPI Master 0 I/O Mode Request */ - __IO uint32_t spim0_ack; /* 0x0074 SPI Master 0 I/O Mode Acknowledge */ - __IO uint32_t spim1_req; /* 0x0078 SPI Master 1 I/O Mode Request */ - __IO uint32_t spim1_ack; /* 0x007C SPI Master 1 I/O Mode Acknowledge */ - __IO uint32_t spim2_req; /* 0x0080 SPI Master 2 I/O Mode Request */ - __IO uint32_t spim2_ack; /* 0x0084 SPI Master 2 I/O Mode Acknowledge */ - __IO uint32_t spib_req; /* 0x0088 SPI Bridge I/O Mode Request */ - __IO uint32_t spib_ack; /* 0x008C SPI Bridge I/O Mode Acknowledge */ - __IO uint32_t owm_req; /* 0x0090 1-Wire Master I/O Mode Request */ - __IO uint32_t owm_ack; /* 0x0094 1-Wire Master I/O Mode Acknowledge */ -} mxc_ioman_regs_t; - - -/* - Register offsets for module IOMAN. -*/ - -#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) -#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) -#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) -#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) -#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) -#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) -#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) -#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) -#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) -#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) -#define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) -#define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) -#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) -#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) -#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) -#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) -#define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) -#define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) -#define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL) -#define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL) -#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) -#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) -#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) -#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) -#define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL) -#define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL) -#define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) -#define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) -#define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) -#define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) -#define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) -#define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) -#define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) -#define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) -#define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL) -#define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL) -#define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) -#define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) - - -/* - Field positions and masks for module IOMAN. -*/ - -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0 -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS)) -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8 -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS)) -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16 -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS)) -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24 -#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS)) - -#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0 -#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS)) -#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8 -#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS)) -#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16 -#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS)) - -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0 -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS)) -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8 -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS)) -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16 -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS)) -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24 -#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS)) - -#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0 -#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS)) -#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8 -#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS)) -#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16 -#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS)) - -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0 -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS)) -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8 -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS)) -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16 -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS)) -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24 -#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS)) - -#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0 -#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS)) -#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8 -#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS)) -#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16 -#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS)) - -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0 -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS)) -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8 -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS)) -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16 -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS)) -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24 -#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS)) - -#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0 -#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS)) -#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8 -#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS)) -#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16 -#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS)) - -#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4 -#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8 -#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9 -#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10 -#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12 -#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16 -#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4 -#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8 -#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9 -#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10 -#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12 -#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16 -#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS)) - -#define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) -#define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4 -#define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) -#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5 -#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) -#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6 -#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) - -#define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) -#define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4 -#define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) -#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5 -#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) -#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6 -#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) - -#define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS)) -#define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4 -#define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS)) -#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5 -#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS)) -#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6 -#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS)) - -#define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS)) -#define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4 -#define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS)) -#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5 -#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS)) -#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6 -#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS)) - -#define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS)) -#define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4 -#define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS)) -#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5 -#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS)) -#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6 -#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS)) - -#define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS)) -#define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4 -#define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS)) -#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5 -#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS)) -#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6 -#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS)) - -#define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS)) -#define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4 -#define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS)) -#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5 -#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS)) -#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6 -#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS)) - -#define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0 -#define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS)) -#define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1 -#define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2 -#define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4 -#define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS)) -#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5 -#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS)) -#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6 -#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS)) - -#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4 -#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) - -#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4 -#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) - -#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4 -#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS)) - -#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4 -#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS)) - -#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4 -#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS)) - -#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4 -#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS)) - -#define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0 -#define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS)) -#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4 -#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS)) - -#define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0 -#define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS)) -#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4 -#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS)) - -#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4 -#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8 -#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9 -#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10 -#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11 -#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12 -#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20 -#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24 -#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4 -#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8 -#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9 -#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10 -#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11 -#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12 -#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20 -#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24 -#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4 -#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8 -#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9 -#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10 -#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20 -#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24 -#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4 -#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8 -#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9 -#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10 -#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20 -#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24 -#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0 -#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4 -#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8 -#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9 -#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10 -#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16 -#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17 -#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20 -#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24 -#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0 -#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4 -#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8 -#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9 -#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10 -#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS 16 -#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK_POS 17 -#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20 -#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24 -#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4 -#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8 -#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12 -#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS)) - -#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4 -#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8 -#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12 -#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS)) - -#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4 -#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS)) -#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5 -#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS)) - -#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4 -#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS)) -#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5 -#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS)) - -/* - Generic field positions and masks for module IOMAN. -*/ -#define MXC_F_IOMAN_UART_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) -#define MXC_F_IOMAN_UART_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) -#define MXC_F_IOMAN_UART_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) -#define MXC_F_IOMAN_UART_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) - -#define MXC_F_IOMAN_UART_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) -#define MXC_F_IOMAN_UART_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) -#define MXC_F_IOMAN_UART_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) -#define MXC_F_IOMAN_UART_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) -#define MXC_F_IOMAN_UART_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) -#define MXC_F_IOMAN_UART_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) - -#define MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) -#define MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) - -#define MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) -#define MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM_ACK_SR0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) -#define MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_IOMAN_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/maa_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/maa_regs.h deleted file mode 100644 index e428b7535a..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/maa_regs.h +++ /dev/null @@ -1,161 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_MAA_REGS_H_ -#define _MXC_MAA_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t ctrl; /* 0x0000 MAA Control, Configuration and Status */ - __IO uint32_t maws; /* 0x0004 MAA Word (Operand) Size, Big/Little Endian Mode Select */ -} mxc_maa_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t seg0[32]; /* 0x0000-0x007C [128 bytes] MAA Memory Segment 0 */ - __IO uint32_t seg1[32]; /* 0x0080-0x00FC [128 bytes] MAA Memory Segment 1 */ - __IO uint32_t seg2[32]; /* 0x0100-0x017C [128 bytes] MAA Memory Segment 2 */ - __IO uint32_t seg3[32]; /* 0x0180-0x01FC [128 bytes] MAA Memory Segment 3 */ - __IO uint32_t seg4[32]; /* 0x0200-0x027C [128 bytes] MAA Memory Segment 4 */ - __IO uint32_t seg5[32]; /* 0x0280-0x02FC [128 bytes] MAA Memory Segment 5 */ -} mxc_maa_mem_regs_t; - - -/* - Register offsets for module MAA. -*/ - -#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) -#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) -#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000080UL) -#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000100UL) -#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x00000180UL) -#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000200UL) -#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000280UL) - - -/* - Field positions and masks for module MAA. -*/ - -#define MXC_F_MAA_CTRL_START_POS 0 -#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) -#define MXC_F_MAA_CTRL_OPSEL_POS 1 -#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) -#define MXC_F_MAA_CTRL_OCALC_POS 4 -#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) -#define MXC_F_MAA_CTRL_IF_DONE_POS 5 -#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) -#define MXC_F_MAA_CTRL_INTEN_POS 6 -#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) -#define MXC_F_MAA_CTRL_IF_ERROR_POS 7 -#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) -#define MXC_F_MAA_CTRL_OFS_A_POS 8 -#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) -#define MXC_F_MAA_CTRL_OFS_B_POS 10 -#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) -#define MXC_F_MAA_CTRL_OFS_EXP_POS 12 -#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) -#define MXC_F_MAA_CTRL_OFS_MOD_POS 14 -#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) -#define MXC_F_MAA_CTRL_SEG_A_POS 16 -#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) -#define MXC_F_MAA_CTRL_SEG_B_POS 20 -#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) -#define MXC_F_MAA_CTRL_SEG_RES_POS 24 -#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) -#define MXC_F_MAA_CTRL_SEG_TMP_POS 28 -#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) - -#define MXC_F_MAA_MAWS_MODLEN_POS 0 -#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) -#define MXC_F_MAA_MAWS_BYTESWAP_POS 15 -#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) - - - -/* - Field values and shifted values for module MAA. -*/ - -#define MXC_V_MAA_OPSEL_EXP ((uint32_t)(0x00000000UL)) -#define MXC_V_MAA_OPSEL_SQR ((uint32_t)(0x00000001UL)) -#define MXC_V_MAA_OPSEL_MUL ((uint32_t)(0x00000002UL)) -#define MXC_V_MAA_OPSEL_SQRMUL ((uint32_t)(0x00000003UL)) -#define MXC_V_MAA_OPSEL_ADD ((uint32_t)(0x00000004UL)) -#define MXC_V_MAA_OPSEL_SUB ((uint32_t)(0x00000005UL)) - -#define MXC_S_MAA_OPSEL_EXP ((uint32_t)(MXC_V_MAA_OPSEL_EXP << MXC_F_MAA_CTRL_OPSEL_POS)) -#define MXC_S_MAA_OPSEL_SQR ((uint32_t)(MXC_V_MAA_OPSEL_SQR << MXC_F_MAA_CTRL_OPSEL_POS)) -#define MXC_S_MAA_OPSEL_MUL ((uint32_t)(MXC_V_MAA_OPSEL_MUL << MXC_F_MAA_CTRL_OPSEL_POS)) -#define MXC_S_MAA_OPSEL_SQRMUL ((uint32_t)(MXC_V_MAA_OPSEL_SQRMUL << MXC_F_MAA_CTRL_OPSEL_POS)) -#define MXC_S_MAA_OPSEL_ADD ((uint32_t)(MXC_V_MAA_OPSEL_ADD << MXC_F_MAA_CTRL_OPSEL_POS)) -#define MXC_S_MAA_OPSEL_SUB ((uint32_t)(MXC_V_MAA_OPSEL_SUB << MXC_F_MAA_CTRL_OPSEL_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_MAA_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/max32620.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/max32620.h deleted file mode 100644 index ead35a0db2..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/max32620.h +++ /dev/null @@ -1,766 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MAX32620_H_ -#define _MAX32620_H_ - -#include - -#ifndef FALSE -#define FALSE (0) -#endif - -#ifndef TRUE -#define TRUE (1) -#endif - -/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ -#if defined ( __GNUC__ ) -#define __weak __attribute__((weak)) -#endif /* __GNUC__ */ - -typedef enum { - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - - /* Device-specific interrupt sources (external to ARM core) */ - /* table entry number */ - /* |||| */ - /* |||| table offset address */ - /* vvvv vvvvvv */ - - CLKMAN_IRQn = 0, /* 0x10 0x0040 CLKMAN */ - PWRMAN_IRQn, /* 0x11 0x0044 PWRMAN */ - FLC_IRQn, /* 0x12 0x0048 Flash Controller */ - RTC0_IRQn, /* 0x13 0x004C RTC Counter match with Compare 0 */ - RTC1_IRQn, /* 0x14 0x0050 RTC Counter match with Compare 1 */ - RTC2_IRQn, /* 0x15 0x0054 RTC Prescaler interval compare match */ - RTC3_IRQn, /* 0x16 0x0058 RTC Overflow */ - PMU_IRQn, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */ - USB_IRQn, /* 0x18 0x0060 USB */ - AES_IRQn, /* 0x19 0x0064 AES */ - MAA_IRQn, /* 0x1A 0x0068 MAA */ - WDT0_IRQn, /* 0x1B 0x006C Watchdog 0 timeout */ - WDT0_P_IRQn, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */ - WDT1_IRQn, /* 0x1D 0x0074 Watchdog 1 timeout */ - WDT1_P_IRQn, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */ - GPIO_P0_IRQn, /* 0x1F 0x007C GPIO Port 0 */ - GPIO_P1_IRQn, /* 0x20 0x0080 GPIO Port 1 */ - GPIO_P2_IRQn, /* 0x21 0x0084 GPIO Port 2 */ - GPIO_P3_IRQn, /* 0x22 0x0088 GPIO Port 3 */ - GPIO_P4_IRQn, /* 0x23 0x008C GPIO Port 4 */ - GPIO_P5_IRQn, /* 0x24 0x0090 GPIO Port 5 */ - GPIO_P6_IRQn, /* 0x25 0x0094 GPIO Port 6 */ - TMR0_0_IRQn, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */ - TMR0_1_IRQn, /* 0x27 0x009C Timer 0 (16-bit #1) */ - TMR1_0_IRQn, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */ - TMR1_1_IRQn, /* 0x29 0x00A4 Timer 1 (16-bit #1) */ - TMR2_0_IRQn, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */ - TMR2_1_IRQn, /* 0x2B 0x00AC Timer 2 (16-bit #1) */ - TMR3_0_IRQn, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */ - TMR3_1_IRQn, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */ - TMR4_0_IRQn, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */ - TMR4_1_IRQn, /* 0x2F 0x00BC Timer 4 (16-bit #1) */ - TMR5_0_IRQn, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */ - TMR5_1_IRQn, /* 0x31 0x00C4 Timer 5 (16-bit #1) */ - UART0_IRQn, /* 0x32 0x00C8 UART 0 */ - UART1_IRQn, /* 0x33 0x00CC UART 1 */ - UART2_IRQn, /* 0x34 0x00D0 UART 2 */ - UART3_IRQn, /* 0x35 0x00D4 UART 3 */ - PT_IRQn, /* 0x36 0x00D8 Pulse Trains */ - I2CM0_IRQn, /* 0x37 0x00DC I2C Master 0 */ - I2CM1_IRQn, /* 0x38 0x00E0 I2C Master 1 */ - I2CM2_IRQn, /* 0x39 0x00E4 I2C Master 2 */ - I2CS0_IRQn, /* 0x3A 0x00E8 I2C Slave */ - SPI0_IRQn, /* 0x3B 0x00EC SPI Master 0 */ - SPI1_IRQn, /* 0x3C 0x00F0 SPI Master 1 */ - SPI2_IRQn, /* 0x3D 0x00F4 SPI Master 2 */ - SPIB_IRQn, /* 0x3E 0x00F8 SPI Bridge */ - OWM_IRQn, /* 0x3F 0x00FC 1-Wire Master */ - AFE_IRQn, /* 0x40 0x0100 Analog Front End, ADC */ - MXC_IRQ_EXT_COUNT, -} IRQn_Type; - -#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ -#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 1 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ - -#include /*!< Cortex-M4 processor and core peripherals */ -#include "system_max32620.h" /*!< System Header */ - - -/* ================================================================================ */ -/* ================== Device Specific Memory Section ================== */ -/* ================================================================================ */ - -#define MXC_FLASH_MEM_BASE 0x00000000UL -#define MXC_FLASH_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_MEM_SIZE 0x00100000UL -#define MXC_SYS_MEM_BASE 0x20000000UL - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/* - Base addresses and configuration settings for all MAX32620 peripheral modules. -*/ - - -/*******************************************************************************/ -/* System Clock Manager */ - -#define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL) -#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) - - - -/*******************************************************************************/ -/* System Power Manager */ - -#define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL) -#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) - - - -/*******************************************************************************/ -/* Real Time Clock */ - -#define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL) -#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) -#define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL) -#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) - -#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \ - i == 1 ? RTC1_IRQn : \ - i == 2 ? RTC2_IRQn : \ - i == 3 ? RTC3_IRQn : 0) - - - -/*******************************************************************************/ -/* Power Sequencer */ - -#define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL) -#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) - - - -/*******************************************************************************/ -/* System I/O Manager */ - -#define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL) -#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) - - - -/*******************************************************************************/ -/* Shadow Trim Registers */ - -#define MXC_BASE_TRIM ((uint32_t)0x40001000UL) -#define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM) - - - -/*******************************************************************************/ -/* Flash Controller */ - -#define MXC_BASE_FLC ((uint32_t)0x40002000UL) -#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) - -#define MXC_FLC_PAGE_SIZE_SHIFT (13) -#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) -#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT - - - -/*******************************************************************************/ -/* Instruction Cache */ - -#define MXC_BASE_ICC ((uint32_t)0x40003000UL) -#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) - - - -/*******************************************************************************/ -/* SPI XIP Interface */ - -#define MXC_BASE_SPIX ((uint32_t)0x40004000UL) -#define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX) - - - -/*******************************************************************************/ -/* Peripheral Management Unit */ - -#define MXC_CFG_PMU_CHANNELS (6) - -#define MXC_BASE_PMU0 ((uint32_t)0x40005000UL) -#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) -#define MXC_BASE_PMU1 ((uint32_t)0x40005020UL) -#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) -#define MXC_BASE_PMU2 ((uint32_t)0x40005040UL) -#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) -#define MXC_BASE_PMU3 ((uint32_t)0x40005060UL) -#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) -#define MXC_BASE_PMU4 ((uint32_t)0x40005080UL) -#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) -#define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL) -#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) - -#define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \ - (i) == 1 ? MXC_BASE_PMU1 : \ - (i) == 2 ? MXC_BASE_PMU2 : \ - (i) == 3 ? MXC_BASE_PMU3 : \ - (i) == 4 ? MXC_BASE_PMU4 : \ - (i) == 5 ? MXC_BASE_PMU5 : 0) - -#define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \ - (i) == 1 ? MXC_PMU1 : \ - (i) == 2 ? MXC_PMU2 : \ - (i) == 3 ? MXC_PMU3 : \ - (i) == 4 ? MXC_PMU4 : \ - (i) == 5 ? MXC_PMU5 : 0) - -#define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \ - (p) == MXC_PMU1 ? 1 : \ - (p) == MXC_PMU2 ? 2 : \ - (p) == MXC_PMU3 ? 3 : \ - (p) == MXC_PMU4 ? 4 : \ - (p) == MXC_PMU5 ? 5 : -1) - - -/*******************************************************************************/ - - - - -/*******************************************************************************/ -/* USB Device Controller */ - -#define MXC_BASE_USB ((uint32_t)0x40100000UL) -#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) - -#define MXC_USB_MAX_PACKET (64) -#define MXC_USB_NUM_EP (8) - - - -/*******************************************************************************/ -/* CRC-16/CRC-32 Engine */ - -#define MXC_BASE_CRC ((uint32_t)0x40006000UL) -#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) -#define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL) -#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) - - - -/*******************************************************************************/ -/* Trust Protection Unit (TPU) */ - -#define MXC_BASE_TPU ((uint32_t)0x40007000UL) -#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) -#define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL) -#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) - - - -/*******************************************************************************/ -/* AES Cryptographic Engine */ - -#define MXC_BASE_AES ((uint32_t)0x40007400UL) -#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) -#define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL) -#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) - - - -/*******************************************************************************/ -/* MAA Cryptographic Engine */ - -#define MXC_BASE_MAA ((uint32_t)0x40007800UL) -#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) -#define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL) -#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) - - - -/*******************************************************************************/ -/* Watchdog Timers */ - -#define MXC_CFG_WDT_INSTANCES (2) - -#define MXC_BASE_WDT0 ((uint32_t)0x40008000UL) -#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) -#define MXC_BASE_WDT1 ((uint32_t)0x40009000UL) -#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) - -#define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \ - (i) == 1 ? WDT1_IRQn : 0) - -#define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \ - (i) == 1 ? WDT1_P_IRQn : 0) - -#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ - (i) == 1 ? MXC_BASE_WDT1 : 0) - -#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ - (i) == 1 ? MXC_WDT1 : 0) - -#define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: (i) == MXC_WDT1 ? 1: -1) - - - -/*******************************************************************************/ -/* General Purpose I/O Ports (GPIO) */ - -#define MXC_GPIO_NUM_PORTS (7) -#define MXC_GPIO_MAX_PINS_PER_PORT (8) - -#define MXC_BASE_GPIO ((uint32_t)0x4000A000UL) -#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) - -#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO_P0_IRQn : \ - (i) == 1 ? GPIO_P1_IRQn : \ - (i) == 2 ? GPIO_P2_IRQn : \ - (i) == 3 ? GPIO_P3_IRQn : \ - (i) == 4 ? GPIO_P4_IRQn : \ - (i) == 5 ? GPIO_P5_IRQn : \ - (i) == 6 ? GPIO_P6_IRQn : 0) - - - -/*******************************************************************************/ -/* 16/32 bit Timer/Counters */ - -#define MXC_CFG_TMR_INSTANCES (6) - -#define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL) -#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) -#define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL) -#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) -#define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL) -#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) -#define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL) -#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) -#define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL) -#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) -#define MXC_BASE_TMR5 ((uint32_t)0x40010000UL) -#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) - -#define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_0_IRQn : \ - (i) == 1 ? TMR1_0_IRQn : \ - (i) == 2 ? TMR2_0_IRQn : \ - (i) == 3 ? TMR3_0_IRQn : \ - (i) == 4 ? TMR4_0_IRQn : \ - (i) == 5 ? TMR5_0_IRQn : 0) - -#define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_0_IRQn : \ - (i) == 1 ? TMR1_0_IRQn : \ - (i) == 2 ? TMR2_0_IRQn : \ - (i) == 3 ? TMR3_0_IRQn : \ - (i) == 4 ? TMR4_0_IRQn : \ - (i) == 5 ? TMR5_0_IRQn : \ - (i) == 6 ? TMR0_1_IRQn : \ - (i) == 7 ? TMR1_1_IRQn : \ - (i) == 8 ? TMR2_1_IRQn : \ - (i) == 9 ? TMR3_1_IRQn : \ - (i) == 10 ? TMR4_1_IRQn : \ - (i) == 11 ? TMR5_1_IRQn : 0) - -#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ - (i) == 1 ? MXC_BASE_TMR1 : \ - (i) == 2 ? MXC_BASE_TMR2 : \ - (i) == 3 ? MXC_BASE_TMR3 : \ - (i) == 4 ? MXC_BASE_TMR4 : \ - (i) == 5 ? MXC_BASE_TMR5 : 0) - -#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ - (i) == 1 ? MXC_TMR1 : \ - (i) == 2 ? MXC_TMR2 : \ - (i) == 3 ? MXC_TMR3 : \ - (i) == 4 ? MXC_TMR4 : \ - (i) == 5 ? MXC_TMR5 : 0) - -#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ - (p) == MXC_TMR1 ? 1 : \ - (p) == MXC_TMR2 ? 2 : \ - (p) == MXC_TMR3 ? 3 : \ - (p) == MXC_TMR4 ? 4 : \ - (p) == MXC_TMR5 ? 5 : -1) - - - - -/*******************************************************************************/ -/* Pulse Train Generation */ - -#define MXC_CFG_PT_INSTANCES (16) - -#define MXC_BASE_PTG ((uint32_t)0x40011000UL) -#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) -#define MXC_BASE_PT0 ((uint32_t)0x40011010UL) -#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) -#define MXC_BASE_PT1 ((uint32_t)0x4001101CUL) -#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) -#define MXC_BASE_PT2 ((uint32_t)0x40011028UL) -#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) -#define MXC_BASE_PT3 ((uint32_t)0x40011034UL) -#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) -#define MXC_BASE_PT4 ((uint32_t)0x40011040UL) -#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) -#define MXC_BASE_PT5 ((uint32_t)0x4001104CUL) -#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) -#define MXC_BASE_PT6 ((uint32_t)0x40011058UL) -#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) -#define MXC_BASE_PT7 ((uint32_t)0x40011064UL) -#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) -#define MXC_BASE_PT8 ((uint32_t)0x40011070UL) -#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8) -#define MXC_BASE_PT9 ((uint32_t)0x4001107CUL) -#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9) -#define MXC_BASE_PT10 ((uint32_t)0x40011088UL) -#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10) -#define MXC_BASE_PT11 ((uint32_t)0x40011094UL) -#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11) -#define MXC_BASE_PT12 ((uint32_t)0x400110A0UL) -#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12) -#define MXC_BASE_PT13 ((uint32_t)0x400110ACUL) -#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13) -#define MXC_BASE_PT14 ((uint32_t)0x400110B8UL) -#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14) -#define MXC_BASE_PT15 ((uint32_t)0x400110C4UL) -#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15) - -#define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \ - (i) == 1 ? MXC_BASE_PT1 : \ - (i) == 2 ? MXC_BASE_PT2 : \ - (i) == 3 ? MXC_BASE_PT3 : \ - (i) == 4 ? MXC_BASE_PT4 : \ - (i) == 5 ? MXC_BASE_PT5 : \ - (i) == 6 ? MXC_BASE_PT6 : \ - (i) == 7 ? MXC_BASE_PT7 : \ - (i) == 8 ? MXC_BASE_PT8 : \ - (i) == 9 ? MXC_BASE_PT9 : \ - (i) == 10 ? MXC_BASE_PT10 : \ - (i) == 11 ? MXC_BASE_PT11 : \ - (i) == 12 ? MXC_BASE_PT12 : \ - (i) == 13 ? MXC_BASE_PT13 : \ - (i) == 14 ? MXC_BASE_PT14 : \ - (i) == 15 ? MXC_BASE_PT15 : 0) - -#define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \ - (i) == 1 ? MXC_PT1 : \ - (i) == 2 ? MXC_PT2 : \ - (i) == 3 ? MXC_PT3 : \ - (i) == 4 ? MXC_PT4 : \ - (i) == 5 ? MXC_PT5 : \ - (i) == 6 ? MXC_PT6 : \ - (i) == 7 ? MXC_PT7 : \ - (i) == 8 ? MXC_PT8 : \ - (i) == 9 ? MXC_PT9 : \ - (i) == 10 ? MXC_PT10 : \ - (i) == 11 ? MXC_PT11 : \ - (i) == 12 ? MXC_PT12 : \ - (i) == 13 ? MXC_PT13 : \ - (i) == 14 ? MXC_PT14 : \ - (i) == 15 ? MXC_PT15 : 0) - -#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \ - (p) == MXC_PT1 ? 1 : \ - (p) == MXC_PT2 ? 2 : \ - (p) == MXC_PT3 ? 3 : \ - (p) == MXC_PT4 ? 4 : \ - (p) == MXC_PT5 ? 5 : \ - (p) == MXC_PT6 ? 6 : \ - (p) == MXC_PT7 ? 7 : \ - (p) == MXC_PT8 ? 8 : \ - (p) == MXC_PT9 ? 9 : \ - (p) == MXC_PT10 ? 10 : \ - (p) == MXC_PT11 ? 11 : \ - (p) == MXC_PT12 ? 12 : \ - (p) == MXC_PT13 ? 13 : \ - (p) == MXC_PT14 ? 14 : \ - (p) == MXC_PT15 ? 15 : -1) - - - -/*******************************************************************************/ -/* UART / Serial Port Interface */ - -#define MXC_CFG_UART_INSTANCES (4) -#define MXC_UART_FIFO_DEPTH (32) - -#define MXC_BASE_UART0 ((uint32_t)0x40012000UL) -#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) -#define MXC_BASE_UART1 ((uint32_t)0x40013000UL) -#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) -#define MXC_BASE_UART2 ((uint32_t)0x40014000UL) -#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) -#define MXC_BASE_UART3 ((uint32_t)0x40015000UL) -#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) -#define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL) -#define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO) -#define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL) -#define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO) -#define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL) -#define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO) -#define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL) -#define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO) - -#define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \ - (i) == 1 ? UART1_IRQn : \ - (i) == 2 ? UART2_IRQn : \ - (i) == 3 ? UART3_IRQn : 0) - -#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ - (i) == 1 ? MXC_BASE_UART1 : \ - (i) == 2 ? MXC_BASE_UART2 : \ - (i) == 3 ? MXC_BASE_UART3 : 0) - -#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ - (i) == 1 ? MXC_UART1 : \ - (i) == 2 ? MXC_UART2 : \ - (i) == 3 ? MXC_UART3 : 0) - -#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ - (p) == MXC_UART1 ? 1 : \ - (p) == MXC_UART2 ? 2 : \ - (p) == MXC_UART3 ? 3 : -1) - -#define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \ - (i) == 1 ? MXC_BASE_UART1_FIFO : \ - (i) == 2 ? MXC_BASE_UART2_FIFO : \ - (i) == 3 ? MXC_BASE_UART3_FIFO : 0) - -#define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \ - (i) == 1 ? MXC_UART1_FIFO : \ - (i) == 2 ? MXC_UART2_FIFO : \ - (i) == 3 ? MXC_UART3_FIFO : 0) - - - -/*******************************************************************************/ -/* I2C Master Interface */ - -#define MXC_CFG_I2CM_INSTANCES (3) -#define MXC_I2CM_FIFO_DEPTH (8) - -#define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL) -#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) -#define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL) -#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) -#define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL) -#define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2) -#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL) -#define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO) -#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL) -#define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO) -#define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL) -#define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO) - -#define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \ - (i) == 1 ? I2CM1_IRQn : \ - (i) == 2 ? I2CM2_IRQn : 0) - -#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ - (i) == 1 ? MXC_BASE_I2CM1 : \ - (i) == 2 ? MXC_BASE_I2CM2 : 0) - -#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ - (i) == 1 ? MXC_I2CM1 : \ - (i) == 2 ? MXC_I2CM2 : 0) - -#define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \ - (p) == MXC_I2CM1 ? 1 : \ - (p) == MXC_I2CM2 ? 2 : -1) - -#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \ - (i) == 1 ? MXC_BASE_I2CM1_FIFO : \ - (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0) - -#define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \ - (i) == 1 ? MXC_I2CM1_FIFO : \ - (i) == 2 ? MXC_I2CM2_FIFO : 0) - - - -/*******************************************************************************/ -/* I2C Slave Interface (Mailbox type) */ - -#define MXC_BASE_I2CS ((uint32_t)0x40019000UL) -#define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS) - - - -/*******************************************************************************/ -/* SPI Master Interface */ - -#define MXC_CFG_SPI_INSTANCES (3) -#define MXC_CFG_SPI_FIFO_DEPTH (16) - -#define MXC_BASE_SPI0 ((uint32_t)0x4001A000UL) -#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) -#define MXC_BASE_SPI1 ((uint32_t)0x4001B000UL) -#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) -#define MXC_BASE_SPI2 ((uint32_t)0x4001C000UL) -#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) -#define MXC_BASE_SPI0_FIFO ((uint32_t)0x4010A000UL) -#define MXC_SPI0_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI0_FIFO) -#define MXC_BASE_SPI1_FIFO ((uint32_t)0x4010B000UL) -#define MXC_SPI1_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI1_FIFO) -#define MXC_BASE_SPI2_FIFO ((uint32_t)0x4010C000UL) -#define MXC_SPI2_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI2_FIFO) - -#define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \ - (i) == 1 ? SPI1_IRQn : \ - (i) == 2 ? SPI2_IRQn : 0) - -#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \ - (i) == 1 ? MXC_BASE_SPI1 : \ - (i) == 2 ? MXC_BASE_SPI2 : 0) - -#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \ - (i) == 1 ? MXC_SPI1 : \ - (i) == 2 ? MXC_SPI2 : 0) - -#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : \ - (p) == MXC_SPI1 ? 1 : \ - (p) == MXC_SPI2 ? 2 : -1) - -#define MXC_SPI_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPI0_FIFO : \ - (i) == 1 ? MXC_BASE_SPI1_FIFO : \ - (i) == 2 ? MXC_BASE_SPI2_FIFO : 0) - -#define MXC_SPI_GET_SPI_FIFO(i) ((i) == 0 ? MXC_SPI0_FIFO : \ - (i) == 1 ? MXC_SPI1_FIFO : \ - (i) == 2 ? MXC_SPI2_FIFO : 0) - - - -/*******************************************************************************/ -/* 1-Wire Master Interface */ - -#define MXC_BASE_OWM ((uint32_t)0x4001E000UL) -#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) - - - -/*******************************************************************************/ -/* ADC / AFE */ - -#define MXC_CFG_ADC_FIFO_DEPTH (32) - -#define MXC_BASE_ADC ((uint32_t)0x4001F000UL) -#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) - - - -/*******************************************************************************/ -/* SPIB AHB-to-SPI Bridge */ - -#define MXC_BASE_SPIB ((uint32_t)0x4000D000UL) -#define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB) - - - -/*******************************************************************************/ -/* Bit Shifting */ - -#define MXC_F_BIT_0 (1 << 0) -#define MXC_F_BIT_1 (1 << 1) -#define MXC_F_BIT_2 (1 << 2) -#define MXC_F_BIT_3 (1 << 3) -#define MXC_F_BIT_4 (1 << 4) -#define MXC_F_BIT_5 (1 << 5) -#define MXC_F_BIT_6 (1 << 6) -#define MXC_F_BIT_7 (1 << 7) -#define MXC_F_BIT_8 (1 << 8) -#define MXC_F_BIT_9 (1 << 9) -#define MXC_F_BIT_10 (1 << 10) -#define MXC_F_BIT_11 (1 << 11) -#define MXC_F_BIT_12 (1 << 12) -#define MXC_F_BIT_13 (1 << 13) -#define MXC_F_BIT_14 (1 << 14) -#define MXC_F_BIT_15 (1 << 15) -#define MXC_F_BIT_16 (1 << 16) -#define MXC_F_BIT_17 (1 << 17) -#define MXC_F_BIT_18 (1 << 18) -#define MXC_F_BIT_19 (1 << 19) -#define MXC_F_BIT_20 (1 << 20) -#define MXC_F_BIT_21 (1 << 21) -#define MXC_F_BIT_22 (1 << 22) -#define MXC_F_BIT_23 (1 << 23) -#define MXC_F_BIT_24 (1 << 24) -#define MXC_F_BIT_25 (1 << 25) -#define MXC_F_BIT_26 (1 << 26) -#define MXC_F_BIT_27 (1 << 27) -#define MXC_F_BIT_28 (1 << 28) -#define MXC_F_BIT_29 (1 << 29) -#define MXC_F_BIT_30 (1 << 30) -#define MXC_F_BIT_31 (1 << 31) - - -/*******************************************************************************/ - -#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) -#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) -#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) -#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) - -#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set)) - - - -#endif /* _MAX32620_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/owm_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/owm_regs.h deleted file mode 100644 index 2f941c3c04..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/owm_regs.h +++ /dev/null @@ -1,153 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_OWM_REGS_H_ -#define _MXC_OWM_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t cfg; /* 0x0000 1-Wire Master Configuration */ - __IO uint32_t clk_div_1us; /* 0x0004 1-Wire Master Clock Divisor */ - __IO uint32_t ctrl_stat; /* 0x0008 1-Wire Master Control/Status */ - __IO uint32_t data; /* 0x000C 1-Wire Master Data Buffer */ - __IO uint32_t intfl; /* 0x0010 1-Wire Master Interrupt Flags */ - __IO uint32_t inten; /* 0x0014 1-Wire Master Interrupt Enables */ -} mxc_owm_regs_t; - - -/* - Register offsets for module OWM. -*/ - -#define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) -#define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) -#define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) -#define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) -#define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) -#define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) - - -/* - Field positions and masks for module OWM. -*/ - -#define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 -#define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) -#define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 -#define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) -#define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 -#define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) -#define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 -#define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) -#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 -#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) -#define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 -#define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) -#define MXC_F_OWM_CFG_OVERDRIVE_POS 6 -#define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) -#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 -#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) - -#define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 -#define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) - -#define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 -#define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) -#define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 -#define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) -#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 -#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) -#define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 -#define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) -#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 -#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) - -#define MXC_F_OWM_DATA_TX_RX_POS 0 -#define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) - -#define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 -#define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) -#define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 -#define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) -#define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 -#define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) -#define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 -#define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) -#define MXC_F_OWM_INTFL_LINE_LOW_POS 4 -#define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) - -#define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 -#define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) -#define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 -#define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) -#define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 -#define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) -#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 -#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) -#define MXC_F_OWM_INTEN_LINE_LOW_POS 4 -#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_OWM_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h deleted file mode 100644 index 2055a9684a..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h +++ /dev/null @@ -1,148 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_PMU_REGS_H_ -#define _MXC_PMU_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -typedef struct { - __IO uint32_t start_opcode[32]; - __IO uint32_t enable; - __IO uint32_t rsvd0; - __IO uint32_t ll_stopped; - __IO uint32_t manual; - __IO uint32_t bus_error; - __IO uint32_t rsvd1; - __IO uint32_t to_stat; - __IO uint32_t rsvd2[4]; - __IO uint32_t to_sel[3]; - __IO uint32_t ps_sel[2]; - __IO uint32_t interrupt; - __IO uint32_t int_enable; - __IO uint32_t rsvd3[6]; - __IO uint32_t burst_size[5]; - __IO uint32_t rsvd4[3]; - __IO uint32_t padding[192]; /* Offset to next channel */ -} mxc_pmu_bits_t; - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t dscadr; /* 0x0000 PMU Channel Next Descriptor Address */ - __IO uint32_t cfg; /* 0x0004 PMU Channel Configuration */ - __IO uint32_t loop; /* 0x0008 PMU Channel Loop Counters */ - __IO uint32_t op; /* 0x000C PMU Channel Current Descriptor DWORD 0 [INTERNAL TEST ONLY] */ - __IO uint32_t dsc1; /* 0x0010 PMU Channel Current Descriptor DWORD 1 [INTERNAL TEST ONLY] */ - __IO uint32_t dsc2; /* 0x0014 PMU Channel Current Descriptor DWORD 2 [INTERNAL TEST ONLY] */ - __IO uint32_t dsc3; /* 0x0018 PMU Channel Current Descriptor DWORD 3 [INTERNAL TEST ONLY] */ - __IO uint32_t dsc4; /* 0x001C PMU Channel Current Descriptor DWORD 4 [INTERNAL TEST ONLY] */ -} mxc_pmu_regs_t; - - -/* - Register offsets for module PMU. -*/ - -#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) -#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) -#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) -#define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL) -#define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL) -#define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL) -#define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL) -#define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL) - - -/* - Field positions and masks for module PMU. -*/ - -#define MXC_F_PMU_CFG_ENABLE_POS 0 -#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS)) -#define MXC_F_PMU_CFG_LL_STOPPED_POS 2 -#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS)) -#define MXC_F_PMU_CFG_MANUAL_POS 3 -#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS)) -#define MXC_F_PMU_CFG_BUS_ERROR_POS 4 -#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS)) -#define MXC_F_PMU_CFG_TO_STAT_POS 6 -#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS)) -#define MXC_F_PMU_CFG_TO_SEL_POS 11 -#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS)) -#define MXC_F_PMU_CFG_PS_SEL_POS 14 -#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS)) -#define MXC_F_PMU_CFG_INTERRUPT_POS 16 -#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS)) -#define MXC_F_PMU_CFG_INT_EN_POS 17 -#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS)) -#define MXC_F_PMU_CFG_BURST_SIZE_POS 24 -#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS)) - -#define MXC_F_PMU_LOOP_COUNTER_0_POS 0 -#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS)) -#define MXC_F_PMU_LOOP_COUNTER_1_POS 16 -#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_PMU_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/pt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/pt_regs.h deleted file mode 100644 index c55606ea49..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/pt_regs.h +++ /dev/null @@ -1,314 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_PT_REGS_H_ -#define _MXC_PT_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t enable; /* 0x0000 Global Enable/Disable Controls for All Pulse Trains */ - __IO uint32_t resync; /* 0x0004 Global Resync (All Pulse Trains) Control */ - __IO uint32_t intfl; /* 0x0008 Pulse Train Interrupt Flags */ - __IO uint32_t inten; /* 0x000C Pulse Train Interrupt Enable/Disable */ -} mxc_ptg_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t rate_length; /* 0x0000 Pulse Train Configuration */ - __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */ - __IO uint32_t loop; /* 0x0008 Pulse Train Loop Count */ -} mxc_pt_regs_t; - - -/* - Register offsets for module PT. -*/ - -#define MXC_R_PTG_OFFS_ENABLE ((uint32_t)0x00000000UL) -#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) -#define MXC_R_PTG_OFFS_INTFL ((uint32_t)0x00000008UL) -#define MXC_R_PTG_OFFS_INTEN ((uint32_t)0x0000000CUL) -#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) -#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) -#define MXC_R_PT_OFFS_LOOP ((uint32_t)0x00000008UL) - - -/* - Field positions and masks for module PT. -*/ - -#define MXC_F_PT_ENABLE_PT0_POS 0 -#define MXC_F_PT_ENABLE_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT0_POS)) -#define MXC_F_PT_ENABLE_PT1_POS 1 -#define MXC_F_PT_ENABLE_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT1_POS)) -#define MXC_F_PT_ENABLE_PT2_POS 2 -#define MXC_F_PT_ENABLE_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT2_POS)) -#define MXC_F_PT_ENABLE_PT3_POS 3 -#define MXC_F_PT_ENABLE_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT3_POS)) -#define MXC_F_PT_ENABLE_PT4_POS 4 -#define MXC_F_PT_ENABLE_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT4_POS)) -#define MXC_F_PT_ENABLE_PT5_POS 5 -#define MXC_F_PT_ENABLE_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT5_POS)) -#define MXC_F_PT_ENABLE_PT6_POS 6 -#define MXC_F_PT_ENABLE_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT6_POS)) -#define MXC_F_PT_ENABLE_PT7_POS 7 -#define MXC_F_PT_ENABLE_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT7_POS)) -#define MXC_F_PT_ENABLE_PT8_POS 8 -#define MXC_F_PT_ENABLE_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT8_POS)) -#define MXC_F_PT_ENABLE_PT9_POS 9 -#define MXC_F_PT_ENABLE_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT9_POS)) -#define MXC_F_PT_ENABLE_PT10_POS 10 -#define MXC_F_PT_ENABLE_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT10_POS)) -#define MXC_F_PT_ENABLE_PT11_POS 11 -#define MXC_F_PT_ENABLE_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT11_POS)) -#define MXC_F_PT_ENABLE_PT12_POS 12 -#define MXC_F_PT_ENABLE_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT12_POS)) -#define MXC_F_PT_ENABLE_PT13_POS 13 -#define MXC_F_PT_ENABLE_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT13_POS)) -#define MXC_F_PT_ENABLE_PT14_POS 14 -#define MXC_F_PT_ENABLE_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT14_POS)) -#define MXC_F_PT_ENABLE_PT15_POS 15 -#define MXC_F_PT_ENABLE_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT15_POS)) - -#define MXC_F_PT_RESYNC_PT0_POS 0 -#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) -#define MXC_F_PT_RESYNC_PT1_POS 1 -#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) -#define MXC_F_PT_RESYNC_PT2_POS 2 -#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) -#define MXC_F_PT_RESYNC_PT3_POS 3 -#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) -#define MXC_F_PT_RESYNC_PT4_POS 4 -#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) -#define MXC_F_PT_RESYNC_PT5_POS 5 -#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) -#define MXC_F_PT_RESYNC_PT6_POS 6 -#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) -#define MXC_F_PT_RESYNC_PT7_POS 7 -#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) -#define MXC_F_PT_RESYNC_PT8_POS 8 -#define MXC_F_PT_RESYNC_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT8_POS)) -#define MXC_F_PT_RESYNC_PT9_POS 9 -#define MXC_F_PT_RESYNC_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT9_POS)) -#define MXC_F_PT_RESYNC_PT10_POS 10 -#define MXC_F_PT_RESYNC_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT10_POS)) -#define MXC_F_PT_RESYNC_PT11_POS 11 -#define MXC_F_PT_RESYNC_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT11_POS)) -#define MXC_F_PT_RESYNC_PT12_POS 12 -#define MXC_F_PT_RESYNC_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT12_POS)) -#define MXC_F_PT_RESYNC_PT13_POS 13 -#define MXC_F_PT_RESYNC_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT13_POS)) -#define MXC_F_PT_RESYNC_PT14_POS 14 -#define MXC_F_PT_RESYNC_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT14_POS)) -#define MXC_F_PT_RESYNC_PT15_POS 15 -#define MXC_F_PT_RESYNC_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT15_POS)) - -#define MXC_F_PT_INTFL_PT0_POS 0 -#define MXC_F_PT_INTFL_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT0_POS)) -#define MXC_F_PT_INTFL_PT1_POS 1 -#define MXC_F_PT_INTFL_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT1_POS)) -#define MXC_F_PT_INTFL_PT2_POS 2 -#define MXC_F_PT_INTFL_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT2_POS)) -#define MXC_F_PT_INTFL_PT3_POS 3 -#define MXC_F_PT_INTFL_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT3_POS)) -#define MXC_F_PT_INTFL_PT4_POS 4 -#define MXC_F_PT_INTFL_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT4_POS)) -#define MXC_F_PT_INTFL_PT5_POS 5 -#define MXC_F_PT_INTFL_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT5_POS)) -#define MXC_F_PT_INTFL_PT6_POS 6 -#define MXC_F_PT_INTFL_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT6_POS)) -#define MXC_F_PT_INTFL_PT7_POS 7 -#define MXC_F_PT_INTFL_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT7_POS)) -#define MXC_F_PT_INTFL_PT8_POS 8 -#define MXC_F_PT_INTFL_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT8_POS)) -#define MXC_F_PT_INTFL_PT9_POS 9 -#define MXC_F_PT_INTFL_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT9_POS)) -#define MXC_F_PT_INTFL_PT10_POS 10 -#define MXC_F_PT_INTFL_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT10_POS)) -#define MXC_F_PT_INTFL_PT11_POS 11 -#define MXC_F_PT_INTFL_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT11_POS)) -#define MXC_F_PT_INTFL_PT12_POS 12 -#define MXC_F_PT_INTFL_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT12_POS)) -#define MXC_F_PT_INTFL_PT13_POS 13 -#define MXC_F_PT_INTFL_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT13_POS)) -#define MXC_F_PT_INTFL_PT14_POS 14 -#define MXC_F_PT_INTFL_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT14_POS)) -#define MXC_F_PT_INTFL_PT15_POS 15 -#define MXC_F_PT_INTFL_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT15_POS)) - -#define MXC_F_PT_INTEN_PT0_POS 0 -#define MXC_F_PT_INTEN_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT0_POS)) -#define MXC_F_PT_INTEN_PT1_POS 1 -#define MXC_F_PT_INTEN_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT1_POS)) -#define MXC_F_PT_INTEN_PT2_POS 2 -#define MXC_F_PT_INTEN_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT2_POS)) -#define MXC_F_PT_INTEN_PT3_POS 3 -#define MXC_F_PT_INTEN_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT3_POS)) -#define MXC_F_PT_INTEN_PT4_POS 4 -#define MXC_F_PT_INTEN_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT4_POS)) -#define MXC_F_PT_INTEN_PT5_POS 5 -#define MXC_F_PT_INTEN_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT5_POS)) -#define MXC_F_PT_INTEN_PT6_POS 6 -#define MXC_F_PT_INTEN_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT6_POS)) -#define MXC_F_PT_INTEN_PT7_POS 7 -#define MXC_F_PT_INTEN_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT7_POS)) -#define MXC_F_PT_INTEN_PT8_POS 8 -#define MXC_F_PT_INTEN_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT8_POS)) -#define MXC_F_PT_INTEN_PT9_POS 9 -#define MXC_F_PT_INTEN_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT9_POS)) -#define MXC_F_PT_INTEN_PT10_POS 10 -#define MXC_F_PT_INTEN_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT10_POS)) -#define MXC_F_PT_INTEN_PT11_POS 11 -#define MXC_F_PT_INTEN_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT11_POS)) -#define MXC_F_PT_INTEN_PT12_POS 12 -#define MXC_F_PT_INTEN_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT12_POS)) -#define MXC_F_PT_INTEN_PT13_POS 13 -#define MXC_F_PT_INTEN_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT13_POS)) -#define MXC_F_PT_INTEN_PT14_POS 14 -#define MXC_F_PT_INTEN_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT14_POS)) -#define MXC_F_PT_INTEN_PT15_POS 15 -#define MXC_F_PT_INTEN_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT15_POS)) - -#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 -#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) -#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 -#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) - - - -/* - Field values and shifted values for module PT. -*/ - -#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(0x00000000UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x00000001UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(0x00000002UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(0x00000003UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(0x00000004UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(0x00000005UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(0x00000006UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(0x00000007UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(0x00000008UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(0x00000009UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(0x0000000AUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(0x0000000BUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(0x0000000CUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(0x0000000DUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(0x0000000EUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(0x0000000FUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(0x00000010UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(0x00000011UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(0x00000012UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(0x00000013UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(0x00000014UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(0x00000015UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(0x00000016UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(0x00000017UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(0x00000018UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(0x00000019UL)) -#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(0x0000001AUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(0x0000001BUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(0x0000001CUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(0x0000001DUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(0x0000001EUL)) -#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(0x0000001FUL)) - -#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) -#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_PT_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/pwrman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/pwrman_regs.h deleted file mode 100644 index 4dc452d7dc..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/pwrman_regs.h +++ /dev/null @@ -1,371 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_PWRMAN_REGS_H_ -#define _MXC_PWRMAN_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/** - * @brief Defines PAD Modes for Wake Up Detection. - */ -typedef enum { - /** WUD Mode for Selected PAD = Clear/Activate */ - MXC_E_PWRMAN_PAD_MODE_CLEAR_SET, - /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */ - MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO, - /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */ - MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO, - /** WUD Mode for Selected PAD = No pad state change */ - MXC_E_PWRMAN_PAD_MODE_NONE -} mxc_pwrman_pad_mode_t; - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */ - __IO uint32_t intfl; /* 0x0004 Interrupt Flags */ - __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ - __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */ - __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */ - __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */ - __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */ - __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */ - __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */ - __I uint32_t rsv024[5]; /* 0x0024-0x0034 */ - __IO uint32_t die_type; /* 0x0038 Die Type ID Register */ - __IO uint32_t base_part_num; /* 0x003C Base Part Number */ - __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */ - __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */ - __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */ -} mxc_pwrman_regs_t; - - -/* - Register offsets for module PWRMAN. -*/ - -#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL) -#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL) -#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL) -#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL) -#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL) -#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL) -#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL) -#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL) -#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL) -#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL) -#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL) -#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL) -#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL) - - -/* - Field positions and masks for module PWRMAN. -*/ - -#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2 -#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3 -#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4 -#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5 -#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8 -#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9 -#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16 -#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17 -#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18 -#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19 -#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20 -#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21 -#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22 -#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS)) -#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31 -#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS)) - -#define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0 -#define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS)) -#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1 -#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS)) -#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2 -#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS)) -#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3 -#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS)) -#define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4 -#define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS)) - -#define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0 -#define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS)) -#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1 -#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS)) -#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2 -#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS)) -#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3 -#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS)) -#define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4 -#define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS)) - -#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0 -#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS)) -#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1 -#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS)) -#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2 -#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS)) -#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3 -#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS)) -#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4 -#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS)) - -#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0 -#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS)) -#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8 -#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS)) -#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12 -#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS)) -#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16 -#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS)) - -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS)) -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31 -#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS)) - -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS)) -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16 -#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS)) - -#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0 -#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS)) - -#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0 -#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS)) -#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4 -#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS)) - -#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0 -#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS)) -#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31 -#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS)) - -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS)) -#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28 -#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_PWRMAN_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/pwrseq_regs.h deleted file mode 100644 index dbe459f72e..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/pwrseq_regs.h +++ /dev/null @@ -1,322 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_PWRSEQ_REGS_H_ -#define _MXC_PWRSEQ_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ - __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ - __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ - __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ - __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */ - __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ - __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ - __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */ - __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ - __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ - __I uint32_t rsv028[2]; /* 0x0028-0x002C */ - __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */ - __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */ -} mxc_pwrseq_regs_t; - - -/* - Register offsets for module PWRSEQ. -*/ - -#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) -#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) -#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) -#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) -#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) -#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) -#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) -#define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL) -#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) -#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) -#define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL) -#define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL) - - -/* - Field positions and masks for module PWRSEQ. -*/ - -#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 -#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 -#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 -#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3 -#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4 -#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5 -#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6 -#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 -#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 -#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 -#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 -#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 -#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 -#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13 -#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15 -#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 -#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19 -#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21 -#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23 -#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24 -#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25 -#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26 -#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27 -#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS)) -#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28 -#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS)) - -#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0 -#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS)) -#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1 -#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS)) -#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2 -#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS)) -#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3 -#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS)) -#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4 -#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS)) - -#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0 -#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS)) -#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2 -#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS)) -#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4 -#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS)) -#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6 -#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS)) -#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8 -#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS)) - -#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 -#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) -#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3 -#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS)) -#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6 -#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) -#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8 -#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) -#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10 -#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS)) - -#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 -#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) -#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 -#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) -#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 -#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) -#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4 -#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS)) -#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5 -#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS)) -#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6 -#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS)) -#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7 -#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS)) - -#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 -#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) -#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9 -#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS)) -#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_POS 15 -#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_POS)) -#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21 -#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS)) - -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11 -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS)) -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20 -#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS)) - -#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0 -#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS)) - -#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 -#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 -#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2 -#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3 -#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4 -#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5 -#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6 -#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7 -#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8 -#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9 -#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10 -#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 -#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) -#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12 -#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) -#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13 -#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) -#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14 -#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) -#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15 -#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 -#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 -#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) -#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18 -#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS)) - -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12 -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13 -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14 -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15 -#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18 -#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS)) - -#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0 -#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS)) -#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1 -#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS)) -#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2 -#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS)) -#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3 -#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS)) -#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4 -#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS)) - -#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0 -#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS)) -#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4 -#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_PWRSEQ_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/rtc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/rtc_regs.h deleted file mode 100644 index 031631f9e8..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/rtc_regs.h +++ /dev/null @@ -1,241 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_RTC_REGS_H_ -#define _MXC_RTC_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */ - __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */ - __IO uint32_t comp[2]; /* 0x0008-0x000C RTC Time of Day Alarm [0..1] Compare Register */ - __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */ - __IO uint32_t snz_val; /* 0x0014 RTC Timer Alarm Snooze Value */ - __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */ - __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */ - __I uint32_t rsv020; /* 0x0020 */ - __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */ - __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */ - __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */ -} mxc_rtctmr_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t nano_cntr; /* 0x0000 Nano Oscillator Counter Read Register */ - __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */ - __I uint32_t rsv008; /* 0x0008 */ - __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */ -} mxc_rtccfg_regs_t; - - -/* - Register offsets for module RTC. -*/ - -#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) -#define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) -#define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) -#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) -#define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) -#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) -#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) -#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) -#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) -#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) -#define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) -#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) -#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) - - -/* - Field positions and masks for module RTC. -*/ - -#define MXC_F_RTC_CTRL_ENABLE_POS 0 -#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) -#define MXC_F_RTC_CTRL_CLEAR_POS 1 -#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) -#define MXC_F_RTC_CTRL_PENDING_POS 2 -#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) -#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 -#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) -#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 -#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) -#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 -#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) -#define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 -#define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) -#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 -#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 -#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 -#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 -#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 -#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 -#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 -#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 -#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 -#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 -#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 -#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 -#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 -#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 -#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) -#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 -#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) - -#define MXC_F_RTC_FLAGS_COMP0_POS 0 -#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) -#define MXC_F_RTC_FLAGS_COMP1_POS 1 -#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) -#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 -#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) -#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 -#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) -#define MXC_F_RTC_FLAGS_TRIM_POS 4 -#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) -#define MXC_F_RTC_FLAGS_SNOOZE_POS 5 -#define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) -#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 -#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) -#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 -#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) -#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 -#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) -#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 -#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) -#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 -#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) -#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 -#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) - -#define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 -#define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) - -#define MXC_F_RTC_INTEN_COMP0_POS 0 -#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) -#define MXC_F_RTC_INTEN_COMP1_POS 1 -#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) -#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 -#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) -#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 -#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) -#define MXC_F_RTC_INTEN_TRIM_POS 4 -#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) - -#define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 -#define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) - -#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 -#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) - -#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 -#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) -#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 -#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) -#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 -#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) - -#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 -#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) -#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 -#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) - -#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 -#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) - -#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 -#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) -#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 -#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) -#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 -#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) - -#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 -#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) -#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 -#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) -#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 -#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) -#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 -#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_RTC_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/spi_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/spi_regs.h deleted file mode 100644 index 86c948393a..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/spi_regs.h +++ /dev/null @@ -1,243 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_SPI_REGS_H_ -#define _MXC_SPI_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */ - __IO uint32_t ss_sr_polarity; /* 0x0004 SPI Master Polarity Control for SS and SR Signals */ - __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */ - __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */ - __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */ - __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */ - __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */ -} mxc_spi_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */ - __IO uint8_t trans_8[2048]; - __IO uint16_t trans_16[1024]; - __IO uint32_t trans_32[512]; - }; - union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */ - __IO uint8_t rslts_8[2048]; - __IO uint16_t rslts_16[1024]; - __IO uint32_t rslts_32[512]; - }; -} mxc_spi_fifo_regs_t; - - -/* - Register offsets for module SPI. -*/ - -#define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) -#define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) -#define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) -#define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) -#define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) -#define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL) -#define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL) -#define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) -#define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) - - -/* - Field positions and masks for module SPI. -*/ - -#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0 -#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS)) -#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3 -#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS)) -#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4 -#define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS)) -#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6 -#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)) -#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8 -#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS)) -#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12 -#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)) -#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16 -#define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS)) -#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18 -#define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS)) -#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20 -#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS)) -#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24 -#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS)) - -#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL) -#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL) -#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL) -#define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL) - -#define MXC_S_SPI_MSTR_CFG_PAGE_4B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS) -#define MXC_S_SPI_MSTR_CFG_PAGE_8B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS) -#define MXC_S_SPI_MSTR_CFG_PAGE_16B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS) -#define MXC_S_SPI_MSTR_CFG_PAGE_32B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS) - -#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0 -#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS)) -#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8 -#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS)) - -#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0 -#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS)) -#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1 -#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS)) -#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2 -#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS)) -#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3 -#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS)) -#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4 -#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS)) -#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5 -#define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS)) -#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6 -#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS)) -#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8 -#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS)) -#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12 -#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS)) -#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16 -#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS)) - -#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 -#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) -#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8 -#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS)) -#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 -#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) -#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24 -#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS)) - -#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 -#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS)) -#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1 -#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS)) -#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 -#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) -#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 -#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) - -#define MXC_F_SPI_INTFL_TX_STALLED_POS 0 -#define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS)) -#define MXC_F_SPI_INTFL_RX_STALLED_POS 1 -#define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS)) -#define MXC_F_SPI_INTFL_TX_READY_POS 2 -#define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS)) -#define MXC_F_SPI_INTFL_RX_DONE_POS 3 -#define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS)) -#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4 -#define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS)) -#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5 -#define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS)) - -#define MXC_F_SPI_INTEN_TX_STALLED_POS 0 -#define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS)) -#define MXC_F_SPI_INTEN_RX_STALLED_POS 1 -#define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS)) -#define MXC_F_SPI_INTEN_TX_READY_POS 2 -#define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS)) -#define MXC_F_SPI_INTEN_RX_DONE_POS 3 -#define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS)) -#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4 -#define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS)) -#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5 -#define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS)) - -#define MXC_F_SPI_FIFO_DIR_POS 0 -#define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS)) -#define MXC_F_SPI_FIFO_UNIT_POS 2 -#define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS)) -#define MXC_F_SPI_FIFO_SIZE_POS 4 -#define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS)) -#define MXC_F_SPI_FIFO_WIDTH_POS 9 -#define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS)) -#define MXC_F_SPI_FIFO_ALT_POS 11 -#define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS)) -#define MXC_F_SPI_FIFO_FLOW_POS 12 -#define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS)) -#define MXC_F_SPI_FIFO_DASS_POS 13 -#define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS)) - -#define MXC_S_SPI_FIFO_DIR_NONE ((uint32_t)(0X00000000UL << MXC_F_SPI_FIFO_DIR_POS)) -#define MXC_S_SPI_FIFO_DIR_TX ((uint32_t)(0X00000001UL << MXC_F_SPI_FIFO_DIR_POS)) -#define MXC_S_SPI_FIFO_DIR_RX ((uint32_t)(0X00000002UL << MXC_F_SPI_FIFO_DIR_POS)) -#define MXC_S_SPI_FIFO_DIR_BOTH ((uint32_t)(0X00000003UL << MXC_F_SPI_FIFO_DIR_POS)) - -#define MXC_S_SPI_FIFO_UNIT_BITS ((uint32_t)(0X00000000UL << MXC_F_SPI_FIFO_UNIT_POS)) -#define MXC_S_SPI_FIFO_UNIT_BYTES ((uint32_t)(0X00000001UL << MXC_F_SPI_FIFO_UNIT_POS)) -#define MXC_S_SPI_FIFO_UNIT_PAGES ((uint32_t)(0X00000002UL << MXC_F_SPI_FIFO_UNIT_POS)) - -#define MXC_S_SPI_FIFO_WIDTH_SINGLE ((uint32_t)(0X00000000UL << MXC_F_SPI_FIFO_WIDTH_POS)) -#define MXC_S_SPI_FIFO_WIDTH_DUAL ((uint32_t)(0X00000001UL << MXC_F_SPI_FIFO_WIDTH_POS)) -#define MXC_S_SPI_FIFO_WIDTH_QUAD ((uint32_t)(0X00000002UL << MXC_F_SPI_FIFO_WIDTH_POS)) - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_SPI_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/spib_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/spib_regs.h deleted file mode 100644 index 3236a85c44..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/spib_regs.h +++ /dev/null @@ -1,238 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_SPIB_REGS_H_ -#define _MXC_SPIB_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t master_cfg; /* 0x0000 SPIB Master Configuration */ - __IO uint32_t oob_ctrl; /* 0x0004 SPIB OOB Control */ - __IO uint32_t intfl; /* 0x0008 SPIB Interrupt Flags */ - __IO uint32_t inten; /* 0x000C SPIB Interrupt Enables */ - __IO uint32_t slave_reg; /* 0x0010 SPIB Slave Register Access */ -} mxc_spib_regs_t; - - -/* - Register offsets for module SPIB. -*/ - -#define MXC_R_SPIB_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) -#define MXC_R_SPIB_OFFS_OOB_CTRL ((uint32_t)0x00000004UL) -#define MXC_R_SPIB_OFFS_INTFL ((uint32_t)0x00000008UL) -#define MXC_R_SPIB_OFFS_INTEN ((uint32_t)0x0000000CUL) -#define MXC_R_SPIB_OFFS_SLAVE_REG ((uint32_t)0x00000010UL) - - -/* - Field positions and masks for module SPIB. -*/ - -#define MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS 0 -#define MXC_F_SPIB_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) -#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS 2 -#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) -#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS 8 -#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS)) -#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS 12 -#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS)) -#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS 16 -#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS 18 -#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) - -#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS 0 -#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) -#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS 1 -#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) -#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS 2 -#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) - -#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS 0 -#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) -#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS 1 -#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) -#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS 2 -#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) - -#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS 0 -#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) -#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS 1 -#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) -#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS 2 -#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) - -#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS 0 -#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS)) -#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS 1 -#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS)) -#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS 2 -#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) -#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS 8 -#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS)) -#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS 16 -#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS)) - - - -/* - Field values and shifted values for module SPIB. -*/ - -#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) - -#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) -#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) - -#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) -#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) - -#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) -#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) -#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) - -#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) - -#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) -#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) -#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) - -#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) -#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) -#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) -#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) - -#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) -#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) - -#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) -#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) - -#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) -#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) - -#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) -#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) - -#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) -#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) - -#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) -#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) - -#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) -#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) - -#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) -#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) - -#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) -#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) - -#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) -#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_SPIB_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/spix_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/spix_regs.h deleted file mode 100644 index 2d79ebd496..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/spix_regs.h +++ /dev/null @@ -1,201 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_SPIX_REGS_H_ -#define _MXC_SPIX_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t master_cfg; /* 0x0000 SPIX Master Configuration */ - __IO uint32_t fetch_ctrl; /* 0x0004 SPIX Fetch Control */ - __IO uint32_t mode_ctrl; /* 0x0008 SPIX Mode Control */ - __IO uint32_t mode_data; /* 0x000C SPIX Mode Data */ -} mxc_spix_regs_t; - - -/* - Register offsets for module SPIX. -*/ - -#define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) -#define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL) -#define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL) -#define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL) - - -/* - Field positions and masks for module SPIX. -*/ - -#define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0 -#define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) -#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2 -#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) -#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3 -#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) -#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4 -#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS)) -#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 8 -#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)) -#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 12 -#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS)) -#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16 -#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18 -#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) -#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 20 -#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS)) -#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 24 -#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS)) - -#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0 -#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS)) -#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8 -#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) -#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10 -#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) -#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12 -#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) - -#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0 -#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS)) -#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8 -#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS)) - -#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0 -#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS)) -#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16 -#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS)) - - - -/* - Field values and shifted values for module SPIX. -*/ - -#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) - -#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) -#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) - -#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) -#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) - -#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL)) - -#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) -#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) - -#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) -#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) -#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) - -#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) -#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) - -#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) -#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) -#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) - -#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) -#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) -#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) -#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) - -#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) -#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) - -#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) -#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) -#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) - -#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) -#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) - -#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) -#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) -#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) - -#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) -#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) -#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) - -#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) -#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) -#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_SPIX_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c b/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c deleted file mode 100644 index 0e46ae3bbf..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c +++ /dev/null @@ -1,212 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "max32620.h" -#include "clkman_regs.h" -#include "icc_regs.h" -#include "pwrseq_regs.h" -#include "pwrman_regs.h" -#include "adc_regs.h" -#include "flc_regs.h" -#include "trim_regs.h" -#include "rtc_regs.h" - -/* SCB CPACR Register Definitions */ -/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ -#define SCB_CPACR_CP10_Pos 20 /* SCB CPACR: Coprocessor 10 Position */ -#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /* SCB CPACR: Coprocessor 10 Mask */ -#define SCB_CPACR_CP11_Pos 22 /* SCB CPACR: Coprocessor 11 Position */ -#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /* SCB CPACR: Coprocessor 11 Mask */ - -static uint8_t running; - -// NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will -// be AFTER SystemInit() runs. This is required so the hal drivers will have -// the correct value when the DATA sections are initialized. -uint32_t SystemCoreClock = RO_FREQ / 2; - -void SystemCoreClockUpdate(void) -{ - switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) { - - case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2: - default: - SystemCoreClock = RO_FREQ / 2; - break; - case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO: - SystemCoreClock = RO_FREQ; - break; - } -} - -void Trim_ROAtomic(void) -{ - uint32_t trim; - - // Step 1: enable 32KHz RTC - running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; - MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; - - // Step 2: enable RO calibration complete interrupt - MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IE; - - // Step 3: clear RO calibration complete interrupt - MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IF; - - /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */ - - /* Step 5: write initial trim to frequency calibration initial condition register */ - trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS; - MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) | - ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT); - - // Step 6: load initial trim to active frequency trim register - MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD; - - // Step 7: enable frequency loop to control RO trim - MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN; - - // Step 8: run frequency calibration in atomic mode - MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC; - - // Step 9: waiting for ro_cal_done flag - while (!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF)); - - // Step 10: stop frequency calibration - MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN; - - // Step 11: disable RO calibration complete interrupt - MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) & ~MXC_F_ADC_INTR_RO_CAL_DONE_IE; - - // Step 12: read final frequency trim value - trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS; - - /* Step 13: write final trim to RO flash trim shadow register */ - MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) | - ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF); - - // Step 14: restore RTC status - if (!running) { - MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; - } - - // Step 15: disable frequency loop to control RO trim - MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN; -} - -static void ICC_Enable(void) -{ - /* Invalidate cache and wait until ready */ - MXC_ICC->invdt_all = 1; - while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); - - /* Enable cache */ - MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; - - /* Must invalidate a second time for proper use */ - MXC_ICC->invdt_all = 1; -} - -// This function to be implemented by the hal -extern void low_level_init(void); - -// Note: This is called before C run-time initialization. Do not use any initialized variables. -void SystemInit(void) -{ - ICC_Enable(); - - low_level_init(); - - // Select 48MHz ring oscillator as clock source - uint32_t reg = MXC_CLKMAN->clk_ctrl; - reg &= ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT; - MXC_CLKMAN->clk_ctrl = reg; - - // Copy trim information from shadow registers into power manager registers - // NOTE: Checks have been added to prevent bad/missing trim values from being loaded - if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) && - (MXC_TRIM->for_pwr_reg5 != 0xffffffff) && - (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) { - MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5; - MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6; - } else { - /* No valid info block, use some reasonable defaults */ - MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF; - MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS); - } - - // Use ASYNC flags, and ASYNC Reset of flags to improve synchronization speed - // between RTC and ARM core. Also avoid delayed RTC interrupts after lp wake. - MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS | MXC_F_RTC_CTRL_AGGRESSIVE_RST); - - /* Clear the GPIO WUD event if not waking up from LP0 */ - /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/ - if (MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT || !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) { - /* Clear GPIO WUD event and configuration registers, globally */ - MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH); - MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH); - } else { - /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */ - MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE); - } - - // Turn on retention regulator - MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP); - - // Clear all unused wakeup sources - // Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals - MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP | - MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP); - - // RTC sources are inverted, so a 1 will disable them - MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 | - MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP); - - /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */ - MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; - - // Enable real-time clock during sleep mode - MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); - -#if (__FPU_PRESENT == 1) - /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ - /* Grant full access, per "Table B3-24 CPACR bit assignments". */ - /* DDI0403D "ARMv7-M Architecture Reference Manual" */ - SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; - __DSB(); - __ISB(); -#endif - - // Trim ring oscillator - Trim_ROAtomic(); -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.h deleted file mode 100644 index 3df2235fc2..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.h +++ /dev/null @@ -1,78 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _SYSTEM_MAX32620_H_ -#define _SYSTEM_MAX32620_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#ifndef RO_FREQ -#define RO_FREQ 96000000 -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit(void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_MAX32620_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/tmr_regs.h deleted file mode 100644 index adae1555bd..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/tmr_regs.h +++ /dev/null @@ -1,203 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_TMR_REGS_H_ -#define _MXC_TMR_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t ctrl; /* 0x0000 Timer Control Register */ - __IO uint32_t count32; /* 0x0004 Timer [32 bit] Current Count Value */ - __IO uint32_t term_cnt32; /* 0x0008 Timer [32 bit] Terminal Count Setting */ - __IO uint32_t pwm_cap32; /* 0x000C Timer [32 bit] PWM Compare Setting or Capture/Measure Value */ - __IO uint32_t count16_0; /* 0x0010 Timer [16 bit] Current Count Value, 16-bit Timer 0 */ - __IO uint32_t term_cnt16_0; /* 0x0014 Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */ - __IO uint32_t count16_1; /* 0x0018 Timer [16 bit] Current Count Value, 16-bit Timer 1 */ - __IO uint32_t term_cnt16_1; /* 0x001C Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */ - __IO uint32_t intfl; /* 0x0020 Timer Interrupt Flags */ - __IO uint32_t inten; /* 0x0024 Timer Interrupt Enable/Disable Settings */ -} mxc_tmr_regs_t; - - -/* - Register offsets for module TMR. -*/ - -#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) -#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) -#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) -#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) -#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) -#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) -#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) -#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) -#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) - - -/* - Field positions and masks for module TMR. -*/ - -#define MXC_F_TMR_CTRL_MODE_POS 0 -#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_F_TMR_CTRL_TMR2X16_POS 3 -#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) -#define MXC_F_TMR_CTRL_PRESCALE_POS 4 -#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_F_TMR_CTRL_POLARITY_POS 8 -#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) -#define MXC_F_TMR_CTRL_ENABLE0_POS 12 -#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) -#define MXC_F_TMR_CTRL_ENABLE1_POS 13 -#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) - -#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 -#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) - -#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 -#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) - -#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 -#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) - -#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 -#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) - -#define MXC_F_TMR_INTFL_TIMER0_POS 0 -#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) -#define MXC_F_TMR_INTFL_TIMER1_POS 1 -#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) - -#define MXC_F_TMR_INTEN_TIMER0_POS 0 -#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) -#define MXC_F_TMR_INTEN_TIMER1_POS 1 -#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) - - - -/* - Field values and shifted values for module TMR. -*/ - -#define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL)) -#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL)) -#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL)) -#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL)) -#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL)) -#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL)) -#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL)) -#define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL)) - -#define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS)) -#define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS)) - -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL)) -#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL)) - -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS)) -#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS)) - - -/* - * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module - * is in dual 16-bit timer mode. - */ - -#define MXC_F_TMR_CTRL_MODE_16_0_POS 0 -#define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_16_0_POS)) - -#define MXC_F_TMR_CTRL_MODE_16_1_POS 1 -#define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_16_1_POS)) - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_TMR_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/tpu_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/tpu_regs.h deleted file mode 100644 index dedd2e2b9f..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/tpu_regs.h +++ /dev/null @@ -1,98 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_TPU_REGS_H_ -#define _MXC_TPU_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t prng_user_entropy; /* 0x0000 PRNG User Entropy Value */ - __IO uint32_t prng_rnd_num; /* 0x0004 PRNG Seed Output */ -} mxc_tpu_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __I uint32_t rsv000[4]; /* 0x0000-0x000C */ - __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 (Cleared on Tamper Detect) */ - __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 1 (Cleared on Tamper Detect) */ - __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 2 (Cleared on Tamper Detect) */ - __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 3 (Cleared on Tamper Detect) */ -} mxc_tpu_tsr_regs_t; - - -/* - Register offsets for module TPU. -*/ - -#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY ((uint32_t)0x00000000UL) -#define MXC_R_TPU_OFFS_PRNG_RND_NUM ((uint32_t)0x00000004UL) -#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL) -#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL) -#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL) -#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL) - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_TPU_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/trim_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/trim_regs.h deleted file mode 100644 index c0e9658f1a..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/trim_regs.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_TRIM_REGS_H_ -#define _MXC_TRIM_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __I uint32_t rsv000[11]; /* 0x0000-0x0028 */ - __IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */ - __IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */ - __IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */ - __IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */ -} mxc_trim_regs_t; - - -/* - Register offsets for module TRIM. -*/ - -#define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL) -#define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL) -#define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL) -#define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL) - - -/* - Field positions and masks for module TRIM. -*/ - -#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0 -#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS)) -#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16 -#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS)) - -#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0 -#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS)) -#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16 -#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS)) -#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28 -#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_TRIM_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/uart_regs.h deleted file mode 100644 index 276c95e8f2..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/uart_regs.h +++ /dev/null @@ -1,226 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_UART_REGS_H_ -#define _MXC_UART_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t ctrl; /* 0x0000 UART Control Register */ - __IO uint32_t baud; /* 0x0004 UART Baud Control Register */ - __IO uint32_t tx_fifo_ctrl; /* 0x0008 UART TX FIFO Control Register */ - __IO uint32_t rx_fifo_ctrl; /* 0x000C UART RX FIFO Control Register */ - __IO uint32_t md_ctrl; /* 0x0010 UART Multidrop Control Register */ - __IO uint32_t intfl; /* 0x0014 UART Interrupt Flags */ - __IO uint32_t inten; /* 0x0018 UART Interrupt Enable/Disable Controls */ -} mxc_uart_regs_t; - - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - union { /* 0x0000-0x07FC FIFO Write Point for Data to Transmit */ - __IO uint8_t tx_8[2048]; - __IO uint16_t tx_16[1024]; - __IO uint32_t tx_32[512]; - }; - union { /* 0x0800-0x0FFC FIFO Read Point for Received Data */ - __IO uint8_t rx_8[2048]; - __IO uint16_t rx_16[1024]; - __IO uint32_t rx_32[512]; - }; -} mxc_uart_fifo_regs_t; - - -/* - Register offsets for module UART. -*/ - -#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL) -#define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL) -#define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL) -#define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL) -#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL) -#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL) -#define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL) -#define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL) - - -/* - Field positions and masks for module UART. -*/ - -#define MXC_F_UART_CTRL_UART_EN_POS 0 -#define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS)) -#define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1 -#define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS)) -#define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2 -#define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS)) -#define MXC_F_UART_CTRL_DATA_SIZE_POS 4 -#define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS)) -#define MXC_F_UART_CTRL_EXTRA_STOP_POS 8 -#define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS)) -#define MXC_F_UART_CTRL_PARITY_POS 12 -#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS)) -#define MXC_F_UART_CTRL_CTS_EN_POS 16 -#define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS)) -#define MXC_F_UART_CTRL_CTS_POLARITY_POS 17 -#define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS)) -#define MXC_F_UART_CTRL_RTS_EN_POS 18 -#define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS)) -#define MXC_F_UART_CTRL_RTS_POLARITY_POS 19 -#define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS)) -#define MXC_F_UART_CTRL_RTS_LEVEL_POS 20 -#define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS)) - -#define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0 -#define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS)) - -#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0 -#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)) -#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16 -#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS)) - -#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0 -#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS)) -#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16 -#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS)) - -#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0 -#define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS)) -#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8 -#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS)) -#define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16 -#define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS)) -#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17 -#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS)) - -#define MXC_F_UART_INTFL_TX_DONE_POS 0 -#define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS)) -#define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1 -#define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS)) -#define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2 -#define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS)) -#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3 -#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS)) -#define MXC_F_UART_INTFL_RX_STALLED_POS 4 -#define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS)) -#define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5 -#define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS)) -#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6 -#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS)) -#define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7 -#define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS)) -#define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8 -#define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS)) - -#define MXC_F_UART_INTEN_TX_DONE_POS 0 -#define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS)) -#define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1 -#define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS)) -#define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2 -#define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS)) -#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3 -#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS)) -#define MXC_F_UART_INTEN_RX_STALLED_POS 4 -#define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS)) -#define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5 -#define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS)) -#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6 -#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS)) -#define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7 -#define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS)) -#define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8 -#define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS)) - - - -/* - Field values and shifted values for module UART. -*/ - -#define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL)) -#define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL)) -#define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL)) -#define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL)) - -#define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) -#define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) -#define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) -#define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS)) - -#define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL)) -#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL)) -#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL)) -#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL)) - -#define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS)) -#define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS)) -#define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS)) -#define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_UART_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/usb_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/usb_regs.h deleted file mode 100644 index 05c39dda7d..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/usb_regs.h +++ /dev/null @@ -1,296 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_USB_REGS_H_ -#define _MXC_USB_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __I -#define __I volatile const -#endif - - -#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL) -#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL) -#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL) -#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL) - -#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS) -#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS) -#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS) -#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS) - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t cn; /* 0x0000 USB Control Register */ - __I uint32_t rsv004[127]; /* 0x0004-0x01FC */ - __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */ - __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */ - __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */ - __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */ - __I uint32_t rsv210[4]; /* 0x0210-0x021C */ - __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */ - __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */ - __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */ - __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */ - __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */ - __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */ - __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */ - __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */ - __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */ - __I uint32_t rsv244[7]; /* 0x0244-0x025C */ - __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */ - __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */ - __I uint32_t rsv268[6]; /* 0x0268-0x027C */ - __IO uint32_t ep[8]; /* 0x0280-0x029C USB Endpoint[n] Control Register */ -} mxc_usb_regs_t; - - -/* - Register offsets for module USB. -*/ - -#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL) -#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL) -#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL) -#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL) -#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL) -#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL) -#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL) -#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL) -#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL) -#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL) -#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL) -#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL) -#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL) -#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL) -#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL) -#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL) -#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL) -#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL) -#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL) -#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL) -#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL) -#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL) -#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL) -#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL) - - -/* - Field positions and masks for module USB. -*/ - -#define MXC_F_USB_CN_USB_EN_POS 0 -#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS)) -#define MXC_F_USB_CN_HOST_POS 1 -#define MXC_F_USB_CN_HOST ((uint32_t)(0x00000001UL << MXC_F_USB_CN_HOST_POS)) - -#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0 -#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS)) - -#define MXC_F_USB_DEV_CN_SIGRWU_POS 2 -#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS)) -#define MXC_F_USB_DEV_CN_CONNECT_POS 3 -#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS)) -#define MXC_F_USB_DEV_CN_ULPM_POS 4 -#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS)) -#define MXC_F_USB_DEV_CN_URST_POS 5 -#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS)) -#define MXC_F_USB_DEV_CN_VBGATE_POS 6 -#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS)) -#define MXC_F_USB_DEV_CN_OSCEN_POS 7 -#define MXC_F_USB_DEV_CN_OSCEN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_OSCEN_POS)) -#define MXC_F_USB_DEV_CN_BACT_OE_POS 8 -#define MXC_F_USB_DEV_CN_BACT_OE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_BACT_OE_POS)) -#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9 -#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS)) - -#define MXC_F_USB_DEV_INTFL_DPACT_POS 0 -#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS)) -#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1 -#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS)) -#define MXC_F_USB_DEV_INTFL_BACT_POS 2 -#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS)) -#define MXC_F_USB_DEV_INTFL_BRST_POS 3 -#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS)) -#define MXC_F_USB_DEV_INTFL_SUSP_POS 4 -#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS)) -#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5 -#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS)) -#define MXC_F_USB_DEV_INTFL_VBUS_POS 6 -#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS)) -#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7 -#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS)) -#define MXC_F_USB_DEV_INTFL_SETUP_POS 8 -#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS)) -#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9 -#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS)) -#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10 -#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS)) -#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11 -#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS)) -#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12 -#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS)) -#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13 -#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS)) -#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16 -#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS)) - -#define MXC_F_USB_DEV_INTEN_DPACT_POS 0 -#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS)) -#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1 -#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS)) -#define MXC_F_USB_DEV_INTEN_BACT_POS 2 -#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS)) -#define MXC_F_USB_DEV_INTEN_BRST_POS 3 -#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS)) -#define MXC_F_USB_DEV_INTEN_SUSP_POS 4 -#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS)) -#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5 -#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS)) -#define MXC_F_USB_DEV_INTEN_VBUS_POS 6 -#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS)) -#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7 -#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS)) -#define MXC_F_USB_DEV_INTEN_SETUP_POS 8 -#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS)) -#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9 -#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS)) -#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10 -#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS)) -#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11 -#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS)) -#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12 -#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS)) -#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13 -#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS)) - -#define MXC_F_USB_EP_BASE_EP_BASE_POS 9 -#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS)) - -#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0 -#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS)) -#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16 -#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS)) - -#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0 -#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS)) -#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16 -#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS)) - -#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0 -#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS)) -#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16 -#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS)) - -#define MXC_F_USB_IN_INT_INBAV_POS 0 -#define MXC_F_USB_IN_INT_INBAV ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_INT_INBAV_POS)) - -#define MXC_F_USB_OUT_INT_OUTDAV_POS 0 -#define MXC_F_USB_OUT_INT_OUTDAV ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_INT_OUTDAV_POS)) - -#define MXC_F_USB_NAK_INT_NAK_POS 0 -#define MXC_F_USB_NAK_INT_NAK ((uint32_t)(0x000000FFUL << MXC_F_USB_NAK_INT_NAK_POS)) - -#define MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS 0 -#define MXC_F_USB_DMA_ERR_INT_DMA_ERR ((uint32_t)(0x000000FFUL << MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS)) - -#define MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS 0 -#define MXC_F_USB_BUF_OVR_INT_BUF_OVR ((uint32_t)(0x000000FFUL << MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS)) - -#define MXC_F_USB_SETUP0_BYTE0_POS 0 -#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS)) -#define MXC_F_USB_SETUP0_BYTE1_POS 8 -#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS)) -#define MXC_F_USB_SETUP0_BYTE2_POS 16 -#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS)) -#define MXC_F_USB_SETUP0_BYTE3_POS 24 -#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS)) - -#define MXC_F_USB_SETUP1_BYTE0_POS 0 -#define MXC_F_USB_SETUP1_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE0_POS)) -#define MXC_F_USB_SETUP1_BYTE1_POS 8 -#define MXC_F_USB_SETUP1_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE1_POS)) -#define MXC_F_USB_SETUP1_BYTE2_POS 16 -#define MXC_F_USB_SETUP1_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE2_POS)) -#define MXC_F_USB_SETUP1_BYTE3_POS 24 -#define MXC_F_USB_SETUP1_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE3_POS)) - -#define MXC_F_USB_EP_DIR_POS 0 -#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS)) -#define MXC_F_USB_EP_BUF2_POS 3 -#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS)) -#define MXC_F_USB_EP_INT_EN_POS 4 -#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INT_EN_POS)) -#define MXC_F_USB_EP_NAK_EN_POS 5 -#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS)) -#define MXC_F_USB_EP_DT_POS 6 -#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS)) -#define MXC_F_USB_EP_STALL_POS 8 -#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS)) -#define MXC_F_USB_EP_ST_STALL_POS 9 -#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS)) -#define MXC_F_USB_EP_ST_ACK_POS 10 -#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_USB_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/wdt_regs.h deleted file mode 100644 index f01895ff52..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/device/wdt_regs.h +++ /dev/null @@ -1,238 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _MXC_WDT_REGS_H_ -#define _MXC_WDT_REGS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif - - -/* - Typedefed structure(s) for module registers (per instance or section) with direct 32-bit - access to each register in module. -*/ - -/* Offset Register Description - ============= ============================================================================ */ -typedef struct { - __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */ - __IO uint32_t clear; /* 0x0004 Watchdog Timer Clear Register (Feed Dog) */ - __IO uint32_t flags; /* 0x0008 Watchdog Timer Interrupt and Reset Flags */ - __IO uint32_t enable; /* 0x000C Watchdog Timer Interrupt/Reset Enable/Disable Controls */ - __I uint32_t rsv010; /* 0x0010 */ - __IO uint32_t lock_ctrl; /* 0x0014 Watchdog Timer Register Setting Lock for Control Register */ -} mxc_wdt_regs_t; - - -/* - Register offsets for module WDT. -*/ - -#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) -#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) -#define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL) -#define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL) -#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) - - -/* - Field positions and masks for module WDT. -*/ - -#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 -#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 -#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 -#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) -#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 -#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) -#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 -#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) - -#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 -#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) -#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 -#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) -#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 -#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) - -#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 -#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) -#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 -#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) -#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 -#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) - -#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 -#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) - - - -/* - Field values and shifted values for module WDT. -*/ - -#define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) -#define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) - -#define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) - -#define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) -#define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) - -#define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) -#define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) - -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) -#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) - -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) -#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) - - -#define MXC_V_WDT_LOCK_KEY 0x24 -#define MXC_V_WDT_UNLOCK_KEY 0x42 - -#define MXC_V_WDT_RESET_KEY_0 0xA5 -#define MXC_V_WDT_RESET_KEY_1 0x5A - - -#ifdef __cplusplus -} -#endif - -#endif /* _MXC_WDT_REGS_H_ */ - diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c deleted file mode 100644 index b4f988fd2e..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c +++ /dev/null @@ -1,100 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "gpio_regs.h" -#include "clkman_regs.h" - -uint32_t gpio_set(PinName name) -{ - MBED_ASSERT(name != (PinName)NC); - pin_function(name, 0); - return 1 << PINNAME_TO_PIN(name); -} - -void gpio_init(gpio_t *obj, PinName name) -{ - obj->name = name; - if (name == (PinName)NC) { - return; - } - - unsigned int port = PINNAME_TO_PORT(name); - unsigned int pin = PINNAME_TO_PIN(name); - - obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin); - obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin); - - /* Ensure that the GPIO clock is enabled */ - MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER; - - /* Ensure that the GPIO clock is enabled */ - MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->name, mode); -} - -void pin_dir(PinName name, PinDirection direction) -{ - MBED_ASSERT(name != (PinName)NC); - - unsigned int port = PINNAME_TO_PORT(name); - unsigned int pin = PINNAME_TO_PIN(name); - - /* Set function; Firmware Control (GPIO mode) */ - MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin)); - - /* Normal input is always enabled */ - MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin)); - - if (direction == PIN_INPUT) { - /* Set requested output mode */ - MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * pin)); - - /* Enable default input weak pull-up by setting corresponding output */ - MXC_GPIO->out_val[port] |= 1 << pin; - } else { - /* Set requested output mode */ - MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * pin)); - } -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - pin_dir(obj->name, direction); -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c deleted file mode 100644 index dd00bea21d..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c +++ /dev/null @@ -1,286 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "ioman_regs.h" -#include "pwrman_regs.h" -#include "pwrseq_regs.h" - -static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}}; -static gpio_irq_handler irq_handler; - -static void gpio_irq_wud_req(gpio_irq_t *obj) -{ - unsigned int port = obj->port; - unsigned int pin = obj->pin; - uint32_t pin_mask = 1 << pin; - - /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1 */ - /* During the time the WUD IOMAN requests are asserted (1), the GPIO Pad */ - /* is in HIGH Z mode, regardless of GPIO setting. This may cause bogus interrupts. */ - if (port < 4) { - uint32_t mask = pin_mask << (port << 3); - if (!(MXC_IOMAN->wud_ack0 & mask)) { - MXC_IOMAN->wud_req0 |= mask; - while(!(MXC_IOMAN->wud_ack0 & mask)); - } - } else if (port < 8) { - uint32_t mask = pin_mask << ((port-4) << 3); - if (!(MXC_IOMAN->wud_ack1 & mask)) { - MXC_IOMAN->wud_req1 |= mask; - while(!(MXC_IOMAN->wud_ack1 & mask)); - } - } -} - -/* Clear the selected pin from wake-up detect */ -static void gpio_irq_wud_clear(gpio_irq_t *obj) -{ - unsigned int port = obj->port; - unsigned int pin = obj->pin; - - /* Enable modifications to WUD configuration */ - MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE; - - /* Select pad in WUD control */ - /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */ - MXC_PWRMAN->wud_ctrl |= (port * 8) + pin; - - /* Clear any existing WUD configuration for this pad */ - MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE); - MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); - /* Clear with PULSE0; PULSE1 enables WUD */ - MXC_PWRMAN->wud_pulse0 = 1; - - /* Disable configuration */ - MXC_PWRMAN->wud_ctrl = 0; - MXC_IOMAN->wud_req0 = 0; - MXC_IOMAN->wud_req1 = 0; -} - -/* Configure the selected pin for wake-up detect */ -static void gpio_irq_wud_config(gpio_irq_t *obj) -{ - unsigned int port = obj->port; - unsigned int pin = obj->pin; - uint32_t pin_mask = 1 << pin; - - /* Enable modifications to WUD configuration */ - MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE; - - /* Select pad in WUD control */ - /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */ - MXC_PWRMAN->wud_ctrl |= (port * 8) + pin; - - /* First clear any existing WUD configuration for this pad */ - MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE); - MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); - /* Clear with PULSE0; PULSE1 enables WUD */ - MXC_PWRMAN->wud_pulse0 = 1; - - if (obj->fall_en || obj->rise_en) { - /* Configure sense level on this pad */ - MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE); - MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); - - uint32_t in_val = MXC_GPIO->in_val[port] & pin_mask; - do { - if (in_val) { - /* Select active low with PULSE1 (backwards from what you'd expect) */ - MXC_PWRMAN->wud_pulse1 = 1; - } else { - /* Select active high with PULSE0 (backwards from what you'd expect) */ - MXC_PWRMAN->wud_pulse0 = 1; - } - } while ((MXC_GPIO->in_val[port] & pin_mask) != in_val); - - /* Select this pad to have the wake-up function enabled */ - MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE); - MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS); - /* Activate with PULSE1 */ - MXC_PWRMAN->wud_pulse1 = 1; - - // NOTE: Low Power Pullup/down is not normally needed in addition to - // standard GPIO Pullup/downs. - - /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */ - MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP; - } - - /* Disable configuration */ - MXC_PWRMAN->wud_ctrl = 0; - MXC_IOMAN->wud_req0 = 0; - MXC_IOMAN->wud_req1 = 0; -} - -static void handle_irq(unsigned int port) -{ - uint32_t intfl, in_val; - uint32_t mask; - unsigned int pin; - - /* Read pin state */ - in_val = MXC_GPIO->in_val[port]; - - /* Read interrupts */ - intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port]; - - mask = 1; - - for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { - if (intfl & mask) { - MXC_GPIO->intfl[port] = mask; /* clear interrupt */ - gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL; - gpio_irq_t *obj = objs[port][pin]; - if (obj && obj->id) { - if ((event == IRQ_RISE) && obj->rise_en) { - irq_handler(obj->id, IRQ_RISE); - } else if ((event == IRQ_FALL) && obj->fall_en) { - irq_handler(obj->id, IRQ_FALL); - } - } - - gpio_irq_wud_config(obj); - } - mask <<= 1; - } -} - -void gpio_irq_0(void) { handle_irq(0); } -void gpio_irq_1(void) { handle_irq(1); } -void gpio_irq_2(void) { handle_irq(2); } -void gpio_irq_3(void) { handle_irq(3); } -void gpio_irq_4(void) { handle_irq(4); } -void gpio_irq_5(void) { handle_irq(5); } -void gpio_irq_6(void) { handle_irq(6); } - -int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) -{ - if (name == NC) { - return -1; - } - - uint8_t port = PINNAME_TO_PORT(name); - uint8_t pin = PINNAME_TO_PIN(name); - - if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) { - return 1; - } - - obj->port = port; - obj->pin = pin; - obj->id = id; - objs[port][pin] = obj; - - /* register handlers */ - irq_handler = handler; - NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0); - NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1); - NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2); - NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3); - NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4); - NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5); - NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6); - - /* request WUD in case the application is going to sleep */ - gpio_irq_wud_req(obj); - - /* disable the interrupt locally */ - MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4)); - - /* clear a pending request */ - MXC_GPIO->intfl[port] = 1 << pin; - - /* enable the requested interrupt */ - MXC_GPIO->inten[port] |= (1 << pin); - NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port)); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - /* disable interrupt */ - MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); - MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); - objs[obj->port][obj->pin] = NULL; - gpio_irq_wud_clear(obj); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - if (event == IRQ_FALL) { - obj->fall_en = enable; - } else if (event == IRQ_RISE) { - obj->rise_en = enable; - } - - if (obj->fall_en || obj->rise_en) { - MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); - gpio_irq_wud_config(obj); /* enable WUD for this pin so we may wake from deepsleep as well */ - } else { - MXC_GPIO->int_mode[obj->port] &= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); - gpio_irq_wud_clear(obj); - } -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - MXC_GPIO->inten[obj->port] |= (1 << obj->pin); - gpio_irq_wud_config(obj); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); - gpio_irq_wud_clear(obj); -} - -gpio_irq_t *gpio_irq_get_obj(PinName name) -{ - if (name == NC) { - return NULL; - } - - unsigned int port = PINNAME_TO_PORT(name); - unsigned int pin = PINNAME_TO_PIN(name); - - if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) { - return NULL; - } - - return objs[port][pin]; -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h deleted file mode 100644 index 8281590e77..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h +++ /dev/null @@ -1,72 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName name; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->name != (PinName)NC); - *obj->reg_out = !!value; -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->name != (PinName)NC); - return *obj->reg_in; -} - -void pin_dir(PinName name, PinDirection direction); - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return obj->name != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c deleted file mode 100644 index 39b293b35f..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c +++ /dev/null @@ -1,457 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "i2cm_regs.h" -#include "clkman_regs.h" -#include "ioman_regs.h" -#include "PeripheralPins.h" - -#define I2C_SLAVE_ADDR_READ_BIT 0x0001 - -#ifndef MXC_I2CM_TX_TIMEOUT -#define MXC_I2CM_TX_TIMEOUT 0x5000 -#endif - -#ifndef MXC_I2CM_RX_TIMEOUT -#define MXC_I2CM_RX_TIMEOUT 0x5000 -#endif - -typedef enum { - /** 100KHz */ - MXC_E_I2CM_SPEED_100KHZ = 0, - /** 400KHz */ - MXC_E_I2CM_SPEED_400KHZ -} i2cm_speed_t; - -/* Clock divider lookup table */ -static const uint32_t clk_div_table[2][8] = { - /* MXC_E_I2CM_SPEED_100KHZ */ - { - /* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - /* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - /* 2: */ 0, /* not supported */ - /* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - /* 4: */ 0, /* not supported */ - /* 5: */ 0, /* not supported */ - /* 6: */ 0, /* not supported */ - /* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - }, - /* MXC_E_I2CM_SPEED_400KHZ */ - { - /* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - /* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - /* 2: */ 0, /* not supported */ - /* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - /* 4: */ 0, /* not supported */ - /* 5: */ 0, /* not supported */ - /* 6: */ 0, /* not supported */ - /* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | - (33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | - (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), - }, -}; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)i2c != NC); - - obj->i2c = i2c; - obj->fifos = (mxc_i2cm_fifo_regs_t*)MXC_I2CM_GET_BASE_FIFO(MXC_I2CM_GET_IDX(i2c)); - obj->start_pending = 0; - obj->stop_pending = 0; - - // configure the pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - - // enable the clock - MXC_CLKMAN->sys_clk_ctrl_9_i2cm = MXC_S_CLKMAN_CLK_SCALE_DIV_1; - - // reset module - i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; - i2c->ctrl = 0; - - // set default frequency at 100k - i2c_frequency(obj, 100000); - - // set timeout to 255 ms and turn on the auto-stop option - i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN; - - // enable tx_fifo and rx_fifo - i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN); -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - // compute clock array index - // (96Mhz/12M) -1 = 7 - // (48Mhz/12M) -1 = 3 - // (24Mhz/12M) -1 = 1 - // (12Mhz/12M) -1 = 0 - int clki = (SystemCoreClock / 12000000) - 1; - - // get clock divider settings from lookup table - if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) { - obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki]; - } else if ((hz >= 400000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) { - obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki]; - } -} - -static int write_tx_fifo(i2c_t *obj, const uint16_t data) -{ - int timeout = MXC_I2CM_TX_TIMEOUT; - - while (*obj->fifos->trans) { - uint32_t intfl = obj->i2c->intfl; - if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { - return I2C_ERROR_NO_SLAVE; - } - if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { - return I2C_ERROR_BUS_BUSY; - } - timeout--; - } - *obj->fifos->trans = data; - - return 0; -} - -static int wait_tx_in_progress(i2c_t *obj) -{ - int timeout = MXC_I2CM_TX_TIMEOUT; - - while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout); - - uint32_t intfl = obj->i2c->intfl; - - if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { - i2c_reset(obj); - return I2C_ERROR_NO_SLAVE; - } - - if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { - i2c_reset(obj); - return I2C_ERROR_BUS_BUSY; - } - - return 0; -} - -int i2c_start(i2c_t *obj) -{ - obj->start_pending = 1; - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - obj->start_pending = 0; - write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP); - - return wait_tx_in_progress(obj); -} - -void i2c_reset(i2c_t *obj) -{ - obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; - obj->i2c->intfl = 0x3FF; // clear all interrupts - obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN; - obj->start_pending = 0; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - int err; - - // clear all interrupts - obj->i2c->intfl = 0x3FF; - - if (obj->start_pending) { - obj->start_pending = 0; - data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START; - } else { - data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK; - } - - if ((err = write_tx_fifo(obj, data)) != 0) { - return err; - } - - obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; - - // Wait for the FIFO to be empty - while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY)); - - if (obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) { - i2c_reset(obj); - return 0; - } - - if (obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) { - i2c_reset(obj); - return 2; - } - - return 1; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - uint16_t fifo_value; - int err; - - // clear all interrupts - obj->i2c->intfl = 0x3FF; - - if (last) { - fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK; - } else { - fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT; - } - - if ((err = write_tx_fifo(obj, fifo_value)) != 0) { - i2c_reset(obj); - return err; - } - - obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; - - int timeout = MXC_I2CM_RX_TIMEOUT; - while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && - (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { - if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT | - MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) { - break; - } - } - - if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) { - obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; - return *obj->fifos->rslts; - } - - i2c_reset(obj); - - return -1; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int err, retval = 0; - int i; - - if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { - return 0; - } - - // clear all interrupts - obj->i2c->intfl = 0x3FF; - - // write the address to the fifo - if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write) - i2c_reset(obj); - return err; - } - obj->start_pending = 0; - - // start the transaction - obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; - - // load as much of the cmd into the FIFO as possible - for (i = 0; i < length; i++) { - if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK) - retval = (retval ? retval : err); - break; - } - } - - if (stop) { - obj->stop_pending = 0; - if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition - retval = (retval ? retval : err); - } - - if ((err = wait_tx_in_progress(obj)) != 0) { - retval = (retval ? retval : err); - } - } else { - obj->stop_pending = 1; - int timeout = MXC_I2CM_TX_TIMEOUT; - // Wait for TX fifo to be empty - while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--); - } - - if (retval == 0) { - return length; - } - - i2c_reset(obj); - - return retval; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int err, retval = 0; - int i = length; - int timeout; - - if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { - return 0; - } - - // clear all interrupts - obj->i2c->intfl = 0x3FF; - - // start + addr (read) - if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) { - goto read_done; - } - obj->start_pending = 0; - - while (i > 256) { - if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) { - goto read_done; - } - i -= 256; - } - - if (i > 1) { - if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) { - goto read_done; - } - } - - // start the transaction - obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; - - if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte - goto read_done; - } - - if (stop) { - if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition - goto read_done; - } - } - - timeout = MXC_I2CM_RX_TIMEOUT; - i = 0; - while (i < length) { - while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && - (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { - if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT | - MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) { - retval = -3; - goto read_done; - } - } - - timeout = MXC_I2CM_RX_TIMEOUT; - - obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; - - uint16_t temp = *obj->fifos->rslts; - - if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) { - continue; - } - data[i++] = (uint8_t) temp; - } - -read_done: - - if (stop) { - obj->stop_pending = 0; - if ((err = wait_tx_in_progress(obj)) != 0) { - retval = (retval ? retval : err); - } - } else { - obj->stop_pending = 1; - } - - if (retval == 0) { - return length; - } - - i2c_reset(obj); - - return retval; -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/objects.h b/targets/TARGET_Maxim/TARGET_MAX32620/objects.h deleted file mode 100644 index 86b89c4163..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/objects.h +++ /dev/null @@ -1,125 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "gpio_object.h" -#include "gpio_regs.h" -#include "uart_regs.h" -#include "i2cm_regs.h" -#include "spi_regs.h" -#include "pt_regs.h" -#include "adc_regs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct port_s { - PortName port; - uint32_t mask; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; -}; - -struct gpio_irq_s { - uint8_t port; - uint8_t pin; - uint8_t rise_en; - uint8_t fall_en; - uint32_t id; -}; - -struct serial_s { - int index; - mxc_uart_regs_t *uart; - mxc_uart_fifo_regs_t *fifo; -}; - -struct i2c_s { - int index; - mxc_i2cm_regs_t *i2c; - mxc_i2cm_fifo_regs_t *fifos; - int start_pending; - int stop_pending; -}; - -struct spi_s { - int index; - mxc_spi_regs_t *spi; - mxc_spi_fifo_regs_t *fifo; - int bits; - int ssel; - uint32_t width; // SPI data width (number of data lines to use) - PinName sclk; // PinName saved to use in Quad SPI pin mapping table -#if DEVICE_SPI_ASYNCH - // Async transaction state - const uint8_t *tx_data; // TX buffer - uint8_t *rx_data; // RX buffer - unsigned len; // Number of bytes to send - unsigned read_num; // Number of bytes read - unsigned write_num; // Number of bytes written - void (*callback)(); // Callback for asynchronous request - unsigned head_rem; // Remaining count for current header - uint32_t event; // Callback response events -#endif -}; - -struct pwmout_s { - mxc_pt_regs_t *pwm; - int period; - int pulse_width; -}; - -struct analogin_s { - mxc_adc_regs_t *adc; - PinName adc_pin; -}; - -typedef struct { - volatile uint32_t *reg_req; - volatile uint32_t *reg_ack; - uint32_t req_val; - uint32_t ack_mask; -} pin_function_t; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c b/targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c deleted file mode 100644 index e10b0fb5b9..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c +++ /dev/null @@ -1,117 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "pinmap.h" -#include "objects.h" -#include "gpio_regs.h" -#include "ioman_regs.h" - -void pin_function(PinName name, int function) -{ - MBED_ASSERT(name != (PinName)NC); - - if ((function >= 0) && (function <= 0xF)) { - unsigned int port = PINNAME_TO_PORT(name); - unsigned int pin = PINNAME_TO_PIN(name); - uint32_t temp = MXC_GPIO->func_sel[port] & ~(0xF << (pin*4)); - MXC_GPIO->func_sel[port] = temp | ((uint32_t)function << (pin*4)); - } else { - /* Assume this is a pointer to a pin function object */ - pin_function_t *obj = (pin_function_t*)function; - - if ((*obj->reg_ack & obj->ack_mask) != obj->req_val) { - /* Request pin mapping */ - *obj->reg_req |= obj->req_val; - - /* Check for acknowledgment */ - MBED_ASSERT((*obj->reg_ack & obj->ack_mask) == obj->req_val); - } - } -} - -void pin_mode(PinName name, PinMode mode) -{ - MBED_ASSERT(name != (PinName)NC); - unsigned int port = PINNAME_TO_PORT(name); - unsigned int pin = PINNAME_TO_PIN(name); - - /* Must set mode while retaining direction */ - - /* Get the current direction */ - uint32_t out_mode = MXC_GPIO->out_mode[port]; - uint32_t curr_mode = (out_mode >> (pin * 4)) & 0xF; - PinDirection dir = PIN_OUTPUT; - if ((curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) || - (curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN) || - (curr_mode == MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z)) { - dir = PIN_INPUT; - } - - /* Set mode based on current direction */ - uint32_t new_mode; - if (dir == PIN_OUTPUT) { - // PullUp = not valid, - // PullDown = not valid, - // OpenDrain = MXC_V_GPIO_OUT_MODE_OD, - // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL, - if (mode == OpenDrain) { - new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN; - } else { - new_mode = MXC_V_GPIO_OUT_MODE_NORMAL; - } - } else { - // PullUp = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP - // PullDown = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN - // OpenDrain = MXC_V_GPIO_OUT_MODE_OD - // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z - if (mode == PullUp) { - new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP; - MXC_GPIO->out_val[port] |= 1 << pin; - } else if (mode == PullDown) { - new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN; - MXC_GPIO->out_val[port] &= ~(1 << pin); - } else if (mode == OpenDrain) { - new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN; - MXC_GPIO->out_val[port] |= 1 << pin; - } else { - new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z; - MXC_GPIO->out_val[port] &= ~(1 << pin); - } - } - - /* Set new mode */ - out_mode &= ~(0xF << (pin * 4)); - out_mode |= (new_mode << (pin * 4)); - MXC_GPIO->out_mode[port] = out_mode; -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/port_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/port_api.c deleted file mode 100644 index 2c72603bb7..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/port_api.c +++ /dev/null @@ -1,95 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "gpio_regs.h" -#include "clkman_regs.h" - -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)((port << PORT_SHIFT) | pin_n); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - obj->port = port; - obj->mask = mask; - obj->reg_out = &MXC_GPIO->out_val[port]; - obj->reg_in = &MXC_GPIO->in_val[port]; - - /* Ensure that the GPIO clock is enabled */ - MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1; - - uint32_t i; - // The function is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i)); - pin_dir(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - // The mode is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i), dir); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - return (*obj->reg_in & obj->mask); -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c deleted file mode 100644 index 61ea845185..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c +++ /dev/null @@ -1,228 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "cmsis.h" -#include "pwmout_api.h" -#include "pinmap.h" -#include "clkman_regs.h" -#include "PeripheralPins.h" - -//****************************************************************************** -void pwmout_init(pwmout_t *obj, PinName pin) -{ - // Make sure the pin is free for GPIO use - unsigned int port = (unsigned int)pin >> PORT_SHIFT; - unsigned int port_pin = (unsigned int)pin & ~(0xFFFFFFFF << PORT_SHIFT); - MBED_ASSERT(MXC_GPIO->free[port] & (0x1 << port_pin)); - - int i = 0; - PinMap pwm = PinMap_PWM[0]; - - // Check if there is a pulse train already active on this port - int pin_func = (MXC_GPIO->func_sel[port] & (0xF << (port_pin * 4))) >> (port_pin * 4); - MBED_ASSERT((pin_func < 1) || (pin_func > 3)); - - // Search through PinMap_PWM to find the pin - while (pwm.pin != pin) { - pwm = PinMap_PWM[++i]; - } - - // Find a free PT instance on this pin - while (pwm.pin == pin) { - - // Check to see if this PT instance is free - if (((mxc_pt_regs_t *)pwm.peripheral)->rate_length & MXC_F_PT_RATE_LENGTH_MODE) { - break; - } - - pwm = PinMap_PWM[++i]; - - // Raise an assertion if we can not allocate another PT instance. - MBED_ASSERT(pwm.pin == pin); - } - - // Enable the clock - MXC_CLKMAN->sys_clk_ctrl_7_pt = MXC_S_CLKMAN_CLK_SCALE_DIV_1; - - // Set the obj pointer to the propper PWM instance - obj->pwm = (mxc_pt_regs_t *)pwm.peripheral; - - // Initialize object period and pulse width - obj->period = -1; - obj->pulse_width = -1; - - // Disable the output - obj->pwm->train = 0x0; - obj->pwm->rate_length = 0x0; - - // Configure the pin - pin_mode(pin, (PinMode)PullNone); - pin_function(pin, pwm.function); - - // default to 20ms: standard for servos, and fine for e.g. brightness control - pwmout_period_us(obj, 20000); - pwmout_write(obj, 0); - - // Set the drive mode to normal - MXC_SET_FIELD(&MXC_GPIO->out_mode[port], (0x7 << (port_pin * 4)), (MXC_V_GPIO_OUT_MODE_NORMAL << (port_pin * 4))); - - // Enable this PWM channel - MXC_PTG->enable |= (1 << MXC_PT_GET_IDX(obj->pwm)); -} - -//****************************************************************************** -void pwmout_free(pwmout_t *obj) -{ - // Set the registers to the reset value - obj->pwm->train = 0; - obj->pwm->rate_length = 0x08000000; -} - -//****************************************************************************** -static void pwmout_update(pwmout_t *obj) -{ - // Calculate and set the divider ratio - int div = (obj->period * (SystemCoreClock / 1000000)) / 32; - if (div < 2) { - div = 2; - } - MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div); - - // Change the duty cycle to adjust the pulse width - obj->pwm->train = (0xFFFFFFFF << (32 - ((32 * obj->pulse_width) / obj->period))); -} - - -//****************************************************************************** -void pwmout_write(pwmout_t *obj, float percent) -{ - // Saturate percent if outside of range - if (percent < 0.0f) { - percent = 0.0f; - } else if (percent > 1.0f) { - percent = 1.0f; - } - - // Resize the pulse width to set the duty cycle - pwmout_pulsewidth_us(obj, (int)(percent * obj->period)); -} - -//****************************************************************************** -float pwmout_read(pwmout_t *obj) -{ - // Check for when pulsewidth or period equals 0 - if ((obj->pulse_width == 0) || (obj->period == 0)) { - return 0; - } - - // Return the duty cycle - return ((float)obj->pulse_width / (float)obj->period); -} - -//****************************************************************************** -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -//****************************************************************************** -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -//****************************************************************************** -void pwmout_period_us(pwmout_t *obj, int us) -{ - // Check the range of the period - MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock / 32))); - - // Set pulse width to half the period if uninitialized - if (obj->pulse_width == -1) { - obj->pulse_width = us / 2; - } - - // Save the period - obj->period = us; - - // Update the registers - pwmout_update(obj); -} - -//****************************************************************************** -int pwmout_read_period_us(pwmout_t *obj) -{ - return obj->period; -} - -//****************************************************************************** -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0f)); -} - -//****************************************************************************** -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -//****************************************************************************** -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - // Check the range of the pulsewidth - MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock / 32))); - - // Initialize period to double the pulsewidth if uninitialized - if (obj->period == -1) { - obj->period = 2 * us; - } - - // Save the pulsewidth - obj->pulse_width = us; - - // Update the register - pwmout_update(obj); -} - -//****************************************************************************** -int pwmout_read_pulsewidth_us(pwmout_t *obj) -{ - return obj->pulse_width; -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c deleted file mode 100644 index e6aa214687..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c +++ /dev/null @@ -1,313 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "rtc_api.h" -#include "lp_ticker_api.h" -#include "cmsis.h" -#include "rtc_regs.h" -#include "pwrseq_regs.h" -#include "clkman_regs.h" - -/** - * Defines clock divider for 4096Hz input clock. - */ -typedef enum { - /** (4kHz) divide input clock by 2^0 = 1 */ - MXC_E_RTC_PRESCALE_DIV_2_0 = 0, - /** (2kHz) divide input clock by 2^1 = 2 */ - MXC_E_RTC_PRESCALE_DIV_2_1, - /** (1kHz) divide input clock by 2^2 = 4 */ - MXC_E_RTC_PRESCALE_DIV_2_2, - /** (512Hz) divide input clock by 2^3 = 8 */ - MXC_E_RTC_PRESCALE_DIV_2_3, - /** (256Hz) divide input clock by 2^4 = 16 */ - MXC_E_RTC_PRESCALE_DIV_2_4, - /** (128Hz) divide input clock by 2^5 = 32 */ - MXC_E_RTC_PRESCALE_DIV_2_5, - /** (64Hz) divide input clock by 2^6 = 64 */ - MXC_E_RTC_PRESCALE_DIV_2_6, - /** (32Hz) divide input clock by 2^7 = 128 */ - MXC_E_RTC_PRESCALE_DIV_2_7, - /** (16Hz) divide input clock by 2^8 = 256 */ - MXC_E_RTC_PRESCALE_DIV_2_8, - /** (8Hz) divide input clock by 2^9 = 512 */ - MXC_E_RTC_PRESCALE_DIV_2_9, - /** (4Hz) divide input clock by 2^10 = 1024 */ - MXC_E_RTC_PRESCALE_DIV_2_10, - /** (2Hz) divide input clock by 2^11 = 2048 */ - MXC_E_RTC_PRESCALE_DIV_2_11, - /** (1Hz) divide input clock by 2^12 = 4096 */ - MXC_E_RTC_PRESCALE_DIV_2_12, -} mxc_rtc_prescale_t; - -#define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock -#define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL) - -#define WINDOW 1000 - -static int rtc_inited = 0; -static volatile uint32_t overflow_cnt = 0; - -static uint64_t rtc_read64(void); - -//****************************************************************************** -static void overflow_handler(void) -{ - MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; - overflow_cnt++; - - // Wait for pending transactions - while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); -} - -//****************************************************************************** -void rtc_init(void) -{ - if (rtc_inited) { - return; - } - rtc_inited = 1; - - overflow_cnt = 0; - - // Enable the clock to the synchronizer - MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DIV_1; - - // Enable the clock to the RTC - MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; - - // Prepare interrupt handlers - NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler); - NVIC_EnableIRQ(RTC0_IRQn); - NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler); - NVIC_EnableIRQ(RTC3_IRQn); - - // Enable wakeup on RTC rollover - MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER; - - /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC - * if it is already running. - */ - if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) { - // Set the clock divider - MXC_RTCTMR->prescale = PRESCALE_VAL; - - // Enable the overflow interrupt - MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW; - - // Restart the timer from 0 - MXC_RTCTMR->timer = 0; - - // Enable the RTC - MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; - } -} - -//****************************************************************************** -void lp_ticker_init(void) -{ - rtc_init(); -} - -//****************************************************************************** -void rtc_free(void) -{ - if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) { - // Clear and disable RTC - MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR; - MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; - - // Wait for pending transactions - while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); - } - - // Disable the clock to the RTC - MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); - - // Disable the clock to the synchronizer - MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DISABLED; -} - -//****************************************************************************** -int rtc_isenabled(void) -{ - return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE); -} - -//****************************************************************************** -time_t rtc_read(void) -{ - uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; - uint32_t ovf1, ovf2; - - // Make sure RTC is setup before trying to read - if (!rtc_inited) { - rtc_init(); - } - - // Ensure coherency between overflow_cnt and timer - do { - ovf_cnt_1 = overflow_cnt; - ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW; - timer_cnt = MXC_RTCTMR->timer; - ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW; - ovf_cnt_2 = overflow_cnt; - } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2)); - - // Account for an unserviced interrupt - if (ovf1) { - ovf_cnt_1++; - } - - return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT)); -} - -//****************************************************************************** -static uint64_t rtc_read64(void) -{ - uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; - uint32_t ovf1, ovf2; - uint64_t current_us; - - // Make sure RTC is setup before trying to read - if (!rtc_inited) { - rtc_init(); - } - - // Ensure coherency between overflow_cnt and timer - do { - ovf_cnt_1 = overflow_cnt; - ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW; - timer_cnt = MXC_RTCTMR->timer; - ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW; - ovf_cnt_2 = overflow_cnt; - } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2)); - - // Account for an unserviced interrupt - if (ovf1) { - ovf_cnt_1++; - } - - current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT)); - - return current_us; -} - -//****************************************************************************** -void rtc_write(time_t t) -{ - // Make sure RTC is setup before accessing - if (!rtc_inited) { - rtc_init(); - } - - MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating - MXC_RTCTMR->timer = t << SHIFT_AMT; - overflow_cnt = t >> (32 - SHIFT_AMT); - MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating -} - -//****************************************************************************** -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - uint32_t comp_value; - uint64_t curr_ts64; - uint64_t ts64; - - // Note: interrupts are disabled before this function is called. - - // Disable the alarm while it is prepared - MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; - - curr_ts64 = rtc_read64(); - ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL); - - // If this event is older than a recent window, it must be in the future - if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) { - ts64 += 0x100000000ULL; - } - - uint32_t timer = MXC_RTCTMR->timer; - if (ts64 <= curr_ts64) { - // This event has already occurred. Set the alarm to expire immediately. - comp_value = timer + 1; - } else { - comp_value = (ts64 << SHIFT_AMT) / 1000000; - } - - // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs. - if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) { - comp_value = timer + 2; - } - - MXC_RTCTMR->comp[0] = comp_value; - MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; - MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt - - // Enable wakeup from RTC - MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0; - - // Wait for pending transactions - while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); -} - -void lp_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(RTC0_IRQn); -} - -//****************************************************************************** -inline void lp_ticker_disable_interrupt(void) -{ - MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; -} - -//****************************************************************************** -inline void lp_ticker_clear_interrupt(void) -{ - MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; - - // Wait for pending transactions - while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); -} - -//****************************************************************************** -inline uint32_t lp_ticker_read(void) -{ - return rtc_read64(); -} - -void lp_ticker_free(void) -{ - -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c deleted file mode 100644 index 64970e2069..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c +++ /dev/null @@ -1,511 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include -#include "mbed_assert.h" -#include "cmsis.h" -#include "serial_api.h" -#include "uart_regs.h" -#include "ioman_regs.h" -#include "gpio_api.h" -#include "clkman_regs.h" -#include "PeripheralPins.h" - -#define DEFAULT_BAUD 9600 -#define DEFAULT_STOP 1 -#define DEFAULT_PARITY ParityNone - -#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \ - MXC_F_UART_INTFL_RX_PARITY_ERR | \ - MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) - -// Variables for managing the stdio UART -int stdio_uart_inited; -serial_t stdio_uart; - -// Variables for interrupt driven -static uart_irq_handler irq_handler; -static uint32_t serial_irq_ids[MXC_CFG_UART_INSTANCES]; - -//****************************************************************************** -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine which uart is associated with each pin - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - - // Make sure that both pins are pointing to the same uart - MBED_ASSERT(uart != (UARTName)NC); - - // Ensure that the UART clock is enabled - switch (uart) { - case UART_0: - MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER; - break; - case UART_1: - MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER; - break; - case UART_2: - MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER; - break; - case UART_3: - MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER; - break; - default: - break; - } - - // Ensure that the UART clock is enabled - // But don't override the scaler - // - // To support the most common baud rates, 9600 and 115200, we need to - // scale down the uart input clock. - if (!(MXC_CLKMAN->sys_clk_ctrl_8_uart & MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE)) { - - switch (SystemCoreClock) { - case RO_FREQ: - MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4; - break; - case (RO_FREQ / 2): - MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_2; - break; - default: - MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4; - break; - } - } - - // Set the obj pointer to the proper uart - obj->uart = (mxc_uart_regs_t*)uart; - - // Set the uart index - obj->index = MXC_UART_GET_IDX(obj->uart); - obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index); - - // Configure the pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - // Flush the RX and TX FIFOs, clear the settings - obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN); - obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN); - - // Disable interrupts - obj->uart->inten = 0; - obj->uart->intfl = obj->uart->intfl; - - // Configure to default settings - serial_baud(obj, DEFAULT_BAUD); - serial_format(obj, 8, ParityNone, 1); - - // Manage stdio UART - if (uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - - // Enable UART - obj->uart->ctrl |= MXC_F_UART_CTRL_UART_EN; -} - -//****************************************************************************** -void serial_baud(serial_t *obj, int baudrate) -{ - uint32_t baud_setting = 0; - - MBED_ASSERT(MXC_CLKMAN->sys_clk_ctrl_8_uart > MXC_S_CLKMAN_CLK_SCALE_DISABLED); - - // Calculate the integer and decimal portions - baud_setting = SystemCoreClock / (1<<(MXC_CLKMAN->sys_clk_ctrl_8_uart-1)); - baud_setting = baud_setting / (baudrate * 16); - - // If the result doesn't fit in the register - MBED_ASSERT(baud_setting <= UINT8_MAX); - - obj->uart->baud = baud_setting; -} - -//****************************************************************************** -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - // Check the validity of the inputs - MBED_ASSERT((data_bits > 4) && (data_bits < 9)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || - (parity == ParityEven) || (parity == ParityForced1) || - (parity == ParityForced0)); - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - - // Adjust the stop and data bits - stop_bits -= 1; - data_bits -= 5; - - // Adjust the parity setting - int mode = 0; - switch (parity) { - case ParityNone: - mode = 0; - break; - case ParityOdd : - mode = 1; - break; - case ParityEven: - mode = 2; - break; - case ParityForced1: - // Hardware does not support forced parity - MBED_ASSERT(0); - break; - case ParityForced0: - // Hardware does not support forced parity - MBED_ASSERT(0); - break; - default: - mode = 0; - break; - } - - int temp = obj->uart->ctrl; - temp &= ~(MXC_F_UART_CTRL_DATA_SIZE | MXC_F_UART_CTRL_EXTRA_STOP | MXC_F_UART_CTRL_PARITY); - temp |= (data_bits << MXC_F_UART_CTRL_DATA_SIZE_POS); - temp |= (stop_bits << MXC_F_UART_CTRL_EXTRA_STOP_POS); - temp |= (mode << MXC_F_UART_CTRL_PARITY_POS); - obj->uart->ctrl = temp; -} - -//****************************************************************************** -void uart_handler(mxc_uart_regs_t* uart, int id) -{ - // Check for errors or RX Threshold - if (uart->intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) { - if (serial_irq_ids[id]) { - irq_handler(serial_irq_ids[id], RxIrq); - } - uart->intfl = (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); - } - - // Check for TX Threshold - if (uart->intfl & MXC_F_UART_INTFL_TX_FIFO_AE) { - if (serial_irq_ids[id]) { - irq_handler(serial_irq_ids[id], TxIrq); - } - uart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE; - } -} - -void uart0_handler(void) { uart_handler(MXC_UART0, 0); } -void uart1_handler(void) { uart_handler(MXC_UART1, 1); } -void uart2_handler(void) { uart_handler(MXC_UART2, 2); } -void uart3_handler(void) { uart_handler(MXC_UART3, 3); } - -//****************************************************************************** -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -//****************************************************************************** -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - switch (obj->index) { - case 0: - NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); - NVIC_EnableIRQ(UART0_IRQn); - break; - case 1: - NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); - NVIC_EnableIRQ(UART1_IRQn); - break; - case 2: - NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler); - NVIC_EnableIRQ(UART2_IRQn); - break; - case 3: - NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler); - NVIC_EnableIRQ(UART3_IRQn); - break; - default: - MBED_ASSERT(0); - } - - if (irq == RxIrq) { - // Enable RX FIFO Threshold Interrupt - if (enable) { - // Clear pending interrupts - obj->uart->intfl = obj->uart->intfl; - obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); - } else { - // Clear pending interrupts - obj->uart->intfl = obj->uart->intfl; - obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); - } - - } else if (irq == TxIrq) { - // Set TX Almost Empty level to interrupt when empty - MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL, - (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS); - - // Enable TX Almost Empty Interrupt - if (enable) { - // Clear pending interrupts - obj->uart->intfl = obj->uart->intfl; - obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE; - } else { - // Clear pending interrupts - obj->uart->intfl = obj->uart->intfl; - obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE; - } - - } else { - MBED_ASSERT(0); - } -} - - -//****************************************************************************** -int serial_getc(serial_t *obj) -{ - int c; - - // Wait for data to be available - while ((obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) == 0); - - c = *obj->fifo->rx_8; - - return c; -} - -//****************************************************************************** -void serial_putc(serial_t *obj, int c) -{ - // Wait for TXFIFO to not be full - while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) - >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) - >= MXC_UART_FIFO_DEPTH ); - - // Must clear before every write to the buffer to know that the fifo - // is empty when the TX DONE bit is set - obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE; - *obj->fifo->tx_8 = (uint8_t)c; -} - -//****************************************************************************** -int serial_readable(serial_t *obj) -{ - return (obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY); -} - -//****************************************************************************** -int serial_writable(serial_t *obj) -{ - return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) - >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) - < MXC_UART_FIFO_DEPTH ); -} - -//****************************************************************************** -void serial_clear(serial_t *obj) -{ - // Clear the rx and tx fifos - obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN); - obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN); -} - - -//****************************************************************************** -void serial_break_set(serial_t *obj) -{ - // Make sure that nothing is being sent - while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) - >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0); - while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE)); - - // Configure the GPIO to output 0 - gpio_t tx_gpio; - switch (((UARTName)(obj->uart))) { - case UART_0: - gpio_init_out(&tx_gpio, UART0_TX); - break; - case UART_1: - gpio_init_out(&tx_gpio, UART1_TX); - break; - case UART_2: - gpio_init_out(&tx_gpio, UART2_TX); - break; - case UART_3: - gpio_init_out(&tx_gpio, UART3_TX); - break; - default: - gpio_init_out(&tx_gpio, (PinName)NC); - break; - } - - gpio_write(&tx_gpio, 0); - - // GPIO is setup now, but we need to map GPIO to the pin - switch (((UARTName)(obj->uart))) { - case UART_0: - MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ; - MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0); - break; - case UART_1: - MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ; - MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0); - break; - case UART_2: - MXC_IOMAN->uart2_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ; - MBED_ASSERT((MXC_IOMAN->uart2_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0); - break; - case UART_3: - MXC_IOMAN->uart3_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ; - MBED_ASSERT((MXC_IOMAN->uart3_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0); - break; - default: - break; - } -} - -//****************************************************************************** -void serial_break_clear(serial_t *obj) -{ - // Configure the GPIO to output 1 - gpio_t tx_gpio; - switch (((UARTName)(obj->uart))) { - case UART_0: - gpio_init_out(&tx_gpio, UART0_TX); - break; - case UART_1: - gpio_init_out(&tx_gpio, UART1_TX); - break; - case UART_2: - gpio_init_out(&tx_gpio, UART2_TX); - break; - case UART_3: - gpio_init_out(&tx_gpio, UART3_TX); - break; - default: - gpio_init_out(&tx_gpio, (PinName)NC); - break; - } - - gpio_write(&tx_gpio, 1); - - // Renable UART - switch (((UARTName)(obj->uart))) { - case UART_0: - serial_pinout_tx(UART0_TX); - break; - case UART_1: - serial_pinout_tx(UART1_TX); - break; - case UART_2: - serial_pinout_tx(UART2_TX); - break; - case UART_3: - serial_pinout_tx(UART3_TX); - break; - default: - serial_pinout_tx((PinName)NC); - break; - } -} - -//****************************************************************************** -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -//****************************************************************************** -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - uint32_t ctrl = obj->uart->ctrl; - - // Disable hardware flow control - ctrl &= ~(MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_CTS_EN); - - if (FlowControlNone != type) { - // Check to see if we can use HW flow control - UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); - UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); - UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts); - - // Make sure that the pins are pointing to the same UART - MBED_ASSERT(uart != (UARTName)NC); - - if ((FlowControlCTS == type) || (FlowControlRTSCTS == type)) { - // Make sure pin is in the PinMap - MBED_ASSERT(uart_cts != (UARTName)NC); - - // Enable the pin for CTS function - pinmap_pinout(txflow, PinMap_UART_CTS); - - // Enable active-low hardware flow control - ctrl |= (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_CTS_POLARITY); - } - - if ((FlowControlRTS == type) || (FlowControlRTSCTS == type)) { - // Make sure pin is in the PinMap - MBED_ASSERT(uart_rts != (UARTName)NC); - - // Enable the pin for RTS function - pinmap_pinout(rxflow, PinMap_UART_RTS); - - // Enable active-low hardware flow control - ctrl |= (MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_RTS_POLARITY); - } - } - - obj->uart->ctrl = ctrl; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c b/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c deleted file mode 100644 index 35c3d72936..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c +++ /dev/null @@ -1,219 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "sleep_api.h" -#include "pwrman_regs.h" -#include "pwrseq_regs.h" -#include "clkman_regs.h" -#include "ioman_regs.h" -#include "rtc_regs.h" -#include "usb_regs.h" - -#define REVISION_A3 2 -#define REVISION_A4 3 - -// USB state to be restored upon wakeup -typedef struct { - uint32_t dev_cn; - uint32_t dev_inten; - uint32_t ep_base; - uint32_t ep[MXC_USB_NUM_EP]; -} usb_state_t; - -static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART; -static int restore_usb; -static usb_state_t usb_state; - -void hal_sleep(void) -{ - // Normal sleep mode for ARM core - SCB->SCR = 0; - - __DSB(); - __WFI(); -} - -static void usb_sleep(void) -{ - int i; - - if (MXC_USB->cn & MXC_F_USB_CN_USB_EN) { - // The USB module will not survive Deep Sleep. - - // Save the USB state to restore it upon wakeup - usb_state.dev_cn = MXC_USB->dev_cn; - usb_state.dev_inten = MXC_USB->dev_inten; - usb_state.ep_base = MXC_USB->ep_base; - for (i = 0; i < MXC_USB_NUM_EP; i++) { - usb_state.ep[i] = MXC_USB->ep[i] & (MXC_F_USB_EP_DIR | MXC_F_USB_EP_BUF2 | MXC_F_USB_EP_INT_EN | MXC_F_USB_EP_NAK_EN); - } - restore_usb = 1; - - // Shut down the USB module. - MXC_USB->dev_inten = 0; - MXC_USB->dev_cn = 0; - MXC_USB->cn = 0; - restore_usb = 1; // USB should be restored upon wakeup - } else { - restore_usb = 0; - } -} - -// Restore the USB module state. -static void usb_wakeup(void) -{ - int i; - - if (restore_usb) { - MXC_USB->cn = MXC_F_USB_CN_USB_EN; - MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST; - MXC_USB->dev_cn = 0; - for (i = 0; i < MXC_USB_NUM_EP; i++) { - MXC_USB->ep[i] = usb_state.ep[i]; - } - MXC_USB->ep_base = usb_state.ep_base; - MXC_USB->dev_cn = usb_state.dev_cn; - MXC_USB->dev_inten = usb_state.dev_inten; - restore_usb = 0; - } -} - -// Low-power stop mode -void hal_deepsleep(void) -{ - unsigned int part_rev = MXC_PWRMAN->mask_id0 & MXC_F_PWRMAN_MASK_ID0_REVISION_ID; - - // Deep Sleep is not working properly on Revisions A3 and earlier - if (part_rev <= REVISION_A3) { - hal_sleep(); - return; - } - - // Wait for all STDIO characters to be sent. The UART clock will stop. - while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) || - !(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE)); - - __disable_irq(); - - // Do not enter Deep Sleep if connected to VBUS - if (MXC_USB->dev_intfl & MXC_F_USB_DEV_INTFL_VBUS_ST) { - __enable_irq(); - hal_sleep(); - return; - } - - // The USB module will not survive Deep Sleep. Shut it down. - usb_sleep(); - - // Make sure RTC is not pending before sleeping, if its still synchronizing - // we might not wake up. - while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); - - // Clear any active GPIO Wake Up Events - if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP) { - // NOTE: These must be cleared before clearing IOWAKEUP - MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH; - MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH; - - MXC_PWRSEQ->flags |= MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP; - } - - // Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP - if (part_rev == REVISION_A4) { - MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_LP1; // A4 requires part to go to pseudo LP0 - } else { - MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; - } - - // The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - if (part_rev == REVISION_A4) { - // WORKAROUND: Toggle SVM bits, which send extra clocks to the power sequencer to fix retention controller - MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD; - MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN); - MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN; - MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD; - } - - // Enable Retention controller - MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN; - - // Clear the firstboot bit, which is generated by a POR event and locks out LPx modes - MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; - - // Freeze GPIO using MBUS so that it doesn't flail while digital core is asleep - MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE; - - // Dummy read to make sure SSB writes are complete - MXC_PWRSEQ->reg0 = MXC_PWRSEQ->reg0; - - if (part_rev == REVISION_A4) { - // Note: ARM deep-sleep requires a specific sequence to clear event latches, - // otherwise the CPU will not enter sleep. - __SEV(); - __WFE(); - __WFI(); - } else { - // Note: ARM deep-sleep requires a specific sequence to clear event latches, - // otherwise the CPU will not enter sleep. - __SEV(); - __WFE(); - __WFE(); - } - - // We'll wakeup here ... - - // Unfreeze the GPIO by clearing MBUS_GATE - MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE; - - usb_wakeup(); - - // Clear power sequencer event flags (write-1-to-clear) - // RTC and GPIO flags are cleared in their interrupts handlers - // NOTE: We are ignoring all of these potential wake up types - MXC_PWRSEQ->flags = (MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL | - MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL | - MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE | - MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD | - MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD | - MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD | - MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD | - MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD | - MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH | - MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP | - MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP | - MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD); - - __enable_irq(); -} diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c deleted file mode 100644 index cae5f12139..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c +++ /dev/null @@ -1,615 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include -#include "mbed_assert.h" -#include "cmsis.h" -#include "spi_api.h" -#include "spi_multi_api.h" -#include "pinmap.h" -#include "ioman_regs.h" -#include "clkman_regs.h" -#include "PeripheralPins.h" - -#define DEFAULT_CHAR 8 -#define DEFAULT_MODE 0 -#define DEFAULT_FREQ 1000000 - -// BYTE maximums for FIFO and page writes; FIFO depth spec'd as 16-bit words -#define SPI_MAX_BYTE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2) -#define SPI_MAX_PAGE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2) - -#if DEVICE_SPI_ASYNCH -// Instance references for async transactions -static struct spi_s *state[MXC_CFG_SPI_INSTANCES] = {NULL}; -#endif - -//****************************************************************************** -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Make sure pins are pointing to the same SPI instance - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl; - - // Give the application the option to manually control Slave Select - if ((SPIName)spi_ssel != (SPIName)NC) { - spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - // Slave select is currently limited to slave select zero. If others are - // to be supported a function to map PinName to a value suitable for use - // in mstr_cfg.slave_sel will be required. - obj->spi.ssel = 0; - } else { - spi_cntl = spi_sclk; - obj->spi.ssel = -1; - } - - SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - - MBED_ASSERT((SPIName)spi != (SPIName)NC); - - // Set the obj pointer to the proper SPI Instance - obj->spi.spi = (mxc_spi_regs_t*)spi; - - // Set the SPI index and FIFOs - obj->spi.index = MXC_SPI_GET_IDX(obj->spi.spi); - obj->spi.fifo = MXC_SPI_GET_SPI_FIFO(obj->spi.index); - - // Configure the pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - pinmap_pinout(ssel, PinMap_SPI_SSEL); - -#if DEVICE_SPI_ASYNCH - // Configure default page size; size is known to async interface - obj->spi.spi->mstr_cfg = (obj->spi.spi->mstr_cfg & ~MXC_F_SPI_MSTR_CFG_PAGE_SIZE) | MXC_S_SPI_MSTR_CFG_PAGE_32B; -#endif - - // Enable SPI and FIFOs - obj->spi.spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN | - MXC_F_SPI_GEN_CTRL_TX_FIFO_EN | - MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ); - - obj->spi.sclk = sclk; // save the sclk PinName in the object as a key for Quad SPI pin mapping lookup - spi_master_width(obj, 0); // default this for Single SPI communications -} - -//****************************************************************************** -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Check the validity of the inputs - MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3))); - - // Only supports master mode - MBED_ASSERT(!slave); - - // Save formatting data - obj->spi.bits = bits; - - // Set the mode - MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, MXC_F_SPI_MSTR_CFG_SPI_MODE, mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS); -} - -//****************************************************************************** -void spi_frequency(spi_t *obj, int hz) -{ - // Maximum frequency is half the system frequency - MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2)); - unsigned clocks = ((SystemCoreClock / 2) / hz); - - // Figure out the divider ratio - int clk_div = 1; - while (clk_div < 10) { - if (clocks < 0x10) { - break; - } - clk_div++; - clocks = clocks >> 1; - } - - // Turn on the SPI clock - if (obj->spi.index == 0) { - MXC_CLKMAN->sys_clk_ctrl_11_spi0 = clk_div; - } else if (obj->spi.index == 1) { - MXC_CLKMAN->sys_clk_ctrl_12_spi1 = clk_div; - } else if (obj->spi.index == 2) { - MXC_CLKMAN->sys_clk_ctrl_13_spi2 = clk_div; - } else { - MBED_ASSERT(0); - } - - // Set the number of clocks to hold sclk high and low - MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK), - ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))); -} - -//****************************************************************************** -void spi_master_width(spi_t *obj, SpiWidth width) -{ - // Save the width to be used in the SPI header - switch (width) { - case WidthSingle: - obj->spi.width = MXC_S_SPI_FIFO_WIDTH_SINGLE; - break; - case WidthDual: - obj->spi.width = MXC_S_SPI_FIFO_WIDTH_DUAL; - break; - case WidthQuad: - obj->spi.width = MXC_S_SPI_FIFO_WIDTH_QUAD; - // do pin mapping for SDIO[2] and SDIO[3] if Quad SPI is selected - pinmap_pinout(obj->spi.sclk, PinMap_SPI_QUAD); - break; - default: - MBED_ASSERT(0); - } -} - -//****************************************************************************** -/** Performs a master write or read transaction - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] value The value to send - * @param[in] direction Direction of the transaction, TX, RX or both - * @return Returns the value received during send - */ -static int spi_master_transaction(spi_t *obj, int value, uint32_t direction) -{ - int bits; - - // Create the header - uint16_t header = (direction | // direction based on SPI object - MXC_S_SPI_FIFO_UNIT_BITS | // unit size - ((obj->spi.bits == 32) ? 0 : obj->spi.bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units - obj->spi.width | // I/O width - ((obj->spi.ssel == -1) ? 0 : 1 << MXC_F_SPI_FIFO_DASS_POS)); - - // Send the message header - *obj->spi.fifo->trans_16 = header; - - // Send the data - if (obj->spi.bits < 17) { - *obj->spi.fifo->trans_16 = (uint16_t)value; - } else { - *obj->spi.fifo->trans_32 = (uint32_t)value; - } - - // Get the data - bits = obj->spi.bits; - int result = 0; - int i = 0; - while (bits > 0) { - // Wait for data - while (((obj->spi.spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) - >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1); - - result |= (*obj->spi.fifo->rslts_8 << (i++*8)); - bits-=8; - } - - return result; -} - -//****************************************************************************** -int spi_master_write(spi_t *obj, int value) -{ - // set the fifo direction for full duplex, TX and RX simultaneously - return spi_master_transaction(obj, value, MXC_S_SPI_FIFO_DIR_BOTH); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -//****************************************************************************** -int spi_master_read(spi_t *obj) -{ - return spi_master_transaction(obj, 0xFF, MXC_S_SPI_FIFO_DIR_RX); -} - -//****************************************************************************** -// spi_busy() is part of the synchronous API, it is not used by the asynchronous API. -int spi_busy(spi_t *obj) -{ - return !(obj->spi.spi->intfl & MXC_F_SPI_INTFL_TX_READY); -} - -#if DEVICE_SPI_ASYNCH -//****************************************************************************** -static uint32_t spi_master_read_rxfifo(mxc_spi_regs_t *spim, mxc_spi_fifo_regs_t *fifo, uint8_t *data, uint32_t len) -{ - uint32_t num = 0; - uint32_t avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS); - - // Get data from the RXFIFO - while (avail && (len - num)) { - // Save data from the RXFIFO - if ((avail >= 4) && ((len - num) >= 4)) { - uint32_t temp = *fifo->rslts_32; - data[num++] = temp; - data[num++] = temp >> 8; - data[num++] = temp >> 16; - data[num++] = temp >> 24; - avail -= 4; - } else if ((avail >= 2) && ((len - num) >= 2)) { - uint16_t temp = *fifo->rslts_16; - data[num++] = temp; - data[num++] = temp >> 8; - avail -= 2; - } else { - data[num++] = *fifo->rslts_8; - avail--; - } - - // Check to see if there is more data in the FIFO - if (avail == 0) { - avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS); - } - } - - return num; -} - -//****************************************************************************** -static uint32_t spi_master_transfer_handler(spi_t *obj) -{ - uint8_t read; - uint8_t write; - uint16_t header; - uint32_t pages; - uint32_t bytes; - uint32_t inten; - unsigned remain; - unsigned bytes_read; - unsigned head_rem_temp; - unsigned avail; - struct spi_s *req = &obj->spi; - mxc_spi_regs_t *spim = obj->spi.spi; - mxc_spi_fifo_regs_t *fifo = obj->spi.fifo; - - inten = 0; - - // Figure out if we're reading - read = (req->rx_data != NULL) ? 1 : 0; - - // Figure out if we're writing - write = (req->tx_data != NULL) ? 1 : 0; - - // Read byte from the FIFO if we are reading - if (read) { - - // Read all of the data in the RXFIFO, or until we don't need anymore - bytes_read = spi_master_read_rxfifo(spim, fifo, &req->rx_data[req->read_num], (req->len - req->read_num)); - - req->read_num += bytes_read; - - // Adjust head_rem if we are only reading - if (!write && (req->head_rem > 0)) { - req->head_rem -= bytes_read; - } - - // Figure out how many bytes we have left to read - if (req->head_rem > 0) { - remain = req->head_rem; - } else { - remain = req->len - req->read_num; - } - - if (remain) { - - // Set the RX interrupts - if (remain > MXC_CFG_SPI_FIFO_DEPTH) { - spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) | - ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS)); - } else { - spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) | - ((remain - 1) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS)); - } - - inten |= MXC_F_SPI_INTEN_RX_FIFO_AF; - } - } - - // Figure out how many bytes we have left to send headers for - if (write) { - remain = req->len - req->write_num; - } else { - remain = req->len - req->read_num; - } - - // See if we need to send a new header - if ((req->head_rem <= 0) && remain) { - - // Set the transaction configuration in the header - header = ((write | (read << 1)) << MXC_F_SPI_FIFO_DIR_POS) | (req->width << MXC_F_SPI_FIFO_WIDTH_POS); - - if (remain >= SPI_MAX_BYTE_LEN) { - - // Send a 32 byte header - if (remain == SPI_MAX_BYTE_LEN) { - - header |= (MXC_S_SPI_FIFO_UNIT_BYTES | MXC_F_SPI_FIFO_DASS); - - // Save the number of bytes we need to write to the FIFO - bytes = SPI_MAX_BYTE_LEN; - - } else { - // Send in increments of 32 byte pages - header |= MXC_S_SPI_FIFO_UNIT_PAGES; - pages = remain / SPI_MAX_PAGE_LEN; - - if (pages >= 32) { - // 0 maps to 32 in the header - bytes = 32 * SPI_MAX_PAGE_LEN; - } else { - header |= (pages << MXC_F_SPI_FIFO_SIZE_POS); - bytes = pages * SPI_MAX_PAGE_LEN; - } - - // Check if this is the last header we will send - if ((remain - bytes) == 0) { - header |= MXC_F_SPI_FIFO_DASS; - } - } - - fifo->trans_16[0] = header; - - // Save the number of bytes we need to write to the FIFO - req->head_rem = bytes; - - } else { - // Send final header with the number of bytes remaining and de-assert the SS at the end of the transaction - header |= (MXC_S_SPI_FIFO_UNIT_BYTES | (remain << MXC_F_SPI_FIFO_SIZE_POS) | MXC_F_SPI_FIFO_DASS); - fifo->trans_16[0] = header; - req->head_rem = remain; - } - } - - // Put data into the FIFO if we are writing - remain = req->len - req->write_num; - head_rem_temp = req->head_rem; - if (write && head_rem_temp) { - - // Fill the FIFO - avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS)); - - // Use memcpy for everything except the last byte in odd length transactions - while ((avail >= 2) && (head_rem_temp >= 2)) { - - unsigned length; - if (head_rem_temp < avail) { - length = head_rem_temp; - } else { - length = avail; - } - - // Only memcpy even numbers - length = ((length / 2) * 2); - - memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length); - - head_rem_temp -= length; - req->write_num += length; - - avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS)); - } - - // Copy the last byte and pad with 0xF0 to not get confused as header - if ((avail >= 1) && (head_rem_temp == 1)) { - - // Write the last byte - fifo->trans_16[0] = (0xF000 | req->tx_data[req->write_num]); - - avail -= 1; - req->write_num += 1; - head_rem_temp -= 1; - } - - req->head_rem = head_rem_temp; - remain = req->len - req->write_num; - - // Set the TX interrupts - if (remain) { - - // Set the TX FIFO almost empty interrupt if we have to refill - spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL) | - ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS)); - - inten |= MXC_F_SPI_INTEN_TX_FIFO_AE; - } - } - - // Check to see if we've finished reading and writing - if (((read && (req->read_num == req->len)) || !read) && - ((req->write_num == req->len) || !write)) { - - // Disable interrupts - spim->inten = 0; - } - - // Enable the SPIM interrupts - return inten; -} - -//****************************************************************************** -void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - MBED_ASSERT(tx_length == rx_length); - MBED_ASSERT(bit_width == obj->spi.bits); - - // Save object reference for callback - state[obj->spi.index] = &obj->spi; - - // Initialize request info - obj->spi.tx_data = tx; - obj->spi.rx_data = rx; - obj->spi.len = tx_length; - obj->spi.callback = (void(*)())handler; - obj->spi.event = event; - // Clear transfer state - obj->spi.read_num = 0; - obj->spi.write_num = 0; - obj->spi.head_rem = 0; - - NVIC_EnableIRQ(MXC_SPI_GET_IRQ(obj->spi.index)); - - obj->spi.spi->inten = spi_master_transfer_handler(obj); -} - -//****************************************************************************** -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - mxc_spi_regs_t *spim = obj->spi.spi; - uint32_t flags; - - // Clear the interrupt flags - spim->inten = 0; - flags = spim->intfl; - spim->intfl = flags; - - // Figure out if this SPIM has an active request - if (flags) { - if ((spim->inten = spi_master_transfer_handler(obj)) != 0) { - return 0; - } - } - - state[obj->spi.index] = NULL; - - return SPI_EVENT_COMPLETE; -} - -//****************************************************************************** -uint8_t spi_active(spi_t *obj) -{ - mxc_spi_regs_t *spim = obj->spi.spi; - - // Check to see if there are any ongoing transactions - if ((state[obj->spi.index] == NULL) && - !(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) { - return 0; - } - - return 1; -} - -//****************************************************************************** -void spi_abort_asynch(spi_t *obj) -{ - mxc_spi_regs_t *spim = obj->spi.spi; - - // Disable interrupts, clear the flags - spim->inten = 0; - spim->intfl = spim->intfl; - - // Reset the SPIM to cancel the on ongoing transaction - spim->gen_ctrl &= ~(MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN); - spim->gen_ctrl |= (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN); - - state[obj->spi.index] = NULL; -} - -//****************************************************************************** -static void SPI_IRQHandler(int spim_num) -{ - if (state[spim_num] != NULL) { - if (state[spim_num]->callback != NULL) { - state[spim_num]->callback(); - return; - } - } - mxc_spi_regs_t *spim = MXC_SPI_GET_SPI(spim_num); - spim->inten = 0; -} - -//****************************************************************************** -void SPI0_IRQHandler(void) { SPI_IRQHandler(0); } -void SPI1_IRQHandler(void) { SPI_IRQHandler(1); } -void SPI2_IRQHandler(void) { SPI_IRQHandler(2); } - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/spi_multi_api.h b/targets/TARGET_Maxim/TARGET_MAX32620/spi_multi_api.h deleted file mode 100644 index 9e6e37318f..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/spi_multi_api.h +++ /dev/null @@ -1,67 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef MBED_SPI_MULTI_H -#define MBED_SPI_MULTI_H - -#include "spi_api.h" - -typedef enum { - WidthSingle = 0, - WidthDual = 1, - WidthQuad = 2, -} SpiWidth; - -#ifdef __cplusplus -extern "C" { -#endif - -/** Read a byte in master mode, this is use for Dual or Quad SPI when a simplex transfer is needed - * - * @param[in] obj The SPI peripheral to use for sending - * @return Returns the value received - */ -int spi_master_read(spi_t *obj); - -/** Specify I/O width of SPI transaction - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] width The I/O width of SPI transaction - */ -void spi_master_width(spi_t *obj, SpiWidth width); - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // MBED_SPI_MULTI_H diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c deleted file mode 100644 index 6047576e29..0000000000 --- a/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c +++ /dev/null @@ -1,306 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#include "mbed_error.h" -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "tmr_regs.h" -#include "clkman_regs.h" - -#define US_TIMER MXC_TMR0 -#define US_TIMER_IRQn TMR0_0_IRQn - -/** - * Defines timer modes for 16 and 32-bit timers - */ -typedef enum { - /** 32-bit or 16-bit timer one-shot mode */ - MXC_E_TMR_MODE_ONE_SHOT = 0, - /** 32-bit or 16-bit timer one-shot mode */ - MXC_E_TMR_MODE_CONTINUOUS, - /** 32-bit timer counter mode */ - MXC_E_TMR_MODE_COUNTER, - /** 32-bit timer pulse width modulation mode */ - MXC_E_TMR_MODE_PWM, - /** 32-bit timer capture mode */ - MXC_E_TMR_MODE_CAPTURE, - /** 32-bit timer compare mode */ - MXC_E_TMR_MODE_COMPARE, - /** 32-bit timer gated mode */ - MXC_E_TMR_MODE_GATED, - /** 32-bit timer measure mode */ - MXC_E_TMR_MODE_MEASURE -} mxc_tmr_mode_t; - -static int us_ticker_inited = 0; -static uint32_t ticks_per_us; -static uint32_t tick_win; -static volatile uint64_t current_cnt; // Hold the current ticks -static volatile uint64_t event_cnt; // Holds the value of the next event - -#define ticks_to_us(ticks) ((ticks) / ticks_per_us); -#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us) - -//****************************************************************************** -static inline void inc_current_cnt(uint32_t inc) -{ - - // Overflow the ticker when the us ticker overflows - current_cnt += inc; - if (current_cnt > MAX_TICK_VAL) { - current_cnt -= (MAX_TICK_VAL + 1); - } -} - -//****************************************************************************** -static inline int event_passed(uint64_t current, uint64_t event) -{ - - // Determine if the event has already happened. - // If the event is behind the current ticker, within a window, - // then the event has already happened. - if (((current < tick_win) && ((event < current) || - (event > (MAX_TICK_VAL - (tick_win - current))))) || - ((event < current) && (event > (current - tick_win)))) { - return 1; - } - - return 0; -} - -//****************************************************************************** -static inline uint64_t event_diff(uint64_t current, uint64_t event) -{ - - // Check to see if the ticker will overflow before the event - if(current <= event) { - return (event - current); - } - - return ((MAX_TICK_VAL - current) + event); -} - -//****************************************************************************** -static void tmr_handler(void) -{ - uint32_t term_cnt32 = US_TIMER->term_cnt32; - US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts - US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt - NVIC_ClearPendingIRQ(US_TIMER_IRQn); - - inc_current_cnt(term_cnt32); - - if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) { - // the timestamp has expired - event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value - us_ticker_irq_handler(); - } else { - - uint64_t diff = event_diff(current_cnt, event_cnt); - if (diff < (uint64_t)0xFFFFFFFF) { - // the event occurs before the next overflow - US_TIMER->term_cnt32 = diff; - - // Since the timer keeps counting after the terminal value is reached, it is possible that the new - // terminal value is in the past. - if (US_TIMER->term_cnt32 < US_TIMER->count32) { - // the timestamp has expired - US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts - US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt - NVIC_ClearPendingIRQ(US_TIMER_IRQn); - event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value - us_ticker_irq_handler(); - } - } - } -} - -//****************************************************************************** -void us_ticker_init(void) -{ - if (us_ticker_inited) - return; - us_ticker_inited = 1; - - /* Ensure that the TIMER0 clock is enabled */ - if (!(MXC_CLKMAN->clk_gate_ctrl1 & MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER)) { - MXC_CLKMAN->clk_gate_ctrl1 |= (2 << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS); - } - - current_cnt = 0; - event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value - - if (SystemCoreClock <= 1000000) { - error("us_ticker cannot operate at this SystemCoreClock"); - return; - } - - // Configure timer for 32-bit continuous mode with /1 prescaler - US_TIMER->ctrl = MXC_E_TMR_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS | (0 << MXC_F_TMR_CTRL_PRESCALE_POS); - ticks_per_us = SystemCoreClock / 1000000; - - // Set the tick window to 10ms - tick_win = SystemCoreClock/100; - - // Set timer overflow to the max - US_TIMER->term_cnt32 = 0xFFFFFFFF; - US_TIMER->pwm_cap32 = 0xFFFFFFFF; - US_TIMER->count32 = 0; - - US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear pending interrupts - - NVIC_SetVector(US_TIMER_IRQn, (uint32_t)tmr_handler); - NVIC_EnableIRQ(US_TIMER_IRQn); - - US_TIMER->inten |= MXC_F_TMR_INTEN_TIMER0; // enable interrupts - US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer -} - -//****************************************************************************** -void us_ticker_deinit(void) -{ - US_TIMER->ctrl = 0; // disable timer - US_TIMER->inten = 0; // disable interrupts - US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupts - us_ticker_inited = 0; -} - -//****************************************************************************** -uint32_t us_ticker_read(void) -{ - uint64_t current_cnt1, current_cnt2; - uint32_t term_cnt, tmr_cnt; - uint32_t intfl1, intfl2; - - if (!us_ticker_inited) - us_ticker_init(); - - // Ensure coherency between current_cnt and US_TIMER->count32 - do { - current_cnt1 = current_cnt; - intfl1 = US_TIMER->intfl; - term_cnt = US_TIMER->term_cnt32; - tmr_cnt = US_TIMER->count32; - intfl2 = US_TIMER->intfl; - current_cnt2 = current_cnt; - } while ((current_cnt1 != current_cnt2) || (intfl1 != intfl2)); - - // Account for an unserviced interrupt - if (intfl1) { - current_cnt1 += term_cnt; - } - - current_cnt1 += tmr_cnt; - - return (current_cnt1 / ticks_per_us); -} - -//****************************************************************************** -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Note: interrupts are disabled before this function is called. - - US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer - - if (US_TIMER->intfl) { - US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt - NVIC_ClearPendingIRQ(US_TIMER_IRQn); - inc_current_cnt(US_TIMER->term_cnt32); - } - - // add and reset the current count value - inc_current_cnt(US_TIMER->count32); - US_TIMER->count32 = 0; - - // add the number of cycles that the timer is disabled here for - inc_current_cnt(200); - - event_cnt = (uint64_t)timestamp * ticks_per_us; - - // Check to see if the event has already passed - if (!event_passed(current_cnt, event_cnt)) { - uint64_t diff = event_diff(current_cnt, event_cnt); - if (diff < (uint64_t)0xFFFFFFFF) { - // the event occurs before the next overflow - US_TIMER->term_cnt32 = diff; - } else { - // the event occurs after the next overflow - US_TIMER->term_cnt32 = 0xFFFFFFFF; // set to max - } - } else { - // the requested timestamp occurs in the past - // set the timer up to immediately expire - US_TIMER->term_cnt32 = 1; - } - US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer -} - -void us_ticker_fire_interrupt(void) -{ - US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer - US_TIMER->term_cnt32 = 1; - US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer -} - -//****************************************************************************** -void us_ticker_disable_interrupt(void) -{ - // There are no more events, set timer overflow to the max - US_TIMER->term_cnt32 = 0xFFFFFFFF; -} - -//****************************************************************************** -void us_ticker_clear_interrupt(void) -{ - // cleared in the local handler -} - -//****************************************************************************** -void us_ticker_set(timestamp_t timestamp) -{ - US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer - current_cnt = (uint64_t)timestamp * ticks_per_us; - US_TIMER->count32 = 0; - US_TIMER->term_cnt32 = 0xFFFFFFFF; - US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer - - if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) { - // The next timestamp has elapsed. Trigger the interrupt to handle it. - NVIC_SetPendingIRQ(US_TIMER_IRQn); - } -} - -void us_ticker_free(void) -{ - -}