From b01022314517adddf50680e1b3f88cc39c1e8aa5 Mon Sep 17 00:00:00 2001 From: gorazd Date: Wed, 18 Oct 2017 22:14:12 +0200 Subject: [PATCH] add new target L-Tek FF-LPC546XX --- .../TARGET_FF_LPC546XX/PeripheralNames.h | 113 ++++++++ .../TARGET_FF_LPC546XX/PeripheralPins.c | 125 +++++++++ .../TARGET_FF_LPC546XX/PinNames.h | 250 ++++++++++++++++++ .../TARGET_FF_LPC546XX/clock_config.c | 248 +++++++++++++++++ .../TARGET_FF_LPC546XX/clock_config.h | 144 ++++++++++ .../TARGET_FF_LPC546XX/device.h | 39 +++ .../TARGET_FF_LPC546XX/mbed_overrides.c | 121 +++++++++ targets/targets.json | 6 + 8 files changed, 1046 insertions(+) create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h new file mode 100644 index 0000000000..7efa1e5c20 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h @@ -0,0 +1,113 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = Flexcomm0, + UART_2 = Flexcomm2, + UART_7 = Flexcomm7 +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_7 = Flexcomm7, + I2C_2 = Flexcomm2 +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 + +typedef enum { + ADC0_SE0 = 0, + ADC0_SE1 = 1, + ADC0_SE2 = 2, + ADC0_SE3 = 3, + ADC0_SE4 = 4, + ADC0_SE5 = 5, + ADC0_SE6 = 6, + ADC0_SE7 = 7, + ADC0_SE8 = 8, + ADC0_SE9 = 9, + ADC0_SE10 = 10, + ADC0_SE11 = 11, +} ADCName; + +typedef enum { + CAN_1 = 1 +} CANName; + +typedef enum { + SPI_0 = Flexcomm0, + SPI_2 = Flexcomm2, + SPI_3 = Flexcomm3 +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c new file mode 100644 index 0000000000..bb555ca3b7 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c @@ -0,0 +1,125 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P0_15, ADC0_SE3, 0}, + {P0_16, ADC0_SE4, 0}, + {P0_23, ADC0_SE11, 0}, + {P0_31, ADC0_SE5, 0}, + {P1_0, ADC0_SE6, 0}, + {P0_10, ADC0_SE0, 0}, + {NC , NC , 0} +}; + +/************CAN***************/ +const PinMap PinMap_CAN_TD[] = { + {P0_1, CAN_1, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_CAN_RD[] = { + {P0_0, CAN_1, 1}, + {NC , NC , 0} +}; + + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_26, I2C_2, 1}, + {P1_29, I2C_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_27, I2C_2, 1}, + {P1_30, I2C_7, 1}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_30, UART_0, 1}, + {P0_27, UART_2, 1}, + {P1_30, UART_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_29, UART_0, 1}, + {P0_26, UART_2, 1}, + {P1_29, UART_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P1_4, SPI_0, 1}, + {P1_23, SPI_2, 1}, + {P0_6, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P1_5, SPI_0, 1}, + {P1_24, SPI_2, 1}, + {P0_8, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P1_6, SPI_0, 1}, + {P1_25, SPI_2, 1}, + {P0_9, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P1_7, SPI_0, 1}, + {P0_7, SPI_3, 1}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P0_17 , PWM_1, 4}, + {P0_18 , PWM_2, 4}, + {P0_19 , PWM_3, 4}, + {P0_22 , PWM_4, 4}, + {P0_28 , PWM_8, 4}, + {P0_29 , PWM_9, 4}, + {NC , NC, 0} +}; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h new file mode 100644 index 0000000000..bc22e8e4bc --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h @@ -0,0 +1,250 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + P0_0 = (0 << PORT_SHIFT | 0), + P0_1 = (0 << PORT_SHIFT | 1), + P0_2 = (0 << PORT_SHIFT | 2), + P0_3 = (0 << PORT_SHIFT | 3), + P0_4 = (0 << PORT_SHIFT | 4), + P0_5 = (0 << PORT_SHIFT | 5), + P0_6 = (0 << PORT_SHIFT | 6), + P0_7 = (0 << PORT_SHIFT | 7), + P0_8 = (0 << PORT_SHIFT | 8), + P0_9 = (0 << PORT_SHIFT | 9), + P0_10 = (0 << PORT_SHIFT | 10), + P0_11 = (0 << PORT_SHIFT | 11), + P0_12 = (0 << PORT_SHIFT | 12), + P0_13 = (0 << PORT_SHIFT | 13), + P0_14 = (0 << PORT_SHIFT | 14), + P0_15 = (0 << PORT_SHIFT | 15), + P0_16 = (0 << PORT_SHIFT | 16), + P0_17 = (0 << PORT_SHIFT | 17), + P0_18 = (0 << PORT_SHIFT | 18), + P0_19 = (0 << PORT_SHIFT | 19), + P0_20 = (0 << PORT_SHIFT | 20), + P0_21 = (0 << PORT_SHIFT | 21), + P0_22 = (0 << PORT_SHIFT | 22), + P0_23 = (0 << PORT_SHIFT | 23), + P0_24 = (0 << PORT_SHIFT | 24), + P0_25 = (0 << PORT_SHIFT | 25), + P0_26 = (0 << PORT_SHIFT | 26), + P0_27 = (0 << PORT_SHIFT | 27), + P0_28 = (0 << PORT_SHIFT | 28), + P0_29 = (0 << PORT_SHIFT | 29), + P0_30 = (0 << PORT_SHIFT | 30), + P0_31 = (0 << PORT_SHIFT | 31), + + P1_0 = (1 << PORT_SHIFT | 0), + P1_1 = (1 << PORT_SHIFT | 1), + P1_2 = (1 << PORT_SHIFT | 2), + P1_3 = (1 << PORT_SHIFT | 3), + P1_4 = (1 << PORT_SHIFT | 4), + P1_5 = (1 << PORT_SHIFT | 5), + P1_6 = (1 << PORT_SHIFT | 6), + P1_7 = (1 << PORT_SHIFT | 7), + P1_8 = (1 << PORT_SHIFT | 8), + P1_9 = (1 << PORT_SHIFT | 9), + P1_10 = (1 << PORT_SHIFT | 10), + P1_11 = (1 << PORT_SHIFT | 11), + P1_12 = (1 << PORT_SHIFT | 12), + P1_13 = (1 << PORT_SHIFT | 13), + P1_14 = (1 << PORT_SHIFT | 14), + P1_15 = (1 << PORT_SHIFT | 15), + P1_16 = (1 << PORT_SHIFT | 16), + P1_17 = (1 << PORT_SHIFT | 17), + P1_18 = (1 << PORT_SHIFT | 18), + P1_19 = (1 << PORT_SHIFT | 19), + P1_20 = (1 << PORT_SHIFT | 20), + P1_21 = (1 << PORT_SHIFT | 21), + P1_22 = (1 << PORT_SHIFT | 22), + P1_23 = (1 << PORT_SHIFT | 23), + P1_24 = (1 << PORT_SHIFT | 24), + P1_25 = (1 << PORT_SHIFT | 25), + P1_26 = (1 << PORT_SHIFT | 26), + P1_27 = (1 << PORT_SHIFT | 27), + P1_28 = (1 << PORT_SHIFT | 28), + P1_29 = (1 << PORT_SHIFT | 29), + P1_30 = (1 << PORT_SHIFT | 30), + P1_31 = (1 << PORT_SHIFT | 31), + + P2_0 = (2 << PORT_SHIFT | 0), + P2_1 = (2 << PORT_SHIFT | 1), + P2_2 = (2 << PORT_SHIFT | 2), + P2_3 = (2 << PORT_SHIFT | 3), + P2_4 = (2 << PORT_SHIFT | 4), + P2_5 = (2 << PORT_SHIFT | 5), + P2_6 = (2 << PORT_SHIFT | 6), + P2_7 = (2 << PORT_SHIFT | 7), + P2_8 = (2 << PORT_SHIFT | 8), + P2_9 = (2 << PORT_SHIFT | 9), + P2_10 = (2 << PORT_SHIFT | 10), + P2_11 = (2 << PORT_SHIFT | 11), + P2_12 = (2 << PORT_SHIFT | 12), + P2_13 = (2 << PORT_SHIFT | 13), + P2_14 = (2 << PORT_SHIFT | 14), + P2_15 = (2 << PORT_SHIFT | 15), + P2_16 = (2 << PORT_SHIFT | 16), + P2_17 = (2 << PORT_SHIFT | 17), + P2_18 = (2 << PORT_SHIFT | 18), + P2_19 = (2 << PORT_SHIFT | 19), + P2_20 = (2 << PORT_SHIFT | 20), + P2_21 = (2 << PORT_SHIFT | 21), + P2_22 = (2 << PORT_SHIFT | 22), + P2_23 = (2 << PORT_SHIFT | 23), + P2_24 = (2 << PORT_SHIFT | 24), + P2_25 = (2 << PORT_SHIFT | 25), + P2_26 = (2 << PORT_SHIFT | 26), + P2_27 = (2 << PORT_SHIFT | 27), + P2_28 = (2 << PORT_SHIFT | 28), + P2_29 = (2 << PORT_SHIFT | 29), + P2_30 = (2 << PORT_SHIFT | 30), + P2_31 = (2 << PORT_SHIFT | 31), + + P3_0 = (3 << PORT_SHIFT | 0), + P3_1 = (3 << PORT_SHIFT | 1), + P3_2 = (3 << PORT_SHIFT | 2), + P3_3 = (3 << PORT_SHIFT | 3), + P3_4 = (3 << PORT_SHIFT | 4), + P3_5 = (3 << PORT_SHIFT | 5), + P3_6 = (3 << PORT_SHIFT | 6), + P3_7 = (3 << PORT_SHIFT | 7), + P3_8 = (3 << PORT_SHIFT | 8), + P3_9 = (3 << PORT_SHIFT | 9), + P3_10 = (3 << PORT_SHIFT | 10), + P3_11 = (3 << PORT_SHIFT | 11), + P3_12 = (3 << PORT_SHIFT | 12), + P3_13 = (3 << PORT_SHIFT | 13), + P3_14 = (3 << PORT_SHIFT | 14), + P3_15 = (3 << PORT_SHIFT | 15), + P3_16 = (3 << PORT_SHIFT | 16), + P3_17 = (3 << PORT_SHIFT | 17), + P3_18 = (3 << PORT_SHIFT | 18), + P3_19 = (3 << PORT_SHIFT | 19), + P3_20 = (3 << PORT_SHIFT | 20), + P3_21 = (3 << PORT_SHIFT | 21), + P3_22 = (3 << PORT_SHIFT | 22), + P3_23 = (3 << PORT_SHIFT | 23), + P3_24 = (3 << PORT_SHIFT | 24), + P3_25 = (3 << PORT_SHIFT | 25), + P3_26 = (3 << PORT_SHIFT | 26), + P3_27 = (3 << PORT_SHIFT | 27), + P3_28 = (3 << PORT_SHIFT | 28), + P3_29 = (3 << PORT_SHIFT | 29), + P3_30 = (3 << PORT_SHIFT | 30), + P3_31 = (3 << PORT_SHIFT | 31), + + P4_0 = (4 << PORT_SHIFT | 0), + P4_1 = (4 << PORT_SHIFT | 1), + P4_2 = (4 << PORT_SHIFT | 2), + P4_3 = (4 << PORT_SHIFT | 3), + P4_4 = (4 << PORT_SHIFT | 4), + P4_5 = (4 << PORT_SHIFT | 5), + P4_6 = (4 << PORT_SHIFT | 6), + P4_7 = (4 << PORT_SHIFT | 7), + P4_8 = (4 << PORT_SHIFT | 8), + P4_9 = (4 << PORT_SHIFT | 9), + P4_10 = (4 << PORT_SHIFT | 10), + P4_11 = (4 << PORT_SHIFT | 11), + P4_12 = (4 << PORT_SHIFT | 12), + P4_13 = (4 << PORT_SHIFT | 13), + P4_14 = (4 << PORT_SHIFT | 14), + P4_15 = (4 << PORT_SHIFT | 15), + P4_16 = (4 << PORT_SHIFT | 16), + + + + // mbed original LED naming + LED1 = P0_13, + LED2 = P1_27, + LED3 = P0_14, + LED4 = P1_28, + + + // USB Pins + USBTX = P0_30, + USBRX = P0_29, + + + A0 = P0_16, + A1 = P0_31, + A2 = P1_0, + A3 = P2_0, + A4 = P3_4, + A5 = P1_1, + + + p5 = P1_24, + p6 = P1_25, + p7 = P1_23, + p8 = P1_8, + p9 = P0_26, + p10 = P0_27, + p11 = P1_4, + p12 = P1_5, + p13 = P1_6, + p14 = P1_7, + p15 = P0_15, + p16 = P0_16, + p17 = P0_23, + p18 = P0_31, + p19 = P1_0, + p20 = P0_10, + p21 = P0_17, + p22 = P0_18, + p23 = P0_19, + p24 = P0_22, + p25 = P0_28, + p26 = P0_29, + p27 = P1_30, + p28 = P1_29, + p29 = P0_0, + p30 = P0_1, + + + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c new file mode 100644 index 0000000000..cea986a6c0 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Setup voltage for the fastest of the clock outputs + * + * 3. Set up wait states of the flash. + * + * 4. Set up all dividers. + * + * 5. Set up all selectors to provide selected clocks. + */ + +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!ClocksProfile +product: Clocks v1.0 +processor: LPC54618J512 +package_id: LPC54618J512ET180 +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: LPCXpresso54618 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} +sources: +- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockPLL180M +outputs: +- {id: FRO12M_clock.outFreq, value: 12 MHz} +- {id: FROHF_clock.outFreq, value: 48 MHz} +- {id: SYSPLL_clock.outFreq, value: 180 MHz} +- {id: System_clock.outFreq, value: 180 MHz} +settings: +- {id: SYSCON.M_MULT.scale, value: '30', locked: true} +- {id: SYSCON.N_DIV.scale, value: '1', locked: true} +- {id: SYSCON.PDEC.scale, value: '2', locked: true} +- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up} +sources: +- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +void BOARD_BootClockPLL180M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up SYS PLL */ + const pll_setup_t pllSetup = { + .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U), + .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), + .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), + .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), + .pllRate = 180000000U, + .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP}; + CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */ + CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ + POWER_SetVoltageForFreq( + 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */ + CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */ + + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK; +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h new file mode 100644 index 0000000000..f9cdab4d95 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ +#define BOARD_BootClockRUN BOARD_BootClockFROHF48M + + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL180M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h new file mode 100644 index 0000000000..de347c375d --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define NUMBER_OF_GPIO_INTS 8 + +#define APP_EXCLUDE_FROM_DEEPSLEEP \ + (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK | SYSCON_PDRUNCFG_PDEN_SRAMX_MASK | \ + SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK) + +/* Defines used by the sleep code */ +#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M +#define LPC_CLOCK_RUN BOARD_BootClockFROHF48M + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c new file mode 100644 index 0000000000..b727924a6a --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c @@ -0,0 +1,121 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "clock_config.h" +#include "fsl_emc.h" +#include "fsl_power.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* The SDRAM timing. */ +#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */ +#define SDRAM_TRP_NS (18u) +#define SDRAM_TRAS_NS (42u) +#define SDRAM_TSREX_NS (67u) +#define SDRAM_TAPR_NS (18u) +#define SDRAM_TWRDELT_NS (6u) +#define SDRAM_TRC_NS (60u) +#define SDRAM_RFC_NS (60u) +#define SDRAM_XSR_NS (67u) +#define SDRAM_RRD_NS (12u) +#define SDRAM_MRD_NCLK (2u) +#define SDRAM_RAS_NCLK (2u) +#define SDRAM_MODEREG_VALUE (0x23u) +#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ + +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockFROHF48M(); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + //gpio_t gpio; + //gpio_init_in(&gpio, PTA4); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(void) +{ + /* Enable the RTC 32K Oscillator */ + SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK; +} + +void ADC_ClockPower_Configuration(void) +{ + /* SYSCON power. */ + POWER_DisablePD(kPDRUNCFG_PD_VDDA); /* Power on VDDA. */ + POWER_DisablePD(kPDRUNCFG_PD_ADC0); /* Power on the ADC converter. */ + POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */ + POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ + POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ + + /* Enable the clock. */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + + /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ + /* Sync clock source is not used. Using sync clock source and would be divided by 2. + * The divider would be set when configuring the converter. + */ + CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */ +} + +/* Initialize the external memory. */ +void BOARD_InitSDRAM(void) +{ + emc_basic_config_t basicConfig; + emc_dynamic_timing_config_t dynTiming; + emc_dynamic_chip_config_t dynChipConfig; + + /* Basic configuration. */ + basicConfig.endian = kEMC_LittleEndian; + basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk; + /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M. + * If you change the divide to 0 and EMC clock is larger than 100M + * please take refer to emc.dox to adjust EMC clock delay. + */ + basicConfig.emcClkDiv = 1; + /* Dynamic memory timing configuration. */ + dynTiming.readConfig = kEMC_Cmddelay; + dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS; + dynTiming.tRp_Ns = SDRAM_TRP_NS; + dynTiming.tRas_Ns = SDRAM_TRAS_NS; + dynTiming.tSrex_Ns = SDRAM_TSREX_NS; + dynTiming.tApr_Ns = SDRAM_TAPR_NS; + dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */ + dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns; + dynTiming.tRc_Ns = SDRAM_TRC_NS; + dynTiming.tRfc_Ns = SDRAM_RFC_NS; + dynTiming.tXsr_Ns = SDRAM_XSR_NS; + dynTiming.tRrd_Ns = SDRAM_RRD_NS; + dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK; + /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */ + dynChipConfig.chipIndex = 0; + dynChipConfig.dynamicDevice = kEMC_Sdram; + dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK; + dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE; + dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */ + dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP; + /* EMC Basic configuration. */ + EMC_Init(EMC, &basicConfig); + /* EMC Dynamc memory configuration. */ + EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1); +} diff --git a/targets/targets.json b/targets/targets.json index e7775acd8e..cda9b682d4 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -706,6 +706,12 @@ "release_versions": ["2", "5"], "device_name" : "LPC54618J512ET180" }, + "FF_LPC546XX": { + "inherits": ["LPC546XX"], + "extra_labels_remove" : ["LPCXpresso"], + "supported_form_factors": [""], + "detect_code": ["8081"] + }, "NUCLEO_F030R8": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"],