From 49338852ad3050f6d4cccd9bc89690e72ac5ab8e Mon Sep 17 00:00:00 2001 From: adustm Date: Fri, 4 Mar 2016 14:32:00 +0100 Subject: [PATCH] [STM32F7_DISCO_F746NG] Update target files with latest STM32F7Cube_FW version --- .../TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S | 10 +- .../TOOLCHAIN_ARM_MICRO/stm32f746ng.sct | 2 +- .../TOOLCHAIN_ARM_STD/startup_stm32f746ng.S | 10 +- .../TOOLCHAIN_ARM_STD/stm32f746ng.sct | 2 +- .../TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S | 4 +- .../TOOLCHAIN_IAR/startup_stm32f746xx.S | 6 +- .../TARGET_DISCO_F746NG/cmsis.h | 2 +- .../TARGET_DISCO_F746NG/cmsis_nvic.c | 4 +- .../TARGET_DISCO_F746NG/cmsis_nvic.h | 2 +- .../TARGET_DISCO_F746NG/hal_tick.c | 2 +- .../TARGET_DISCO_F746NG/hal_tick.h | 2 +- .../TARGET_DISCO_F746NG/stm32f746xx.h | 122 ++++++++----- .../TARGET_DISCO_F746NG/stm32f7xx.h | 6 +- .../TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h | 6 +- .../TARGET_DISCO_F746NG/system_stm32f7xx.c | 168 ++++++++++++++++-- .../TARGET_DISCO_F746NG/system_stm32f7xx.h | 6 +- 16 files changed, 265 insertions(+), 89 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S index ab302a5d11..b2326dcd07 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S @@ -1,8 +1,8 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f746xx.s ;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 28-April-2015 +;* Version : V1.0.2 +;* Date : 21-September-2015 ;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -350,12 +350,12 @@ Default_Handler PROC EXPORT DMA2D_IRQHandler [WEAK] EXPORT SAI2_IRQHandler [WEAK] EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] EXPORT CEC_IRQHandler [WEAK] EXPORT I2C4_EV_IRQHandler [WEAK] - EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] EXPORT SPDIF_RX_IRQHandler [WEAK] - + WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct index aabd424957..cb52146d47 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct @@ -1,6 +1,6 @@ ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics +; Copyright (c) 2016, STMicroelectronics ; All rights reserved. ; ; Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S index 76cd68372a..4e25bfa2a8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S @@ -1,8 +1,8 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f746xx.s ;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 28-April-2015 +;* Version : V1.0.2 +;* Date : 21-September-2015 ;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -323,12 +323,12 @@ Default_Handler PROC EXPORT DMA2D_IRQHandler [WEAK] EXPORT SAI2_IRQHandler [WEAK] EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] EXPORT CEC_IRQHandler [WEAK] EXPORT I2C4_EV_IRQHandler [WEAK] - EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] EXPORT SPDIF_RX_IRQHandler [WEAK] - + WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct index aabd424957..cb52146d47 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct @@ -1,6 +1,6 @@ ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics +; Copyright (c) 2016, STMicroelectronics ; All rights reserved. ; ; Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S index 1fcde5f2bd..b14a8455b8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f746xx.s * @author MCD Application Team - * Version V1.0.0 - * Date 28-April-2015 + * @Version V1.0.2 + * @Date 21-September-2015 * @brief STM32F746xx Devices vector table for GCC based toolchain. * This module performs: * - Set the initial SP diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S index 50788a47c1..42431f529c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S @@ -1,8 +1,8 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f746xx.s ;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 28-April-2015 +;* Version : V1.0.2 +;* Date : 21-September-2015 ;* Description : STM32F746xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h index 1341e459a1..ee3ba9007b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2016, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c index 9263c748e7..69a0fa5832 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2016, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,7 +27,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* - */ + */ #include "cmsis_nvic.h" #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h index b37c70e1a1..0a26d73682 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2016, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c index a1b76f9b61..e21ca156ae 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2015 STMicroelectronics

+ *

© COPYRIGHT 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h index 168d313950..6501819b5d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h index a510fb023c..b84b4cf36e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f746xx.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.0.2 + * @date 21-September-2015 * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File. * * This file contains: @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ * @brief STM32F7xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ -typedef enum IRQn +typedef enum { /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ @@ -125,7 +125,7 @@ typedef enum IRQn TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ @@ -182,14 +182,14 @@ typedef enum IRQn /** * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ -#define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */ +#define __CM7_REV 0x0001 /*!< Cortex-M7 revision r0p1 */ #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present */ #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ -#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ +#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ #include "system_stm32f7xx.h" @@ -353,6 +353,7 @@ typedef struct __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; + /** * @brief Debug MCU */ @@ -697,11 +698,10 @@ typedef struct __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ uint32_t RESERVED1[3]; /*!< Reserved */ - __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ } LTDC_Layer_TypeDef; - /** * @brief Power Control */ @@ -967,7 +967,6 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ } LPTIM_TypeDef; @@ -1002,6 +1001,7 @@ typedef struct __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; + /** * @brief RNG */ @@ -1140,7 +1140,8 @@ typedef struct * @} */ - + + /** @addtogroup Peripheral_memory_map * @{ */ @@ -1148,13 +1149,13 @@ typedef struct #define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */ #define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ #define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */ -#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ -#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */ #define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */ #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */ #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ /* Legacy define */ @@ -1226,7 +1227,7 @@ typedef struct #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) #define LTDC_BASE (APB2PERIPH_BASE + 0x6800) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) @@ -3125,6 +3126,7 @@ typedef struct /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */ + /******************************************************************************/ /* */ /* Digital to Analog Converter */ @@ -3216,6 +3218,7 @@ typedef struct #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!
© COPYRIGHT(c) 2015 STMicroelectronics
+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h index 8c67585b9b..d0339d3055 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f7xx_hal_conf_template.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.0.4 + * @date 09-December-2015 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f7xx_hal_conf.h. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c index 9c3676eb68..9672a56d78 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.c * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.0.2 + * @date 21-September-2015 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from @@ -39,7 +39,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2015 STMicroelectronics

+ *

© COPYRIGHT 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -109,14 +109,13 @@ HAL_StatusTypeDef HAL_Init(void); /************************* Miscellaneous Configuration ************************/ /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted - on EVAL board as data memory */ + on STMicroelectronics EVAL/Discovery boards as data memory */ +/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define + need to be added in the project preprocessor to avoid SDRAM multiple configuration + (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */ /* #define DATA_IN_ExtSRAM */ /* #define DATA_IN_ExtSDRAM */ -#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) - #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " -#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ - /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ @@ -218,7 +217,7 @@ void SystemInit(void) /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif @@ -336,7 +335,151 @@ void SystemCoreClockUpdate(void) void SystemInit_ExtMemCtl(void) { __IO uint32_t tmp = 0; -#if defined (DATA_IN_ExtSDRAM) +#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x55550545; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554145; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xFF800FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55400555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CC00CC; + GPIOG->AFR[1] = 0xC00000CC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x80220AAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0x80320FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x40110555; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x55550450; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00145555; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[4] = 0x00001091; + FMC_Bank1->BTCR[5] = 0x00110212; + FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E5; + FMC_Bank5_6->SDTR[0] = 0x01116361; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x000000F3; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#elif defined (DATA_IN_ExtSDRAM) register uint32_t tmpreg = 0, timeout = 0xFFFF; register uint32_t index; @@ -473,9 +616,8 @@ void SystemInit_ExtMemCtl(void) /* Disable write protection */ tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); -#endif /* DATA_IN_ExtSDRAM */ - -#if defined(DATA_IN_ExtSRAM) + +#elif defined(DATA_IN_ExtSRAM) /*-- GPIOs Configuration -----------------------------------------------------*/ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHB1ENR |= 0x00000078; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h index 529cb4a24d..146e57a589 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.0.2 + * @date 21-September-2015 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: