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Merge pull request #7631 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.9.4
pull/7591/merge mbed-os-5.9.4
Cruz Monrreal 2018-07-30 15:23:29 -05:00 committed by GitHub
parent 50bd61a4a7 6974f23e99
commit 485bdeee15
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
414 changed files with 416073 additions and 502 deletions
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25
LICENSE-BSD-3-Clause
View File

@ -1,25 +0,0 @@
Copyright 2017 Arm Limited and affiliates.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

32
TESTS/mbed_hal/common_tickers/main.cpp
View File

@ -29,8 +29,10 @@
#define TICKER_INT_VAL 500
#define TICKER_DELTA 10
#define LP_TICKER_OVERFLOW_DELTA 0 // this will allow to detect that ticker counter rollovers to 0
#define US_TICKER_OVERFLOW_DELTA 50
#define LP_TICKER_OVERFLOW_DELTA1 0 // this will allow to detect that ticker counter rollovers to 0
#define LP_TICKER_OVERFLOW_DELTA2 0
#define US_TICKER_OVERFLOW_DELTA1 50
#define US_TICKER_OVERFLOW_DELTA2 60
#define TICKER_100_TICKS 100
@ -48,7 +50,18 @@ using namespace utest::v1;
volatile int intFlag = 0;
const ticker_interface_t* intf;
ticker_irq_handler_type prev_irq_handler;
unsigned int ticker_overflow_delta;
/* Some targets might fail overflow test uncertainly due to getting trapped in busy
* intf->read() loop. In the loop, some ticker values wouldn't get caught in time
* because of:
* 1. Lower CPU clock
* 2. Compiled code with worse performance
* 3. Interrupt at that time
*
* We fix it by checking small ticker value range rather than one exact ticker point
* in near overflow check.
*/
unsigned int ticker_overflow_delta1;
unsigned int ticker_overflow_delta2;
/* Auxiliary function to count ticker ticks elapsed during execution of N cycles of empty while loop.
* Parameter <step> is used to disable compiler optimisation. */
@ -293,12 +306,13 @@ void ticker_overflow_test(void)
intFlag = 0;
/* Wait for max count. */
while (intf->read() != (max_count - ticker_overflow_delta)) {
while (intf->read() >= (max_count - ticker_overflow_delta2) &&
intf->read() <= (max_count - ticker_overflow_delta1)) {
/* Just wait. */
}
/* Now we are near/at the overflow point. Detect rollover. */
while (intf->read() > ticker_overflow_delta);
while (intf->read() > ticker_overflow_delta1);
const uint32_t after_overflow = intf->read();
@ -310,7 +324,7 @@ void ticker_overflow_test(void)
const uint32_t next_after_overflow = intf->read();
/* Check that after the overflow ticker continue count. */
TEST_ASSERT(after_overflow <= ticker_overflow_delta);
TEST_ASSERT(after_overflow <= ticker_overflow_delta1);
TEST_ASSERT(next_after_overflow >= TICKER_100_TICKS);
TEST_ASSERT_EQUAL(0, intFlag);
@ -465,7 +479,8 @@ utest::v1::status_t us_ticker_setup(const Case *const source, const size_t index
prev_irq_handler = set_us_ticker_irq_handler(ticker_event_handler_stub);
ticker_overflow_delta = US_TICKER_OVERFLOW_DELTA;
ticker_overflow_delta1 = US_TICKER_OVERFLOW_DELTA1;
ticker_overflow_delta2 = US_TICKER_OVERFLOW_DELTA2;
return greentea_case_setup_handler(source, index_of_case);
}
@ -493,7 +508,8 @@ utest::v1::status_t lp_ticker_setup(const Case *const source, const size_t index
prev_irq_handler = set_lp_ticker_irq_handler(ticker_event_handler_stub);
ticker_overflow_delta = LP_TICKER_OVERFLOW_DELTA;
ticker_overflow_delta1 = LP_TICKER_OVERFLOW_DELTA1;
ticker_overflow_delta2 = LP_TICKER_OVERFLOW_DELTA2;
return greentea_case_setup_handler(source, index_of_case);
}

4
TESTS/mbedmicro-rtos-mbed/basic/main.cpp
View File

@ -29,7 +29,11 @@
using utest::v1::Case;
#if defined(__CORTEX_M23) || defined(__CORTEX_M33)
#define TEST_STACK_SIZE 512
#else
#define TEST_STACK_SIZE 256
#endif
#define ONE_MILLI_SEC 1000
volatile uint32_t elapsed_time_ms = 0;

4
TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp
View File

@ -30,7 +30,11 @@ using utest::v1::Case;
#error [NOT_SUPPORTED] test not supported
#endif
#if defined(__CORTEX_M23) || defined(__CORTEX_M33)
#define THREAD_STACK_SIZE 512
#else
#define THREAD_STACK_SIZE 320 /* 512B stack on GCC_ARM compiler cause out of memory on some 16kB RAM boards e.g. NUCLEO_F070RB */
#endif
#define MAX_FLAG_POS 30
#define PROHIBITED_FLAG_POS 31

4
TESTS/mbedmicro-rtos-mbed/mail/main.cpp
View File

@ -29,7 +29,11 @@
using namespace utest::v1;
#if defined(__CORTEX_M23) || defined(__CORTEX_M33)
#define THREAD_STACK_SIZE 512
#else
#define THREAD_STACK_SIZE 320 /* larger stack cause out of heap memory on some 16kB RAM boards in multi thread test*/
#endif
#define QUEUE_SIZE 16
#define THREAD_1_ID 1
#define THREAD_2_ID 2

2
TESTS/mbedmicro-rtos-mbed/malloc/main.cpp
View File

@ -37,6 +37,8 @@ volatile bool thread_should_continue = true;
#if defined(__CORTEX_A9)
#define THREAD_STACK_SIZE 512
#elif defined(__CORTEX_M23) || defined(__CORTEX_M33)
#define THREAD_STACK_SIZE 512
#else
#define THREAD_STACK_SIZE 256
#endif

4
TESTS/mbedmicro-rtos-mbed/mutex/main.cpp
View File

@ -29,7 +29,11 @@
using namespace utest::v1;
#if defined(__CORTEX_M23) || defined(__CORTEX_M33)
#define TEST_STACK_SIZE 768
#else
#define TEST_STACK_SIZE 512
#endif
#define TEST_LONG_DELAY 20
#define TEST_DELAY 10

2
TESTS/mbedmicro-rtos-mbed/systimer/main.cpp
View File

@ -13,7 +13,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if !MBED_TICKLESS
#ifndef MBED_TICKLESS
#error [NOT_SUPPORTED] Tickless mode not supported for this target.
#endif

2
TESTS/mbedmicro-rtos-mbed/threads/main.cpp
View File

@ -32,6 +32,8 @@
#define THREAD_STACK_SIZE 512
#if defined(__CORTEX_A9)
#define PARALLEL_THREAD_STACK_SIZE 512
#elif defined(__CORTEX_M23) || defined(__CORTEX_M33)
#define PARALLEL_THREAD_STACK_SIZE 512
#else
#define PARALLEL_THREAD_STACK_SIZE 384
#endif

30
TESTS/netsocket/tcp/main.cpp
View File

@ -32,6 +32,7 @@ using namespace utest::v1;
namespace
{
NetworkInterface* net;
Timer tc_bucket; // Timer to limit a test cases run time
}
char tcp_global::rx_buffer[RX_BUFF_SIZE];
@ -66,24 +67,32 @@ static void _ifdown() {
printf("MBED: ifdown\n");
}
void tcpsocket_connect_to_echo_srv(TCPSocket& sock) {
nsapi_error_t tcpsocket_connect_to_echo_srv(TCPSocket& sock) {
SocketAddress tcp_addr;
get_interface()->gethostbyname(MBED_CONF_APP_ECHO_SERVER_ADDR, &tcp_addr);
tcp_addr.set_port(MBED_CONF_APP_ECHO_SERVER_PORT);
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(get_interface()));
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.connect(tcp_addr));
nsapi_error_t err = sock.open(get_interface());
if (err != NSAPI_ERROR_OK) {
return err;
}
return sock.connect(tcp_addr);
}
void tcpsocket_connect_to_discard_srv(TCPSocket& sock) {
nsapi_error_t tcpsocket_connect_to_discard_srv(TCPSocket& sock) {
SocketAddress tcp_addr;
get_interface()->gethostbyname(MBED_CONF_APP_ECHO_SERVER_ADDR, &tcp_addr);
tcp_addr.set_port(9);
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(get_interface()));
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.connect(tcp_addr));
nsapi_error_t err = sock.open(get_interface());
if (err != NSAPI_ERROR_OK) {
return err;
}
return sock.connect(tcp_addr);
}
void fill_tx_buffer_ascii(char *buff, size_t len)
@ -93,16 +102,23 @@ void fill_tx_buffer_ascii(char *buff, size_t len)
}
}
int split2half_rmng_tcp_test_time()
{
return (tcp_global::TESTS_TIMEOUT-tc_bucket.read())/2;
}
// Test setup
utest::v1::status_t greentea_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(480, "default_auto");
GREENTEA_SETUP(tcp_global::TESTS_TIMEOUT, "default_auto");
_ifup();
tc_bucket.start();
return greentea_test_setup_handler(number_of_cases);
}
void greentea_teardown(const size_t passed, const size_t failed, const failure_t failure)
{
tc_bucket.stop();
_ifdown();
return greentea_test_teardown_handler(passed, failed, failure);
}

10
TESTS/netsocket/tcp/tcp_tests.h
View File

@ -21,11 +21,17 @@
NetworkInterface* get_interface();
void drop_bad_packets(TCPSocket& sock, int orig_timeout);
void fill_tx_buffer_ascii(char *buff, size_t len);
void tcpsocket_connect_to_echo_srv(TCPSocket& sock);
void tcpsocket_connect_to_discard_srv(TCPSocket& sock);
nsapi_error_t tcpsocket_connect_to_echo_srv(TCPSocket& sock);
nsapi_error_t tcpsocket_connect_to_discard_srv(TCPSocket& sock);
/**
* Single testcase might take only half of the remaining execution time
*/
int split2half_rmng_tcp_test_time(); // [s]
namespace tcp_global
{
static const int TESTS_TIMEOUT = 480;
static const int TCP_OS_STACK_SIZE = 1024;
static const int RX_BUFF_SIZE = 1220;

35
TESTS/netsocket/tcp/tcpsocket_echotest.cpp
View File

@ -37,6 +37,9 @@ namespace
1100,1200};
TCPSocket sock;
Semaphore tx_sem(0, 1);
Timer tc_exec_time;
int time_allotted;
}
static void _sigio_handler(osThreadId id) {
@ -45,7 +48,10 @@ static void _sigio_handler(osThreadId id) {
void TCPSOCKET_ECHOTEST()
{
tcpsocket_connect_to_echo_srv(sock);
if (tcpsocket_connect_to_echo_srv(sock) != NSAPI_ERROR_OK) {
TEST_FAIL();
return;
}
int recvd;
int sent;
@ -57,6 +63,8 @@ void TCPSOCKET_ECHOTEST()
if (sent < 0) {
printf("[Round#%02d] network error %d\n", x, sent);
TEST_FAIL();
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
return;
}
int bytes2recv = sent;
@ -65,6 +73,8 @@ void TCPSOCKET_ECHOTEST()
if (recvd < 0) {
printf("[Round#%02d] network error %d\n", x, recvd);
TEST_FAIL();
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
return;
}
bytes2recv -= recvd;
}
@ -80,10 +90,15 @@ void tcpsocket_echotest_nonblock_receiver(void *receive_bytes)
while (bytes2recv) {
recvd = sock.recv(&(tcp_global::rx_buffer[*(int*)receive_bytes-bytes2recv]), bytes2recv);
if (recvd == NSAPI_ERROR_WOULD_BLOCK) {
if (tc_exec_time.read() >= time_allotted) {
TEST_FAIL();
break;
}
wait(1);
continue;
} else if (recvd < 0) {
TEST_FAIL();
break;
}
bytes2recv -= recvd;
}
@ -99,6 +114,9 @@ void tcpsocket_echotest_nonblock_receiver(void *receive_bytes)
void TCPSOCKET_ECHOTEST_NONBLOCK()
{
tc_exec_time.start();
time_allotted = split2half_rmng_tcp_test_time(); // [s]
tcpsocket_connect_to_echo_srv(sock);
sock.set_blocking(false);
sock.sigio(callback(_sigio_handler, Thread::gettid()));
@ -124,19 +142,30 @@ void TCPSOCKET_ECHOTEST_NONBLOCK()
while (bytes2send > 0) {
sent = sock.send(&(tcp_global::tx_buffer[pkt_s-bytes2send]), bytes2send);
if (sent == NSAPI_ERROR_WOULD_BLOCK) {
TEST_ASSERT_NOT_EQUAL(osEventTimeout, osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status);
if (tc_exec_time.read() >= time_allotted ||
osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) {
thread->terminate();
delete thread;
TEST_FAIL();
goto END;
}
continue;
} else if (sent <= 0) {
printf("[Sender#%02d] network error %d\n", s_idx, sent);
thread->terminate();
delete thread;
TEST_FAIL();
goto END;
}
bytes2send -= sent;
}
printf("[Sender#%02d] bytes sent: %d\n", s_idx, pkt_s);
tx_sem.wait();
tx_sem.wait(split2half_rmng_tcp_test_time());
thread->join();
delete thread;
}
END:
tc_exec_time.stop();
free(stack_mem);
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
}

13
TESTS/netsocket/tcp/tcpsocket_echotest_burst.cpp
View File

@ -57,11 +57,13 @@ void TCPSOCKET_ECHOTEST_BURST()
if (sent == NSAPI_ERROR_WOULD_BLOCK) {
if(osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) {
TEST_FAIL();
goto END;
}
continue;
} else if (sent < 0) {
printf("[%02d] network error %d\n", i, sent);
TEST_FAIL();
goto END;
}
bt_left -= sent;
}
@ -79,10 +81,12 @@ void TCPSOCKET_ECHOTEST_BURST()
if (bt_left != 0) {
drop_bad_packets(sock, 0);
TEST_FAIL();
goto END;
}
TEST_ASSERT_EQUAL(0, memcmp(tcp_global::tx_buffer, tcp_global::rx_buffer, BURST_SIZE));
}
END:
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
}
@ -106,15 +110,20 @@ void TCPSOCKET_ECHOTEST_BURST_NONBLOCK()
if (sent == NSAPI_ERROR_WOULD_BLOCK) {
if(osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) {
TEST_FAIL();
goto END;
}
continue;
} else if (sent < 0) {
printf("[%02d] network error %d\n", i, sent);
TEST_FAIL();
goto END;
}
bt_left -= sent;
}
TEST_ASSERT_EQUAL(0, bt_left);
if (bt_left != 0) {
TEST_FAIL();
goto END;
}
bt_left = BURST_SIZE;
while (bt_left > 0) {
@ -136,9 +145,11 @@ void TCPSOCKET_ECHOTEST_BURST_NONBLOCK()
printf("network error %d, missing %d bytes from a burst\n", recvd, bt_left);
drop_bad_packets(sock, -1);
TEST_FAIL();
goto END;
}
TEST_ASSERT_EQUAL(0, memcmp(tcp_global::tx_buffer, tcp_global::rx_buffer, BURST_SIZE));
}
END:
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
}

26
TESTS/netsocket/tcp/tcpsocket_endpoint_close.cpp
View File

@ -35,14 +35,18 @@ static void _sigio_handler(osThreadId id) {
osSignalSet(id, SIGNAL_SIGIO);
}
static void _tcpsocket_connect_to_daytime_srv(TCPSocket& sock) {
static nsapi_error_t _tcpsocket_connect_to_daytime_srv(TCPSocket& sock) {
SocketAddress tcp_addr;
get_interface()->gethostbyname(MBED_CONF_APP_ECHO_SERVER_ADDR, &tcp_addr);
tcp_addr.set_port(13);
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(get_interface()));
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.connect(tcp_addr));
nsapi_error_t err = sock.open(get_interface());
if (err != NSAPI_ERROR_OK) {
return err;
}
return sock.connect(tcp_addr);
}
@ -50,9 +54,15 @@ void TCPSOCKET_ENDPOINT_CLOSE()
{
static const int MORE_THAN_AVAILABLE = 30;
char buff[MORE_THAN_AVAILABLE];
int time_allotted = split2half_rmng_tcp_test_time(); // [s]
Timer tc_exec_time;
tc_exec_time.start();
TCPSocket sock;
_tcpsocket_connect_to_daytime_srv(sock);
if (_tcpsocket_connect_to_daytime_srv(sock) != NSAPI_ERROR_OK) {
TEST_FAIL();
return;
}
sock.sigio(callback(_sigio_handler, Thread::gettid()));
int recvd = 0;
@ -61,16 +71,20 @@ void TCPSOCKET_ENDPOINT_CLOSE()
recvd = sock.recv(&(buff[recvd_total]), MORE_THAN_AVAILABLE);
if (recvd_total > 0 && recvd == 0) {
break; // Endpoint closed socket, success
} else if (recvd == 0) {
} else if (recvd <= 0) {
TEST_FAIL();
break;
} else if (recvd == NSAPI_ERROR_WOULD_BLOCK) {
if(osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) {
if(tc_exec_time.read() >= time_allotted ||
osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) {
TEST_FAIL();
break;
}
continue;
}
recvd_total += recvd;
TEST_ASSERT(recvd_total < MORE_THAN_AVAILABLE);
}
tc_exec_time.stop();
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
}

60
TESTS/netsocket/tcp/tcpsocket_recv_100k.cpp
View File

@ -31,14 +31,19 @@ namespace
static const int SIGIO_TIMEOUT = 20000; //[ms]
}
static void _tcpsocket_connect_to_chargen_srv(TCPSocket& sock) {
static nsapi_error_t _tcpsocket_connect_to_chargen_srv(TCPSocket& sock)
{
SocketAddress tcp_addr;
get_interface()->gethostbyname(MBED_CONF_APP_ECHO_SERVER_ADDR, &tcp_addr);
tcp_addr.set_port(19);
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(get_interface()));
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.connect(tcp_addr));
nsapi_error_t err = sock.open(get_interface());
if (err != NSAPI_ERROR_OK) {
return err;
}
return sock.connect(tcp_addr);
}
/** Generate RFC 864 example pattern.
@ -86,35 +91,46 @@ void rcv_n_chk_against_rfc864_pattern(TCPSocket& sock) {
uint8_t buff[buff_size];
size_t recvd_size = 0;
Timer timer;
timer.start();
// Verify received data
while (recvd_size < total_size) {
int rd = sock.recv(buff, buff_size);
TEST_ASSERT(rd > 0);
if (rd < 0) {
break;
}
check_RFC_864_pattern(buff, rd, recvd_size);
recvd_size += rd;
}
timer.stop();
printf("MBED: Time taken: %fs\n", timer.read());
}
void TCPSOCKET_RECV_100K()
{
TCPSocket sock;
_tcpsocket_connect_to_chargen_srv(sock);
if (_tcpsocket_connect_to_chargen_srv(sock) != NSAPI_ERROR_OK) {
TEST_FAIL();
return;
}
Timer timer;
timer.start();
rcv_n_chk_against_rfc864_pattern(sock);
timer.stop();
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
printf("MBED: Time taken: %fs\n", timer.read());
}
void rcv_n_chk_against_rfc864_pattern_nonblock(TCPSocket& sock) {
void rcv_n_chk_against_rfc864_pattern_nonblock(TCPSocket& sock)
{
static const size_t total_size = 1024 * 100;
static const size_t buff_size = 1220;
uint8_t buff[buff_size];
size_t recvd_size = 0;
int time_allotted = split2half_rmng_tcp_test_time(); // [s]
Timer timer;
timer.start();
// Verify received data
while (recvd_size < total_size) {
@ -124,9 +140,18 @@ void rcv_n_chk_against_rfc864_pattern_nonblock(TCPSocket& sock) {
check_RFC_864_pattern(buff, rd, recvd_size);
recvd_size += rd;
} else if (rd == NSAPI_ERROR_WOULD_BLOCK) {
if (timer.read() >= time_allotted) {
TEST_FAIL();
break;
}
TEST_ASSERT_NOT_EQUAL(osEventTimeout, osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status);
} else {
TEST_FAIL();
break;
}
}
timer.stop();
printf("MBED: Time taken: %fs\n", timer.read());
}
static void _sigio_handler(osThreadId id) {
@ -135,17 +160,18 @@ static void _sigio_handler(osThreadId id) {
void TCPSOCKET_RECV_100K_NONBLOCK()
{
TCPSocket sock;
_tcpsocket_connect_to_chargen_srv(sock);
TCPSocket sock;
nsapi_error_t err = _tcpsocket_connect_to_chargen_srv(sock);
if (err != NSAPI_ERROR_OK) {
TEST_FAIL();
return;
}
sock.set_blocking(false);
sock.sigio(callback(_sigio_handler, Thread::gettid()));
Timer timer;
timer.start();
rcv_n_chk_against_rfc864_pattern_nonblock(sock);
timer.stop();
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
printf("MBED: Time taken: %fs\n", timer.read());
}

11
TESTS/netsocket/tcp/tcpsocket_recv_timeout.cpp
View File

@ -39,6 +39,9 @@ void TCPSOCKET_RECV_TIMEOUT()
{
static const int DATA_LEN = 100;
char buff[DATA_LEN] = {0};
int time_allotted = split2half_rmng_tcp_test_time(); // [s]
Timer tc_exec_time;
tc_exec_time.start();
TCPSocket sock;
tcpsocket_connect_to_echo_srv(sock);
@ -59,8 +62,10 @@ void TCPSOCKET_RECV_TIMEOUT()
timer.stop();
if (recvd == NSAPI_ERROR_WOULD_BLOCK) {
if(osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout) {
if (tc_exec_time.read() >= time_allotted ||
(osSignalWait(SIGNAL_SIGIO, SIGIO_TIMEOUT).status == osEventTimeout)) {
TEST_FAIL();
goto CLEANUP;
}
printf("MBED: recv() took: %dms\n", timer.read_ms());
TEST_ASSERT_INT_WITHIN(50, 150, timer.read_ms());
@ -68,9 +73,13 @@ void TCPSOCKET_RECV_TIMEOUT()
} else if (recvd < 0) {
printf("[pkt#%02d] network error %d\n", i, recvd);
TEST_FAIL();
goto CLEANUP;
}
pkt_unrecvd -= recvd;
}
}
CLEANUP:
tc_exec_time.stop();
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
}

9
TESTS/netsocket/tcp/tcpsocket_send_repeat.cpp
View File

@ -30,12 +30,15 @@ void TCPSOCKET_SEND_REPEAT()
TCPSocket sock;
tcpsocket_connect_to_discard_srv(sock);
int err;
int snd;
Timer timer;
static const char tx_buffer[] = {'h','e','l','l','o'};
for (int i = 0; i < 1000; i++) {
err = sock.send(tx_buffer, sizeof(tx_buffer));
TEST_ASSERT_EQUAL(sizeof(tx_buffer), err);
snd = sock.send(tx_buffer, sizeof(tx_buffer));
if (snd != sizeof(tx_buffer)) {
TEST_FAIL();
break;
}
}
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());

13
TESTS/netsocket/tcp/tcpsocket_send_timeout.cpp
View File

@ -28,7 +28,10 @@ using namespace utest::v1;
void TCPSOCKET_SEND_TIMEOUT()
{
TCPSocket sock;
tcpsocket_connect_to_discard_srv(sock);
if (tcpsocket_connect_to_discard_srv(sock) != NSAPI_ERROR_OK) {
TEST_FAIL();
return;
}
int err;
Timer timer;
@ -38,8 +41,12 @@ void TCPSOCKET_SEND_TIMEOUT()
timer.start();
err = sock.send(tx_buffer, sizeof(tx_buffer));
timer.stop();
TEST_ASSERT_EQUAL(sizeof(tx_buffer), err);
TEST_ASSERT(timer.read_ms() <= 800);
if ((err == sizeof(tx_buffer)) &&
(timer.read_ms() <= 800)) {
continue;
}
TEST_FAIL();
break;
}
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());

11
TESTS/netsocket/tcp/tcpsocket_thread_per_socket_safety.cpp
View File

@ -65,11 +65,13 @@ static void check_const_len_rand_sequence()
if (sent == NSAPI_ERROR_WOULD_BLOCK) {
if(osSignalWait(SIGNAL_SIGIO1, SIGIO_TIMEOUT).status == osEventTimeout) {
TEST_FAIL();
goto END;
}
continue;
} else if (sent < 0) {
printf("network error %d\n", sent);
TEST_FAIL();
goto END;
}
bytes2process -= sent;
}
@ -82,6 +84,7 @@ static void check_const_len_rand_sequence()
} else if (recvd < 0) {
printf("network error %d\n", recvd);
TEST_FAIL();
goto END;
}
bytes2process -= recvd;
}
@ -89,9 +92,11 @@ static void check_const_len_rand_sequence()
if (bytes2process != 0) {
drop_bad_packets(sock, 0);
TEST_FAIL();
goto END;
}
TEST_ASSERT_EQUAL(0, memcmp(tx_buff, rx_buff, BUFF_SIZE));
}
END:
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
}
@ -117,11 +122,13 @@ static void check_var_len_rand_sequence()
if (sent == NSAPI_ERROR_WOULD_BLOCK) {
if(osSignalWait(SIGNAL_SIGIO2, SIGIO_TIMEOUT).status == osEventTimeout) {
TEST_FAIL();
goto END;
}
continue;
} else if (sent < 0) {
printf("[%02d] network error %d\n", i, sent);
TEST_FAIL();
goto END;
}
bytes2process -= sent;
}
@ -134,6 +141,7 @@ static void check_var_len_rand_sequence()
} else if (recvd < 0) {
printf("[%02d] network error %d\n", i, recvd);
TEST_FAIL();
goto END;
}
bytes2process -= recvd;
}
@ -141,10 +149,11 @@ static void check_var_len_rand_sequence()
if (bytes2process != 0) {
drop_bad_packets(sock, 0);
TEST_FAIL();
goto END;
}
TEST_ASSERT_EQUAL(0, memcmp(tx_buff, rx_buff, i));
}
END:
TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close());
}

9
features/FEATURE_LWIP/lwip-interface/mbed_lib.json
View File

@ -124,6 +124,15 @@
},
"LPC546XX": {
"mem-size": 36496
},
"EFM32GG11-STK3701": {
"mem-size": 36560
},
"RZ_A1_EMAC": {
"tcpip-thread-stacksize": 1328,
"default-thread-stacksize": 640,
"ppp-thread-stacksize": 896,
"mem-size": 51200
}
}
}

14
features/frameworks/unity/source/unity.c
View File

@ -29,6 +29,7 @@ static const char UnityStrOk[] = "OK";
static const char UnityStrPass[] = "PASS";
static const char UnityStrFail[] = "FAIL";
static const char UnityStrIgnore[] = "IGNORE";
static const char UnityStrSkip[] = "SKIP";
static const char UnityStrNull[] = "NULL";
static const char UnityStrSpacer[] = ". ";
static const char UnityStrExpected[] = " Expected ";
@ -1228,6 +1229,19 @@ void UnityIgnore(const char* msg, const UNITY_LINE_TYPE line)
UNITY_IGNORE_AND_BAIL;
}
/*-----------------------------------------------*/
void UnitySkipPrint(const char* msg, const UNITY_LINE_TYPE line)
{
UnityTestResultsBegin(Unity.TestFile, line);
UnityPrint(UnityStrSkip);
if (msg != NULL)
{
UNITY_OUTPUT_CHAR(':');
UNITY_OUTPUT_CHAR(' ');
UnityPrint(msg);
}
}
/*-----------------------------------------------*/
#if defined(UNITY_WEAK_ATTRIBUTE)
UNITY_WEAK_ATTRIBUTE void setUp(void) { }

11
features/frameworks/unity/unity/unity.h
View File

@ -294,6 +294,17 @@ void tearDown(void);
#define TEST_ASSERT_DOUBLE_IS_NOT_NAN_MESSAGE(actual, message) UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN((actual), __LINE__, (message))
#define TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE_MESSAGE(actual, message) UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE((actual), __LINE__, (message))
/*-------------------------------------------------------
* Test skipping
*-------------------------------------------------------*/
// Use these to skip the test case (marking it successful).
// Use only in test case function itself, and only if it returns nothing (void).
#define TEST_SKIP_MESSAGE(message) UNITY_TEST_SKIP(__LINE__, (message))
#define TEST_SKIP() UNITY_TEST_SKIP(__LINE__, NULL)
#define TEST_SKIP_UNLESS(condition) UNITY_TEST_SKIP_UNLESS((condition), __LINE__, NULL)
#define TEST_SKIP_UNLESS_MESSAGE(condition, message) UNITY_TEST_SKIP_UNLESS((condition), __LINE__, (message))
/* end of UNITY_FRAMEWORK_H */
#ifdef __cplusplus
}

9
features/frameworks/unity/unity/unity_internals.h
View File

@ -554,6 +554,8 @@ void UnityFail(const char* message, const UNITY_LINE_TYPE line);
void UnityIgnore(const char* message, const UNITY_LINE_TYPE line);
void UnitySkipPrint(const char* message, const UNITY_LINE_TYPE line);
#ifndef UNITY_EXCLUDE_FLOAT
void UnityAssertFloatsWithin(const _UF delta,
const _UF expected,
@ -785,6 +787,13 @@ extern const char UnityStrErr64[];
#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual, line, message) UnityAssertDoubleSpecial((_UD)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_DET)
#endif
/*-------------------------------------------------------
* Test skip
*-------------------------------------------------------*/
#define UNITY_TEST_SKIP(line, message) { UnitySkipPrint( (message), (UNITY_LINE_TYPE)(line)); return; }
#define UNITY_TEST_SKIP_UNLESS(condition, line, message) if (!(condition)) UNITY_TEST_SKIP((line), (message))
/* End of UNITY_INTERNALS_H */
#endif

74
features/frameworks/utest/TESTS/unit_tests/test_skip/main.cpp Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright (c) 2018 ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "utest/utest.h"
#include "unity/unity.h"
using namespace utest::v1;
int skipped_at_right_place = 0;
utest::v1::status_t test_skip_case_teardown(const Case *const source, const size_t passed, const size_t failed, const failure_t failure)
{
TEST_ASSERT_EQUAL(1, skipped_at_right_place);
greentea_case_teardown_handler(source, passed, failed, failure);
return STATUS_CONTINUE;
}
// Aborting Teardown Handler ------------------------------------------------------------------------------------------
void unconditional_test_skip_test()
{
TEST_SKIP();
// Should not get here
TEST_ASSERT(0);
}
void conditional_test_skip_test()
{
skipped_at_right_place = 0;
TEST_SKIP_UNLESS_MESSAGE(1, "Test skipped at the wrong place!");
skipped_at_right_place = 1;
TEST_SKIP_UNLESS_MESSAGE(0, "Test skipped at the right place.");
// Should not get here
skipped_at_right_place = 0;
TEST_ASSERT(0);
}
// Cases --------------------------------------------------------------------------------------------------------------
Case cases[] = {
Case("Unconditional test skip macro test", unconditional_test_skip_test),
Case("Conditional test skip macro test", conditional_test_skip_test, test_skip_case_teardown),
};
// Specification: Setup & Teardown ------------------------------------------------------------------------------------
utest::v1::status_t greentea_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(15, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_setup, cases);
int main()
{
// Run the specification only AFTER setting the custom scheduler(if required).
Harness::run(specification);
}

2
features/lorawan/lorastack/mac/LoRaMac.cpp
View File

@ -772,7 +772,7 @@ bool LoRaMac::continue_joining_process()
}
// Schedule a retry
if (handle_retransmission() != LORAWAN_STATUS_OK) {
if (handle_retransmission() != LORAWAN_STATUS_CONNECT_IN_PROGRESS) {
return false;
}

34
features/netsocket/emac-drivers/TARGET_Silicon_Labs/mbed_lib.json Normal file
View File

@ -0,0 +1,34 @@
{
"name": "sl-eth",
"config": {
"rmii-location": {
"help": "Location number to use for the RMII pins, see chip datasheet",
"value": null
},
"mdio-location": {
"help": "Location number to use for the MDIO pins, see chip datasheet",
"value": null
},
"refclk-location": {
"help": "Location number to use for the REFCLK output from CMU (CLKOUTSEL2), see chip datasheet",
"value": null
},
"phy-enable-pin": {
"help": "Pin attached to the PHY enable line",
"value": null
},
"phy-power-pin": {
"help": "Pin used to switch on power to the PHY. If not defined, we assume the PHY is always powered.",
"value": null
}
},
"target_overrides": {
"EFM32GG11_STK3701": {
"rmii-location": 1,
"mdio-location": 1,
"refclk-location": 5,
"phy-enable-pin": "PH7",
"phy-power-pin": "PI10"
}
}
}

712
features/netsocket/emac-drivers/TARGET_Silicon_Labs/sl_emac.cpp Normal file
View File

@ -0,0 +1,712 @@
/***************************************************************************//**
* @file sl_emac.cpp
*******************************************************************************
* @section License
* <b>(C) Copyright 2018 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include "device.h"
#if defined(ETH_PRESENT)
#include "sl_emac_config.h"
#include "sl_emac.h"
#include "sl_eth_hw.h"
#include "sl_eth_phy.h"
#include "mbed_power_mgmt.h"
#include <stdlib.h>
#include "mbed-trace/mbed_trace.h"
#define TRACE_GROUP "SEth"
#define FLAG_TX 1
#define FLAG_RX 2
#define FLAG_POLL 4
// -----------------------------------------------------------------------------
// Setup
// -----------------------------------------------------------------------------
bool SL_EMAC::power_up()
{
// If the worker thread doesn't exist, launch it
if(thread == 0) {
/* Worker thread */
osThreadAttr_t attr = {0};
attr.name = "sl_emac_thread";
attr.stack_mem = malloc(SL_ETH_THREAD_STACKSIZE);
attr.cb_mem = &thread_cb;
attr.stack_size = SL_ETH_THREAD_STACKSIZE;
attr.cb_size = sizeof(mbed_rtos_storage_thread_t);
attr.priority = SL_ETH_THREAD_PRIORITY;
thread = osThreadNew(&this->eth_thread, this, &attr);
}
// Can't turn off HF clock as long as Ethernet is active
sleep_manager_lock_deep_sleep();
// Bring up data structures
data_init();
// Bring up clocks
sl_eth_hw_init();
// Point to RX queue
ETH->RXQPTR = (uint32_t)rx_bds;
ETH->DMACFG = (ETH->DMACFG & ~_ETH_DMACFG_RXBUFSIZE_MASK)
| ((SL_ETH_RX_BUF_SIZE/64) << _ETH_DMACFG_RXBUFSIZE_SHIFT);
// Set up MAC address
uint8_t addr[6];
get_hwaddr(addr);
set_hwaddr(addr);
ETH->IFCR |= _ETH_IFCR_MASK;
ETH->RXSTATUS = 0xFFFFFFFF;
ETH->TXSTATUS = 0xFFFFFFFF;
ETH->IENS = ETH_IENS_RXCMPLT |
ETH_IENS_RXUSEDBITREAD |
ETH_IENS_TXCMPLT |
ETH_IENS_TXUNDERRUN |
ETH_IENS_RTRYLMTORLATECOL |
ETH_IENS_TXUSEDBITREAD |
ETH_IENS_AMBAERR |
ETH_IENS_MNGMNTDONE;
ETH->NETWORKCFG |= ETH_NETWORKCFG_FCSREMOVE |
ETH_NETWORKCFG_UNICASTHASHEN |
ETH_NETWORKCFG_MULTICASTHASHEN |
ETH_NETWORKCFG_RXCHKSUMOFFLOADEN;
ETH->NETWORKCFG |= ETH_NETWORKCFG_FULLDUPLEX |
ETH_NETWORKCFG_SPEED;
ETH->DMACFG |= _ETH_DMACFG_AMBABRSTLEN_MASK |
ETH_DMACFG_FRCDISCARDONERR |
ETH_DMACFG_TXPBUFTCPEN;
ETH->DMACFG &= ~ETH_DMACFG_HDRDATASPLITEN;
ETH->NETWORKCTRL |= ETH_NETWORKCTRL_ENBTX |
ETH_NETWORKCTRL_ENBRX |
ETH_NETWORKCTRL_MANPORTEN;
phy_init();
NVIC_EnableIRQ(ETH_IRQn);
up = true;
tr_debug("Link booted");
osThreadFlagsSet(thread, FLAG_POLL);
return true;
}
void SL_EMAC::power_down()
{
up = false;
tr_debug("Link coming down, waiting for TX to be done.");
tx_sem.wait();
NVIC_DisableIRQ(ETH_IRQn);
sl_eth_hw_deinit();
data_deinit();
/* link is down */
if(connected && emac_link_state_cb) {
emac_link_state_cb(false);
}
connected = false;
tr_debug("Link down");
// Ethernet went down, HF clock is no longer required here
sleep_manager_unlock_deep_sleep();
}
void SL_EMAC::data_init(void)
{
size_t i;
/* Allocate a full-frame buffer for each RX BD and set up said BD */
for(i = 0; i < SL_ETH_NUM_RX_BD; i++) {
rx_bufs[i] = memory_manager->alloc_heap(SL_ETH_RX_BUF_SIZE, SL_ETH_ALIGN);
rx_bds[i].addr = ((uint32_t)memory_manager->get_ptr(rx_bufs[i])) & ~0x3;
if(i == SL_ETH_NUM_RX_BD-1) {
rx_bds[i].addr |= 0x2;
}
rx_bds[i].status = 0;
}
/* Set up TX BDs */
tx_buf = (emac_mem_buf_t*)NULL;
for(i = 0; i < SL_ETH_NUM_TX_BD; i++) {
tx_bds[i].addr = 0;
tx_bds[i].status = 0;
if(i == SL_ETH_NUM_TX_BD-1) {
tx_bds[i].status |= (0x1 << 30);
}
}
/* Start RX reception at index 0 */
rx_idx = 0;
}
void SL_EMAC::data_deinit(void)
{
for(size_t i = 0; i < SL_ETH_NUM_RX_BD; i++) {
memory_manager->free(rx_bufs[i]);
}
}
// -----------------------------------------------------------------------------
// IRQ & IRQ de-escalation logic
// -----------------------------------------------------------------------------
/* IRQ handler for ethernet interrupts */
void ETH_IRQHandler(void)
{
uint32_t int_clr = 0;
uint32_t int_status = ETH->IFCR;
uint32_t txdone_mask = ETH_IFCR_TXCMPLT |
ETH_IFCR_TXUNDERRUN |
ETH_IFCR_RTRYLMTORLATECOL |
ETH_IFCR_TXUSEDBITREAD |
ETH_IFCR_AMBAERR;
uint32_t rxdone_mask = ETH_IFCR_RXCMPLT |
ETH_IFCR_RXUSEDBITREAD;
SL_EMAC &emac = SL_EMAC::get_instance();
if(int_status & rxdone_mask) {
if (emac.thread) {
osThreadFlagsSet(emac.thread, FLAG_RX);
}
int_clr |= rxdone_mask;
}
if(int_status & txdone_mask) {
if (emac.thread) {
osThreadFlagsSet(emac.thread, FLAG_TX);
}
int_clr |= txdone_mask;
}
int_clr |= ETH_IFCR_MNGMNTDONE;
ETH->IFCR = int_clr;
}
void SL_EMAC::eth_thread(void* instance)
{
struct SL_EMAC *emac = static_cast<SL_EMAC *>(instance);
for (;;) {
uint32_t flags = osThreadFlagsWait(FLAG_RX|FLAG_TX|FLAG_POLL, osFlagsWaitAny, SL_ETH_LINK_POLL_PERIOD_MS);
if ((flags == osFlagsErrorTimeout) && emac->up) {
// Rather than calling strictly every period, we call when idle
// for that period - hopefully good enough. We run this task
// from lwIP's thread rather than our RX/TX thread, as PHY reads can
// be slow, and we don't want them to interfere with data pumping.
// This is analogous to the way the PHY polling works in the Nanostack
// version of the driver
emac->link_state_poll();
continue;
}
if((flags & FLAG_POLL)) {
emac->link_state_poll();
continue;
}
MBED_ASSERT((flags & osFlagsError) == 0);
/* Packet received */
if ((flags & FLAG_RX) && emac->up) {
/* Find packets in the RX BD chain which have been fully received. Feed the
* corresponding buffer upstream, and attach a new buffer to the BD. */
while(emac->rx_bds[emac->rx_idx].addr & 0x1) {
/* DMA has relinquished control over this packet */
emac_mem_buf_t* buf = emac->rx_bufs[emac->rx_idx];
emac->memory_manager->set_len(buf, emac->rx_bds[emac->rx_idx].status & 0x1FFF);
tr_debug("Received packet of size %d", emac->memory_manager->get_len(buf));
/* Attempt to queue new buffer */
emac_mem_buf_t* temp_rxbuf = emac->memory_manager->alloc_heap(SL_ETH_RX_BUF_SIZE, 4);
if (NULL == temp_rxbuf) {
/* out of memory, drop packet */
tr_warn("Packet index %d dropped for OOM",
emac->rx_idx);
emac->rx_bds[emac->rx_idx].addr &= ~0x1;
} else {
emac->rx_bufs[emac->rx_idx] = temp_rxbuf;
emac->rx_bds[emac->rx_idx].status = 0;
if(emac->rx_bds[emac->rx_idx].addr & 0x2) {
emac->rx_bds[emac->rx_idx].addr = (uint32_t)emac->memory_manager->get_ptr(temp_rxbuf) | 0x2;
} else {
emac->rx_bds[emac->rx_idx].addr = (uint32_t)emac->memory_manager->get_ptr(temp_rxbuf);
}
/* pass all packets to ethernet_input, which decides what packets it supports */
if(emac->emac_link_input_cb) {
emac->emac_link_input_cb(buf);
}
}
emac->rx_idx = (emac->rx_idx + 1) % SL_ETH_NUM_RX_BD;
}
}
/* Packet transmission done */
if (flags & FLAG_TX) {
/* Free the buffer */
if(emac->tx_buf != NULL) {
emac->memory_manager->free(emac->tx_buf);
emac->tx_buf = NULL;
}
/* Signal TX thread(s) we're ready to start TX'ing */
emac->tx_sem.release();
}
}
}
// -----------------------------------------------------------------------------
// PHY manipulation
// -----------------------------------------------------------------------------
void SL_EMAC::phy_init(void)
{
uint8_t phy_addr = 0;
uint16_t regid1, regid2;
/* PHY has been enabled by hw_init. Figure out address first */
for(; phy_addr < 32; phy_addr++) {
read_phy(PHY_PHYSID1, &regid1);
read_phy(PHY_PHYSID2, &regid2);
if (((regid1 == 0x0000u) && (regid2 == 0x0000u)) ||
((regid1 == 0x3FFFu) && (regid2 == 0x0000u)) ||
((regid1 == 0x0000u) && (regid2 == 0x3FFFu)) ||
((regid1 == 0x3FFFu) && (regid2 == 0x3FFFu)) ||
((regid1 == 0xFFFFu) && (regid2 == 0x0000u)) ||
((regid1 == 0x0000u) && (regid2 == 0xFFFFu)) ||
((regid1 == 0x3FFFu) && (regid2 == 0xFFFFu)) ||
((regid1 == 0xFFFFu) && (regid2 == 0xFFFFu))) {
continue;
} else {
break;
}
}
if(phy_addr >= 32) {
/* no PHY found */
this->phy_addr = 0xFF;
return;
} else {
this->phy_addr = phy_addr;
}
/* Reset PHY */
write_phy(PHY_BMCR, BMCR_RESET);
read_phy(PHY_BMCR, &regid1);
/* wait for PHY to come out of reset */
while(regid1 & BMCR_RESET) {
osDelay(2);
read_phy(PHY_BMCR, &regid1);
}
/* Enable PHY */
if(regid1 & BMCR_PDOWN) {
write_phy(PHY_BMCR, regid1 & (~BMCR_PDOWN));
}
/* Set up auto-negotiation */
read_phy(PHY_BMCR, &regid1);
regid1 |= BMCR_ANENABLE | BMCR_ANRESTART;
write_phy(PHY_BMCR, regid1);
}
void SL_EMAC::write_phy(uint8_t reg_addr, uint16_t data)
{
unsigned int timeout;
ETH->PHYMNGMNT = ETH_PHYMNGMNT_WRITE0_DEFAULT
| ETH_PHYMNGMNT_WRITE1
| (0x01 << _ETH_PHYMNGMNT_OPERATION_SHIFT)
| ((phy_addr << _ETH_PHYMNGMNT_PHYADDR_SHIFT)
& _ETH_PHYMNGMNT_PHYADDR_MASK)
| ((reg_addr << _ETH_PHYMNGMNT_REGADDR_SHIFT)
& _ETH_PHYMNGMNT_REGADDR_MASK)
| (0x2 << _ETH_PHYMNGMNT_WRITE10_SHIFT)
| (data & _ETH_PHYMNGMNT_PHYRWDATA_MASK);
for(timeout = 0; timeout < 10000u; timeout++) {
if(ETH->NETWORKSTATUS & ETH_NETWORKSTATUS_MANDONE) {
break;
}
}
}
void SL_EMAC::read_phy(uint8_t reg_addr, uint16_t *data)
{
unsigned int timeout;
ETH->PHYMNGMNT = ETH_PHYMNGMNT_WRITE0_DEFAULT
| ETH_PHYMNGMNT_WRITE1
| (0x02 << _ETH_PHYMNGMNT_OPERATION_SHIFT)
| ((phy_addr << _ETH_PHYMNGMNT_PHYADDR_SHIFT)
& _ETH_PHYMNGMNT_PHYADDR_MASK)
| ((reg_addr << _ETH_PHYMNGMNT_REGADDR_SHIFT)
& _ETH_PHYMNGMNT_REGADDR_MASK)
| (0x2 << _ETH_PHYMNGMNT_WRITE10_SHIFT);
for(timeout = 0; timeout < 10000u; timeout++) {
if(ETH->NETWORKSTATUS & ETH_NETWORKSTATUS_MANDONE) {
break;
}
}
*data = ETH->PHYMNGMNT & _ETH_PHYMNGMNT_PHYRWDATA_MASK;
}
void SL_EMAC::link_state_poll(void)
{
uint16_t phy_val, link_val;
/* read BMSR twice, since it needs to latch */
read_phy(PHY_BMSR, &phy_val);
read_phy(PHY_BMSR, &phy_val);
if((phy_val & BMSR_LSTATUS) == 0) {
/* link is down */
tr_debug("link down");
if(connected && emac_link_state_cb) {
emac_link_state_cb(false);
/* TODO: Reset all buffers here */
/* For now, this is not a problem. In-transit buffers will
* still be sent the next time the link comes up, so the
* only impact is that we'd be sending stale packets. */
}
connected = false;
return;
}
/* link is up, get speed and duplex status */
read_phy(PHY_ANAR, &phy_val);
read_phy(PHY_ANLPAR, &link_val);
link_val &= (ANLPAR_100BASE4 |
ANLPAR_100FULL |
ANLPAR_100HALF |
ANLPAR_10FULL |
ANLPAR_10HALF);
phy_val &= link_val;
uint32_t old_link_state = ETH->NETWORKCFG & 0x3;
if (phy_val >= ANLPAR_100FULL) {
/* 100 mbit full duplex */
if (old_link_state != 0x3 || !connected) {
tr_debug("renegotiated to 100 full");
ETH->NETWORKCFG = (ETH->NETWORKCFG & ~0x3) | 0x3;
}
} else if (phy_val >= ANLPAR_100HALF) {
/* 100 mbit half duplex */
if (old_link_state != 0x1 || !connected) {
tr_debug("renegotiated to 100 half");
ETH->NETWORKCFG = (ETH->NETWORKCFG & ~0x3) | 0x1;
}
} else if (phy_val >= ANLPAR_10FULL) {
/* 10 mbit full duplex */
if (old_link_state != 0x2 || !connected) {
tr_debug("renegotiated to 10 full");
ETH->NETWORKCFG = (ETH->NETWORKCFG & ~0x3) | 0x2;
}
} else {
/* 10 mbit half duplex */
if (old_link_state != 0x0 || !connected) {
tr_debug("renegotiated to 10 half");
ETH->NETWORKCFG = (ETH->NETWORKCFG & ~0x3) | 0x0;
}
}
if(!connected && emac_link_state_cb) {
tr_debug("link up");
emac_link_state_cb(true);
}
connected = true;
}
// -----------------------------------------------------------------------------
// Receive
// -----------------------------------------------------------------------------
/* Handled inside processing thread */
// -----------------------------------------------------------------------------
// Send
// -----------------------------------------------------------------------------
bool SL_EMAC::link_out(emac_mem_buf_t *buf)
{
size_t num_bufs = 1, i;
emac_mem_buf_t * next = buf;
/* If the link is down (or going down), don't even attempt sending anything */
if(!up) {
tr_debug("Trying to send a packet while link is down");
memory_manager->free(buf);
return false;
}
/* Figure out how many buffers the buffer consists of */
while((next = memory_manager->get_next(next)) != (emac_mem_buf_t*)NULL) {
num_bufs++;
}
if(num_bufs >= SL_ETH_NUM_TX_BD) {
/* We've been passed more chained buffers than we can handle */
tr_err("More TX buffers passed than provisioned!");
memory_manager->free(buf);
return false;
}
/* Wait for previous packet to finish transmitting */
int32_t stat = tx_sem.wait(100);
if (stat <= 0) {
tr_warn("TX process didn't complete within 100ms");
memory_manager->free(buf);
return false;
}
tr_debug("Sending packet of %d bytes over %d buffers", memory_manager->get_total_len(buf), num_bufs);
/* Set up TX descriptors with buffer, keep track of buffer reference */
tx_buf = buf;
for(i = 0; i < num_bufs; i++) {
uint32_t statusword = memory_manager->get_len(buf) & 0x3FFF;
if(i == (SL_ETH_NUM_TX_BD-1)) {
/* Mark as last BD in list */
statusword |= (0x1 << 30);
}
if(i == num_bufs - 1) {
/* Mark as last BD for this frame */
statusword |= (0x1 << 15);
}
tx_bds[i].addr = (uint32_t)memory_manager->get_ptr(buf);
tx_bds[i].status = statusword;
buf = memory_manager->get_next(buf);
}
/* (Re-)Kick off ETH TX */
ETH->TXQPTR = (uint32_t)tx_bds;
ETH->NETWORKCTRL |= ETH_NETWORKCTRL_TXSTRT;
return true;
}
// -----------------------------------------------------------------------------
// Multicast manipulation
// -----------------------------------------------------------------------------
static uint8_t sl_eth_calc_hash(const uint8_t* const mac)
{
return (uint8_t)(( (mac[0] & 0x3F) & 0x3F)
^ ((((mac[0] >> 6) & 0x3) | ((mac[1] & 0xF) << 2)) & 0x3F)
^ ((((mac[1] >> 4) & 0xF) | ((mac[2] & 0x3) << 4)) & 0x3F)
^ ((((mac[2] >> 2) & 0x3F)) & 0x3F)
^ ((mac[3] & 0x3F) & 0x3F)
^ ((((mac[3] >> 6) & 0x3) | ((mac[4] & 0xF) << 2)) & 0x3F)
^ ((((mac[4] >> 4) & 0xF) | ((mac[5] & 0x3) << 4)) & 0x3F)
^ ((((mac[5] >> 2) & 0x3F)) & 0x3F));
}
void SL_EMAC::add_multicast_group(const uint8_t *address)
{
uint8_t bitnr;
/* Calculate bit number for hash of this address */
bitnr = sl_eth_calc_hash(address);
/* Increment refcnt */
if (mcast_hash_refcnt[bitnr] == 0) {
if(bitnr > 31) {
ETH->HASHTOP |= (0x1 << (bitnr - 32));
} else {
ETH->HASHBOTTOM |= (0x1 << bitnr);
}
}
mcast_hash_refcnt[bitnr]++;
}
void SL_EMAC::remove_multicast_group(const uint8_t *address)
{
uint8_t bitnr;
/* Calculate bit number for hash of this address */
bitnr = sl_eth_calc_hash(address);
/* Decrement refcnt, remove bit if 0 */
if(mcast_hash_refcnt[bitnr] == 1) {
mcast_hash_refcnt[bitnr] = 0;
if(bitnr > 31) {
ETH->HASHTOP &= ~(0x1 << (bitnr - 32));
} else {
ETH->HASHBOTTOM &= ~(0x1 << bitnr);
}
} else {
mcast_hash_refcnt[bitnr]--;
}
}
void SL_EMAC::set_all_multicast(bool all)
{
uint32_t bottom = 0, top = 0;
if(all == true) {
/* temporarily allow all packets to get processed */
tr_debug("Accept all multicast packets");
top = 0xFFFFFFFFUL;
bottom = 0xFFFFFFFFUL;
} else {
/* Revert to what was in the refcount */
tr_debug("Revert to multicast filtering");
size_t i = 0;
for(; i < 32; i++) {
if(mcast_hash_refcnt[i] > 0) {
bottom |= (1 << i);
}
}
for(; i < 64; i++) {
if(mcast_hash_refcnt[i-32] > 0) {
top |= (1 << (i-32));
}
}
}
/* Commit to peripheral */
ETH->HASHTOP = top;
ETH->HASHBOTTOM = bottom;
}
// -----------------------------------------------------------------------------
// MAC manipulation
// -----------------------------------------------------------------------------
uint8_t SL_EMAC::get_hwaddr_size() const
{
// Ethernet uses EUI48
return 6;
}
bool SL_EMAC::get_hwaddr(uint8_t *addr) const
{
if (DEVINFO->EUI48L != 0xFFFFFFFF) {
addr[0] = DEVINFO->EUI48H >> 8;
addr[1] = DEVINFO->EUI48H >> 0;
addr[2] = DEVINFO->EUI48L >> 24;
addr[3] = DEVINFO->EUI48L >> 16;
addr[4] = DEVINFO->EUI48L >> 8;
addr[5] = DEVINFO->EUI48L >> 0;
} else {
addr[0] = DEVINFO->UNIQUEH >> 24;
addr[1] = DEVINFO->UNIQUEH >> 16;
addr[2] = DEVINFO->UNIQUEH >> 8;
addr[3] = DEVINFO->UNIQUEL >> 16;
addr[4] = DEVINFO->UNIQUEL >> 8;
addr[5] = DEVINFO->UNIQUEL >> 0;
}
return true;
}
void SL_EMAC::set_hwaddr(const uint8_t *addr)
{
tr_debug("Setting MAC address %02x:%02x:%02x:%02x:%02x:%02x",
addr[0],
addr[1],
addr[2],
addr[3],
addr[4],
addr[5]);
ETH->SPECADDR1BOTTOM = ((uint32_t)addr[0] << (0)) |
((uint32_t)addr[1] << (8)) |
((uint32_t)addr[2] << (16))|
((uint32_t)addr[3] << (24));
ETH->SPECADDR1TOP = ((uint32_t)addr[4] << (0)) |
((uint32_t)addr[5] << (8));
}
// -----------------------------------------------------------------------------
// Boilerplate
// -----------------------------------------------------------------------------
SL_EMAC::SL_EMAC()
: thread(0),
tx_sem(1, 1),
phy_addr(0xFF),
rx_idx(0),
mcast_hash_refcnt(),
emac_link_input_cb(NULL),
emac_link_state_cb(NULL),
memory_manager(NULL),
connected(false),
up(false)
{
}
uint32_t SL_EMAC::get_mtu_size() const
{
return SL_ETH_MTU;
}
uint32_t SL_EMAC::get_align_preference() const
{
return SL_ETH_ALIGN;
}
void SL_EMAC::get_ifname(char *name, uint8_t size) const
{
memcpy(name, SL_ETH_IF_NAME, (size < sizeof(SL_ETH_IF_NAME)) ? size : sizeof(SL_ETH_IF_NAME));
}
void SL_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
{
emac_link_input_cb = input_cb;
}
void SL_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
{
emac_link_state_cb = state_cb;
}
void SL_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
{
memory_manager = &mem_mngr;
}
SL_EMAC &SL_EMAC::get_instance() {
static SL_EMAC emac;
return emac;
}
MBED_WEAK EMAC &EMAC::get_default_instance() {
return SL_EMAC::get_instance();
}
#endif //ETH_PRESENT

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/***************************************************************************//**
* @file sl_eth_phy.h
*******************************************************************************
* @section License
* <b>modifications (C) Copyright 2018 Silicon Labs, http://www.silabs.com</b>
* <b>original Copyright (c) 2015 ARM Limited</b>
*******************************************************************************
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef SL_EMAC_H_
#define SL_EMAC_H_
#include "EMAC.h"
#include "rtos/Semaphore.h"
#include "rtos/Mutex.h"
class SL_EMAC : public EMAC {
public:
SL_EMAC();
static SL_EMAC &get_instance();
/**
* Return maximum transmission unit
*
* @return MTU in bytes
*/
virtual uint32_t get_mtu_size() const;
/**
* Gets memory buffer alignment preference
*
* Gets preferred memory buffer alignment of the Emac device.
* IP stack may or may not align link out memory buffer chains
* using the alignment.
*
* @return Memory alignment requirement in bytes
*/
virtual uint32_t get_align_preference() const;
/**
* Return interface name
*
* @param name Pointer to where the name should be written
* @param size Maximum number of character to copy
*/
virtual void get_ifname(char *name, uint8_t size) const;
/**
* Returns size of the underlying interface HW address size.
*
* @return HW address size in bytes
*/
virtual uint8_t get_hwaddr_size() const;
/**
* Return interface-supplied HW address
*
* Copies HW address to provided memory, @param addr has to be of correct
* size see @a get_hwaddr_size
*
* HW address need not be provided if this interface does not have its own
* HW address configuration; stack will choose address from central system
* configuration if the function returns false and does not write to addr.
*
* @param addr HW address for underlying interface
* @return true if HW address is available
*/
virtual bool get_hwaddr(uint8_t *addr) const;
/**
* Set HW address for interface
*
* Provided address has to be of correct size, see @a get_hwaddr_size
*
* Called to set the MAC address to actually use - if @a get_hwaddr is
* provided the stack would normally use that, but it could be overridden,
* eg for test purposes.
*
* @param addr Address to be set
*/
virtual void set_hwaddr(const uint8_t *addr);
/**
* Sends the packet over the link
*
* That can not be called from an interrupt context.
*
* @param buf Packet to be send
* @return True if the packet was send successfully, False otherwise
*/
virtual bool link_out(emac_mem_buf_t *buf);
/**
* Initializes the HW
*
* @return True on success, False in case of an error.
*/
virtual bool power_up();
/**
* Deinitializes the HW
*
*/
virtual void power_down();
/**
* Sets a callback that needs to be called for packets received for that
* interface
*
* @param input_cb Function to be register as a callback
*/
virtual void set_link_input_cb(emac_link_input_cb_t input_cb);
/**
* Sets a callback that needs to be called on link status changes for given
* interface
*
* @param state_cb Function to be register as a callback
*/
virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb);
/** Add device to a multicast group
*
* @param address A multicast group hardware address
*/
virtual void add_multicast_group(const uint8_t *address);
/** Remove device from a multicast group
*
* @param address A multicast group hardware address
*/
virtual void remove_multicast_group(const uint8_t *address);
/** Request reception of all multicast packets
*
* @param all True to receive all multicasts
* False to receive only multicasts addressed to specified groups
*/
virtual void set_all_multicast(bool all);
/** Sets memory manager that is used to handle memory buffers
*
* @param mem_mngr Pointer to memory manager
*/
virtual void set_memory_manager(EMACMemoryManager &mem_mngr);
osThreadId_t thread; /** Ethernet driver thread */
private:
/* Instance variables */
/** Semaphore protecting the TX state.
* Not a mutex since we're posting from IRQ
*/
rtos::Semaphore tx_sem;
/** (R)MII address where the detected PHY is residing */
uint8_t phy_addr;
/** Index in RX queue for next packet to read */
uint8_t rx_idx;
/** Multicast mask reference count. Multicast filtering is done using a hash
* bit, so multiple multicast addresses might map to the same bit. That's
* why there needs to be a reference count for every bit in the 64-bit mask
*/
uint8_t mcast_hash_refcnt[64];
/** Local reference to the buffer that's in the process of being sent */
emac_mem_buf_t *tx_buf;
/** List of current RX buffers, which autonomously get filled by the
* Ethernet peripheral.
*/
emac_mem_buf_t *rx_bufs[SL_ETH_NUM_RX_BD];
typedef struct {
uint32_t addr;
uint32_t status;
} sl_eth_bd_t;
/** Internal list of DMA descriptors for the RX buffer pool */
sl_eth_bd_t rx_bds[SL_ETH_NUM_RX_BD];
/** Internal list of DMA descriptors to point to the current buffer being
* sent */
sl_eth_bd_t tx_bds[SL_ETH_NUM_TX_BD];
/**< Processing thread */
mbed_rtos_storage_thread_t thread_cb;
/**< Callback for incoming data */
emac_link_input_cb_t emac_link_input_cb;
/**< Callback for link state change */
emac_link_state_change_cb_t emac_link_state_cb;
/**< Memory manager instance */
EMACMemoryManager *memory_manager;
bool connected;
bool up;
/* private functions */
/**
* Thread to de-escalate Ethernet peripheral IRQ's
*/
static void eth_thread(void* instance);
/**
* This function polls the (R)MII bus for the first
* available attached PHY chip, resets and enables the PHY
* in auto-negotiation mode.
*/
void phy_init(void);
/**
* Write to detected PHY register. Nop if no PHY initialized.
*/
void write_phy(uint8_t reg_addr, uint16_t data);
/**
* Read from detected PHY register. Nop if no PHY initialized.
*/
void read_phy(uint8_t reg_addr, uint16_t *data);
/**
* This function checks the detected PHY for its
* current link status. Nop if no PHY was previously detected.
* Fires callback set by set_link_state_cb on change in link state.
*/
void link_state_poll(void);
/**
* Initializes buffer structures
*/
void data_init(void);
/**
* De-initializes buffer structures
*/
void data_deinit(void);
};
#endif /* SL_EMAC_H_ */

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/***************************************************************************//**
* @file sl_emac_config.h
*******************************************************************************
* @section License
* <b>(C) Copyright 2018 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef SL_EMAC_CONFIG_H
#define SL_EMAC_CONFIG_H
// -----------------------------------------------------------------------------
// Config options
// -----------------------------------------------------------------------------
/** Number of descriptors in receive list */
#define SL_ETH_NUM_RX_BD (16)
/** Number of descriptors in transmit list */
#define SL_ETH_NUM_TX_BD (8)
/** Size of one buffer in a buffer descriptor (must be multiple of 64) */
#define SL_ETH_RX_BUF_SIZE (1536)
/** Timeout in milliseconds for polling the PHY link status */
#define SL_ETH_LINK_POLL_PERIOD_MS (500)
/** Default Ethernet worker thread stack size in bytes */
#define SL_ETH_THREAD_STACKSIZE (512)
/** Default Ethernet worker thread stack priority */
#define SL_ETH_THREAD_PRIORITY (osPriorityHigh)
/** Name of interface */
#define SL_ETH_IF_NAME "sl"
/** Required alignment (in bytes) for packet buffers */
#define SL_ETH_ALIGN (16)
/** Link MTU */
#define SL_ETH_MTU (1500)
#endif /* SL_EMAC_CONFIG_H */

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/***************************************************************************//**
* @file sl_eth_hw.c
*******************************************************************************
* @section License
* <b>(C) Copyright 2017 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include "sl_eth_hw.h"
#include "device.h"
#include "em_cmu.h"
#include "em_gpio.h"
#include "hal/gpio_api.h"
#if defined(ETH_PRESENT)
void sl_eth_hw_init(void)
{
/* Turn on clocks to ETH */
CMU_ClockEnable(cmuClock_HFPER, true);
CMU_ClockEnable(cmuClock_ETH, true);
CMU_ClockEnable(cmuClock_GPIO, true);
/* Drive RMII from the MCU-side 50MHz clock */
GPIO_PinModeSet(AF_CMU_CLK2_PORT(MBED_CONF_SL_ETH_REFCLK_LOCATION),
AF_CMU_CLK2_PIN(MBED_CONF_SL_ETH_REFCLK_LOCATION),
gpioModePushPull, 0);
CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO;
CMU->ROUTELOC0 = (CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK) | (MBED_CONF_SL_ETH_REFCLK_LOCATION << _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT);
CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN;
ETH->CTRL = ETH_CTRL_GBLCLKEN | ETH_CTRL_MIISEL_RMII;
/* Set pins to ETH for RMII config */
GPIO_PinModeSet(AF_ETH_RMIICRSDV_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIICRSDV_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeInput, 0); /* CRS_DV */
GPIO_PinModeSet(AF_ETH_RMIITXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIITXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModePushPull, 0); /* TXD0 */
GPIO_PinModeSet(AF_ETH_RMIITXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIITXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModePushPull, 0); /* TXD1 */
GPIO_PinModeSet(AF_ETH_RMIITXEN_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIITXEN_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModePushPull, 0); /* TX_EN */
GPIO_PinModeSet(AF_ETH_RMIIRXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIIRXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeInput, 0); /* RXD0 */
GPIO_PinModeSet(AF_ETH_RMIIRXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIIRXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeInput, 0); /* RXD1 */
GPIO_PinModeSet(AF_ETH_RMIIRXER_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIIRXER_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeInput, 0); /* RX_ER */
/* Setup route locations and enable pins */
ETH->ROUTELOC1 = (MBED_CONF_SL_ETH_RMII_LOCATION << _ETH_ROUTELOC1_RMIILOC_SHIFT)
| (MBED_CONF_SL_ETH_MDIO_LOCATION << _ETH_ROUTELOC1_MDIOLOC_SHIFT);
ETH->ROUTEPEN = ETH_ROUTEPEN_RMIIPEN | ETH_ROUTEPEN_MDIOPEN;
ETH->ROUTEPEN = ETH_ROUTEPEN_RMIIPEN | ETH_ROUTEPEN_MDIOPEN;
/* Setup the MDIO pins */
GPIO_PinModeSet(AF_ETH_MDIO_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
AF_ETH_MDIO_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
gpioModePushPull, 0); /* MDIO */
GPIO_PinModeSet(AF_ETH_MDC_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
AF_ETH_MDC_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
gpioModePushPull, 0); /* MDC */
/* Enable the PHY on the STK */
#if defined(MBED_CONF_SL_ETH_PHY_POWER_PIN)
gpio_t pwr_pin;
gpio_init_out_ex(&pwr_pin, MBED_CONF_SL_ETH_PHY_POWER_PIN, 1);
#endif
#if defined(MBED_CONF_SL_ETH_PHY_ENABLE_PIN)
gpio_t en_pin;
gpio_init_out_ex(&en_pin, MBED_CONF_SL_ETH_PHY_ENABLE_PIN, 1);
#endif
}
void sl_eth_hw_deinit(void)
{
/* Turn off PHY */
#if defined(MBED_CONF_SL_ETH_PHY_POWER_PIN)
gpio_t pwr_pin;
gpio_init(&pwr_pin, MBED_CONF_SL_ETH_PHY_ENABLE_PIN);
gpio_write(&pwr_pin, 0);
gpio_mode(&pwr_pin, Disabled);
#endif
#if defined(MBED_CONF_SL_ETH_PHY_ENABLE_PIN)
gpio_t en_pin;
gpio_init(&en_pin, MBED_CONF_SL_ETH_PHY_POWER_PIN);
gpio_write(&en_pin, 0);
gpio_mode(&en_pin, Disabled);
#endif
/* Turn off MAC */
ETH->ROUTEPEN = 0;
ETH->CTRL = _ETH_CTRL_RESETVALUE;
/* Turn off clock */
CMU->CTRL &= ~CMU_CTRL_CLKOUTSEL2_HFXO;
CMU->ROUTEPEN &= ~CMU_ROUTEPEN_CLKOUT2PEN;
CMU_ClockEnable(cmuClock_ETH, false);
/* Set used pins back to disabled */
GPIO_PinModeSet(AF_ETH_MDIO_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
AF_ETH_MDIO_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
gpioModeDisabled, 0); /* MDIO */
GPIO_PinModeSet(AF_ETH_MDC_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
AF_ETH_MDC_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
gpioModeDisabled, 0); /* MDC */
GPIO_PinModeSet(AF_ETH_RMIICRSDV_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIICRSDV_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeDisabled, 0); /* CRS_DV */
GPIO_PinModeSet(AF_ETH_RMIITXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIITXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeDisabled, 0); /* TXD0 */
GPIO_PinModeSet(AF_ETH_RMIITXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIITXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeDisabled, 0); /* TXD1 */
GPIO_PinModeSet(AF_ETH_RMIITXEN_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIITXEN_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeDisabled, 0); /* TX_EN */
GPIO_PinModeSet(AF_ETH_RMIIRXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIIRXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeDisabled, 0); /* RXD0 */
GPIO_PinModeSet(AF_ETH_RMIIRXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIIRXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeDisabled, 0); /* RXD1 */
GPIO_PinModeSet(AF_ETH_RMIIRXER_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
AF_ETH_RMIIRXER_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
gpioModeDisabled, 0); /* RX_ER */
GPIO_PinModeSet(AF_CMU_CLK2_PORT(MBED_CONF_SL_ETH_REFCLK_LOCATION),
AF_CMU_CLK2_PIN(MBED_CONF_SL_ETH_REFCLK_LOCATION),
gpioModeDisabled, 0); /* REF_CLK */
}
#endif //ETH_PRESENT

44
features/netsocket/emac-drivers/TARGET_Silicon_Labs/sl_eth_hw.h Normal file
View File

@ -0,0 +1,44 @@
/***************************************************************************//**
* @file sl_eth_hw.h
*******************************************************************************
* @section License
* <b>(C) Copyright 2018 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef SL_ETH_HW_H
#define SL_ETH_HW_H
#if defined(__cplusplus)
extern "C" {
#endif
/**
* Sets up hardware pins and configures internal clocks
*/
void sl_eth_hw_init(void);
/**
* Releases hardware pins and turns off internal clocks
*/
void sl_eth_hw_deinit(void);
#if defined(__cplusplus)
}
#endif
#endif

94
features/netsocket/emac-drivers/TARGET_Silicon_Labs/sl_eth_phy.h Normal file
View File

@ -0,0 +1,94 @@
/***************************************************************************//**
* @file sl_eth_phy.h
*******************************************************************************
* @section License
* <b>(C) Copyright 2017 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef __SL_ETH_PHY_H__
#define __SL_ETH_PHY_H__
#define PHY_BMCR 0x00u /* Basic mode control reg. */
#define PHY_BMSR 0x01u /* Basic mode status reg. */
#define PHY_PHYSID1 0x02u /* PHYS ID 1 reg. */
#define PHY_PHYSID2 0x03u /* PHYS ID 2 reg. */
#define PHY_ANAR 0x04u /* Advertisement control reg. */
#define PHY_ANLPAR 0x05u /* Link partner ability reg. */
#define PHY_ANER 0x06u /* Expansion reg. */
#define PHY_ANNPTR 0x07u /* Next page transmit reg. */
/* -------------- PHY_BMCR REGISTER BITS -------------- */
#define BMCR_CTST (0x1 << 7) /* Collision test. */
#define BMCR_FULLDPLX (0x1 << 8) /* Full duplex. */
#define BMCR_ANRESTART (0x1 << 9) /* Auto negotiation restart. */
#define BMCR_ISOLATE (0x1 << 10) /* Disconnect Phy from MII. */
#define BMCR_PDOWN (0x1 << 11) /* Power down. */
#define BMCR_ANENABLE (0x1 << 12) /* Enable auto negotiation. */
#define BMCR_SPEED100 (0x1 << 13) /* Select 100Mbps. */
#define BMCR_LOOPBACK (0x1 << 14) /* TXD loopback bits. */
#define BMCR_RESET (0x1 << 15) /* Reset. */
/* -------------- PHY_BMSR REGISTER BITS -------------- */
#define BMSR_ERCAP (0x1 << 0) /* Ext-reg capability. */
#define BMSR_JCD (0x1 << 1) /* Jabber detected. */
#define BMSR_LSTATUS (0x1 << 2) /* Link status. */
#define BMSR_ANEGCAPABLE (0x1 << 3) /* Able to do auto-negotiation. */
#define BMSR_RFAULT (0x1 << 4) /* Remote fault detected. */
#define BMSR_ANEGCOMPLETE (0x1 << 5) /* Auto-negotiation complete. */
#define BMSR_10HALF (0x1 << 11) /* Can do 10mbps, half-duplex. */
#define BMSR_10FULL (0x1 << 12) /* Can do 10mbps, full-duplex. */
#define BMSR_100HALF (0x1 << 13) /* Can do 100mbps, half-duplex. */
#define BMSR_100FULL (0x1 << 14) /* Can do 100mbps, full-duplex. */
#define BMSR_100BASE4 (0x1 << 15) /* Can do 100mbps, 4k packets. */
/* -------------- PHY_ANAR REGISTER BITS -------------- */
#define ANAR_SLCT 0x001Fu /* Selector bits. */
#define ANAR_CSMA DEF_BIT_04 /* Only selector supported. */
#define ANAR_10HALF DEF_BIT_05 /* Try for 10mbps half-duplex. */
#define ANAR_10FULL DEF_BIT_06 /* Try for 10mbps full-duplex. */
#define ANAR_100HALF DEF_BIT_07 /* Try for 100mbps half-duplex. */
#define ANAR_100FULL DEF_BIT_08 /* Try for 100mbps full-duplex. */
#define ANAR_100BASE4 DEF_BIT_09 /* Try for 100mbps 4k packets. */
#define ANAR_RFAULT DEF_BIT_13 /* Say we can detect faults. */
#define ANAR_LPACK DEF_BIT_14 /* Ack link partners response. */
#define ANAR_NPAGE DEF_BIT_15 /* Next page bit. */
#define ANAR_FULL (ANAR_100FULL | ANAR_10FULL | ANAR_CSMA)
#define ANAR_ALL (ANAR_100BASE4 | ANAR_100FULL | ANAR_10FULL | ANAR_100HALF | ANAR_10HALF)
/* ------------- PHY_ANLPAR REGISTER BITS ------------- */
#define ANLPAR_10HALF (0x1 << 5) /* Can do 10mbps half-duplex. */
#define ANLPAR_10FULL (0x1 << 6) /* Can do 10mbps full-duplex. */
#define ANLPAR_100HALF (0x1 << 7) /* Can do 100mbps half-duplex. */
#define ANLPAR_100FULL (0x1 << 8) /* Can do 100mbps full-duplex. */
#define ANLPAR_100BASE4 (0x1 << 9) /* Can do 100mbps 4k packets. */
#define ANLPAR_RFAULT (0x1 << 13) /* Link partner faulted. */
#define ANLPAR_LPACK (0x1 << 14) /* Link partner acked us. */
#define ANLPAR_NPAGE (0x1 << 15) /* Next page bit. */
#define ANLPAR_DUPLEX (ANLPAR_10FULL | ANLPAR_100FULL)
#define ANLPAR_100 (ANLPAR_100FULL | ANLPAR_100HALF | ANLPAR_100BASE4)
/* -------------- PHY_ANER REGISTER BITS -------------- */
#define ANER_NWAY (0x1 << 0) /* Can do N-way auto-negotiation. */
#define ANER_LCWP (0x1 << 1) /* Got new RX page code word. */
#define ANER_ENABLENPAGE (0x1 << 2) /* This enables npage words. */
#define ANER_NPCAPABLE (0x1 << 3) /* Link partner supports npage. */
#define ANER_MFAULTS (0x1 << 4) /* Multiple faults detected. */
#endif

120
features/nvstore/TESTS/nvstore/functionality/main.cpp
View File

@ -26,6 +26,7 @@
#include <stdlib.h>
#include <stdio.h>
#include <algorithm>
#include "mbed_stats.h"
#if !NVSTORE_ENABLED
#error [NOT_SUPPORTED] NVSTORE needs to be enabled for this test
@ -42,19 +43,19 @@ static const int thr_test_num_secs = 5;
static const int thr_test_max_data_size = 32;
static const int thr_test_num_threads = 3;
#ifdef TARGET_NRF52
static const int thr_test_stack_size = 1024;
#if defined(__CORTEX_M23) || defined(__CORTEX_M33)
static const int thr_test_min_stack_size = 1280;
static const int thr_test_max_stack_size = 1280;
#else
static const int thr_test_stack_size = 768;
static const int thr_test_min_stack_size = 768;
static const int thr_test_max_stack_size = 1024;
#endif
typedef struct {
uint8_t *buffs[max_test_keys][thr_test_num_buffs];
uint16_t sizes[max_test_keys][thr_test_num_buffs];
int inds[max_test_keys];
uint16_t max_keys;
uint16_t last_key;
int last_ind;
bool stop_threads;
} thread_test_data_t;
static thread_test_data_t *thr_test_data;
@ -62,6 +63,8 @@ static thread_test_data_t *thr_test_data;
static const int race_test_num_threads = 4;
static const int race_test_key = 1;
static const int race_test_data_size = 128;
static const int race_test_min_stack_size = 768;
static const int race_test_max_stack_size = 1024;
static void gen_random(uint8_t *s, int len)
{
@ -378,6 +381,41 @@ static void nvstore_basic_functionality_test()
delete[] nvstore_testing_buf_get;
}
// This function calculates the stack size that needs to be allocated per thread in
// the multi-thread tests. Given minimal and maximal stack sizes, and based on the heap
// stats (automatically enabled in CI), the function checks whether each thread has at least
// the minimal stack size, otherwise it reduces the number of threads (something that may happen
// on low memory boards).
static void calc_thread_stack_size(int &num_threads, uint32_t min_size, uint32_t max_size,
uint32_t &stack_size)
{
mbed_stats_heap_t heap_stats;
mbed_stats_heap_get(&heap_stats);
// reserved size (along with all other fields in heap stats) will be zero if
// app is compiled without heap stats (typically local builds)
if (!heap_stats.reserved_size) {
stack_size = max_size;
printf("Heap stats disabled in this build, so test may fail due to insufficient heap size\n");
printf("If this happens, please build the test with heap stats enabled (-DMBED_HEAP_STATS_ENABLED=1)\n");
return;
}
NVStore &nvstore = NVStore::get_instance();
int page_size = nvstore.size() / nvstore.get_max_possible_keys();
// Check if we can allocate enough stack size (per thread) for the current number of threads
while (num_threads) {
stack_size = (heap_stats.reserved_size - heap_stats.current_size) / num_threads - sizeof(rtos::Thread) - page_size;
stack_size = std::min(stack_size, max_size);
if (stack_size >= min_size) {
return;
}
// Got here - stack not sufficient per thread. Reduce number of threads
num_threads--;
}
}
static void thread_test_check_key(uint16_t key)
{
@ -386,7 +424,7 @@ static void thread_test_check_key(uint16_t key)
uint16_t actual_len_bytes;
NVStore &nvstore = NVStore::get_instance();
ret = nvstore.get(key, basic_func_max_data_size, get_buff, actual_len_bytes);
ret = nvstore.get(key, thr_test_max_data_size, get_buff, actual_len_bytes);
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
TEST_ASSERT_NOT_EQUAL(0, actual_len_bytes);
@ -400,13 +438,6 @@ static void thread_test_check_key(uint16_t key)
}
}
if (key == thr_test_data->last_key) {
if ((thr_test_data->sizes[key][thr_test_data->last_ind] == actual_len_bytes) &&
(!memcmp(thr_test_data->buffs[key][thr_test_data->last_ind], get_buff, actual_len_bytes))) {
return;
}
}
// Got here - always assert
TEST_ASSERT(0);
@ -420,17 +451,13 @@ static void thread_test_worker()
uint16_t key;
NVStore &nvstore = NVStore::get_instance();
for (;;) {
while (!thr_test_data->stop_threads) {
key = rand() % thr_test_data->max_keys;
is_set = rand() % 10;
if (is_set) {
buf_num = rand() % thr_test_num_buffs;
thr_test_data->last_key = key;
thr_test_data->last_ind = buf_num;
ret = nvstore.set(key, thr_test_data->sizes[key][buf_num], thr_test_data->buffs[key][buf_num]);
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
thr_test_data->inds[key] = buf_num;
} else {
thread_test_check_key(key);
}
@ -445,6 +472,7 @@ static void nvstore_multi_thread_test()
#ifdef MBED_CONF_RTOS_PRESENT
int i;
int num_threads = thr_test_num_threads;
uint32_t stack_size;
uint16_t size;
uint16_t key;
int ret;
@ -458,43 +486,51 @@ static void nvstore_multi_thread_test()
thr_test_data = new thread_test_data_t;
thr_test_data->max_keys = max_test_keys / 2;
thr_test_data->stop_threads = false;
for (key = 0; key < thr_test_data->max_keys; key++) {
for (i = 0; i < thr_test_num_buffs; i++) {
size = 1 + rand() % thr_test_max_data_size;
thr_test_data->sizes[key][i] = size;
thr_test_data->buffs[key][i] = new uint8_t[size + 1];
thr_test_data->inds[key] = 0;
gen_random(thr_test_data->buffs[key][i], size);
}
ret = nvstore.set(key, thr_test_data->sizes[key][0], thr_test_data->buffs[key][0]);
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
}
calc_thread_stack_size(num_threads, thr_test_min_stack_size, thr_test_max_stack_size, stack_size);
if (!num_threads) {
printf("Not enough heap space to run test. Test skipped\n");
goto end;
}
for (i = 0; i < num_threads; i++) {
threads[i] = new rtos::Thread((osPriority_t)((int)osPriorityBelowNormal-num_threads+i), thr_test_stack_size);
threads[i] = new rtos::Thread((osPriority_t)((int)osPriorityBelowNormal - num_threads + i), stack_size);
threads[i]->start(callback(thread_test_worker));
}
wait_ms(thr_test_num_secs * 1000);
thr_test_data->stop_threads = true;
wait_ms(1000);
for (i = 0; i < num_threads; i++) {
threads[i]->terminate();
delete threads[i];
}
delete[] threads;
wait_ms(1000);
ret = nvstore.deinit();
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
nvstore.deinit();
nvstore.init();
ret = nvstore.init();
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
for (key = 0; key < thr_test_data->max_keys; key++) {
thread_test_check_key(key);
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
}
end:
for (key = 0; key < thr_test_data->max_keys; key++) {
for (i = 0; i < thr_test_num_buffs; i++) {
delete[] thr_test_data->buffs[key][i];
@ -503,9 +539,12 @@ static void nvstore_multi_thread_test()
delete thr_test_data;
nvstore.reset();
#endif
}
static void race_test_worker(void *buf)
{
int ret;
@ -519,10 +558,12 @@ static void nvstore_race_test()
{
#ifdef MBED_CONF_RTOS_PRESENT
int i;
uint32_t stack_size;
uint16_t initial_buf_size;
int ret;
rtos::Thread *threads[race_test_num_threads];
uint8_t *get_buff, *buffs[race_test_num_threads];
int num_threads = race_test_num_threads;
uint16_t actual_len_bytes;
NVStore &nvstore = NVStore::get_instance();
@ -530,7 +571,7 @@ static void nvstore_race_test()
ret = nvstore.reset();
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
initial_buf_size = std::min((nvstore.size() - race_test_data_size) / 2, (size_t) 256);
initial_buf_size = std::min((nvstore.size() - race_test_data_size) / 2, (size_t) race_test_data_size);
uint8_t *initial_buf = new uint8_t[initial_buf_size];
int num_sets = (nvstore.size() - race_test_data_size) / initial_buf_size;
for (i = 0; i < num_sets; i++) {
@ -539,33 +580,42 @@ static void nvstore_race_test()
}
delete[] initial_buf;
for (i = 0; i < race_test_num_threads; i++) {
get_buff = new uint8_t[race_test_data_size];
calc_thread_stack_size(num_threads, race_test_min_stack_size, race_test_max_stack_size, stack_size);
if (!num_threads) {
printf("Not enough heap space to run test. Test skipped\n");
goto end;
}
for (i = 0; i < num_threads; i++) {
buffs[i] = new uint8_t[race_test_data_size];
gen_random(buffs[i], race_test_data_size);
}
for (i = 0; i < race_test_num_threads; i++) {
threads[i] = new rtos::Thread((osPriority_t)((int)osPriorityBelowNormal - race_test_num_threads + i), thr_test_stack_size);
for (i = 0; i < num_threads; i++) {
threads[i] = new rtos::Thread((osPriority_t)((int)osPriorityBelowNormal - num_threads + i), stack_size);
threads[i]->start(callback(race_test_worker, (void *) buffs[i]));
threads[i]->join();
}
get_buff = new uint8_t[race_test_data_size];
ret = nvstore.get(race_test_key, race_test_data_size, get_buff, actual_len_bytes);
TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret);
TEST_ASSERT_EQUAL(race_test_data_size, actual_len_bytes);
for (i = 0; i < race_test_num_threads; i++) {
for (i = 0; i < num_threads; i++) {
if (!memcmp(buffs[i], get_buff, actual_len_bytes)) {
break;
}
}
TEST_ASSERT_NOT_EQUAL(race_test_num_threads, i);
TEST_ASSERT_NOT_EQUAL(num_threads, i);
for (i = 0; i < race_test_num_threads; i++) {
for (i = 0; i < num_threads; i++) {
delete threads[i];
delete[] buffs[i];
}
end:
delete[] get_buff;
#endif
}

12
platform/mbed_error.c
View File

@ -57,7 +57,7 @@ static mbed_error_ctx first_error_ctx = {0};
static mbed_error_ctx last_error_ctx = {0};
static mbed_error_hook_t error_hook = NULL;
static void print_error_report(mbed_error_ctx *ctx, const char *);
static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number);
static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller);
//Helper function to halt the system
static void mbed_halt_system(void)
@ -82,7 +82,7 @@ WEAK void error(const char *format, ...)
}
//Call handle_error/print_error_report permanently setting error_in_progress flag
handle_error(MBED_ERROR_UNKNOWN, 0, NULL, 0);
handle_error(MBED_ERROR_UNKNOWN, 0, NULL, 0, MBED_CALLER_ADDR());
ERROR_REPORT(&last_error_ctx, "Fatal Run-time error");
error_in_progress = 1;
@ -96,7 +96,7 @@ WEAK void error(const char *format, ...)
}
//Set an error status with the error handling system
static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number)
static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller)
{
mbed_error_ctx current_error_ctx;
@ -123,7 +123,7 @@ static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsign
memset(&current_error_ctx, sizeof(mbed_error_ctx), 0);
//Capture error information
current_error_ctx.error_status = error_status;
current_error_ctx.error_address = (uint32_t)MBED_CALLER_ADDR();
current_error_ctx.error_address = (uint32_t)caller;
current_error_ctx.error_value = error_value;
#ifdef MBED_CONF_RTOS_PRESENT
//Capture thread info
@ -193,14 +193,14 @@ int mbed_get_error_count(void)
//Sets a fatal error
mbed_error_status_t mbed_warning(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number)
{
return handle_error(error_status, error_value, filename, line_number);
return handle_error(error_status, error_value, filename, line_number, MBED_CALLER_ADDR());
}
//Sets a fatal error, this function is marked WEAK to be able to override this for some tests
WEAK mbed_error_status_t mbed_error(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number)
{
//set the error reported and then halt the system
if (MBED_SUCCESS != handle_error(error_status, error_value, filename, line_number)) {
if (MBED_SUCCESS != handle_error(error_status, error_value, filename, line_number, MBED_CALLER_ADDR())) {
return MBED_ERROR_FAILED_OPERATION;
}

4
platform/mbed_retarget.cpp
View File

@ -1196,12 +1196,10 @@ extern "C" uint32_t __HeapLimit;
extern "C" int errno;
// Dynamic memory allocation related syscall.
#if (defined(TARGET_NUVOTON) || defined(TWO_RAM_REGIONS))
#if defined(TWO_RAM_REGIONS)
// Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
// __wrap__sbrk() is implemented in:
// TARGET_NUMAKER_PFM_NUC472 targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/nuc472_retarget.c
// TARGET_NUMAKER_PFM_M453 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/m451_retarget.c
// TARGET_STM32L4 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4/l4_retarget.c
extern "C" void *__wrap__sbrk(int incr);
extern "C" caddr_t _sbrk(int incr)

2
platform/mbed_version.h
View File

@ -43,7 +43,7 @@
*
* @note 99 is default value for development version (master branch)
*/
#define MBED_PATCH_VERSION 3
#define MBED_PATCH_VERSION 4
#define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))

7
platform/mbed_wait_api_rtos.cpp
View File

@ -39,11 +39,10 @@ void wait_us(int us)
const ticker_data_t *const ticker = get_us_ticker_data();
uint32_t start = ticker_read(ticker);
// Use the RTOS to wait for millisecond delays if possible
int ms = us / 1000;
if ((ms > 0) && core_util_are_interrupts_enabled()) {
if ((us >= 1000) && core_util_are_interrupts_enabled()) {
// Use the RTOS to wait for millisecond delays if possible
sleep_manager_lock_deep_sleep();
Thread::wait((uint32_t)ms);
Thread::wait((uint32_t)us / 1000);
sleep_manager_unlock_deep_sleep();
}
// Use busy waiting for sub-millisecond delays, or for the whole

2
rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c
View File

@ -66,7 +66,7 @@ void mbed_fault_handler (uint32_t fault_type, void *mbed_fault_context_in, void
mbed_error_printf("\n\n-- MbedOS Fault Handler --\n\n");
//Now call mbed_error, to log the error and halt the system
mbed_error( faultStatus, "Unrecoverable fault excaption.", mbed_fault_context.PC_reg, NULL, 0 );
mbed_error( faultStatus, "Fault exception", mbed_fault_context.PC_reg, NULL, 0 );
}

6
rtos/TARGET_CORTEX/mbed_boot.c
View File

@ -321,6 +321,12 @@ void mbed_start_main(void)
_main_thread_attr.cb_mem = &_main_obj;
_main_thread_attr.priority = osPriorityNormal;
_main_thread_attr.name = "main_thread";
/* Allow non-secure main thread to call secure functions */
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1U)
_main_thread_attr.tz_module = 1U;
#endif
osThreadId_t result = osThreadNew((osThreadFunc_t)pre_main, NULL, &_main_thread_attr);
if ((void *)result == NULL) {
MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_INITIALIZATION_FAILED), "Pre main thread not created", &_main_thread_attr);

103
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/flash_api.c Normal file
View File

@ -0,0 +1,103 @@
/*
* Copyright (c) 2017-2018 ARM Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device.h"
#include "flash_api.h"
#include "memory_zones.h"
/* Fast Model FVP MPS2 is modeling after V2M-MPS2 platform with a FPGA (AN385).
* The implementation emulates flash over SRAM.
*/
#define FLASH_PAGE_SIZE 256
#define FLASH_OFS_START FLASH_START
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_OFS_END (FLASH_OFS_START + FLASH_SIZE)
int32_t flash_init(flash_t *obj)
{
(void)obj;
return 0;
}
int32_t flash_free(flash_t *obj)
{
(void)obj;
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
(void)obj;
memset((void *)address, 0xff, FLASH_SECTOR_SIZE);
return 0;
}
int32_t flash_read(flash_t *obj, uint32_t address,
uint8_t *data, uint32_t size)
{
(void)obj;
memcpy(data, (void *)address, size);
return 0;
}
int32_t flash_program_page(flash_t *obj, uint32_t address,
const uint8_t *data, uint32_t size)
{
(void)obj;
memcpy((void *)address, data, size);
return 0;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
(void)obj;
if (address < FLASH_OFS_START || address >= FLASH_OFS_END) {
return MBED_FLASH_INVALID_SIZE;
}
return FLASH_SECTOR_SIZE;
}
uint32_t flash_get_page_size(const flash_t *obj)
{
(void)obj;
return FLASH_PAGE_SIZE;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
(void)obj;
return FLASH_OFS_START;
}
uint32_t flash_get_size(const flash_t *obj)
{
(void)obj;
return FLASH_SIZE;
}

50
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/memory_zones.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (c) 2017-2018 ARM Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file contains the information of memory zones for code and data on
* ARM Versatile Express Cortex-M Prototyping Systems (V2M-MPS2) TRM.
* It is used in startup code and linker scripts of supported compilers (ARM and
* GCC_ARM).
*
* WARNING: IAR does not include this file and re-define these values in
* MPS2.icf file. Please make sure that the two files share the same values.
*
* These memory zones are defined in section 4.2 of ARM V2M-MPS2 RTL and
* Fast Model Reference Guide.
*/
#ifndef MEMORY_ZONES_H
#define MEMORY_ZONES_H
/*
* Code memory zones
* Please note that MPS2 on Fast Models do not simulate persistent flash memory.
* The FLASH memory zone is a 256 KiB SRAM block and named FLASH
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide.
*/
#define FLASH_START 0x00000000
#define FLASH_SIZE 0x00040000 /* 256 KiB */
#define ZBT_SRAM1_START 0x00400000
#define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
/* Data memory zones */
#define ZBT_SRAM2_START 0x20000000
#define ZBT_SRAM2_SIZE 0x00800000 /* 8 MiB */
#endif /* MEMORY_ZONES_H */

5
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h
View File

@ -73,6 +73,11 @@ struct analogin_s {
__IO uint32_t address;
};
/* This structure is not used by the HAL implementation. */
struct flash_s {
uint8_t not_used;
};
#include "gpio_object.h"
#ifdef __cplusplus

4
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/nRF52832.icf
View File

@ -16,8 +16,8 @@ if (MBED_APP_START == 0) {
define symbol MBED_RAM_START = 0x20000000;
define symbol MBED_RAM_SIZE = 0x10000;
} else {
define symbol MBED_RAM_START = 0x20003188;
define symbol MBED_RAM_SIZE = 0x3CE78;
define symbol MBED_RAM_START = 0x200031D0;
define symbol MBED_RAM_SIZE = 0xCE30;
}
define symbol MBED_RAM0_START = MBED_RAM_START;

43
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c
View File

@ -62,15 +62,15 @@ void SystemInit(void)
{
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO)
#if defined (ENABLE_SWO)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
#if defined (ENABLE_TRACE)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
@ -78,7 +78,7 @@ void SystemInit(void)
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#endif
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
@ -166,16 +166,16 @@ void SystemInit(void)
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
#endif
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@ -185,12 +185,12 @@ void SystemInit(void)
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
@ -203,7 +203,7 @@ void SystemInit(void)
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
#endif
SystemCoreClockUpdate();
@ -216,6 +216,29 @@ void SystemInit(void)
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
// Do nothing.
}
/**
* Mbed HAL specific code section.
*
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
*/
#if defined (DEVICE_ITM)
/* Enable SWO trace functionality */
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
/* set SWO clock speed to 4 MHz */
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
/* set SWO pin */
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
/* set prescaler */
TPI->ACPR = 0;
#endif
}

46
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c
View File

@ -59,15 +59,15 @@ void SystemInit(void)
{
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO)
#if defined (ENABLE_SWO)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
#if defined (ENABLE_TRACE)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
@ -75,8 +75,8 @@ void SystemInit(void)
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#endif
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_36()){
@ -142,16 +142,16 @@ void SystemInit(void)
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
#endif
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@ -161,12 +161,12 @@ void SystemInit(void)
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
@ -179,7 +179,7 @@ void SystemInit(void)
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
#endif
SystemCoreClockUpdate();
@ -192,6 +192,30 @@ void SystemInit(void)
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
// Do nothing.
}
/**
* Mbed HAL specific code section.
*
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
*/
#if defined (DEVICE_ITM)
/* Enable SWO trace functionality */
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
/* set SWO clock speed to 4 MHz */
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
/* set SWO pin */
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
/* set prescaler */
TPI->ACPR = 0;
#endif
}

22
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/itm_api.c
View File

@ -18,27 +18,11 @@
#include "hal/itm_api.h"
#include "nrf.h"
#include "nrf5x_lf_clk_helper.h"
/* SWO frequency: 4000 kHz */
void itm_init(void)
{
/* Enable SWO trace functionality */
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
/* set SWO clock speed to 4 MHz */
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
/* set SWO pin */
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
/* set prescaler */
TPI->ACPR = 0;
/**
* Initialization moved to system_nrf52840.c due to SoftDevice incompatibility.
*/
}
#endif

325
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/PeripheralNames.h Normal file
View File

@ -0,0 +1,325 @@
/* mbed Microcontroller Library
* Copyright (c) 2015-2016 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "partition_M2351.h"
#ifdef __cplusplus
extern "C" {
#endif
// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name
// which encodes module base address and module index/subindex.
#define NU_MODSUBINDEX_Pos 0
#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos)
#define NU_MODINDEX_Pos 20
#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos)
#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos))
#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk))
#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos)
#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos)
#if 0
typedef enum {
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 0))
GPIO_A = (int) NU_MODNAME(GPIOA_BASE + NS_OFFSET, 0, 0),
#else
GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 1))
GPIO_B = (int) NU_MODNAME(GPIOB_BASE + NS_OFFSET, 1, 0),
#else
GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 2))
GPIO_C = (int) NU_MODNAME(GPIOC_BASE + NS_OFFSET, 2, 0),
#else
GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 3))
GPIO_D = (int) NU_MODNAME(GPIOD_BASE + NS_OFFSET, 3, 0),
#else
GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 4))
GPIO_E = (int) NU_MODNAME(GPIOE_BASE + NS_OFFSET, 4, 0),
#else
GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 5))
GPIO_F = (int) NU_MODNAME(GPIOF_BASE + NS_OFFSET, 5, 0),
#else
GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 6))
GPIO_G = (int) NU_MODNAME(GPIOF_BASE + NS_OFFSET, 6, 0)
#else
GPIO_G = (int) NU_MODNAME(GPIOF_BASE, 6, 0)
#endif
} GPIOName;
#endif
typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 3))
ADC_0_0 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 7),
ADC_0_8 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 8),
ADC_0_9 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 9),
ADC_0_10 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 10),
ADC_0_11 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 11),
ADC_0_12 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 12),
ADC_0_13 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 13),
ADC_0_14 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 14),
ADC_0_15 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 15)
#else
ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 0, 7),
ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 0, 8),
ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 0, 9),
ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 0, 10),
ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 0, 11),
ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 0, 12),
ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 0, 13),
ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 0, 14),
ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15)
#endif
} ADCName;
typedef enum {
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1<<16))
UART_0 = (int) NU_MODNAME(UART0_BASE + NS_OFFSET, 0, 0),
#else
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1<<17))
UART_1 = (int) NU_MODNAME(UART1_BASE + NS_OFFSET, 1, 0),
#else
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1<<18))
UART_2 = (int) NU_MODNAME(UART2_BASE + NS_OFFSET, 2, 0),
#else
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<19))
UART_3 = (int) NU_MODNAME(UART3_BASE + NS_OFFSET, 3, 0),
#else
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<20))
UART_4 = (int) NU_MODNAME(UART4_BASE + NS_OFFSET, 4, 0),
#else
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<21))
UART_5 = (int) NU_MODNAME(UART5_BASE + NS_OFFSET, 5, 0),
#else
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
#endif
// NOTE: board-specific
STDIO_UART = UART_3
} UARTName;
typedef enum {
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 0))
SPI_0 = (int) NU_MODNAME(SPI0_BASE + NS_OFFSET, 0, 0),
#else
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 1))
SPI_1 = (int) NU_MODNAME(SPI1_BASE + NS_OFFSET, 1, 0),
#else
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 2))
SPI_2 = (int) NU_MODNAME(SPI2_BASE + NS_OFFSET, 2, 0),
#else
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 3))
SPI_3 = (int) NU_MODNAME(SPI3_BASE + NS_OFFSET, 3, 0),
#else
SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 5))
SPI_5 = (int) NU_MODNAME(SPI5_BASE + NS_OFFSET, 5, 0)
#else
SPI_5 = (int) NU_MODNAME(SPI5_BASE, 5, 0)
#endif
} SPIName;
typedef enum {
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 0))
I2C_0 = (int) NU_MODNAME(I2C0_BASE + NS_OFFSET, 0, 0),
#else
I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0),
#endif
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 1))
I2C_1 = (int) NU_MODNAME(I2C1_BASE + NS_OFFSET, 1, 0),
#else
I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0),
#endif
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 2))
I2C_2 = (int) NU_MODNAME(I2C2_BASE + NS_OFFSET, 2, 0)
#else
I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0)
#endif
} I2CName;
typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 24))
PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 0),
PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 1),
PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 2),
PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 3),
PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 4),
PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 5),
#else
PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE, 0, 0),
PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE, 0, 1),
PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE, 0, 2),
PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE, 0, 3),
PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE, 0, 4),
PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE, 0, 5),
#endif
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 25))
PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 0),
PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 1),
PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 2),
PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 3),
PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 4),
PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 5),
#else
PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE, 1, 0),
PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE, 1, 1),
PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE, 1, 2),
PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE, 1, 3),
PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE, 1, 4),
PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE, 1, 5),
#endif
} PWMName;
typedef enum {
/* TMR0/1 are hard-wired to Secure mode */
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0),
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 17))
TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0),
#else
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x100, 3, 0),
#endif
} TIMERName;
typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 1))
RTC_0 = (int) NU_MODNAME(RTC_BASE + NS_OFFSET, 0, 0)
#else
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0)
#endif
} RTCName;
typedef enum {
/* PDMA0 is hard-wired to Secure mode. */
DMA_0 = (int) NU_MODNAME(PDMA0_BASE, 0, 0),
#if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 24))
DMA_1 = (int) NU_MODNAME(PDMA1_BASE + NS_OFFSET, 1, 0)
#else
DMA_1 = (int) NU_MODNAME(PDMA1_BASE, 1, 0)
#endif
} DMAName;
typedef enum {
#if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 13))
SD_0 = (int) NU_MODNAME(SDH0_BASE + NS_OFFSET, 0, 0)
#else
SD_0 = (int) NU_MODNAME(SDH0_BASE, 0, 0)
#endif
} SDName;
typedef enum {
#if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 0))
CAN_0 = (int) NU_MODNAME(CAN0_BASE + NS_OFFSET, 0, 0)
#else
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0)
#endif
} CANName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/PeripheralPins.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2017-2018 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
// =====
// Note: Commented lines are alternative possibilities which are not used per default.
// If you change them, you will have also to modify the corresponding xxx_api.c file
// for pwmout, analogin, analogout, ...
// =====
#if 0
//*** GPIO ***
const PinMap PinMap_GPIO[] = {
// GPIO A MFP
{PA_0, GPIO_A, SYS_GPA_MFPL_PA0MFP_GPIO},
{PA_1, GPIO_A, SYS_GPA_MFPL_PA1MFP_GPIO},
{PA_2, GPIO_A, SYS_GPA_MFPL_PA2MFP_GPIO},
{PA_3, GPIO_A, SYS_GPA_MFPL_PA3MFP_GPIO},
{PA_4, GPIO_A, SYS_GPA_MFPL_PA4MFP_GPIO},
{PA_5, GPIO_A, SYS_GPA_MFPL_PA5MFP_GPIO},
{PA_6, GPIO_A, SYS_GPA_MFPL_PA6MFP_GPIO},
{PA_7, GPIO_A, SYS_GPA_MFPL_PA7MFP_GPIO},
{PA_8, GPIO_A, SYS_GPA_MFPH_PA8MFP_GPIO},
{PA_9, GPIO_A, SYS_GPA_MFPH_PA9MFP_GPIO},
{PA_10, GPIO_A, SYS_GPA_MFPH_PA10MFP_GPIO},
{PA_11, GPIO_A, SYS_GPA_MFPH_PA11MFP_GPIO},
{PA_12, GPIO_A, SYS_GPA_MFPH_PA12MFP_GPIO},
{PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO},
{PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO},
{PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO},
// GPIO B MFP
{PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO},
{PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO},
{PB_2, GPIO_B, SYS_GPB_MFPL_PB2MFP_GPIO},
{PB_3, GPIO_B, SYS_GPB_MFPL_PB3MFP_GPIO},
{PB_4, GPIO_B, SYS_GPB_MFPL_PB4MFP_GPIO},
{PB_5, GPIO_B, SYS_GPB_MFPL_PB5MFP_GPIO},
{PB_6, GPIO_B, SYS_GPB_MFPL_PB6MFP_GPIO},
{PB_7, GPIO_B, SYS_GPB_MFPL_PB7MFP_GPIO},
{PB_8, GPIO_B, SYS_GPB_MFPH_PB8MFP_GPIO},
{PB_9, GPIO_B, SYS_GPB_MFPH_PB9MFP_GPIO},
{PB_10, GPIO_B, SYS_GPB_MFPH_PB10MFP_GPIO},
{PB_11, GPIO_B, SYS_GPB_MFPH_PB11MFP_GPIO},
{PB_12, GPIO_B, SYS_GPB_MFPH_PB12MFP_GPIO},
{PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO},
{PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO},
{PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO},
// GPIO C MFP
{PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO},
{PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO},
{PC_2, GPIO_C, SYS_GPC_MFPL_PC2MFP_GPIO},
{PC_3, GPIO_C, SYS_GPC_MFPL_PC3MFP_GPIO},
{PC_4, GPIO_C, SYS_GPC_MFPL_PC4MFP_GPIO},
{PC_5, GPIO_C, SYS_GPC_MFPL_PC5MFP_GPIO},
{PC_6, GPIO_C, SYS_GPC_MFPL_PC6MFP_GPIO},
{PC_7, GPIO_C, SYS_GPC_MFPL_PC7MFP_GPIO},
{PC_8, GPIO_C, SYS_GPC_MFPH_PC8MFP_GPIO},
{PC_9, GPIO_C, SYS_GPC_MFPH_PC9MFP_GPIO},
{PC_10, GPIO_C, SYS_GPC_MFPH_PC10MFP_GPIO},
{PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO},
{PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO},
{PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO},
// GPIO D MFP
{PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO},
{PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO},
{PD_2, GPIO_D, SYS_GPD_MFPL_PD2MFP_GPIO},
{PD_3, GPIO_D, SYS_GPD_MFPL_PD3MFP_GPIO},
{PD_4, GPIO_D, SYS_GPD_MFPL_PD4MFP_GPIO},
{PD_5, GPIO_D, SYS_GPD_MFPL_PD5MFP_GPIO},
{PD_6, GPIO_D, SYS_GPD_MFPL_PD6MFP_GPIO},
{PD_7, GPIO_D, SYS_GPD_MFPL_PD7MFP_GPIO},
{PD_8, GPIO_D, SYS_GPD_MFPH_PD8MFP_GPIO},
{PD_9, GPIO_D, SYS_GPD_MFPH_PD9MFP_GPIO},
{PD_10, GPIO_D, SYS_GPD_MFPH_PD10MFP_GPIO},
{PD_11, GPIO_D, SYS_GPD_MFPH_PD11MFP_GPIO},
{PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO},
{PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO},
{PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO},
// GPIO E MFP
{PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO},
{PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO},
{PE_2, GPIO_E, SYS_GPE_MFPL_PE2MFP_GPIO},
{PE_3, GPIO_E, SYS_GPE_MFPL_PE3MFP_GPIO},
{PE_4, GPIO_E, SYS_GPE_MFPL_PE4MFP_GPIO},
{PE_5, GPIO_E, SYS_GPE_MFPL_PE5MFP_GPIO},
{PE_6, GPIO_E, SYS_GPE_MFPL_PE6MFP_GPIO},
{PE_7, GPIO_E, SYS_GPE_MFPL_PE7MFP_GPIO},
{PE_8, GPIO_E, SYS_GPE_MFPH_PE8MFP_GPIO},
{PE_9, GPIO_E, SYS_GPE_MFPH_PE9MFP_GPIO},
{PE_10, GPIO_E, SYS_GPE_MFPH_PE10MFP_GPIO},
{PE_11, GPIO_E, SYS_GPE_MFPH_PE11MFP_GPIO},
{PE_12, GPIO_E, SYS_GPE_MFPH_PE12MFP_GPIO},
{PE_13, GPIO_E, SYS_GPE_MFPH_PE13MFP_GPIO},
{PE_14, GPIO_E, SYS_GPE_MFPH_PE14MFP_GPIO},
{PE_15, GPIO_E, SYS_GPE_MFPH_PE15MFP_GPIO},
// GPIO F MFP
{PF_0, GPIO_F, SYS_GPF_MFPL_PF0MFP_GPIO},
{PF_1, GPIO_F, SYS_GPF_MFPL_PF1MFP_GPIO},
{PF_2, GPIO_F, SYS_GPF_MFPL_PF2MFP_GPIO},
{PF_3, GPIO_F, SYS_GPF_MFPL_PF3MFP_GPIO},
{PF_4, GPIO_F, SYS_GPF_MFPL_PF4MFP_GPIO},
{PF_5, GPIO_F, SYS_GPF_MFPL_PF5MFP_GPIO},
{PF_6, GPIO_F, SYS_GPF_MFPL_PF6MFP_GPIO},
{PF_7, GPIO_F, SYS_GPF_MFPL_PF7MFP_GPIO},
{PF_8, GPIO_F, SYS_GPF_MFPH_PF8MFP_GPIO},
{PF_9, GPIO_F, SYS_GPF_MFPH_PF9MFP_GPIO},
{PF_10, GPIO_F, SYS_GPF_MFPH_PF10MFP_GPIO},
{PF_11, GPIO_F, SYS_GPF_MFPH_PF11MFP_GPIO},
// GPIO G/H MFP
{PG_2, GPIO_G, SYS_GPG_MFPL_PG2MFP_GPIO},
{PG_3, GPIO_G, SYS_GPG_MFPL_PG3MFP_GPIO},
{PG_4, GPIO_G, SYS_GPG_MFPL_PG4MFP_GPIO},
{PG_9, GPIO_G, SYS_GPG_MFPH_PG9MFP_GPIO},
{PG_10, GPIO_G, SYS_GPG_MFPH_PG10MFP_GPIO},
{PG_11, GPIO_G, SYS_GPG_MFPH_PG11MFP_GPIO},
{PG_12, GPIO_G, SYS_GPG_MFPH_PG12MFP_GPIO},
{PG_13, GPIO_G, SYS_GPG_MFPH_PG13MFP_GPIO},
{PG_14, GPIO_G, SYS_GPG_MFPH_PG14MFP_GPIO},
{PG_15, GPIO_G, SYS_GPG_MFPH_PG15MFP_GPIO},
{PH_4, GPIO_H, SYS_GPH_MFPL_PH4MFP_GPIO},
{PH_5, GPIO_H, SYS_GPH_MFPL_PH5MFP_GPIO},
{PH_6, GPIO_H, SYS_GPH_MFPL_PH6MFP_GPIO},
{PH_7, GPIO_H, SYS_GPH_MFPL_PH7MFP_GPIO},
{PH_8, GPIO_H, SYS_GPH_MFPH_PH8MFP_GPIO},
{PH_9, GPIO_H, SYS_GPH_MFPH_PH9MFP_GPIO},
{PH_10, GPIO_H, SYS_GPH_MFPH_PH10MFP_GPIO},
{PH_11, GPIO_H, SYS_GPH_MFPH_PH11MFP_GPIO},
{NC, NC, 0}
};
#endif
//*** ADC ***
const PinMap PinMap_ADC[] = {
{PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC0_CH0},
{PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC0_CH1},
{PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC0_CH2},
{PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC0_CH3},
{PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC0_CH4},
{PB_5, ADC_0_5, SYS_GPB_MFPL_PB5MFP_EADC0_CH5},
{PB_6, ADC_0_6, SYS_GPB_MFPL_PB6MFP_EADC0_CH6},
{PB_7, ADC_0_7, SYS_GPB_MFPL_PB7MFP_EADC0_CH7},
{PB_8, ADC_0_8, SYS_GPB_MFPH_PB8MFP_EADC0_CH8},
{PB_9, ADC_0_9, SYS_GPB_MFPH_PB9MFP_EADC0_CH9},
{PB_10, ADC_0_10, SYS_GPB_MFPH_PB10MFP_EADC0_CH10},
{PB_11, ADC_0_11, SYS_GPB_MFPH_PB11MFP_EADC0_CH11},
{PB_12, ADC_0_12, SYS_GPB_MFPH_PB12MFP_EADC0_CH12},
{PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13},
{PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14},
{PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15},
{NC, NC, 0}
};
//*** I2C ***
const PinMap PinMap_I2C_SDA[] = {
{PA_0, I2C_2, SYS_GPA_MFPL_PA0MFP_I2C2_SDA},
{PA_2, I2C_1, SYS_GPA_MFPL_PA2MFP_I2C1_SDA},
{PA_4, I2C_0, SYS_GPA_MFPL_PA4MFP_I2C0_SDA},
{PA_6, I2C_1, SYS_GPA_MFPL_PA6MFP_I2C1_SDA},
{PA_10, I2C_2, SYS_GPA_MFPH_PA10MFP_I2C2_SDA},
{PA_13, I2C_1, SYS_GPA_MFPH_PA13MFP_I2C1_SDA},
{PA_15, I2C_2, SYS_GPA_MFPH_PA15MFP_I2C2_SDA},
{PB_0, I2C_1, SYS_GPB_MFPL_PB0MFP_I2C1_SDA},
{PB_4, I2C_0, SYS_GPB_MFPL_PB4MFP_I2C0_SDA},
{PB_10, I2C_1, SYS_GPB_MFPH_PB10MFP_I2C1_SDA},
{PB_12, I2C_2, SYS_GPB_MFPH_PB12MFP_I2C2_SDA},
{PC_0, I2C_0, SYS_GPC_MFPL_PC0MFP_I2C0_SDA},
{PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SDA},
{PC_8, I2C_0, SYS_GPC_MFPH_PC8MFP_I2C0_SDA},
{PC_11, I2C_0, SYS_GPC_MFPH_PC11MFP_I2C0_SDA},
{PD_0, I2C_2, SYS_GPD_MFPL_PD0MFP_I2C2_SDA},
{PD_4, I2C_1, SYS_GPD_MFPL_PD4MFP_I2C1_SDA},
{PD_6, I2C_0, SYS_GPD_MFPL_PD6MFP_I2C0_SDA},
{PD_8, I2C_2, SYS_GPD_MFPH_PD8MFP_I2C2_SDA},
{PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA},
{PF_1, I2C_1, SYS_GPF_MFPL_PF1MFP_I2C1_SDA},
{PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA},
{PG_3, I2C_1, SYS_GPG_MFPL_PG3MFP_I2C1_SDA},
{PH_9, I2C_2, SYS_GPH_MFPH_PH9MFP_I2C2_SDA},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PA_1, I2C_2, SYS_GPA_MFPL_PA1MFP_I2C2_SCL},
{PA_3, I2C_1, SYS_GPA_MFPL_PA3MFP_I2C1_SCL},
{PA_5, I2C_0, SYS_GPA_MFPL_PA5MFP_I2C0_SCL},
{PA_7, I2C_1, SYS_GPA_MFPL_PA7MFP_I2C1_SCL},
{PA_11, I2C_2, SYS_GPA_MFPH_PA11MFP_I2C2_SCL},
{PA_12, I2C_1, SYS_GPA_MFPH_PA12MFP_I2C1_SCL},
{PA_14, I2C_2, SYS_GPA_MFPH_PA14MFP_I2C2_SCL},
{PB_1, I2C_1, SYS_GPB_MFPL_PB1MFP_I2C1_SCL},
{PB_5, I2C_0, SYS_GPB_MFPL_PB5MFP_I2C0_SCL},
{PB_11, I2C_1, SYS_GPB_MFPH_PB11MFP_I2C1_SCL},
{PB_13, I2C_2, SYS_GPB_MFPH_PB13MFP_I2C2_SCL},
{PC_1, I2C_0, SYS_GPC_MFPL_PC1MFP_I2C0_SCL},
{PC_5, I2C_1, SYS_GPC_MFPL_PC5MFP_I2C1_SCL},
{PC_12, I2C_0, SYS_GPC_MFPH_PC12MFP_I2C0_SCL},
{PD_1, I2C_2, SYS_GPD_MFPL_PD1MFP_I2C2_SCL},
{PD_5, I2C_1, SYS_GPD_MFPL_PD5MFP_I2C1_SCL},
{PD_7, I2C_0, SYS_GPD_MFPL_PD7MFP_I2C0_SCL},
{PD_9, I2C_2, SYS_GPD_MFPH_PD9MFP_I2C2_SCL},
{PE_1, I2C_1, SYS_GPE_MFPL_PE1MFP_I2C1_SCL},
{PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SCL},
{PF_0, I2C_1, SYS_GPF_MFPL_PF0MFP_I2C1_SCL},
{PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL},
{PG_2, I2C_1, SYS_GPG_MFPL_PG2MFP_I2C1_SCL},
{PH_8, I2C_2, SYS_GPH_MFPH_PH8MFP_I2C2_SCL},
{NC, NC, 0}
};
//*** PWM ***
const PinMap PinMap_PWM[] = {
{PA_0, PWM_0_5, SYS_GPA_MFPL_PA0MFP_EPWM0_CH5},
{PA_1, PWM_0_4, SYS_GPA_MFPL_PA1MFP_EPWM0_CH4},
{PA_2, PWM_0_3, SYS_GPA_MFPL_PA2MFP_EPWM0_CH3},
{PA_3, PWM_0_2, SYS_GPA_MFPL_PA3MFP_EPWM0_CH2},
{PA_4, PWM_0_1, SYS_GPA_MFPL_PA4MFP_EPWM0_CH1},
{PA_5, PWM_0_0, SYS_GPA_MFPL_PA5MFP_EPWM0_CH0},
{PA_6, PWM_1_5, SYS_GPA_MFPL_PA6MFP_EPWM1_CH5},
{PA_7, PWM_1_4, SYS_GPA_MFPL_PA7MFP_EPWM1_CH4},
{PB_0, PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5},
{NU_PINNAME_BIND(PB_0, PWM_0_5), PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5},
{PB_0, PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5},
{NU_PINNAME_BIND(PB_0, PWM_1_5), PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5},
{PB_1, PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4},
{NU_PINNAME_BIND(PB_1, PWM_0_4), PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4},
{PB_1, PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4},
{NU_PINNAME_BIND(PB_1, PWM_1_4), PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4},
{PB_2, PWM_0_3, SYS_GPB_MFPL_PB2MFP_EPWM0_CH3},
{PB_3, PWM_0_2, SYS_GPB_MFPL_PB3MFP_EPWM0_CH2},
{PB_4, PWM_0_1, SYS_GPB_MFPL_PB4MFP_EPWM0_CH1},
{PB_5, PWM_0_0, SYS_GPB_MFPL_PB5MFP_EPWM0_CH0},
{PB_6, PWM_1_5, SYS_GPB_MFPL_PB6MFP_EPWM1_CH5},
{PB_7, PWM_1_4, SYS_GPB_MFPL_PB7MFP_EPWM1_CH4},
{PB_12, PWM_1_3, SYS_GPB_MFPH_PB12MFP_EPWM1_CH3},
{PB_13, PWM_1_2, SYS_GPB_MFPH_PB13MFP_EPWM1_CH2},
{PB_14, PWM_1_1, SYS_GPB_MFPH_PB14MFP_EPWM1_CH1},
{PB_15, PWM_1_0, SYS_GPB_MFPH_PB15MFP_EPWM1_CH0},
{PC_0, PWM_1_5, SYS_GPC_MFPL_PC0MFP_EPWM1_CH5},
{PC_1, PWM_1_4, SYS_GPC_MFPL_PC1MFP_EPWM1_CH4},
{PC_2, PWM_1_3, SYS_GPC_MFPL_PC2MFP_EPWM1_CH3},
{PC_3, PWM_1_2, SYS_GPC_MFPL_PC3MFP_EPWM1_CH2},
{PC_4, PWM_1_1, SYS_GPC_MFPL_PC4MFP_EPWM1_CH1},
{PC_5, PWM_1_0, SYS_GPC_MFPL_PC5MFP_EPWM1_CH0},
{PC_6, PWM_1_3, SYS_GPC_MFPL_PC6MFP_EPWM1_CH3},
{PC_7, PWM_1_2, SYS_GPC_MFPL_PC7MFP_EPWM1_CH2},
{PC_8, PWM_1_1, SYS_GPC_MFPH_PC8MFP_EPWM1_CH1},
{PC_9, PWM_1_3, SYS_GPC_MFPH_PC9MFP_EPWM1_CH3},
{PC_10, PWM_1_2, SYS_GPC_MFPH_PC10MFP_EPWM1_CH2},
{PC_11, PWM_1_1, SYS_GPC_MFPH_PC11MFP_EPWM1_CH1},
{PC_12, PWM_1_0, SYS_GPC_MFPH_PC12MFP_EPWM1_CH0},
{PD_14, PWM_0_4, SYS_GPD_MFPH_PD14MFP_EPWM0_CH4},
{PE_2, PWM_0_5, SYS_GPE_MFPL_PE2MFP_EPWM0_CH5},
{PE_3, PWM_0_4, SYS_GPE_MFPL_PE3MFP_EPWM0_CH4},
{PE_4, PWM_0_3, SYS_GPE_MFPL_PE4MFP_EPWM0_CH3},
{PE_5, PWM_0_2, SYS_GPE_MFPL_PE5MFP_EPWM0_CH2},
{PE_6, PWM_0_1, SYS_GPE_MFPL_PE6MFP_EPWM0_CH1},
{PE_7, PWM_0_0, SYS_GPE_MFPL_PE7MFP_EPWM0_CH0},
{PE_8, PWM_0_0, SYS_GPE_MFPH_PE8MFP_EPWM0_CH0},
{PE_9, PWM_0_1, SYS_GPE_MFPH_PE9MFP_EPWM0_CH1},
{PE_10, PWM_0_2, SYS_GPE_MFPH_PE10MFP_EPWM0_CH2},
{PE_11, PWM_0_3, SYS_GPE_MFPH_PE11MFP_EPWM0_CH3},
{PE_12, PWM_0_4, SYS_GPE_MFPH_PE12MFP_EPWM0_CH4},
{PE_13, PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5},
{NU_PINNAME_BIND(PE_13, PWM_0_5), PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5},
{PE_13, PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0},
{NU_PINNAME_BIND(PE_13, PWM_1_0), PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0},
{PH_11, PWM_0_5, SYS_GPH_MFPH_PH11MFP_EPWM0_CH5},
{NC, NC, 0}
};
//*** SERIAL ***
const PinMap PinMap_UART_TX[] = {
{PA_1, UART_0, SYS_GPA_MFPL_PA1MFP_UART0_TXD},
{PA_3, UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD},
{NU_PINNAME_BIND(PA_3, UART_1), UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD},
{PA_3, UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD},
{NU_PINNAME_BIND(PA_3, UART_4), UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD},
{PA_5, UART_5, SYS_GPA_MFPL_PA5MFP_UART5_TXD},
{PA_7, UART_0, SYS_GPA_MFPL_PA7MFP_UART0_TXD},
{PA_9, UART_1, SYS_GPA_MFPH_PA9MFP_UART1_TXD},
{PA_12, UART_4, SYS_GPA_MFPH_PA12MFP_UART4_TXD},
{PA_14, UART_0, SYS_GPA_MFPH_PA14MFP_UART0_TXD},
{PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD},
{PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD},
{PB_5, UART_5, SYS_GPB_MFPL_PB5MFP_UART5_TXD},
{PB_7, UART_1, SYS_GPB_MFPL_PB7MFP_UART1_TXD},
{PB_9, UART_0, SYS_GPB_MFPH_PB9MFP_UART0_TXD},
{PB_11, UART_4, SYS_GPB_MFPH_PB11MFP_UART4_TXD},
{PB_13, UART_0, SYS_GPB_MFPH_PB13MFP_UART0_TXD},
{PB_15, UART_3, SYS_GPB_MFPH_PB15MFP_UART3_TXD},
{PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_TXD},
{PC_3, UART_3, SYS_GPC_MFPL_PC3MFP_UART3_TXD},
{PC_5, UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD},
{NU_PINNAME_BIND(PC_5, UART_2), UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD},
{PC_5, UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD},
{NU_PINNAME_BIND(PC_5, UART_4), UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD},
{PC_7, UART_4, SYS_GPC_MFPL_PC7MFP_UART4_TXD},
{PC_10, UART_3, SYS_GPC_MFPH_PC10MFP_UART3_TXD},
{PC_12, UART_0, SYS_GPC_MFPH_PC12MFP_UART0_TXD},
{PC_13, UART_2, SYS_GPC_MFPH_PC13MFP_UART2_TXD},
{PD_1, UART_3, SYS_GPD_MFPL_PD1MFP_UART3_TXD},
{PD_3, UART_0, SYS_GPD_MFPL_PD3MFP_UART0_TXD},
{PD_7, UART_1, SYS_GPD_MFPL_PD7MFP_UART1_TXD},
{PD_11, UART_1, SYS_GPD_MFPH_PD11MFP_UART1_TXD},
{PE_1, UART_3, SYS_GPE_MFPL_PE1MFP_UART3_TXD},
{PE_7, UART_5, SYS_GPE_MFPL_PE7MFP_UART5_TXD},
{PE_8, UART_2, SYS_GPE_MFPH_PE8MFP_UART2_TXD},
{PE_10, UART_3, SYS_GPE_MFPH_PE10MFP_UART3_TXD},
{PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_TXD},
{PE_14, UART_2, SYS_GPE_MFPH_PE14MFP_UART2_TXD},
{PF_0, UART_1, SYS_GPF_MFPL_PF0MFP_UART1_TXD},
{PF_3, UART_0, SYS_GPF_MFPL_PF3MFP_UART0_TXD},
{PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_TXD},
{PF_7, UART_4, SYS_GPF_MFPL_PF7MFP_UART4_TXD},
{PH_8, UART_1, SYS_GPH_MFPH_PH8MFP_UART1_TXD},
{PH_10, UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD},
{NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD},
{PH_10, UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
{NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{PA_0, UART_0, SYS_GPA_MFPL_PA0MFP_UART0_RXD},
{PA_2, UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD},
{NU_PINNAME_BIND(PA_2, UART_1), UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD},
{PA_2, UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
{NU_PINNAME_BIND(PA_2, UART_4), UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
{PA_4, UART_5, SYS_GPA_MFPL_PA4MFP_UART5_RXD},
{PA_6, UART_0, SYS_GPA_MFPL_PA6MFP_UART0_RXD},
{PA_8, UART_1, SYS_GPA_MFPH_PA8MFP_UART1_RXD},
{PA_13, UART_4, SYS_GPA_MFPH_PA13MFP_UART4_RXD},
{PA_15, UART_0, SYS_GPA_MFPH_PA15MFP_UART0_RXD},
{PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD},
{PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD},
{PB_4, UART_5, SYS_GPB_MFPL_PB4MFP_UART5_RXD},
{PB_6, UART_1, SYS_GPB_MFPL_PB6MFP_UART1_RXD},
{PB_8, UART_0, SYS_GPB_MFPH_PB8MFP_UART0_RXD},
{PB_10, UART_4, SYS_GPB_MFPH_PB10MFP_UART4_RXD},
{PB_12, UART_0, SYS_GPB_MFPH_PB12MFP_UART0_RXD},
{PB_14, UART_3, SYS_GPB_MFPH_PB14MFP_UART3_RXD},
{PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_RXD},
{PC_2, UART_3, SYS_GPC_MFPL_PC2MFP_UART3_RXD},
{PC_4, UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD},
{NU_PINNAME_BIND(PC_4, UART_2), UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD},
{PC_4, UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD},
{NU_PINNAME_BIND(PC_4, UART_4), UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD},
{PC_6, UART_4, SYS_GPC_MFPL_PC6MFP_UART4_RXD},
{PC_8, UART_1, SYS_GPC_MFPH_PC8MFP_UART1_RXD},
{PC_9, UART_3, SYS_GPC_MFPH_PC9MFP_UART3_RXD},
{PC_11, UART_0, SYS_GPC_MFPH_PC11MFP_UART0_RXD},
{PD_0, UART_3, SYS_GPD_MFPL_PD0MFP_UART3_RXD},
{PD_2, UART_0, SYS_GPD_MFPL_PD2MFP_UART0_RXD},
{PD_6, UART_1, SYS_GPD_MFPL_PD6MFP_UART1_RXD},
{PD_10, UART_1, SYS_GPD_MFPH_PD10MFP_UART1_RXD},
{PD_12, UART_2, SYS_GPD_MFPH_PD12MFP_UART2_RXD},
{PE_0, UART_3, SYS_GPE_MFPL_PE0MFP_UART3_RXD},
{PE_6, UART_5, SYS_GPE_MFPL_PE6MFP_UART5_RXD},
{PE_9, UART_2, SYS_GPE_MFPH_PE9MFP_UART2_RXD},
{PE_11, UART_3, SYS_GPE_MFPH_PE11MFP_UART3_RXD},
{PE_15, UART_2, SYS_GPE_MFPH_PE15MFP_UART2_RXD},
{PF_1, UART_1, SYS_GPF_MFPL_PF1MFP_UART1_RXD},
{PF_2, UART_0, SYS_GPF_MFPL_PF2MFP_UART0_RXD},
{PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_RXD},
{PF_6, UART_4, SYS_GPF_MFPL_PF6MFP_UART4_RXD},
{PH_9, UART_1, SYS_GPH_MFPH_PH9MFP_UART1_RXD},
{PH_11, UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD},
{NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD},
{PH_11, UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
{NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nRTS},
{PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_nRTS},
{PB_3, UART_5, SYS_GPB_MFPL_PB3MFP_UART5_nRTS},
{PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS},
{PB_10, UART_0, SYS_GPB_MFPH_PB10MFP_UART0_nRTS},
{PB_13, UART_3, SYS_GPB_MFPH_PB13MFP_UART3_nRTS},
{PB_14, UART_0, SYS_GPB_MFPH_PB14MFP_UART0_nRTS},
{PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_nRTS},
{PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_nRTS},
{PD_3, UART_3, SYS_GPD_MFPL_PD3MFP_UART3_nRTS},
{PD_8, UART_2, SYS_GPD_MFPH_PD8MFP_UART2_nRTS},
{PE_0, UART_4, SYS_GPE_MFPL_PE0MFP_UART4_nRTS},
{PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_nRTS},
{PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_nRTS},
{PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS},
{PH_8, UART_3, SYS_GPH_MFPH_PH8MFP_UART3_nRTS},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nCTS},
{PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_nCTS},
{PB_2, UART_5, SYS_GPB_MFPL_PB2MFP_UART5_nCTS},
{PB_9, UART_1, SYS_GPB_MFPH_PB9MFP_UART1_nCTS},
{PB_11, UART_0, SYS_GPB_MFPH_PB11MFP_UART0_nCTS},
{PB_12, UART_3, SYS_GPB_MFPH_PB12MFP_UART3_nCTS},
{PB_15, UART_0, SYS_GPB_MFPH_PB15MFP_UART0_nCTS},
{PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_nCTS},
{PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_nCTS},
{PC_8, UART_4, SYS_GPC_MFPH_PC8MFP_UART4_nCTS},
{PD_2, UART_3, SYS_GPD_MFPL_PD2MFP_UART3_nCTS},
{PD_9, UART_2, SYS_GPD_MFPH_PD9MFP_UART2_nCTS},
{PE_1, UART_4, SYS_GPE_MFPL_PE1MFP_UART4_nCTS},
{PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS},
{PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS},
{PH_9, UART_3, SYS_GPH_MFPH_PH9MFP_UART3_nCTS},
{NC, NC, 0}
};
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
{PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI},
{PA_8, SPI_2, SYS_GPA_MFPH_PA8MFP_SPI2_MOSI},
{PA_15, SPI_2, SYS_GPA_MFPH_PA15MFP_SPI2_MOSI},
{PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_MOSI},
{PB_8, SPI_3, SYS_GPB_MFPH_PB8MFP_SPI3_MOSI},
{PB_12, SPI_0, SYS_GPB_MFPH_PB12MFP_SPI0_MOSI},
{PC_0, SPI_5, SYS_GPC_MFPL_PC0MFP_SPI5_MOSI},
{PC_2, SPI_1, SYS_GPC_MFPL_PC2MFP_SPI1_MOSI},
{PC_6, SPI_1, SYS_GPC_MFPL_PC6MFP_SPI1_MOSI},
{PC_11, SPI_3, SYS_GPC_MFPH_PC11MFP_SPI3_MOSI},
{PD_0, SPI_0, SYS_GPD_MFPL_PD0MFP_SPI0_MOSI},
{PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_MOSI},
{PE_0, SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI},
{PE_2, SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MOSI},
{NU_PINNAME_BIND(PE_2, SPI_3), SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MOSI},
{PE_2, SPI_5, SYS_GPE_MFPL_PE2MFP_SPI5_MOSI},
{NU_PINNAME_BIND(PE_2, SPI_5), SPI_5, SYS_GPE_MFPL_PE2MFP_SPI5_MOSI},
{PE_10, SPI_2, SYS_GPE_MFPH_PE10MFP_SPI2_MOSI},
{PF_6, SPI_0, SYS_GPF_MFPL_PF6MFP_SPI0_MOSI},
{PF_11, SPI_2, SYS_GPF_MFPH_PF11MFP_SPI2_MOSI},
{PG_10, SPI_5, SYS_GPG_MFPH_PG10MFP_SPI5_MOSI},
{PH_5, SPI_1, SYS_GPH_MFPL_PH5MFP_SPI1_MOSI},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO},
{PA_9, SPI_2, SYS_GPA_MFPH_PA9MFP_SPI2_MISO},
{PA_14, SPI_2, SYS_GPA_MFPH_PA14MFP_SPI2_MISO},
{PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MISO},
{PB_9, SPI_3, SYS_GPB_MFPH_PB9MFP_SPI3_MISO},
{PB_13, SPI_0, SYS_GPB_MFPH_PB13MFP_SPI0_MISO},
{PC_1, SPI_5, SYS_GPC_MFPL_PC1MFP_SPI5_MISO},
{PC_3, SPI_1, SYS_GPC_MFPL_PC3MFP_SPI1_MISO},
{PC_7, SPI_1, SYS_GPC_MFPL_PC7MFP_SPI1_MISO},
{PC_12, SPI_3, SYS_GPC_MFPH_PC12MFP_SPI3_MISO},
{PD_1, SPI_0, SYS_GPD_MFPL_PD1MFP_SPI0_MISO},
{PD_7, SPI_1, SYS_GPD_MFPL_PD7MFP_SPI1_MISO},
{PE_1, SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO},
{PE_3, SPI_3, SYS_GPE_MFPL_PE3MFP_SPI3_MISO},
{NU_PINNAME_BIND(PE_3, SPI_3), SPI_3, SYS_GPE_MFPL_PE3MFP_SPI3_MISO},
{PE_3, SPI_5, SYS_GPE_MFPL_PE3MFP_SPI5_MISO},
{NU_PINNAME_BIND(PE_3, SPI_5), SPI_5, SYS_GPE_MFPL_PE3MFP_SPI5_MISO},
{PE_9, SPI_2, SYS_GPE_MFPH_PE9MFP_SPI2_MISO},
{PF_7, SPI_0, SYS_GPF_MFPL_PF7MFP_SPI0_MISO},
{PG_4, SPI_2, SYS_GPG_MFPL_PG4MFP_SPI2_MISO},
{PG_9, SPI_5, SYS_GPG_MFPH_PG9MFP_SPI5_MISO},
{PH_4, SPI_1, SYS_GPH_MFPL_PH4MFP_SPI1_MISO},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SCLK[] = {
{PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK},
{PA_4, SPI_0, SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK},
{PA_5, SPI_1, SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK},
{PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK},
{PA_10, SPI_2, SYS_GPA_MFPH_PA10MFP_SPI2_CLK},
{PA_13, SPI_2, SYS_GPA_MFPH_PA13MFP_SPI2_CLK},
{PB_0, SPI_0, SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK},
{PB_1, SPI_1, SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK},
{NU_PINNAME_BIND(PB_1, SPI_1), SPI_1, SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK},
{PB_1, SPI_3, SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK},
{NU_PINNAME_BIND(PB_1, SPI_3), SPI_3, SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK},
{PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_CLK},
{PB_11, SPI_0, SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK},
{NU_PINNAME_BIND(PB_11, SPI_0), SPI_0, SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK},
{PB_11, SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK},
{NU_PINNAME_BIND(PB_11, SPI_3), SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK},
{PB_14, SPI_0, SYS_GPB_MFPH_PB14MFP_SPI0_CLK},
{PC_1, SPI_1, SYS_GPC_MFPL_PC1MFP_SPI1_CLK},
{PC_2, SPI_5, SYS_GPC_MFPL_PC2MFP_SPI5_CLK},
{PC_4, SPI_1, SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK},
{PC_10, SPI_3, SYS_GPC_MFPH_PC10MFP_SPI3_CLK},
{PC_13, SPI_2, SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK},
{PD_2, SPI_0, SYS_GPD_MFPL_PD2MFP_SPI0_CLK},
{PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_CLK},
{PD_13, SPI_0, SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK},
{NU_PINNAME_BIND(PD_13, SPI_0), SPI_0, SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK},
{PD_13, SPI_1, SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK},
{NU_PINNAME_BIND(PD_13, SPI_1), SPI_1, SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK},
{PD_14, SPI_0, SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK},
{NU_PINNAME_BIND(PD_14, SPI_0), SPI_0, SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK},
{PD_14, SPI_3, SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK},
{NU_PINNAME_BIND(PD_14, SPI_3), SPI_3, SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK},
{PE_4, SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK},
{NU_PINNAME_BIND(PE_4, SPI_3), SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK},
{PE_4, SPI_5, SYS_GPE_MFPL_PE4MFP_SPI5_CLK},
{NU_PINNAME_BIND(PE_4, SPI_5), SPI_5, SYS_GPE_MFPL_PE4MFP_SPI5_CLK},
{PE_6, SPI_3, SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK},
{PE_8, SPI_2, SYS_GPE_MFPH_PE8MFP_SPI2_CLK},
{PE_12, SPI_2, SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK},
{PF_8, SPI_0, SYS_GPF_MFPH_PF8MFP_SPI0_CLK},
{PF_10, SPI_0, SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK},
{PG_3, SPI_2, SYS_GPG_MFPL_PG3MFP_SPI2_CLK},
{PG_11, SPI_5, SYS_GPG_MFPH_PG11MFP_SPI5_CLK},
{PH_6, SPI_1, SYS_GPH_MFPL_PH6MFP_SPI1_CLK},
{PH_8, SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK},
{PH_10, SPI_1, SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PA_3, SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS},
{PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_SS},
{PA_11, SPI_2, SYS_GPA_MFPH_PA11MFP_SPI2_SS},
{PA_12, SPI_2, SYS_GPA_MFPH_PA12MFP_SPI2_SS},
{PB_2, SPI_1, SYS_GPB_MFPL_PB2MFP_SPI1_SS},
{PB_10, SPI_3, SYS_GPB_MFPH_PB10MFP_SPI3_SS},
{PB_15, SPI_0, SYS_GPB_MFPH_PB15MFP_SPI0_SS},
{PC_0, SPI_1, SYS_GPC_MFPL_PC0MFP_SPI1_SS},
{PC_3, SPI_5, SYS_GPC_MFPL_PC3MFP_SPI5_SS},
{PC_9, SPI_3, SYS_GPC_MFPH_PC9MFP_SPI3_SS},
{PD_3, SPI_0, SYS_GPD_MFPL_PD3MFP_SPI0_SS},
{PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_SS},
{PE_5, SPI_3, SYS_GPE_MFPL_PE5MFP_SPI3_SS},
{NU_PINNAME_BIND(PE_5, SPI_3), SPI_3, SYS_GPE_MFPL_PE5MFP_SPI3_SS},
{PE_5, SPI_5, SYS_GPE_MFPL_PE5MFP_SPI5_SS},
{NU_PINNAME_BIND(PE_5, SPI_5), SPI_5, SYS_GPE_MFPL_PE5MFP_SPI5_SS},
{PE_11, SPI_2, SYS_GPE_MFPH_PE11MFP_SPI2_SS},
{PF_9, SPI_0, SYS_GPF_MFPH_PF9MFP_SPI0_SS},
{PG_2, SPI_2, SYS_GPG_MFPL_PG2MFP_SPI2_SS},
{PG_12, SPI_5, SYS_GPG_MFPH_PG12MFP_SPI5_SS},
{PH_7, SPI_1, SYS_GPH_MFPL_PH7MFP_SPI1_SS},
{PH_9, SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS},
{NC, NC, 0}
};
//*** SD ***
const PinMap PinMap_SD_DAT0[] = {
{PB_2, SD_0, SYS_GPB_MFPL_PB2MFP_SD0_DAT0},
{PE_2, SD_0, SYS_GPE_MFPL_PE2MFP_SD0_DAT0},
{NC, NC, 0}
};
const PinMap PinMap_SD_DAT1[] = {
{PB_3, SD_0, SYS_GPB_MFPL_PB3MFP_SD0_DAT1},
{PE_3, SD_0, SYS_GPE_MFPL_PE3MFP_SD0_DAT1},
{NC, NC, 0}
};
const PinMap PinMap_SD_DAT2[] = {
{PB_4, SD_0, SYS_GPB_MFPL_PB4MFP_SD0_DAT2},
{PE_4, SD_0, SYS_GPE_MFPL_PE4MFP_SD0_DAT2},
{NC, NC, 0}
};
const PinMap PinMap_SD_DAT3[] = {
{PB_5, SD_0, SYS_GPB_MFPL_PB5MFP_SD0_DAT3},
{PE_5, SD_0, SYS_GPE_MFPL_PE5MFP_SD0_DAT3},
{NC, NC, 0}
};
const PinMap PinMap_SD_CMD[] = {
{PB_0, SD_0, SYS_GPB_MFPL_PB0MFP_SD0_CMD},
{PE_7, SD_0, SYS_GPE_MFPL_PE7MFP_SD0_CMD},
{NC, NC, 0}
};
const PinMap PinMap_SD_CLK[] = {
{PB_1, SD_0, SYS_GPB_MFPL_PB1MFP_SD0_CLK},
{PE_6, SD_0, SYS_GPE_MFPL_PE6MFP_SD0_CLK},
{NC, NC, 0}
};
const PinMap PinMap_SD_CD[] = {
{PB_12, SD_0, SYS_GPB_MFPH_PB12MFP_SD0_nCD},
{PD_13, SD_0, SYS_GPD_MFPH_PD13MFP_SD0_nCD},
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
{PA_5, CAN_0, SYS_GPA_MFPL_PA5MFP_CAN0_TXD},
{PA_12, CAN_0, SYS_GPA_MFPH_PA12MFP_CAN0_TXD},
{PB_11, CAN_0, SYS_GPB_MFPH_PB11MFP_CAN0_TXD},
{PC_5, CAN_0, SYS_GPC_MFPL_PC5MFP_CAN0_TXD},
{PD_11, CAN_0, SYS_GPD_MFPH_PD11MFP_CAN0_TXD},
{PE_14, CAN_0, SYS_GPE_MFPH_PE14MFP_CAN0_TXD},
{NC, NC, 0}
};
const PinMap PinMap_CAN_RD[] = {
{PA_4, CAN_0, SYS_GPA_MFPL_PA4MFP_CAN0_RXD},
{PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD},
{PB_10, CAN_0, SYS_GPB_MFPH_PB10MFP_CAN0_RXD},
{PC_4, CAN_0, SYS_GPC_MFPL_PC4MFP_CAN0_RXD},
{PD_10, CAN_0, SYS_GPD_MFPH_PD10MFP_CAN0_RXD},
{PE_15, CAN_0, SYS_GPE_MFPH_PE15MFP_CAN0_RXD},
{NC, NC, 0}
};

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/* mbed Microcontroller Library
* Copyright (c) 2015-2016 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
#ifdef __cplusplus
extern "C" {
#endif
//*** GPIO ***
extern const PinMap PinMap_GPIO[];
//*** ADC ***
extern const PinMap PinMap_ADC[];
//*** I2C ***
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
//*** PWM ***
extern const PinMap PinMap_PWM[];
//*** SERIAL ***
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
extern const PinMap PinMap_UART_RTS[];
extern const PinMap PinMap_UART_CTS[];
//*** SPI ***
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_SSEL[];
//*** SD ***
extern const PinMap PinMap_SD_CD[];
extern const PinMap PinMap_SD_CMD[];
extern const PinMap PinMap_SD_CLK[];
extern const PinMap PinMap_SD_DAT0[];
extern const PinMap PinMap_SD_DAT1[];
extern const PinMap PinMap_SD_DAT2[];
extern const PinMap PinMap_SD_DAT3[];
//*** CAN ***
extern PinMap const PinMap_CAN_TD[];
extern PinMap const PinMap_CAN_RD[];
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2017-2018 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "partition_M2351.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NU_PININDEX_Pos 0
#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos)
#define NU_PINPORT_Pos 8
#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos)
#define NU_PIN_MODINDEX_Pos 12
#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos)
#define NU_PIN_BIND_Pos 16
#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos)
#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos)
#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos)
#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos)
#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos)
#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos))
#define NU_PINNAME_BIND(PINNAME, modname) ((PinName) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname))
#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
/* Revise NU_PORT_BASE to be TrustZone-aware */
__STATIC_INLINE GPIO_T *NU_PORT_BASE(uint32_t PORT)
{
uint32_t port_base = ((uint32_t) GPIOA_BASE) + 0x40 * PORT;
#if defined(SCU_INIT_IONSSET_VAL)
if (SCU_INIT_IONSSET_VAL & (1 << (PORT + 0))) {
port_base += NS_OFFSET;
}
#endif
return ((GPIO_T *) port_base);
}
#define NU_MFP_POS(pin) ((pin % 8) * 4)
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
/* TrustZone-aware version of GPIO_PIN_DATA to get GPIO pin data */
__STATIC_INLINE uint32_t NU_GET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN)
{
#if defined(SCU_INIT_IONSSET_VAL)
if (SCU_INIT_IONSSET_VAL & (1 << (PORT + 0))) {
return GPIO_PIN_DATA_NS(PORT, PIN);
}
#endif
return GPIO_PIN_DATA(PORT, PIN);
}
/* TrustZone-aware version of GPIO_PIN_DATA to set GPIO pin data */
__STATIC_INLINE void NU_SET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN, uint32_t VALUE)
{
#if defined(SCU_INIT_IONSSET_VAL)
if (SCU_INIT_IONSSET_VAL & (1 << (PORT + 0))) {
GPIO_PIN_DATA_NS(PORT, PIN) = VALUE;
return;
}
#endif
GPIO_PIN_DATA(PORT, PIN) = VALUE;
}
// LEGACY
#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME)
#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME)
#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME)
#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN))
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PullNone = 0,
PullDown,
PullUp,
PushPull,
OpenDrain,
Quasi,
PullDefault = PullUp,
} PinMode;
typedef enum {
// Not connected
NC = (int)0xFFFFFFFF,
// Generic naming
PA_0 = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
PB_0 = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
PC_0 = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13,
PD_0 = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14,
PE_0 = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15,
PF_0 = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11,
PG_0 = NU_PORT_N_PIN_TO_PINNAME(6, 0), PG_1, PG_2, PG_3, PG_4, PG_5, PG_6, PG_7, PG_8, PG_9, PG_10, PG_11, PG_12, PG_13, PG_14, PG_15,
PH_0 = NU_PORT_N_PIN_TO_PINNAME(7, 0), PH_1, PH_2, PH_3, PH_4, PH_5, PH_6, PH_7, PH_8, PH_9, PH_10, PH_11,
// Arduino UNO naming
A0 = PB_11,
A1 = PB_10,
A2 = PB_9,
A3 = PB_8,
A4 = PB_7,
A5 = PB_6,
D0 = PA_8,
D1 = PA_9,
D2 = PB_5,
D3 = PB_4,
D4 = PB_3,
D5 = PB_2,
D6 = PC_12,
D7 = PC_11,
D8 = PC_9,
D9 = PC_10,
D10 = PF_9,
D11 = PF_6,
D12 = PF_7,
D13 = PF_8,
D14 = PG_3,
D15 = PG_2,
// Other board-specific naming
// UART naming
USBTX = PB_13,
USBRX = PB_12,
STDIO_UART_TX = USBTX,
STDIO_UART_RX = USBRX,
// I2C naming
I2C_SCL = D15,
I2C_SDA = D14,
// LED naming
LED1 = PA_10,
LED2 = PA_11,
LED3 = PA_10, // No real LED. Just for passing ATS.
LED4 = PA_11, // No real LED. Just for passing ATS.
LED_GREEN = LED2,
// Button naming
SW2 = PB_0,
SW3 = PB_1,
} PinName;
#ifdef __cplusplus
}
#endif
#endif // MBED_PINNAMES_H

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/* mbed Microcontroller Library
* Copyright (c) 2015-2016 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2015-2016 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2015-2016 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "mbed_error.h"
void mbed_sdk_init(void)
{
// NOTE: Support singleton semantics to be called from other init functions
static int inited = 0;
if (inited) {
return;
}
inited = 1;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable HIRC clock (Internal RC 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Enable LIRC for lp_ticker */
CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
/* Enable LXT for RTC */
CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
/* Enable HIRC48 clock (Internal RC 48MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Wait for LIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
/* Wait for LXT clock ready */
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
/* Wait for HIRC48 clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
#if defined(NU_CHIP_MAJOR) && (NU_CHIP_MAJOR == 1UL)
/* NOTE: There is a reset halt issue with PLL in A version. Work around it
* by using HIRC48 instead of PLL as HCLK clock source. */
/* Trim HIRC48 to 48M against LXT */
/* Reset TISTS48M status flags */
SYS->TISTS48M |= (SYS_TISTS48M_FREQLOCK_Msk | SYS_TISTS48M_TFAILIF_Msk | SYS_TISTS48M_CLKERRIF_Msk);
/* With reference clock from LXT, start trimming HIRC48 to 48M */
SYS->TCTL48M = (SYS->TCTL48M & ~(SYS_TCTL48M_FREQSEL_Msk | SYS_TCTL48M_REFCKSEL_Msk)) | (0x01 << SYS_TCTL48M_FREQSEL_Pos) | (0x00 << SYS_TCTL48M_REFCKSEL_Pos);
/* Wait for HIRC48 clock locked */
while (1)
{
if (SYS->TISTS48M & SYS_TISTS48M_FREQLOCK_Msk)
{
break;
}
else if (SYS->TISTS48M & SYS_TISTS48M_TFAILIF_Msk)
{
error("HIRC48 auto-trim error: SYS_TISTS48M_TFAILIF_Msk");
}
else if (SYS->TISTS48M & SYS_TISTS48M_CLKERRIF_Msk)
{
error("HIRC48 auto-trim error: SYS_TISTS48M_CLKERRIF_Msk");
}
}
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC48, CLK_CLKDIV0_HCLK(1UL));
#else
/* Set core clock as 64M from PLL */
CLK_SetCoreClock(FREQ_64MHZ);
#endif
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
#else
SystemCoreClockUpdate();
#endif
}

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/* mbed Microcontroller Library
* Copyright (c) 2015-2017 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "dma_api.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
PinName pin;
uint32_t irq_handler;
uint32_t irq_id;
struct gpio_irq_s *next;
};
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
};
struct analogin_s {
ADCName adc;
};
struct serial_s {
UARTName uart;
PinName pin_tx;
PinName pin_rx;
uint32_t baudrate;
uint32_t databits;
uint32_t parity;
uint32_t stopbits;
void (*vec)(void);
uint32_t irq_handler;
uint32_t irq_id;
uint32_t irq_en;
uint32_t inten_msk;
// Async transfer related fields
DMAUsage dma_usage_tx;
DMAUsage dma_usage_rx;
int dma_chn_id_tx;
int dma_chn_id_rx;
uint32_t event;
void (*irq_handler_tx_async)(void);
void (*irq_handler_rx_async)(void);
};
struct spi_s {
SPIName spi;
PinName pin_miso;
PinName pin_mosi;
PinName pin_sclk;
PinName pin_ssel;
// Async transfer related fields
DMAUsage dma_usage;
int dma_chn_id_tx;
int dma_chn_id_rx;
uint32_t event;
uint32_t hdlr_async;
};
struct i2c_s {
I2CName i2c;
int slaveaddr_state;
uint32_t tran_ctrl;
char * tran_beg;
char * tran_pos;
char * tran_end;
int inten;
// Async transfer related fields
DMAUsage dma_usage;
uint32_t event;
int stop;
uint32_t address;
uint32_t hdlr_async;
};
struct pwmout_s {
PWMName pwm;
uint32_t period_us;
uint32_t pulsewidth_us;
};
struct sleep_s {
int powerdown;
};
struct trng_s {
uint8_t dummy;
};
#ifdef __cplusplus
}
#endif
#include "gpio_object.h"
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2017-2018 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#if DEVICE_ANALOGIN
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "nu_modutil.h"
static uint32_t eadc_modinit_mask = 0;
static const struct nu_modinit_s adc_modinit_tab[] = {
{ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
};
void analogin_init(analogin_t *obj, PinName pin)
{
obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName) NC);
const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == (int) obj->adc);
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
if (! eadc_modinit_mask) {
/* Reset module
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
/* Select IP clock source
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
// Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
}
uint32_t chn = NU_MODSUBINDEX(obj->adc);
// Wire pinout
pinmap_pinout(pin, PinMap_ADC);
// Configure the sample module Nmod for analog input channel Nch and software trigger source
EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn);
eadc_modinit_mask |= 1 << chn;
}
uint16_t analogin_read_u16(analogin_t *obj)
{
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
uint32_t chn = NU_MODSUBINDEX(obj->adc);
EADC_START_CONV(eadc_base, 1 << chn);
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != ((uint32_t) (1 << chn)));
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
// Just 12 bits are effective. Convert to 16 bits.
// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
// conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8);
return conv_res_16;
}
float analogin_read(analogin_t *obj)
{
uint16_t value = analogin_read_u16(obj);
return (float) value * (1.0f / (float) 0xFFFF);
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2017-2018 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "mbed_assert.h"
#include "mbed_critical.h"
#include "mbed_error.h"
#include <limits.h>
#include "nu_modutil.h"
#include "nu_bitutil.h"
#include "crypto-misc.h"
#if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT)
/* NOTE: There's inconsistency in cryptography related naming, Crpt or Crypto. For example, cryptography IRQ
* handler could be CRPT_IRQHandler or CRYPTO_IRQHandler. To override default cryptography IRQ handler, see
* device/startup_{CHIP}.c for its name or call NVIC_SetVector regardless of its name. */
void CRPT_IRQHandler();
/* Track if AES H/W is available */
static uint16_t crypto_aes_avail = 1;
/* Track if DES H/W is available */
static uint16_t crypto_des_avail = 1;
/* Track if SHA H/W is available */
static uint16_t crypto_sha_avail = 1;
/* Track if ECC H/W is available */
static uint16_t crypto_ecc_avail = 1;
/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */
static uint16_t crypto_init_counter = 0U;
static bool crypto_submodule_acquire(uint16_t *submodule_avail);
static void crypto_submodule_release(uint16_t *submodule_avail);
/* Crypto done flags */
#define CRYPTO_DONE_OK BIT0 /* Done with OK */
#define CRYPTO_DONE_ERR BIT1 /* Done with error */
/* Track if PRNG H/W operation is done */
static volatile uint16_t crypto_prng_done;
/* Track if AES H/W operation is done */
static volatile uint16_t crypto_aes_done;
/* Track if DES H/W operation is done */
static volatile uint16_t crypto_des_done;
/* Track if ECC H/W operation is done */
static volatile uint16_t crypto_ecc_done;
static void crypto_submodule_prestart(volatile uint16_t *submodule_done);
static bool crypto_submodule_wait(volatile uint16_t *submodule_done);
/* As crypto init counter changes from 0 to 1:
*
* 1. Enable crypto clock
* 2. Enable crypto interrupt
*/
void crypto_init(void)
{
core_util_critical_section_enter();
if (crypto_init_counter == USHRT_MAX) {
core_util_critical_section_exit();
error("Crypto clock enable counter would overflow (> USHRT_MAX)");
}
core_util_atomic_incr_u16(&crypto_init_counter, 1);
if (crypto_init_counter == 1) {
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(CRPT_MODULE);
NVIC_SetVector(CRPT_IRQn, (uint32_t) CRPT_IRQHandler);
NVIC_EnableIRQ(CRPT_IRQn);
}
core_util_critical_section_exit();
}
/* As crypto init counter changes from 1 to 0:
*
* 1. Disable crypto interrupt
* 2. Disable crypto clock
*/
void crypto_uninit(void)
{
core_util_critical_section_enter();
if (crypto_init_counter == 0) {
core_util_critical_section_exit();
error("Crypto clock enable counter would underflow (< 0)");
}
core_util_atomic_decr_u16(&crypto_init_counter, 1);
if (crypto_init_counter == 0) {
NVIC_DisableIRQ(CRPT_IRQn);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_DisableModuleClock_S(CRPT_MODULE);
}
core_util_critical_section_exit();
}
/* Implementation that should never be optimized out by the compiler */
void crypto_zeroize(void *v, size_t n)
{
volatile unsigned char *p = (volatile unsigned char*) v;
while (n--) {
*p++ = 0;
}
}
/* Implementation that should never be optimized out by the compiler */
void crypto_zeroize32(uint32_t *v, size_t n)
{
volatile uint32_t *p = (volatile uint32_t*) v;
while (n--) {
*p++ = 0;
}
}
bool crypto_aes_acquire(void)
{
return crypto_submodule_acquire(&crypto_aes_avail);
}
void crypto_aes_release(void)
{
crypto_submodule_release(&crypto_aes_avail);
}
bool crypto_des_acquire(void)
{
return crypto_submodule_acquire(&crypto_des_avail);
}
void crypto_des_release(void)
{
crypto_submodule_release(&crypto_des_avail);
}
bool crypto_sha_acquire(void)
{
return crypto_submodule_acquire(&crypto_sha_avail);
}
void crypto_sha_release(void)
{
crypto_submodule_release(&crypto_sha_avail);
}
bool crypto_ecc_acquire(void)
{
return crypto_submodule_acquire(&crypto_ecc_avail);
}
void crypto_ecc_release(void)
{
crypto_submodule_release(&crypto_ecc_avail);
}
void crypto_prng_prestart(void)
{
crypto_submodule_prestart(&crypto_prng_done);
}
bool crypto_prng_wait(void)
{
return crypto_submodule_wait(&crypto_prng_done);
}
void crypto_aes_prestart(void)
{
crypto_submodule_prestart(&crypto_aes_done);
}
bool crypto_aes_wait(void)
{
return crypto_submodule_wait(&crypto_aes_done);
}
void crypto_des_prestart(void)
{
crypto_submodule_prestart(&crypto_des_done);
}
bool crypto_des_wait(void)
{
return crypto_submodule_wait(&crypto_des_done);
}
void crypto_ecc_prestart(void)
{
crypto_submodule_prestart(&crypto_ecc_done);
}
bool crypto_ecc_wait(void)
{
return crypto_submodule_wait(&crypto_ecc_done);
}
bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to)
{
uint32_t buff_ = (uint32_t) buff;
return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */
((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */
(((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */
}
/* Overlap cases
*
* 1. in_buff in front of out_buff:
*
* in in_end
* | |
* ||||||||||||||||
* ||||||||||||||||
* | |
* out out_end
*
* 2. out_buff in front of in_buff:
*
* in in_end
* | |
* ||||||||||||||||
* ||||||||||||||||
* | |
* out out_end
*/
bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size)
{
uint32_t in = (uint32_t) in_buff;
uint32_t in_end = in + in_buff_size;
uint32_t out = (uint32_t) out_buff;
uint32_t out_end = out + out_buff_size;
bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end);
return overlap;
}
static bool crypto_submodule_acquire(uint16_t *submodule_avail)
{
uint16_t expectedCurrentValue = 1;
return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0);
}
static void crypto_submodule_release(uint16_t *submodule_avail)
{
uint16_t expectedCurrentValue = 0;
while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1));
}
static void crypto_submodule_prestart(volatile uint16_t *submodule_done)
{
*submodule_done = 0;
/* Ensure memory accesses above are completed before DMA is started
*
* Replacing __DSB() with __DMB() is also OK in this case.
*
* Refer to "multi-master systems" section with DMA in:
* https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf
*/
__DSB();
}
static bool crypto_submodule_wait(volatile uint16_t *submodule_done)
{
while (! *submodule_done);
/* Ensure while loop above and subsequent code are not reordered */
__DSB();
if ((*submodule_done & CRYPTO_DONE_OK)) {
/* Done with OK */
return true;
} else if ((*submodule_done & CRYPTO_DONE_ERR)) {
/* Done with error */
return false;
}
return false;
}
/* Crypto interrupt handler */
void CRPT_IRQHandler()
{
uint32_t intsts;
if ((intsts = PRNG_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Done with OK */
crypto_prng_done |= CRYPTO_DONE_OK;
/* Clear interrupt flag */
PRNG_CLR_INT_FLAG(CRYPTO_MODBASE());
} else if ((intsts = AES_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Done with OK */
crypto_aes_done |= CRYPTO_DONE_OK;
/* Clear interrupt flag */
AES_CLR_INT_FLAG(CRYPTO_MODBASE());
} else if ((intsts = TDES_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Done with OK */
crypto_des_done |= CRYPTO_DONE_OK;
/* Clear interrupt flag */
TDES_CLR_INT_FLAG(CRYPTO_MODBASE());
} else if ((intsts = ECC_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Check interrupt flags */
if (intsts & CRPT_INTSTS_ECCIF_Msk) {
/* Done with OK */
crypto_ecc_done |= CRYPTO_DONE_OK;
} else if (intsts & CRPT_INTSTS_ECCEIF_Msk) {
/* Done with error */
crypto_ecc_done |= CRYPTO_DONE_ERR;
}
/* Clear interrupt flag */
ECC_CLR_INT_FLAG(CRYPTO_MODBASE());
}
}
#endif /* #if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) */

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/* mbed Microcontroller Library
* Copyright (c) 2017-2018 Nuvoton
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CRYPTO_MISC_H
#define MBED_CRYPTO_MISC_H
#include <stdbool.h>
#include "partition_M2351.h"
/* Policy for configuring secure attribute of CRYPTO/CRPT module:
*
* There's only one CRYPTO/CRPT module and we have the following policy for configuring its secure attribute:
*
* 1. TRNG or mbedtls H/W support can be enabled on either secure target or non-secure target, but not both.
* 2. TRNG and mbedtls H/W supports cannot be enabled on different targets.
* 3. On secure target, if TRNG or mbedtls H/W support is enabled, CRYPTO/CRPT must configure to secure.
* 4. On non-secure target, if TRNG or mbedtls H/W support is enabled, CRYPTO/CRPT must configure to non-secure.
*/
#if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT)
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined(SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & (1 << 18))
#error("CRYPTO/CRPT must configure to secure for secure target which supports TRNG or mbedtls H/W")
#endif
#else
#if (! defined(SCU_INIT_PNSSET1_VAL)) || (! (SCU_INIT_PNSSET1_VAL & (1 << 18)))
#error("CRYPTO/CRPT must configure to non-secure for non-secure target which supports TRNG or mbedtls H/W")
#endif
#endif
#endif
#if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT)
#ifdef __cplusplus
extern "C" {
#endif
/* Get Crypto module base dependent on security state */
__STATIC_INLINE CRPT_T *CRYPTO_MODBASE(void)
{
#if defined(SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & (1<<18))
return CRPT_NS;
#else
return CRPT;
#endif
}
/* Init/Uninit crypto module */
void crypto_init(void);
void crypto_uninit(void);
/* Clear buffer to zero
* Implementation that should never be optimized out by the compiler */
void crypto_zeroize(void *v, size_t n);
void crypto_zeroize32(uint32_t *v, size_t n);
/* Acquire/release ownership of AES H/W */
/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
bool crypto_aes_acquire(void);
void crypto_aes_release(void);
/* Acquire/release ownership of DES H/W */
/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
bool crypto_des_acquire(void);
void crypto_des_release(void);
/* Acquire/release ownership of SHA H/W */
/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
bool crypto_sha_acquire(void);
void crypto_sha_release(void);
/* Acquire/release ownership of ECC H/W */
/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */
bool crypto_ecc_acquire(void);
void crypto_ecc_release(void);
/* Flow control between crypto/xxx start and crypto/xxx ISR
*
* crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR.
*
* crypto_xxx_prestart will also address synchronization issue with memory barrier instruction.
*
* On finish, return of crypto_xxx_wait indicates success or not:
* true if successful
* false if failed
*
* Example: Start AES H/W and wait for its finish
* crypto_aes_prestart();
* AES_Start();
* crypto_aes_wait();
*/
void crypto_prng_prestart(void);
bool crypto_prng_wait(void);
void crypto_aes_prestart(void);
bool crypto_aes_wait(void);
void crypto_des_prestart(void);
bool crypto_des_wait(void);
void crypto_ecc_prestart(void);
bool crypto_ecc_wait(void);
/* Check if buffer can be used for crypto DMA. It has the following requirements:
* (1) Word-aligned buffer base address
* (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power.
* (3) Located in 0x20000000-0x2FFFFFFF region
*/
bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to);
/* Check if input/output buffers are overlapped */
bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size);
#ifdef __cplusplus
}
#endif
#endif /* #if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) */
#endif

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/**************************************************************************//**
* @file M2351.h
* @version V1.0
* @brief Peripheral Access Layer Header File
*
* @note
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
/**
\mainpage Introduction
*
*
* This user manual describes the usage of M2351 device driver
*
* <b>Disclaimer</b>
*
* The Software is furnished "AS IS", without warranty as to performance or results, and
* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
* warranties, express, implied or otherwise, with regard to the Software, its use, or
* operation, including without limitation any and all warranties of merchantability, fitness
* for a particular purpose, and non-infringement of intellectual property rights.
*
* <b>Copyright Notice</b>
*
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*/
#ifndef __M2351_H__
#define __M2351_H__
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup CMSIS_Device CMSIS Definitions
Configuration of the Cortex-M23 Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
/**
* @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M23 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M23 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M23 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M23 System Tick Interrupt */
/****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/
BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
IRC_IRQn = 1, /*!< Internal RC Interrupt */
PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
ISP_IRQn = 5, /*!< FMC ISP Interrupt */
RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */
WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */
EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */
SPI0_IRQn = 23, /*!< SPI0 Interrupt */
BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
EPWM0_P0_IRQn = 25, /*!< EPWM0P0 Interrupt */
EPWM0_P1_IRQn = 26, /*!< EPWM0P1 Interrupt */
EPWM0_P2_IRQn = 27, /*!< EPWM0P2 Interrupt */
BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
EPWM1_P0_IRQn = 29, /*!< EPWM1P0 Interrupt */
EPWM1_P1_IRQn = 30, /*!< EPWM1P1 Interrupt */
EPWM1_P2_IRQn = 31, /*!< EPWM1P2 Interrupt */
TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
UART0_IRQn = 36, /*!< UART 0 Interrupt */
UART1_IRQn = 37, /*!< UART 1 Interrupt */
I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */
DAC_IRQn = 41, /*!< DAC Interrupt */
EADC0_IRQn = 42, /*!< EADC Source 0 Interrupt */
EADC1_IRQn = 43, /*!< EADC Source 1 Interrupt */
ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
EADC2_IRQn = 46, /*!< EADC Source 2 Interrupt */
EADC3_IRQn = 47, /*!< EADC Source 3 Interrupt */
UART2_IRQn = 48, /*!< UART2 Interrupt */
UART3_IRQn = 49, /*!< UART3 Interrupt */
SPI1_IRQn = 51, /*!< SPI1 Interrupt */
SPI2_IRQn = 52, /*!< SPI2 Interrupt */
USBD_IRQn = 53, /*!< USB device Interrupt */
USBH_IRQn = 54, /*!< USB host Interrupt */
USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
CAN0_IRQn = 56, /*!< CAN0 Interrupt */
SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */
SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */
SPI3_IRQn = 62, /*!< SPI3 Interrupt */
SDH0_IRQn = 64, /*!< SDH0 Interrupt */
I2S0_IRQn = 68, /*!< I2S0 Interrupt */
CRPT_IRQn = 71, /*!< CRPT Interrupt */
GPG_IRQn = 72, /*!< GPIO Port G Interrupt */
EINT6_IRQn = 73, /*!< External Input 6 Interrupt */
UART4_IRQn = 74, /*!< UART4 Interrupt */
UART5_IRQn = 75, /*!< UART5 Interrupt */
USCI0_IRQn = 76, /*!< USCI0 Interrupt */
USCI1_IRQn = 77, /*!< USCI1 Interrupt */
BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */
BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */
I2C2_IRQn = 82, /*!< I2C2 Interrupt */
QEI0_IRQn = 84, /*!< QEI0 Interrupt */
QEI1_IRQn = 85, /*!< QEI1 Interrupt */
ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */
ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */
GPH_IRQn = 88, /*!< GPIO Port H Interrupt */
EINT7_IRQn = 89, /*!< External Input 7 Interrupt */
SPI5_IRQn = 96, /*!< SPI5 Interrupt */
DSRC_IRQn = 97, /*!< DSRC Interrupt */
PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */
SCU_IRQn = 99, /*!< SCU Interrupt */
TRNG_IRQn = 101 /*!< TRNG interrupt */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
#define __SAU_PRESENT 1U /* SAU present */
#define __SAUREGION_PRESENT 1U /* SAU present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define USE_ASSERT 0U /* Define to use Assert function or not */
/*@}*/ /* end of group CMSIS */
#include "core_armv8mbl.h" /* Processor and core peripherals */
#include "system_M2351.h" /* System Header */
/**
* Initialize the system clock
*
* @param none
* @return none
*
* @brief Setup the micro controller system
* Initialize the PLL and update the SystemFrequency variable
*/
extern void SystemInit(void);
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
#include "acmp_reg.h"
#include "bpwm_reg.h"
#include "can_reg.h"
#include "clk_reg.h"
#include "crc_reg.h"
#include "dac_reg.h"
#include "eadc_reg.h"
#include "ebi_reg.h"
#include "ecap_reg.h"
#include "fmc_reg.h"
#include "gpio_reg.h"
#include "hdiv_reg.h"
#include "i2c_reg.h"
#include "i2s_reg.h"
#include "pdma_reg.h"
#include "epwm_reg.h"
#include "qei_reg.h"
#include "rtc_reg.h"
#include "sc_reg.h"
#include "scu_reg.h"
#include "sdh_reg.h"
#include "qspi_reg.h"
#include "spi_reg.h"
#include "spi5_reg.h"
#include "sys_reg.h"
#include "timer_reg.h"
#include "trng_reg.h"
#include "uart_reg.h"
#include "ui2c_reg.h"
#include "usbh_reg.h"
#include "usbd_reg.h"
#include "otg_reg.h"
#include "crpt_reg.h"
#include "uspi_reg.h"
#include "uuart_reg.h"
#include "wdt_reg.h"
#include "wwdt_reg.h"
/**@}*/ /* end of REGISTER group */
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base
Memory Mapped Structure for Series Peripheral
@{
*/
/* Peripheral and SRAM base address */
#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
#define NS_OFFSET (0x10000000UL)
/* Peripheral memory map */
#define AHBPERIPH_BASE PERIPH_BASE
#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL)
/*!< AHB peripherals */
#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
#define INT_BASE (AHBPERIPH_BASE + 0x00300UL)
#define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL)
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL)
#define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL)
#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL)
#define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL)
/*!< APB peripherals */
#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
#define EADC0_BASE (APBPERIPH_BASE + 0x03000UL)
#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
#define I2S0_BASE (APBPERIPH_BASE + 0x08000UL)
#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
#define TMR01_BASE (APBPERIPH_BASE + 0x10000UL)
#define TMR23_BASE (APBPERIPH_BASE + 0x11000UL)
#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
#define SPI5_BASE (APBPERIPH_BASE + 0x25000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)
#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)
#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)
#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)
#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)
#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
#define DSRC_BASE (APBPERIPH_BASE + 0x77000UL)
#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
/**@}*/ /* PERIPHERAL */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/** @addtogroup PMODULE Peripheral Pointer
The Declaration of Peripheral Pointer
@{
*/
/** @addtogroup PMODULE_S Secure Peripheral Pointer
The Declaration of Secure Peripheral Pointer
@{
*/
#define PA ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */
#define PB ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */
#define PC ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */
#define PD ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */
#define PE ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */
#define PF ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */
#define PG ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */
#define PH ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */
#define UART0 ((UART_T *) UART0_BASE) /*!< UART0 Pointer */
#define UART1 ((UART_T *) UART1_BASE) /*!< UART1 Pointer */
#define UART2 ((UART_T *) UART2_BASE) /*!< UART2 Pointer */
#define UART3 ((UART_T *) UART3_BASE) /*!< UART3 Pointer */
#define UART4 ((UART_T *) UART4_BASE) /*!< UART4 Pointer */
#define UART5 ((UART_T *) UART5_BASE) /*!< UART5 Pointer */
#define TIMER0 ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */
#define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */
#define TIMER2 ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */
#define TIMER3 ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */
#define WDT ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */
#define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */
#define QSPI0 ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */
#define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */
#define SPI1 ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */
#define SPI2 ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */
#define SPI3 ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */
#define SPI5 ((SPI5_T *) SPI5_BASE) /*!< SPI5 Pointer */
#define I2S0 ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */
#define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */
#define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */
#define I2C2 ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */
#define QEI0 ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */
#define QEI1 ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */
#define RTC ((RTC_T *) RTC_BASE) /*!< RTC Pointer */
#define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */
#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */
#define DAC0 ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */
#define DAC1 ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */
#define EADC ((EADC_T *) EADC_BASE) /*!< EADC Pointer */
#define SYS ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */
#define SYSINT ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */
#define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */
#define SDH0 ((SDH_T *) SDH0_BASE)
#define CRPT ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */
#define TRNG ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */
#define BPWM0 ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */
#define BPWM1 ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */
#define EPWM0 ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */
#define EPWM1 ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */
#define SC0 ((SC_T *) SC0_BASE) /*!< SC0 Pointer */
#define SC1 ((SC_T *) SC1_BASE) /*!< SC1 Pointer */
#define SC2 ((SC_T *) SC2_BASE) /*!< SC2 Pointer */
#define EBI ((EBI_T *) EBI_BASE) /*!< EBI Pointer */
#define CRC ((CRC_T *) CRC_BASE) /*!< CRC Pointer */
#define USBD ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */
#define USBH ((USBH_T *) USBH_BASE) /*!< USBH Pointer */
#define OTG ((OTG_T *) OTG_BASE) /*!< OTG Pointer */
#define PDMA0 ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */
#define PDMA1 ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */
#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */
#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */
#define UI2C2 ((UI2C_T *) USCI2_BASE) /*!< UI2C2 Pointer */
#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */
#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */
#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */
#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */
#define SCU ((SCU_T *) SCU_BASE) /*!< SCU Pointer */
#define ECAP0 ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */
#define ECAP1 ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */
#define CAN0 ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */
/**@}*/ /* end of group PMODULE_S */
/** @addtogroup PMODULE_NS Non-secure Peripheral Pointer
The Declaration of Non-secure Peripheral Pointer
@{
*/
#define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */
#define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */
#define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */
#define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */
#define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */
#define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */
#define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */
#define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */
#define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */
#define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */
#define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */
#define UART3_NS ((UART_T *) (UART3_BASE+NS_OFFSET)) /*!< UART3 Pointer */
#define UART4_NS ((UART_T *) (UART4_BASE+NS_OFFSET)) /*!< UART4 Pointer */
#define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */
#define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */
#define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */
#define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */
#define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */
#define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */
#define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */
#define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */
#define SPI5_NS ((SPI5_T *) (SPI5_BASE+NS_OFFSET)) /*!< SPI5 Pointer */
#define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */
#define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */
#define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */
#define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */
#define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */
#define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */
#define RTC_NS ((RTC_T *) (RTC_BASE +NS_OFFSET)) /*!< RTC Pointer */
#define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */
#define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */
#define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */
#define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */
#define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET))
#define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET))
#define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */
#define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */
#define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */
#define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */
#define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */
#define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */
#define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */
#define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */
#define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */
#define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */
#define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */
#define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */
#define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */
#define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */
#define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */
#define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */
#define UI2C2_NS ((UI2C_T *) (USCI2_BASE +NS_OFFSET)) /*!< UI2C2 Pointer */
#define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */
#define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */
#define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */
#define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */
#define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */
#define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */
#define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */
#define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */
/**@}*/ /* end of group PMODULE_NS */
/**@}*/ /* end of group PMODULE */
/* -------------------- End of section using anonymous unions ------------------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
/*=============================================================================*/
typedef volatile unsigned char vu8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
#define M8(adr) (*((vu8 *) (adr)))
#define M16(adr) (*((vu16 *) (adr)))
#define M32(adr) (*((vu32 *) (adr)))
#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
#define inpw(port) ((*((volatile unsigned int *)(port))))
#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
#define inpb(port) ((*((volatile unsigned char *)(port))))
#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
#define inps(port) ((*((volatile unsigned short *)(port))))
#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
#define inp32(port) ((*((volatile unsigned int *)(port))))
#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
#define inp8(port) ((*((volatile unsigned char *)(port))))
#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
#define inp16(port) ((*((volatile unsigned short *)(port))))
#define E_SUCCESS 0
#define TRUE (1L)
#define FALSE (0L)
#define ENABLE 1
#define DISABLE 0
/* Bit Mask Definitions */
#define BIT0 0x00000001UL
#define BIT1 0x00000002UL
#define BIT2 0x00000004UL
#define BIT3 0x00000008UL
#define BIT4 0x00000010UL
#define BIT5 0x00000020UL
#define BIT6 0x00000040UL
#define BIT7 0x00000080UL
#define BIT8 0x00000100UL
#define BIT9 0x00000200UL
#define BIT10 0x00000400UL
#define BIT11 0x00000800UL
#define BIT12 0x00001000UL
#define BIT13 0x00002000UL
#define BIT14 0x00004000UL
#define BIT15 0x00008000UL
#define BIT16 0x00010000UL
#define BIT17 0x00020000UL
#define BIT18 0x00040000UL
#define BIT19 0x00080000UL
#define BIT20 0x00100000UL
#define BIT21 0x00200000UL
#define BIT22 0x00400000UL
#define BIT23 0x00800000UL
#define BIT24 0x01000000UL
#define BIT25 0x02000000UL
#define BIT26 0x04000000UL
#define BIT27 0x08000000UL
#define BIT28 0x10000000UL
#define BIT29 0x20000000UL
#define BIT30 0x40000000UL
#define BIT31 0x80000000UL
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FFUL)
#define BYTE1_Msk (0x0000FF00UL)
#define BYTE2_Msk (0x00FF0000UL)
#define BYTE3_Msk (0xFF000000UL)
#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
/******************************************************************************/
/* Peripheral header files */
/******************************************************************************/
#include "m2351_sys.h"
#include "m2351_clk.h"
#include "m2351_dac.h"
#include "m2351_eadc.h"
#include "m2351_ebi.h"
#include "m2351_ecap.h"
#include "m2351_fmc.h"
#include "m2351_gpio.h"
#include "m2351_i2c.h"
#include "m2351_i2s.h"
#include "m2351_bpwm.h"
#include "m2351_epwm.h"
#include "m2351_qspi.h"
#include "m2351_spi.h"
#include "m2351_spi5.h"
#include "m2351_timer.h"
#include "m2351_timer_pwm.h"
#include "m2351_wdt.h"
#include "m2351_wwdt.h"
#include "m2351_rtc.h"
#include "m2351_uart.h"
#include "m2351_acmp.h"
#include "m2351_crc.h"
#include "m2351_usbd.h"
#include "m2351_otg.h"
#include "m2351_pdma.h"
#include "m2351_ebi.h"
#include "m2351_crypto.h"
#include "m2351_sc.h"
#include "m2351_scuart.h"
#include "m2351_usci_spi.h"
#include "m2351_usci_uart.h"
#include "m2351_usci_i2c.h"
#include "m2351_sdh.h"
#include "m2351_qei.h"
#include "m2351_can.h"
#include "m2351_scu.h"
#include "m2351_bootloader.h"
#endif /* __M2351_H__ */
/* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. */

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#if defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
AREA |.text|, CODE, READONLY
__PC PROC
EXPORT __PC
#elif defined(__GNUC__)
.text
.thumb
.thumb_func
.globl __PC
.type __PC, %function
__PC:
#else ;; for IAR, __ICCARM__ seems not defined in IAR asm
MODULE nvtfunc
SECTION .text:CODE:REORDER:NOROOT(1)
THUMB
PUBLIC __PC
__PC
#endif
MOV r0, lr
BLX lr
#if defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
ALIGN
ENDP
END
#elif defined(__GNUC__)
.align
.pool
.size __PC, . - __PC
.end
#else ;; for IAR, __ICCARM__ seems not defined in IAR asm
END
#endif

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/**************************************************************************//**
* @file NuMicro.h
* @version V1.00
* @brief NuMicro peripheral access layer header file.
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "M2351.h"
#endif /* __NUMICRO_H__ */
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file acmp_reg.h
* @version V1.00
* @brief ACMP register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ACMP_REG_H__
#define __ACMP_REG_H__
/*---------------------- Analog Comparator Controller -------------------------*/
/**
@addtogroup ACMP Analog Comparator Controller(ACMP)
Memory Mapped Structure for ACMP Controller
@{ */
typedef struct
{
/**
* @var ACMP_T::CTL
* Offset: 0x00 Analog Comparator 0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPEN |Comparator Enable Bit
* | | |0 = Comparator 0 Disabled.
* | | |1 = Comparator 0 Enabled.
* | | |
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
* | | |0 = Comparator 0 interrupt Disabled.
* | | |1 = Comparator 0 interrupt Enabled
* | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
* | | |
* |[2] |HYSEN |Comparator Hysteresis Enable Bit
* | | |0 = Comparator 0 hysteresis Disabled.
* | | |1 = Comparator 0 hysteresis Enabled.
* | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL.
* | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysteresis is fixed to 30mV.
* |[3] |ACMPOINV |Comparator Output Inverse
* | | |0 = Comparator 0 output inverse Disabled.
* | | |1 = Comparator 0 output inverse Enabled.
* | | |
* |[5:4] |NEGSEL |Comparator Negative Input Selection
* | | |00 = ACMP0_N pin.
* | | |01 = Internal comparator reference voltage (CRV).
* | | |10 = Band-gap voltage.
* | | |11 = DAC output.
* | | |
* |[7:6] |POSSEL |Comparator Positive Input Selection
* | | |00 = Input from ACMP0_P0.
* | | |01 = Input from ACMP0_P1.
* | | |10 = Input from ACMP0_P2.
* | | |11 = Input from ACMP0_P3.
* | | |
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
* | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
* | | |00 = Rising edge or falling edge.
* | | |01 = Rising edge.
* | | |10 = Falling edge.
* | | |11 = Reserved.
* | | |
* |[12] |OUTSEL |Comparator Output Select
* | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
* | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
* | | |
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
* | | |000 = Filter function is Disabled.
* | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
* | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
* | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
* | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
* | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
* | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
* | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
* | | |
* |[16] |WKEN |Power-down Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* | | |
* |[17] |WLATEN |Window Latch Mode Enable Bit
* | | |0 = Window Latch Mode Disabled.
* | | |1 = Window Latch Mode Enabled.
* | | |
* |[18] |WCMPSEL |Window Compare Mode Selection
* | | |0 = Window Compare Mode Disabled.
* | | |1 = Window Compare Mode is Selected.
* | | |
* |[25:24] |HYSSEL |Hysteresis Mode Selection
* | | |00 = Hysteresis is 0mV.
* | | |01 = Hysteresis is 10mV.
* | | |10 = Hysteresis is 20mV.
* | | |11 = Hysteresis is 30mV.
* | | |
* |[29:28] |MODESEL |Propagation Delay Mode Selection
* | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
* | | |01 = Max propagation delay is 2uS, operation current is 3uA.
* | | |10 = Max propagation delay is 600nS, operation current is 10uA.
* | | |11 = Max propagation delay is 200nS, operation current is 75uA.
* | | |
* @var ACMP_T::STATUS
* Offset: 0x08 Analog Comparator Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output
* | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* | | |
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* | | |
* |[4] |ACMPO0 |Comparator 0 Output
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* | | |
* |[5] |ACMPO1 |Comparator 1 Output
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* | | |
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* | | |
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* | | |
* |[12] |ACMPS0 |Comparator 0 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[13] |ACMPS1 |Comparator 1 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[16] |ACMPWO |Comparator Window Output
* | | |This bit shows the output status of window compare mode
* | | |0 = The positive input voltage is outside the window.
* | | |1 = The positive input voltage is in the window.
* | | |
* @var ACMP_T::VREF
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
* | | |
* |[6] |CRVSSEL |CRV Source Voltage Selection
* | | |0 = VDDA is selected as CRV source voltage.
* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
* | | |
*/
__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0~1 Control Register */
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
} ACMP_T;
/**
@addtogroup ACMP_CONST ACMP Bit Field Definition
Constant Definitions for ACMP Controller
@{ */
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */
#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */
#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */
#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
/**@}*/ /* ACMP_CONST */
/**@}*/ /* end of ACMP register group */
#endif /* __ACMP_REG_H__ */

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/**************************************************************************//**
* @file can_reg.h
* @version V1.00
* @brief CAN register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CAN_REG_H__
#define __CAN_REG_H__
/*---------------------- Controller Area Network Controller -------------------------*/
/**
@addtogroup CAN Controller Area Network Controller(CAN)
Memory Mapped Structure for CAN Controller
@{ */
typedef struct
{
/**
* @var CAN_IF_T::CREQ
* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |MessageNumber|Message Number
* | | |0x01-0x20: Valid Message Number, the Message Object in the Message
* | | |RAM is selected for data transfer.
* | | |0x00: Not a valid Message Number, interpreted as 0x20.
* | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
* |[15] |Busy |Busy Flag
* | | |0 = Read/write action has finished.
* | | |1 = Writing to the IFn Command Request Register is in progress.
* | | |This bit can only be read by the software.
* @var CAN_IF_T::CMASK
* Offset: 0x24, 0x84 IFn Command Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DAT_B |Access Data Bytes [7:4]
* | | |Write Operation:
* | | |0 = Data Bytes [7:4] unchanged.
* | | |1 = Transfer Data Bytes [7:4] to Message Object.
* | | |Read Operation:
* | | |0 = Data Bytes [7:4] unchanged.
* | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
* |[1] |DAT_A |Access Data Bytes [3:0]
* | | |Write Operation:
* | | |0 = Data Bytes [3:0] unchanged.
* | | |1 = Transfer Data Bytes [3:0] to Message Object.
* | | |Read Operation:
* | | |0 = Data Bytes [3:0] unchanged.
* | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
* |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
* | | |0 = TxRqst bit unchanged.
* | | |1 = Set TxRqst bit.
* | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
* | | |Access New Data Bit when Read Operation.
* | | |0 = NewDat bit remains unchanged.
* | | |1 = Clear NewDat bit in the Message Object.
* | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
* | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
* |[3] |ClrIntPnd |Clear Interrupt Pending Bit
* | | |Write Operation:
* | | |When writing to a Message Object, this bit is ignored.
* | | |Read Operation:
* | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
* | | |1 = Clear IntPnd bit in the Message Object.
* |[4] |Control |Control Access Control Bits
* | | |Write Operation:
* | | |0 = Control Bits unchanged.
* | | |1 = Transfer Control Bits to Message Object.
* | | |Read Operation:
* | | |0 = Control Bits unchanged.
* | | |1 = Transfer Control Bits to IFn Message Buffer Register.
* |[5] |Arb |Access Arbitration Bits
* | | |Write Operation:
* | | |0 = Arbitration bits unchanged.
* | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
* | | |Read Operation:
* | | |0 = Arbitration bits unchanged.
* | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
* |[6] |Mask |Access Mask Bits
* | | |Write Operation:
* | | |0 = Mask bits unchanged.
* | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
* | | |Read Operation:
* | | |0 = Mask bits unchanged.
* | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
* |[7] |WR_RD |Write / Read Mode
* | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
* | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
* @var CAN_IF_T::MASK1
* Offset: 0x28, 0x88 IFn Mask 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |Msk[15:0] |Identifier Mask 15-0
* | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
* | | |1 = The corresponding identifier bit is used for acceptance filtering.
* @var CAN_IF_T::MASK2
* Offset: 0x2C, 0x8C IFn Mask 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |Msk[28:16]|Identifier Mask 28-16
* | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
* | | |1 = The corresponding identifier bit is used for acceptance filtering.
* |[14] |MDir |Mask Message Direction
* | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
* | | |1 = The message direction bit (Dir) is used for acceptance filtering.
* |[15] |MXtd |Mask Extended Identifier
* | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
* | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
* | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
* | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
* @var CAN_IF_T::ARB1
* Offset: 0x30, 0x90 IFn Arbitration 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ID[15:0] |Message Identifier 15-0
* | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
* | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
* @var CAN_IF_T::ARB2
* Offset: 0x34, 0x94 IFn Arbitration 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |ID[28:16] |Message Identifier 28-16
* | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
* | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
* |[13] |Dir |Message Direction
* | | |0 = Direction is receive.
* | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
* | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
* | | |1 = Direction is transmit.
* | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
* | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
* |[14] |Xtd |Extended Identifier
* | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
* | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
* |[15] |MsgVal |Message Valid
* | | |0 = The Message Object is ignored by the Message Handler.
* | | |1 = The Message Object is configured and should be considered by the Message Handler.
* | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
* | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
* @var CAN_IF_T::MCON
* Offset: 0x38, 0x98 IFn Message Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DLC |Data Length Code
* | | |0-8: Data Frame has 0-8 data bytes.
* | | |9-15: Data Frame has 8 data bytes
* | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
* | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
* | | |Data 0: 1st data byte of a CAN Data Frame
* | | |Data 1: 2nd data byte of a CAN Data Frame
* | | |Data 2: 3rd data byte of a CAN Data Frame
* | | |Data 3: 4th data byte of a CAN Data Frame
* | | |Data 4: 5th data byte of a CAN Data Frame
* | | |Data 5: 6th data byte of a CAN Data Frame
* | | |Data 6: 7th data byte of a CAN Data Frame
* | | |Data 7 : 8th data byte of a CAN Data Frame
* | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
* | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
* | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
* |[7] |EoB |End Of Buffer
* | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
* | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
* | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
* | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
* |[8] |TxRqst |Transmit Request
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* |[9] |RmtEn |Remote Enable Control
* | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
* | | |1 = At the reception of a Remote Frame, TxRqst is set.
* |[10] |RxIE |Receive Interrupt Enable Control
* | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
* | | |1 = IntPnd will be set after a successful reception of a frame.
* |[11] |TxIE |Transmit Interrupt Enable Control
* | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
* | | |1 = IntPnd will be set after a successful transmission of a frame.
* |[12] |UMask |Use Acceptance Mask
* | | |0 = Mask ignored.
* | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
* | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
* |[13] |IntPnd |Interrupt Pending
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
* |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
* | | |0 = No message lost since last time this bit was reset by the CPU.
* | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
* |[15] |NewDat |New Data
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_IF_T::DAT_A1
* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data0 |Data Byte 0
* | | |1st data byte of a CAN Data Frame
* |[15:8] |Data1 |Data Byte 1
* | | |2nd data byte of a CAN Data Frame
* @var CAN_IF_T::DAT_A2
* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data2 |Data Byte 2
* | | |3rd data byte of CAN Data Frame
* |[15:8] |Data3 |Data Byte 3
* | | |4th data byte of CAN Data Frame
* @var CAN_IF_T::DAT_B1
* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data4 |Data Byte 4
* | | |5th data byte of CAN Data Frame
* |[15:8] |Data5 |Data Byte 5
* | | |6th data byte of CAN Data Frame
* @var CAN_IF_T::DAT_B2
* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data6 |Data Byte 6
* | | |7th data byte of CAN Data Frame.
* |[15:8] |Data7 |Data Byte 7
* | | |8th data byte of CAN Data Frame.
*/
__IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
__IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
__IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
__IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
__IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
__IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
__IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
__IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
__IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
__IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
__IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
__I uint32_t RESERVE0[13];
} CAN_IF_T;
typedef struct
{
/**
* @var CAN_T::CON
* Offset: 0x00 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |Init |Init Initialization
* | | |0 = Normal Operation.
* | | |1 = Initialization is started.
* |[1] |IE |Module Interrupt Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[2] |SIE |Status Change Interrupt Enable Control
* | | |0 = Disabled - No Status Change Interrupt will be generated.
* | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
* |[3] |EIE |Error Interrupt Enable Control
* | | |0 = Disabled - No Error Status Interrupt will be generated.
* | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
* |[5] |DAR |Automatic Re-Transmission Disable Control
* | | |0 = Automatic Retransmission of disturbed messages enabled.
* | | |1 = Automatic Retransmission disabled.
* |[6] |CCE |Configuration Change Enable Control
* | | |0 = No write access to the Bit Timing Register.
* | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
* |[7] |Test |Test Mode Enable Control
* | | |0 = Normal Operation.
* | | |1 = Test Mode.
* @var CAN_T::STATUS
* Offset: 0x04 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
* | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
* | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
* | | |The unused code '7' may be written by the CPU to check for updates.
* | | |The following table describes the error code.
* |[3] |TxOK |Transmitted A Message Successfully
* | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
* | | |This bit is never reset by the CAN Core.
* | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
* |[4] |RxOK |Received A Message Successfully
* | | |0 = No message has been successfully received since this bit was last reset by the CPU.
* | | |This bit is never reset by the CAN Core.
* | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
* |[5] |EPass |Error Passive (Read Only)
* | | |0 = The CAN Core is error active.
* | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
* |[6] |EWarn |Error Warning Status (Read Only)
* | | |0 = Both error counters are below the error warning limit of 96.
* | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
* |[7] |BOff |Bus-Off Status (Read Only)
* | | |0 = The CAN module is not in bus-off state.
* | | |1 = The CAN module is in bus-off state.
* @var CAN_T::ERR
* Offset: 0x08 Error Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TEC |Transmit Error Counter
* | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
* |[14:8] |REC |Receive Error Counter
* | | |Actual state of the Receive Error Counter. Values between 0 and 127.
* |[15] |RP |Receive Error Passive
* | | |0 = The Receive Error Counter is below the error passive level.
* | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
* @var CAN_T::BTIME
* Offset: 0x0C Bit Timing Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |BRP |Baud Rate Prescaler
* | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
* | | |The bit time is built up from a multiple of this quanta.
* | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* |[7:6] |SJW |(Re)Synchronization Jump Width
* | | |0x0-0x3: Valid programmed values are [0 ... 3].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
* | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
* |[14:12] |TSeg2 |Time Segment After Sample Point
* | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* @var CAN_T::IIDR
* Offset: 0x10 Interrupt Identifier Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
* | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
* | | |An interrupt remains pending until the application software has cleared it.
* | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
* | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
* | | |The Status Interrupt has the highest priority.
* | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
* | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
* | | |The Status Interrupt is cleared by reading the Status Register.
* @var CAN_T::TEST
* Offset: 0x14 Test Register (Register Map Note 1)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |Res |Reserved
* | | |There are reserved bits.
* | | |These bits are always read as '0' and must always be written with '0'.
* |[2] |Basic |Basic Mode
* | | |0 = Basic Mode disabled.
* | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
* |[3] |Silent |Silent Mode
* | | |0 = Normal operation.
* | | |1 = The module is in Silent Mode.
* |[4] |LBack |Loop Back Mode Enable Control
* | | |0 = Loop Back Mode is disabled.
* | | |1 = Loop Back Mode is enabled.
* |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
* | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
* | | |01 = Sample Point can be monitored at CAN_TX pin.
* | | |10 = CAN_TX pin drives a dominant ('0') value.
* | | |11 = CAN_TX pin drives a recessive ('1') value.
* |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
* | | |0 = The CAN bus is dominant (CAN_RX = '0').
* | | |1 = The CAN bus is recessive (CAN_RX = '1').
* @var CAN_T::BRPE
* Offset: 0x18 Baud Rate Prescaler Extension Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
* | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
* | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
* @var CAN_T::IF
* Offset: 0x20~0xFC CAN Interface Registers
* ---------------------------------------------------------------------------------------------------
* CAN interface structure. Refer to \ref CAN_IF_T for detail information.
*
* @var CAN_T::TXREQ1
* Offset: 0x100 Transmission Request Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* | | |These bits are read only.
* @var CAN_T::TXREQ2
* Offset: 0x104 Transmission Request Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* | | |These bits are read only.
* @var CAN_T::NDAT1
* Offset: 0x120 New Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_T::NDAT2
* Offset: 0x124 New Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_T::IPND1
* Offset: 0x140 Interrupt Pending Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* @var CAN_T::IPND2
* Offset: 0x144 Interrupt Pending Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* @var CAN_T::MVLD1
* Offset: 0x160 Message Valid Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
* | | |0 = This Message Object is ignored by the Message Handler.
* | | |1 = This Message Object is configured and should be considered by the Message Handler.
* | | |Ex.
* | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
* | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
* @var CAN_T::MVLD2
* Offset: 0x164 Message Valid Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
* | | |0 = This Message Object is ignored by the Message Handler.
* | | |1 = This Message Object is configured and should be considered by the Message Handler.
* | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
* | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
* @var CAN_T::WU_EN
* Offset: 0x168 Wake-up Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WAKUP_EN |Wake-Up Enable Control
* | | |0 = The wake-up function Disabled.
* | | |1 = The wake-up function Enabled.
* | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
* @var CAN_T::WU_STATUS
* Offset: 0x16C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WAKUP_STS |Wake-Up Status
* | | |0 = No wake-up event occurred.
* | | |1 = Wake-up event occurred.
* | | |Note: This bit can be cleared by writing '0'.
*/
__IO uint32_t CON; /* Offset: 0x00 Control Register */
__IO uint32_t STATUS; /* Offset: 0x04 Status Register */
__I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
__IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
__I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
__IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
__IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
__I uint32_t RESERVE0[1];
__IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
__I uint32_t RESERVE1[8];
__I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
__I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
__I uint32_t RESERVE3[6];
__I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
__I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
__I uint32_t RESERVE4[6];
__I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
__I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
__I uint32_t RESERVE5[6];
__I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
__I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
__IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
__IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
} CAN_T;
/**
@addtogroup CAN_CONST CAN Bit Field Definition
Constant Definitions for CAN Controller
@{ */
/* CAN CON Bit Field Definitions */
#define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
#define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
#define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
#define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
#define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
#define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
#define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
/* CAN STATUS Bit Field Definitions */
#define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
#define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
#define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
#define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
#define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
#define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
/* CAN ERR Bit Field Definitions */
#define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
#define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
#define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
/* CAN BTIME Bit Field Definitions */
#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
#define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
#define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
/* CAN IIDR Bit Field Definitions */
#define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
/* CAN TEST Bit Field Definitions */
#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
#define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
/* CAN BPRE Bit Field Definitions */
#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
/* CAN IFn_CREQ Bit Field Definitions */
#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
/* CAN IFn_CMASK Bit Field Definitions */
#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
/* CAN IFn_MASK1 Bit Field Definitions */
#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
/* CAN IFn_MASK2 Bit Field Definitions */
#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
/* CAN IFn_ARB1 Bit Field Definitions */
#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
/* CAN IFn_ARB2 Bit Field Definitions */
#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
/* CAN IFn_MCON Bit Field Definitions */
#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
#define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
#define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
#define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
#define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
/* CAN IFn_DATA_A1 Bit Field Definitions */
#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
/* CAN IFn_DATA_A2 Bit Field Definitions */
#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
/* CAN IFn_DATA_B1 Bit Field Definitions */
#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
/* CAN IFn_DATA_B2 Bit Field Definitions */
#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
/* CAN IFn_TXRQST1 Bit Field Definitions */
#define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
#define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
/* CAN IFn_TXRQST2 Bit Field Definitions */
#define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
#define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
/* CAN IFn_NDAT1 Bit Field Definitions */
#define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
#define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
/* CAN IFn_NDAT2 Bit Field Definitions */
#define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
#define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
/* CAN IFn_IPND1 Bit Field Definitions */
#define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
#define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
/* CAN IFn_IPND2 Bit Field Definitions */
#define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
#define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
/* CAN IFn_MVLD1 Bit Field Definitions */
#define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
#define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
/* CAN IFn_MVLD2 Bit Field Definitions */
#define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
#define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
/* CAN WUEN Bit Field Definitions */
#define CAN_WU_EN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
/* CAN WUSTATUS Bit Field Definitions */
#define CAN_WU_STATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
/**@}*/ /* CAN_CONST */
/**@}*/ /* end of CAN register group */
#endif /* __CAN_REG_H__ */

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/**************************************************************************//**
* @file crc_reg.h
* @version V1.00
* @brief CRC register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRC_REG_H__
#define __CRC_REG_H__
/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
/**
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
Memory Mapped Structure for CRC Controller
@{ */
typedef struct
{
/**
* @var CRC_T::CTL
* Offset: 0x00 CRC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRCEN |CRC Channel Generator Enable Bit
* | | |Set this bit 1 to enable CRC generator for CRC operation.
* | | |0 = No effect.
* | | |1 = CRC operation generator is active.
* |[1] |CHKSINIT |Checksum Initialization
* | | |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.
* | | |0 = No effect.
* | | |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value.
* | | |The others contents of CRC_CTL register will not be cleared.
* | | |Note1: This bit will be cleared automatically
* | | |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value.
* |[24] |DATREV |Write Data Bit Order Reverse Enable Bit
* | | |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register.
* | | |0 = Bit order reversed for CRC_DATA write data in Disabled.
* | | |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte).
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
* |[25] |CHKSREV |Checksum Bit Order Reverse Enable Bit
* | | |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
* | | |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled.
* | | |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled.
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
* |[26] |DATFMT |Write Data 1's Complement Enable Bit
* | | |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).
* | | |0 = 1's complement for CRC_DATA writes data in Disabled.
* | | |1 = 1's complement for CRC_DATA writes data in Enabled.
* |[27] |CHKSFMT |Checksum 1's Complement Enable Bit
* | | |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register.
* | | |0 = 1's complement for CRC CHECKSUM Disabled.
* | | |1 = 1's complement for CRC CHECKSUMCRC Enabled.
* |[29:28] |DATLEN |CPU Write Data Length
* | | |This field indicates the valid write data length of DATA (CRC_DAT[31:0]).
* | | |00 = Data length is 8-bit mode.
* | | |01 = Data length is 16-bit mode.
* | | |1x = Data length is 32-bit mode.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
* |[31:30] |CRCMODE |CRC Polynomial Mode
* | | |This field indicates the CRC operation polynomial mode.
* | | |00 = CRC-CCITT Polynomial mode.
* | | |01 = CRC-8 Polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |11 = CRC-32 Polynomial mode.
* @var CRC_T::DAT
* Offset: 0x04 CRC Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |CRC Write Data Bits
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* @var CRC_T::SEED
* Offset: 0x08 CRC Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |CRC Seed Value
* | | |This field indicates the CRC seed value.
* | | |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1.
* | | |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
* @var CRC_T::CHECKSUM
* Offset: 0x0C CRC Checksum Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CHECKSUM |CRC Checksum Results
* | | |This field indicates the CRC checksum result.
* | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
*/
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
} CRC_T;
/**
@addtogroup CRC_CONST CRC Bit Field Definition
Constant Definitions for CRC Controller
@{ */
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
/**@}*/ /* CRC_CONST */
/**@}*/ /* end of CRC register group */
#endif /* __CLK_REG_H__ */

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/**************************************************************************//**
* @file dac_reg.h
* @version V1.00
* @brief DAC register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __DAC_REG_H__
#define __DAC_REG_H__
/*---------------------- Digital to Analog Converter -------------------------*/
/**
@addtogroup DAC Digital to Analog Converter(DAC)
Memory Mapped Structure for DAC Controller
@{ */
typedef struct
{
/**
* @var DAC_T::CTL
* Offset: 0x00 DAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DACEN |DAC Enable Bit
* | | |0 = DAC is Disabled.
* | | |1 = DAC is Enabled.
* |[1] |DACIEN |DAC Interrupt Enable Bit
* | | |0 = Interrupt is Disabled.
* | | |1 = Interrupt is Enabled.
* |[2] |DMAEN |DMA Mode Enable Bit
* | | |0 = DMA mode Disabled.
* | | |1 = DMA mode Enabled.
* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
* | | |0 = DMA under-run interrupt Disabled.
* | | |1 = DMA under-run interrupt Enabled.
* |[4] |TRGEN |Trigger Mode Enable Bit
* | | |0 = DAC event trigger mode Disabled.
* | | |1 = DAC event trigger mode Enabled.
* |[7:5] |TRGSEL |Trigger Source Selection
* | | |000 = Software trigger.
* | | |001 = External pin DAC0_ST trigger.
* | | |010 = Timer 0 trigger.
* | | |011 = Timer 1 trigger.
* | | |100 = Timer 2 trigger.
* | | |101 = Timer 3 trigger.
* | | |110 = EPWM0 trigger.
* | | |111 = EPWM1 trigger.
* |[8] |BYPASS |Bypass Buffer Mode
* | | |0 = Output voltage buffer Enabled.
* | | |1 = Output voltage buffer Disabled.
* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
* | | |0 = Right alignment.
* | | |1 = Left alignment.
* |[13:12] |ETRGSEL |External Pin Trigger Selection
* | | |00 = Low level trigger.
* | | |01 = High level trigger.
* | | |10 = Falling edge trigger.
* | | |11 = Rising edge trigger.
* |[15:14] |BWSEL |DAC Data Bit-width Selection
* | | |00 = data is 12 bits.
* | | |01 = data is 8 bits.
* | | |Others = reserved.
* |[16] |GRPEN |DAC Group Mode Enable Bit
* | | |0 = DAC0 and DAC1 are not grouped.
* | | |1 = DAC0 and DAC1 are grouped.
* @var DAC_T::SWTRG
* Offset: 0x04 DAC Software Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWTRG |Software Trigger
* | | |0 = Software trigger Disabled.
* | | |1 = Software trigger Enabled.
* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
* @var DAC_T::DAT
* Offset: 0x08 DAC Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DACDAT |DAC 12-bit Holding Data
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
* | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits.
* @var DAC_T::DATOUT
* Offset: 0x0C DAC Data Output Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DATOUT |DAC 12-bit Output Data
* | | |These bits are current digital data for DAC output conversion.
* | | |It is loaded from DAC_DAT register and user cannot write it directly.
* @var DAC_T::STATUS
* Offset: 0x10 DAC Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |DAC Conversion Complete Finish Flag
* | | |0 = DAC is in conversion state.
* | | |1 = DAC conversion finish.
* | | |This bit set to 1 when conversion time counter counts to SETTLET.
* | | |It is cleared to 0 when DAC starts a new conversion.
* | | |User writes 1 to clear this bit to 0.
* |[1] |DMAUDR |DMA Under-run Interrupt Flag
* | | |0 = No DMA under-run error condition occurred.
* | | |1 = DMA under-run error condition occurred.
* | | |User writes 1 to clear this bit.
* |[8] |BUSY |DAC Busy Flag (Read Only)
* | | |0 = DAC is ready for next conversion.
* | | |1 = DAC is busy in conversion.
* | | |This is read only bit.
* @var DAC_T::TCTL
* Offset: 0x14 DAC Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |SETTLET |DAC Output Settling Time
* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
* | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40.
*/
__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
} DAC_T;
/**
@addtogroup DAC_CONST DAC Bit Field Definition
Constant Definitions for DAC Controller
@{ */
#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
/**@}*/ /* DAC_CONST */
/**@}*/ /* end of DAC register group */
#endif /* __DAC_REG_H__ */

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/**************************************************************************//**
* @file ebi_reg.h
* @version V1.00
* @brief EBI register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_REG_H__
#define __EBI_REG_H__
/*---------------------- External Bus Interface Controller -------------------------*/
/**
@addtogroup EBI External Bus Interface Controller(EBI)
Memory Mapped Structure for EBI Controller
@{ */
typedef struct
{
/**
* @var EBI_T::CTL
* Offset: 0x00 External Bus Interface Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
* | | |0 = Address/Data Bus Separating Mode Disabled.
* | | |1 = Address/Data Bus Separating Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* @var EBI_T::TCTL
* Offset: 0x04 External Bus Interface Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC define data access time (tACC).
* | | |tACC = (TACC+1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD define data access hold time (tAHD).
* | | |tAHD = (TAHD+1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
*/
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{ */
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
#endif /* __EBI_REG_H__ */

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/**************************************************************************//**
* @file ecap_reg.h
* @version V1.00
* @brief ECAP register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ECAP_REG_H__
#define __ECAP_REG_H__
/*---------------------- Enhanced Input Capture Timer -------------------------*/
/**
@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
Memory Mapped Structure for ECAP Controller
@{ */
typedef struct
{
/**
* @var ECAP_T::CNT
* Offset: 0x00 Input Capture Counter (24-bit up counter)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Input Capture Timer/Counter
* | | |The input Capture Timer/Counter is a 24-bit up-counting counter
* | | |The clock source for the counter is from the clock divider
* @var ECAP_T::HLD0
* Offset: 0x04 Input Capture Hold Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD1
* Offset: 0x08 Input Capture Hold Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD2
* Offset: 0x0C Input Capture Hold Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::CNTCMP
* Offset: 0x10 Input Capture Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNTCMP |Input Capture Counter Compare Register
* | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
* | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
* @var ECAP_T::CTL0
* Offset: 0x14 Input Capture Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock
* | | |000 = CAP_CLK.
* | | |001 = CAP_CLK/2.
* | | |010 = CAP_CLK/4.
* | | |011 = CAP_CLK/16.
* | | |100 = CAP_CLK/32.
* | | |101 = CAP_CLK/64.
* |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
* | | |0 = Noise filter of Input Capture Enabled.
* | | |1 = Noise filter of Input Capture Disabled (Bypass).
* |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
* | | |0 = IC0 input to Input Capture Unit Disabled.
* | | |1 = IC0 input to Input Capture Unit Enabled.
* |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
* | | |0 = IC1 input to Input Capture Unit Disabled.
* | | |1 = IC1 input to Input Capture Unit Enabled.
* |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
* | | |0 = IC2 input to Input Capture Unit Disabled.
* | | |1 = IC2 input to Input Capture Unit Enabled.
* |[9:8] |CAPSEL0 |CAP0 Input Source Selection
* | | |00 = CAP0 input is from port pin ICAP0.
* | | |01 = Reserved.
* | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[11:10] |CAPSEL1 |CAP1 Input Source Selection
* | | |00 = CAP1 input is from port pin ICAP1.
* | | |01 = Reserved.
* | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[13:12] |CAPSEL2 |CAP2 Input Source Selection
* | | |00 = CAP2 input is from port pin ICAP2.
* | | |01 = Reserved.
* | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
* | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
* |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
* | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
* |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
* | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
* |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
* |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
* |[24] |CNTEN |Input Capture Counter Start Counting Control
* | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
* | | |0 = ECAP_CNT stop counting.
* | | |1 = ECAP_CNT starts up-counting.
* |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
* | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
* | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
* |[28] |CMPEN |Compare Function Enable Control
* | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
* | | |0 = The compare function Disabled.
* | | |1 = The compare function Enabled.
* |[29] |CAPEN |Input Capture Timer/Counter Enable Control
* | | |0 = Input Capture function Disabled.
* | | |1 = Input Capture function Enabled.
* @var ECAP_T::CTL1
* Offset: 0x18 Input Capture Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
* | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
* | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
* | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
* | | |0 = The reload triggered by Event CAPTE0 Disabled.
* | | |1 = The reload triggered by Event CAPTE0 Enabled.
* |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
* | | |0 = The reload triggered by Event CAPTE1 Disabled.
* | | |1 = The reload triggered by Event CAPTE1 Enabled.
* |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
* | | |0 = The reload triggered by Event CAPTE2 Disabled.
* | | |1 = The reload triggered by Event CAPTE2 Enabled.
* |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
* | | |0 = The reload triggered by CAPOV Disabled.
* | | |1 = The reload triggered by CAPOV Enabled.
* |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
* | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
* | | |000 = CAP_CLK/1.
* | | |001 = CAP_CLK/4.
* | | |010 = CAP_CLK/16.
* | | |011 = CAP_CLK/32.
* | | |100 = CAP_CLK/64.
* | | |101 = CAP_CLK/96.
* | | |110 = CAP_CLK/112.
* | | |111 = CAP_CLK/128.
* |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
* | | |Select the capture timer/counter clock source.
* | | |00 = CAP_CLK (default).
* | | |01 = CAP0.
* | | |10 = CAP1.
* | | |11 = CAP2.
* |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
* | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
* |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
* | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
* |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
* | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
* @var ECAP_T::STATUS
* Offset: 0x1C Input Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
* | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
* | | |0 = No valid edge change has been detected at CAP0 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
* | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
* | | |0 = No valid edge change has been detected at CAP1 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
* | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
* | | |0 = No valid edge change has been detected at CAP2 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[4] |CAPCMPF |Input Capture Compare-match Flag
* | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
* | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
* | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[5] |CAPOVF |Input Capture Counter Overflow Flag
* | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
* | | |0 = No overflow event has occurred since last clear.
* | | |1 = Overflow event(s) has/have occurred since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
* | | |Reflecting the value of input channel 0, CAP0
* | | |(The bit is read only and write is ignored)
* |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
* | | |Reflecting the value of input channel 1, CAP1
* | | |(The bit is read only and write is ignored)
* |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
* | | |Reflecting the value of input channel 2, CAP2.
* | | |(The bit is read only and write is ignored)
*/
__IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
__IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
__IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
__IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
__IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
__IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
__IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
} ECAP_T;
/**
@addtogroup ECAP_CONST ECAP Bit Field Definition
Constant Definitions for ECAP Controller
@{ */
#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
/**@}*/ /* ECAP_CONST */
/**@}*/ /* end of ECAP register group */
#endif /* __ECAP_REG_H__ */

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/**************************************************************************//**
* @file fmc_reg.h
* @version V1.00
* @brief FMC register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __FMC_REG_H__
#define __FMC_REG_H__
/*---------------------- Flash Memory Controller -------------------------*/
/**
@addtogroup FMC Flash Memory Controller(FMC)
Memory Mapped Structure for FMC Controller
@{ */
typedef struct
{
/**
* @var FMC_T::ISPCTL
* Offset: 0x00 ISP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPEN |ISP Enable Bit (Write Protect)
* | | |ISP function enable bit. Set this bit to enable ISP function.
* | | |0 = ISP function Disabled.
* | | |1 = ISP function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |BS |Boot Select (Write Protect)
* | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
* | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
* | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |APUEN |APROM Update Enable Bit (Write Protect)
* | | |0 = APROM cannot be updated when the chip runs in APROM.
* | | |1 = APROM can be updated when the chip runs in APROM.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
* | | |0 = CONFIG cannot be updated.
* | | |1 = CONFIG can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
* | | |LDROM update enable bit.
* | | |0 = LDROM cannot be updated.
* | | |1 = LDROM can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |This bit needs to be cleared by writing 1 to it.
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(9) APROM is erased/programmed if KEYLOCK is set to 1
* | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0
* | | |(12) Read any content of boot loader with ICE connection
* | | |(13) The address of block erase and bank erase is not in APROM
* | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
* | | |(15) The wrong setting of page erase ISP CMD in XOM
* | | |(16) Violate XOM setting one time protection
* | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page
* | | |(18) Mass erase when MERASE (CFG0[13]) is disable
* | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[16] |BL |Boot Loader Booting (Write Protect)
* | | |This bit is initiated with the inverses value of MBS (CONFIG0[5])
* | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
* | | |This bit is used to check chip boot from Boot Loader or not
* | | |User should keep original value of this bit when updating FMC_ISPCTL register.
* | | |0 = Booting from APROM or LDROM.
* | | |1 = Booting from Boot Loader.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[24] |INTEN |Interrupt Enable (Write Protect)
* | | |0 = ISP INT Disabled.
* | | |1 = ISP INT Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
* @var FMC_T::ISPADDR
* Offset: 0x04 ISP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPADDR |ISP Address
* | | |The NuMicro M2351 series is equipped with embedded flash
* | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
* | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
* | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation.
* | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
* | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
* @var FMC_T::ISPDAT
* Offset: 0x08 ISP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT |ISP Data
* | | |Write data to this register before ISP program operation.
* | | |Read data from this register after ISP read operation.
* | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
* | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment
* | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
* | | |For XOM page erase function, , ISPDAT = 0x0055_aa03.
* @var FMC_T::ISPCMD
* Offset: 0x0C ISP Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |CMD |ISP Command
* | | |ISP command table is shown below:
* | | |0x00= FLASH Read.
* | | |0x04= Read Unique ID.
* | | |0x08= Read Flash All-One Result.
* | | |0x0B= Read Company ID.
* | | |0x0C= Read Device ID.
* | | |0x0D= Read Checksum.
* | | |0x21= FLASH 32-bit Program.
* | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
* | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
* | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1..
* | | |0x27= FLASH Multi-Word Program.
* | | |0x28= Run Flash All-One Verification.
* | | |0x2D= Run Checksum Calculation.
* | | |0x2E= Vector Remap.
* | | |0x40= FLASH 64-bit Read.
* | | |0x61= FLASH 64-bit Program.
* | | |The other commands are invalid.
* @var FMC_T::ISPTRG
* Offset: 0x10 ISP Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPGO |ISP Start Trigger (Write Protect)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished
* | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0
* | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY.
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::ISPSTS
* Offset: 0x40 ISP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPBUSY |ISP Busy Flag (Read Only)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* |[2] |CBS |Boot Selection of CONFIG (Read Only)
* | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
* | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
* | | |0 = LDROM with IAP mode.
* | | |1 = APROM with IAP mode.
* |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
* | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from Boot Loader.
* | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)
* |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
* | | |This bit is set if flash access cycle auto-tuning function is disabled
* | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
* | | |0 = Flash access cycle auto-tuning is Enabled.
* | | |1 = Flash access cycle auto-tuning is Disabled.
* |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
* | | |This bit is set if data is mismatched at ISP programming verification
* | | |This bit is clear by performing ISP flash erase or ISP read CID operation
* | | |0 = Flash Program is success.
* | | |1 = Flash Program is fail. Program data is different with data in the flash memory
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set.
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(9) APROM is erased/programmed if KEYLOCK is set to 1
* | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.
* | | |(12) Read any content of boot loader with ICE connection
* | | |(13) The address of block erase and bank erase is not in APROM
* | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
* | | |(15) The wrong setting of page erase ISP CMD in XOM
* | | |(16) Violate XOM setting one time protection
* | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page
* | | |(18) Mass erase when MERASE (CFG0[13]) is disable
* | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |ALLONE |Flash All-one Verification Flag
* | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1
* | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete.
* | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete.
* |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
* |[24] |INTFLAG |Interrupt Flag
* | | |0 = ISP is not finish.
* | | |1 = ISP done or ISPFF set.
* @var FMC_T::CYCCTL
* Offset: 0x4C Flash Access Cycle Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
* | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1)
* | | |0000 = CPU access with zero wait cycle ; flash access cycle is 1;.
* | | |The HCLK working frequency range is <27MHz; Cache is disabled by hardware.
* | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;.
* | | |The HCLK working frequency range range is<27MHz
* | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;.
* | | | The optimized HCLK working frequency range is 27~54 MHz
* | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;.
* | | |The optimized HCLK working frequency range is 54~81MHz
* | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;.
* | | | The optimized HCLK working frequency range is81~108MHz
* | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;.
* | | |The optimized HCLK working frequency range is 108~135MHz
* | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;.
* | | | The optimized HCLK working frequency range is 135~162MHz
* | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;.
* | | | The optimized HCLK working frequency range is 162~192MHz
* | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;.
* | | |The optimized HCLK working frequency range is >192MHz
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
* | | |Set this bit to disable flash access cycle auto-tuning function
* | | |0 = Flash access cycle auto-tuning is enabled.
* | | |1 = Flash access cycle auto-tuning is disabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::KPKEY0
* Offset: 0x50 KPROM KEY0 Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only)
* | | |Write KPKEY0 data to this register before KEY Comparison operation.
* @var FMC_T::KPKEY1
* Offset: 0x54 KPROM KEY1 Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only)
* | | |Write KPKEY1 data to this register before KEY Comparison operation.
* @var FMC_T::KPKEY2
* Offset: 0x58 KPROM KEY2 Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only)
* | | |Write KPKEY2 data to this register before KEY Comparison operation.
* @var FMC_T::KPKEYTRG
* Offset: 0x5C KPROM KEY Comparison Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection)
* | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished
* | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.
* | | |0 = KEY comparison operation is finished.
* | | |1 = KEY comparison is progressed.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[1] |TCEN |Timeout Counting Enable (Write Protection)
* | | |0 = Timeout counting is disabled.
* | | |1 = Timeout counting is enabled if input key is matched after key comparison finish.
* | | |10 minutes is at least for timeout, and average is about 20 minutes.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::KPKEYSTS
* Offset: 0x60 KPROM KEY Comparison Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KEYBUSY |KEY Comparison Busy (Read Only)
* | | |0 = KEY comparison is finished.
* | | |1 = KEY comparison is busy.
* |[1] |KEYLOCK |KEY LOCK Flag
* | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection
* | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0
* | | |This bit also can be set to 1 while
* | | |l CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
* | | |l KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or
* | | |l KEYENROM is programmed a non-0x5a value or
* | | |l Timeout event or
* | | |l FORBID(FMC_KPKEYSTS[3]) is 1
* | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.
* | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.
* | | |CONFIG write protect is depended on CFGFLAG
* |[2] |KEYMATCH |KEY Match Flag (Read Only)
* | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched
* | | |This bit is also cleared to 0 while
* | | |l CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
* | | |l Timeout event or
* | | |l KPROM is erased or
* | | |l KEYENROM is programmed to a non-0x5a value.
* | | |l Chip is in power down mode.
* | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.
* | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
* |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only)
* | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).
* | | |0 = KEY comparison is not forbidden.
* | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
* |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only)
* | | |This bit is set while the KEYENROM [7:0] is not 0x5a at power-on or reset
* | | |This bit is cleared to 0 by hardware while KPROM is erased
* | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0x5a value.
* | | |0 = Security Key protection is disabled.
* | | |1 = Security Key protection is enabled.
* |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only)
* | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset
* | | |This bit is cleared to 0 by hardware while KPROM is erased
* | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
* | | |0 = CONFIG write-protection is disabled.
* | | |1 = CONFIG write-protection is enabled.
* |[8] |SBKPBUSY |Secure Boot Key Programming BUSY (Read Only)
* | | |This bit is set to 1 while secure boot key program function is running
* | | |This bit is cleared to 0 while secure boot key key program function had been done.
* | | |0 = Secure boot key program function is done.
* | | |1 = Secure boot key program function is busy.
* |[9] |SBKPFLAG |Secure Boot Key Programming Flag (Read Only)
* | | |This bit is set to 1 while secure boot key program function fails
* | | |This bit is cleared to 0 while secure boot key had been programmed into flash memory.
* | | |0 = Secure boot key program function is successful.
* | | |1 = Secure boot key program function fails.
* @var FMC_T::KPKEYCNT
* Offset: 0x64 KPROM KEY-Unmatched Counting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only)
* | | |KPKECNT is increased when entry keys is wrong in Security Key protection
* | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on.
* |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only)
* | | |KPKEMAX is the maximum error key entry number at each power-on
* | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated
* | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting
* | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.
* @var FMC_T::KPCNT
* Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only)
* | | |KPCNT is the power-on counting for error key entry in Security Key protection
* | | |KPCNT is cleared to 0 if key comparison is matched.
* |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only)
* | | |KPMAX is the power-on maximum number for error key entry
* | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated
* | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting
* | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
* @var FMC_T::MPDAT0
* Offset: 0x80 ISP Data0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT0 |ISP Data 0
* | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
* @var FMC_T::MPDAT1
* Offset: 0x84 ISP Data1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT1 |ISP Data 1
* | | |This register is the second 32-bit data for 64-bit/multi-word programming.
* @var FMC_T::MPDAT2
* Offset: 0x88 ISP Data2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT2 |ISP Data 2
* | | |This register is the third 32-bit data for multi-word programming.
* @var FMC_T::MPDAT3
* Offset: 0x8C ISP Data3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT3 |ISP Data 3
* | | |This register is the fourth 32-bit data for multi-word programming.
* @var FMC_T::MPSTS
* Offset: 0xC0 ISP Multi-Program Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
* | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP Multi-Word program operation is finished.
* | | |1 = ISP Multi-Word program operation is progressed.
* |[1] |PPGO |ISP Multi-program Status (Read Only)
* | | |0 = ISP multi-word program operation is not active.
* | | |1 = ISP multi-word program operation is in progress.
* |[2] |ISPFF |ISP Fail Flag (Read Only)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* |[4] |D0 |ISP DATA 0 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
* | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
* |[5] |D1 |ISP DATA 1 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
* | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
* |[6] |D2 |ISP DATA 2 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
* | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
* |[7] |D3 |ISP DATA 3 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
* | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
* @var FMC_T::MPADDR
* Offset: 0xC4 ISP Multi-Program Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |MPADDR |ISP Multi-word Program Address
* | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
* | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
* @var FMC_T::XOMR0STS
* Offset: 0xD0 XOM Region 0 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 0 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 0.
* |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 0.
* @var FMC_T::XOMR1STS
* Offset: 0xD4 XOM Region 1 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 1 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 1.
* |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 1.
* @var FMC_T::XOMR2STS
* Offset: 0xD8 XOM Region 2 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 2 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 2.
* |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 2.
* @var FMC_T::XOMR3STS
* Offset: 0xDC XOM Region 3 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 3 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 3.
* |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 3.
* @var FMC_T::XOMSTS
* Offset: 0xE0 XOM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |XOMR0ON |XOM Region 0 On
* | | |XOM Region 0 active status.
* | | |0 = No active.
* | | |1 = XOM region 0 is active.
* |[1] |XOMR1ON |XOM Region 1 On
* | | |XOM Region 1 active status.
* | | |0 = No active.
* | | |1 = XOM region 1 is active.
* |[2] |XOMR2ON |XOM Region 2 On
* | | |XOM Region 2 active status.
* | | |0 = No active.
* | | |1 = XOM region 2 is active.
* |[3] |XOMR3ON |XOM Region 3 On
* | | |XOM Region 3 active status.
* | | |0 = No active.
* | | |1 = XOM region 3 is active.
* |[4] |XOMPEF |XOM Page Erase Function Fail
* | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
* | | |0 = Success.
* | | |1 = Fail.
*/
__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
__IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
__I uint32_t RESERVE0[11];
__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
__O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */
__O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */
__O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */
__IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */
__IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */
__I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */
__I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */
__I uint32_t RESERVE2[5];
__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
__I uint32_t RESERVE3[12];
__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
__I uint32_t RESERVE4[2];
__I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */
__I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */
__I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */
__I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */
__I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */
} FMC_T;
/**
@addtogroup FMC_CONST FMC Bit Field Definition
Constant Definitions for FMC Controller
@{ */
#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */
#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */
#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
#define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */
#define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */
#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */
#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */
#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */
#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
#define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */
#define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */
#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */
#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */
#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */
#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */
#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */
#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */
#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */
#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */
#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */
#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */
#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */
#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */
#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */
#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */
#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */
#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */
#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */
#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */
#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */
#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */
#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */
#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */
#define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */
#define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */
#define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */
#define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */
#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */
#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */
#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */
#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */
#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */
#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */
#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */
#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */
#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */
#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */
#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */
#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */
#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */
#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */
#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */
#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */
#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */
#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */
#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */
#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */
#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */
#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */
#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */
#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */
#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */
#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */
#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */
#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */
#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */
#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */
#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */
#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */
#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */
#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */
/**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */
#endif /* __FMC_REG_H__ */

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/**************************************************************************//**
* @file gpio_reg.h
* @version V1.00
* @brief GPIO register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __GPIO_REG_H__
#define __GPIO_REG_H__
/*---------------------- General Purpose Input/Output Controller -------------------------*/
/**
@addtogroup GPIO General Purpose Input/Output Controller(GPIO)
Memory Mapped Structure for GPIO Controller
@{ */
typedef struct
{
/**
* @var GPIO_T::MODE
* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 PA-H I/O Mode Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control
* | | |Determine each I/O mode of Px.n pins.
* | | |00 = Px.n is in Input mode.
* | | |01 = Px.n is in Push-pull Output mode.
* | | |10 = Px.n is in Open-drain Output mode.
* | | |11 = Px.n is in Quasi-bidirectional mode.
* | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
* | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
* | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
* | | |Note2:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::DINOFF
* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 PA-H Digital Input Path Disable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control
* | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
* | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
* | | |0 = Px.n digital input path Enabled.
* | | |1 = Px.n digital input path Disabled (digital input tied to low).
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::DOUT
* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 PA-H Data Output Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DOUTn |Port A-H Pin[n] Output Value
* | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::DATMSK
* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC PA-H Data Output Write Mask
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask
* | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
* | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
* | | |If the write signal is masked, writing data to the protect bit is ignored.
* | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
* | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
* | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
* | | |Note2:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::PIN
* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 PA-H Pin Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |PINn |Port A-H Pin[n] Pin Value
* | | |Each bit of the register reflects the actual status of the respective Px.n pin
* | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::DBEN
* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 PA-H De-Bounce Enable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DBENn |Port A-H Pin[n] Input Signal De-bounce Enable Bit
* | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
* | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
* | | |0 = Px.n de-bounce function Disabled.
* | | |1 = Px.n de-bounce function Enabled.
* | | |The de-bounce function is valid only for edge triggered interrupt
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::INTTYPE
* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 PA-H Interrupt Trigger Type Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
* | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
* | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
* | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
* | | |0 = Edge trigger interrupt.
* | | |1 = Level trigger interrupt.
* | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
* | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
* | | |The de-bounce function is valid only for edge triggered interrupt
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::INTEN
* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC PA-H Interrupt Enable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
* | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
* | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
* | | |0 = Px.n level low or high to low interrupt Disabled.
* | | |1 = Px.n level low or high to low interrupt Enabled.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* |[n+16] |RHIENn |Port A-G Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
* | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
* | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
* | | |0 = Px.n level high or low to high interrupt Disabled.
* | | |1 = Px.n level high or low to high interrupt Enabled.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::INTSRC
* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 PA-H Interrupt Source Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag
* | | |Write Operation :
* | | |0 = No action.
* | | |1 = Clear the corresponding pending interrupt.
* | | |Read Operation :
* | | |0 = No interrupt at Px.n.
* | | |1 = Px.n generates an interrupt.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::SMTEN
* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 PA-H Input Schmitt Trigger Enable
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit
* | | |0 = Px.n input Schmitt trigger function Disabled.
* | | |1 = Px.n input Schmitt trigger function Enabled.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::SLEWCTL
* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 PA-H High Slew Rate Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control
* | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).
* | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).
* | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.
* | | |11 = Reserved.
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::PUSEL
* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 PA-H Pull-up and Pull-down Selection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|PUSEL0 |Port A-H Pin[n] Pull-up and Pull-down Enable Register
* | | |Determine each I/O Pull-up/pull-down of Px.n pins.
* | | |00 = Px.n pull-up and pull-down disable.
* | | |01 = Px.n pull-up enable.
* | | |10 = Px.n pull-down enable.
* | | |11 = Px.n pull-up and pull-down disable.
* | | |Note1:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation
* | | |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode
* | | |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode
* | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode
* | | |Note:
* | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored.
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* @var GPIO_T::DBCTL
* Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4 PA-H Interrupt De-bounce Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection
* | | |0000 = Sample interrupt input once per 1 clocks.
* | | |0001 = Sample interrupt input once per 2 clocks.
* | | |0010 = Sample interrupt input once per 4 clocks.
* | | |0011 = Sample interrupt input once per 8 clocks.
* | | |0100 = Sample interrupt input once per 16 clocks.
* | | |0101 = Sample interrupt input once per 32 clocks.
* | | |0110 = Sample interrupt input once per 64 clocks.
* | | |0111 = Sample interrupt input once per 128 clocks.
* | | |1000 = Sample interrupt input once per 256 clocks.
* | | |1001 = Sample interrupt input once per 2*256 clocks.
* | | |1010 = Sample interrupt input once per 4*256 clocks.
* | | |1011 = Sample interrupt input once per 8*256 clocks.
* | | |1100 = Sample interrupt input once per 16*256 clocks.
* | | |1101 = Sample interrupt input once per 32*256 clocks.
* | | |1110 = Sample interrupt input once per 64*256 clocks.
* | | |1111 = Sample interrupt input once per 128*256 clocks.
* |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection
* | | |0 = De-bounce counter clock source is the HCLK.
* | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
* |[5] |ICLKON |Interrupt Clock on Mode
* | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
* | | |1 = All I/O pins edge detection circuit is always active after reset.
* | | |Note: It is recommended to disable this bit to save system power if no special application concern.
*/
__IO uint32_t MODE; /*!< [0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0] Port A-H I/O Mode Control */
__IO uint32_t DINOFF; /*!< [0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4] Port A-H Digital Input Path Disable Control */
__IO uint32_t DOUT; /*!< [0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8] Port A-H Data Output Value */
__IO uint32_t DATMSK; /*!< [0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC] Port A-H Data Output Write Mask */
__I uint32_t PIN; /*!< [0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0] Port A-H Pin Value */
__IO uint32_t DBEN; /*!< [0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4] Port A-H De-Bounce Enable Control */
__IO uint32_t INTTYPE; /*!< [0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8] Port A-H Interrupt Trigger Type Control */
__IO uint32_t INTEN; /*!< [0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC] Port A-H Interrupt Enable Control */
__IO uint32_t INTSRC; /*!< [0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0] Port A-H Interrupt Source Flag */
__IO uint32_t SMTEN; /*!< [0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4] Port A-H Input Schmitt Trigger Enable */
__IO uint32_t SLEWCTL; /*!< [0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8] Port A-H High Slew Rate Control */
__I uint32_t RESERVE0[1];
__IO uint32_t PUSEL; /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0] Port A-H Pull-up and Pull-down Selection Register */
__IO uint32_t DBCTL; /*!< [0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4] Port A-H Interrupt De-bounce Control */
} GPIO_T;
/**
@addtogroup GPIO_CONST GPIO Bit Field Definition
Constant Definitions for GPIO Controller
@{ */
#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */
#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */
#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */
#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */
#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */
#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */
#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */
#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */
#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */
#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */
#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */
#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */
#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */
#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */
#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */
#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */
#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */
#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */
#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */
#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */
#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */
#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */
#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */
#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */
#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */
#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */
#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */
#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */
#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */
#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */
#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */
#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */
#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */
#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */
#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */
#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */
#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */
#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */
#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */
#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */
#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */
#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */
#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */
#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */
#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */
#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */
#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */
#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */
#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */
#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */
#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */
#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */
#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */
#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */
#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */
#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */
#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */
#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */
#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */
#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */
#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */
#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */
#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */
#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */
#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
/**@}*/ /* GPIO_CONST */
/**@}*/ /* end of GPIO register group */
#endif /* __GPIO_REG_H__ */

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targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/hdiv_reg.h Normal file
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/**************************************************************************//**
* @file hdiv_reg.h
* @version V1.00
* @brief HDIV register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __HDIV_REG_H__
#define __HDIV_REG_H__
/*---------------------- Hardware Divider --------------------------------*/
/**
@addtogroup HDIV Hardware Divider(HDIV)
Memory Mapped Structure for HDIV Controller
@{ */
typedef struct
{
/**
* @var HDIV_T::DIVIDEND
* Offset: 0x00 Dividend Source Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DIVIDEND |Dividend Source
* | | |This register is given the dividend of divider before calculation starting.
* @var HDIV_T::DIVISOR
* Offset: 0x04 Divisor Source Resister
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DIVISOR |Divisor Source
* | | |This register is given the divisor of divider before calculation starts.
* | | |Note: When this register is written, hardware divider will start calculate.
* @var HDIV_T::DIVQUO
* Offset: 0x08 Quotient Result Resister
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |QUOTIENT |Quotient Result
* | | |This register holds the quotient result of divider after calculation complete.
* @var HDIV_T::DIVREM
* Offset: 0x0C Remainder Result Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |REMAINDER |Remainder Result
* | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.
* | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.
* | | |This register holds the remainder result of divider after calculation complete.
* @var HDIV_T::DIVSTS
* Offset: 0x10 Divider Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |Division Finish Flag
* | | |0 = Under Calculation.
* | | |1 = Calculation finished.
* | | |The flag will become low when the divider is in calculation.
* | | |The flag will go back to high once the calculation finished.
* |[1] |DIV0 |Divisor Zero Warning
* | | |0 = The divisor is not 0.
* | | |1 = The divisor is 0.
* | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written
* | | |This register is read only.
*/
__IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */
__IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */
__IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */
__IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */
__I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */
} HDIV_T;
/**
@addtogroup HDIV_CONST HDIV Bit Field Definition
Constant Definitions for HDIV Controller
@{ */
#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */
#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */
#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */
#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */
#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */
#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */
#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */
#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */
/**@}*/ /* HDIV_CONST */
/**@}*/ /* end of HDIV register group */
#endif /* __HDIV_REG_H__ */

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targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/i2c_reg.h Normal file
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/**************************************************************************//**
* @file i2c_reg.h
* @version V1.00
* @brief I2C register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2C_REG_H__
#define __I2C_REG_H__
/*---------------------- Inter-IC Bus Controller -------------------------*/
/**
@addtogroup I2C Inter-IC Bus Controller(I2C)
Memory Mapped Structure for I2C Controller
@{ */
typedef struct
{
/**
* @var I2C_T::CTL0
* Offset: 0x00 I2C Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
* |[3] |SI |I2C Interrupt Flag
* | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
* | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
* | | |SI must be cleared by software
* | | |Clear SI by writing 1 to this bit.
* | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
* |[4] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
* | | |This bit will be cleared by hardware automatically.
* |[5] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[6] |I2CEN |I2C Controller Enable Bit
* | | |Set to enable I2C serial function controller
* | | |When I2CEN=1 the I2C serial function enable
* | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
* | | |0 = I2C controller Disabled.
* | | |1 = I2C controller Enabled.
* |[7] |INTEN |Enable Interrupt
* | | |0 = I2C interrupt Disabled.
* | | |1 = I2C interrupt Enabled.
* @var I2C_T::ADDR0
* Offset: 0x04 I2C Slave Address Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::DAT
* Offset: 0x08 I2C Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |I2C Data
* | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
* @var I2C_T::STATUS0
* Offset: 0x0C I2C Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |STATUS |I2C Status
* | | |The three least significant bits are always 0
* | | |The five most significant bits contain the status code
* | | |There are 28 possible status codes
* | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested
* | | |Others I2C_STATUS0 values correspond to defined I2C states
* | | |When each of these states is entered, a status interrupt is requested (SI = 1)
* | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
* | | |In addition, states 00H stands for a Bus Error
* | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
* @var I2C_T::CLKDIV
* Offset: 0x10 I2C Clock Divided Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DIVIDER |I2C Clock Divided
* | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
* | | |Note: The minimum value of I2C_CLKDIV is 4.
* @var I2C_T::TOCTL
* Offset: 0x14 I2C Time-out Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIF |Time-out Flag
* | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
* | | |Note: Software can write 1 to clear this bit.
* |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
* | | |When Enabled, The time-out period is extend 4 times.
* | | |0 = Time-out period is extend 4 times Disabled.
* | | |1 = Time-out period is extend 4 times Enabled.
* |[2] |TOCEN |Time-out Counter Enable Bit
* | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear
* | | |Setting flag SI to u20181' will reset counter and re-start up counting after SI is cleared.
* | | |0 = Time-out counter Disabled.
* | | |1 = Time-out counter Enabled.
* @var I2C_T::ADDR1
* Offset: 0x18 I2C Slave Address Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::ADDR2
* Offset: 0x1C I2C Slave Address Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::ADDR3
* Offset: 0x20 I2C Slave Address Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::ADDRMSK0
* Offset: 0x24 I2C Slave Address Mask Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK1
* Offset: 0x28 I2C Slave Address Mask Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK2
* Offset: 0x2C I2C Slave Address Mask Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK3
* Offset: 0x30 I2C Slave Address Mask Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::WKCTL
* Offset: 0x3C I2C Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |I2C Wake-up Enable Bit
* | | |0 = I2C wake-up function Disabled.
* | | |1= I2C wake-up function Enabled.
* |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
* | | |0 = I2C don't hold bus after wake-up disable.
* | | |1= I2C don't hold bus after wake-up enable.
* | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
* | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
* @var I2C_T::WKSTS
* Offset: 0x40 I2C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKIF |I2C Wake-up Flag
* | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
* |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
* @var I2C_T::CTL1
* Offset: 0x44 I2C Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function disable.
* | | |1 = Transmit PDMA function enable.
* |[1] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function disable.
* | | |1 = Receive PDMA function enable.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the I2C request to PDMA. This bit will be cleared to 0 automatically.
* |[8] |PDMASTR |PDMA Stretch Bit
* | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
* | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
* | | |(only master TX)
* |[9] |ADDR10EN |Address 10-bit Function Enable
* | | |0 = Address match 10-bit function is disabled.
* | | |1 = Address match 10-bit function is enabled.
* @var I2C_T::STATUS1
* Offset: 0x48 I2C Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |I2C Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |I2C Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[2] |ADMAT2 |I2C Address 2 Match Status Register
* | | |When address 2 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[3] |ADMAT3 |I2C Address 3 Match Status Register
* | | |When address 3 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[8] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected.
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* | | |Note:This bit is read only.
* @var I2C_T::TMCTL
* Offset: 0x4C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
* | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
* | | |Note: Setup time setting should not make SCL output less than three PCLKs.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
* @var I2C_T::BUSCTL
* Offset: 0x50 I2C Bus Management Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACKMEN |Acknowledge Control by Manual
* | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
* | | |0 = Slave byte control Disabled.
* | | |1 = Slave byte control Enabled
* | | |The 9th bit can response the ACK or NACK according the received data by user
* | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
* | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
* |[1] |PECEN |Packet Error Checking Calculation Enable Bit
* | | |0 = Packet Error Checking Calculation Disabled.
* | | |1 = Packet Error Checking Calculation Enabled.
* | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
* |[2] |BMDEN |Bus Management Device Default Address Enable Bit
* | | |0 = Device default address Disable
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
* | | |1 = Device default address Enabled
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
* |[3] |BMHEN |Bus Management Host Enable Bit
* | | |0 = Host function Disabled.
* | | |1 = Host function Enabled.
* |[4] |ALERTEN |Bus Management Alert Enable Bit
* | | |Device Mode (BMHEN =0).
* | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
* | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
* | | |Host Mode (BMHEN =1).
* | | |0 = BM_ALERT pin not supported.
* | | |1 = BM_ALERT pin supported.
* |[5] |SCTLOSTS |Suspend/Control Data Output Status
* | | |0 = The output of SUSCON pin is low.
* | | |1 = The output of SUSCON pin is high.
* |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit
* | | |0 = The SUSCON pin in input.
* | | |1 = The output enable is active on the SUSCON pin.
* |[7] |BUSEN |BUS Enable Bit
* | | |0 = The system management function is Disabled.
* | | |1 = The system management function is Enable.
* | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
* |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
* | | |0 = No PEC transfer.
* | | |1 = PEC transmission is requested.
* | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
* |[9] |TIDLE |Timer Check in Idle State
* | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
* | | |This bit is used to define which condition is enabled.
* | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
* | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
* | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
* |[10] |PECCLR |PEC Clear at Repeat Start
* | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
* | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
* | | |0 = The PEC calculation is cleared by Repeat Start function is Disabled.
* | | |1 = The PEC calculation is cleared by Repeat Start function is Enabled.
* |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
* | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
* | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
* |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
* | | |0 = Indicates the byte count done interrupt is Disabled.
* | | |1 = Indicates the byte count done interrupt is Enabled.
* | | |Note: This bit is used in PECEN =1.
* |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
* | | |0 = Indicates the PEC transfer done interrupt is Disabled.
* | | |1 = Indicates the PEC transfer done interrupt is Enabled.
* | | |Note: This bit is used in PECEN =1.
* @var I2C_T::BUSTCTL
* Offset: 0x54 I2C Bus Management Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSTOEN |Bus Time Out Enable Bit
* | | |0 = Indicates the bus clock low time-out detection is Disabled.
* | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1)
* |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
* | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
* | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
* | | |For Master, it calculates the period from START to ACK
* | | |For Slave, it calculates the period from START to STOP
* |[2] |BUSTOIEN |Time-out Interrupt Enable Bit
* | | |BUSY =1.
* | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
* | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
* | | |BUSY =0.
* | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
* | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
* |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
* | | |0 = Indicates the clock time out interrupt is Disabled.
* | | |1 = Indicates the clock time out interrupt is Enabled.
* |[4] |TORSTEN |Time Out Reset Enable Bit
* | | |0 = Indicates the I2C state machine reset is Disable.
* | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
* @var I2C_T::BUSSTS
* Offset: 0x58 I2C Bus Management Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[1] |BCDONE |Byte Count Transmission/Receive Done
* | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* |[2] |PECERR |PEC Error in Reception
* | | |0 = Indicates the PEC value equal the received PEC data packet.
* | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
* | | |Note: Software can write 1 to clear this bit.
* |[3] |ALERT |SMBus Alert Status
* | | |Device Mode (BMHEN =0).
* | | |0 = Indicates SMBALERT pin state is low.
* | | |1 = Indicates SMBALERT pin state is high.
* | | |Host Mode (BMHEN =1).
* | | |0 = No SMBALERT event.
* | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
* | | |Note: 1
* | | |The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
* | | |2
* | | |Software can write 1 to clear this bit.
* |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status
* | | |0 = The input status of SUSCON pin is 0.
* | | |1 = The input status of SUSCON pin is 1.
* |[5] |BUSTO |Bus Time-out Status
* | | |0 = Indicates that there is no any time-out or external clock time-out.
* | | |1 = Indicates that a time-out or external clock time-out occurred.
* | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[6] |CLKTO |Clock Low Accumulate Time-out Status
* | | |0 = Indicates that the cumulative clock low is no any time-out.
* | | |1 = Indicates that the cumulative clock low time-out occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[7] |PECDONE |PEC Byte Transmission/Receive Done
* | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* @var I2C_T::PKTSIZE
* Offset: 0x5C I2C Packet Error Checking Byte Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |PLDSIZE |Transfer Byte Number
* | | |The transmission or receive byte number in one transaction when the PECEN is set
* | | |The maximum transaction or receive byte is 256 Bytes.
* | | |Notice: The byte number counting includes address, command code, and data frame.
* @var I2C_T::PKTCRC
* Offset: 0x60 I2C Packet Error Checking Byte Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PECCRC |Packet Error Checking Byte Value
* | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
* | | |It is read only.
* @var I2C_T::BUSTOUT
* Offset: 0x64 I2C Bus Management Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |BUSTO |Bus Management Time-out Value
* | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
* | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
* @var I2C_T::CLKTOUT
* Offset: 0x68 I2C Bus Management Clock Low Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CLKTO |Bus Clock Low Timer
* | | |The field is used to configure the cumulative clock extension time-out.
* | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
__IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
__IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
__I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
__IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
__IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
__IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
__IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
__IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
__IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
__IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
__IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
__I uint32_t RESERVE0[2];
__IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
__IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
__IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
__IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
__IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
__IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
__IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
__I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
__IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
__IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
} I2C_T;
/**
@addtogroup I2C_CONST I2C Bit Field Definition
Constant Definitions for I2C Controller
@{ */
#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */
#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */
#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */
#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */
#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */
#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */
#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */
#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */
#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */
#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */
#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */
#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */
#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */
#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
/**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */
#endif /* __I2C_REG_H__ */

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/**************************************************************************//**
* @file i2s_reg.h
* @version V1.00
* @brief I2S register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2S_REG_H__
#define __I2S_REG_H__
/*---------------------- I2S Interface Controller -------------------------*/
/**
@addtogroup I2S I2S Interface Controller(I2S)
Memory Mapped Structure for I2S Controller
@{ */
typedef struct
{
/**
* @var I2S_T::CTL0
* Offset: 0x00 I2S Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Control
* | | |0 = I2S controller Disabled.
* | | |1 = I2S controller Enabled.
* |[1] |TXEN |Transmit Enable Control
* | | |0 = Data transmission Disabled.
* | | |1 = Data transmission Enabled.
* |[2] |RXEN |Receive Enable Control
* | | |0 = Data receiving Disabled.
* | | |1 = Data receiving Enabled.
* |[3] |MUTE |Transmit Mute Enable Control
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Send zero on transmit channel.
* |[5:4] |DATWIDTH |Data Width
* | | |This bit field is used to define the bit-width of data word in each audio channel
* | | |00 = The bit-width of data word is 8-bit.
* | | |01 = The bit-width of data word is 16-bit.
* | | |10 = The bit-width of data word is 24-bit.
* | | |11 = The bit-width of data word is 32-bit.
* |[6] |MONO |Monaural Data Control
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
* | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
* | | |0 = Even channel data at high byte in 8-bit/16-bit data width.
* | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
* | | |1 = Even channel data at low byte.
* | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
* |[8] |SLAVE |Slave Mode Enable Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* | | |Note: I2S can operate as master or slave
* | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
* | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
* |[15] |MCLKEN |Master Clock Enable Control
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[18] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear TX FIFO.
* | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
* | | |Note2: This bit is clear by hardware automatically, read it return zero.
* |[19] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear RX FIFO.
* | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
* | | |Note2: This bit is cleared by hardware automatically, read it return zero.
* |[20] |TXPDMAEN |Transmit PDMA Enable Control
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[21] |RXPDMAEN |Receive PDMA Enable Control
* | | |0 = Receiver PDMA function Disabled.
* | | |1 = Receiver PDMA function Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Control
* | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
* | | |0 = Receives channel1 data in MONO mode.
* | | |1 = Receives channel0 data in MONO mode.
* |[26:24] |FORMAT |Data Format Selection
* | | |000 = I2S standard data format.
* | | |001 = I2S with MSB justified.
* | | |010 = I2S with LSB justified.
* | | |011 = Reserved.
* | | |100 = PCM standard data format.
* | | |101 = PCM with MSB justified.
* | | |110 = PCM with LSB justified.
* | | |111 = Reserved.
* |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection
* | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
* | | |0 = One BCLK period.
* | | |1 = One channel period.
* | | |Note: This bit is only available in master mode
* |[29:28] |CHWIDTH |Channel Width
* | | |This bit fields are used to define the length of audio channel
* | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
* | | |00 = The bit-width of each audio channel is 8-bit.
* | | |01 = The bit-width of each audio channel is 16-bit.
* | | |10 = The bit-width of each audio channel is 24-bit.
* | | |11 = The bit-width of each audio channel is 32-bit.
* |[31:30] |TDMCHNUM |TDM Channel Number
* | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
* | | |00 = 2 channels in audio frame.
* | | |01 = 4 channels in audio frame.
* | | |10 = 6 channels in audio frame.
* | | |11 = 8 channels in audio frame.
* @var I2S_T::CLKDIV
* Offset: 0x04 I2S Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |MCLKDIV |Master Clock Divider
* | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
* | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
* | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
* | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
* | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
* | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
* |[16:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |Software can program these bit fields to generate sampling rate clock frequency.
* | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
* | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
* @var I2S_T::IEN
* Offset: 0x08 I2S Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
* |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
* |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1
* | | |If RXTHIEN bit is enabled, interrupt occur.
* |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
* |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
* |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
* |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross
* | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross
* | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* @var I2S_T::STATUS0
* Offset: 0x0C I2S Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SINT |I2S Interrupt Flag (Read Only)
* | | |0 = No I2S interrupt.
* | | |1 = I2S interrupt.
* | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
* |[1] |I2SRXINT |I2S Receive Interrupt (Read Only)
* | | |0 = No receive interrupt.
* | | |1 = Receive interrupt.
* |[2] |I2STXINT |I2S Transmit Interrupt (Read Only)
* | | |0 = No transmit interrupt.
* | | |1 = Transmit interrupt.
* |[5:3] |DATACH |Transmission Data Channel (Read Only)
* | | |This bit fields are used to indicate which audio channel is current transmit data belong.
* | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
* | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
* | | |010 = channel2 (available while 4-channel TDM PCM mode).
* | | |011 = channel3 (available while 4-channel TDM PCM mode).
* | | |100 = channel4 (available while 6-channel TDM PCM mode).
* | | |101 = channel5 (available while 6-channel TDM PCM mode).
* | | |110 = channel6 (available while 8-channel TDM PCM mode).
* | | |111 = channel7 (available while 8-channel TDM PCM mode).
* |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag
* | | |0 = No underflow occur.
* | | |1 = Underflow occur.
* | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again
* | | |This bit will be set to 1, and it indicates underflow situation occurs.
* | | |Note2: Write 1 to clear this bit to zero
* |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag
* | | |0 = No overflow occur.
* | | |1 = Overflow occur.
* | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
* | | |Note2: Write 1 to clear this bit to 0.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is not higher than threshold level.
* | | |1 = Data word(s) in FIFO is higher than threshold level.
* | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
* | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
* |[11] |RXFULL |Receive FIFO Full (Read Only)
* | | |0 = Not full.
* | | |1 = Full.
* | | |Note: This bit reflects data words number in receive FIFO is 16.
* |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
* | | |0 = Not empty.
* | | |1 = Empty.
* | | |Note: This bit reflects data words number in receive FIFO is zero
* |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag
* | | |0 = No underflow.
* | | |1 = Underflow.
* | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
* | | |Note2: Write 1 to clear this bit to 0.
* |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag
* | | |0 = No overflow.
* | | |1 = Overflow.
* | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1
* | | |Note2: Write 1 to clear this bit to 0.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is higher than threshold level.
* | | |1 = Data word(s) in FIFO is equal or lower than threshold level.
* | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
* | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
* |[19] |TXFULL |Transmit FIFO Full (Read Only)
* | | |This bit reflect data word number in transmit FIFO is 16
* | | |0 = Not full.
* | | |1 = Full.
* |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
* | | |This bit reflect data word number in transmit FIFO is zero
* | | |0 = Not empty.
* | | |1 = Empty.
* |[21] |TXBUSY |Transmit Busy (Read Only)
* | | |0 = Transmit shift buffer is empty.
* | | |1 = Transmit shift buffer is busy.
* | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
* | | |And set to 1 when 1st data is load to shift buffer
* @var I2S_T::TXFIFO
* Offset: 0x10 I2S Transmit FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXFIFO |Transmit FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data transmit
* | | |Write data to this register to prepare data for transmit
* | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
* @var I2S_T::RXFIFO
* Offset: 0x14 I2S Receive FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXFIFO |Receive FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data receive
* | | |Read this register to get data in FIFO
* | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
* @var I2S_T::CTL1
* Offset: 0x20 I2S Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control
* | | |0 = channel0 zero-cross detect Disabled.
* | | |1 = channel0 zero-cross detect Enabled.
* | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
* | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
* |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control
* | | |0 = channel1 zero-cross detect Disabled.
* | | |1 = channel1 zero-cross detect Enabled.
* | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
* | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
* |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control
* | | |0 = channel2 zero-cross detect Disabled.
* | | |1 = channel2 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
* | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
* |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control
* | | |0 = channel3 zero-cross detect Disabled.
* | | |1 = channel3 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
* | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
* |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control
* | | |0 = channel4 zero-cross detect Disabled.
* | | |1 = channel4 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
* | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
* |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control
* | | |0 = channel5 zero-cross detect Disabled.
* | | |1 = channel5 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
* | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
* |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control
* | | |0 = channel6 zero-cross detect Disabled.
* | | |1 = channel6 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
* | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
* |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control
* | | |0 = channel7 zero-cross detect Disabled.
* | | |1 = channel7 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
* | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
* |[11:8] |TXTH |Transmit FIFO Threshold Level
* | | |0000 = 0 data word in transmit FIFO.
* | | |0001 = 1 data word in transmit FIFO.
* | | |0010 = 2 data words in transmit FIFO.
* | | |...
* | | |1110 = 14 data words in transmit FIFO.
* | | |1111 = 15 data words in transmit FIFO.
* | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
* |[19:16] |RXTH |Receive FIFO Threshold Level
* | | |0000 = 1 data word in receive FIFO.
* | | |0001 = 2 data words in receive FIFO.
* | | |0010 = 3 data words in receive FIFO.
* | | |...
* | | |1110 = 15 data words in receive FIFO.
* | | |1111 = 16 data words in receive FIFO.
* | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
* |[24] |PBWIDTH |Peripheral Bus Data Width Selection
* | | |This bit is used to choice the available data width of APB bus
* | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
* | | |0 = 32 bits data width.
* | | |1 = 16 bits data width.
* | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
* | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
* | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
* |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
* | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
* | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
* | | |0 = Low 16-bit read/write access first.
* | | |1 = High 16-bit read/write access first.
* | | |Note: This bit is available while PBWIDTH = 1.
* @var I2S_T::STATUS1
* Offset: 0x24 I2S Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag
* | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel0.
* | | |1 = Channel0 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag
* | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel1.
* | | |1 = Channel1 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag
* | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel2.
* | | |1 = Channel2 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag
* | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel3.
* | | |1 = Channel3 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag
* | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel4.
* | | |1 = Channel4 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag
* | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel5.
* | | |1 = Channel5 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag
* | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel6.
* | | |1 = Channel6 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag
* | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel7.
* | | |1 = Channel7 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[12:8] |TXCNT |Transmit FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in transmit FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in transmit FIFO.
* | | |00010 = 2 words in transmit FIFO.
* | | |...
* | | |01110 = 14 words in transmit FIFO.
* | | |01111 = 15 words in transmit FIFO.
* | | |10000 = 16 words in transmit FIFO.
* | | |Others are reserved.
* |[20:16] |RXCNT |Receive FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in receive FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in receive FIFO.
* | | |00010 = 2 words in receive FIFO.
* | | |...
* | | |01110 = 14 words in receive FIFO.
* | | |01111 = 15 words in receive FIFO.
* | | |10000 = 16 words in receive FIFO.
* | | |Others are reserved.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */
__IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */
__IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */
__O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */
__I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */
} I2S_T;
/**
@addtogroup I2S_CONST I2S Bit Field Definition
Constant Definitions for I2S Controller
@{ */
#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */
#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */
#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */
#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */
#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */
#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */
#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */
#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */
#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */
#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */
#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */
#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */
#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */
#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */
#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */
#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */
#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */
#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */
#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */
#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */
#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */
#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */
#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */
#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */
#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */
#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */
#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */
#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */
#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */
#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */
#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */
#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */
#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */
#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */
#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */
#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */
#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */
#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */
#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */
#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */
#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */
#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */
#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */
#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */
#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */
#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */
#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */
#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */
#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */
#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */
#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */
#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */
#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */
#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */
#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */
#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */
#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */
#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */
#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */
#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */
#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */
#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */
#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */
#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */
#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */
#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */
#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */
#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */
#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */
#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */
#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */
#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */
#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */
#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */
#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */
#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */
#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */
#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */
#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */
#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */
#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */
#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */
#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */
#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */
#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */
#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */
#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */
#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */
#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */
#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */
#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */
#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */
#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */
#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */
#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */
#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */
#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */
#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */
#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */
#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */
#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */
#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */
#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */
#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */
#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */
#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */
#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */
#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */
#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */
#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */
#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */
#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */
#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */
#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */
#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */
#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */
#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */
#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */
#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */
#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */
#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */
#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */
#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */
#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */
#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */
#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */
#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */
#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */
#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */
#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */
#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */
#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */
#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */
#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */
#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */
#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */
#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */
#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */
#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */
#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */
#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */
#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */
#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */
#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */
#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */
#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */
/**@}*/ /* I2S_CONST */
/**@}*/ /* end of I2S register group */
#endif /* __I2S_REG_H__ */

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targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/otg_reg.h Normal file
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/**************************************************************************//**
* @file otg_reg.h
* @version V1.00
* @brief OTG register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __OTG_REG_H__
#define __OTG_REG_H__
/*---------------------- USB On-The-Go Controller -------------------------*/
/**
@addtogroup OTG USB On-The-Go Controller(OTG)
Memory Mapped Structure for OTG Controller
@{ */
typedef struct
{
/**
* @var OTG_T::CTL
* Offset: 0x00 OTG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDROP |Drop VBUS Control
* | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
* | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
* | | |0 = Not drop the VBUS.
* | | |1 = Drop the VBUS.
* |[1] |BUSREQ |OTG Bus Request
* | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
* | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
* | | |This bit will be cleared when A-device goes to A_wait_vfall state
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
* | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification)
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
* | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
* |[2] |HNPREQEN |OTG HNP Request Enable Bit
* | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
* | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
* | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
* | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
* | | |0 = HNP request Disabled.
* | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
* | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
* |[4] |OTGEN |OTG Function Enable Bit
* | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
* | | |When USB frame not configured as OTG device, this bit is must be low.
* | | |0= OTG function Disabled.
* | | |1 = OTG function Enabled.
* |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
* | | |0 = OTG ID pin status change wake-up function Disabled.
* | | |1 = OTG ID pin status change wake-up function Enabled.
* @var OTG_T::PHYCTL
* Offset: 0x04 OTG PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OTGPHYEN |OTG PHY Enable Bit
* | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
* | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care".
* | | |0 = OTG PHY Disabled.
* | | |1 = OTG PHY Enabled.
* |[1] |IDDETEN |ID Detection Enable Bit
* | | |0 = Detect ID pin status Disabled.
* | | |1 = Detect ID pin status Enabled.
* |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
* | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
* | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
* | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The off-chip USB VBUS power switch enable is active high.
* | | |1 = The off-chip USB VBUS power switch enable is active low.
* |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
* | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
* | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
* | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
* @var OTG_T::INTEN
* Offset: 0x08 OTG Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification.
* |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Going to idle state means going to a_idle or b_idle state
* | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
* |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted.
* | | |0 = This device as a peripheral interrupt Disabled.
* | | |1 = This device as a peripheral interrupt Enabled.
* |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted.
* | | |0 = This device as a host interrupt Disabled.
* | | |1 = This device as a host interrupt Enabled.
* |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var OTG_T::INTSTS
* Offset: 0x0C OTG Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIF |OTG Role Change Interrupt Status
* | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
* | | |0 = OTG device role not changed.
* | | |1 = OTG device role changed.
* | | |Note: Write 1 to clear this flag.
* |[1] |VBEIF |VBUS Error Interrupt Status
* | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
* | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
* | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
* | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
* |[2] |SRPFIF |SRP Fail Interrupt Status
* | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
* | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
* | | |0 = OTG B-device gets VBUS high before this interval.
* | | |1 = OTG B-device does not get VBUS high before this interval.
* | | |Note: Write 1 to clear this flag.
* |[3] |HNPFIF |HNP Fail Interrupt Status
* | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
* | | |0 = A-device connects to B-device before specified interval expires.
* | | |1 = A-device does not connect to B-device before specified interval expires.
* | | |Note: Write 1 to clear this flag.
* |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
* | | |Flag is set if the OTG device transfers from non-idle state to idle state
* | | |The OTG device will be neither a host nor a peripheral.
* | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
* | | |1 = OTG device goes back to idle state(a_idle or b_idle).
* | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
* | | |Note 2: Write 1 to clear this flag.
* |[5] |IDCHGIF |ID State Change Interrupt Status
* | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
* | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[6] |PDEVIF |Act As Peripheral Interrupt Status
* | | |0= This device does not act as a peripheral.
* | | |1 = This device acts as a peripheral.
* | | |Note: Write 1 to clear this flag.
* |[7] |HOSTIF |Act As Host Interrupt Status
* | | |0= This device does not act as a host.
* | | |1 = This device acts as a host.
* | | |Note: Write 1 to clear this flag.
* |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
* | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
* | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
* | | |0 = AVLD (OTG_STATUS[4]) not toggled.
* | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
* | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
* | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
* | | |Note: Write 1 to clear this status.
* |[11] |SECHGIF |SESSEND State Change Interrupt Status
* | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
* | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[13] |SRPDETIF |SRP Detected Interrupt Status
* | | |0 = SRP not detected.
* | | |1 = SRP detected.
* | | |Note: Write 1 to clear this status.
* @var OTG_T::STATUS
* Offset: 0x10 OTG Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OVERCUR |Over Current Condition
* | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
* | | |0 = OTG A-device drives VBUS successfully.
* | | |1 = OTG A-device cannot drives VBUS high in this interval.
* |[1] |IDSTS |USB_ID Pin State of Mini-/Micro- Plug
* | | |0 = Mini-A/Micro-A plug is attached.
* | | |1 = Mini-B/Micro-B plug is attached.
* |[2] |SESSEND |Session End Status
* | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
* | | |Session end means no meaningful power on VBUS.
* | | |0 = Session is not end.
* | | |1 = Session is end.
* |[3] |BVLD |B-device Session Valid Status
* | | |0 = B-device session is not valid.
* | | |1 = B-device session is valid.
* |[4] |AVLD |A-device Session Valid Status
* | | |0 = A-device session is not valid.
* | | |1 = A-device session is valid.
* |[5] |VBUSVLD |VBUS Valid Status
* | | |When VBUS is larger than 4.7V, this bit will be set to 1.
* | | |0 = VBUS is not valid.
* | | |1 = VBUS is valid.
* |[6] |ASPERI |As Peripheral Status
* | | |When OTG as peripheral, this bit is set.
* | | |0: OTG not as peripheral
* | | |1: OTG as peripheral
* |[7] |ASHOST |As Host Status
* | | |When OTG as Host, this bit is set.
* | | |0: OTG not as Host
* | | |1: OTG as Host
*/
__IO uint32_t CTL; /*!< [0x0000] OTG Control Register */
__IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */
__IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */
__I uint32_t STATUS; /*!< [0x0010] OTG Status Register */
} OTG_T;
/**
@addtogroup OTG_CONST OTG Bit Field Definition
Constant Definitions for OTG Controller
@{ */
#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */
#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */
#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */
#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */
/**@}*/ /* OTG_CONST */
/**@}*/ /* end of OTG register group */
#endif /* __OTG_REG_H__ */

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/**************************************************************************//**
* @file pdma_reg.h
* @version V1.00
* @brief PDMA register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PDMA_REG_H__
#define __PDMA_REG_H__
/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
/**
@addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
Memory Mapped Structure for PDMA Controller
@{ */
typedef struct
{
/**
* @var DSCT_T::CTL
* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |OPMODE |PDMA Operation Mode Selection
* | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
* | | |01 = Basic mode: The descriptor table only has one task
* | | |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted.
* | | |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute.
* | | |11 = Reserved.
* | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
* |[2] |TXTYPE |Transfer Type
* | | |0 = Burst transfer type.
* | | |1 = Single transfer type.
* |[6:4] |BURSIZE |Burst Size
* | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
* | | |000 = 128 Transfers.
* | | |001 = 64 Transfers.
* | | |010 = 32 Transfers.
* | | |011 = 16 Transfers.
* | | |100 = 8 Transfers.
* | | |101 = 4 Transfers.
* | | |110 = 2 Transfers.
* | | |111 = 1 Transfers.
* | | |Note: This field is only useful in burst transfer type.
* |[7] |TBINTDIS |Table Interrupt Disable Bit
* | | |This field can be used to decide whether to enable table interrupt or not
* | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
* | | |0 = Table interrupt Enabled.
* | | |1 = Table interrupt Disabled.
* | | |Note: If this bit set to 1, the TEMPTYF will not be set.
* |[9:8] |SAINC |Source Address Increment
* | | |This field is used to set the source address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[11:10] |DAINC |Destination Address Increment
* | | |This field is used to set the destination address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[13:12] |TXWIDTH |Transfer Width Selection
* | | |This field is used for transfer width.
* | | |00 = One byte (8 bit) is transferred for every operation.
* | | |01 = One half-word (16 bit) is transferred for every operation.
* | | |10 = One word (32-bit) is transferred for every operation.
* | | |11 = Reserved.
* | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
* | | |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment
* | | |The source address is aligned when TXWIDTH is byte or half-word transfer.
* |[14] |TXACK |Transfer Acknowledge Selection
* | | |0 = transfer ack when transfer done.
* | | |1 = transfer ack when PDMA get transfer data.
* |[15] |STRIDEEN |Stride Mode Enable Bit
* | | |0 = Stride transfer mode Disabled.
* | | |1 = Stride transfer mode Enabled.
* |[31:16] |TXCNT |Transfer Count
* | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
* | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
* @var DSCT_T::SA
* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SA |PDMA Transfer Source Address Register
* | | |This field indicates a 32-bit source address of PDMA controller.
* | | |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
* @var DSCT_T::DA
* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DA |PDMA Transfer Destination Address Register
* | | |This field indicates a 32-bit destination address of PDMA controller.
* | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
* @var DSCT_T::FIRST
* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FIRST |PDMA First Descriptor Table Offset
* | | |This field indicates the offset of the first descriptor table address in system memory.
* | | |Write Operation:
* | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
* | | |Read Operation:
* | | |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.
* | | |Note1: The first descriptor table address must be word boundary.
* | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
* |[31:16] |NEXT |PDMA Next Descriptor Table Offset
* | | |This field indicates the offset of next descriptor table address in system memory.
* | | |Note: write operation is useless in this field.
*/
__IO uint32_t CTL; /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 */
__IO uint32_t SA; /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 */
__IO uint32_t DA; /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 */
__IO uint32_t NEXT; /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset */
} DSCT_T;
typedef struct
{
/**
* @var STRIDE_T::STCR
* Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |STC |PDMA Stride Transfer Count
* | | |The 16-bit register defines the stride transfer count of each row.
* @var STRIDE_T::ASOCR
* Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SASOL |VDMA Source Address Stride Offset Length
* | | |The 16-bit register defines the source address stride transfer offset count of each row.
* |[31:16] |DASOL |VDMA Destination Address Stride Offset Length
* | | |The 16-bit register defines the destination address stride transfer offset count of each row.
*/
__IO uint32_t STCR; /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7 */
__IO uint32_t ASOCR; /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0 */
} STRIDE_T;
typedef struct
{
/**
* @var PDMA_T::CURSCAT
* Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
* | | |This field indicates a 32-bit current external description address of PDMA controller.
* | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
* @var PDMA_T::CHCTL
* Offset: 0x400 PDMA Channel Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CHENn |PDMA Channel Enable Bit
* | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
* | | |0 = PDMA channel [n] Disabled.
* | | |1 = PDMA channel [n] Enabled.
* | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
* @var PDMA_T::PAUSE
* Offset: 0x404 PDMA Transfer Pause Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only)
* | | |User can set PAUSEn bit field to pause the PDMA transfer
* | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
* | | |If re-enable the paused channel again, the remaining transfers will be processed.
* | | |0 = No effect.
* | | |1 = Pause PDMA channel n transfer.
* @var PDMA_T::SWREQ
* Offset: 0x408 PDMA Software Request Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SWREQn |PDMA Software Request Register (Write Only)
* | | |Set this bit to 1 to generate a software request to PDMA [n].
* | | |0 = No effect.
* | | |1 = Generate a software request.
* | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active
* | | |Active flag may be triggered by software request or peripheral request.
* | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
* @var PDMA_T::TRGSTS
* Offset: 0x40C PDMA Channel Request Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only)
* | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
* | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
* | | |0 = PDMA Channel n has no request.
* | | |1 = PDMA Channel n has a request.
* | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
* @var PDMA_T::PRISET
* Offset: 0x410 PDMA Fixed Priority Setting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register
* | | |Set this bit to 1 to enable fixed priority level.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set PDMA channel [n] to fixed priority channel.
* | | |Read Operation:
* | | |0 = Corresponding PDMA channel is round-robin priority.
* | | |1 = Corresponding PDMA channel is fixed priority.
* | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
* @var PDMA_T::PRICLR
* Offset: 0x414 PDMA Fixed Priority Clear Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
* | | |Set this bit to 1 to clear fixed priority level.
* | | |0 = No effect.
* | | |1 = Clear PDMA channel [n] fixed priority setting.
* | | |Note: User can read PDMA_PRISET register to know the channel priority.
* @var PDMA_T::INTEN
* Offset: 0x418 PDMA Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |INTENn |PDMA Interrupt Enable Register
* | | |This field is used for enabling PDMA channel[n] interrupt.
* | | |0 = PDMA channel n interrupt Disabled.
* | | |1 = PDMA channel n interrupt Enabled.
* @var PDMA_T::INTSTS
* Offset: 0x41C PDMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
* | | |0 = No AHB bus ERROR response received.
* | | |1 = AHB bus ERROR response received.
* |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
* | | |0 = Not finished yet.
* | | |1 = PDMA channel has finished transmission.
* |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* |[8] |REQTOF0 |Request Time-out Flag for Channel 0
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* |[9] |REQTOF1 |Request Time-out Flag for Channel 1
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* @var PDMA_T::ABTSTS
* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
* | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
* | | |0 = No AHB bus ERROR response received when channel n transfer.
* | | |1 = AHB bus ERROR response received when channel n transfer.
* @var PDMA_T::TDSTS
* Offset: 0x424 PDMA Channel Transfer Done Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TDIFn |Transfer Done Flag Register
* | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
* | | |0 = PDMA channel transfer has not finished.
* | | |1 = PDMA channel has finished transmission.
* @var PDMA_T::ALIGN
* Offset: 0x428 PDMA Transfer Alignment Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ALIGNn |Transfer Alignment Flag Register
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* @var PDMA_T::TACTSTS
* Offset: 0x42C PDMA Transfer Active Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only)
* | | |This bit indicates which PDMA channel is in active.
* | | |0 = PDMA channel is not finished.
* | | |1 = PDMA channel is active.
* @var PDMA_T::TOUTPSC
* Offset: 0x430 PDMA Time-out Prescaler Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8.
* | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9.
* | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10.
* | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11.
* | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12.
* | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13.
* | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14.
* | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15.
* |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8.
* | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9.
* | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10.
* | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11.
* | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12.
* | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13.
* | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14.
* | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15.
* @var PDMA_T::TOUTEN
* Offset: 0x434 PDMA Time-out Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOUTEN0 |PDMA Channel 0 Time-out Enable Bit
* | | |0 = PDMA Channel 0 time-out function Disable.
* | | |1 = PDMA Channel 0 time-out function Enable.
* |[1] |TOUTEN1 |PDMA Channel 1 Time-out Enable Bit
* | | |0 = PDMA Channel 1 time-out function Disable.
* | | |1 = PDMA Channel 1 time-out function Enable.
* @var PDMA_T::TOUTIEN
* Offset: 0x438 PDMA Time-out Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOUTIEN0 |PDMA Channel 0 Time-out Interrupt Enable Bit
* | | |0 = PDMA Channel 0 time-out interrupt Disable.
* | | |1 = PDMA Channel 0 time-out interrupt Enable.
* |[1] |TOUTIEN1 |PDMA Channel 1 Time-out Interrupt Enable Bit
* | | |0 = PDMA Channel 1 time-out interrupt Disable.
* | | |1 = PDMA Channel 1 time-out interrupt Enable.
* @var PDMA_T::SCATBA
* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register
* | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address
* | | |The next link address equation is
* | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
* | | |Note: Only useful in Scatter-Gather mode.
* @var PDMA_T::TOC0_1
* Offset: 0x440 PDMA Channel 0 and Channel 1 Time-out Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TOC0 |Time-out Counter for Channel 0
* | | |This controls the period of time-out function for channel 0
* | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
* | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1.
* |[31:16] |TOC1 |Time-out Counter for Channel 1
* | | |This controls the period of time-out function for channel 1
* | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock
* | | |The example of time-out period can refer TOC0 bit description.
* @var PDMA_T::RESET
* Offset: 0x460 PDMA Channel Reset Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CHnRST |Channel N Reset
* | | |0 = corresponding channel n not reset.
* | | |1 = corresponding channel n is reset.
* @var PDMA_T::REQSEL0_3
* Offset: 0x480 PDMA Channel 0 to Channel 3 Request Source Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC0 |Channel 0 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 0
* | | |User can configure the peripheral by setting REQSRC0.
* | | |0 = Disable PDMA.
* | | |1 = Reserved.
* | | |2 = Channel connects to USB_TX.
* | | |3 = Channel connects to USB_RX.
* | | |4 = Channel connects to UART0_TX.
* | | |5 = Channel connects to UART0_RX.
* | | |6 = Channel connects to UART1_TX.
* | | |7 = Channel connects to UART1_RX.
* | | |8 = Channel connects to UART2_TX.
* | | |9 = Channel connects to UART2_RX.
* | | |10 = Channel connects to UART3_TX.
* | | |11 = Channel connects to UART3_RX.
* | | |12 = Channel connects to UART4_TX.
* | | |13 = Channel connects to UART4_RX.
* | | |14 = Channel connects to UART5_TX.
* | | |15 = Channel connects to UART5_RX.
* | | |16 = Channel connects to USCI0_TX.
* | | |17 = Channel connects to USCI0_RX.
* | | |18 = Channel connects to USCI1_TX.
* | | |19 = Channel connects to USCI1_RX.
* | | |20 = Channel connects to QSPI0_TX.
* | | |21 = Channel connects to QSPI0_RX.
* | | |22 = Channel connects to SPI0_TX.
* | | |23 = Channel connects to SPI0_RX.
* | | |24 = Channel connects to SPI1_TX.
* | | |25 = Channel connects to SPI1_RX.
* | | |26 = Channel connects to SPI2_TX.
* | | |27 = Channel connects to SPI2_RX.
* | | |28 = Channel connects to SPI3_TX.
* | | |29 = Channel connects to SPI3_RX.
* | | |30 = Channel connects to SPI5_TX.
* | | |31 = Channel connects to SPI5_RX.
* | | |32 = Channel connects to EPWM0_P1_RX.
* | | |33 = Channel connects to EPWM0_P2_RX.
* | | |34 = Channel connects to EPWM0_P3_RX.
* | | |35 = Channel connects to EPWM1_P1_RX.
* | | |36 = Channel connects to EPWM1_P2_RX.
* | | |37 = Channel connects to EPWM1_P3_RX.
* | | |38 = Channel connects to I2C0_TX.
* | | |39 = Channel connects to I2C0_RX.
* | | |40 = Channel connects to I2C1_TX.
* | | |41 = Channel connects to I2C1_RX.
* | | |42 = Channel connects to I2C2_TX.
* | | |43 = Channel connects to I2C2_RX.
* | | |44 = Channel connects to I2S0_TX.
* | | |45 = Channel connects to I2S0_RX.
* | | |46 = Channel connects to TMR0.
* | | |47 = Channel connects to TMR1.
* | | |48 = Channel connects to TMR2.
* | | |49 = Channel connects to TMR3.
* | | |50 = Channel connects to ADC_RX.
* | | |51 = Channel connects to DAC0_TX.
* | | |52 = Channel connects to DAC1_TX.
* | | |53 = Channel connects to EPWM0_CH0_TX.
* | | |54 = Channel connects to EPWM0_CH1_TX.
* | | |55 = Channel connects to EPWM0_CH2_TX.
* | | |56 = Channel connects to EPWM0_CH3_TX.
* | | |57 = Channel connects to EPWM0_CH4_TX.
* | | |58 = Channel connects to EPWM0_CH5_TX.
* | | |59 = Channel connects to EPWM1_CH0_TX.
* | | |60 = Channel connects to EPWM1_CH1_TX.
* | | |61 = Channel connects to EPWM1_CH2_TX.
* | | |62 = Channel connects to EPWM1_CH3_TX.
* | | |63 = Channel connects to EPWM1_CH4_TX.
* | | |64 = Channel connects to EPWM1_CH5_TX.
* | | |Others = Reserved.
* | | |Note 1: A request source cannot assign to two channels at the same time.
* | | |Note 2: This field is useless when transfer between memory and memory.
* |[14:8] |REQSRC1 |Channel 1 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 1
* | | |User can configure the peripheral setting by REQSRC1.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC2 |Channel 2 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 2
* | | |User can configure the peripheral setting by REQSRC2.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC3 |Channel 3 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 3
* | | |User can configure the peripheral setting by REQSRC3.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* @var PDMA_T::REQSEL4_7
* Offset: 0x484 PDMA Request Source Select Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC4 |Channel 4 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 4
* | | |User can configure the peripheral setting by REQSRC4.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[14:8] |REQSRC5 |Channel 5 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 5
* | | |User can configure the peripheral setting by REQSRC5.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC6 |Channel 6 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 6
* | | |User can configure the peripheral setting by REQSRC6.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC7 |Channel 7 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 7
* | | |User can configure the peripheral setting by REQSRC7.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
*/
DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7 */
__I uint32_t CURSCAT[8]; /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */
__I uint32_t RESERVE0[216];
__IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */
__O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */
__O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */
__I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */
__IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */
__O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */
__IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */
__IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */
__IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */
__IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */
__I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */
__IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */
__IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */
__IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */
__IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */
__IO uint32_t TOC0_1; /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register */
__I uint32_t RESERVE1[7];
__IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */
__I uint32_t RESERVE2[7];
__IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register */
__IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register */
__I uint32_t RESERVE4[30];
STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5 */
} PDMA_T;
/**
@addtogroup PDMA_CONST PDMA Bit Field Definition
Constant Definitions for PDMA Controller
@{ */
#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */
#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */
#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */
#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */
#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */
#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */
#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */
#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */
#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */
#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */
#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */
#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */
#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */
#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */
#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */
#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */
#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */
#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */
#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */
#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */
#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */
#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */
#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */
#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */
#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */
#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */
#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */
#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */
#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */
#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */
#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */
#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */
#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */
#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */
#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */
#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */
#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */
#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */
#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */
#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */
#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */
#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */
#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */
#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */
#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */
#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */
#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */
#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */
#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */
#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */
#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */
#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */
#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */
#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */
#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */
#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */
#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */
#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */
#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */
#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */
#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */
#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */
#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */
#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */
#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */
#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */
#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */
#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */
#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */
#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */
#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */
#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */
#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */
#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */
#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */
#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */
#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */
#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */
#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */
#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */
#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */
#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */
#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */
#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */
#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */
#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */
#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */
#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */
#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */
#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */
#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */
#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */
#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */
#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */
#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */
#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */
#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */
#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */
#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */
#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */
#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */
#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */
#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */
#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */
#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */
#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */
#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */
#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */
#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */
#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */
#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */
#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */
#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */
#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */
/**@}*/ /* PDMA_CONST */
/**@}*/ /* end of PDMA register group */
#endif /* __PDMA_REG_H__ */

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/**************************************************************************//**
* @file qei_reg.h
* @version V1.00
* @brief QEI register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QEI_REG_H__
#define __QEI_REG_H__
/*---------------------- Quadrature Encoder Interface -------------------------*/
/**
@addtogroup QEI Quadrature Encoder Interface(QEI)
Memory Mapped Structure for QEI Controller
@{ */
typedef struct
{
/**
* @var QEI_T::CNT
* Offset: 0x00 QEI Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |Quadrature Encoder Interface Counter
* | | |A 32-bit up/down counter
* | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero
* | | |This register performs an integrator which count value is proportional to the encoder position
* | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
* | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
* | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
* | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1.
* @var QEI_T::CNTHOLD
* Offset: 0x04 QEI Counter Hold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
* | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
* @var QEI_T::CNTLATCH
* Offset: 0x08 QEI Counter Index Latch Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
* | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
* @var QEI_T::CNTCMP
* Offset: 0x0C QEI Counter Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
* | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
* | | |This register is software writable.
* @var QEI_T::CNTMAX
* Offset: 0x14 QEI Pre-set Maximum Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
* | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
* @var QEI_T::CTL
* Offset: 0x18 QEI Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock .
* | | |000 = QEI_CLK.
* | | |001 = QEI_CLK/2.
* | | |010 = QEI_CLK/4.
* | | |011 = QEI_CLK/16.
* | | |100 = QEI_CLK/32.
* | | |101 = QEI_CLK/64.
* |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
* | | |0 = The noise filter of QEI controller Enabled.
* | | |1 = The noise filter of QEI controller Disabled.
* |[4] |CHAEN |QEA Input to QEI Controller Enable Bit
* | | |0 = QEA input to QEI Controller Disabled.
* | | |1 = QEA input to QEI Controller Enabled.
* |[5] |CHBEN |QEB Input to QEI Controller Enable Bit
* | | |0 = QEB input to QEI Controller Disabled.
* | | |1 = QEB input to QEI Controller Enabled.
* |[6] |IDXEN |IDX Input to QEI Controller Enable Bit
* | | |0 = IDX input to QEI Controller Disabled.
* | | |1 = IDX input to QEI Controller Enabled.
* |[9:8] |MODE |QEI Counting Mode Selection
* | | |There are four quadrature encoder pulse counter operation modes.
* | | |00 = X4 Free-counting Mode.
* | | |01 = X2 Free-counting Mode.
* | | |10 = X4 Compare-counting Mode.
* | | |11 = X2 Compare-counting Mode.
* |[12] |CHAINV |Inverse QEA Input Polarity
* | | |0 = Not inverse QEA input polarity.
* | | |1 = QEA input polarity is inverse to QEI controller.
* |[13] |CHBINV |Inverse QEB Input Polarity
* | | |0 = Not inverse QEB input polarity.
* | | |1 = QEB input polarity is inverse to QEI controller.
* |[14] |IDXINV |Inverse IDX Input Polarity
* | | |0 = Not inverse IDX input polarity.
* | | |1 = IDX input polarity is inverse to QEI controller.
* |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit
* | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
* | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
* |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit
* | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
* | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
* |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit
* | | |0 = CMPF can trigger QEI controller interrupt Disabled.
* | | |1 = CMPF can trigger QEI controller interrupt Enabled.
* |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit
* | | |0 = The IDXF can trigger QEI interrupt Disabled.
* | | |1 = The IDXF can trigger QEI interrupt Enabled.
* |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0
* | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
* |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1
* | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
* |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2
* | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
* |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3
* | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
* |[24] |HOLDCNT |Hold QEI_CNT Control
* | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD
* | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
* | | |0 = No operation.
* | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
* | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
* |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit
* | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
* | | |0 = The index signal latch QEI counter function Disabled.
* | | |1 = The index signal latch QEI counter function Enabled.
* |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit
* | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0).
* | | |0 = Reload function Disabled.
* | | |1 = QEI_CNT re-initialized by Index signal Enabled.
* |[28] |CMPEN |the Compare Function Enable Bit
* | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
* | | |0 = Compare function Disabled.
* | | |1 = Compare function Enabled.
* |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit
* | | |0 = QEI controller function Disabled.
* | | |1 = QEI controller function Enabled.
* @var QEI_T::STATUS
* Offset: 0x2C QEI Controller Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IDXF |IDX Detected Flag
* | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
* | | |0 = No rising edge detected on signal CHX.
* | | |1 = A rising edge occurs on signal CHX.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CMPF |Compare-match Flag
* | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
* | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
* | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
* | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
* | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
* | | |0 = No overflow or underflow occurs in QEI counter.
* | | |1 = QEI counter occurs counting overflow or underflow.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[3] |DIRCHGF |Direction Change Flag
* | | |Flag is set by hardware while QEI counter counting direction is changed
* | | |Software can clear this bit by writing 1 to it.
* | | |0 = No change in QEI counter counting direction.
* | | |1 = QEI counter counting direction is changed.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[8] |DIRF |QEI Counter Counting Direction Indication
* | | |0 = QEI Counter is in down-counting.
* | | |1 = QEI Counter is in up-counting.
* | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
*/
__IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */
__IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */
__IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */
__IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */
__I uint32_t RESERVE0[1];
__IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */
__IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */
__I uint32_t RESERVE1[4];
__IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */
} QEI_T;
/**
@addtogroup QEI_CONST QEI Bit Field Definition
Constant Definitions for QEI Controller
@{ */
#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */
#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */
#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */
#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */
#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */
#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */
#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */
#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */
#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */
#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */
#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */
#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */
#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */
#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */
#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */
#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */
#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */
#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */
#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */
#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */
#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */
#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */
#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */
#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */
#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */
#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */
#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */
#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */
#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */
#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */
#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */
#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */
#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */
#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */
#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */
#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */
#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */
#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */
#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */
#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */
#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */
#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */
#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */
#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */
#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */
#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */
#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */
#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */
#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */
#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */
#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */
#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */
#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */
#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */
#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */
#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */
#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */
#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */
#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */
#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */
#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */
#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */
#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */
#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */
/**@}*/ /* QEI_CONST */
/**@}*/ /* end of QEI register group */
#endif /* __QEI_REG_H__ */

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/**************************************************************************//**
* @file qspi_reg.h
* @version V1.00
* @brief QSPI register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QSPI_REG_H__
#define __QSPI_REG_H__
/*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/
/**
@addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI)
Memory Mapped Structure for QSPI Controller
@{ */
typedef struct
{
/**
* @var QSPI_T::CTL
* Offset: 0x00 QSPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |QSPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = QSPI bus clock is idle low.
* | | |1 = QSPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
* | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
* | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 .... 8 bits.
* | | |DWIDTH = 0x09 .... 9 bits.
* | | |.....
* | | |DWIDTH = 0x1F .... 31 bits.
* | | |DWIDTH = 0x00 .... 32 bits.
* | | |Note: For QSPI0~QSPI3, this bit field will decide the depth of TX/RX FIFO configuration in QSPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in QSPI0~QSPI3.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
* |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for QSPI transfer
* | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = QSPI operates in full-duplex transfer.
* | | |1 = QSPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0)
* | | |0 = 2-Bit Transfer mode Disabled.
* | | |1 = 2-Bit Transfer mode Enabled.
* | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = QSPI unit transfer interrupt Disabled.
* | | |1 = QSPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = QSPI data is input direction.
* | | |1 = QSPI data is output direction.
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0)
* | | |0 = Dual I/O mode Disabled.
* | | |1 = Dual I/O mode Enabled.
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0)
* | | |0 = Quad I/O mode Disabled.
* | | |1 = Quad I/O mode Enabled.
* @var QSPI_T::CLKDIV
* Offset: 0x04 QSPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* @var QSPI_T::SSCTL
* Offset: 0x08 QSPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the QSPIx_SS line to inactive state.
* | | |1 = set the QSPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the QSPIx_SS line at inactive state.
* | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).
* | | |0 = The slave selection signal QSPIx_SS is active low.
* | | |1 = The slave selection signal QSPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0)
* | | |Slave 3-wire mode is only available in QSPI0
* | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0)
* | | |0 = Slave mode time-out interrupt Disabled.
* | | |1 = Slave mode time-out interrupt Enabled.
* |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0)
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0)
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var QSPI_T::PDMACTL
* Offset: 0x0C QSPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
* @var QSPI_T::FIFOCTL
* Offset: 0x10 QSPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.
* @var QSPI_T::STATUS
* Offset: 0x14 QSPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = QSPI controller is in idle state.
* | | |1 = QSPI controller is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d.
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
* | | |e.
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = QSPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0)
* | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
* | | |0 = Slave time-out is not active.
* | | |1 = Slave time-out is active.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurs.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurs.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |QSPI Enable Status (Read Only)
* | | |0 = The QSPI controller is disabled.
* | | |1 = The QSPI controller is enabled.
* | | |Note: The QSPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var QSPI_T::TX
* Offset: 0x20 QSPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.
* | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
* | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
* | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var QSPI_T::RX
* Offset: 0x30 QSPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register (Read Only)
* | | |There are 8-level FIFO buffers in this controller.
* | | |The data receive register holds the data received from QSPI data input pin.
* | | |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
*/
__IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
__I uint32_t RESERVE0[2];
__O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
} QSPI_T;
/**
@addtogroup QSPI_CONST QSPI Bit Field Definition
Constant Definitions for QSPI Controller
@{ */
#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */
#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */
#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */
#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */
#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
/**@}*/ /* QSPI_CONST */
/**@}*/ /* end of QSPI register group */
#endif /* __QSPI_REG_H__ */

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/**************************************************************************//**
* @file sc_reg.h
* @version V1.00
* @brief SC register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SC_REG_H__
#define __SC_REG_H__
/*---------------------- Smart Card Host Interface Controller -------------------------*/
/**
@addtogroup SC Smart Card Host Interface Controller(SC)
Memory Mapped Structure for SC Controller
@{ */
typedef struct
{
/**
* @var SC_T::DAT
* Offset: 0x00 SC Receive/Transmit Holding Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |Receive/Transmit Holding Buffer
* | | |Write Operation:
* | | |By writing data to DAT, the SC will send out an 8-bit data.
* | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
* | | |Read Operation:
* | | |By reading DAT, the SC will return an 8-bit received data.
* @var SC_T::CTL
* Offset: 0x04 SC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SCEN |SC Controller Enable Bit
* | | |Set this bit to 1 to enable SC operation.
* | | |0 = SC will force all transition to IDLE state.
* | | |1 = SC controller is enabled and all function can work correctly.
* | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
* |[1] |RXOFF |RX Transition Disable Control Bit
* | | |This bit is used for disable Rx transition function.
* | | |0 = The receiver Enabled.
* | | |1 = The receiver Disabled.
* | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[2] |TXOFF |TX Transition Disable Control Bit
* | | |This bit is used for disable Tx transition function.
* | | |0 = The transceiver Enabled.
* | | |1 = The transceiver Disabled.
* |[3] |AUTOCEN |Auto Convention Enable Bit
* | | |This bit is used for enable auto convention function.
* | | |0 = Auto-convention Disabled.
* | | |1 = Auto-convention Enabled.
* | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F
* | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F
* | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
* | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
* |[5:4] |CONSEL |Convention Selection
* | | |00 = Direct convention.
* | | |01 = Reserved.
* | | |10 = Reserved.
* | | |11 = Inverse convention.
* | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[7:6] |RXTRGLV |Rx Buffer Trigger Level
* | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
* | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
* | | |00 = Rx Buffer Trigger Level with 01 bytes.
* | | |01 = Rx Buffer Trigger Level with 02 bytes.
* | | |10 = Rx Buffer Trigger Level with 03 bytes.
* | | |11 = Reserved.
* |[12:8] |BGT |Block Guard Time (BGT)
* | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions
* | | |This field indicates the counter for the bit length of block guard time
* | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
* | | |Note: The real block guard time is BGT + 1.
* |[14:13] |TMRSEL |Timer Channel Selection
* | | |00 = All internal timer function Disabled.
* | | |.
* | | |11 = Internal 24 bit timer and two 8 bit timers Enabled
* | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
* | | |Other configurations are reserve
* |[15] |NSB |Stop Bit Length
* | | |This field indicates the length of stop bit.
* | | |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode).
* | | |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode).
* | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
* | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
* |[18:16] |RXRTY |RX Error Retry Count Number
* | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
* | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when RXRTYEN enabled
* | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
* |[19] |RXRTYEN |RX Error Retry Enable Bit
* | | |This bit enables receiver retry function when parity error has occurred.
* | | |0 = RX error retry function Disabled.
* | | |1 = RX error retry function Enabled.
* | | |Note: User must fill in the RXRTY value before enabling this bit.
* |[22:20] |TXRTY |TX Error Retry Count Number
* | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
* | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when TXRTYEN enabled
* | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
* |[23] |TXRTYEN |TX Error Retry Enable Bit
* | | |This bit enables transmitter retry function when parity error has occurred.
* | | |0 = TX error retry function Disabled.
* | | |1 = TX error retry function Enabled.
* |[25:24] |CDDBSEL |Card Detect De-bounce Selection
* | | |This field indicates the card detect de-bounce selection.
* | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks.
* | | |Other configurations are reserved.
* |[26] |CDLV |Card Detect Level Selection
* | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
* | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
* | | |Note: User must select card detect level before Smart Card controller enabled.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
* | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
* | | |1 = Last value is synchronizing.
* @var SC_T::ALTCTL
* Offset: 0x08 SC Alternate Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXRST |TX Software Reset
* | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[1] |RXRST |Rx Software Reset
* | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the Rx internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by deactivation sequence.
* | | |0 = No effect.
* | | |1 = Deactivation sequence generator Enabled.
* | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[3] |ACTEN |Activation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by activation sequence.
* | | |0 = No effect.
* | | |1 = Activation sequence generator Enabled.
* | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data
* | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
* |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by warm reset sequence.
* | | |0 = No effect.
* | | |1 = Warm reset sequence generator Enabled.
* | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data
* | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.
* |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
* | | |This bit enables Timer 0 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed
* |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
* | | |This bit enables Timer 1 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
* | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
* | | |This bit enables Timer 2 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
* | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[9:8] |INITSEL |Initial Timing Selection
* | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.
* | | |The unit of initial timing is SC module clock.
* | | |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence.
* | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence.
* | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence.
* | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.
* |[11] |ADACEN |Auto Deactivation When Card Removal
* | | |This bit is used for enable hardware auto deactivation when smart card is removed.
* | | |0 = Auto deactivation Disabled.
* | | |1 = Auto deactivation Enabled.
* | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set
* | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
* |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
* | | |This bit enables the receiver block guard time function.
* | | |0 = Receiver block guard time function Disabled.
* | | |1 = Receiver block guard time function Enabled.
* |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer0.
* | | |0 = Timer0 is not active.
* | | |1 = Timer0 is active.
* | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
* |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer1.
* | | |0 = Timer1 is not active.
* | | |1 = Timer1 is active.
* | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
* |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer2.
* | | |0 = Timer2 is not active.
* | | |1 = Timer2 is active.
* | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::EGT
* Offset: 0x0C SC Extra Guard Time Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |EGT |Extra Guard Time
* | | |This field indicates the extra guard time value.
* | | |Note: The extra guard time unit is ETU base.
* @var SC_T::RXTOUT
* Offset: 0x10 SC Receive Buffer Time-out Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |RFTM |SC Receiver FIFO Time-out Counter
* | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data
* | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.
* | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
* | | |Note2: Filling in all 0 to this field indicates to disable this function.
* @var SC_T::ETUCTL
* Offset: 0x14 SC Element Time Unit Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ETURDIV |ETU Rate Divider
* | | |The field is used for ETU clock rate divider.
* | | |The real ETU is ETURDIV + 1.
* | | |Note: User can configure this field, but this field must be greater than 0x04.
* @var SC_T::INTEN
* Offset: 0x18 SC Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
* | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
* | | |0 = Receive data reach trigger level interrupt Disabled.
* | | |1 = Receive data reach trigger level interrupt Enabled.
* |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
* | | |This field is used to enable transmit buffer empty interrupt.
* | | |0 = Transmit buffer empty interrupt Disabled.
* | | |1 = Transmit buffer empty interrupt Enabled.
* |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
* | | |This field is used to enable transfer error interrupt
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt Disabled.
* | | |1 = Transfer error interrupt Enabled.
* |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
* | | |This field is used to enable Timer0 interrupt function.
* | | |0 = Timer0 interrupt Disabled.
* | | |1 = Timer0 interrupt Enabled.
* |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
* | | |This field is used to enable the Timer1 interrupt function.
* | | |0 = Timer1 interrupt Disabled.
* | | |1 = Timer1 interrupt Enabled.
* |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
* | | |This field is used to enable Timer2 interrupt function.
* | | |0 = Timer2 interrupt Disabled.
* | | |1 = Timer2 interrupt Enabled.
* |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
* | | |This field is used to enable block guard time interrupt in receive direction.
* | | |0 = Block guard time interrupt Disabled.
* | | |1 = Block guard time interrupt Enabled.
* | | |Note: This bit is valid only for receive receive direction block guard time.
* |[7] |CDIEN |Card Detect Interrupt Enable Bit
* | | |This field is used to enable card detect interrupt
* | | |The card detect status is CDPINSTS (SCn_STATUS[13]).
* | | |0 = Card detect interrupt Disabled.
* | | |1 = Card detect interrupt Enabled.
* |[8] |INITIEN |Initial End Interrupt Enable Bit
* | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
* | | |0 = Initial end interrupt Disabled.
* | | |1 = Initial end interrupt Enabled.
* |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit
* | | |This field is used to enable receiver buffer time-out interrupt.
* | | |0 = Receiver buffer time-out interrupt Disabled.
* | | |1 = Receiver buffer time-out interrupt Enabled.
* |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
* | | |This field is used to enable auto-convention error interrupt.
* | | |0 = Auto-convention error interrupt Disabled.
* | | |1 = Auto-convention error interrupt Enabled.
* @var SC_T::INTSTS
* Offset: 0x1C SC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
* | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
* | | |0 = Number of receive buffer is less than RXTRGLV setting.
* | | |1 = Number of receive buffer data equals the RXTRGLV setting.
* | | |Note: This bit is read only
* | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.
* |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
* | | |This field is used for transmit buffer empty interrupt status flag.
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* | | |Note: This bit is read only
* | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.
* |[2] |TERRIF |Transfer Error Interrupt Status Flag
* | | |This field is used for transfer error interrupt status flag
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt did not occur.
* | | |1 = Transfer error interrupt occurred.
* | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[3] |TMR0IF |Timer0 Interrupt Status Flag
* | | |This field is used for Timer0 interrupt status flag.
* | | |0 = Timer0 interrupt did not occur.
* | | |1 = Timer0 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[4] |TMR1IF |Timer1 Interrupt Status Flag
* | | |This field is used for Timer1 interrupt status flag.
* | | |0 = Timer1 interrupt did not occur.
* | | |1 = Timer1 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[5] |TMR2IF |Timer2 Interrupt Status Flag
* | | |This field is used for Timer2 interrupt status flag.
* | | |0 = Timer2 interrupt did not occur.
* | | |1 = Timer2 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[6] |BGTIF |Block Guard Time Interrupt Status Flag
* | | |This field is used for indicate block guard time interrupt status flag in receive direction.
* | | |0 = Block guard time interrupt did not occur.
* | | |1 = Block guard time interrupt occurred.
* | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
* | | |This field is used for card detect interrupt status flag
* | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
* | | |0 = Card detect event did not occur.
* | | |1 = Card detect event occurred.
* | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
* |[8] |INITIF |Initial End Interrupt Status Flag
* | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
* | | |0 = Initial sequence is not complete.
* | | |1 = Initial sequence is completed.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only)
* | | |This field is used for indicate receive buffer time-out interrupt status flag.
* | | |0 = Receive buffer time-out interrupt did not occur.
* | | |1 = Receive buffer time-out interrupt occurred.
* | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it.
* |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag
* | | |This field indicates auto convention sequence error.
* | | |0 = Received TS at ATR state is 0x3B or 0x3F.
* | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
* | | |Note: This bit can be cleared by writing 1 to it.
* @var SC_T::STATUS
* Offset: 0x20 SC Transfer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXOV |Receive Overflow Error Status Flag
* | | |This bit is set when Rx buffer overflow.
* | | |0 = Rx buffer is not overflow.
* | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only)
* | | |This bit indicates Rx buffer empty or not.
* | | |0 = Rx buffer is not empty.
* | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.
* |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only)
* | | |This bit indicates Rx buffer full or not.
* | | |0 = Rx buffer count is less than 4.
* | | |1 = Rx buffer count equals to 4.
* |[4] |PEF |Receiver Parity Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
* | | |0 = Receiver parity error flag did not occur.
* | | |1 = Receiver parity error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[5] |FEF |Receiver Frame Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = Receiver frame error flag did not occur.
* | | |1 = Receiver frame error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[6] |BEF |Receiver Break Error Status Flag
* | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits).
* | | |0 = Receiver break error flag did not occur.
* | | |1 = Receiver break error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag
* | | |This bit is set when Tx buffer overflow.
* | | |0 = Tx buffer is not overflow.
* | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
* | | |This bit indicates TX buffer empty or not.
* | | |0 = Tx buffer is not empty.
* | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register.
* | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
* |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
* | | |This bit indicates Tx buffer full or not.
* | | |0 = Tx buffer count is less than 4.
* | | |1 = Tx buffer count equals to 4.
* |[11] |CREMOVE |Card Removal Status of SCn_CD Pin
* | | |This bit is set whenever card has been removal.
* | | |0 = No effect.
* | | |1 = Card removed.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.
* |[12] |CINSERT |Card Insert Status of SCn_CD Pin
* | | |This bit is set whenever card has been inserted.
* | | |0 = No effect.
* | | |1 = Card insert.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.
* |[13] |CDPINSTS |Card Detect Pin Status (Read Only)
* | | |This bit is the pin status of SCn_CD.
* | | |0 = The SCn_CD pin state at low.
* | | |1 = The SCn_CD pin state at high.
* |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only)
* | | |This field indicates the Rx buffer pointer status
* | | |When SC controller receives one byte from external device, RXPOINT increases one
* | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
* |[21] |RXRERR |Receiver Retry Error
* | | |This bit is used for receiver error retry and set by hardware.
* | | |0 = No Rx retry transfer.
* | | |1 = Rx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
* | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[22] |RXOVERR |Receiver over Retry Error
* | | |This bit is used for receiver retry counts over than retry number limitation.
* | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[23] |RXACT |Receiver in Active Status Flag (Read Only)
* | | |This bit indicates Rx transfer status.
* | | |0 = This bit is cleared automatically when Rx transfer is finished.
* | | |1 = This bit is set by hardware when Rx transfer is in active.
* | | |Note: This bit is read only.
* | | |Note2:
* |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only)
* | | |This field indicates the Tx buffer pointer status
* | | |When CPU writes data into SCn_DAT, TXPOINT increases one
* | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
* |[29] |TXRERR |Transmitter Retry Error
* | | |This bit is used for indicate transmitter error retry and set by hardware..
* | | |0 = No Tx retry transfer.
* | | |1 = Tx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is a flag and cannot generate any interrupt to CPU.
* |[30] |TXOVERR |Transmitter over Retry Error
* | | |This bit is used for transmitter retry counts over than retry number limitation.
* | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1.
* | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[31] |TXACT |Transmit in Active Status Flag (Read Only)
* | | |This bit indicates Tx transmit status.
* | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed.
* | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted.
* | | |Note: This bit is read only.
* @var SC_T::PINCTL
* Offset: 0x24 SC Pin Control State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PWREN |SCn_PWR Pin Signal
* | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
* | | |Write this field to drive SCn_PWR pin
* | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
* | | |Read this field to get SCn_PWR signal status.
* | | |0 = SCn_PWR signal status is low.
* | | |1 = SCn_PWR signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[1] |RSTEN |SCn_RST Pin Signal
* | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
* | | |Write this field to drive SCn_RST pin.
* | | |0 = Drive SCn_RST pin to low.
* | | |1 = Drive SCn_RST pin to high.
* | | |Read this field to get SCn_RST signal status.
* | | |0 = SCn_RST signal status is low.
* | | |1 = SCn_RST signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[5] |CSTOPLV |SCn_CLK Pin Stop Level
* | | |This field indicates the SCn_CLK pin status when SC clock in clock stop mode.
* | | |0 = SCn_CLK pin keeps at low when SC clock stopped.
* | | |1 = SCn_CLK pin keeps at high when SC clock stopped.
* |[6] |CLKKEEP |SC Clock Enable Bit
* | | |0 = SC clock generation Disabled.
* | | |1 = SC clock always keeps free running.
* | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[9] |SCDATA |SCn_DATA Pin Signal
* | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
* | | |0 = Drive SCn_DATA pin to low.
* | | |1 = Drive SCn_DATA pin to high.
* | | |Read this field to get SCn_DATA signal status.
* | | |0 = SCn_DATA signal status is low.
* | | |1 = SCn_DATA signal status is high.
* | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when SC is in these modes.
* |[11] |PWRINV |SCn_PWR Pin Inverse
* | | |This bit is used for inverse the SCn_PWR pin.
* | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
* | | |0 = SCn_PWR pin inverse Disabled
* | | |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0.
* | | |1 = SCn_PWR pin inverse Enabled
* | | |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1.
* | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
* |[16] |DATASTS |SCn_DATA Pin Status (Read Only)
* | | |This bit is the pin status of SCn_DATA.
* | | |0 = The SCn_DATA pin status is low.
* | | |1 = The SCn_DATA pin status is high.
* | | |Note:
* |[17] |PWRSTS |SCn_PWR Pin Status (Read Only)
* | | |This bit is the pin status of SCn_PWR.
* | | |0 = SCn_PWR pin to low.
* | | |1 = SCn_PWR pin to high.
* |[18] |RSTSTS |SCn_RST Pin Status (Read Only)
* | | |This bit is the pin status of SCn_RST.
* | | |0 = SCn_RST pin is low.
* | | |1 = SCn_RST pin is high.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL0
* Offset: 0x28 SC Internal Timer0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer0 Counter Value
* | | |This field indicates the internal Timer0 counter values.
* | | |Note: Unit of Timer0 counter is ETU base.
* |[27:24] |OPMODE |Timer0 Operation Mode Selection
* | | |This field indicates the internal 24-bit Timer0 operation selection.
* | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL1
* Offset: 0x2C SC Internal Timer1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 1 Counter Value
* | | |This field indicates the internal Timer1 counter values.
* | | |Note: Unit of Timer1 counter is ETU base.
* |[27:24] |OPMODE |Timer 1 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer1 operation selection.
* | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL2
* Offset: 0x30 SC Internal Timer2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 2 Counter Value
* | | |This field indicates the internal Timer2 counter values.
* | | |Note: Unit of Timer2 counter is ETU base.
* |[27:24] |OPMODE |Timer 2 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer2 operation selection
* | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::UARTCTL
* Offset: 0x34 SC UART Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |UARTEN |UART Mode Enable Bit
* | | |Sets this bit to enable UART mode function.
* | | |0 = Smart Card mode.
* | | |1 = UART mode.
* | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
* | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
* | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
* |[5:4] |WLS |Word Length Selection
* | | |This field is used for select UART data length.
* | | |00 = Word length is 8 bits.
* | | |01 = Word length is 7 bits.
* | | |10 = Word length is 6 bits.
* | | |11 = Word length is 5 bits.
* | | |Note: In smart card mode, this WLS must be u201800'.
* |[6] |PBOFF |Parity Bit Disable Control
* | | |Sets this bit is used for disable parity check function.
* | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data.
* | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
* | | |Note: In smart card mode, this field must be u20180' (default setting is with parity bit).
* |[7] |OPE |Odd Parity Enable Bit
* | | |This is used for odd/even parity selection.
* | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |Note: This bit has effect only when PBOFF bit is u20180'.
* @var SC_T::ACTCTL
* Offset: 0x4C SC Activation Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |T1EXT |T1 Extend Time of Hardware Activation
* | | |This field provide the configurable cycles to extend the activation time T1 period.
* | | |The cycle scaling factor is 2048.
* | | |Extend cycles = (filled value * 2048) cycles.
* | | |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence.
* | | |For example,
* | | |SCLK = 4MHz, each cycle = 0.25us,.
* | | |Filled 20 to this field
* | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms.
* | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
*/
__IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */
__IO uint32_t CTL; /*!< [0x0004] SC Control Register */
__IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */
__IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */
__IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */
__IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */
__IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */
__IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */
__IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */
__IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */
__IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */
__IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */
__IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */
__IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */
__I uint32_t RESERVE0[5];
__IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */
} SC_T;
/**
@addtogroup SC_CONST SC Bit Field Definition
Constant Definitions for SC Controller
@{ */
#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */
#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */
#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */
#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */
#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */
#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */
#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */
#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */
#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */
#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */
#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */
#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */
#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */
#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */
#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */
#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */
#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */
#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */
#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */
#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */
#define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */
#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Mask */
#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */
#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */
#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */
#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */
#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */
#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */
#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */
#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */
#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */
#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */
#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */
#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */
#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */
#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */
#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */
#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */
#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */
#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */
#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */
#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */
#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */
#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */
#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */
#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */
#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */
#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */
#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */
/**@}*/ /* SC_CONST */
/**@}*/ /* end of SC register group */
#endif /* __SC_REG_H__ */

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targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/scu_reg.h Normal file
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targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/sdh_reg.h Normal file
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/**************************************************************************//**
* @file sdh_reg.h
* @version V1.00
* @brief SDH register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SDH_REG_H__
#define __SDH_REG_H__
/*---------------------- SD Card Host Interface -------------------------*/
/**
@addtogroup SDH SD Card Host Interface(SDH)
Memory Mapped Structure for SDH Controller
@{ */
typedef struct
{
/**
* @var SDH_T::FB
* Offset: 0x00~0x7C Shared Buffer (FIFO)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |BUFFER |Shared Buffer
* | | |Buffer for DMA transfer
* @var SDH_T::DMACTL
* Offset: 0x400 DMA Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMAEN |DMA Engine Enable Bit
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |0 = DMA Disabled.
* | | |1 = DMA Enabled.
* | | |Note: If target abort is occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers
* | | |The contents of control register will not be cleared
* | | |This bit will auto be cleared after few clock cycles.
* | | |Note: The software reset DMA related registers.
* |[3] |SGEN |Scatter-gather Function Enable Bit
* | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
* | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
* | | |The format of these Pads' will be described later).
* |[9] |DMABUSY |DMA Transfer Is in Progress
* | | |This bit indicates if SD Host is granted and doing DMA transfer or not.
* | | |0 = DMA transfer is not in progress.
* | | |1 = DMA transfer is in progress.
* @var SDH_T::DMASA
* Offset: 0x408 DMA Transfer Starting Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order
* | | |0 = PAD table is fetched in order.
* | | |1 = PAD table is fetched out of order.
* | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
* |[31:1] |DMASA |DMA Transfer Starting Address
* | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
* | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
* | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
* @var SDH_T::DMABCNT
* Offset: 0x40C DMA Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[25:0] |BCNT |DMA Transfer Byte Count (Read Only)
* | | |This field indicates the remained byte count of DMA transfer
* | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.
* @var SDH_T::DMAINTEN
* Offset: 0x410 DMA Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit
* | | |0 = Target abort interrupt generation Disabled during DMA transfer.
* | | |1 = Target abort interrupt generation Enabled during DMA transfer.
* |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit
* | | |0 = Interrupt generation Disabled when wrong EOT is encountered.
* | | |1 = Interrupt generation Enabled when wrong EOT is encountered.
* @var SDH_T::DMAINTSTS
* Offset: 0x414 DMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note1: This bit is read only, but can be cleared by writing '1' to it.
* | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
* | | |DMA will stop transfer and respond this event and then go to IDLE state
* | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
* |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag
* | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
* | | |0 = No EOT encountered before DMA transfer finished.
* | | |1 = EOT encountered before DMA transfer finished.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::GCTL
* Offset: 0x800 Global Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset SD host
* | | |The contents of control register will not be cleared
* | | |This bit will auto cleared after reset complete.
* |[1] |SDEN |Secure Digital Functionality Enable Bit
* | | |0 = SD functionality disabled.
* | | |1 = SD functionality enabled.
* @var SDH_T::GINTEN
* Offset: 0x804 Global Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit
* | | |0 = DMA READ/WRITE target abort interrupt generation disabled.
* | | |1 = DMA READ/WRITE target abort interrupt generation enabled.
* @var SDH_T::GINTSTS
* Offset: 0x808 Global Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
* | | |When Target Abort is occurred, please reset all engine.
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::CTL
* Offset: 0x820 SD Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |COEN |Command Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output a command to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[1] |RIEN |Response Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[2] |DIEN |Data Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[3] |DOEN |Data Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[4] |R2EN |Response R2 Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 74 clock cycles to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 8 clock cycles.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[7] |CLKKEEP0 |SD Clock Enable Control for Port 0
* | | |0 = SD host decided when to output clock and when to disable clock output automatically.
* | | |1 = SD clock always keeps free running.
* |[13:8] |CMDCODE |SD Command Code
* | | |This register contains the SD command code (0x00 ~ 0x3F).
* |[14] |CTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset the internal state machine and counters
* | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared)
* | | |This bit will be auto cleared after few clock cycles.
* |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection)
* | | |0 = Data bus width is 1-bit.
* | | |1 = Data bus width is 4-bit.
* |[23:16] |BLKCNT |Block Counts to Be Transferred or Received
* | | |This field contains the block counts for data-in and data-out transfer
* | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
* | | |Don't fill 0x0 to this field.
* | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
* |[27:24] |SDNWR |NWR Parameter for Block Write Operation
* | | |This value indicates the NWR parameter for data block write operation in SD clock counts
* | | |The actual clock cycle will be SDNWR+1.
* @var SDH_T::CMDARG
* Offset: 0x824 SD Command Argument Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ARGUMENT |SD Command Argument
* | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
* | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
* @var SDH_T::INTEN
* Offset: 0x828 SD Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit
* | | |0 = SD host will not generate interrupt when data-in (out) transfer done.
* | | |1 = SD host will generate interrupt when data-in (out) transfer done.
* |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
* | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error.
* | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error.
* |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed.
* | | |0 = SD card detection interrupt Disabled.
* | | |1 = SD card detection interrupt Enabled.
* |[12] |RTOIEN |Response Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = Response time-out interrupt Disabled.
* | | |1 = Response time-out interrupt Enabled.
* |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when data input time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = Data input time-out interrupt Disabled.
* | | |1 = Data input time-out interrupt Enabled.
* |[14] |WKIEN |Wake-up Signal Generating Enable Bit
* | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
* | | |0 = Wake-up signal generating Disabled.
* | | |1 = Wake-up signal generating Enabled.
* |[30] |CDSRC0 |SD0 Card Detect Source Selection
* | | |0 = From SD0 card's DAT3 pin.
* | | |Host need clock to got data on pin DAT3
* | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
* | | |1 = From GPIO pin.
* @var SDH_T::INTSTS
* Offset: 0x82C SD Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has finished all data-in or data-out block transfer
* | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
* | | |0 = Not finished yet.
* | | |1 = Done.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
* | | |When CRC error is occurred, software should reset SD engine
* | | |Some response (ex
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
* | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error is occurred.
* | | |1 = CRC error is occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in
* | | |If that response does not contain CRC7 information (ex
* | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
* | | |0 = Fault.
* | | |1 = OK.
* |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only)
* | | |SD host will check CRC16 correctness after data-in transfer.
* | | |0 = Fault.
* | | |1 = OK.
* |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only)
* | | |SD host will record CRC status of data-out transfer
* | | |Software could use this value to identify what type of error is during data-out transfer.
* | | |010 = Positive CRC status.
* | | |101 = Negative CRC status.
* | | |111 = SD card programming error occurs.
* |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only)
* | | |This bit is the DAT0 pin status of current selected SD port.
* |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only)
* | | |This bit indicates that SD card 0 is inserted or removed
* | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.
* | | |0 = No card is inserted or removed.
* | | |1 = There is a card inserted in or removed from SD0.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Response time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Data input time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[16] |CDSTS0 |Card Detect Status of SD0 (Read Only)
* | | |This bit indicates the card detect pin status of SD0, and is used for card detection
* | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.
* | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
* | | |0 = Card removed.
* | | |1 = Card inserted.
* | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
* | | |0 = Card inserted.
* | | |1 = Card removed.
* |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only)
* | | |This bit indicates the DAT1 pin status of SD port.
* @var SDH_T::RESP0
* Offset: 0x830 SD Receiving Response Token Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RESPTK0 |SD Receiving Response Token 0
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This field contains response bit 47-16 of the response token.
* @var SDH_T::RESP1
* Offset: 0x834 SD Receiving Response Token Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RESPTK1 |SD Receiving Response Token 1
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This register contains the bit 15-8 of the response token.
* @var SDH_T::BLEN
* Offset: 0x838 SD Block Length Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit
* | | |An 11-bit value specifies the SD transfer byte count of a block
* | | |The actual byte count is equal to BLKLEN+1.
* | | |Note: The default SD block length is 512 bytes
* @var SDH_T::TOUT
* Offset: 0x83C SD Response/Data-in Time-out Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |TOUT |SD Response/Data-in Time-out Value
* | | |A 24-bit value specifies the time-out counts of response and data input
* | | |SD host controller will wait start bit of response or data-in until this value reached
* | | |The time period depends on SD engine clock frequency
* | | |Do not write a small number into this field, or you may never get response or data due to time-out.
* | | |Note: Filling 0x0 into this field will disable hardware time-out function.
*/
__IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */
__I uint32_t RESERVE0[224];
__IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */
__I uint32_t RESERVE1[1];
__IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */
__I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */
__IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */
__IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */
__I uint32_t RESERVE2[250];
__IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */
__IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */
__IO uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */
__I uint32_t RESERVE3[5];
__IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */
__IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */
__IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */
__IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */
__I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */
__I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */
__IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */
__IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */
} SDH_T;
/**
@addtogroup SDH_CONST SDH Bit Field Definition
Constant Definitions for SDH Controller
@{ */
#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */
#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */
#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */
#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */
#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */
#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */
#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */
#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */
#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */
#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */
#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */
#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */
#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */
#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */
#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */
#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */
#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */
#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */
#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */
#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */
#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */
#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */
#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */
#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */
#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */
#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */
#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */
#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */
#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */
#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */
#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */
#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */
#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */
#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */
#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */
#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */
#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */
#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */
#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */
#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */
#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */
#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */
#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */
#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */
#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */
#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */
#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */
#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */
#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */
#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */
#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */
#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */
#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */
#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */
#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */
#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */
#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */
#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */
#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */
#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */
#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */
#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */
#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */
#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */
#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */
#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */
#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */
#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */
#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */
#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */
#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */
#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */
#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */
#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */
#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */
#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */
#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */
#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */
#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */
#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */
#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */
#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */
#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */
#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */
#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */
#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */
#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */
#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */
#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */
#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */
#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */
#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */
#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */
#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */
#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */
#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */
#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */
#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */
#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */
#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */
#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */
#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */
/**@}*/ /* SDH_CONST */
/**@}*/ /* end of SDH register group */
#endif /* __SDH_REG_H__ */

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/**************************************************************************//**
* @file spi5_reg.h
* @version V1.00
* @brief SPI5 register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI5_REG_H__
#define __SPI5_REG_H__
/*---------------------- DSRC Serial Peripheral Interface Controller -------------------------*/
/**
@addtogroup SPI5 DSRC Serial Peripheral Interface Controller(SPI5)
Memory Mapped Structure for SPI5 Controller
@{ */
typedef struct
{
/**
* @var SPI5_T::CTL
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GOBUSY |SPI Transfer Control Bit and Busy Status
* | | |0 = Writing this bit 0 will stop data transfer if SPI is transferring.
* | | |1 = In Master mode, writing 1 to this bit will start the SPI data transfer; In Slave mode, writing u20181' to this bit indicates that the slave is ready to communicate with a master.
* | | |If the FIFO mode is disabled, during the data transfer, this bit keeps the value of u20181'
* | | |As the transfer is finished, this bit will be cleared automatically
* | | |Software can read this bit to check if the SPI is in busy status.
* | | |In FIFO mode, this bit will be controlled by hardware
* | | |Software should not modify this bit
* | | |In slave mode, this bit always returns 1 when software reads this register
* | | |In master mode, this bit reflects the busy or idle status of SPI.
* | | |Note:
* | | |1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register.
* | | |2
* | | |When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = The received data is latched on the rising edge of SPI_CLK.
* | | |1 = The received data is latched on the falling edge of SPI_CLK.
* | | |Note: Refer to Edge section.
* | | |Note:
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = The transmitted data output is changed on the rising edge of SPI_CLK.
* | | |1 = The transmitted data output is changed on the falling edge of SPI_CLK.
* | | |Note: Refer to Edge section.
* | | |Note:
* |[7:3] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can be up to 32 bits.
* | | |0x1~0x7: reserved
* | | |0x8 = 8 bits are transmitted in one transaction.
* | | |0x9 = 9 bits are transmitted in one transaction.
* | | |0xA = 10 bits are transmitted in one transaction.
* | | |u2026
* | | |0x1F = 31 bits are transmitted in one transaction.
* | | |0x0 = 32 bits are transmitted in one transaction.
* | | |Note:
* |[10] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI_TX, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (SPI_RX
* | | |Note: Refer to LSB first section.
* |[11] |CLKPOL |Clock Polarity
* | | |0 = The default level of SPI_CLK is low.
* | | |1 = The default level of SPI_CLK is high.
* | | |Note: Refer to Clock Parity section.
* | | |Note:
* |[15:12] |SUSPITV |Suspend Interval (Master Only)
* | | |These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL = 0
* | | |If CLKPOL = 1, the interval is from the rising clock edge to the falling clock edge.
* | | |The default value is 0x3
* | | |The desired suspend interval is obtained according to the following equation: (SUSPITV[3:0] + 0.5) * period of SPI_CLK
* | | |For example,
* | | |SUSPITV = 0x0 u2026. 0.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0x1 u2026. 1.5 SPI_CLK clock cycle.
* | | |u2026u2026
* | | |SUSPITV = 0xE u2026. 14.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0xF u2026. 15.5 SPI_CLK clock cycle.
* | | |Note:
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = SPI unit transfer interrupt Disabled.
* | | |1 = SPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Selection
* | | |0 = SPI controller set as Master mode.
* | | |1 = SPI controller set as Slave mode.
* | | |Note: Refer to Slave Selection section
* | | |Note:
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte reorder function Disabled.
* | | |1 = Enable byte reorder function and insert a byte suspend interval among each byte
* | | |The byte reorder function is only available when DWIDTH is configured as 16, 24, and 32 bits.
* | | |Note: The suspend interval is defined in SUSPITV. Refer to Byte Reorder section.
* | | |Note: Byte Suspend is only used in SPI Byte Reorder mode.
* |[21] |FIFOM |FIFO Mode Enable Bit
* | | |0 = FIFO mode Disabled (in Normal mode).
* | | |1 = FIFO mode Enabled.
* | | |Note: Refer to FIFO Mode section.
* | | |Note:
* |[30] |WKSSEN |Wake-up by Slave Select Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* | | |Note: The Slave select wake-up function is only available in SPI Slave mode
* | | |When the system enters power-down mode, the system can be wake-up from the SPI controller if this bit and PDWKIEN (CLK_PWRCTL[5]) are enabled and there is any toggle on the SPI_SS port
* | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
* | | |Note: The wake up event will not assert the SPI interrupt, but user can read the corresponding status bit to check its occurrence.
* |[31] |WKCLKEN |Wake-up by SPI Clock Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* | | |Note: When the system enters power-down mode, the system can be wake-up from the SPI controller if this bit and PDWKIEN (CLK_PWRCTL[5]) are enabled and there is any toggle on the SPI_CLK port
* | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
* | | |Note: The wake up event will not assert the SPI interrupt, but user can read the corresponding status bit to check its occurrence.
* @var SPI5_T::STATUS
* Offset: 0x04 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Received data FIFO is not empty in the FIFO mode.
* | | |1 = Received data FIFO is empty in the FIFO mode.
* |[1] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Received data FIFO is not full in FIFO mode.
* | | |1 = Received data FIFO is full in the FIFO mode.
* |[2] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmitted data FIFO is not empty in the FIFO mode.
* | | |1 =Transmitted data FIFO is empty in the FIFO mode.
* |[3] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmitted data FIFO is not full in the FIFO mode.
* | | |1 = Transmitted data FIFO is full in the FIFO mode.
* |[4] |LTRIGF |Level Trigger Accomplish Flag (Read Only)
* | | |In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.
* | | |0 = The transferred bit length of one transaction does not meet the specified requirement.
* | | |1 = The transferred bit length meets the specified requirement which defined in DWIDTH.
* | | |Note: This bit is read only
* | | |As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period
* | | |In FIFO mode, this bit is unmeaning.
* |[6] |SLVSTAIF |Slave Start Interrupt Flag
* | | |It is used to dedicate that the transfer has started in Slave mode with no slave select.
* | | |0 = Slave started transfer no active.
* | | |1 = Transfer has started in Slave mode with no slave select
* | | |It is automatically cleared by transfer done or writing u20181'.
* |[7] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = SPI controller has finished one unit transfer.
* | | |Note 1: If SSINAIEN (SPI_SSCTL[16]) is set to 1, this bit will be asserted again when transfer is done and the slave select signal becomes inactive from active condition.
* | | |Note 2: This bit will be cleared by writing 1 to it.
* |[8] |RXTHIF |RX FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = RX valid data counts are less than or equal to RXTH (SPI_FIFOCTL[26:24]).
* | | |1 = RX valid data counts are larger than RXTH.
* | | |Note: If RXTHIEN (SPI_FIFOCTL[2]) = 1 and RXTHIF = 1, SPI will generate interrupt.
* |[9] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |0 = No FIFO overrun.
* | | |1 = Receive FIFO overrun.
* | | |Note 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.
* | | |Note 2: This bit will be cleared by writing 1 to it.
* |[10] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = TX valid data counts are larger than TXTH (SPI_FIFOCTL[30:28]).
* | | |1 = TX valid data counts are less than or equal to TXTH.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = There is not time-out event on the received buffer.
* | | |1 = Time-out event active in RX FIFO is not empty.
* | | |Refer to Time Out section.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[13] |SLVTOIF |Slave Time-out Interrupt Flag
* | | |If SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur
* | | |Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit.
* | | |0 = Slave time-out does not occur yet.
* | | |1 = Slave time-out has occurred.
* |[15] |SLVTXSKE |Slave Mode Transmit Skew Buffer Empty Status
* | | |This bit indicates the empty status of transmit skew buffer which is used in Slave mode.
* |[19:16] |RXCNT |Receive FIFO Data Counts (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[23:20] |TXCNT |Transmit FIFO Data Counts (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* |[30] |WKSSIF |Wake-up by Slave Select Interrupt Flag
* | | |When chip is woken up from power-down mode by the toggle event on SPI_SS port, this bit is set to 1
* | | |This bit can be cleared by writing u20181' to it.
* |[31] |WKCLKIF |Wake-up by SPI Clock Interrupt Flag
* | | |When chip is woken up from power-down mode by the toggle event on SPI_CLK port, this bit is set to 1
* | | |This bit can be cleared by writing u20181' to it.
* @var SPI5_T::CLKDIV
* Offset: 0x08 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DIVIDER |Clock Divider
* | | |The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_CLK
* | | |The desired frequency is obtained according to the following equation:
* | | |Where
* | | |is the SPI peripheral clock source
* | | |It is defined in the CLK_CLKSEL2[15:14] in Clock control section (CLK_BA + 0x18).
* | | |Note:
* @var SPI5_T::SSCTL
* Offset: 0x0C SPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS (SPI_SSCTL[0]) bit sets the SPI_SS line to an active state and writing 0 sets the line back to inactive state
* | | |If AUTOSS = 0,.
* | | |0 = SPI_SS is inactive.
* | | |1 =SPI_SS is active.
* | | |If AUTOSS bit is set, writing 1 to this field will select appropriate SPI_SS line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time
* | | |(The active level of SPI_SS is specified in SSACTPOL).
* | | |If AUTOSS =1,.
* | | |0 = SPI_SS is inactive.
* | | |1 = SPI_SS is active on the duration of transaction.
* | | |Note:
* | | |1
* | | |This interface can only drive one device/slave at a given time
* | | |Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
* | | |2
* | | |SPI_SS is also defined as device/slave select input in Slave mode
* | | |And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |It defines the active polarity of slave selection signal (SPI_SS).
* | | |0 = The SPI_SS slave select signal is active Low.
* | | |1 = The SPI_SS slave select signal is active High.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = If this bit is set as 0, slave select signals are asserted and de-asserted by setting and clearing related bits in SS (SPI_SSCTL[0]).
* | | |1 = If this bit is set as 1, SPI_SS signals are generated automatically
* | | |It means that device/slave select signal, which is set in SS (SPI_SSCTL[0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done.
* |[4] |SSLTRIG |Slave Select Level Trigger Control
* | | |0 = The input slave select signal is edge-trigger.
* | | |1 = The slave select signal will be level-trigger
* | | |It depends on SSACTPOL to decide the signal is active low or active high.
* |[5] |SLV3WIRE |Slave 3-wire Mode Enable Bit
* | | |This bit is used to ignore the slave select signal in Slave mode
* | | |The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.
* | | |0 = The controller is 4-wire bi-direction interface.
* | | |1 = The controller is 3-wire bi-direction interface in Slave mode
* | | |When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input.
* | | |Note 1: Refer to No Slave Select Mode.
* | | |Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically.
* |[6] |SLVTOIEN |Slave Time-out Interrupt Enable Bit
* | | |This bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur
* | | |0 = Slave time-out function and interrupt both Disabled.
* | | |1 = Slave time-out function and interrupt both Enabled.
* |[8] |SLVABORT |Abort in Slave Mode with No Slave Selected
* | | |0 = No force the slave abort.
* | | |1 = Force the current transfer done in no slave select mode.
* | | |Refer to No Slave Select Mode.
* | | |Note: It is auto cleared to 0 by hardware when the abort event is active.
* |[9] |SSTAIEN |Slave Start Interrupt Enable Bit
* | | |0 = Transfer start interrupt Disabled in no slave select mode.
* | | |1 = Transaction start interrupt Enabled in no slave select mode
* | | |It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear).
* | | |Refer to No Slave Select Mode.
* |[16] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |It is used to enable the interrupt when the transfer has done in slave mode.
* | | |0 = No any interrupt, even there is slave select inactive event.
* | | |1 = There is interrupt event when the slave select signal becomes inactive from active condition
* | | |It is used to inform the user to know that the transaction has finished and the slave select into the inactive state.
* |[29:20] |SLVTOCNT |Slave Mode Time-out Period
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var SPI5_T::RX
* Offset: 0x10 SPI Receive Data FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Receive Data Register (Read Only)
* | | |The received data can be read on it
* | | |If the FIFO bit is set as 1, the user also checks the RXEMPTY (SPI_STATUS[0]), to check if there is any more received data or not.
* @var SPI5_T::TX
* Offset: 0x20 SPI Transmit Data FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Transmit Data Register (Write Only)
* | | |The Data Transmit Registers hold the data to be transmitted in the next transfer
* | | |The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
* | | |For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer
* | | |If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.
* | | |Note:
* | | |If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1
* @var SPI5_T::PDMACTL
* Offset: 0x38 SPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Refer to PDMA section for more detail information.
* | | |Note:
* | | |1
* | | |Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.
* | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
* |[1] |RXPDMAEN |Receiving PDMA Enable Bit
* | | |0 = Receiver PDMA function Disabled.
* | | |1 = Receiver PDMA function Enabled.
* | | |Refer to PDMA section for more detail information.
* | | |Note:
* | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
* | | |In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock
* |[2] |PDMARST |PDMA Reset
* | | |It is used to reset the SPI PDMA function into default state.
* | | |0 = After reset PDMA function or in normal operation.
* | | |1 = Reset PDMA function.
* | | |Note: It is auto cleared to 0 after the reset function has done.
* @var SPI5_T::FIFOCTL
* Offset: 0x3C SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No clear the received FIFO.
* | | |1 = Clear the received FIFO.
* | | |Note: This bit is used to clear the receiver counter in FIFO Mode
* | | |This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter
* | | |After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1.
* |[1] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = Not clear the transmitted FIFO.
* | | |1 = Clear the transmitted FIFO.
* | | |Note: This bit is used to clear the transmit counter in FIFO Mode
* | | |This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter
* | | |After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1.
* |[2] |RXTHIEN |Receive Threshold Interrupt Enable Bit
* | | |0 = RX threshold interrupt Disabled.
* | | |1 = RX threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit Threshold Interrupt Enable Bit
* | | |0 = TX threshold interrupt Disabled.
* | | |1 = TX threshold interrupt Enabled.
* |[4] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = RX FIFO overrun interrupt Disabled.
* | | |1 = RX FIFO overrun interrupt Enabled.
* |[7] |RXTOIEN |RX Read Time Out Interrupt Enable Bit
* | | |0 = RX read Timeout Interrupt Disabled.
* | | |1 = RX read Timeout Interrupt Enabled.
* |[26:24] |RXTH |Received FIFO Threshold
* | | |If RX valid data counts are larger than RXTH, RXTHIF (SPI_STATUS[8]) will be set to 1..
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If TX valid data counts are less than or equal to TXTH, TXTHIF (SPI_STATUS[10]) will be set to 1.
*/
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
__IO uint32_t STATUS; /*!< [0x0004] SPI Status Register */
__IO uint32_t CLKDIV; /*!< [0x0008] SPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x000c] SPI Slave Select Control Register */
__I uint32_t RX; /*!< [0x0010] SPI Receive Data FIFO Register */
__I uint32_t RESERVE0[3];
__O uint32_t TX; /*!< [0x0020] SPI Transmit Data FIFO Register */
__I uint32_t RESERVE1[5];
__IO uint32_t PDMACTL; /*!< [0x0038] SPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x003c] SPI FIFO Control Register */
} SPI5_T;
/**
@addtogroup SPI5_CONST SPI5 Bit Field Definition
Constant Definitions for SPI5 Controller
@{ */
#define SPI5_CTL_GOBUSY_Pos (0) /*!< SPI5_T::CTL: GOBUSY Position */
#define SPI5_CTL_GOBUSY_Msk (0x1ul << SPI5_CTL_GOBUSY_Pos) /*!< SPI5_T::CTL: GOBUSY Mask */
#define SPI5_CTL_RXNEG_Pos (1) /*!< SPI5_T::CTL: RXNEG Position */
#define SPI5_CTL_RXNEG_Msk (0x1ul << SPI5_CTL_RXNEG_Pos) /*!< SPI5_T::CTL: RXNEG Mask */
#define SPI5_CTL_TXNEG_Pos (2) /*!< SPI5_T::CTL: TXNEG Position */
#define SPI5_CTL_TXNEG_Msk (0x1ul << SPI5_CTL_TXNEG_Pos) /*!< SPI5_T::CTL: TXNEG Mask */
#define SPI5_CTL_DWIDTH_Pos (3) /*!< SPI5_T::CTL: DWIDTH Position */
#define SPI5_CTL_DWIDTH_Msk (0x1ful << SPI5_CTL_DWIDTH_Pos) /*!< SPI5_T::CTL: DWIDTH Mask */
#define SPI5_CTL_LSB_Pos (10) /*!< SPI5_T::CTL: LSB Position */
#define SPI5_CTL_LSB_Msk (0x1ul << SPI5_CTL_LSB_Pos) /*!< SPI5_T::CTL: LSB Mask */
#define SPI5_CTL_CLKPOL_Pos (11) /*!< SPI5_T::CTL: CLKPOL Position */
#define SPI5_CTL_CLKPOL_Msk (0x1ul << SPI5_CTL_CLKPOL_Pos) /*!< SPI5_T::CTL: CLKPOL Mask */
#define SPI5_CTL_SUSPITV_Pos (12) /*!< SPI5_T::CTL: SUSPITV Position */
#define SPI5_CTL_SUSPITV_Msk (0xful << SPI5_CTL_SUSPITV_Pos) /*!< SPI5_T::CTL: SUSPITV Mask */
#define SPI5_CTL_UNITIEN_Pos (17) /*!< SPI5_T::CTL: UNITIEN Position */
#define SPI5_CTL_UNITIEN_Msk (0x1ul << SPI5_CTL_UNITIEN_Pos) /*!< SPI5_T::CTL: UNITIEN Mask */
#define SPI5_CTL_SLAVE_Pos (18) /*!< SPI5_T::CTL: SLAVE Position */
#define SPI5_CTL_SLAVE_Msk (0x1ul << SPI5_CTL_SLAVE_Pos) /*!< SPI5_T::CTL: SLAVE Mask */
#define SPI5_CTL_REORDER_Pos (19) /*!< SPI5_T::CTL: REORDER Position */
#define SPI5_CTL_REORDER_Msk (0x1ul << SPI5_CTL_REORDER_Pos) /*!< SPI5_T::CTL: REORDER Mask */
#define SPI5_CTL_FIFOM_Pos (21) /*!< SPI5_T::CTL: FIFOM Position */
#define SPI5_CTL_FIFOM_Msk (0x1ul << SPI5_CTL_FIFOM_Pos) /*!< SPI5_T::CTL: FIFOM Mask */
#define SPI5_CTL_WKSSEN_Pos (30) /*!< SPI5_T::CTL: WKSSEN Position */
#define SPI5_CTL_WKSSEN_Msk (0x1ul << SPI5_CTL_WKSSEN_Pos) /*!< SPI5_T::CTL: WKSSEN Mask */
#define SPI5_CTL_WKCLKEN_Pos (31) /*!< SPI5_T::CTL: WKCLKEN Position */
#define SPI5_CTL_WKCLKEN_Msk (0x1ul << SPI5_CTL_WKCLKEN_Pos) /*!< SPI5_T::CTL: WKCLKEN Mask */
#define SPI5_STATUS_RXEMPTY_Pos (0) /*!< SPI5_T::STATUS: RXEMPTY Position */
#define SPI5_STATUS_RXEMPTY_Msk (0x1ul << SPI5_STATUS_RXEMPTY_Pos) /*!< SPI5_T::STATUS: RXEMPTY Mask */
#define SPI5_STATUS_RXFULL_Pos (1) /*!< SPI5_T::STATUS: RXFULL Position */
#define SPI5_STATUS_RXFULL_Msk (0x1ul << SPI5_STATUS_RXFULL_Pos) /*!< SPI5_T::STATUS: RXFULL Mask */
#define SPI5_STATUS_TXEMPTY_Pos (2) /*!< SPI5_T::STATUS: TXEMPTY Position */
#define SPI5_STATUS_TXEMPTY_Msk (0x1ul << SPI5_STATUS_TXEMPTY_Pos) /*!< SPI5_T::STATUS: TXEMPTY Mask */
#define SPI5_STATUS_TXFULL_Pos (3) /*!< SPI5_T::STATUS: TXFULL Position */
#define SPI5_STATUS_TXFULL_Msk (0x1ul << SPI5_STATUS_TXFULL_Pos) /*!< SPI5_T::STATUS: TXFULL Mask */
#define SPI5_STATUS_LTRIGF_Pos (4) /*!< SPI5_T::STATUS: LTRIGF Position */
#define SPI5_STATUS_LTRIGF_Msk (0x1ul << SPI5_STATUS_LTRIGF_Pos) /*!< SPI5_T::STATUS: LTRIGF Mask */
#define SPI5_STATUS_SLVSTAIF_Pos (6) /*!< SPI5_T::STATUS: SLVSTAIF Position */
#define SPI5_STATUS_SLVSTAIF_Msk (0x1ul << SPI5_STATUS_SLVSTAIF_Pos) /*!< SPI5_T::STATUS: SLVSTAIF Mask */
#define SPI5_STATUS_UNITIF_Pos (7) /*!< SPI5_T::STATUS: UNITIF Position */
#define SPI5_STATUS_UNITIF_Msk (0x1ul << SPI5_STATUS_UNITIF_Pos) /*!< SPI5_T::STATUS: UNITIF Mask */
#define SPI5_STATUS_RXTHIF_Pos (8) /*!< SPI5_T::STATUS: RXTHIF Position */
#define SPI5_STATUS_RXTHIF_Msk (0x1ul << SPI5_STATUS_RXTHIF_Pos) /*!< SPI5_T::STATUS: RXTHIF Mask */
#define SPI5_STATUS_RXOVIF_Pos (9) /*!< SPI5_T::STATUS: RXOVIF Position */
#define SPI5_STATUS_RXOVIF_Msk (0x1ul << SPI5_STATUS_RXOVIF_Pos) /*!< SPI5_T::STATUS: RXOVIF Mask */
#define SPI5_STATUS_TXTHIF_Pos (10) /*!< SPI5_T::STATUS: TXTHIF Position */
#define SPI5_STATUS_TXTHIF_Msk (0x1ul << SPI5_STATUS_TXTHIF_Pos) /*!< SPI5_T::STATUS: TXTHIF Mask */
#define SPI5_STATUS_RXTOIF_Pos (12) /*!< SPI5_T::STATUS: RXTOIF Position */
#define SPI5_STATUS_RXTOIF_Msk (0x1ul << SPI5_STATUS_RXTOIF_Pos) /*!< SPI5_T::STATUS: RXTOIF Mask */
#define SPI5_STATUS_SLVTOIF_Pos (13) /*!< SPI5_T::STATUS: SLVTOIF Position */
#define SPI5_STATUS_SLVTOIF_Msk (0x1ul << SPI5_STATUS_SLVTOIF_Pos) /*!< SPI5_T::STATUS: SLVTOIF Mask */
#define SPI5_STATUS_SLVTXSKE_Pos (15) /*!< SPI5_T::STATUS: SLVTXSKE Position */
#define SPI5_STATUS_SLVTXSKE_Msk (0x1ul << SPI5_STATUS_SLVTXSKE_Pos) /*!< SPI5_T::STATUS: SLVTXSKE Mask */
#define SPI5_STATUS_RXCNT_Pos (16) /*!< SPI5_T::STATUS: RXCNT Position */
#define SPI5_STATUS_RXCNT_Msk (0xful << SPI5_STATUS_RXCNT_Pos) /*!< SPI5_T::STATUS: RXCNT Mask */
#define SPI5_STATUS_TXCNT_Pos (20) /*!< SPI5_T::STATUS: TXCNT Position */
#define SPI5_STATUS_TXCNT_Msk (0xful << SPI5_STATUS_TXCNT_Pos) /*!< SPI5_T::STATUS: TXCNT Mask */
#define SPI5_STATUS_WKSSIF_Pos (30) /*!< SPI5_T::STATUS: WKSSIF Position */
#define SPI5_STATUS_WKSSIF_Msk (0x1ul << SPI5_STATUS_WKSSIF_Pos) /*!< SPI5_T::STATUS: WKSSIF Mask */
#define SPI5_STATUS_WKCLKIF_Pos (31) /*!< SPI5_T::STATUS: WKCLKIF Position */
#define SPI5_STATUS_WKCLKIF_Msk (0x1ul << SPI5_STATUS_WKCLKIF_Pos) /*!< SPI5_T::STATUS: WKCLKIF Mask */
#define SPI5_CLKDIV_DIVIDER_Pos (0) /*!< SPI5_T::CLKDIV: DIVIDER Position */
#define SPI5_CLKDIV_DIVIDER_Msk (0xfful << SPI5_CLKDIV_DIVIDER_Pos) /*!< SPI5_T::CLKDIV: DIVIDER Mask */
#define SPI5_SSCTL_SS_Pos (0) /*!< SPI5_T::SSCTL: SS Position */
#define SPI5_SSCTL_SS_Msk (0x1ul << SPI5_SSCTL_SS_Pos) /*!< SPI5_T::SSCTL: SS Mask */
#define SPI5_SSCTL_SSACTPOL_Pos (2) /*!< SPI5_T::SSCTL: SSACTPOL Position */
#define SPI5_SSCTL_SSACTPOL_Msk (0x1ul << SPI5_SSCTL_SSACTPOL_Pos) /*!< SPI5_T::SSCTL: SSACTPOL Mask */
#define SPI5_SSCTL_AUTOSS_Pos (3) /*!< SPI5_T::SSCTL: AUTOSS Position */
#define SPI5_SSCTL_AUTOSS_Msk (0x1ul << SPI5_SSCTL_AUTOSS_Pos) /*!< SPI5_T::SSCTL: AUTOSS Mask */
#define SPI5_SSCTL_SSLTRIG_Pos (4) /*!< SPI5_T::SSCTL: SSLTRIG Position */
#define SPI5_SSCTL_SSLTRIG_Msk (0x1ul << SPI5_SSCTL_SSLTRIG_Pos) /*!< SPI5_T::SSCTL: SSLTRIG Mask */
#define SPI5_SSCTL_SLV3WIRE_Pos (5) /*!< SPI5_T::SSCTL: SLV3WIRE Position */
#define SPI5_SSCTL_SLV3WIRE_Msk (0x1ul << SPI5_SSCTL_SLV3WIRE_Pos) /*!< SPI5_T::SSCTL: SLV3WIRE Mask */
#define SPI5_SSCTL_SLVTOIEN_Pos (6) /*!< SPI5_T::SSCTL: SLVTOIEN Position */
#define SPI5_SSCTL_SLVTOIEN_Msk (0x1ul << SPI5_SSCTL_SLVTOIEN_Pos) /*!< SPI5_T::SSCTL: SLVTOIEN Mask */
#define SPI5_SSCTL_SLVABORT_Pos (8) /*!< SPI5_T::SSCTL: SLVABORT Position */
#define SPI5_SSCTL_SLVABORT_Msk (0x1ul << SPI5_SSCTL_SLVABORT_Pos) /*!< SPI5_T::SSCTL: SLVABORT Mask */
#define SPI5_SSCTL_SSTAIEN_Pos (9) /*!< SPI5_T::SSCTL: SSTAIEN Position */
#define SPI5_SSCTL_SSTAIEN_Msk (0x1ul << SPI5_SSCTL_SSTAIEN_Pos) /*!< SPI5_T::SSCTL: SSTAIEN Mask */
#define SPI5_SSCTL_SSINAIEN_Pos (16) /*!< SPI5_T::SSCTL: SSINAIEN Position */
#define SPI5_SSCTL_SSINAIEN_Msk (0x1ul << SPI5_SSCTL_SSINAIEN_Pos) /*!< SPI5_T::SSCTL: SSINAIEN Mask */
#define SPI5_SSCTL_SLVTOCNT_Pos (20) /*!< SPI5_T::SSCTL: SLVTOCNT Position */
#define SPI5_SSCTL_SLVTOCNT_Msk (0x3fful << SPI5_SSCTL_SLVTOCNT_Pos) /*!< SPI5_T::SSCTL: SLVTOCNT Mask */
#define SPI5_RX_RX_Pos (0) /*!< SPI5_T::RX: RX Position */
#define SPI5_RX_RX_Msk (0xfffffffful << SPI5_RX_RX_Pos) /*!< SPI5_T::RX: RX Mask */
#define SPI5_TX_TX_Pos (0) /*!< SPI5_T::TX: TX Position */
#define SPI5_TX_TX_Msk (0xfffffffful << SPI5_TX_TX_Pos) /*!< SPI5_T::TX: TX Mask */
#define SPI5_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI5_T::PDMACTL: TXPDMAEN Position */
#define SPI5_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI5_PDMACTL_TXPDMAEN_Pos) /*!< SPI5_T::PDMACTL: TXPDMAEN Mask */
#define SPI5_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI5_T::PDMACTL: RXPDMAEN Position */
#define SPI5_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI5_PDMACTL_RXPDMAEN_Pos) /*!< SPI5_T::PDMACTL: RXPDMAEN Mask */
#define SPI5_PDMACTL_PDMARST_Pos (2) /*!< SPI5_T::PDMACTL: PDMARST Position */
#define SPI5_PDMACTL_PDMARST_Msk (0x1ul << SPI5_PDMACTL_PDMARST_Pos) /*!< SPI5_T::PDMACTL: PDMARST Mask */
#define SPI5_FIFOCTL_RXFBCLR_Pos (0) /*!< SPI5_T::FIFOCTL: RXFBCLR Position */
#define SPI5_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI5_FIFOCTL_RXFBCLR_Pos) /*!< SPI5_T::FIFOCTL: RXFBCLR Mask */
#define SPI5_FIFOCTL_TXFBCLR_Pos (1) /*!< SPI5_T::FIFOCTL: TXFBCLR Position */
#define SPI5_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI5_FIFOCTL_TXFBCLR_Pos) /*!< SPI5_T::FIFOCTL: TXFBCLR Mask */
#define SPI5_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI5_T::FIFOCTL: RXTHIEN Position */
#define SPI5_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI5_FIFOCTL_RXTHIEN_Pos) /*!< SPI5_T::FIFOCTL: RXTHIEN Mask */
#define SPI5_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI5_T::FIFOCTL: TXTHIEN Position */
#define SPI5_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI5_FIFOCTL_TXTHIEN_Pos) /*!< SPI5_T::FIFOCTL: TXTHIEN Mask */
#define SPI5_FIFOCTL_RXOVIEN_Pos (4) /*!< SPI5_T::FIFOCTL: RXOVIEN Position */
#define SPI5_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI5_FIFOCTL_RXOVIEN_Pos) /*!< SPI5_T::FIFOCTL: RXOVIEN Mask */
#define SPI5_FIFOCTL_RXTOIEN_Pos (7) /*!< SPI5_T::FIFOCTL: RXTOIEN Position */
#define SPI5_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI5_FIFOCTL_RXTOIEN_Pos) /*!< SPI5_T::FIFOCTL: RXTOIEN Mask */
#define SPI5_FIFOCTL_RXTH_Pos (24) /*!< SPI5_T::FIFOCTL: RXTH Position */
#define SPI5_FIFOCTL_RXTH_Msk (0x7ul << SPI5_FIFOCTL_RXTH_Pos) /*!< SPI5_T::FIFOCTL: RXTH Mask */
#define SPI5_FIFOCTL_TXTH_Pos (28) /*!< SPI5_T::FIFOCTL: TXTH Position */
#define SPI5_FIFOCTL_TXTH_Msk (0x7ul << SPI5_FIFOCTL_TXTH_Pos) /*!< SPI5_T::FIFOCTL: TXTH Mask */
/**@}*/ /* SPI5_CONST */
/**@}*/ /* end of SPI5 register group */
#endif /* __SPI5_REG_H__ */

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/**************************************************************************//**
* @file spi_reg.h
* @version V1.00
* @brief SPI register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI_REG_H__
#define __SPI_REG_H__
/*---------------------- Serial Peripheral Interface Controller -------------------------*/
/**
@addtogroup SPI Serial Peripheral Interface Controller(SPI)
Memory Mapped Structure for SPI Controller
@{ */
typedef struct
{
/**
* @var SPI_T::CTL
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |SPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = SPI bus clock is idle low.
* | | |1 = SPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle.
* | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle.
* | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 .... 8 bits.
* | | |DWIDTH = 0x09 .... 9 bits.
* | | |.....
* | | |DWIDTH = 0x1F .... 31 bits.
* | | |DWIDTH = 0x00 .... 32 bits.
* | | |Note: For SPI0~SPI3, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI0~SPI3.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
* |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for SPI transfer
* | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = SPI operates in full-duplex transfer.
* | | |1 = SPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = SPI unit transfer interrupt Disabled.
* | | |1 = SPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = SPI data is input direction.
* | | |1 = SPI data is output direction.
* @var SPI_T::CLKDIV
* Offset: 0x04 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* | | |Note: Not supported in I2S mode.
* @var SPI_T::SSCTL
* Offset: 0x08 SPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the SPIx_SS line to inactive state.
* | | |1 = set the SPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the SPIx_SS line at inactive state.
* | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (SPIx_SS).
* | | |0 = The slave selection signal SPIx_SS is active low.
* | | |1 = The slave selection signal SPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* @var SPI_T::PDMACTL
* Offset: 0x0C SPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
* @var SPI_T::FIFOCTL
* Offset: 0x10 SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. This bit should be set as 0 in I2S mode.
* | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
* @var SPI_T::STATUS
* Offset: 0x14 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = SPI controller is in idle state.
* | | |1 = SPI controller is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d.
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |e.
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = SPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurs.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurs.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |SPI Enable Status (Read Only)
* | | |0 = The SPI controller is disabled.
* | | |1 = The SPI controller is enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var SPI_T::TX
* Offset: 0x20 SPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
* | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
* | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
* | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var SPI_T::RX
* Offset: 0x30 SPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register (Read Only)
* | | |There are 4-level FIFO buffers in this controller.
* | | |The data receive register holds the data received from SPI data input pin.
* | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
* @var SPI_T::I2SCTL
* Offset: 0x60 I2S Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Bit
* | | |0 = Disabled I2S mode.
* | | |1 = Enabled I2S mode.
* | | |Note:
* | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode.
* | | |2
* | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
* |[1] |TXEN |Transmit Enable Bit
* | | |0 = Data transmit Disabled.
* | | |1 = Data transmit Enabled.
* |[2] |RXEN |Receive Enable Bit
* | | |0 = Data receive Disabled.
* | | |1 = Data receive Enabled.
* |[3] |MUTE |Transmit Mute Enable Bit
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Transmit channel zero.
* |[5:4] |WDWIDTH |Word Width
* | | |00 = data size is 8-bit.
* | | |01 = data size is 16-bit.
* | | |10 = data size is 24-bit.
* | | |11 = data size is 32-bit.
* |[6] |MONO |Monaural Data
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |0 = Left channel data at high byte.
* | | |1 = Left channel data at low byte.
* |[8] |SLAVE |Slave Mode
* | | |I2S can operate as master or slave
* | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M2351 series to audio CODEC chip
* | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[15] |MCLKEN |Master Clock Enable Bit
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Right channel zero cross detection Disabled.
* | | |1 = Right channel zero cross detection Enabled.
* |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Left channel zero cross detection Disabled.
* | | |1 = Left channel zero cross detection Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Bit
* | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
* | | |0 = Receive right channel data in Mono mode.
* | | |1 = Receive left channel data in Mono mode.
* |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[29:28] |FORMAT |Data Format Selection
* | | |00 = I2S data format.
* | | |01 = MSB justified data format.
* | | |10 = PCM mode A.
* | | |11 = PCM mode B.
* @var SPI_T::I2SCLK
* Offset: 0x64 I2S Clock Divider Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |MCLKDIV |Master Clock Divider
* | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
* | | |The frequency of master clock, F_MCLK, is determined by the following expressions:
* | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
* | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
* | | |F_I2SCLK is the frequency of I2S peripheral clock.
* | | |In general, the master clock rate is 256 times sampling clock rate.
* |[17:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode.
* | | |The clock frequency of bit clock, F_BCLK, is determined by the following expression:
* | | |F_BCLK = F_I2SCLK/(2x(BCLKDIV + 1)),
* | | |where
* | | |F_I2SCLK is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
* | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by F_I2SCLK/(BCLKDIV/2 + 1).
* | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
* @var SPI_T::I2SSTS
* Offset: 0x68 I2S Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4] |RIGHT |Right Channel (Read Only)
* | | |This bit indicates the current transmit data is belong to which channel.
* | | |0 = Left channel.
* | | |1 = Right channel.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |I2SENSTS |I2S Enable Status (Read Only)
* | | |0 = The SPI/I2S control logic is disabled.
* | | |1 = The SPI/I2S control logic is enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
* | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on right channel.
* | | |1 = Zero cross event occurred on right channel.
* |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on left channel.
* | | |1 = Zero cross event occurred on left channel.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
*/
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */
__I uint32_t RESERVE0[2];
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
__I uint32_t RESERVE2[11];
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */
} SPI_T;
/**
@addtogroup SPI_CONST SPI Bit Field Definition
Constant Definitions for SPI Controller
@{ */
#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */
#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */
#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */
#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */
#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */
#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */
#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
/**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */
#endif /* __SPI_REG_H__ */

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/**************************************************************************//**
* @file trng_reg.h
* @version V1.00
* @brief TRNG register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TRNG_REG_H__
#define __TRNG_REG_H__
/*---------------------- True Random Number Generator -------------------------*/
/**
@addtogroup TRNG True Random Number Generator(TRNG)
Memory Mapped Structure for TRNG Controller
@{ */
typedef struct
{
/**
* @var TRNG_T::CTL
* Offset: 0x00 TRNG Control Register and Status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TRNGEN |Random Number Generator Enable Bit
* | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.
* | | |0 = TRNG disabled.
* | | |1 = TRNG enabled.
* | | |Note: TRNGEN is an enable bit of digital part
* | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.
* |[1] |DVIF |Data Valid (Read Only)
* | | |0 = Data is not valid. Reading from RNGD returns 0x00000000.
* | | |1 = Data is valid. A valid random number can be read form RNGD.
* | | |This bit is cleared to u20180u2019 by read TRNG_DATA.
* |[5:2] |CLKP |Clock Prescaler
* | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation)
* | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module.
* | | |0000 = 80 ~ 100 MHz.
* | | |0001 = 60 ~ 80 MHz.
* | | |0010 = 50 ~60 MHz.
* | | |0011 = 40 ~50 MHz.
* | | |0100 = 30 ~40 MHz.
* | | |0101 = 25 ~30 MHz.
* | | |0110 = 20 ~25 MHz.
* | | |0111 = 15 ~20 MHz.
* | | |1000 = 12 ~15 MHz.
* | | |1001 = 9 ~12 MHz.
* | | |1010 = 7 ~9 MHz.
* | | |1011 = 6 ~7 MHz.
* | | |1100 = 5 ~6 MHz.
* | | |1101 = 4 ~5 MHz.
* | | |1111 = Reserved.
* |[6] |DVIEN |Data Valid Interrupt Enable Bit
* | | |0 = Interrupt disabled..
* | | |1 = Interrupt enabled.
* |[7] |READY |Random Number Generator Ready (Read Only)
* | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us.
* | | |0 = RNG is not ready or was not activated.
* | | |1 = RNG is ready to be enabled..
* |[31:8] |Reversed |Reversed
* @var TRNG_T::DATA
* Offset: 0x04 TRNG Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DATA |Random Number Generator Data (Read Only)
* | | |The DATA store the random number generated by TRNG and can be read only once.
* @var TRNG_T::ACT
* Offset: 0x0C TRNG Activation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |VER |TRNG Version
* | | |TRNG version number is dependent on TRNG module.
* | | |0x02:(Current Version Number)
* |[7] |ACT |Random Number Generator Activation
* | | |After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.
* | | |0 = TRNG inactive.
* | | |1 = TRNG active.
* | | |Note: ACT is an enable bit of analog part
* | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.
*/
__IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */
__I uint32_t DATA; /*!< [0x0004] TRNG Data Register */
__I uint32_t RESERVE0[1];
__IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */
} TRNG_T;
/**
@addtogroup TRNG_CONST TRNG Bit Field Definition
Constant Definitions for TRNG Controller
@{ */
#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */
#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */
#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */
#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */
#define TRNG_CTL_CLKP_Pos (2) /*!< TRNG_T::CTL: CLKP Position */
#define TRNG_CTL_CLKP_Msk (0xful << TRNG_CTL_CLKP_Pos) /*!< TRNG_T::CTL: CLKP Mask */
#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */
#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */
#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */
#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */
#define TRNG_CTL_Reversed_Pos (8) /*!< TRNG_T::CTL: Reversed Position */
#define TRNG_CTL_Reversed_Msk (0xfffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */
#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */
#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */
#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */
#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */
#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */
#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */
/**@}*/ /* TRNG_CONST */
/**@}*/ /* end of TRNG register group */
#endif /* __TRNG_REG_H__ */

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/**************************************************************************//**
* @file ui2c_reg.h
* @version V1.00
* @brief UI2C register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UI2C_REG_H__
#define __UI2C_REG_H__
/*---------------------- I2C Mode of USCI Controller -------------------------*/
/**
@addtogroup UI2C I2C Mode of USCI Controller(UI2C)
Memory Mapped Structure for UI2C Controller
@{ */
typedef struct
{
/**
* @var UI2C_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var UI2C_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK = fDIV_CLK.
* | | |01 = fSAMP_CLK = fPROT_CLK.
* | | |10 = fSAMP_CLK = fSCLK.
* | | |11 = fSAMP_CLK = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UI2C_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits.
* @var UI2C_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UI2C_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
* | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]).
* @var UI2C_T::DEVADDR0
* Offset: 0x44 USCI Device Address Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
* @var UI2C_T::DEVADDR1
* Offset: 0x48 USCI Device Address Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
* @var UI2C_T::ADDRMSK0
* Offset: 0x4C USCI Device Address Mask Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not set address mask.
* @var UI2C_T::ADDRMSK1
* Offset: 0x50 USCI Device Address Mask Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not set address mask.
* @var UI2C_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* @var UI2C_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var UI2C_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCFUNC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[1] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
* |[2] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
* | | |In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode when bus error (UI2C_PROTSTS.ERRIF = 1).
* |[3] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[4] |ADDR10EN |Address 10-bit Function Enable Bit
* | | |0 = Address match 10 bit function is disabled.
* | | |1 = Address match 10 bit function is enabled.
* |[5] |PTRG |I2C Protocol Trigger (Write Only)
* | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
* | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
* | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
* | | |1 = I2C's stretch active.
* |[8] |SCLOUTEN |SCL Output Enable Bit
* | | |This bit enables monitor pulling SCL to low
* | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
* | | |0 = SCL output will be forced high due to open drain mechanism.
* | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
* |[9] |MONEN |Monitor Mode Enable Bit
* | | |This bit enables monitor mode
* | | |In monitor mode the SDA output will be put in high impedance mode
* | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
* | | |0 = The monitor mode is disabled.
* | | |1 = The monitor mode is enabled.
* | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
* |[25:16] |TOCNT |Time-out Clock Cycle
* | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear
* | | |The time-out is enable when TOCNT bigger than 0.
* | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
* |[31] |PROTEN |I2C Protocol Enable Bit
* | | |0 = I2C Protocol disable.
* | | |1 = I2C Protocol enable.
* @var UI2C_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIEN |Time-out Interrupt Enable Control
* | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
* | | |0 = The time-out interrupt is disabled.
* | | |1 = The time-out interrupt is enabled.
* |[1] |STARIEN |Start Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a start condition is detected.
* | | |0 = The start condition interrupt is disabled.
* | | |1 = The start condition interrupt is enabled.
* |[2] |STORIEN |Stop Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a stop condition is detected.
* | | |0 = The stop condition interrupt is disabled.
* | | |1 = The stop condition interrupt is enabled.
* |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
* | | |0 = The non - acknowledge interrupt is disabled.
* | | |1 = The non - acknowledge interrupt is enabled.
* |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
* | | |0 = The arbitration lost interrupt is disabled.
* | | |1 = The arbitration lost interrupt is enabled.
* |[5] |ERRIEN |Error Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
* | | |0 = The error interrupt is disabled.
* | | |1 = The error interrupt is enabled.
* |[6] |ACKIEN |Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
* | | |0 = The acknowledge interrupt is disabled.
* | | |1 = The acknowledge interrupt is enabled.
* @var UI2C_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5] |TOIF |Time-out Interrupt Flag
* | | |0 = A time-out interrupt status has not occurred.
* | | |1 = A time-out interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit
* |[6] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[8] |STARIF |Start Condition Received Interrupt Flag
* | | |This bit indicates that a start condition or repeated start condition has been detected on master mode
* | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1.
* | | |0 = A start condition has not yet been detected.
* | | |1 = A start condition has been detected.
* | | |It is cleared by software writing one into this bit
* |[9] |STORIF |Stop Condition Received Interrupt Flag
* | | |This bit indicates that a stop condition has been detected on the I2C bus lines
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1.
* | | |0 = A stop condition has not yet been detected.
* | | |1 = A stop condition has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave RX mode.
* |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag
* | | |This bit indicates that a non - acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1.
* | | |0 = A non - acknowledge has not been received.
* | | |1 = A non - acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[11] |ARBLOIF |Arbitration Lost Interrupt Flag
* | | |This bit indicates that an arbitration has been lost
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1.
* | | |0 = An arbitration has not been lost.
* | | |1 = An arbitration has been lost.
* | | |It is cleared by software writing one into this bit
* |[12] |ERRIF |Error Interrupt Flag
* | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1.
* | | |0 = An I2C error has not been detected.
* | | |1 = An I2C error has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode.
* |[13] |ACKIF |Acknowledge Received Interrupt Flag
* | | |This bit indicates that an acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1.
* | | |0 = An acknowledge has not been received.
* | | |1 = An acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[14] |SLASEL |Slave Select Status
* | | |This bit indicates that this device has been selected as slave.
* | | |0 = The device is not selected as slave.
* | | |1 = The device is selected as slave.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[15] |SLAREAD |Slave Read Request Status
* | | |This bit indicates that a slave read request has been detected.
* | | |0 = A slave R/W bit is 1 has not been detected.
* | | |1 = A slave R/W bit is 1 has been detected.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release when WKUPIF is set.
* |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* |[18] |BUSHANG |Bus Hang-up
* | | |This bit indicates bus hang-up status
* | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
* | | |The hang-up counter will count to overflow and set this bit when SDA is low
* | | |The counter will be reset by falling edge of SCL signal.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is hang-up status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* |[19] |ERRARBLO |Error Arbitration Lost
* | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
* | | |The I2C can send start condition when ERRARBLO is set
* | | |Thus this bit doesn't be cared on slave mode.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is error arbitration lost status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* @var UI2C_T::ADMAT
* Offset: 0x88 I2C Slave Match Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |USCI Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |USCI Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* @var UI2C_T::TMCTL
* Offset: 0x8C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
* | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge SDA edge in
* | | |transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__I uint32_t RESERVE0[1];
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
__I uint32_t RESERVE1[8];
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__I uint32_t RESERVE2[3];
__IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */
__IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */
__IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */
__IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
__I uint32_t RESERVE3[8];
__IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */
__IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */
} UI2C_T;
/**
@addtogroup UI2C_CONST UI2C Bit Field Definition
Constant Definitions for UI2C Controller
@{ */
#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */
#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */
#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */
#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */
#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */
#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */
#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */
#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */
#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */
#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */
#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */
#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */
#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */
#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */
#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */
#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */
#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */
#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */
#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */
#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */
#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */
#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */
#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */
#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */
#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */
#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */
#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */
#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */
#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */
#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */
#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */
#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */
#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */
#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */
#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */
#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */
#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */
#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */
#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */
#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */
#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */
#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */
#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */
#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */
#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */
#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */
#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */
#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */
#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */
#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */
#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */
#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */
#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */
#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */
#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */
#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */
#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */
#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */
#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */
#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */
#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */
#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */
#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */
#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */
#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */
#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */
#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */
#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */
#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */
#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */
#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */
#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */
#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */
#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */
#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */
#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */
#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */
#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */
#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */
#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */
#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */
#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */
#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */
#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */
#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */
#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */
#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */
#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */
#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */
#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */
#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */
#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */
#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */
#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */
#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */
#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */
#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */
#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */
#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */
#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */
#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */
#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */
#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */
#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */
#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */
#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */
#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */
#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */
#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */
#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */
/**@}*/ /* UI2C_CONST */
/**@}*/ /* end of UI2C register group */
#endif /* __UI2C_REG_H__ */

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/**************************************************************************//**
* @file usbd_reg.h
* @version V1.00
* @brief USBD register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USBD_REG_H__
#define __USBD_REG_H__
/*---------------------- USB Device Controller -------------------------*/
/**
@addtogroup USBD USB Device Controller(USBD)
Memory Mapped Structure for USBD Controller
@{ */
/**
* @brief USBD endpoints register
*/
typedef struct
{
/**
* @var USBD_EP_T::BUFSEG
* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0 Endpoint Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |BUFSEG |Endpoint Buffer Segmentation
* | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
* | | |USBD_SRAM address + { BUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Refer to the section 6.29.5.7 for the endpoint SRAM structure and its description.
* @var USBD_EP_T::MXPLD
* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4 Endpoint Maximal Payload Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |MXPLD |Maximal Payload
* | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
* | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
* | | |(1) When the register is written by CPU,
* | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
* | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
* | | |(2) When the register is read by CPU,
* | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
* | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
* | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
* @var USBD_EP_T::CFG
* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8 Endpoint Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPNUM |Endpoint Number
* | | |These bits are used to define the endpoint number of the current endpoint
* |[4] |ISOCH |Isochronous Endpoint
* | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
* | | |0 = No Isochronous endpoint.
* | | |1 = Isochronous endpoint.
* |[6:5] |STATE |Endpoint STATE
* | | |00 = Endpoint is Disabled.
* | | |01 = Out endpoint.
* | | |10 = IN endpoint.
* | | |11 = Undefined.
* |[7] |DSQSYNC |Data Sequence Synchronization
* | | |0 = DATA0 PID.
* | | |1 = DATA1 PID.
* | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
* | | |hardware will toggle automatically in IN token base on the bit.
* |[9] |CSTALL |Clear STALL Response
* | | |0 = Disable the device to clear the STALL handshake in setup stage.
* | | |1 = Clear the device to response STALL handshake in setup stage.
* @var USBD_EP_T::CFGP
* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC Endpoint Set Stall and Clear In/Out Ready Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CLRRDY |Clear Ready
* | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
* | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
* | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
* | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
* | | |This bit is write 1 only and is always 0 when it is read back.
* |[1] |SSTALL |Set STALL
* | | |0 = Disable the device to response STALL.
* | | |1 = Set the device to respond STALL automatically.
*/
__IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */
__IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */
__IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */
__IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */
} USBD_EP_T;
typedef struct
{
/**
* @var USBD_T::INTEN
* Offset: 0x00 USB Device Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIEN |Bus Event Interrupt Enable Bit
* | | |0 = BUS event interrupt Disabled.
* | | |1 = BUS event interrupt Enabled.
* |[1] |USBIEN |USB Event Interrupt Enable Bit
* | | |0 = USB event interrupt Disabled.
* | | |1 = USB event interrupt Enabled.
* |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit
* | | |0 = VBUS detection Interrupt Disabled.
* | | |1 = VBUS detection Interrupt Enabled.
* |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit
* | | |0 = No-event-wake-up Interrupt Disabled.
* | | |1 = No-event-wake-up Interrupt Enabled.
* |[4] |SOFIEN |Start of Frame Interrupt Enable Bit
* | | |0 = SOF Interrupt Disabled.
* | | |1 = SOF Interrupt Enabled.
* |[8] |WKEN |Wake-up Function Enable Bit
* | | |0 = USB wake-up function Disabled.
* | | |1 = USB wake-up function Enabled.
* |[15] |INNAKEN |Active NAK Function and Its Status in IN Token
* | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
* | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
* @var USBD_T::INTSTS
* Offset: 0x04 USB Device Interrupt Event Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIF |BUS Interrupt Status
* | | |The BUS event means that there is one of the suspense or the resume function in the bus.
* | | |0 = No BUS event occurred.
* | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
* |[1] |USBIF |USB Event Interrupt Status
* | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
* | | |0 = No USB event occurred.
* | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
* |[2] |VBDETIF |VBUS Detection Interrupt Status
* | | |0 = There is not attached/detached event in the USB.
* | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
* |[3] |NEVWKIF |No-event-wake-up Interrupt Status
* | | |0 = NEVWK event does not occur.
* | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
* |[4] |SOFIF |Start of Frame Interrupt Status
* | | |0 = SOF event does not occur.
* | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
* |[16] |EPEVT0 |Endpoint 0's USB Event Status
* | | |0 = No event occurred in endpoint 0.
* | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
* |[17] |EPEVT1 |Endpoint 1's USB Event Status
* | | |0 = No event occurred in endpoint 1.
* | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
* |[18] |EPEVT2 |Endpoint 2's USB Event Status
* | | |0 = No event occurred in endpoint 2.
* | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
* |[19] |EPEVT3 |Endpoint 3's USB Event Status
* | | |0 = No event occurred in endpoint 3.
* | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
* |[20] |EPEVT4 |Endpoint 4's USB Event Status
* | | |0 = No event occurred in endpoint 4.
* | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
* |[21] |EPEVT5 |Endpoint 5's USB Event Status
* | | |0 = No event occurred in endpoint 5.
* | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
* |[22] |EPEVT6 |Endpoint 6's USB Event Status
* | | |0 = No event occurred in endpoint 6.
* | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
* |[23] |EPEVT7 |Endpoint 7's USB Event Status
* | | |0 = No event occurred in endpoint 7.
* | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
* |[24] |EPEVT8 |Endpoint 8's USB Event Status
* | | |0 = No event occurred in endpoint 8.
* | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
* |[25] |EPEVT9 |Endpoint 9's USB Event Status
* | | |0 = No event occurred in endpoint 9.
* | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
* |[26] |EPEVT10 |Endpoint 10's USB Event Status
* | | |0 = No event occurred in endpoint 10.
* | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
* |[27] |EPEVT11 |Endpoint 11's USB Event Status
* | | |0 = No event occurred in endpoint 11.
* | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
* |[31] |SETUP |Setup Event Status
* | | |0 = No Setup event.
* | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
* @var USBD_T::FADDR
* Offset: 0x08 USB Device Function Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |FADDR |USB Device Function Address
* @var USBD_T::EPSTS
* Offset: 0x0C USB Device Endpoint Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |OV |Overrun
* | | |It indicates that the received data is over the maximum payload number or not.
* | | |0 = No overrun.
* | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
* @var USBD_T::ATTR
* Offset: 0x10 USB Device Bus Status and Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBRST |USB Reset Status
* | | |0 = Bus no reset.
* | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
* | | |Note: This bit is read only.
* |[1] |SUSPEND |Suspend Status
* | | |0 = Bus no suspend.
* | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
* | | |Note: This bit is read only.
* |[2] |RESUME |Resume Status
* | | |0 = No bus resume.
* | | |1 = Resume from suspend.
* | | |Note: This bit is read only.
* |[3] |TOUT |Time-out Status
* | | |0 = No time-out.
* | | |1 = No Bus response more than 18 bits time.
* | | |Note: This bit is read only.
* |[4] |PHYEN |PHY Transceiver Function Enable Bit
* | | |0 = PHY transceiver function Disabled.
* | | |1 = PHY transceiver function Enabled.
* |[5] |RWAKEUP |Remote Wake-up
* | | |0 = Release the USB bus from K state.
* | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
* |[7] |USBEN |USB Controller Enable Bit
* | | |0 = USB Controller Disabled.
* | | |1 = USB Controller Enabled.
* |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit
* | | |0 = Pull-up resistor in USB_D+ bus Disabled.
* | | |1 = Pull-up resistor in USB_D+ bus Active.
* |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
* | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
* | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
* |[11] |LPMACK |LPM Token Acknowledge Enable Bit
* | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
* | | |0= the valid LPM Token will be NYET.
* | | |1= the valid LPM Token will be ACK.
* |[12] |L1SUSPEND |LPM L1 Suspend
* | | |0 = Bus no L1 state suspend.
* | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
* | | |Note: This bit is read only.
* |[13] |L1RESUME |LPM L1 Resume
* | | |0 = Bus no LPM L1 state resume.
* | | |1 = LPM L1 state Resume from LPM L1 state suspend.
* | | |Note: This bit is read only.
* @var USBD_T::VBUSDET
* Offset: 0x14 USB Device VBUS Detection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDET |Device VBUS Detection
* | | |0 = Controller is not attached to the USB host.
* | | |1 = Controller is attached to the USB host.
* @var USBD_T::STBUFSEG
* Offset: 0x18 SETUP Token Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation
* | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
* | | |USBD_SRAM address + {STBUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Note: It is used for SETUP token only.
* @var USBD_T::EPSTS0
* Offset: 0x20 USB Device Endpoint Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPSTS0 |Endpoint 0 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[7:4] |EPSTS1 |Endpoint 1 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:8] |EPSTS2 |Endpoint 2 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS3 |Endpoint 3 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[19:16] |EPSTS4 |Endpoint 4 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[23:20] |EPSTS5 |Endpoint 5 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[27:24] |EPSTS6 |Endpoint 6 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[31:28] |EPSTS7 |Endpoint 7 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::EPSTS1
* Offset: 0x24 USB Device Endpoint Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPSTS8 |Endpoint 8 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[7:4] |EPSTS9 |Endpoint 9 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:8] |EPSTS10 |Endpoint 10 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS11 |Endpoint 11 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::LPMATTR
* Offset: 0x88 USB LPM Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |LPMLINKSTS|LPM Link State
* | | |These bits contain the bLinkState received with last ACK LPM Token
* | | |0000 = Reserve.
* | | |0001 = L1 (Sleep).
* | | |0010 - 1111 = Reserve.
* |[7:4] |LPMBESL |LPM Best Effort Service Latency
* | | |These bits contain the BESL value received with last ACK LPM Token
* | | |0000 = 125us.
* | | |0001 = 150us.
* | | |0010 = 200us.
* | | |0011 = 300us.
* | | |0100 = 400us.
* | | |0101 = 500us.
* | | |0110 = 1000us.
* | | |0111 = 2000us.
* | | |1000 = 3000us.
* | | |1001 = 4000us.
* | | |1010 = 5000us.
* | | |1011 = 6000us.
* | | |1100 = 7000us.
* | | |1101 = 8000us.
* | | |1110 = 9000us.
* | | |1111 = 10000us.
* |[8] |LPMRWAKUP |LPM Remote Wakeup
* | | |This bit contains the bRemoteWake value received with last ACK LPM Token
* @var USBD_T::FN
* Offset: 0x8C USB Frame number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |FN |Frame Number
* | | |These bits contain the 11-bits frame number in the last received SOF packet.
* @var USBD_T::SE0
* Offset: 0x90 USB Device Drive SE0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SE0 |Drive Single Ended Zero in USB Bus
* | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
* | | |0 = Normal operation.
* | | |1 = Force USB PHY transceiver to drive SE0.
*/
__IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */
__IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */
__I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */
__IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */
__I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */
__IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */
__I uint32_t RESERVE0[1];
__I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */
__I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */
__I uint32_t RESERVE1[24];
__I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */
__I uint32_t FN; /*!< [0x008c] USB Frame number Register */
__IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */
__I uint32_t RESERVE2[283];
USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */
} USBD_T;
/**
@addtogroup USBD_CONST USBD Bit Field Definition
Constant Definitions for USBD Controller
@{ */
#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */
#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */
#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */
#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */
#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */
#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */
#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */
#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */
#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */
#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */
#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */
#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */
#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */
#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */
#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */
#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */
#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */
#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */
#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */
#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */
#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */
#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */
#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */
#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */
#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */
#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */
#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */
#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */
#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */
#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */
#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */
#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */
#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */
#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */
#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */
#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */
#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */
#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */
#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */
#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */
#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */
#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */
#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */
#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */
#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */
#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */
#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */
#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */
#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */
#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */
#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
/**@}*/ /* USBD_CONST */
/**@}*/ /* end of USBD register group */
#endif /* __USBD_REG_H__ */

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/**************************************************************************//**
* @file usbh_reg.h
* @version V1.00
* @brief USBH register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USBH_REG_H__
#define __USBH_REG_H__
/*---------------------- USB Host Controller -------------------------*/
/**
@addtogroup USBH USB Host Controller(USBH)
Memory Mapped Structure for USBH Controller
@{ */
typedef struct
{
/**
* @var USBH_T::HcRevision
* Offset: 0x00 Host Controller Revision Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |REV |Revision Number
* | | |Indicates the Open HCI Specification revision number implemented by the Hardware
* | | |Host Controller supports 1.1 specification.
* | | |(X.Y = XYh).
* @var USBH_T::HcControl
* Offset: 0x04 Host Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CBSR |Control Bulk Service Ratio
* | | |This specifies the service ratio between Control and Bulk EDs
* | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
* | | |The internal count will be retained when crossing the frame boundary
* | | |In case of reset, HCD is responsible for restoring this
* | | |Value.
* | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
* | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
* | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
* | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
* |[2] |PLE |Periodic List Enable Bit
* | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
* | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
* | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
* | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
* |[3] |IE |Isochronous List Enable Bit
* | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
* | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
* | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
* |[4] |CLE |Control List Enable Bit
* | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Control list in the next frame Enabled.
* |[5] |BLE |Bulk List Enable Bit
* | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Bulk list in the next frame Enabled.
* |[7:6] |HCFS |Host Controller Functional State
* | | |This field sets the Host Controller state
* | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
* | | |States are:
* | | |00 = USBSUSPEND.
* | | |01 = USBOPERATIONAL.
* | | |10 = USBRESUME.
* | | |11 = USBRESET.
* @var USBH_T::HcCommandStatus
* Offset: 0x08 Host Controller Command Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HCR |Host Controller Reset
* | | |This bit is set to initiate the software reset of Host Controller
* | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
* | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
* | | |0 = Host Controller is not in software reset state.
* | | |1 = Host Controller is in software reset state.
* |[1] |CLF |Control List Filled
* | | |Set high to indicate there is an active TD on the Control List
* | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
* | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
* | | |1 = An active TD added or found on the Control list.
* |[2] |BLF |Bulk List Filled
* | | |Set high to indicate there is an active TD on the Bulk list
* | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
* | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
* | | |1 = An active TD added or found on the Bulk list.
* |[17:16] |SOC |Schedule Overrun Count
* | | |These bits are incremented on each scheduling overrun error
* | | |It is initialized to 00b and wraps around at 11b
* | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
* @var USBH_T::HcInterruptStatus
* Offset: 0x0C Host Controller Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun
* | | |Set when the List Processor determines a Schedule Overrun has occurred.
* | | |0 = Schedule Overrun didn't occur.
* | | |1 = Schedule Overrun has occurred.
* |[1] |WDH |Write Back Done Head
* | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead
* | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
* | | |0 =.Host Controller didn't update HccaDoneHead.
* | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
* |[2] |SF |Start of Frame
* | | |Set when the Frame Management functional block signals a u2018Start of Frame' event
* | | |Host Control generates a SOF token at the same time.
* | | |0 =.Not the start of a frame.
* | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
* |[3] |RD |Resume Detected
* | | |Set when Host Controller detects resume signaling on a downstream port.
* | | |0 = No resume signaling detected on a downstream port.
* | | |1 = Resume signaling detected on a downstream port.
* |[5] |FNO |Frame Number Overflow
* | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* | | |0 = The bit 15 of Frame Number didn't change.
* | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* |[6] |RHSC |Root Hub Status Change
* | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.
* | | |0 = The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change.
* | | |1 = The content of HcRhStatus or the content of HcRhPortStatus1 register has changed.
* @var USBH_T::HcInterruptEnable
* Offset: 0x10 Host Controller Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Enable Bit
* | | |This bit is a global interrupt enable
* | | |A write of u20181' allows interrupts to be enabled via the specific enable bits listed above.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcInterruptDisable
* Offset: 0x14 Host Controller Interrupt Disable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Disable Bit
* | | |Global interrupt disable. Writing u20181' to disable all interrupts.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcHCCA
* Offset: 0x18 Host Controller Communication Area Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:8] |HCCA |Host Controller Communication Area
* | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
* @var USBH_T::HcPeriodCurrentED
* Offset: 0x1C Host Controller Period Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |PCED |Periodic Current ED
* | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
* @var USBH_T::HcControlHeadED
* Offset: 0x20 Host Controller Control Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CHED |Control Head ED
* | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
* @var USBH_T::HcControlCurrentED
* Offset: 0x24 Host Controller Control Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CCED |Control Current Head ED
* | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
* @var USBH_T::HcBulkHeadED
* Offset: 0x28 Host Controller Bulk Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BHED |Bulk Head ED
* | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
* @var USBH_T::HcBulkCurrentED
* Offset: 0x2C Host Controller Bulk Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BCED |Bulk Current Head ED
* | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
* @var USBH_T::HcDoneHead
* Offset: 0x30 Host Controller Done Head Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |DH |Done Head
* | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
* @var USBH_T::HcFmInterval
* Offset: 0x34 Host Controller Frame Interval Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FI |Frame Interval
* | | |This field specifies the length of a frame as (bit times - 1)
* | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
* |[30:16] |FSMPS |FS Largest Data Packet
* | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
* |[31] |FIT |Frame Interval Toggle
* | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
* | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
* | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
* @var USBH_T::HcFmRemaining
* Offset: 0x38 Host Controller Frame Remaining Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FR |Frame Remaining
* | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
* | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
* | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
* |[31] |FRT |Frame Remaining Toggle
* | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
* @var USBH_T::HcFmNumber
* Offset: 0x3C Host Controller Frame Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FN |Frame Number
* | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
* | | |The count rolls over from u2018FFFFh' to u20180h.'
* @var USBH_T::HcPeriodicStart
* Offset: 0x40 Host Controller Periodic Start Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |PS |Periodic Start
* | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
* @var USBH_T::HcLSThreshold
* Offset: 0x44 Host Controller Low-speed Threshold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |LST |Low-speed Threshold
* | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
* | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
* | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
* @var USBH_T::HcRhDescriptorA
* Offset: 0x48 Host Controller Root Hub Descriptor A Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |NDP |Number Downstream Ports
* | | |USB host control supports two downstream ports and only one port is available in this series of chip.
* |[8] |PSM |Power Switching Mode
* | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
* | | |0 = Global Switching.
* | | |1 = Individual Switching.
* |[11] |OCPM |over Current Protection Mode
* | | |This bit describes how the over current status for the Root Hub ports reported
* | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
* | | |0 = Global Over current.
* | | |1 = Individual Over current.
* |[12] |NOCP |No over Current Protection
* | | |This bit describes how the over current status for the Root Hub ports reported.
* | | |0 = Over current status is reported.
* | | |1 = Over current status is not reported.
* @var USBH_T::HcRhDescriptorB
* Offset: 0x4C Host Controller Root Hub Descriptor B Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |PPCM |Port Power Control Mask
* | | |Global power switching
* | | |This field is only valid if PowerSwitchingMode is set (individual port switching)
* | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower)
* | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
* | | |0 = Port power controlled by global power switching.
* | | |1 = Port power controlled by port power switching.
* | | |Note: PPCM[15:2] and PPCM[0] are reserved.
* @var USBH_T::HcRhStatus
* Offset: 0x50 Host Controller Root Hub Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LPS |Clear Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear global power.
* |[1] |OCI |over Current Indicator
* | | |This bit reflects the state of the over current status pin
* | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
* | | |0 = No over current condition.
* | | |1 = Over current condition.
* |[15] |DRWE |Device Remote Wakeup Enable Bit
* | | |This bit controls if port's Connect Status Change as a remote wake-up event.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* | | |Read Operation:
* | | |0 = Connect Status Change as a remote wake-up event Disabled.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* |[16] |LPSC |Set Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set global power.
* |[17] |OCIC |over Current Indicator Change
* | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
* | | |Write 1 to clear this bit to zero.
* | | |0 = OCI (HcRhStatus[1]) didn't change.
* | | |1 = OCI (HcRhStatus[1]) change.
* |[31] |CRWE |Clear Remote Wake-up Enable Bit
* | | |This bit is use to clear DRWE (HcRhStatus[15]).
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear DRWE (HcRhStatus[15]).
* @var USBH_T::HcRhPortStatus1
* Offset: 0x54 Host Controller Root Hub Port Status [1]
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port enable.
* | | |Read Operation:
* | | |0 = No device connected.
* | | |1 = Device connected.
* |[1] |PES |Port Enable Status
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port enable.
* | | |Read Operation:
* | | |0 = Port Disabled.
* | | |1 = Port Enabled.
* |[2] |PSS |Port Suspend Status
* | | |This bit indicates the port is suspended
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port suspend.
* | | |Read Operation:
* | | |0 = Port is not suspended.
* | | |1 = Port is selectively suspended.
* |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write)
* | | |This bit reflects the state of the over current status pin dedicated to this port
* | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
* | | |This bit is also used to initiate the selective result sequence for the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port suspend.
* | | |Read Operation:
* | | |0 = No over current condition.
* | | |1 = Over current condition.
* |[4] |PRS |Port Reset Status
* | | |This bit reflects the reset state of the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port reset.
* | | |Read Operation
* | | |0 = Port reset signal is not active.
* | | |1 = Port reset signal is active.
* |[8] |PPS |Port Power Status
* | | |This bit reflects the power state of the port regardless of the power switching mode.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Port Power Enabled.
* | | |Read Operation:
* | | |0 = Port power is Disabled.
* | | |1 = Port power is Enabled.
* |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write)
* | | |This bit defines the speed (and bud idle) of the attached device
* | | |It is only valid when CCS (HcRhPortStatus1[0]) is set.
* | | |This bit is also used to clear port power.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear PPS (HcRhPortStatus1[8]).
* | | |Read Operation:
* | | |0 = Full Speed device.
* | | |1 = Low-speed device.
* |[16] |CSC |Connect Status Change
* | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).
* | | |Write 1 to clear this bit to zero.
* | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change).
* | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
* |[17] |PESC |Port Enable Status Change
* | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.
* | | |Write 1 to clear this bit to zero.
* | | |0 = PES (HcRhPortStatus1[1]) didn't change.
* | | |1 = PES (HcRhPortStatus1[1]) changed.
* |[18] |PSSC |Port Suspend Status Change
* | | |This bit indicates the completion of the selective resume sequence for the port.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port resume is not completed.
* | | |1 = Port resume completed.
* |[19] |OCIC |Port over Current Indicator Change
* | | |This bit is set when POCI (HcRhPortStatus1[3]) changes.
* | | |Write 1 to clear this bit to zero.
* | | |0 = POCI (HcRhPortStatus1[3]) didn't change.
* | | |1 = POCI (HcRhPortStatus1[3]) changes.
* |[20] |PRSC |Port Reset Status Change
* | | |This bit indicates that the port reset signal has completed.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port reset is not complete.
* | | |1 = Port reset is complete.
* @var USBH_T::HcPhyControl
* Offset: 0x200 Host Controller PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[27] |STBYEN |USB Transceiver Standby Enable Bit
* | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
* | | |0 = The USB transceiver would never enter the standby mode.
* | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
* @var USBH_T::HcMiscControl
* Offset: 0x204 Host Controller Miscellaneous Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABORT |AHB Bus ERROR Response
* | | |This bit indicates there is an ERROR response received in AHB bus.
* | | |0 = No ERROR response received.
* | | |1 = ERROR response received.
* |[3] |OCAL |over Current Active Low
* | | |This bit controls the polarity of over current flag from external power IC.
* | | |0 = Over current flag is high active.
* | | |1 = Over current flag is low active.
* |[16] |DPRT1 |Disable Port 1
* | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
* | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
* | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
* | | |0 = The connection between USB host controller and transceiver of port 1 Enabled.
* | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
*/
__I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */
__IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */
__IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */
__IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */
__IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */
__IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */
__IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */
__IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */
__IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */
__IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */
__IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */
__IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */
__IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */
__IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */
__I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */
__I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */
__IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */
__IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */
__IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */
__IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */
__IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */
__IO uint32_t HcRhPortStatus1; /*!< [0x0054] Host Controller Root Hub Port Status [1] */
__I uint32_t RESERVE0[106];
__IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */
__IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */
} USBH_T;
/**
@addtogroup USBH_CONST USBH Bit Field Definition
Constant Definitions for USBH Controller
@{ */
#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */
#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */
#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/
#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/
#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/
#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/
#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/
#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/
#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/
#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/
#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/
#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/
#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/
#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/
#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/
#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/
#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/
#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
#define USBH_HcRhPortStatus1_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */
#define USBH_HcRhPortStatus1_CCS_Msk (0x1ul << USBH_HcRhPortStatus1_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */
#define USBH_HcRhPortStatus1_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */
#define USBH_HcRhPortStatus1_PES_Msk (0x1ul << USBH_HcRhPortStatus1_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */
#define USBH_HcRhPortStatus1_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */
#define USBH_HcRhPortStatus1_PSS_Msk (0x1ul << USBH_HcRhPortStatus1_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */
#define USBH_HcRhPortStatus1_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */
#define USBH_HcRhPortStatus1_POCI_Msk (0x1ul << USBH_HcRhPortStatus1_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */
#define USBH_HcRhPortStatus1_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */
#define USBH_HcRhPortStatus1_PRS_Msk (0x1ul << USBH_HcRhPortStatus1_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */
#define USBH_HcRhPortStatus1_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */
#define USBH_HcRhPortStatus1_PPS_Msk (0x1ul << USBH_HcRhPortStatus1_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */
#define USBH_HcRhPortStatus1_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */
#define USBH_HcRhPortStatus1_LSDA_Msk (0x1ul << USBH_HcRhPortStatus1_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */
#define USBH_HcRhPortStatus1_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */
#define USBH_HcRhPortStatus1_CSC_Msk (0x1ul << USBH_HcRhPortStatus1_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */
#define USBH_HcRhPortStatus1_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */
#define USBH_HcRhPortStatus1_PESC_Msk (0x1ul << USBH_HcRhPortStatus1_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */
#define USBH_HcRhPortStatus1_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */
#define USBH_HcRhPortStatus1_PSSC_Msk (0x1ul << USBH_HcRhPortStatus1_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */
#define USBH_HcRhPortStatus1_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */
#define USBH_HcRhPortStatus1_OCIC_Msk (0x1ul << USBH_HcRhPortStatus1_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */
#define USBH_HcRhPortStatus1_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */
#define USBH_HcRhPortStatus1_PRSC_Msk (0x1ul << USBH_HcRhPortStatus1_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */
#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
/**@}*/ /* USBH_CONST */
/**@}*/ /* end of USBH register group */
#endif /* __USBH_REG_H__ */

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/**************************************************************************//**
* @file uspi_reg.h
* @version V1.00
* @brief USPI register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USPI_REG_H__
#define __USPI_REG_H__
/*---------------------- SPI Mode of USCI Controller -------------------------*/
/**
@addtogroup USPI SPI Mode of USCI Controller(USPI)
Memory Mapped Structure for USPI Controller
@{ */
typedef struct
{
/**
* @var USPI_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var USPI_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var USPI_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fDIV_CLK.
* | | |01 = fPROT_CLK.
* | | |10 = fSCLK.
* | | |11 = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.
* @var USPI_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var USPI_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
* | | |0 = Data output level is not inverted.
* | | |1 = Data output level is inverted.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: The control signal has different definitions in different protocol
* | | |In SPI protocol, the control signal means slave select signal
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* @var USPI_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission
* | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
* |[16] |PORTDIR |Port Direction Control
* | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer
* | | |It is used to define the direction of the data port pin
* | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
* | | |0 = The data pin is configured as output mode.
* | | |1 = The data pin is configured as input mode.
* @var USPI_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* @var USPI_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6] |TXUDRIEN |Slave Transmit Under-run Interrupt Enable Bit
* | | |0 = Transmit under-run interrupt Disabled.
* | | |1 = Transmit under-run interrupt Enabled.
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* @var USPI_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Overrun Interrupt Status
* | | |This bit indicates that a receive buffer overrun event has been detected
* | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun event has not been detected.
* | | |1 = A receive buffer overrun event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty and available for the next transmission datum.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status
* | | |This bit indicates that a transmit buffer under-run event has been detected
* | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit
* | | |0 = A transmit buffer under-run event has not been detected.
* | | |1 = A transmit buffer under-run event has been detected.
* @var USPI_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* | | |Notice: The I2C is not supporting PDMA function.
* @var USPI_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var USPI_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var USPI_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SLAVE |Slave Mode Selection
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)
* | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[2] |SS |Slave Select Control (Master Only)
* | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.
* | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
* | | |Note: In SPI protocol, the internal slave select signal is active high.
* |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)
* | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
* | | |1 = Slave select signal will be generated automatically
* | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
* |[7:6] |SCLKMODE |Serial Bus Clock Mode
* | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.
* | | |MODE0 = The idle state of SPI clock is low level
* | | |Data is transmitted with falling edge and received with rising edge.
* | | |MODE1 = The idle state of SPI clock is low level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE2 = The idle state of SPI clock is high level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE3 = The idle state of SPI clock is high level
* | | |Data is transmitted with falling edge and received with rising edge.
* |[11:8] |SUSPITV |Suspend Interval (Master Only)
* | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
* |[14:12] |TSMSEL |Transmit Data Mode Selection
* | | |This bit field describes how receive and transmit data is shifted in and out.
* | | |TSMSEL = 000b: Full-duplex SPI.
* | | |TSMSEL = 100b: Half-duplex SPI.
* | | |Other values are reserved.
* | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
* |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)
* | | |In Slave mode, this bit field is used for Slave time-out period
* | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event
* | | |Writing 0x0 into this bit field will disable the Slave time-out function.
* | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
* |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)
* | | |This bit defines the transmitting data level when no data is available for transferring.
* | | |0 = The output data level is 0 if TX under-run event occurs.
* | | |1 = The output data level is 1 if TX under-run event occurs.
* |[31] |PROTEN |SPI Protocol Enable Bit
* | | |0 = SPI Protocol Disabled.
* | | |1 = SPI Protocol Enabled.
* @var USPI_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
* | | |0 = Slave select inactive interrupt generation Disabled.
* | | |1 = Slave select inactive interrupt generation Enabled.
* |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
* | | |0 = Slave select active interrupt generation Disabled.
* | | |1 = Slave select active interrupt generation Enabled.
* |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control
* | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
* | | |0 = The Slave time-out interrupt Disabled.
* | | |1 = The Slave time-out interrupt Enabled.
* |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control
* | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])
* | | |Bit count error event occurs.
* | | |0 = The Slave mode bit count error interrupt Disabled.
* | | |1 = The Slave mode bit count error interrupt Enabled.
* @var USPI_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = Transmit start event does not occur.
* | | |1 = Transmit start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = Transmit end event does not occur.
* | | |1 = Transmit end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = Receive start event does not occur.
* | | |1 = Receive start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = Receive end event does not occur.
* | | |1 = Receive end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)
* | | |0 = Slave time-out event does not occur.
* | | |1 = Slave time-out event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)
* | | |0 = Slave bit count error event does not occur.
* | | |1 = Slave bit count error event occurs.
* | | |Note: It is cleared by software writes 1 to this bit.
* |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to inactive
* | | |It is cleared by software writes 1 to this bit
* | | |0 = The slave select signal has not changed to inactive.
* | | |1 = The slave select signal has changed to inactive.
* | | |Note: The internal slave select signal is active high.
* |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to active
* | | |It is cleared by software writes one to this bit
* | | |0 = The slave select signal has not changed to active.
* | | |1 = The slave select signal has changed to active.
* | | |Note: The internal slave select signal is active high.
* |[16] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |This bit is only available in Slave mode
* | | |It used to monitor the current status of the input slave select signal on the bus.
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* |[17] |BUSY |Busy Status (Read Only)
* | | |0 = SPI is in idle state.
* | | |1 = SPI is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
* | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)
* | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1
* | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
* | | |0 = Slave transmit under-run event does not occur.
* | | |1 = Slave transmit under-run event occurs.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
__I uint32_t RESERVE0[1];
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
__I uint32_t RESERVE1[3];
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
__I uint32_t RESERVE2[1];
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
__I uint32_t RESERVE3[4];
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
} USPI_T;
/**
@addtogroup USPI_CONST USPI Bit Field Definition
Constant Definitions for USPI Controller
@{ */
#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */
#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */
#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */
#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */
#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */
#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */
#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */
#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */
#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */
#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */
#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */
#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */
#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */
#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */
#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */
#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */
#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */
#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */
#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */
#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */
#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */
#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */
#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */
#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */
#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */
#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */
#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */
#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */
#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */
#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */
#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */
#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */
#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */
#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */
#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */
#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */
#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */
#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */
#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */
#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */
#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */
#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */
#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */
#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */
#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */
#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */
#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */
#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */
#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */
#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */
#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */
#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */
#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */
#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */
#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */
#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */
#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */
#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */
#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */
#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */
#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */
#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */
#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */
#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */
#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */
#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */
#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */
#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */
#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */
#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */
#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */
#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */
#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */
#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */
#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */
#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */
#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */
#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */
#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */
#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */
#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */
#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */
#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */
#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */
#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */
#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */
#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */
#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */
#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */
#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */
#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */
#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */
#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */
#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */
#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */
#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */
#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */
#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */
#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */
#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */
#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */
#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */
#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */
#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */
#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */
#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */
#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */
#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */
#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */
#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */
#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */
#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */
#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */
#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */
#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */
#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */
#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */
#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */
#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */
#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */
#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */
#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */
#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */
#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */
#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */
#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */
#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */
#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */
#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */
#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */
#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */
#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */
#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */
#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */
#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */
#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */
/**@}*/ /* USPI_CONST */
/**@}*/ /* end of USPI register group */
#endif /* __USPI_REG_H__ */

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/**************************************************************************//**
* @file uuart_reg.h
* @version V1.00
* @brief UUART register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UUART_REG_H__
#define __UUART_REG_H__
/*---------------------- UART Mode of USCI Controller -------------------------*/
/**
@addtogroup UUART UART Mode of USCI Controller(UUART)
Memory Mapped Structure for UUART Controller
@{ */
typedef struct
{
/**
* @var UUART_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller.
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI.
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol.
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Others = Reserved.
* @var UUART_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var UUART_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK frequency is fDIV_CLK.
* | | |01 = fSAMP_CLK frequency is from fPROT_CLK.
* | | |10 = fSAMP_CLK frequency is from fSCLK.
* | | |11 = fSAMP_CLK frequency is from fREF_CLK.
* |[4] |TMCNTEN |Timing Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Timing measurement counter is Disabled.
* | | |1 = Timing measurement counter is Enabled.
* |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection
* | | |0 = Timing measurement counter with fPROT_CLK.
* | | |1 = Timing measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK.
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled.
* | | |The revised value is the average bit time between bit 5 and bit 6.
* | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UUART_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* |[4:3] |EDGEDET |Input Signal Edge Detection Mode
* | | |This bit field selects which edge actives the trigger event of input data signal.
* | | |00 = The trigger event activation is disabled.
* | | |01 = A rising edge activates the trigger event of input data signal.
* | | |10 = A falling edge activates the trigger event of input data signal.
* | | |11 = Both edges activate the trigger event of input data signal.
* | | |Note: In UART function mode, it is suggested to set this bit field as 10.
* @var UUART_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var UUART_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* @var UUART_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
* | | |0 = The value of USCIx_DAT1 is equal to the data shift register.
* | | |1 = The value of USCIx_DAT1 is the inversion of data shift register.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: In UART protocol, the control signal means nRTS signal.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0 = The data word contains 16 bits located at bit positions [15:0].
* | | |0x1 = Reserved.
* | | |0x2 = Reserved.
* | | |0x3 = Reserved.
* | | |0x4 = The data word contains 4 bits located at bit positions [3:0].
* | | |0x5 = The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF = The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits.
* @var UUART_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UUART_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
* @var UUART_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note1: It is cleared automatically after one PCLK cycle.
* | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
* @var UUART_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status
* | | |This bit indicates that a receive buffer overrun error event has been detected.
* | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated.
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun error event has not been detected.
* | | |1 = A receive buffer overrun error event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* @var UUART_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* @var UUART_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var UUART_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var UUART_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |STOPB |Stop Bits
* | | |This bit defines the number of stop bits in an UART frame.
* | | |0 = The number of stop bits is 1.
* | | |1 = The number of stop bits is 2.
* |[1] |PARITYEN |Parity Enable Bit
* | | |This bit defines the parity bit is enabled in an UART frame.
* | | |0 = The parity bit Disabled.
* | | |1 = The parity bit Enabled.
* |[2] |EVENPARITY|Even Parity Enable Bit
* | | |0 = Odd number of logic 1's is transmitted and checked in each word.
* | | |1 = Even number of logic 1's is transmitted and checked in each word.
* | | |Note: This bit has effect only when PARITYEN is set.
* |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
* | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal.
* | | |0 = nRTS auto-flow control Disabled.
* | | |1 = nRTS auto-flow control Enabled.
* | | |Note: This bit has effect only when the RTSAUDIREN is not set.
* |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
* | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
* | | |0 = nCTS auto-flow control Disabled.
* | | |1 = nCTS auto-flow control Enabled.
* |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit
* | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive.
* | | |0 = nRTS auto direction control Disabled.
* | | |1 = nRTS auto direction control Enabled.
* | | |Note1: This bit is used for nRTS auto direction control for RS485.
* | | |Note2: This bit has effect only when the RTSAUTOEN is not set.
* |[6] |ABREN |Auto-baud Rate Detect Enable Bit
* | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled.
* | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit.
* | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
* |[9] |DATWKEN |Data Wake-up Mode Enable Bit
* | | |0 = Data wake-up mode Disabled.
* | | |1 = Data wake-up mode Enabled.
* |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit
* | | |0 = nCTS wake-up mode Disabled.
* | | |1 = nCTS wake-up mode Enabled.
* |[14:11] |WAKECNT |Wake-up Counter
* | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
* |[24:16] |BRDETITV |Baud Rate Detection Interval
* | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits.
* | | |The order of the bus shall be 1 and 0 step by step (e.g
* | | |the input data pattern shall be 0x55)
* | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.
* | | |Note: This bit can be cleared to 0 by software writing u20180' to the BRDETITV.
* |[26] |STICKEN |Stick Parity Enable Bit
* | | |0 = Stick parity Disabled.
* | | |1 = Stick parity Enabled.
* | | |Note: Refer to RS-485 Support section for detail information.
* |[29] |BCEN |Transmit Break Control Enable Bit
* | | |0 = Transmit Break Control Disabled.
* | | |1 = Transmit Break Control Enabled.
* | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
* | | |This bit acts only on TX line and has no effect on the transmitter logic.
* |[31] |PROTEN |UART Protocol Enable Bit
* | | |0 = UART Protocol Disabled.
* | | |1 = UART Protocol Enabled.
* @var UUART_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
* | | |0 = Auto-baud rate interrupt Disabled.
* | | |1 = Auto-baud rate interrupt Enabled.
* |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
* | | |0 = Receive line status interrupt Disabled.
* | | |1 = Receive line status interrupt Enabled.
* | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
* @var UUART_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = A transmit start interrupt status has not occurred.
* | | |1 = A transmit start interrupt status has occurred.
* | | |Note1: It is cleared by software writing one into this bit.
* | | |Note2: Used for user to load next transmit data when there is no data in transmit buffer.
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = A transmit end interrupt status has not occurred.
* | | |1 = A transmit end interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = A receive start interrupt status has not occurred.
* | | |1 = A receive start interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = A receive finish interrupt status has not occurred.
* | | |1 = A receive finish interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[5] |PARITYERR |Parity Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
* | | |0 = No parity error is generated.
* | | |1 = Parity error is generated.
* | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
* |[6] |FRMERR |Framing Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = No framing error is generated.
* | | |1 = Framing error is generated.
* | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
* |[7] |BREAK |Break Flag
* | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
* | | |0 = No Break is generated.
* | | |1 = Break is generated in the receiver bus.
* | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
* |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag
* | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data.
* | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated.
* | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
* | | |0 = Auto-baud rate detect function is not done.
* | | |1 = One Bit auto-baud rate detect function is done.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[10] |RXBUSY |RX Bus Status Flag (Read Only)
* | | |This bit indicates the busy status of the receiver.
* | | |0 = The receiver is Idle.
* | | |1 = The receiver is BUSY.
* |[11] |ABERRSTS |Auto-baud Rate Error Status
* | | |This bit is set when auto-baud rate detection counter overrun.
* | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.
* | | |0 = Auto-baud rate detect counter is not overrun.
* | | |1 = Auto-baud rate detect counter is overrun.
* | | |Note1: This bit is set at the same time of ABRDETIF.
* | | |Note2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS.
* |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
* | | |This bit used to indicate the current status of the internal synchronized nCTS signal.
* | | |0 = The internal synchronized nCTS is low.
* | | |1 = The internal synchronized nCTS is high.
* |[17] |CTSLV |nCTS Pin Status (Read Only)
* | | |This bit used to monitor the current status of nCTS pin input.
* | | |0 = nCTS pin input is low level voltage logic state.
* | | |1 = nCTS pin input is high level voltage logic state.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
__I uint32_t RESERVE0[1];
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
__I uint32_t RESERVE1[3];
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
__I uint32_t RESERVE2[1];
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
__I uint32_t RESERVE3[4];
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
} UUART_T;
/**
@addtogroup UUART_CONST UUART Bit Field Definition
Constant Definitions for UUART Controller
@{ */
#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */
#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */
#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */
#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */
#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */
#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */
#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */
#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */
#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */
#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */
#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */
#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */
#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */
#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */
#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */
#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */
#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */
#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */
#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */
#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */
#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */
#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */
#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */
#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */
#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */
#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */
#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */
#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */
#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */
#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */
#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */
#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */
#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */
#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */
#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */
#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */
#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */
#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */
#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */
#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */
#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */
#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */
#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */
#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */
#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */
#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */
#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */
#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */
#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */
#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */
#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */
#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */
#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */
#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */
#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */
#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */
#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */
#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */
#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */
#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */
#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */
#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */
#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */
#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */
#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */
#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */
#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */
#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */
#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */
#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */
#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */
#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */
#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */
#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */
#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */
#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */
#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */
#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */
#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */
#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */
#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */
#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */
#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */
#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */
#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */
#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */
#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */
#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */
#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */
#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */
#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */
#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */
#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */
#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */
#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */
#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */
#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */
#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */
#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */
#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */
#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */
#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */
#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */
#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */
#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */
#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */
#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */
#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */
#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */
#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */
#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */
#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */
#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */
#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */
#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */
#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */
#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */
#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */
#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */
#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */
#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */
#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */
#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */
#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */
#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */
#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */
#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */
#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */
#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */
#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */
#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */
#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */
#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */
#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */
#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */
#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */
#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */
#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */
#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */
#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */
/**@}*/ /* UUART_CONST */
/**@}*/ /* end of UUART register group */
#endif /* __UUART_REG_H__ */

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/**************************************************************************//**
* @file wdt_reg.h
* @version V1.00
* @brief WDT register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_REG_H__
#define __WDT_REG_H__
/*---------------------- Watch Dog Timer Controller -------------------------*/
/**
@addtogroup WDT Watch Dog Timer Controller(WDT)
Memory Mapped Structure for WDT Controller
@{ */
typedef struct
{
/**
* @var WDT_T::CTL
* Offset: 0x00 WDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect)
* | | |Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
* | | |0 = WDT time-out reset system function Disabled.
* | | |1 = WDT time-out reset system function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |RSTF |WDT Time-out Reset Flag
* | | |This bit indicates the system has been reset by WDT time-out reset system event or not.
* | | |0 = WDT time-out reset system event did not occur.
* | | |1 = WDT time-out reset system event has been occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |IF |WDT Time-out Interrupt Flag
* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
* | | |0 = WDT time-out interrupt event interrupt did not occur.
* | | |1 = WDT time-out interrupt interrupt event occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip.
* | | |0 = Trigger wWake-up trigger event function Disabled if WDT time-out interrupt signal generated.
* | | |1 = Trigger Wake-up trigger event function Enabled if WDT time-out interrupt signal generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: Chip can be woken-up by while WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz (LIRC (10 kHz) or LXT (32 kHz).
* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
* | | |This bit indicates the WDT time-out event has triggered interrupt chip wake-up or not.flag status of WDT
* | | |0 = WDT does not cause chip wake-up.
* | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This bit is cleared by writing 1 to it.
* |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect)
* | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU.
* | | |0 = WDT time-out interrupt Disabled.
* | | |1 = WDT time-out interrupt Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |WDTEN |WDT Enable Control (Write Protect)
* | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also).
* | | |1 = Set WDT counter start Enabled.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not.
* | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0.
* | | |Note3: This bit disabled needs 2 * WDT_CLK.
* |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
* | | |These three bits select the time-out interval period after for the WDT starts counting.
* | | |000 = 24 * WDT_CLK.
* | | |001 = 26 * WDT_CLK.
* | | |010 = 28 * WDT_CLK.
* | | |011 = 210 * WDT_CLK.
* | | |100 = 212 * WDT_CLK.
* | | |101 = 214 * WDT_CLK.
* | | |110 = 216 * WDT_CLK.
* | | |111 = 218 * WDT_CLK.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only)
* | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not..
* | | |SYNC delay is
* | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion.
* | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet..
* | | |Note: Perform enable or disable WDTEN bit
* | | |This bit enabled needs 2 * WDT_CLK period to become active.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
* | | |0 = ICE debug mode acknowledgment affects WDT counting.
* | | |WDT up counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgment Disabled.
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var WDT_T::ALTCTL
* Offset: 0x04 WDT Alternative Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect)
* | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened
* | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period.
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened.
* @var WDT_T::RSTCNT
* Offset: 0x08 WDT Reset Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RSTCNT |WDT Reset Counter Register
* | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0.
* | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected.
* | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
*/
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
} WDT_T;
/**
@addtogroup WDT_CONST WDT Bit Field Definition
Constant Definitions for WDT Controller
@{ */
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
/**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */
#endif /* __WDT_REG_H__ */

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/**************************************************************************//**
* @file wwdt_reg.h
* @version V1.00
* @brief WWDT register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_REG_H__
#define __WWDT_REG_H__
/*---------------------- Window Watchdog Timer -------------------------*/
/**
@addtogroup WWDT Window Watchdog Timer(WWDT)
Memory Mapped Structure for WWDT Controller
@{ */
typedef struct
{
/**
* @var WWDT_T::RLDCNT
* Offset: 0x00 WWDT Reload Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RLDCNT |WWDT Reload Counter Register
* | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
* | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16])
* | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately.
* | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also.
* @var WWDT_T::CTL
* Offset: 0x04 WWDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTEN |WWDT Enable Control Bit
* | | |Set this bit to enable start WWDT counter counting.
* | | |0 = WWDT counter is stopped.
* | | |1 = WWDT counter is starting counting.
* |[1] |INTEN |WWDT Interrupt Enable Control Bit
* | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.
* | | |0 = WWDT counter compare match interrupt Disabled.
* | | |1 = WWDT counter compare match interrupt Enabled.
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
* |[21:16] |CMPDAT |WWDT Window Compare Register Value
* | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated..
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT
* | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
* | | |0 = ICE debug mode acknowledgment effects WWDT counter counting.
* | | |WWDT down counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgment Disabled.
* | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not.
* @var WWDT_T::STATUS
* Offset: 0x08 WWDT Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
* | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
* | | |0 = No effect.
* | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |WWDTRF |WWDT Timer-out Reset System Flag
* | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not.
* | | |0 = WWDT time-out reset system event did not occur.
* | | |1 = WWDT time-out reset system event occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var WWDT_T::CNT
* Offset: 0x0C WWDT Counter Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CNTDAT |WWDT Counter Value
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
*/
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
} WWDT_T;
/**
@addtogroup WWDT_CONST WWDT Bit Field Definition
Constant Definitions for WWDT Controller
@{ */
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
/**@}*/ /* WWDT_CONST */
/**@}*/ /* end of WWDT register group */
#endif /* __WWDT_REG_H__ */

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/**************************************************************************//**
* @file acmp.c
* @version V3.00
* $Revision: 1 $
* $Date: 16/07/07 7:50p $
* @brief Analog Comparator(ACMP) driver source file
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M2351.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/**
* @brief Configure the specified ACMP module
*
* @param[in] Acmp The pointer of the specified ACMP module
* @param[in] u32ChNum Comparator number.
* @param[in] u32NegSrc Comparator negative input selection. Including:
* - \ref ACMP_CTL_NEGSEL_PIN
* - \ref ACMP_CTL_NEGSEL_CRV
* - \ref ACMP_CTL_NEGSEL_VBG
* - \ref ACMP_CTL_NEGSEL_DAC
* @param[in] u32HysSel The hysteresis function option. Including:
* - \ref ACMP_CTL_HYSTERESIS_30MV
* - \ref ACMP_CTL_HYSTERESIS_20MV
* - \ref ACMP_CTL_HYSTERESIS_10MV
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
*
* @return None
*
* @details Configure hysteresis function, select the source of negative input and enable analog comparator.
*/
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel)
{
acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk);
}
/**
* @brief Close analog comparator
*
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum Comparator number.
*
* @return None
*
* @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
*/
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
{
acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
}
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group ACMP_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

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