mirror of https://github.com/ARMmbed/mbed-os.git
* Updated IAR startup file.
* Grouped SAMR21G18A specific files to its particular folder. * Added files for all variants of SAMR21 and SAMD21. * Removed Quick Start files from ASF. * Added Target Dependency in port.c for PORT MASK. * Grouped PWM pin implementation to SAMR21G18A folder.pull/1297/head
akhilpanayam
Karthik Purushothaman
parent
d34e39ff05
commit
47d62cd8ce
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@ -102,7 +102,7 @@ void I2S_Handler ( void );
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//! [startup_vector_table]
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const DeviceVectors __vector_table[] = {
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__sfe("CSTACK"),
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(void*) Reset_Handler,
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(void*) __iar_program_start,
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(void*) NMI_Handler,
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(void*) HardFault_Handler,
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(void*) (0UL), /* Reserved */
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@ -117,7 +117,7 @@ void Dummy_Handler(void);
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#pragma location = ".intvec"
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const DeviceVectors __vector_table[] = {
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__sfe("CSTACK"),
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(void*) Reset_Handler,
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(void*) __iar_program_start,
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(void*) NMI_Handler,
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(void*) HardFault_Handler,
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(void*) (0UL), /* Reserved */
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@ -0,0 +1,500 @@
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#ifndef _SAMD21E15A_
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#define _SAMD21E15A_
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/**
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* \ingroup SAMD21_definitions
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* \addtogroup SAMD21E15A_definitions SAMD21E15A definitions
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* This file defines all structures and symbols for SAMD21E15A:
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* - registers and bitfields
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* - peripheral base address
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* - peripheral ID
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* - PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#include <stdint.h>
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#else
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typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#endif
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typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
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typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
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typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
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#define CAST(type, value) ((type *)(value))
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#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
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#else
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#define CAST(type, value) (value)
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#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
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#endif
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/* ************************************************************************** */
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/** CMSIS DEFINITIONS FOR SAMD21E15A */
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/* ************************************************************************** */
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/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
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/*@{*/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
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NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
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PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
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/****** SAMD21E15A-specific Interrupt Numbers ***********************/
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PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
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SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
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WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
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RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
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EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
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NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
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DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
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USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
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EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
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SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
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SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
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SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
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SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
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TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
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TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
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TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
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TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
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TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
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TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
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ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
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AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
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DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
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PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
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I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
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PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
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} IRQn_Type;
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typedef struct _DeviceVectors
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{
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/* Stack pointer */
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void* pvStack;
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/* Cortex-M handlers */
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void* pfnReset_Handler;
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void* pfnNMI_Handler;
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void* pfnHardFault_Handler;
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void* pfnReservedM12;
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void* pfnReservedM11;
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void* pfnReservedM10;
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void* pfnReservedM9;
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void* pfnReservedM8;
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void* pfnReservedM7;
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void* pfnReservedM6;
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void* pfnSVC_Handler;
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void* pfnReservedM4;
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void* pfnReservedM3;
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void* pfnPendSV_Handler;
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void* pfnSysTick_Handler;
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/* Peripheral handlers */
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void* pfnPM_Handler; /* 0 Power Manager */
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void* pfnSYSCTRL_Handler; /* 1 System Control */
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void* pfnWDT_Handler; /* 2 Watchdog Timer */
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void* pfnRTC_Handler; /* 3 Real-Time Counter */
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void* pfnEIC_Handler; /* 4 External Interrupt Controller */
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void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
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void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
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void* pfnUSB_Handler; /* 7 Universal Serial Bus */
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void* pfnEVSYS_Handler; /* 8 Event System Interface */
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void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
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void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
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void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
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void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
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void* pfnReserved13;
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void* pfnReserved14;
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void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
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void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
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void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
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void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
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void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
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void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
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void* pfnReserved21;
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void* pfnReserved22;
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void* pfnADC_Handler; /* 23 Analog Digital Converter */
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void* pfnAC_Handler; /* 24 Analog Comparators */
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void* pfnDAC_Handler; /* 25 Digital Analog Converter */
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void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
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void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
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} DeviceVectors;
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/* Cortex-M0+ processor handlers */
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void Reset_Handler ( void );
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void NMI_Handler ( void );
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void HardFault_Handler ( void );
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void SVC_Handler ( void );
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void PendSV_Handler ( void );
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void SysTick_Handler ( void );
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/* Peripherals handlers */
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void PM_Handler ( void );
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void SYSCTRL_Handler ( void );
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void WDT_Handler ( void );
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void RTC_Handler ( void );
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void EIC_Handler ( void );
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void NVMCTRL_Handler ( void );
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void DMAC_Handler ( void );
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void USB_Handler ( void );
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void EVSYS_Handler ( void );
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void SERCOM0_Handler ( void );
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void SERCOM1_Handler ( void );
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void SERCOM2_Handler ( void );
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void SERCOM3_Handler ( void );
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void TCC0_Handler ( void );
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void TCC1_Handler ( void );
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void TCC2_Handler ( void );
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void TC3_Handler ( void );
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void TC4_Handler ( void );
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void TC5_Handler ( void );
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void ADC_Handler ( void );
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void AC_Handler ( void );
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void DAC_Handler ( void );
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void PTC_Handler ( void );
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void I2S_Handler ( void );
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/*
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* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
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*/
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#define LITTLE_ENDIAN 1
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#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
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#define __VTOR_PRESENT 1 /*!< VTOR present or not */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* \brief CMSIS includes
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*/
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#include <core_cm0plus.h>
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#if !defined DONT_USE_CMSIS_INIT
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#include "system_samd21.h"
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#endif /* DONT_USE_CMSIS_INIT */
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/*@}*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
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/* ************************************************************************** */
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/** \defgroup SAMD21E15A_api Peripheral Software API */
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/*@{*/
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#include "component/ac.h"
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#include "component/adc.h"
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#include "component/dac.h"
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#include "component/dmac.h"
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#include "component/dsu.h"
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#include "component/eic.h"
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#include "component/evsys.h"
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#include "component/gclk.h"
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#include "component/i2s.h"
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#include "component/mtb.h"
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#include "component/nvmctrl.h"
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#include "component/pac.h"
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#include "component/pm.h"
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#include "component/port.h"
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#include "component/rtc.h"
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#include "component/sercom.h"
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#include "component/sysctrl.h"
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#include "component/tc.h"
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#include "component/tcc.h"
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#include "component/usb.h"
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#include "component/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
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/* ************************************************************************** */
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/** \defgroup SAMD21E15A_reg Registers Access Definitions */
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/*@{*/
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#include "instance/ac.h"
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#include "instance/adc.h"
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#include "instance/dac.h"
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#include "instance/dmac.h"
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#include "instance/dsu.h"
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#include "instance/eic.h"
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#include "instance/evsys.h"
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#include "instance/gclk.h"
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#include "instance/i2s.h"
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#include "instance/mtb.h"
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#include "instance/nvmctrl.h"
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#include "instance/pac0.h"
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#include "instance/pac1.h"
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#include "instance/pac2.h"
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#include "instance/pm.h"
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#include "instance/port.h"
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#include "instance/rtc.h"
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#include "instance/sercom0.h"
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#include "instance/sercom1.h"
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#include "instance/sercom2.h"
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#include "instance/sercom3.h"
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#include "instance/sysctrl.h"
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#include "instance/tc3.h"
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#include "instance/tc4.h"
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#include "instance/tc5.h"
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#include "instance/tcc0.h"
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#include "instance/tcc1.h"
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#include "instance/tcc2.h"
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#include "instance/usb.h"
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#include "instance/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
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/* ************************************************************************** */
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/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
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/*@{*/
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// Peripheral instances on HPB0 bridge
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#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
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#define ID_PM 1 /**< \brief Power Manager (PM) */
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#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
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#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
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#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
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#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
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#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
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// Peripheral instances on HPB1 bridge
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#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
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#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
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#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
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#define ID_PORT 35 /**< \brief Port Module (PORT) */
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#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
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#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
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#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
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// Peripheral instances on HPB2 bridge
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#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
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#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
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#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
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#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
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#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
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#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
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#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
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#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
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#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
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#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
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#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
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#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
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#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
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#define ID_AC 81 /**< \brief Analog Comparators (AC) */
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#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
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#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
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#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
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#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
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/*@}*/
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/* ************************************************************************** */
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/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
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/* ************************************************************************** */
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/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
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/*@{*/
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#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
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#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
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#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
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#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
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#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
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#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
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#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
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#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
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#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
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#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
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#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
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#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
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#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
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#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
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#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
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#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
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#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
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#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
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#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
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#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
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#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
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#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
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#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
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#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
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#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
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#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
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#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
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#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
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#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
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#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21E15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E15A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21e15a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000 /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000D
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 1
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21E15A_H */
|
||||
|
|
@ -0,0 +1,500 @@
|
|||
#ifndef _SAMD21E16A_
|
||||
#define _SAMD21E16A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
|
||||
* This file defines all structures and symbols for SAMD21E16A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21E16A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E16A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E16A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E16A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21e16a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x10000 /* 64 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000 /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000C
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 1
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21E16A_H */
|
||||
|
|
@ -0,0 +1,500 @@
|
|||
#ifndef _SAMD21E17A_
|
||||
#define _SAMD21E17A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
|
||||
* This file defines all structures and symbols for SAMD21E17A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21E17A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E17A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E17A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E17A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21e17a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x20000 /* 128 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000B
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 1
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21E17A_H */
|
||||
|
|
@ -0,0 +1,500 @@
|
|||
#ifndef _SAMD21E18A_
|
||||
#define _SAMD21E18A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
|
||||
* This file defines all structures and symbols for SAMD21E18A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21E18A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E18A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E18A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21E18A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21e18a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x40000 /* 256 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 4096
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000A
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 1
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21E18A_H */
|
||||
|
|
@ -0,0 +1,512 @@
|
|||
#ifndef _SAMD21G15A_
|
||||
#define _SAMD21G15A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
|
||||
* This file defines all structures and symbols for SAMD21G15A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21G15A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G15A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G15A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G15A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21g15a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000 /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010008
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21G15A_H */
|
||||
|
|
@ -0,0 +1,512 @@
|
|||
#ifndef _SAMD21G16A_
|
||||
#define _SAMD21G16A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
|
||||
* This file defines all structures and symbols for SAMD21G16A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21G16A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G16A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G16A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G16A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21g16a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x10000 /* 64 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000 /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010007
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21G16A_H */
|
||||
|
|
@ -0,0 +1,512 @@
|
|||
#ifndef _SAMD21G17A_
|
||||
#define _SAMD21G17A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
|
||||
* This file defines all structures and symbols for SAMD21G17A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21G17A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G17A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G17A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G17A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21g17a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x20000 /* 128 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010006
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21G17A_H */
|
||||
|
|
@ -0,0 +1,512 @@
|
|||
#ifndef _SAMD21G18A_
|
||||
#define _SAMD21G18A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
|
||||
* This file defines all structures and symbols for SAMD21G18A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21G18A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G18A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G18A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21G18A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21g18a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x40000 /* 256 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 4096
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010005
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21G18A_H */
|
||||
|
|
@ -0,0 +1,524 @@
|
|||
#ifndef _SAMD21J15A_
|
||||
#define _SAMD21J15A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
|
||||
* This file defines all structures and symbols for SAMD21J15A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21J15A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J15A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J15A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tc6.h"
|
||||
#include "instance/tc7.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
|
||||
#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
|
||||
#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
|
||||
#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
|
||||
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J15A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21j15a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000 /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010003
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21J15A_H */
|
||||
|
|
@ -0,0 +1,524 @@
|
|||
#ifndef _SAMD21J16A_
|
||||
#define _SAMD21J16A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
|
||||
* This file defines all structures and symbols for SAMD21J16A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21J16A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J16A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J16A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tc6.h"
|
||||
#include "instance/tc7.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
|
||||
#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
|
||||
#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
|
||||
#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
|
||||
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J16A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21j16a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x10000 /* 64 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000 /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010002
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21J16A_H */
|
||||
|
|
@ -0,0 +1,524 @@
|
|||
#ifndef _SAMD21J17A_
|
||||
#define _SAMD21J17A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMD21_definitions
|
||||
* \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
|
||||
* This file defines all structures and symbols for SAMD21J17A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMD21J17A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samd21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J17A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/i2s.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J17A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/i2s.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tc6.h"
|
||||
#include "instance/tc7.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
|
||||
#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
|
||||
#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
|
||||
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
|
||||
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
|
||||
#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
|
||||
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMD21J17A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samd21j17a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x20000 /* 128 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010001
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMD21J17A_H */
|
||||
|
|
@ -0,0 +1,509 @@
|
|||
#ifndef _SAMR21E16A_
|
||||
#define _SAMR21E16A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMR21_definitions
|
||||
* \addtogroup SAMR21E16A_definitions SAMR21E16A definitions
|
||||
* This file defines all structures and symbols for SAMR21E16A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E16A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMR21E16A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samr21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E16A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rfctrl.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E16A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rfctrl.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E16A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E16A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RFCTRL (0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RFCTRL ((Rfctrl *)0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
|
||||
#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E16A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samr21e16a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x10000 /* 64 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001001E
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 3
|
||||
#define SIP_CONFIG RF233
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMR21E16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMR21E16A_H */
|
||||
|
|
@ -0,0 +1,509 @@
|
|||
#ifndef _SAMR21E17A_
|
||||
#define _SAMR21E17A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMR21_definitions
|
||||
* \addtogroup SAMR21E17A_definitions SAMR21E17A definitions
|
||||
* This file defines all structures and symbols for SAMR21E17A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E17A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMR21E17A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samr21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E17A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rfctrl.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E17A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rfctrl.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E17A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E17A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RFCTRL (0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RFCTRL ((Rfctrl *)0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
|
||||
#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E17A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samr21e17a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x20000 /* 128 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001001D
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 3
|
||||
#define SIP_CONFIG RF233
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMR21E17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMR21E17A_H */
|
||||
|
|
@ -0,0 +1,509 @@
|
|||
#ifndef _SAMR21E18A_
|
||||
#define _SAMR21E18A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMR21_definitions
|
||||
* \addtogroup SAMR21E18A_definitions SAMR21E18A definitions
|
||||
* This file defines all structures and symbols for SAMR21E18A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E18A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMR21E18A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samr21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E18A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rfctrl.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E18A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rfctrl.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E18A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E18A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RFCTRL (0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RFCTRL ((Rfctrl *)0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
|
||||
#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21E18A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samr21e18a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x40000 /* 256 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 4096
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001001C
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 3
|
||||
#define SIP_CONFIG RF233
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMR21E18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMR21E18A_H */
|
||||
|
|
@ -0,0 +1,509 @@
|
|||
#ifndef _SAMR21G16A_
|
||||
#define _SAMR21G16A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMR21_definitions
|
||||
* \addtogroup SAMR21G16A_definitions SAMR21G16A definitions
|
||||
* This file defines all structures and symbols for SAMR21G16A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G16A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMR21G16A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samr21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G16A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rfctrl.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G16A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rfctrl.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G16A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G16A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RFCTRL (0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RFCTRL ((Rfctrl *)0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
|
||||
#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G16A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samr21g16a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x10000 /* 64 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001001B
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 3
|
||||
#define SIP_CONFIG RF233
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMR21G16A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMR21G16A_H */
|
||||
|
|
@ -0,0 +1,509 @@
|
|||
#ifndef _SAMR21G17A_
|
||||
#define _SAMR21G17A_
|
||||
|
||||
/**
|
||||
* \ingroup SAMR21_definitions
|
||||
* \addtogroup SAMR21G17A_definitions SAMR21G17A definitions
|
||||
* This file defines all structures and symbols for SAMR21G17A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) ((type *)(value))
|
||||
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G17A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0+ Processor Exceptions Numbers *******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
|
||||
/****** SAMR21G17A-specific Interrupt Numbers ***********************/
|
||||
PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */
|
||||
SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */
|
||||
WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */
|
||||
EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */
|
||||
NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */
|
||||
DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */
|
||||
USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */
|
||||
EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */
|
||||
SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */
|
||||
SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */
|
||||
SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */
|
||||
SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */
|
||||
SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */
|
||||
SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */
|
||||
TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */
|
||||
TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */
|
||||
TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */
|
||||
TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */
|
||||
TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */
|
||||
TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */
|
||||
TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */
|
||||
TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */
|
||||
ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */
|
||||
AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */
|
||||
DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */
|
||||
PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnSYSCTRL_Handler; /* 1 System Control */
|
||||
void* pfnWDT_Handler; /* 2 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 3 Real-Time Counter */
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
|
||||
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
|
||||
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm0plus.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_samr21.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G17A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/mtb.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/rfctrl.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/sysctrl.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G17A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/mtb.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/pac0.h"
|
||||
#include "instance/pac1.h"
|
||||
#include "instance/pac2.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/rfctrl.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/sysctrl.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tc4.h"
|
||||
#include "instance/tc5.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G17A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
|
||||
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_PORT 35 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
|
||||
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
|
||||
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
|
||||
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
|
||||
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
|
||||
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
|
||||
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
|
||||
#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
|
||||
#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
|
||||
#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
|
||||
#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
|
||||
#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
|
||||
#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
|
||||
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
|
||||
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G17A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define RFCTRL (0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
|
||||
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
|
||||
#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
|
||||
#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
|
||||
#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
|
||||
#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
|
||||
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PTC_GCLK_ID 34
|
||||
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
|
||||
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
|
||||
|
||||
#define RFCTRL ((Rfctrl *)0x42005400U) /**< \brief (RFCTRL) APB Base Address */
|
||||
#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
|
||||
#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
||||
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
||||
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
|
||||
|
||||
#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
||||
#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
||||
#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
|
||||
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAMR21G17A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/samr21g17a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define FLASH_SIZE 0x20000 /* 128 kB */
|
||||
#define FLASH_PAGE_SIZE 64
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001001A
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define PORT_GROUPS 3
|
||||
#define SIP_CONFIG RF233
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAMR21G17A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAMR21G17A_H */
|
||||
|
|
@ -102,6 +102,11 @@ typedef enum {
|
|||
PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
|
||||
} PWMName;
|
||||
|
||||
struct pwm_pin_channel {
|
||||
PinName pin;
|
||||
PWMName pwm;
|
||||
uint8_t channel_index;
|
||||
};
|
||||
|
||||
#define STDIO_UART_TX USBTX
|
||||
#define STDIO_UART_RX USBRX
|
||||
|
|
@ -176,5 +176,30 @@ const PinMap PinMap_EXTINT[] = {
|
|||
{NC , NC , NC}
|
||||
};
|
||||
|
||||
const struct pwm_pin_channel pwn_pins[] = {
|
||||
{PA00, PWM_2, 0},
|
||||
{PA01, PWM_2, 1},
|
||||
{PA04, PWM_0, 0},
|
||||
{PA05, PWM_0, 1},
|
||||
{PA06, PWM_1, 0},
|
||||
{PA07, PWM_1, 1},
|
||||
{PA08, PWM_0, 0},
|
||||
{PA09, PWM_0, 1},
|
||||
{PA12, PWM_2, 0},
|
||||
{PA13, PWM_2, 1},
|
||||
{PA16, PWM_2, 0},
|
||||
{PA17, PWM_2, 1},
|
||||
{PA18, PWM_0, 2},
|
||||
{PA19, PWM_0, 3},
|
||||
{PA22, PWM_0, 4},
|
||||
{PA23, PWM_0, 5},
|
||||
{PA24, PWM_1, 2},
|
||||
{PA25, PWM_1, 3},
|
||||
{PA30, PWM_1, 0},
|
||||
{PA31, PWM_1, 1},
|
||||
|
||||
{NC, NC, NC}
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,112 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_dma_basic_use_case Quick Start Guide for Memory to Memory Data Transfer Using DMAC
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAMD21 Xplained Pro
|
||||
* - SAMR21 Xplained Pro
|
||||
* - SAMD11 Xplained Pro
|
||||
* - SAML21 Xplained Pro
|
||||
*
|
||||
* In this use case, the DMAC is configured for:
|
||||
* \li Moving data from memory to memory
|
||||
* \li Using software trigger
|
||||
* \li Using DMA priority level 0
|
||||
* \li Transaction as DMA trigger action
|
||||
* \li No action on input events
|
||||
* \li Output event not enabled
|
||||
*
|
||||
* \section asfdoc_sam0_dma_basic_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_dma_basic_use_casesetup_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_dma_basic_use_casesetup_code Code
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_dma_basic.c setup
|
||||
*
|
||||
* Add the below section to user application initialization (typically the
|
||||
* start of \c main()):
|
||||
* \snippet qs_dma_basic.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_dma_basic_use_casesetup_flow Workflow
|
||||
* -# Create a DMA resource configuration structure, which can be filled out to
|
||||
* adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_dma_basic.c setup_1
|
||||
* \br
|
||||
*
|
||||
* -# Initialize the DMA resource configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_dma_basic.c setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Allocate a DMA resource with the configurations.
|
||||
* \snippet qs_dma_basic.c setup_3
|
||||
* \br
|
||||
|
||||
* -# Declare a DMA transfer descriptor configuration structure, which can be
|
||||
* filled out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_dma_basic.c setup_4
|
||||
* \br
|
||||
*
|
||||
* -# Initialize the DMA transfer descriptor configuration struct with the
|
||||
* module's default values.
|
||||
* \snippet qs_dma_basic.c setup_5
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set the specific parameters for a DMA transfer with transfer size, source
|
||||
* address, and destination address. In this example, we have enabled the
|
||||
* source and destination address increment.
|
||||
* The source and destination addresses to be stored into descriptor_config
|
||||
* must correspond to the end of the transfer.
|
||||
*
|
||||
* \snippet qs_dma_basic.c setup_6
|
||||
* \br
|
||||
*
|
||||
* -# Create the DMA transfer descriptor.
|
||||
* \snippet qs_dma_basic.c setup_7
|
||||
* \br
|
||||
*
|
||||
* -# Add the DMA transfer descriptor to the allocated DMA resource.
|
||||
* \snippet qs_dma_basic.c add_descriptor_to_dma_resource
|
||||
* \br
|
||||
*
|
||||
* -# Register a callback to indicate transfer status.
|
||||
* \snippet qs_dma_basic.c setup_callback_register
|
||||
* \br
|
||||
*
|
||||
* -# Set the transfer done flag in the registered callback function.
|
||||
* \snippet qs_dma_basic.c _transfer_done
|
||||
* \br
|
||||
*
|
||||
* -# Enable the registered callbacks.
|
||||
* \snippet qs_dma_basic.c setup_enable_callback
|
||||
* \br
|
||||
*
|
||||
* \section asfdoc_sam0_dma_basic_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_dma_basic_use_casecode_code Code
|
||||
* Add the following code at the start of \c main():
|
||||
* \snippet qs_dma_basic.c sample_resource
|
||||
* Copy the following code to your user application:
|
||||
* \snippet qs_dma_basic.c main
|
||||
*
|
||||
* \subsection dma_basic_use_case_code_flow Workflow
|
||||
* -# Start the DMA transfer job with the allocated DMA resource and
|
||||
* transfer descriptor.
|
||||
* \snippet qs_dma_basic.c main_1
|
||||
*
|
||||
* -# Set the software trigger for the DMA channel. This can be done before
|
||||
* or after the DMA job is started. Note that all transfers needs a trigger
|
||||
* to start.
|
||||
* \snippet qs_dma_basic.c main_1_1
|
||||
*
|
||||
* -# Waiting for the setting of the transfer done flag.
|
||||
* \snippet qs_dma_basic.c main_2
|
||||
*/
|
||||
/**
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
|
||||
*
|
||||
* In this use case, the PORT module is configured for:
|
||||
* \li One pin in input mode, with pull-up enabled
|
||||
* \li One pin in output mode
|
||||
*
|
||||
* This use case sets up the PORT to read the current state of a GPIO pin set as
|
||||
* an input, and mirrors the opposite logical state on a pin configured as an
|
||||
* output.
|
||||
*
|
||||
* \section asfdoc_sam0_port_basic_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_port_basic.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_port_basic.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
|
||||
* -# Create a PORT module pin configuration struct, which can be filled out to
|
||||
* adjust the configuration of a single port pin.
|
||||
* \snippet qs_port_basic.c setup_1
|
||||
* -# Initialize the pin configuration struct with the module's default values.
|
||||
* \snippet qs_port_basic.c setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to request an input pin.
|
||||
* \snippet qs_port_basic.c setup_3
|
||||
* -# Configure push button pin with the initialized pin configuration struct, to enable
|
||||
* the input sampler on the pin.
|
||||
* \snippet qs_port_basic.c setup_4
|
||||
* -# Adjust the configuration struct to request an output pin.
|
||||
* \snippet qs_port_basic.c setup_5
|
||||
* \note The existing configuration struct may be re-used, as long as any
|
||||
* values that have been altered from the default settings are taken
|
||||
* into account by the user application.
|
||||
*
|
||||
* -# Configure LED pin with the initialized pin configuration struct, to enable
|
||||
* the output driver on the pin.
|
||||
* \snippet qs_port_basic.c setup_6
|
||||
*
|
||||
* \section asfdoc_sam0_port_basic_use_case_use_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_port_basic.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
|
||||
* -# Read in the current input sampler state of push button pin, which has been
|
||||
* configured as an input in the use-case setup code.
|
||||
* \snippet qs_port_basic.c main_1
|
||||
* -# Write the inverted pin level state to LED pin, which has been configured as
|
||||
* an output in the use-case setup code.
|
||||
* \snippet qs_port_basic.c main_2
|
||||
*/
|
||||
/**
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_sercom_i2c_master_basic_use_case Quick Start Guide for SERCOM I2C Master - Basic
|
||||
*
|
||||
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
|
||||
* - Master mode
|
||||
* - 100KHz operation speed
|
||||
* - Not operational in standby
|
||||
* - 10000 packet timeout value
|
||||
* - 65535 unknown bus state timeout value
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_basic_use_case_prereq Prerequisites
|
||||
* The device must be connected to an I<SUP>2</SUP>C slave.
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_basic_use_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_code Code
|
||||
* The following must be added to the user application:
|
||||
*
|
||||
* - A sample buffer to send, a sample buffer to read:
|
||||
* \snippet qs_i2c_master_basic_use.c packet_data
|
||||
*
|
||||
* - Slave address to access:
|
||||
* \snippet qs_i2c_master_basic_use.c address
|
||||
*
|
||||
* - Number of times to try to send packet if it fails:
|
||||
* \snippet qs_i2c_master_basic_use.c timeout
|
||||
*
|
||||
* - Globally accessible module structure:
|
||||
* \snippet qs_i2c_master_basic_use.c dev_inst
|
||||
*
|
||||
* - Function for setting up the module:
|
||||
* \snippet qs_i2c_master_basic_use.c initialize_i2c
|
||||
*
|
||||
* - Add to user application \c main():
|
||||
* \snippet qs_i2c_master_basic_use.c init
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_workflow Workflow
|
||||
* -# Configure and enable module.
|
||||
* \snippet qs_i2c_master_basic_use.c initialize_i2c
|
||||
* -# Create and initialize configuration structure.
|
||||
* \snippet qs_i2c_master_basic_use.c init_conf
|
||||
* -# Change settings in the configuration.
|
||||
* \snippet qs_i2c_master_basic_use.c conf_change
|
||||
* -# Initialize the module with the set configurations.
|
||||
* \snippet qs_i2c_master_basic_use.c init_module
|
||||
* -# Enable the module.
|
||||
* \snippet qs_i2c_master_basic_use.c enable_module
|
||||
* -# Create a variable to see when we should stop trying to send packet.
|
||||
* \snippet qs_i2c_master_basic_use.c timeout_counter
|
||||
* -# Create a packet to send.
|
||||
* \snippet qs_i2c_master_basic_use.c packet
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_basic_use_implemenation Implementation
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_code Code
|
||||
* Add to user application \c main():
|
||||
* \snippet qs_i2c_master_basic_use.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_workflow Workflow
|
||||
* -# Write packet to slave.
|
||||
* \snippet qs_i2c_master_basic_use.c write_packet
|
||||
* The module will try to send the packet TIMEOUT number of times or until it is
|
||||
* successfully sent.
|
||||
* -# Read packet from slave.
|
||||
* \snippet qs_i2c_master_basic_use.c read_packet
|
||||
* The module will try to read the packet TIMEOUT number of times or until it is
|
||||
* successfully read.
|
||||
*/
|
||||
/**
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_sercom_i2c_master_callback_use_case Quick Start Guide for SERCOM I2C Master - Callback
|
||||
*
|
||||
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
|
||||
* - Master mode
|
||||
* - 100KHz operation speed
|
||||
* - Not operational in standby
|
||||
* - 65535 unknown bus state timeout value
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_prereq Prerequisites
|
||||
* The device must be connected to an I<SUP>2</SUP>C slave.
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_setup_code Code
|
||||
* The following must be added to the user application:
|
||||
*
|
||||
* A sample buffer to write from, a reversed buffer to write from and length of
|
||||
* buffers.
|
||||
* \snippet qs_i2c_master_callback.c packet_data
|
||||
*
|
||||
* Address of slave:
|
||||
* \snippet qs_i2c_master_callback.c address
|
||||
*
|
||||
* Globally accessible module structure:
|
||||
* \snippet qs_i2c_master_callback.c dev_inst
|
||||
*
|
||||
* Globally accessible packet:
|
||||
* \snippet qs_i2c_master_callback.c packet_glob
|
||||
*
|
||||
* Function for setting up module:
|
||||
* \snippet qs_i2c_master_callback.c initialize_i2c
|
||||
*
|
||||
* Callback function for write complete:
|
||||
* \snippet qs_i2c_master_callback.c callback_func
|
||||
*
|
||||
* Function for setting up the callback functionality of the driver:
|
||||
* \snippet qs_i2c_master_callback.c setup_callback
|
||||
*
|
||||
* Add to user application \c main():
|
||||
* \snippet qs_i2c_master_callback.c run_initialize_i2c
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_setup_workflow Workflow
|
||||
* -# Configure and enable module.
|
||||
* \snippet qs_i2c_master_callback.c config
|
||||
* -# Create and initialize configuration structure.
|
||||
* \snippet qs_i2c_master_callback.c init_conf
|
||||
* -# Change settings in the configuration.
|
||||
* \snippet qs_i2c_master_callback.c conf_change
|
||||
* -# Initialize the module with the set configurations.
|
||||
* \snippet qs_i2c_master_callback.c init_module
|
||||
* -# Enable the module.
|
||||
* \snippet qs_i2c_master_callback.c enable_module
|
||||
* -# Configure callback functionality.
|
||||
* \snippet qs_i2c_master_callback.c config_callback
|
||||
* -# Register write complete callback.
|
||||
* \snippet qs_i2c_master_callback.c callback_reg
|
||||
* -# Enable write complete callback.
|
||||
* \snippet qs_i2c_master_callback.c callback_en
|
||||
* -# Create a packet to send to slave.
|
||||
* \snippet qs_i2c_master_callback.c write_packet
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_implementation Implementation
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_code Code
|
||||
* Add to user application \c main():
|
||||
* \snippet qs_i2c_master_callback.c while
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_implementation_workflow Workflow
|
||||
* -# Write packet to slave.
|
||||
* \snippet qs_i2c_master_callback.c write_packet
|
||||
* -# Infinite while loop, while waiting for interaction with slave.
|
||||
* \snippet qs_i2c_master_callback.c while
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_callback_use_case_callback Callback
|
||||
* Each time a packet is sent, the callback function will be called.
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_callback_workflow Workflow
|
||||
* - Write complete callback:
|
||||
* -# Send every other packet in reversed order.
|
||||
* \snippet qs_i2c_master_callback.c revert_order
|
||||
* -# Write new packet to slave.
|
||||
* \snippet qs_i2c_master_callback.c write_packet
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_sercom_i2c_master_dma_use_case Quick Start Guide for Using DMA with SERCOM I2C Master
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAMD21 Xplained Pro
|
||||
* - SAMR21 Xplained Pro
|
||||
* - SAML21 Xplained Pro
|
||||
*
|
||||
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
|
||||
* - Master mode
|
||||
* - 100KHz operation speed
|
||||
* - Not operational in standby
|
||||
* - 10000 packet timeout value
|
||||
* - 65535 unknown bus state timeout value
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_dma_use_case_prereq Prerequisites
|
||||
* The device must be connected to an I<SUP>2</SUP>C slave.
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_dma_use_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_code Code
|
||||
* The following must be added to the user application:
|
||||
*
|
||||
* - A sample buffer to send, number of entries to send and address of slave:
|
||||
* \snippet qs_i2c_master_dma.c packet_data
|
||||
*
|
||||
* Number of times to try to send packet if it fails:
|
||||
* \snippet qs_i2c_master_dma.c timeout
|
||||
*
|
||||
* - Globally accessible module structure:
|
||||
* \snippet qs_i2c_master_dma.c dev_i2c_inst
|
||||
*
|
||||
* - Function for setting up the module:
|
||||
* \snippet qs_i2c_master_dma.c initialize_i2c
|
||||
*
|
||||
* - Globally accessible DMA module structure:
|
||||
* \snippet qs_i2c_master_dma.c dma_resource
|
||||
*
|
||||
* - Globally transfer done flag:
|
||||
* \snippet qs_i2c_master_dma.c transfer_done_flag
|
||||
*
|
||||
* - Globally accessible DMA transfer descriptor:
|
||||
* \snippet qs_i2c_master_dma.c transfer_descriptor
|
||||
*
|
||||
* - Function for transfer done callback:
|
||||
* \snippet qs_i2c_master_dma.c transfer_done
|
||||
*
|
||||
* - Function for setting up the DMA resource:
|
||||
* \snippet qs_i2c_master_dma.c config_dma_resource
|
||||
*
|
||||
* - Function for setting up the DMA transfer descriptor:
|
||||
* \snippet qs_i2c_master_dma.c setup_dma_transfer_descriptor
|
||||
* - Add to user application \c main():
|
||||
* \snippet qs_i2c_master_dma.c init
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow Workflow
|
||||
* \subsubsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow_i2c Configure and enable SERCOM:
|
||||
* \snippet qs_i2c_master_dma.c config_i2c
|
||||
* -# Create and initialize configuration structure.
|
||||
* \snippet qs_i2c_master_dma.c init_conf
|
||||
* -# Change settings in the configuration.
|
||||
* \snippet qs_i2c_master_dma.c conf_change
|
||||
* -# Initialize the module with the set configurations.
|
||||
* \snippet qs_i2c_master_dma.c init_module
|
||||
* -# Enable the module.
|
||||
* \snippet qs_i2c_master_dma.c enable_module
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow_dma Configure DMA
|
||||
* -# Create a DMA resource configuration structure, which can be filled out to
|
||||
* adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_1
|
||||
*
|
||||
* -# Initialize the DMA resource configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set extra configurations for the DMA resource. It is using peripheral
|
||||
* trigger. SERCOM TX trigger causes a transaction transfer in
|
||||
* this example.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_3
|
||||
*
|
||||
* -# Allocate a DMA resource with the configurations.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_4
|
||||
*
|
||||
* -# Create a DMA transfer descriptor configuration structure, which can be
|
||||
* filled out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_5
|
||||
*
|
||||
* -# Initialize the DMA transfer descriptor configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_6
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set the specific parameters for a DMA transfer with transfer size, source
|
||||
* address, and destination address.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_7
|
||||
*
|
||||
* -# Create the DMA transfer descriptor.
|
||||
* \snippet qs_i2c_master_dma.c dma_setup_8
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_master_dma_use_implemenation Implementation
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_code Code
|
||||
* Add to user application \c main():
|
||||
* \snippet qs_i2c_master_dma.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_workflow Workflow
|
||||
* -# Start the DMA transfer job.
|
||||
* \snippet qs_i2c_master_dma.c start_transfer_job
|
||||
*
|
||||
* -# Set the auto address length and enable flag.
|
||||
* \snippet qs_i2c_master_dma.c set_i2c_addr
|
||||
*
|
||||
* -# Waiting for transfer complete.
|
||||
* \snippet qs_i2c_master_dma.c waiting_for_complete
|
||||
*
|
||||
* -# Enter an infinite loop once transfer complete.
|
||||
* \snippet qs_i2c_master_dma.c inf_loop
|
||||
*/
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_sercom_i2c_slave_basic_use_case Quick Start Guide for SERCOM I2C Slave - Basic
|
||||
*
|
||||
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
|
||||
* - Slave mode
|
||||
* - 100KHz operation speed
|
||||
* - Not operational in standby
|
||||
* - 10000 packet timeout value
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_slave_basic_use_case_prereq Prerequisites
|
||||
* The device must be connected to an I<SUP>2</SUP>C master.
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_slave_basic_use_case_setup_code Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_slave_basic_use_setup_code Code
|
||||
* The following must be added to the user application:
|
||||
*
|
||||
* A sample buffer to write from, a sample buffer to read to and length of buffers:
|
||||
* \snippet qs_i2c_slave_basic_use.c packet_data
|
||||
*
|
||||
* Address to respond to:
|
||||
* \snippet qs_i2c_slave_basic_use.c address
|
||||
*
|
||||
* Globally accessible module structure:
|
||||
* \snippet qs_i2c_slave_basic_use.c module
|
||||
*
|
||||
* Function for setting up the module:
|
||||
* \snippet qs_i2c_slave_basic_use.c initialize_i2c
|
||||
*
|
||||
* Add to user application \c main():
|
||||
* \snippet qs_i2c_slave_basic_use.c run_initialize_i2c
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_slave_basic_use_setup_workflow Workflow
|
||||
* -# Configure and enable module.
|
||||
* \snippet qs_i2c_slave_basic_use.c config
|
||||
* -# Create and initialize configuration structure.
|
||||
* \snippet qs_i2c_slave_basic_use.c init_conf
|
||||
* -# Change address and address mode settings in the configuration.
|
||||
* \snippet qs_i2c_slave_basic_use.c conf_changes
|
||||
* -# Initialize the module with the set configurations.
|
||||
* \snippet qs_i2c_slave_basic_use.c init_module
|
||||
* -# Enable the module.
|
||||
* \snippet qs_i2c_slave_basic_use.c enable_module
|
||||
* -# Create variable to hold transfer direction.
|
||||
* \snippet qs_i2c_slave_basic_use.c dir
|
||||
* -# Create packet variable to transfer.
|
||||
* \snippet qs_i2c_slave_basic_use.c pack
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_slave_basic_use_implementation Implementation
|
||||
* \subsection asfdoc_sam0_sercom_i2c_slave_basic_use_implementation_code Code
|
||||
* Add to user application \c main():
|
||||
* \snippet qs_i2c_slave_basic_use.c while
|
||||
* \subsection i2c_slave_basic_use_implementation_workflow Workflow
|
||||
* -# Wait for start condition from master and get transfer direction.
|
||||
* \snippet qs_i2c_slave_basic_use.c get_dir
|
||||
* -# Depending on transfer direction, set up buffer to read to or write from,
|
||||
* and write or read from master.
|
||||
* \snippet qs_i2c_slave_basic_use.c transfer
|
||||
*/
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
|
||||
|
|
@ -1,113 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_sercom_i2c_slave_dma_use_case Quick Start Guide for Using DMA with SERCOM I2C Slave
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAMD21 Xplained Pro
|
||||
* - SAMR21 Xplained Pro
|
||||
* - SAML21 Xplained Pro
|
||||
*
|
||||
* In this use case, the I<SUP>2</SUP>C will used and set up as follows:
|
||||
* - Slave mode
|
||||
* - 100KHz operation speed
|
||||
* - Not operational in standby
|
||||
* - 65535 unknown bus state timeout value
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_slave_dma_use_case_prereq Prerequisites
|
||||
* The device must be connected to an I<SUP>2</SUP>C slave.
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_slave_dma_use_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_code Code
|
||||
* The following must be added to the user application:
|
||||
*
|
||||
* - Address to respond to:
|
||||
* \snippet qs_i2c_slave_dma.c address
|
||||
*
|
||||
* - A sample buffer to send, number of entries to send and address of slave:
|
||||
* \snippet qs_i2c_slave_dma.c packet_data
|
||||
*
|
||||
* - Globally accessible module structure:
|
||||
* \snippet qs_i2c_slave_dma.c module
|
||||
*
|
||||
* - Function for setting up the module:
|
||||
* \snippet qs_i2c_slave_dma.c initialize_i2c
|
||||
*
|
||||
* - Globally accessible DMA module structure:
|
||||
* \snippet qs_i2c_slave_dma.c dma_resource
|
||||
*
|
||||
* - Globally accessible DMA transfer descriptor:
|
||||
* \snippet qs_i2c_slave_dma.c transfer_descriptor
|
||||
*
|
||||
* - Function for setting up the DMA resource:
|
||||
* \snippet qs_i2c_slave_dma.c config_dma_resource
|
||||
*
|
||||
* - Function for setting up the DMA transfer descriptor:
|
||||
* \snippet qs_i2c_slave_dma.c setup_dma_transfer_descriptor
|
||||
*
|
||||
* - Add to user application \c main():
|
||||
* \snippet qs_i2c_slave_dma.c init
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_workflow Workflow
|
||||
* \subsubsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_workflow_i2c Configure and enable SERCOM:
|
||||
* \snippet qs_i2c_slave_dma.c initialize_i2c
|
||||
* -# Create and initialize configuration structure.
|
||||
* \snippet qs_i2c_slave_dma.c init_conf
|
||||
* -# Change settings in the configuration.
|
||||
* \snippet qs_i2c_slave_dma.c conf_changes
|
||||
* -# Initialize the module with the set configurations.
|
||||
* \snippet qs_i2c_slave_dma.c init_module
|
||||
* -# Enable the module.
|
||||
* \snippet qs_i2c_slave_dma.c enable_module
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_workflow_dma Configure DMA
|
||||
* -# Create a DMA resource configuration structure, which can be filled out to
|
||||
* adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_1
|
||||
*
|
||||
* -# Initialize the DMA resource configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set extra configurations for the DMA resource. It is using peripheral
|
||||
* trigger. SERCOM RX trigger causes a beat transfer in this
|
||||
* example.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_3
|
||||
*
|
||||
* -# Allocate a DMA resource with the configurations.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_4
|
||||
*
|
||||
* -# Create a DMA transfer descriptor configuration structure, which can be
|
||||
* filled out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_5
|
||||
*
|
||||
* -# Initialize the DMA transfer descriptor configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_6
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set the specific parameters for a DMA transfer with transfer size, source
|
||||
* address, and destination address.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_7
|
||||
*
|
||||
* -# Create the DMA transfer descriptor.
|
||||
* \snippet qs_i2c_slave_dma.c dma_setup_8
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_i2c_slave_dma_use_implemenation Implementation
|
||||
* \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_implemenation_code Code
|
||||
* Add to user application \c main():
|
||||
* \snippet qs_i2c_slave_dma.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_implemenation_workflow Workflow
|
||||
* -# Start to wait a packet from master.
|
||||
* \snippet qs_i2c_slave_dma.c wait_packet
|
||||
*
|
||||
* -# Once data ready, clear the address match status.
|
||||
* \snippet qs_i2c_slave_dma.c clear_status
|
||||
*
|
||||
*/
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
|
||||
*
|
||||
* In this use case, the PINMUX module is configured for:
|
||||
* \li One pin in input mode, with pull-up enabled, connected to the GPIO
|
||||
* module
|
||||
* \li Sampling mode of the pin changed to sample on demand
|
||||
*
|
||||
* This use case sets up the PINMUX to configure a physical I/O pin set as
|
||||
* an input with pull-up and changes the sampling mode of the pin to reduce
|
||||
* power by only sampling the physical pin state when the user application
|
||||
* attempts to read it.
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
|
||||
* Copy-paste the following setup code to your application:
|
||||
* \snippet qs_pinmux_basic.c setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
|
||||
* -# Create a PINMUX module pin configuration struct, which can be filled out
|
||||
* to adjust the configuration of a single port pin.
|
||||
* \snippet qs_pinmux_basic.c pinmux_config
|
||||
* -# Initialize the pin configuration struct with the module's default values.
|
||||
* \snippet qs_pinmux_basic.c pinmux_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to request an input pin with pullup
|
||||
* connected to the GPIO peripheral.
|
||||
* \snippet qs_pinmux_basic.c pinmux_update_config_values
|
||||
* -# Configure GPIO10 with the initialized pin configuration struct, to enable
|
||||
* the input sampler on the pin.
|
||||
* \snippet qs_pinmux_basic.c pinmux_set_config
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_pinmux_basic.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
|
||||
|
||||
* -# Adjust the configuration of the pin to enable on-demand sampling mode.
|
||||
* \snippet qs_pinmux_basic.c pinmux_change_input_sampling
|
||||
*/
|
||||
/**
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_tcc_basic_use_case Quick Start Guide for TCC - Basic
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21 Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal. Here
|
||||
* the pulse width is set to one quarter of the period.
|
||||
* When connect PWM output to LED it makes the LED light. To see the waveform,
|
||||
* you may need an oscilloscope.
|
||||
*
|
||||
* The PWM output is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAMD21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAMR21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAML21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - No prescaler
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No fault or waveform extensions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input enabled
|
||||
* - No event action
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
* - Counter top set to 0xFFFF
|
||||
* - Capture compare channel 0 set to 0xFFFF/4
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_basic_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* \snippet conf_quick_start.h definition_pwm
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_basic.c module_inst
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_basic.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_basic.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_basic.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the TCC module.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_basic.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_basic.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode and the compare channel 0 value.
|
||||
* \snippet qs_tcc_basic.c setup_change_config
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_basic.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_basic.c setup_set_config
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_basic.c setup_enable
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_basic_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_basic.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_basic.c main_loop
|
||||
*/
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_tcc_buffering_use_case Quick Start Guide for TCC - Double Buffering and Circular
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21 Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal. Here
|
||||
* the pulse width alters in one quarter and three quarter of the period.
|
||||
* When connect PWM output to LED it makes the LED light. To see the waveform,
|
||||
* you may need an oscilloscope.
|
||||
*
|
||||
* The PWM output is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAMD21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAMR21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAML21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - Prescaler is set to 1024
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No fault or waveform extensions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input enabled
|
||||
* - No event action
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
* - Counter top set to 8000
|
||||
* - Capture compare channel set to 8000/4
|
||||
* - Capture compare channel buffer set to 8000*3/4
|
||||
* - Circular option for compare channel is enabled so that the compare
|
||||
* values keep switching on update condition
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_buffering_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* \snippet conf_quick_start_buffering.h definition_pwm
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_buffering.c module_inst
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_buffering.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_buffering.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_buffering.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the TCC module.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_buffering.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_buffering.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode and the compare channel 0 value.
|
||||
* \snippet qs_tcc_buffering.c setup_change_config
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_buffering.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_buffering.c setup_set_config
|
||||
* -# Set to compare buffer value and enable circular of double buffered
|
||||
* compare values.
|
||||
* \snippet qs_tcc_buffering.c setup_set_buffering
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_buffering.c setup_enable
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_buffering_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_buffering.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_buffering.c main_loop
|
||||
*/
|
||||
|
|
@ -1,220 +0,0 @@
|
|||
/**
|
||||
* \page asfdoc_sam0_tcc_dma_use_case Quick Start Guide for Using DMA with TCC
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21 Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal. Here
|
||||
* the pulse width varies through following values with the help of DMA
|
||||
* transfer: one quarter of the period, half of the period, and three quarters
|
||||
* of the period.
|
||||
* The PWM output can be used to drive an LED. The waveform can also be
|
||||
* viewed using an oscilloscope.
|
||||
* The output signal is also fed back to another TCC channel by event system,
|
||||
* the event stamps are captured and transferred to a buffer by DMA.
|
||||
*
|
||||
* The PWM output is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAMD21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAMR21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAML21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be setup as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - No prescaler
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No fault or waveform extensions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - Counter starts on 0
|
||||
* - Counter top set to 0x1000
|
||||
* - Channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is set to
|
||||
* compare and match value 0x1000*3/4 and generate event
|
||||
* - Channel 1 is set to capture on input event
|
||||
*
|
||||
* The event resource of EVSYS module will be setup as follows:
|
||||
* - TCC match capture channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is
|
||||
* selected as event generator
|
||||
* - Event generation is synchronous, with rising edge detected
|
||||
* - TCC match capture channel 1 is the event user
|
||||
*
|
||||
* The DMA resource of DMAC module will be setup as follows:
|
||||
* - Two DMA resources are used
|
||||
* - Both DMA resources use peripheral trigger
|
||||
* - Both DMA resources perform beat transfer on trigger
|
||||
* - Both DMA resources use beat size of 16 bits
|
||||
* - Both DMA resources are configured to transfer three beats and
|
||||
* then repeat again in same buffer
|
||||
* - On DMA resource which controls the compare value
|
||||
* - TCC0 overflow triggers DMA transfer
|
||||
* - The source address increment is enabled
|
||||
* - The destination address is fixed to TCC channel 0 Compare/Capture
|
||||
*register
|
||||
* - On DMA resource which reads the captured value
|
||||
* - TCC0 capture on channel 1 triggers DMA transfer
|
||||
* - The source address is fixed to TCC channel 1 Compare/Capture register
|
||||
* - The destination address increment is enabled
|
||||
* - The captured value is transferred to an array in SRAM
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_dma_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions, according to
|
||||
* the kit used:
|
||||
* - SAM D21 Xplained Pro.
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_dma_capture_trigger
|
||||
* - SAM R21 Xplained Pro.
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_dma_capture_trigger
|
||||
* - SAM L21 Xplained Pro.
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_dma.c module_inst
|
||||
* \snippet qs_tcc_dma.c capture_variables
|
||||
* \snippet qs_tcc_dma.c compare_variables
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_dma.c config_event_for_capture
|
||||
* \snippet qs_tcc_dma.c config_dma_for_capture
|
||||
* \snippet qs_tcc_dma.c config_dma_for_wave
|
||||
* \snippet qs_tcc_dma.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_dma.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_setup_flow Workflow
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_tcc Configure the TCC
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_dma.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_dma.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_dma.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode and the compare channel 0 value.
|
||||
* \snippet qs_tcc_dma.c setup_change_config
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_dma.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_dma.c setup_set_config
|
||||
* -# Configure and enable the desired events for the TCC module.
|
||||
* \snippet qs_tcc_dma.c setup_events
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_event Configure the Event System
|
||||
* Configure the EVSYS module to wire channel 0 event to channel 1.
|
||||
* -# Create an event resource instance.
|
||||
* \snippet qs_tcc_dma.c capture_event_resource
|
||||
* \note This should never go out of scope as long as the resource is in
|
||||
* use. In most cases, this should be global.
|
||||
*
|
||||
* -# Create an event resource configuration struct.
|
||||
* \snippet qs_tcc_dma.c event_setup_1
|
||||
* -# Initialize the event resource configuration struct with default values.
|
||||
* \snippet qs_tcc_dma.c event_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Adjust the event resource configuration to desired values.
|
||||
* \snippet qs_tcc_dma.c event_setup_3
|
||||
* -# Allocate and configure the resource using the configuration structure.
|
||||
* \snippet qs_tcc_dma.c event_setup_4
|
||||
* -# Attach a user to the resource.
|
||||
* \snippet qs_tcc_dma.c event_setup_5
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_dma_capture Configure the DMA for Capture TCC Channel 1
|
||||
* Configure the DMAC module to obtain captured value from TCC channel 1.
|
||||
* -# Create a DMA resource instance.
|
||||
* \snippet qs_tcc_dma.c capture_dma_resource
|
||||
* \note This should never go out of scope as long as the resource is in
|
||||
* use. In most cases, this should be global.
|
||||
* -# Create a DMA resource configuration struct.
|
||||
* \snippet qs_tcc_dma.c dma_setup_1
|
||||
* -# Initialize the DMA resource configuration struct with default values.
|
||||
* \snippet qs_tcc_dma.c dma_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Adjust the DMA resource configurations.
|
||||
* \snippet qs_tcc_dma.c dma_setup_3
|
||||
* -# Allocate a DMA resource with the configurations.
|
||||
* \snippet qs_tcc_dma.c dma_setup_4
|
||||
* -# Prepare DMA transfer descriptor.
|
||||
* -# Create a DMA transfer descriptor.
|
||||
* \snippet qs_tcc_dma.c capture_dma_descriptor
|
||||
* \note When multiple descriptors are linked, the linked item should
|
||||
* never go out of scope before it is loaded (to DMA Write-Back
|
||||
* memory section). In most cases, if more than one descriptors are
|
||||
* used, they should be global except the very first one.
|
||||
* -# Create a DMA transfer descriptor struct.
|
||||
* -# Create a DMA transfer descriptor configuration structure, which can be
|
||||
* filled out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_tcc_dma.c dma_setup_5
|
||||
* -# Initialize the DMA transfer descriptor configuration struct with
|
||||
* default values.
|
||||
* \snippet qs_tcc_dma.c dma_setup_6
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Adjust the DMA transfer descriptor configurations.
|
||||
* \snippet qs_tcc_dma.c dma_setup_7
|
||||
* -# Create the DMA transfer descriptor with the given configuration.
|
||||
* \snippet qs_tcc_dma.c dma_setup_8
|
||||
* -# Start DMA transfer job with prepared descriptor.
|
||||
* -# Add the DMA transfer descriptor to the allocated DMA resource.
|
||||
* \snippet qs_tcc_dma.c dma_setup_10
|
||||
* \note When adding multiple descriptors, the last added one is linked
|
||||
* at the end of descriptor queue. If ringed list is needed, just
|
||||
* add the first descriptor again to build the circle.
|
||||
* -# Start the DMA transfer job with the allocated DMA resource and
|
||||
* transfer descriptor.
|
||||
* \snippet qs_tcc_dma.c dma_setup_11
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_dma_compare Configure the DMA for Compare TCC Channel 0
|
||||
* Configure the DMAC module to update TCC channel 0 compare value.
|
||||
* The flow is similar to last DMA configure step for capture.
|
||||
* -# Allocate and configure the DMA resource.
|
||||
* \snippet qs_tcc_dma.c compare_dma_resource
|
||||
* \snippet qs_tcc_dma.c config_dma_resource_for_wave
|
||||
* -# Prepare DMA transfer descriptor.
|
||||
* \snippet qs_tcc_dma.c compare_dma_descriptor
|
||||
* \snippet qs_tcc_dma.c config_dma_descriptor_for_wave
|
||||
* -# Start DMA transfer job with prepared descriptor.
|
||||
* \snippet qs_tcc_dma.c config_dma_job_for_wave
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_dma.c setup_enable
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_dma_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_dma.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_dma.c main_loop
|
||||
*/
|
||||
|
|
@ -23,36 +23,7 @@
|
|||
|
||||
#include "pinmap_function.h"
|
||||
|
||||
struct pwm_pin_channel {
|
||||
PinName pin;
|
||||
PWMName pwm;
|
||||
uint8_t channel_index;
|
||||
};
|
||||
|
||||
static struct pwm_pin_channel pwn_pins[] = {
|
||||
{PA00, PWM_2, 0},
|
||||
{PA01, PWM_2, 1},
|
||||
{PA04, PWM_0, 0},
|
||||
{PA05, PWM_0, 1},
|
||||
{PA06, PWM_1, 0},
|
||||
{PA07, PWM_1, 1},
|
||||
{PA08, PWM_0, 0},
|
||||
{PA09, PWM_0, 1},
|
||||
{PA12, PWM_2, 0},
|
||||
{PA13, PWM_2, 1},
|
||||
{PA16, PWM_2, 0},
|
||||
{PA17, PWM_2, 1},
|
||||
{PA18, PWM_0, 2},
|
||||
{PA19, PWM_0, 3},
|
||||
{PA22, PWM_0, 4},
|
||||
{PA23, PWM_0, 5},
|
||||
{PA24, PWM_1, 2},
|
||||
{PA25, PWM_1, 3},
|
||||
{PA30, PWM_1, 0},
|
||||
{PA31, PWM_1, 1},
|
||||
|
||||
{NC, NC, NC}
|
||||
};
|
||||
extern struct pwm_pin_channel pwn_pins[];
|
||||
|
||||
static uint32_t pinmap_merge_pins(uint32_t a, uint32_t b)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -18,9 +18,11 @@
|
|||
#include "gpio_api.h"
|
||||
#include "port.h"
|
||||
|
||||
#if defined(TARGET_SAMR21G18A) // mask to be define for other targets
|
||||
#define PORTA_MASK 0xDBDFFFF3 // mask for available pins in Port A
|
||||
#define PORTB_MASK 0xC0C3C30D // mask for available pins in Port B
|
||||
#define PORTC_MASK 0x000D0000 // mask for available pins in Port C
|
||||
#endif
|
||||
|
||||
uint32_t start_pin(PortName port)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue