diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralNames.h deleted file mode 100644 index b26dec4246..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralNames.h +++ /dev/null @@ -1,95 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, - RTC_CLKIN = 2 -} RTCName; - -typedef enum { - UART_0 = (int)UART0_BASE, - UART_1 = (int)UART1_BASE, - UART_2 = (int)UART2_BASE -} UARTName; -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - I2C_0 = (int)I2C0_BASE, - I2C_1 = (int)I2C1_BASE, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5 - - PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0 - PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1 - - PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0 - PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1 -} PWMName; - -#define CHANNELS_A_SHIFT 5 -typedef enum { - ADC0_SE0 = 0, - ADC0_SE3 = 3, - ADC0_SE4a = (1 << CHANNELS_A_SHIFT) | (4), - ADC0_SE4b = 4, - ADC0_SE5b = 5, - ADC0_SE6b = 6, - ADC0_SE7a = (1 << CHANNELS_A_SHIFT) | (7), - ADC0_SE7b = 7, - ADC0_SE8 = 8, - ADC0_SE9 = 9, - ADC0_SE11 = 11, - ADC0_SE12 = 12, - ADC0_SE13 = 13, - ADC0_SE14 = 14, - ADC0_SE15 = 15, - ADC0_SE23 = 23 -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - - -typedef enum { - SPI_0 = (int)SPI0_BASE, - SPI_1 = (int)SPI1_BASE, -} SPIName; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralPins.c deleted file mode 100644 index ef77ff1882..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralPins.c +++ /dev/null @@ -1,197 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {PTC1, RTC_CLKIN, 1}, -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PTE20, ADC0_SE0, 0}, - {PTE22, ADC0_SE3, 0}, - {PTE21, ADC0_SE4a, 0}, - {PTE29, ADC0_SE4b, 0}, - {PTE30, ADC0_SE23, 0}, - {PTE23, ADC0_SE7a, 0}, - {PTB0, ADC0_SE8, 0}, - {PTB1, ADC0_SE9, 0}, - {PTB2, ADC0_SE12, 0}, - {PTB3, ADC0_SE13, 0}, - {PTC0, ADC0_SE14, 0}, - {PTC1, ADC0_SE15, 0}, - {PTC2, ADC0_SE11, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {NC, NC, 0} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {PTE30, DAC_0, 0}, - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTE25, I2C_0, 5}, - {PTC9, I2C_0, 2}, - {PTE0, I2C_1, 6}, - {PTB1, I2C_0, 2}, - {PTB3, I2C_0, 2}, - {PTC11, I2C_1, 2}, - {PTC2, I2C_1, 2}, - {PTA4, I2C_1, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTE24, I2C_0, 5}, - {PTC8, I2C_0, 2}, - {PTE1, I2C_1, 6}, - {PTB0, I2C_0, 2}, - {PTB2, I2C_0, 2}, - {PTC10, I2C_1, 2}, - {PTC1, I2C_1, 2}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PTC4, UART_1, 3}, - {PTA2, UART_0, 2}, - {PTD5, UART_2, 3}, - {PTD3, UART_2, 3}, - {PTD7, UART_0, 3}, - {PTE20, UART_0, 4}, - {PTE22, UART_2, 4}, - {PTE0, UART_1, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTC3, UART_1, 3}, - {PTA1, UART_0, 2}, - {PTD4, UART_2, 3}, - {PTD2, UART_2, 3}, - {PTD6, UART_0, 3}, - {PTE23, UART_2, 4}, - {PTE21, UART_0, 4}, - {PTE1, UART_1, 3}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PTA15, SPI_0, 2}, - {PTB11, SPI_1, 2}, - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {PTD5, SPI_1, 2}, - {PTE2, SPI_1, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PTA16, SPI_0, 2}, - {PTA17, SPI_0, 5}, - {PTB16, SPI_1, 2}, - {PTB17, SPI_1, 5}, - {PTC6, SPI_0, 2}, - {PTC7, SPI_0, 5}, - {PTD2, SPI_0, 2}, - {PTD3, SPI_0, 5}, - {PTD6, SPI_1, 2}, - {PTD7, SPI_1, 5}, - {PTE1, SPI_1, 2}, - {PTE3, SPI_1, 5}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PTA16, SPI_0, 5}, - {PTA17, SPI_0, 2}, - {PTB16, SPI_1, 5}, - {PTB17, SPI_1, 2}, - {PTC6, SPI_0, 5}, - {PTC7, SPI_0, 2}, - {PTD2, SPI_0, 5}, - {PTD3, SPI_0, 2}, - {PTD6, SPI_1, 5}, - {PTD7, SPI_1, 2}, - {PTE1, SPI_1, 5}, - {PTE3, SPI_1, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PTA14, SPI_0, 2}, - {PTB10, SPI_1, 2}, - {PTC4, SPI_0, 2}, - {PTD0, SPI_0, 2}, - {PTD4, SPI_1, 2}, - {PTE4, SPI_1, 2}, - {NC , NC , 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PTA0, PWM_6, 3}, // PTA0 , TPM0 CH5 - {PTA1, PWM_9 , 3}, // PTA1 , TPM2 CH0 - {PTA2, PWM_10, 3}, // PTA2 , TPM2 CH1 - {PTA3, PWM_1, 3}, // PTA3 , TPM0 CH0 - {PTA4, PWM_2 , 3}, // PTA4 , TPM0 CH1 - {PTA5, PWM_3 , 3}, // PTA5 , TPM0 CH2 - {PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0 - {PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1 - - {PTB0, PWM_7, 3}, // PTB0 , TPM1 CH0 - {PTB1, PWM_8, 3}, // PTB1 , TPM1 CH1 - {PTB2, PWM_9, 3}, // PTB2 , TPM2 CH0 - {PTB3, PWM_10, 3}, // PTB3 , TPM2 CH1 - {PTB18, PWM_9, 3}, // PTB18, TPM2 CH0 - {PTB19, PWM_10, 3}, // PTB18, TPM2 CH1 - - {PTC1, PWM_1, 4}, // PTC1 , TPM0 CH0 - {PTC2, PWM_2, 4}, // PTC2 , TPM0 CH1 - {PTC3, PWM_3, 4}, // PTC3 , TPM0 CH2 - {PTC4, PWM_4, 4}, // PTC4 , TPM0 CH3 - {PTC8, PWM_5 , 3}, // PTC8 , TPM0 CH4 - {PTC9, PWM_6 , 3}, // PTC9 , TPM0 CH5 - - {PTD0, PWM_1 , 4}, // PTD0 , TPM0 CH0 - {PTD1, PWM_2 , 4}, // PTD0 , TPM0 CH1 - {PTD2, PWM_3 , 4}, // PTD2 , TPM0 CH2 - {PTD3, PWM_4 , 4}, // PTD3 , TPM0 CH3 - {PTD4, PWM_5 , 4}, // PTD4 , TPM0 CH4 - {PTD5, PWM_6 , 4}, // PTD5 , TPM0 CH5 - - {PTE20, PWM_7, 3}, // PTE20, TPM1 CH0 - {PTE21, PWM_8, 3}, // PTE21, TPM1 CH1 - {PTE22, PWM_9, 3}, // PTE22, TPM2 CH0 - {PTE23, PWM_10, 3}, // PTE23, TPM2 CH1 - {PTE24, PWM_1, 3}, // PTE24, TPM0 CH0 - {PTE25, PWM_2, 3}, // PTE25, TPM0 CH1 - {PTE26, PWM_6, 3}, // PTE26, TPM0 CH5 - {PTE29, PWM_3, 3}, // PTE29, TPM0 CH2 - {PTE30, PWM_4, 3}, // PTE30, TPM0 CH3 - {PTE31, PWM_5, 3}, // PTE31, TPM0 CH4 - {NC , NC, 0} -}; diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PinNames.h b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PinNames.h deleted file mode 100644 index 32c244860c..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PinNames.h +++ /dev/null @@ -1,254 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 12 - -typedef enum { - PTA0 = 0x0, - PTA1 = 0x4, - PTA2 = 0x8, - PTA3 = 0xc, - PTA4 = 0x10, - PTA5 = 0x14, - PTA6 = 0x18, - PTA7 = 0x1c, - PTA8 = 0x20, - PTA9 = 0x24, - PTA10 = 0x28, - PTA11 = 0x2c, - PTA12 = 0x30, - PTA13 = 0x34, - PTA14 = 0x38, - PTA15 = 0x3c, - PTA16 = 0x40, - PTA17 = 0x44, - PTA18 = 0x48, - PTA19 = 0x4c, - PTA20 = 0x50, - PTA21 = 0x54, - PTA22 = 0x58, - PTA23 = 0x5c, - PTA24 = 0x60, - PTA25 = 0x64, - PTA26 = 0x68, - PTA27 = 0x6c, - PTA28 = 0x70, - PTA29 = 0x74, - PTA30 = 0x78, - PTA31 = 0x7c, - PTB0 = 0x1000, - PTB1 = 0x1004, - PTB2 = 0x1008, - PTB3 = 0x100c, - PTB4 = 0x1010, - PTB5 = 0x1014, - PTB6 = 0x1018, - PTB7 = 0x101c, - PTB8 = 0x1020, - PTB9 = 0x1024, - PTB10 = 0x1028, - PTB11 = 0x102c, - PTB12 = 0x1030, - PTB13 = 0x1034, - PTB14 = 0x1038, - PTB15 = 0x103c, - PTB16 = 0x1040, - PTB17 = 0x1044, - PTB18 = 0x1048, - PTB19 = 0x104c, - PTB20 = 0x1050, - PTB21 = 0x1054, - PTB22 = 0x1058, - PTB23 = 0x105c, - PTB24 = 0x1060, - PTB25 = 0x1064, - PTB26 = 0x1068, - PTB27 = 0x106c, - PTB28 = 0x1070, - PTB29 = 0x1074, - PTB30 = 0x1078, - PTB31 = 0x107c, - PTC0 = 0x2000, - PTC1 = 0x2004, - PTC2 = 0x2008, - PTC3 = 0x200c, - PTC4 = 0x2010, - PTC5 = 0x2014, - PTC6 = 0x2018, - PTC7 = 0x201c, - PTC8 = 0x2020, - PTC9 = 0x2024, - PTC10 = 0x2028, - PTC11 = 0x202c, - PTC12 = 0x2030, - PTC13 = 0x2034, - PTC14 = 0x2038, - PTC15 = 0x203c, - PTC16 = 0x2040, - PTC17 = 0x2044, - PTC18 = 0x2048, - PTC19 = 0x204c, - PTC20 = 0x2050, - PTC21 = 0x2054, - PTC22 = 0x2058, - PTC23 = 0x205c, - PTC24 = 0x2060, - PTC25 = 0x2064, - PTC26 = 0x2068, - PTC27 = 0x206c, - PTC28 = 0x2070, - PTC29 = 0x2074, - PTC30 = 0x2078, - PTC31 = 0x207c, - PTD0 = 0x3000, - PTD1 = 0x3004, - PTD2 = 0x3008, - PTD3 = 0x300c, - PTD4 = 0x3010, - PTD5 = 0x3014, - PTD6 = 0x3018, - PTD7 = 0x301c, - PTD8 = 0x3020, - PTD9 = 0x3024, - PTD10 = 0x3028, - PTD11 = 0x302c, - PTD12 = 0x3030, - PTD13 = 0x3034, - PTD14 = 0x3038, - PTD15 = 0x303c, - PTD16 = 0x3040, - PTD17 = 0x3044, - PTD18 = 0x3048, - PTD19 = 0x304c, - PTD20 = 0x3050, - PTD21 = 0x3054, - PTD22 = 0x3058, - PTD23 = 0x305c, - PTD24 = 0x3060, - PTD25 = 0x3064, - PTD26 = 0x3068, - PTD27 = 0x306c, - PTD28 = 0x3070, - PTD29 = 0x3074, - PTD30 = 0x3078, - PTD31 = 0x307c, - PTE0 = 0x4000, - PTE1 = 0x4004, - PTE2 = 0x4008, - PTE3 = 0x400c, - PTE4 = 0x4010, - PTE5 = 0x4014, - PTE6 = 0x4018, - PTE7 = 0x401c, - PTE8 = 0x4020, - PTE9 = 0x4024, - PTE10 = 0x4028, - PTE11 = 0x402c, - PTE12 = 0x4030, - PTE13 = 0x4034, - PTE14 = 0x4038, - PTE15 = 0x403c, - PTE16 = 0x4040, - PTE17 = 0x4044, - PTE18 = 0x4048, - PTE19 = 0x404c, - PTE20 = 0x4050, - PTE21 = 0x4054, - PTE22 = 0x4058, - PTE23 = 0x405c, - PTE24 = 0x4060, - PTE25 = 0x4064, - PTE26 = 0x4068, - PTE27 = 0x406c, - PTE28 = 0x4070, - PTE29 = 0x4074, - PTE30 = 0x4078, - PTE31 = 0x407c, - - LED_RED = PTE29, - LED_GREEN = PTE31, - LED_BLUE = PTD5, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - // USB Pins - USBTX = PTA2, - USBRX = PTA1, - - // Arduino Headers - D0 = PTA1, - D1 = PTA2, - D2 = PTD3, - D3 = PTA12, - D4 = PTA4, - D5 = PTA5, - D6 = PTC8, - D7 = PTC9, - D8 = PTA13, - D9 = PTD2, - D10 = PTD4, - D11 = PTD6, - D12 = PTD7, - D13 = PTD5, - D14 = PTE0, - D15 = PTE1, - - A0 = PTB0, - A1 = PTB1, - A2 = PTB2, - A3 = PTB3, - A4 = PTC2, - A5 = PTC1, - - I2C_SCL = D15, - I2C_SDA = D14, - - TSI_ELEC0 = PTB16, - TSI_ELEC1 = PTB17, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -/* PullDown not available for KL25 */ -typedef enum { - PullNone = 0, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device.h b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device.h deleted file mode 100644 index 29a4e7a0b1..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device.h +++ /dev/null @@ -1,39 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 24 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/MKL26Z4.h b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/MKL26Z4.h deleted file mode 100644 index 4d98cab21d..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/MKL26Z4.h +++ /dev/null @@ -1,4454 +0,0 @@ -/* -** ################################################################### -** Processors: MKL26Z128VFM4 -** MKL26Z64VFM4 -** MKL26Z32VM4 -** MKL26Z128VFT4 -** MKL26Z64VFT4 -** MKL26Z32VFT4 -** MKL26Z256VLH4 -** MKL26Z128VLH4 -** MKL26Z64VLH4 -** MKL26Z32VLH4 -** MKL26Z256VLK4 -** MKL26Z256VLL4 -** MKL26Z128VLL4 -** MKL26Z256VMC4 -** MKL26Z128VMC4 -** -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012 -** Version: rev. 1.0, 2012-12-12 -** -** Abstract: -** CMSIS Peripheral Access Layer for MKL26Z4 -** -** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-12-12) -** Initial version. -** -** ################################################################### -*/ - -/** - * @file MKL26Z4.h - * @version 1.0 - * @date 2012-12-12 - * @brief CMSIS Peripheral Access Layer for MKL26Z4 - * - * CMSIS Peripheral Access Layer for MKL26Z4 - */ - -#if !defined(MKL26Z4_H_) -#define MKL26Z4_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000u - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */ - DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */ - DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */ - DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */ - Reserved20_IRQn = 4, /**< Reserved interrupt 20 */ - FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */ - LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 7, /**< Low Leakage Wakeup */ - I2C0_IRQn = 8, /**< I2C0 interrupt */ - I2C1_IRQn = 9, /**< I2C0 interrupt 25 */ - SPI0_IRQn = 10, /**< SPI0 interrupt */ - SPI1_IRQn = 11, /**< SPI1 interrupt */ - UART0_IRQn = 12, /**< UART0 status/error interrupt */ - UART1_IRQn = 13, /**< UART1 status/error interrupt */ - UART2_IRQn = 14, /**< UART2 status/error interrupt */ - ADC0_IRQn = 15, /**< ADC0 interrupt */ - CMP0_IRQn = 16, /**< CMP0 interrupt */ - TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */ - TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */ - TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */ - RTC_IRQn = 20, /**< RTC interrupt */ - RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */ - PIT_IRQn = 22, /**< PIT timer interrupt */ - I2S0_IRQn = 23, /**< I2S0 transmit interrupt */ - USB0_IRQn = 24, /**< USB0 interrupt */ - DAC0_IRQn = 25, /**< DAC0 interrupt */ - TSI0_IRQn = 26, /**< TSI0 interrupt */ - MCG_IRQn = 27, /**< MCG interrupt */ - LPTimer_IRQn = 28, /**< LPTimer interrupt */ - Reserved45_IRQn = 29, /**< Reserved interrupt 45 */ - PORTA_IRQn = 30, /**< Port A interrupt */ - PORTD_IRQn = 31 /**< Port D interrupt */ -} IRQn_Type; - -/** - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M0 Core Configuration - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_MKL26Z4.h" /* Device specific configuration file */ - -/** - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ;Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;FTFA command complete and read collision - DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD UART0_IRQHandler ;UART0 status and error - DCD UART1_IRQHandler ;UART1 status and error - DCD UART2_IRQHandler ;UART2 status and error - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT_IRQHandler ;PIT single interrupt vector for all channels - DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources - DCD USB0_IRQHandler ;USB0 OTG - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD TSI0_IRQHandler ;TSI0 interrupt - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD Reserved45_IRQHandler ;Reserved interrupt - DCD PORTA_IRQHandler ;PORTA pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict access to the FTFL module. -; Backdoor Comparison Key -; Backdoor Comparison Key 0. <0x0-0xFF:2> -; Backdoor Comparison Key 1. <0x0-0xFF:2> -; Backdoor Comparison Key 2. <0x0-0xFF:2> -; Backdoor Comparison Key 3. <0x0-0xFF:2> -; Backdoor Comparison Key 4. <0x0-0xFF:2> -; Backdoor Comparison Key 5. <0x0-0xFF:2> -; Backdoor Comparison Key 6. <0x0-0xFF:2> -; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT0 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. -; NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; RESET_PIN_CFG -; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function -; <1=> RESET_b pin is dedicated -; LPBOOT1 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. -; FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -FOPT EQU 0xFF -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor Key Security Enable -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT init_data_bss - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - LDR R0, =FlashConfig ; dummy read, workaround for flashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =init_data_bss - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT Reserved20_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT TSI0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT Reserved45_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTC_PORTD_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_IRQHandler -USB0_IRQHandler -DAC0_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -Reserved45_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/MKL26Z4.ld b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/MKL26Z4.ld deleted file mode 100644 index 27567fdc18..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/MKL26Z4.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * KL25Z ARM GCC linker script file - */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410 - RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .isr_vector : - { - __vector_table = .; - KEEP(*(.vector_table)) - *(.text.Reset_Handler) - *(.text.System_Init) - . = ALIGN(8); - } > VECTORS - - .flash_protect : - { - KEEP(*(.kinetis_flash_config_field)) - . = ALIGN(8); - } > FLASH_PROTECTION - - .text : - { - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/startup_MKL26Z4.S b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/startup_MKL26Z4.S deleted file mode 100644 index 262de0d621..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/startup_MKL26Z4.S +++ /dev/null @@ -1,192 +0,0 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_MKL26Z4.s */ -/* @purpose: CMSIS Cortex-M0P Core Device Startup File */ -/* MKL26Z4 */ -/* @version: 1.7 */ -/* @date: 2015-2-18 */ -/* @build: b150218 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted provided that the following conditions are met: */ -/* */ -/* o Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* o Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv6-m - - .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long DMA0_IRQHandler /* DMA channel 0 transfer complete and error interrupt*/ - .long DMA1_IRQHandler /* DMA channel 1 transfer complete and error interrupt*/ - .long DMA2_IRQHandler /* DMA channel 2 transfer complete and error interrupt*/ - .long DMA3_IRQHandler /* DMA channel 3 transfer complete and error interrupt*/ - .long Reserved20_IRQHandler /* Reserved interrupt*/ - .long FTFA_IRQHandler /* FTFA command complete and read collision*/ - .long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/ - .long LLWU_IRQHandler /* Low Leakage Wakeup*/ - .long I2C0_IRQHandler /* I2C0 interrupt*/ - .long I2C1_IRQHandler /* I2C1 interrupt*/ - .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ - .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ - .long UART0_IRQHandler /* UART0 status and error*/ - .long UART1_IRQHandler /* UART1 status and error*/ - .long UART2_IRQHandler /* UART2 status and error*/ - .long ADC0_IRQHandler /* ADC0 interrupt*/ - .long CMP0_IRQHandler /* CMP0 interrupt*/ - .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ - .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ - .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ - .long RTC_IRQHandler /* RTC alarm interrupt*/ - .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ - .long PIT_IRQHandler /* PIT single interrupt vector for all channels*/ - .long I2S0_IRQHandler /* I2S0 Single interrupt vector for all sources*/ - .long USB0_IRQHandler /* USB0 OTG*/ - .long DAC0_IRQHandler /* DAC0 interrupt*/ - .long TSI0_IRQHandler /* TSI0 interrupt*/ - .long MCG_IRQHandler /* MCG interrupt*/ - .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ - .long Reserved45_IRQHandler /* Reserved interrupt*/ - .long PORTA_IRQHandler /* PORTA pin detect*/ - .long PORTC_PORTD_IRQHandler /* Single interrupt vector for PORTC and PORTD pin detect*/ - - .size __isr_vector, . - __isr_vector - -/* Flash Configuration */ - .section .FlashConfig, "a" - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFE - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - bl init_data_bss - cpsie i /* Unmask interrupts */ -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - bl __START -#else - bl __libc_init_array - bl main -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - ldr r0, =DefaultISR - bx r0 - .size DefaultISR, . - DefaultISR - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler SVC_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - def_irq_handler DMA0_IRQHandler - def_irq_handler DMA1_IRQHandler - def_irq_handler DMA2_IRQHandler - def_irq_handler DMA3_IRQHandler - def_irq_handler Reserved20_IRQHandler - def_irq_handler FTFA_IRQHandler - def_irq_handler LVD_LVW_IRQHandler - def_irq_handler LLWU_IRQHandler - def_irq_handler I2C0_IRQHandler - def_irq_handler I2C1_IRQHandler - def_irq_handler SPI0_IRQHandler - def_irq_handler SPI1_IRQHandler - def_irq_handler UART0_IRQHandler - def_irq_handler UART1_IRQHandler - def_irq_handler UART2_IRQHandler - def_irq_handler ADC0_IRQHandler - def_irq_handler CMP0_IRQHandler - def_irq_handler TPM0_IRQHandler - def_irq_handler TPM1_IRQHandler - def_irq_handler TPM2_IRQHandler - def_irq_handler RTC_IRQHandler - def_irq_handler RTC_Seconds_IRQHandler - def_irq_handler PIT_IRQHandler - def_irq_handler I2S0_IRQHandler - def_irq_handler USB0_IRQHandler - def_irq_handler DAC0_IRQHandler - def_irq_handler TSI0_IRQHandler - def_irq_handler MCG_IRQHandler - def_irq_handler LPTMR0_IRQHandler - def_irq_handler Reserved45_IRQHandler - def_irq_handler PORTA_IRQHandler - def_irq_handler PORTC_PORTD_IRQHandler - - .end diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/MKL26Z4.icf b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/MKL26Z4.icf deleted file mode 100644 index d800ef53fc..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/MKL26Z4.icf +++ /dev/null @@ -1,45 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff; -define symbol __ICFEDIT_region_NVIC_start__ = 0x1ffff000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffff0bf; -define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff0c0; -define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x1000; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __region_RAM2_start__ = 0x20000000; -define symbol __region_RAM2_end__ = 0x20002fff; - -define symbol __FlashConfig_start__ = 0x00000400; -define symbol __FlashConfig_end__ = 0x0000040f; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__]; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in FlashConfig_region {section FlashConfig}; - -place in ROM_region { readonly }; - -place in RAM_region { readwrite, block HEAP, block CSTACK }; diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.S b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.S deleted file mode 100644 index a0a74780cb..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.S +++ /dev/null @@ -1,251 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKL26Z4.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKL26Z4 -; @version: 1.7 -; @date: 2015-2-18 -; @build: b150218 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN init_data_bss - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;FTFA command complete and read collision - DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD UART0_IRQHandler ;UART0 status and error - DCD UART1_IRQHandler ;UART1 status and error - DCD UART2_IRQHandler ;UART2 status and error - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT_IRQHandler ;PIT single interrupt vector for all channels - DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources - DCD USB0_IRQHandler ;USB0 OTG - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD TSI0_IRQHandler ;TSI0 interrupt - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD Reserved45_IRQHandler ;Reserved interrupt - DCD PORTA_IRQHandler ;PORTA pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =init_data_bss - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA3_IRQHandler - PUBWEAK Reserved20_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK LVD_LVW_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK I2S0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK TSI0_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK Reserved45_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTC_PORTD_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_IRQHandler -USB0_IRQHandler -DAC0_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -Reserved45_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/cmsis.h b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/cmsis.h deleted file mode 100644 index 00c81648a6..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "MKL26Z4.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/cmsis_nvic.h b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/cmsis_nvic.h deleted file mode 100644 index 6ac00ce1f0..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFF000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/system_MKL26Z4.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/system_MKL26Z4.c deleted file mode 100644 index 503c25c0ca..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/system_MKL26Z4.c +++ /dev/null @@ -1,406 +0,0 @@ -/* -** ################################################################### -** Processors: MKL26Z128CAL4 -** MKL26Z128VFM4 -** MKL26Z64VFM4 -** MKL26Z32VM4 -** MKL26Z128VFT4 -** MKL26Z64VFT4 -** MKL26Z32VFT4 -** MKL26Z128VLH4 -** MKL26Z64VLH4 -** MKL26Z32VLH4 -** MKL26Z256VLH4 -** MKL26Z256VLL4 -** MKL26Z128VLL4 -** MKL26Z256VMC4 -** MKL26Z128VMC4 -** MKL26Z256VMP4 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013 -** KL26P121M48SF4RM, Rev.2, Dec 2012 -** -** Version: rev. 1.7, 2015-01-13 -** Build: b150129 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2015 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-12-12) -** Initial version. -** - rev. 1.1 (2013-04-05) -** Changed start of doxygen comment. -** - rev. 1.2 (2013-04-12) -** SystemInit function fixed for clock configuration 1. -** Name of the interrupt num. 31 updated to reflect proper function. -** - rev. 1.3 (2014-05-27) -** Updated to Kinetis SDK support standard. -** MCG OSC clock select supported (MCG_C7[OSCSEL]). -** - rev. 1.4 (2014-07-25) -** System initialization updated: -** - Prefix added to the system initialization parameterization constants to avoid name conflicts.. -** - VLLSx wake-up recovery added. -** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. -** - rev. 1.5 (2014-08-28) -** Update of system files - default clock configuration changed, fix of OSC initialization. -** Update of startup files - possibility to override DefaultISR added. -** - rev. 1.6 (2014-10-14) -** Renamed interrupt vector LPTimer to LPTMR0 -** - rev. 1.7 (2015-01-13) -** Update of the copyright. -** -** ################################################################### -*/ - -/*! - * @file MKL26Z4 - * @version 1.7 - * @date 2015-01-13 - * @brief Device specific configuration file for MKL26Z4 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "MKL26Z4.h" - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { - -#if (ACK_ISOLATION) - if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) { - PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */ - } -#endif - - /* Watchdog disable */ -#if (DISABLE_WDOG) - /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */ - SIM->COPC = (uint32_t)0x00u; -#endif /* (DISABLE_WDOG) */ - -#ifdef CLOCK_SETUP - /* RTC_CLKIN route */ -#if (RTC_CLKIN_USED) - /* SIM_SCGC5: PORTC=1 */ - SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; - /* PORTC_PCR1: ISF=0,MUX=1 */ - PORTC->PCR[1] = (uint32_t)((PORTC->PCR[1] & (uint32_t)~(uint32_t)( - PORT_PCR_ISF_MASK | - PORT_PCR_MUX(0x06) - )) | (uint32_t)( - PORT_PCR_MUX(0x01) - )); -#endif /* (RTC_CLKIN_USED) */ - - /* Wake-up from VLLSx? */ - if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U) - { - /* VLLSx recovery */ - if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U) - { - PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/ - } - } - - /* Power mode protection initialization */ -#ifdef SYSTEM_SMC_PMPROT_VALUE - SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE; -#endif - - /* System clock initialization */ - /* Internal reference clock trim initialization */ -#if defined(SLOW_TRIM_ADDRESS) - if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */ - MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS); -#endif /* defined(SLOW_TRIM_ADDRESS) */ -#if defined(SLOW_FINE_TRIM_ADDRESS) - MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK); -#endif -#if defined(FAST_TRIM_ADDRESS) - MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK); -#endif -#if defined(FAST_FINE_TRIM_ADDRESS) - MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK); -#endif /* defined(FAST_FINE_TRIM_ADDRESS) */ -#if defined(SLOW_TRIM_ADDRESS) - } -#endif /* defined(SLOW_TRIM_ADDRESS) */ - - /* Set system prescalers and clock sources */ - SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */ - SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */ - SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~( - SIM_SOPT2_TPMSRC_MASK | - SIM_SOPT2_UART0SRC_MASK | - SIM_SOPT2_PLLFLLSEL_MASK | - SIM_SOPT2_USBSRC_MASK - ))) | ((SYSTEM_SIM_SOPT2_VALUE) & ( - SIM_SOPT2_TPMSRC_MASK | - SIM_SOPT2_UART0SRC_MASK | - SIM_SOPT2_PLLFLLSEL_MASK | - SIM_SOPT2_USBSRC_MASK - )); /* Select TPM, LPUARTs, USB clock sources. */ -#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) - /* Set MCG and OSC */ -#if ((((SYSTEM_OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U)) - /* SIM_SCGC5: PORTA=1 */ - SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR18: ISF=0,MUX=0 */ - PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) { - /* PORTA_PCR19: ISF=0,MUX=0 */ - PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } -#endif - MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ - MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ - /* Check that the source of the FLL reference clock is the requested one. */ - if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { - } - } else { - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { - } - } - MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ - MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ - OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ - -#else /* MCG_MODE */ - /* Set MCG and OSC */ - /* SIM_SCGC5: PORTA=1 */ - SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR18: ISF=0,MUX=0 */ - PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) { - /* PORTA_PCR19: ISF=0,MUX=0 */ - PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } - MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ - MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ - OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ - #if (MCG_MODE == MCG_MODE_PEE) - MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/ - #else - MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ - #endif - if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) { - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ - } - } - /* Check that the source of the FLL reference clock is the requested one. */ - if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { - } - } else { - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { - } - } - MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ -#endif /* MCG_MODE */ - - /* Common for all MCG modes */ - - /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */ - MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */ - MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ - if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) { - MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */ - } - - /* BLPI and BLPE MCG mode specific */ -#if ((MCG_MODE == MCG_MODE_BLPI) || (MCG_MODE == MCG_MODE_BLPE)) - MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ - /* PEE and PBE MCG mode specific */ -#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE)) - MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/ - } - #if (MCG_MODE == MCG_MODE_PEE) - MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK); - #endif -#endif - - /* Clock mode status check */ -#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */ - } - /* Use LPTMR to wait for 1ms for FLL clock stabilization */ - SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* Allow software control of LPMTR */ - LPTMR0->CMR = LPTMR_CMR_COMPARE(0); /* Default 1 LPO tick */ - LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00)); - LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */ - LPTMR0->CSR = LPTMR_CSR_TEN_MASK; /* LPMTR enable */ - while((LPTMR0->CSR & LPTMR_CSR_TCF_MASK) == 0u) { - } - LPTMR0->CSR = 0x00; /* Disable LPTMR */ - SIM->SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK; -#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ - } -#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ - } -#elif (MCG_MODE == MCG_MODE_PEE) - while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */ - } -#endif - - /* Very-low-power run mode enable */ -#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT)) - SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */ - while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */ - } -#endif - - /* PLL loss of lock interrupt request initialization */ - if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) { - NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */ - } -#endif //#ifdef CLOCK_SETUP - -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint16_t Divider; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { - /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { - /* External reference clock is selected */ - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) { - switch (MCG->C1 & MCG_C1_FRDIV_MASK) { - case 0x38U: - Divider = 1536U; - break; - case 0x30U: - Divider = 1280U; - break; - default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - break; - } - } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - } - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x00U: - MCGOUTClock *= 640U; - break; - case 0x20U: - MCGOUTClock *= 1280U; - break; - case 0x40U: - MCGOUTClock *= 1920U; - break; - case 0x60U: - MCGOUTClock *= 2560U; - break; - case 0x80U: - MCGOUTClock *= 732U; - break; - case 0xA0U: - MCGOUTClock *= 1464U; - break; - case 0xC0U: - MCGOUTClock *= 2197U; - break; - case 0xE0U: - MCGOUTClock *= 2929U; - break; - default: - break; - } - } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - /* PLL is selected */ - Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); - MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ - Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ - } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); - MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { - /* External reference clock is selected */ - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - /* Reserved value */ - return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); - -} diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/system_MKL26Z4.h b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/system_MKL26Z4.h deleted file mode 100644 index 820241271f..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/system_MKL26Z4.h +++ /dev/null @@ -1,351 +0,0 @@ -/* -** ################################################################### -** Processors: MKL26Z128CAL4 -** MKL26Z128VFM4 -** MKL26Z64VFM4 -** MKL26Z32VM4 -** MKL26Z128VFT4 -** MKL26Z64VFT4 -** MKL26Z32VFT4 -** MKL26Z128VLH4 -** MKL26Z64VLH4 -** MKL26Z32VLH4 -** MKL26Z256VLH4 -** MKL26Z256VLL4 -** MKL26Z128VLL4 -** MKL26Z256VMC4 -** MKL26Z128VMC4 -** MKL26Z256VMP4 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013 -** KL26P121M48SF4RM, Rev.2, Dec 2012 -** -** Version: rev. 1.7, 2015-01-13 -** Build: b150129 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2015 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-12-12) -** Initial version. -** - rev. 1.1 (2013-04-05) -** Changed start of doxygen comment. -** - rev. 1.2 (2013-04-12) -** SystemInit function fixed for clock configuration 1. -** Name of the interrupt num. 31 updated to reflect proper function. -** - rev. 1.3 (2014-05-27) -** Updated to Kinetis SDK support standard. -** MCG OSC clock select supported (MCG_C7[OSCSEL]). -** - rev. 1.4 (2014-07-25) -** System initialization updated: -** - Prefix added to the system initialization parameterization constants to avoid name conflicts.. -** - VLLSx wake-up recovery added. -** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. -** - rev. 1.5 (2014-08-28) -** Update of system files - default clock configuration changed, fix of OSC initialization. -** Update of startup files - possibility to override DefaultISR added. -** - rev. 1.6 (2014-10-14) -** Renamed interrupt vector LPTimer to LPTMR0 -** - rev. 1.7 (2015-01-13) -** Update of the copyright. -** -** ################################################################### -*/ - -/*! - * @file MKL26Z4 - * @version 1.7 - * @date 2015-01-13 - * @brief Device specific configuration file for MKL26Z4 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MKL26Z4_H_ -#define SYSTEM_MKL26Z4_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -#define ACK_ISOLATION 1 - -#ifndef RTC_CLKIN_USED - #define RTC_CLKIN_USED 1 -#endif - - -/* MCG mode constants */ - -#define MCG_MODE_FEI 0U -#define MCG_MODE_FBI 1U -#define MCG_MODE_BLPI 2U -#define MCG_MODE_FEE 3U -#define MCG_MODE_FBE 4U -#define MCG_MODE_BLPE 5U -#define MCG_MODE_PBE 6U -#define MCG_MODE_PEE 7U - -/* Predefined clock setups - 0 ... Default part configuration - Multipurpose Clock Generator (MCG) in FEI mode. - Reference clock source for MCG module: Slow internal reference clock - Core clock = 20.97152MHz - Bus clock = 20.97152MHz - 1 ... Maximum achievable clock frequency configuration - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator reference clock - Core clock = 48MHz - Bus clock = 24MHz - 2 ... Chip internally clocked, ready for Very Low Power Run mode - Multipurpose Clock Generator (MCG) in BLPI mode. - Reference clock source for MCG module: Fast internal reference clock - Core clock = 4MHz - Bus clock = 0.8MHz - 3 ... Chip externally clocked, ready for Very Low Power Run mode - Multipurpose Clock Generator (MCG) in BLPE mode. - Reference clock source for MCG module: System oscillator reference clock - Core clock = 4MHz - Bus clock = 1MHz - 4 ... USB clock setup - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator reference clock - Core clock = 48MHz - Bus clock = 24MHz -*/ - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 8000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */ -#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */ - -/* RTC oscillator setting */ - -/* Low power mode enable */ -/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ -#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ - -/* Internal reference clock trim */ -/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ - -#ifdef CLOCK_SETUP -#if (CLOCK_SETUP == 0) - #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ - #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 1) - #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ - #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 2) - #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */ - /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 3) - #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */ - /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=3 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10030000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 4) - #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ - #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=24 */ - #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */ -#else - #error The selected clock setup is not supported. -#endif -#else //#ifdef CLOCK_SETUP - #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ -#endif //#ifdef CLOCK_SETUP - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MKL26Z4_H_) */ diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/gpio_irq_api.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/gpio_irq_api.c deleted file mode 100644 index 844007d7c2..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/gpio_irq_api.c +++ /dev/null @@ -1,170 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#define CHANNEL_NUM 64 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -#define IRQ_DISABLED (0) -#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9) -#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10) -#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11) - -const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001}; - -static void handle_interrupt_in(PORT_Type *port, int ch_base) { - uint32_t isfr; - uint8_t location; - - while((isfr = port->ISFR) != 0) { - location = 0; - for (int i = 0; i < 5; i++) { - if (!(isfr & (search_bits[i] << location))) - location += 1 << (4 - i); - } - - uint32_t id = channel_ids[ch_base + location]; - if (id == 0) { - continue; - } - - FGPIO_Type *gpio; - gpio_irq_event event = IRQ_NONE; - switch (port->PCR[location] & PORT_PCR_IRQC_MASK) { - case IRQ_RAISING_EDGE: - event = IRQ_RISE; - break; - - case IRQ_FALLING_EDGE: - event = IRQ_FALL; - break; - - case IRQ_EITHER_EDGE: - gpio = (port == PORTA) ? (FPTA) : (FPTD); - event = (gpio->PDIR & (1 << location)) ? (IRQ_RISE) : (IRQ_FALL); - break; - } - if (event != IRQ_NONE) { - irq_handler(id, event); - } - port->ISFR = 1 << location; - } -} - -void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);} -void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) return -1; - - irq_handler = handler; - - obj->port = pin >> PORT_SHIFT; - obj->pin = (pin & 0x7F) >> 2; - - uint32_t ch_base, vector; - IRQn_Type irq_n; - switch (obj->port) { - case PortA: - ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA; - break; - - case PortD: - ch_base = 32; irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD; - break; - - default: - error("gpio_irq only supported on port A and D"); - break; - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - obj->ch = ch_base + obj->pin; - channel_ids[obj->ch] = id; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port); - - uint32_t irq_settings = IRQ_DISABLED; - - switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) { - case IRQ_DISABLED: - if (enable) { - irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE); - } - break; - - case IRQ_RAISING_EDGE: - if (enable) { - irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE); - } else { - if (event == IRQ_FALL) - irq_settings = IRQ_RAISING_EDGE; - } - break; - - case IRQ_FALLING_EDGE: - if (enable) { - irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE); - } else { - if (event == IRQ_RISE) - irq_settings = IRQ_FALLING_EDGE; - } - break; - - case IRQ_EITHER_EDGE: - if (enable) { - irq_settings = IRQ_EITHER_EDGE; - } else { - irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE); - } - break; - } - - // Interrupt configuration and clear interrupt - port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK; -} - -void gpio_irq_enable(gpio_irq_t *obj) { - if (obj->port == PortA) { - NVIC_EnableIRQ(PORTA_IRQn); - } else if (obj->port == PortD) { - NVIC_EnableIRQ(PORTD_IRQn); - } -} - -void gpio_irq_disable(gpio_irq_t *obj) { - if (obj->port == PortA) { - NVIC_DisableIRQ(PORTA_IRQn); - } else if (obj->port == PortD) { - NVIC_DisableIRQ(PORTD_IRQn); - } -} diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/mbed_overrides.c deleted file mode 100644 index b590bb0ebc..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/mbed_overrides.c +++ /dev/null @@ -1,32 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" - -// called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//void mbed_sdk_init() -//{ -// -//} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - gpio_t gpio; - gpio_init_in(&gpio, PTA4); -} diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/serial_api.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/serial_api.c deleted file mode 100644 index d86a713c1a..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/serial_api.c +++ /dev/null @@ -1,337 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "serial_api.h" - -// math.h required for floating point operations for baud rate calculation -#include - -#include - -#include "cmsis.h" -#include "pinmap.h" -#include "clk_freqs.h" -#include "PeripheralPins.h" - -//Devices either user UART0 or UARTLP -#ifndef UARTLP_BASES - #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK - #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK - #define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK - #define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT - #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK - #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK - #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK - #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK - #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK - #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK - #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK -#endif - -#ifdef UART2 - #define UART_NUM 3 -#else - #define UART_NUM 1 -#endif - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - // determine the UART to use - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart != NC); - - obj->uart = (UARTLP_Type *)uart; - // enable clk - switch (uart) { - case UART_0: if (mcgpllfll_frequency() != 0) //PLL/FLL is selected - SIM->SOPT2 |= (1<SOPT2 |= (2<SCGC4 |= SIM_SCGC4_UART0_MASK; break; - #if UART_NUM > 1 - case UART_1: SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break; - case UART_2: SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break; - #endif - } - // Disable UART before changing registers - obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); - - // Enable UART transmitter to ensure TX activity is finished - obj->uart->C2 |= UARTLP_C2_TE_MASK; - - // Wait for TX activity to finish - while(!(obj->uart->S1 & UARTLP_S1_TC_MASK)); - - // Disbale UARTs again - obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); - - - switch (uart) { - case UART_0: obj->index = 0; break; - #if UART_NUM > 1 - case UART_1: obj->index = 1; break; - case UART_2: obj->index = 2; break; - #endif - } - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - // pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - // set rx/tx pins in PullUp mode and enable TX/RX - if (tx != NC) { - obj->uart->C2 |= UARTLP_C2_TE_MASK; - pin_mode(tx, PullUp); - } - if (rx != NC) { - obj->uart->C2 |= UARTLP_C2_RE_MASK; - pin_mode(rx, PullUp); - } - - if (uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; -} - -// serial_baud -// -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { - - // save C2 state - uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK)); - - // Disable UART before changing registers - obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); - - uint32_t PCLK; - if (obj->uart == UART0) { - if (mcgpllfll_frequency() != 0) - PCLK = mcgpllfll_frequency(); - else - PCLK = extosc_frequency(); - } else - PCLK = bus_frequency(); - - // First we check to see if the basic divide with no DivAddVal/MulVal - // ratio gives us an integer result. If it does, we set DivAddVal = 0, - // MulVal = 1. Otherwise, we search the valid ratio value range to find - // the closest match. This could be more elegant, using search methods - // and/or lookup tables, but the brute force method is not that much - // slower, and is more maintainable. - uint16_t DL = PCLK / (16 * baudrate); - - // set BDH and BDL - obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f); - obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff); - - // restore C2 state - obj->uart->C2 |= c2_state; -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT(data_bits == 8); // TODO: Support other number of data bits (also in the write method!) - - // save C2 state - uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK)); - - // Disable UART before changing registers - obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); - - - uint8_t parity_enable, parity_select; - switch (parity) { - case ParityNone: parity_enable = 0; parity_select = 0; break; - case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break; - case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break; - default: - break; - } - - stop_bits -= 1; - - // data bits, parity and parity mode - obj->uart->C1 = ((parity_enable << 1) - | (parity_select << 0)); - - // stop bits - obj->uart->BDH &= ~UARTLP_BDH_SBNS_MASK; - obj->uart->BDH |= (stop_bits << UARTLP_BDH_SBNS_SHIFT); - - // restore C2 state - obj->uart->C2 |= c2_state; -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint8_t status, uint32_t index) { - if (serial_irq_ids[index] != 0) { - if (status & UARTLP_S1_TDRE_MASK) - irq_handler(serial_irq_ids[index], TxIrq); - - if (status & UARTLP_S1_RDRF_MASK) - irq_handler(serial_irq_ids[index], RxIrq); - } -} - -void uart0_irq() { - uart_irq(UART0->S1, 0); - if (UART0->S1 & UARTLP_S1_OR_MASK) - UART0->S1 |= UARTLP_S1_OR_MASK; -} -#if UART_NUM > 1 -void uart1_irq() {uart_irq(UART1->S1, 1);} -void uart2_irq() {uart_irq(UART2->S1, 2);} -#endif - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; - #if UART_NUM > 1 - case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; - case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; - #endif - } - - if (enable) { - switch (irq) { - case RxIrq: obj->uart->C2 |= (UARTLP_C2_RIE_MASK); break; - case TxIrq: obj->uart->C2 |= (UARTLP_C2_TIE_MASK); break; - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - switch (irq) { - case RxIrq: obj->uart->C2 &= ~(UARTLP_C2_RIE_MASK); break; - case TxIrq: obj->uart->C2 &= ~(UARTLP_C2_TIE_MASK); break; - } - switch (other_irq) { - case RxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_RIE_MASK)) == 0; break; - case TxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_TIE_MASK)) == 0; break; - } - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) { - while (!serial_readable(obj)); - return obj->uart->D; -} - -void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)); - obj->uart->D = c; -} - -int serial_readable(serial_t *obj) { - // check overrun - if (obj->uart->S1 & UARTLP_S1_OR_MASK) { - obj->uart->S1 |= UARTLP_S1_OR_MASK; - } - return (obj->uart->S1 & UARTLP_S1_RDRF_MASK); -} - -int serial_writable(serial_t *obj) { - // check overrun - if (obj->uart->S1 & UARTLP_S1_OR_MASK) { - obj->uart->S1 |= UARTLP_S1_OR_MASK; - } - return (obj->uart->S1 & UARTLP_S1_TDRE_MASK); -} - -void serial_clear(serial_t *obj) { -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) { - obj->uart->C2 |= UARTLP_C2_SBK_MASK; -} - -void serial_break_clear(serial_t *obj) { - obj->uart->C2 &= ~UARTLP_C2_SBK_MASK; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/spi_api.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/spi_api.c deleted file mode 100644 index 07e690fe93..0000000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/spi_api.c +++ /dev/null @@ -1,281 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#include - -#include "cmsis.h" -#include "pinmap.h" - -static const PinMap PinMap_SPI_SCLK[] = { - {PTA15, SPI_0, 2}, - {PTB9, SPI_1, 2}, - {PTB11, SPI_1, 2}, - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {PTD5, SPI_1, 2}, - {PTE2, SPI_1, 2}, - {PTE17, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PTA16, SPI_0, 2}, - {PTA17, SPI_0, 5}, - {PTB16, SPI_1, 2}, - {PTB17, SPI_1, 5}, - {PTC6, SPI_0, 2}, - {PTC7, SPI_0, 5}, - {PTD2, SPI_0, 2}, - {PTD3, SPI_0, 5}, - {PTD6, SPI_1, 2}, - {PTD7, SPI_1, 5}, - {PTE1, SPI_1, 2}, - {PTE3, SPI_1, 5}, - {PTE18, SPI_0, 2}, - {PTE19, SPI_0, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PTA16, SPI_0, 5}, - {PTA17, SPI_0, 2}, - {PTB16, SPI_1, 5}, - {PTB17, SPI_1, 2}, - {PTC6, SPI_0, 5}, - {PTC7, SPI_0, 2}, - {PTD2, SPI_0, 5}, - {PTD3, SPI_0, 2}, - {PTD6, SPI_1, 5}, - {PTD7, SPI_1, 2}, - {PTE1, SPI_1, 5}, - {PTE3, SPI_1, 2}, - {PTE18, SPI_0, 5}, - {PTE19, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PTA14, SPI_0, 2}, - {PTB10, SPI_1, 2}, - {PTC4, SPI_0, 2}, - {PTD0, SPI_0, 2}, - {PTD4, SPI_1, 2}, - {PTE4, SPI_1, 2}, - {PTE16, SPI_0, 2}, - {NC , NC , 0} -}; - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->spi != NC); - - // enable power and clocking - switch ((int)obj->spi) { - case SPI_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 22; break; - case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break; - } - - // enable SPI - obj->spi->C1 |= SPI_C1_SPE_MASK; - obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) { - // [TODO] -} -void spi_format(spi_t *obj, int bits, int mode, int slave) { - MBED_ASSERT((bits == 8) || (bits == 16)); - MBED_ASSERT((mode >= 0) && (mode <= 3)); - - uint8_t polarity = (mode & 0x2) ? 1 : 0; - uint8_t phase = (mode & 0x1) ? 1 : 0; - uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2); - - // clear MSTR, CPOL and CPHA bits - obj->spi->C1 &= ~(0x7 << 2); - - // write new value - obj->spi->C1 |= c1_data; - if (bits == 8) { - obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; - } else { - obj->spi->C2 |= SPI_C2_SPIMODE_MASK; - } -} - -void spi_frequency(spi_t *obj, int hz) { - uint32_t error = 0; - uint32_t p_error = 0xffffffff; - uint32_t ref = 0; - uint8_t spr = 0; - uint8_t ref_spr = 0; - uint8_t ref_prescaler = 0; - - // bus clk - uint32_t PCLK = SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1); - uint8_t prescaler = 1; - uint8_t divisor = 2; - - for (prescaler = 1; prescaler <= 8; prescaler++) { - divisor = 2; - for (spr = 0; spr <= 8; spr++, divisor *= 2) { - ref = PCLK / (prescaler*divisor); - if (ref > (uint32_t)hz) - continue; - error = hz - ref; - if (error < p_error) { - ref_spr = spr; - ref_prescaler = prescaler - 1; - p_error = error; - } - } - } - - // set SPPR and SPR - obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf); -} - -static inline int spi_writeable(spi_t * obj) { - return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0; -} - -static inline int spi_readable(spi_t * obj) { - return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0; -} - -int spi_master_write(spi_t *obj, int value) { - int ret; - if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) { - // 16bit - while(!spi_writeable(obj)); - obj->spi->DL = (value & 0xff); - obj->spi->DH = ((value >> 8) & 0xff); - - // wait rx buffer full - while (!spi_readable(obj)); - ret = obj->spi->DH; - ret = (ret << 8) | obj->spi->DL; - } else { - //8bit - while(!spi_writeable(obj)); - obj->spi->DL = (value & 0xff); - - // wait rx buffer full - while (!spi_readable(obj)); - ret = (obj->spi->DL & 0xff); - } - - return ret; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *obj) { - return spi_readable(obj); -} - -int spi_slave_read(spi_t *obj) { - int ret; - if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) { - ret = obj->spi->DH; - ret = ((ret << 8) | obj->spi->DL); - } else { - ret = obj->spi->DL; - } - return ret; -} - -void spi_slave_write(spi_t *obj, int value) { - while (!spi_writeable(obj)); - if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) { - obj->spi->DL = (value & 0xff); - obj->spi->DH = ((value >> 8) & 0xff); - } else { - obj->spi->DL = value; - } - -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} diff --git a/targets/TARGET_Freescale/TARGET_KLXX/objects.h b/targets/TARGET_Freescale/TARGET_KLXX/objects.h index ddac9b61b2..cced33fe3d 100644 --- a/targets/TARGET_Freescale/TARGET_KLXX/objects.h +++ b/targets/TARGET_Freescale/TARGET_KLXX/objects.h @@ -29,8 +29,6 @@ extern "C" { #define UARTLP_Type UART0_Type #elif defined(TARGET_KL43Z) #define UARTLP_Type LPUART_Type -#elif defined(TARGET_KL26Z) - #define UARTLP_Type UART0_Type #endif struct gpio_irq_s { diff --git a/targets/TARGET_Freescale/mbed_rtx.h b/targets/TARGET_Freescale/mbed_rtx.h index e3637f2f7c..ed36b0cbee 100644 --- a/targets/TARGET_Freescale/mbed_rtx.h +++ b/targets/TARGET_Freescale/mbed_rtx.h @@ -67,12 +67,6 @@ #define INITIAL_SP (0x20003000UL) #endif -#elif defined(TARGET_KL26Z) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20003000UL) -#endif - #elif defined(TARGET_KL46Z) #ifndef INITIAL_SP diff --git a/targets/targets.json b/targets/targets.json index 00e707b3a6..2e0dc224c6 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -821,44 +821,6 @@ ], "device_name": "MKL25Z128xxx4" }, - "KL26Z": { - "supported_form_factors": [ - "ARDUINO" - ], - "core": "Cortex-M0+", - "extra_labels": [ - "Freescale", - "KLXX" - ], - "is_disk_virtual": true, - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "inherits": [ - "Target" - ], - "device_has": [ - "USTICKER", - "ANALOGIN", - "ANALOGOUT", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SEMIHOST", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES" - ], - "device_name": "MKL26Z128xxx4" - }, "KL46Z": { "supported_form_factors": [ "ARDUINO"