Merge pull request #15263 from MaximIntegrated/add-MAX32670

Add MAX32670

targets/TARGET_Maxim/CMakeLists.txt

@@ -1,4 +1,4 @@
-# Copyright (c) 2020-2021 ARM Limited. All rights reserved.
+# Copyright (c) 2022 ARM Limited. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
 
@@ -6,6 +6,7 @@ add_subdirectory(TARGET_MAX32620C EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MAX32625 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MAX32630 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MAX32660 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_MAX32670 EXCLUDE_FROM_ALL)
 
 add_library(mbed-maxim INTERFACE)
 

targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt

@@ -0,0 +1,132 @@
+# Copyright (c) 2022 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(TARGET_MAX32670EVKIT EXCLUDE_FROM_ALL)
+
+if(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(LINKER_FILE  device/TOOLCHAIN_ARM_STD/MAX32670.sct)
+    set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_max32670.S)
+elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(LINKER_FILE  device/TOOLCHAIN_GCC_ARM/max32670.ld)
+    set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_max32670.S)
+endif()
+
+add_library(mbed-max32670 INTERFACE)
+mbed_set_linker_script(mbed-max32670 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+set(MXM_PARTNUMBER          MAX32670)
+set(MXM_SOURCE_DIR          ./Libraries/PeriphDrivers/Source)
+set(MXM_PERIPH_DRIVER_DIR   ./Libraries/PeriphDrivers)
+set(MXM_CMSIS_DIR           ./Libraries/CMSIS/Device/Maxim)
+
+target_include_directories(mbed-max32670
+    INTERFACE
+        .
+        device
+        
+        ${MXM_PERIPH_DRIVER_DIR}/Include/${MXM_PARTNUMBER}
+        ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Include
+        
+        ${MXM_SOURCE_DIR}/AES
+        ${MXM_SOURCE_DIR}/CRC
+        ${MXM_SOURCE_DIR}/DMA
+        ${MXM_SOURCE_DIR}/LP
+        ${MXM_SOURCE_DIR}/FLC
+        ${MXM_SOURCE_DIR}/GPIO
+        ${MXM_SOURCE_DIR}/I2C
+        ${MXM_SOURCE_DIR}/I2S 
+        ${MXM_SOURCE_DIR}/ICC
+        ${MXM_SOURCE_DIR}/RTC
+        ${MXM_SOURCE_DIR}/SPI
+        ${MXM_SOURCE_DIR}/SYS
+        ${MXM_SOURCE_DIR}/TMR
+        ${MXM_SOURCE_DIR}/TRNG
+        ${MXM_SOURCE_DIR}/UART
+        ${MXM_SOURCE_DIR}/WDT
+)
+
+target_sources(mbed-max32670
+    INTERFACE
+        PeripheralPins.c
+        gpio_api.c
+        gpio_irq_api.c
+        i2c_api.c
+        pinmap.c
+        port_api.c
+        rtc_api.c
+        serial_api.c
+        sleep.c
+        spi_api.c
+        us_ticker.c
+        lp_ticker.c
+        flash_api.c
+        watchdog_api.c
+        
+        ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Source/system_max32670.c
+
+        ${MXM_SOURCE_DIR}/AES/aes_me15.c
+        ${MXM_SOURCE_DIR}/AES/aes_revb.c
+
+        ${MXM_SOURCE_DIR}/CRC/crc_me15.c
+        ${MXM_SOURCE_DIR}/CRC/crc_reva.c
+
+        ${MXM_SOURCE_DIR}/SYS/mxc_assert.c
+        ${MXM_SOURCE_DIR}/SYS/mxc_delay.c
+        ${MXM_SOURCE_DIR}/SYS/mxc_lock.c
+        ${MXM_SOURCE_DIR}/SYS/pins_me15.c
+        ${MXM_SOURCE_DIR}/SYS/sys_me15.c
+
+        ${MXM_SOURCE_DIR}/DMA/dma_me15.c
+        ${MXM_SOURCE_DIR}/DMA/dma_reva.c
+
+        ${MXM_SOURCE_DIR}/LP/lp_me15.c
+
+        ${MXM_SOURCE_DIR}/FLC/flc_common.c
+        ${MXM_SOURCE_DIR}/FLC/flc_me15.c
+        ${MXM_SOURCE_DIR}/FLC/flc_reva.c
+        ${MXM_SOURCE_DIR}/FLC/flc_revb.c
+
+        ${MXM_SOURCE_DIR}/GPIO/gpio_common.c
+        ${MXM_SOURCE_DIR}/GPIO/gpio_me15.c
+        ${MXM_SOURCE_DIR}/GPIO/gpio_reva.c
+
+        ${MXM_SOURCE_DIR}/I2C/i2c_me15.c
+        ${MXM_SOURCE_DIR}/I2C/i2c_reva.c
+
+        ${MXM_SOURCE_DIR}/I2S/i2s_me15.c
+        ${MXM_SOURCE_DIR}/I2S/i2s_reva.c
+
+        ${MXM_SOURCE_DIR}/ICC/icc_common.c
+        ${MXM_SOURCE_DIR}/ICC/icc_me15.c
+        ${MXM_SOURCE_DIR}/ICC/icc_reva.c
+
+        ${MXM_SOURCE_DIR}/RTC/rtc_me15.c
+        ${MXM_SOURCE_DIR}/RTC/rtc_reva.c
+
+        ${MXM_SOURCE_DIR}/SPI/spi_me15.c
+        ${MXM_SOURCE_DIR}/SPI/spi_reva.c
+
+        ${MXM_SOURCE_DIR}/TMR/tmr_common.c
+        ${MXM_SOURCE_DIR}/TMR/tmr_me15.c
+        ${MXM_SOURCE_DIR}/TMR/tmr_revb.c
+
+        ${MXM_SOURCE_DIR}/TRNG/trng_me15.c
+        ${MXM_SOURCE_DIR}/TRNG/trng_revb.c
+
+        ${MXM_SOURCE_DIR}/UART/uart_common.c
+        ${MXM_SOURCE_DIR}/UART/uart_me15.c
+        ${MXM_SOURCE_DIR}/UART/uart_revb.c
+
+        ${MXM_SOURCE_DIR}/WDT/wdt_common.c
+        ${MXM_SOURCE_DIR}/WDT/wdt_me15.c
+        ${MXM_SOURCE_DIR}/WDT/wdt_revb.c
+
+        ${STARTUP_FILE}
+)
+
+target_link_libraries(mbed-max32670
+    INTERFACE 
+        mbed-maxim
+)
+
+

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h

@@ -0,0 +1,117 @@
+/**
+ * @file    aes_key_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _AES_KEY_REGS_H_
+#define _AES_KEY_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     aes_key
+ * @defgroup    aes_key_registers AES_KEY_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
+ * @details AES Key Registers.
+ */
+
+/**
+ * @ingroup aes_key_registers
+ * Structure type to access the AES_KEY Registers.
+ */
+typedef struct {
+    __IO uint32_t aes_key0;             /**< <tt>\b 0x00:</tt> AES_KEY AES_KEY0 Register */
+    __IO uint32_t aes_key1;             /**< <tt>\b 0x04:</tt> AES_KEY AES_KEY1 Register */
+    __IO uint32_t aes_key2;             /**< <tt>\b 0x08:</tt> AES_KEY AES_KEY2 Register */
+    __IO uint32_t aes_key3;             /**< <tt>\b 0x0C:</tt> AES_KEY AES_KEY3 Register */
+    __IO uint32_t aes_key4;             /**< <tt>\b 0x10:</tt> AES_KEY AES_KEY4 Register */
+    __IO uint32_t aes_key5;             /**< <tt>\b 0x14:</tt> AES_KEY AES_KEY5 Register */
+    __IO uint32_t aes_key6;             /**< <tt>\b 0x18:</tt> AES_KEY AES_KEY6 Register */
+    __IO uint32_t aes_key7;             /**< <tt>\b 0x1C:</tt> AES_KEY AES_KEY7 Register */
+} mxc_aes_key_regs_t;
+
+/* Register offsets for module AES_KEY */
+/**
+ * @ingroup    aes_key_registers
+ * @defgroup   AES_KEY_Register_Offsets Register Offsets
+ * @brief      AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_AES_KEY_AES_KEY0             ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY1             ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY2             ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY3             ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY4             ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY5             ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY6             ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY7             ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: <tt> 0x001C</tt> */ 
+/**@} end of group aes_key_registers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AES_KEY_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h

@@ -0,0 +1,223 @@
+/**
+ * @file    aes_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _AES_REGS_H_
+#define _AES_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     aes
+ * @defgroup    aes_registers AES_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
+ * @details AES Keys.
+ */
+
+/**
+ * @ingroup aes_registers
+ * Structure type to access the AES Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x0000:</tt> AES CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x0004:</tt> AES STATUS Register */
+    __IO uint32_t intfl;                /**< <tt>\b 0x0008:</tt> AES INTFL Register */
+    __IO uint32_t inten;                /**< <tt>\b 0x000C:</tt> AES INTEN Register */
+    __IO uint32_t fifo;                 /**< <tt>\b 0x0010:</tt> AES FIFO Register */
+} mxc_aes_regs_t;
+
+/* Register offsets for module AES */
+/**
+ * @ingroup    aes_registers
+ * @defgroup   AES_Register_Offsets Register Offsets
+ * @brief      AES Peripheral Register Offsets from the AES Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_AES_CTRL                     ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_AES_STATUS                   ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_AES_INTFL                    ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_AES_INTEN                    ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_AES_FIFO                     ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: <tt> 0x0010</tt> */ 
+/**@} end of group aes_registers */
+
+/**
+ * @ingroup  aes_registers
+ * @defgroup AES_CTRL AES_CTRL
+ * @brief    AES Control Register
+ * @{
+ */
+ #define MXC_F_AES_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_AES_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_AES_CTRL_DMA_RX_EN_POS                   1 /**< CTRL_DMA_RX_EN Position */
+ #define MXC_F_AES_CTRL_DMA_RX_EN                       ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */
+
+ #define MXC_F_AES_CTRL_DMA_TX_EN_POS                   2 /**< CTRL_DMA_TX_EN Position */
+ #define MXC_F_AES_CTRL_DMA_TX_EN                       ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */
+
+ #define MXC_F_AES_CTRL_START_POS                       3 /**< CTRL_START Position */
+ #define MXC_F_AES_CTRL_START                           ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */
+
+ #define MXC_F_AES_CTRL_INPUT_FLUSH_POS                 4 /**< CTRL_INPUT_FLUSH Position */
+ #define MXC_F_AES_CTRL_INPUT_FLUSH                     ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */
+
+ #define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS                5 /**< CTRL_OUTPUT_FLUSH Position */
+ #define MXC_F_AES_CTRL_OUTPUT_FLUSH                    ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */
+
+ #define MXC_F_AES_CTRL_KEY_SIZE_POS                    6 /**< CTRL_KEY_SIZE Position */
+ #define MXC_F_AES_CTRL_KEY_SIZE                        ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */
+ #define MXC_V_AES_CTRL_KEY_SIZE_AES128                 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */
+ #define MXC_S_AES_CTRL_KEY_SIZE_AES128                 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */
+ #define MXC_V_AES_CTRL_KEY_SIZE_AES192                 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */
+ #define MXC_S_AES_CTRL_KEY_SIZE_AES192                 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */
+ #define MXC_V_AES_CTRL_KEY_SIZE_AES256                 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */
+ #define MXC_S_AES_CTRL_KEY_SIZE_AES256                 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */
+
+ #define MXC_F_AES_CTRL_TYPE_POS                        8 /**< CTRL_TYPE Position */
+ #define MXC_F_AES_CTRL_TYPE                            ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */
+
+/**@} end of group AES_CTRL_Register */
+
+/**
+ * @ingroup  aes_registers
+ * @defgroup AES_STATUS AES_STATUS
+ * @brief    AES Status Register
+ * @{
+ */
+ #define MXC_F_AES_STATUS_BUSY_POS                      0 /**< STATUS_BUSY Position */
+ #define MXC_F_AES_STATUS_BUSY                          ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
+
+ #define MXC_F_AES_STATUS_INPUT_EM_POS                  1 /**< STATUS_INPUT_EM Position */
+ #define MXC_F_AES_STATUS_INPUT_EM                      ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */
+
+ #define MXC_F_AES_STATUS_INPUT_FULL_POS                2 /**< STATUS_INPUT_FULL Position */
+ #define MXC_F_AES_STATUS_INPUT_FULL                    ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */
+
+ #define MXC_F_AES_STATUS_OUTPUT_EM_POS                 3 /**< STATUS_OUTPUT_EM Position */
+ #define MXC_F_AES_STATUS_OUTPUT_EM                     ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */
+
+ #define MXC_F_AES_STATUS_OUTPUT_FULL_POS               4 /**< STATUS_OUTPUT_FULL Position */
+ #define MXC_F_AES_STATUS_OUTPUT_FULL                   ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */
+
+/**@} end of group AES_STATUS_Register */
+
+/**
+ * @ingroup  aes_registers
+ * @defgroup AES_INTFL AES_INTFL
+ * @brief    AES Interrupt Flag Register
+ * @{
+ */
+ #define MXC_F_AES_INTFL_DONE_POS                       0 /**< INTFL_DONE Position */
+ #define MXC_F_AES_INTFL_DONE                           ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */
+
+ #define MXC_F_AES_INTFL_KEY_CHANGE_POS                 1 /**< INTFL_KEY_CHANGE Position */
+ #define MXC_F_AES_INTFL_KEY_CHANGE                     ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */
+
+ #define MXC_F_AES_INTFL_KEY_ZERO_POS                   2 /**< INTFL_KEY_ZERO Position */
+ #define MXC_F_AES_INTFL_KEY_ZERO                       ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */
+
+ #define MXC_F_AES_INTFL_OV_POS                         3 /**< INTFL_OV Position */
+ #define MXC_F_AES_INTFL_OV                             ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */
+
+/**@} end of group AES_INTFL_Register */
+
+/**
+ * @ingroup  aes_registers
+ * @defgroup AES_INTEN AES_INTEN
+ * @brief    AES Interrupt Enable Register
+ * @{
+ */
+ #define MXC_F_AES_INTEN_DONE_POS                       0 /**< INTEN_DONE Position */
+ #define MXC_F_AES_INTEN_DONE                           ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */
+
+ #define MXC_F_AES_INTEN_KEY_CHANGE_POS                 1 /**< INTEN_KEY_CHANGE Position */
+ #define MXC_F_AES_INTEN_KEY_CHANGE                     ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */
+
+ #define MXC_F_AES_INTEN_KEY_ZERO_POS                   2 /**< INTEN_KEY_ZERO Position */
+ #define MXC_F_AES_INTEN_KEY_ZERO                       ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */
+
+ #define MXC_F_AES_INTEN_OV_POS                         3 /**< INTEN_OV Position */
+ #define MXC_F_AES_INTEN_OV                             ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */
+
+/**@} end of group AES_INTEN_Register */
+
+/**
+ * @ingroup  aes_registers
+ * @defgroup AES_FIFO AES_FIFO
+ * @brief    AES Data Register
+ * @{
+ */
+ #define MXC_F_AES_FIFO_DATA_POS                        0 /**< FIFO_DATA Position */
+ #define MXC_F_AES_FIFO_DATA                            ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+
+/**@} end of group AES_FIFO_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AES_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h

@@ -0,0 +1,196 @@
+/**
+ * @file    crc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _CRC_REGS_H_
+#define _CRC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     crc
+ * @defgroup    crc_registers CRC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
+ * @details CRC Registers.
+ */
+
+/**
+ * @ingroup crc_registers
+ * Structure type to access the CRC Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x0000:</tt> CRC CTRL Register */
+  union{
+    __IO uint32_t datain32;             /**< <tt>\b 0x0004:</tt> CRC DATAIN32 Register */
+    __IO uint16_t datain16[2];          /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */
+    __IO uint8_t  datain8[4];           /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */
+  };
+    __IO uint32_t poly;                 /**< <tt>\b 0x0008:</tt> CRC POLY Register */
+    __IO uint32_t val;                  /**< <tt>\b 0x000C:</tt> CRC VAL Register */
+} mxc_crc_regs_t;
+
+/* Register offsets for module CRC */
+/**
+ * @ingroup    crc_registers
+ * @defgroup   CRC_Register_Offsets Register Offsets
+ * @brief      CRC Peripheral Register Offsets from the CRC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_CRC_CTRL                     ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_CRC_DATAIN32                 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_CRC_DATAIN16                 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_CRC_DATAIN8                  ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_CRC_POLY                     ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_CRC_VAL                      ((uint32_t)0x0000000CUL) /**< Offset from CRC Base Address: <tt> 0x000C</tt> */ 
+/**@} end of group crc_registers */
+
+/**
+ * @ingroup  crc_registers
+ * @defgroup CRC_CTRL CRC_CTRL
+ * @brief    CRC Control
+ * @{
+ */
+ #define MXC_F_CRC_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_CRC_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_CRC_CTRL_DMA_EN_POS                      1 /**< CTRL_DMA_EN Position */
+ #define MXC_F_CRC_CTRL_DMA_EN                          ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */
+
+ #define MXC_F_CRC_CTRL_MSB_POS                         2 /**< CTRL_MSB Position */
+ #define MXC_F_CRC_CTRL_MSB                             ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_MSB_POS)) /**< CTRL_MSB Mask */
+
+ #define MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS                3 /**< CTRL_BYTE_SWAP_IN Position */
+ #define MXC_F_CRC_CTRL_BYTE_SWAP_IN                    ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */
+
+ #define MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS               4 /**< CTRL_BYTE_SWAP_OUT Position */
+ #define MXC_F_CRC_CTRL_BYTE_SWAP_OUT                   ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */
+
+ #define MXC_F_CRC_CTRL_BUSY_POS                        16 /**< CTRL_BUSY Position */
+ #define MXC_F_CRC_CTRL_BUSY                            ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
+
+/**@} end of group CRC_CTRL_Register */
+
+/**
+ * @ingroup  crc_registers
+ * @defgroup CRC_DATAIN32 CRC_DATAIN32
+ * @brief    CRC Data Input
+ * @{
+ */
+ #define MXC_F_CRC_DATAIN32_DATA_POS                    0 /**< DATAIN32_DATA Position */
+ #define MXC_F_CRC_DATAIN32_DATA                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */
+
+/**@} end of group CRC_DATAIN32_Register */
+
+/**
+ * @ingroup  crc_registers
+ * @defgroup CRC_DATAIN16 CRC_DATAIN16
+ * @brief    CRC Data Input
+ * @{
+ */
+ #define MXC_F_CRC_DATAIN16_DATA_POS                    0 /**< DATAIN16_DATA Position */
+ #define MXC_F_CRC_DATAIN16_DATA                        ((uint16_t)(0xFFFFUL << MXC_F_CRC_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */
+
+/**@} end of group CRC_DATAIN16_Register */
+
+/**
+ * @ingroup  crc_registers
+ * @defgroup CRC_DATAIN8 CRC_DATAIN8
+ * @brief    CRC Data Input
+ * @{
+ */
+ #define MXC_F_CRC_DATAIN8_DATA_POS                     0 /**< DATAIN8_DATA Position */
+ #define MXC_F_CRC_DATAIN8_DATA                         ((uint8_t)(0xFFUL << MXC_F_CRC_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */
+
+/**@} end of group CRC_DATAIN8_Register */
+
+/**
+ * @ingroup  crc_registers
+ * @defgroup CRC_POLY CRC_POLY
+ * @brief    CRC Polynomial
+ * @{
+ */
+ #define MXC_F_CRC_POLY_POLY_POS                        0 /**< POLY_POLY Position */
+ #define MXC_F_CRC_POLY_POLY                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_POLY_POLY_POS)) /**< POLY_POLY Mask */
+
+/**@} end of group CRC_POLY_Register */
+
+/**
+ * @ingroup  crc_registers
+ * @defgroup CRC_VAL CRC_VAL
+ * @brief    Current CRC Value
+ * @{
+ */
+ #define MXC_F_CRC_VAL_VALUE_POS                        0 /**< VAL_VALUE Position */
+ #define MXC_F_CRC_VAL_VALUE                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_VAL_VALUE_POS)) /**< VAL_VALUE Mask */
+
+/**@} end of group CRC_VAL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CRC_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h

@@ -0,0 +1,453 @@
+/**
+ * @file    dma_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _DMA_REGS_H_
+#define _DMA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     dma
+ * @defgroup    dma_registers DMA_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
+ * @details DMA Controller Fully programmable, chaining capable DMA channels.
+ */
+
+/**
+ * @ingroup dma_registers
+ * Structure type to access the DMA Channel Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x100:</tt> DMA CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x104:</tt> DMA STATUS Register */
+    __IO uint32_t src;                  /**< <tt>\b 0x108:</tt> DMA SRC Register */
+    __IO uint32_t dst;                  /**< <tt>\b 0x10C:</tt> DMA DST Register */
+    __IO uint32_t cnt;                  /**< <tt>\b 0x110:</tt> DMA CNT Register */
+    __IO uint32_t srcrld;               /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
+    __IO uint32_t dstrld;               /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
+    __IO uint32_t cntrld;               /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
+} mxc_dma_ch_regs_t;
+
+/**
+ * @ingroup dma_registers
+ * Structure type to access the DMA Registers.
+ */
+typedef struct {
+    __IO uint32_t inten;                /**< <tt>\b 0x000:</tt> DMA INTEN Register */
+    __I  uint32_t intfl;                /**< <tt>\b 0x004:</tt> DMA INTFL Register */
+    __I  uint32_t rsv_0x8_0xff[62];
+    __IO mxc_dma_ch_regs_t    ch[8];    /**< <tt>\b 0x100:</tt> DMA CH Register */
+} mxc_dma_regs_t;
+
+/* Register offsets for module DMA */
+/**
+ * @ingroup    dma_registers
+ * @defgroup   DMA_Register_Offsets Register Offsets
+ * @brief      DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_DMA_CTRL                     ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 
+ #define MXC_R_DMA_STATUS                   ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */ 
+ #define MXC_R_DMA_SRC                      ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */ 
+ #define MXC_R_DMA_DST                      ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */ 
+ #define MXC_R_DMA_CNT                      ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */ 
+ #define MXC_R_DMA_SRCRLD                   ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */ 
+ #define MXC_R_DMA_DSTRLD                   ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */ 
+ #define MXC_R_DMA_CNTRLD                   ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */ 
+ #define MXC_R_DMA_INTEN                    ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_DMA_INTFL                    ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_DMA_CH                       ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 
+/**@} end of group dma_registers */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_INTEN DMA_INTEN
+ * @brief    DMA Control Register.
+ * @{
+ */
+ #define MXC_F_DMA_INTEN_CH0_POS                        0 /**< INTEN_CH0 Position */
+ #define MXC_F_DMA_INTEN_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */
+
+ #define MXC_F_DMA_INTEN_CH1_POS                        1 /**< INTEN_CH1 Position */
+ #define MXC_F_DMA_INTEN_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */
+
+ #define MXC_F_DMA_INTEN_CH2_POS                        2 /**< INTEN_CH2 Position */
+ #define MXC_F_DMA_INTEN_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */
+
+ #define MXC_F_DMA_INTEN_CH3_POS                        3 /**< INTEN_CH3 Position */
+ #define MXC_F_DMA_INTEN_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */
+
+ #define MXC_F_DMA_INTEN_CH4_POS                        4 /**< INTEN_CH4 Position */
+ #define MXC_F_DMA_INTEN_CH4                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */
+
+ #define MXC_F_DMA_INTEN_CH5_POS                        5 /**< INTEN_CH5 Position */
+ #define MXC_F_DMA_INTEN_CH5                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */
+
+ #define MXC_F_DMA_INTEN_CH6_POS                        6 /**< INTEN_CH6 Position */
+ #define MXC_F_DMA_INTEN_CH6                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */
+
+ #define MXC_F_DMA_INTEN_CH7_POS                        7 /**< INTEN_CH7 Position */
+ #define MXC_F_DMA_INTEN_CH7                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */
+
+/**@} end of group DMA_INTEN_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_INTFL DMA_INTFL
+ * @brief    DMA Interrupt Register.
+ * @{
+ */
+ #define MXC_F_DMA_INTFL_CH0_POS                        0 /**< INTFL_CH0 Position */
+ #define MXC_F_DMA_INTFL_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */
+
+ #define MXC_F_DMA_INTFL_CH1_POS                        1 /**< INTFL_CH1 Position */
+ #define MXC_F_DMA_INTFL_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */
+
+ #define MXC_F_DMA_INTFL_CH2_POS                        2 /**< INTFL_CH2 Position */
+ #define MXC_F_DMA_INTFL_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */
+
+ #define MXC_F_DMA_INTFL_CH3_POS                        3 /**< INTFL_CH3 Position */
+ #define MXC_F_DMA_INTFL_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */
+
+ #define MXC_F_DMA_INTFL_CH4_POS                        4 /**< INTFL_CH4 Position */
+ #define MXC_F_DMA_INTFL_CH4                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */
+
+ #define MXC_F_DMA_INTFL_CH5_POS                        5 /**< INTFL_CH5 Position */
+ #define MXC_F_DMA_INTFL_CH5                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */
+
+ #define MXC_F_DMA_INTFL_CH6_POS                        6 /**< INTFL_CH6 Position */
+ #define MXC_F_DMA_INTFL_CH6                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */
+
+ #define MXC_F_DMA_INTFL_CH7_POS                        7 /**< INTFL_CH7 Position */
+ #define MXC_F_DMA_INTFL_CH7                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */
+
+/**@} end of group DMA_INTFL_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CTRL DMA_CTRL
+ * @brief    DMA Channel Control Register.
+ * @{
+ */
+ #define MXC_F_DMA_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_DMA_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_DMA_CTRL_RLDEN_POS                       1 /**< CTRL_RLDEN Position */
+ #define MXC_F_DMA_CTRL_RLDEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */
+
+ #define MXC_F_DMA_CTRL_PRI_POS                         2 /**< CTRL_PRI Position */
+ #define MXC_F_DMA_CTRL_PRI                             ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */
+ #define MXC_V_DMA_CTRL_PRI_HIGH                        ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */
+ #define MXC_S_DMA_CTRL_PRI_HIGH                        (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */
+ #define MXC_V_DMA_CTRL_PRI_MEDHIGH                     ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */
+ #define MXC_S_DMA_CTRL_PRI_MEDHIGH                     (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */
+ #define MXC_V_DMA_CTRL_PRI_MEDLOW                      ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */
+ #define MXC_S_DMA_CTRL_PRI_MEDLOW                      (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */
+ #define MXC_V_DMA_CTRL_PRI_LOW                         ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */
+ #define MXC_S_DMA_CTRL_PRI_LOW                         (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */
+
+ #define MXC_F_DMA_CTRL_REQUEST_POS                     4 /**< CTRL_REQUEST Position */
+ #define MXC_F_DMA_CTRL_REQUEST                         ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */
+ #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM                ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */
+ #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM                (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI0RX                  ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI0RX                  (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI1RX                  ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI1RX                  (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI2RX                  ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI2RX                  (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART0RX                 ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART0RX                 (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART1RX                 ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART1RX                 (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2C0RX                  ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2C0RX                  (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2C1RX                  ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2C1RX                  (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2C2RX                  ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2C2RX                  (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART2RX                 ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART2RX                 (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI3RX                  ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI3RX                  (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_AESRX                   ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_AESRX                   (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART3RX                 ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART3RX                 (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2SRX                   ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2SRX                   (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI0TX                  ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI0TX                  (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI1TX                  ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI1TX                  (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI2TX                  ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI2TX                  (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART0TX                 ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART0TX                 (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART1TX                 ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART1TX                 (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2C0TX                  ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2C0TX                  (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2C1TX                  ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2C1TX                  (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2C2TX                  ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2C2TX                  (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_CRCTX                   ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_CRCTX                   (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART2TX                 ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART2TX                 (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_SPI3TX                  ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_SPI3TX                  (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_AESTX                   ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_AESTX                   (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_UART3TX                 ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_UART3TX                 (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */
+ #define MXC_V_DMA_CTRL_REQUEST_I2STX                   ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */
+ #define MXC_S_DMA_CTRL_REQUEST_I2STX                   (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */
+
+ #define MXC_F_DMA_CTRL_TO_WAIT_POS                     10 /**< CTRL_TO_WAIT Position */
+ #define MXC_F_DMA_CTRL_TO_WAIT                         ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */
+
+ #define MXC_F_DMA_CTRL_TO_PER_POS                      11 /**< CTRL_TO_PER Position */
+ #define MXC_F_DMA_CTRL_TO_PER                          ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */
+ #define MXC_V_DMA_CTRL_TO_PER_TO4                      ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO4                      (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */
+ #define MXC_V_DMA_CTRL_TO_PER_TO8                      ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO8                      (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */
+ #define MXC_V_DMA_CTRL_TO_PER_TO16                     ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO16                     (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */
+ #define MXC_V_DMA_CTRL_TO_PER_TO32                     ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO32                     (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */
+ #define MXC_V_DMA_CTRL_TO_PER_TO64                     ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO64                     (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */
+ #define MXC_V_DMA_CTRL_TO_PER_TO128                    ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO128                    (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */
+ #define MXC_V_DMA_CTRL_TO_PER_TO256                    ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO256                    (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */
+ #define MXC_V_DMA_CTRL_TO_PER_TO512                    ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */
+ #define MXC_S_DMA_CTRL_TO_PER_TO512                    (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */
+
+ #define MXC_F_DMA_CTRL_TO_CLKDIV_POS                   14 /**< CTRL_TO_CLKDIV Position */
+ #define MXC_F_DMA_CTRL_TO_CLKDIV                       ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */
+ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIS                   ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */
+ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIS                   (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */
+ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256                ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */
+ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */
+ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K                ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */
+ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */
+ #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M                ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */
+ #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */
+
+ #define MXC_F_DMA_CTRL_SRCWD_POS                       16 /**< CTRL_SRCWD Position */
+ #define MXC_F_DMA_CTRL_SRCWD                           ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */
+ #define MXC_V_DMA_CTRL_SRCWD_BYTE                      ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */
+ #define MXC_S_DMA_CTRL_SRCWD_BYTE                      (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */
+ #define MXC_V_DMA_CTRL_SRCWD_HALFWORD                  ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */
+ #define MXC_S_DMA_CTRL_SRCWD_HALFWORD                  (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */
+ #define MXC_V_DMA_CTRL_SRCWD_WORD                      ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */
+ #define MXC_S_DMA_CTRL_SRCWD_WORD                      (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */
+
+ #define MXC_F_DMA_CTRL_SRCINC_POS                      18 /**< CTRL_SRCINC Position */
+ #define MXC_F_DMA_CTRL_SRCINC                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */
+
+ #define MXC_F_DMA_CTRL_DSTWD_POS                       20 /**< CTRL_DSTWD Position */
+ #define MXC_F_DMA_CTRL_DSTWD                           ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */
+ #define MXC_V_DMA_CTRL_DSTWD_BYTE                      ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */
+ #define MXC_S_DMA_CTRL_DSTWD_BYTE                      (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */
+ #define MXC_V_DMA_CTRL_DSTWD_HALFWORD                  ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */
+ #define MXC_S_DMA_CTRL_DSTWD_HALFWORD                  (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */
+ #define MXC_V_DMA_CTRL_DSTWD_WORD                      ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */
+ #define MXC_S_DMA_CTRL_DSTWD_WORD                      (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */
+
+ #define MXC_F_DMA_CTRL_DSTINC_POS                      22 /**< CTRL_DSTINC Position */
+ #define MXC_F_DMA_CTRL_DSTINC                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */
+
+ #define MXC_F_DMA_CTRL_BURST_SIZE_POS                  24 /**< CTRL_BURST_SIZE Position */
+ #define MXC_F_DMA_CTRL_BURST_SIZE                      ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */
+
+ #define MXC_F_DMA_CTRL_DIS_IE_POS                      30 /**< CTRL_DIS_IE Position */
+ #define MXC_F_DMA_CTRL_DIS_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */
+
+ #define MXC_F_DMA_CTRL_CTZ_IE_POS                      31 /**< CTRL_CTZ_IE Position */
+ #define MXC_F_DMA_CTRL_CTZ_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */
+
+/**@} end of group DMA_CTRL_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_STATUS DMA_STATUS
+ * @brief    DMA Channel Status Register.
+ * @{
+ */
+ #define MXC_F_DMA_STATUS_STATUS_POS                    0 /**< STATUS_STATUS Position */
+ #define MXC_F_DMA_STATUS_STATUS                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
+
+ #define MXC_F_DMA_STATUS_IPEND_POS                     1 /**< STATUS_IPEND Position */
+ #define MXC_F_DMA_STATUS_IPEND                         ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */
+
+ #define MXC_F_DMA_STATUS_CTZ_IF_POS                    2 /**< STATUS_CTZ_IF Position */
+ #define MXC_F_DMA_STATUS_CTZ_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */
+
+ #define MXC_F_DMA_STATUS_RLD_IF_POS                    3 /**< STATUS_RLD_IF Position */
+ #define MXC_F_DMA_STATUS_RLD_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */
+
+ #define MXC_F_DMA_STATUS_BUS_ERR_POS                   4 /**< STATUS_BUS_ERR Position */
+ #define MXC_F_DMA_STATUS_BUS_ERR                       ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */
+
+ #define MXC_F_DMA_STATUS_TO_IF_POS                     6 /**< STATUS_TO_IF Position */
+ #define MXC_F_DMA_STATUS_TO_IF                         ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */
+
+/**@} end of group DMA_STATUS_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_SRC DMA_SRC
+ * @brief    Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or
+ *           4, depending on the data width of each AHB cycle. For peripheral transfers, some
+ *           or all of the actual address bits are fixed. If SRCINC=0, this register remains
+ *           constant. In the case where a count-to-zero condition occurs while RLDEN=1, the
+ *           register is reloaded with the contents of DMA_SRC_RLD.
+ * @{
+ */
+ #define MXC_F_DMA_SRC_ADDR_POS                         0 /**< SRC_ADDR Position */
+ #define MXC_F_DMA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */
+
+/**@} end of group DMA_SRC_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_DST DMA_DST
+ * @brief    Destination Device Address. For peripheral transfers, some or all of the actual
+ *           address bits are fixed. If DSTINC=1, this register is incremented on every AHB
+ *           write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the
+ *           data width of each AHB cycle. In the case where a count-to-zero condition occurs
+ *           while RLDEN=1, the register is reloaded with DMA_DST_RLD.
+ * @{
+ */
+ #define MXC_F_DMA_DST_ADDR_POS                         0 /**< DST_ADDR Position */
+ #define MXC_F_DMA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */
+
+/**@} end of group DMA_DST_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CNT DMA_CNT
+ * @brief    DMA Counter. The user loads this register with the number of bytes to transfer.
+ *           This counter decreases on every AHB cycle into the DMA FIFO. The decrement will
+ *           be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter
+ *           reaches 0, a count-to-zero condition is triggered.
+ * @{
+ */
+ #define MXC_F_DMA_CNT_CNT_POS                          0 /**< CNT_CNT Position */
+ #define MXC_F_DMA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
+
+/**@} end of group DMA_CNT_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_SRCRLD DMA_SRCRLD
+ * @brief    Source Address Reload Value. The value of this register is loaded into DMA0_SRC
+ *           upon a count-to-zero condition.
+ * @{
+ */
+ #define MXC_F_DMA_SRCRLD_ADDR_POS                      0 /**< SRCRLD_ADDR Position */
+ #define MXC_F_DMA_SRCRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */
+
+/**@} end of group DMA_SRCRLD_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_DSTRLD DMA_DSTRLD
+ * @brief    Destination Address Reload Value. The value of this register is loaded into
+ *           DMA0_DST upon a count-to-zero condition.
+ * @{
+ */
+ #define MXC_F_DMA_DSTRLD_ADDR_POS                      0 /**< DSTRLD_ADDR Position */
+ #define MXC_F_DMA_DSTRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */
+
+/**@} end of group DMA_DSTRLD_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CNTRLD DMA_CNTRLD
+ * @brief    DMA Channel Count Reload Register.
+ * @{
+ */
+ #define MXC_F_DMA_CNTRLD_CNT_POS                       0 /**< CNTRLD_CNT Position */
+ #define MXC_F_DMA_CNTRLD_CNT                           ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */
+
+ #define MXC_F_DMA_CNTRLD_EN_POS                        31 /**< CNTRLD_EN Position */
+ #define MXC_F_DMA_CNTRLD_EN                            ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */
+
+/**@} end of group DMA_CNTRLD_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DMA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h

@@ -0,0 +1,121 @@
+/**
+ * @file    ecc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the ECC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _ECC_REGS_H_
+#define _ECC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     ecc
+ * @defgroup    ecc_registers ECC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the ECC Peripheral Module.
+ * @details Error Correction Code
+ */
+
+/**
+ * @ingroup ecc_registers
+ * Structure type to access the ECC Registers.
+ */
+typedef struct {
+    __I  uint32_t rsv_0x0_0x7[2];
+    __IO uint32_t en;                   /**< <tt>\b 0x08:</tt> ECC EN Register */
+} mxc_ecc_regs_t;
+
+/* Register offsets for module ECC */
+/**
+ * @ingroup    ecc_registers
+ * @defgroup   ECC_Register_Offsets Register Offsets
+ * @brief      ECC Peripheral Register Offsets from the ECC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_ECC_EN                       ((uint32_t)0x00000008UL) /**< Offset from ECC Base Address: <tt> 0x0008</tt> */ 
+/**@} end of group ecc_registers */
+
+/**
+ * @ingroup  ecc_registers
+ * @defgroup ECC_EN ECC_EN
+ * @brief    ECC Enable Register
+ * @{
+ */
+ #define MXC_F_ECC_EN_RAM_POS                           8 /**< EN_RAM Position */
+ #define MXC_F_ECC_EN_RAM                               ((uint32_t)(0x1UL << MXC_F_ECC_EN_RAM_POS)) /**< EN_RAM Mask */
+
+ #define MXC_F_ECC_EN_ICC0_POS                          9 /**< EN_ICC0 Position */
+ #define MXC_F_ECC_EN_ICC0                              ((uint32_t)(0x1UL << MXC_F_ECC_EN_ICC0_POS)) /**< EN_ICC0 Mask */
+
+ #define MXC_F_ECC_EN_FLASH_POS                         10 /**< EN_FLASH Position */
+ #define MXC_F_ECC_EN_FLASH                             ((uint32_t)(0x1UL << MXC_F_ECC_EN_FLASH_POS)) /**< EN_FLASH Mask */
+
+/**@} end of group ECC_EN_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ECC_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/emcc_regs.h

@@ -0,0 +1,180 @@
+/**
+ * @file    emcc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _EMCC_REGS_H_
+#define _EMCC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     emcc
+ * @defgroup    emcc_registers EMCC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module.
+ * @details External Memory Cache Controller Registers.
+ */
+
+/**
+ * @ingroup emcc_registers
+ * Structure type to access the EMCC Registers.
+ */
+typedef struct {
+    __I  uint32_t cache_id;             /**< <tt>\b 0x0000:</tt> EMCC CACHE_ID Register */
+    __I  uint32_t memcfg;               /**< <tt>\b 0x0004:</tt> EMCC MEMCFG Register */
+    __I  uint32_t rsv_0x8_0xff[62];
+    __IO uint32_t cache_ctrl;           /**< <tt>\b 0x0100:</tt> EMCC CACHE_CTRL Register */
+    __I  uint32_t rsv_0x104_0x6ff[383];
+    __IO uint32_t invalidate;           /**< <tt>\b 0x0700:</tt> EMCC INVALIDATE Register */
+} mxc_emcc_regs_t;
+
+/* Register offsets for module EMCC */
+/**
+ * @ingroup    emcc_registers
+ * @defgroup   EMCC_Register_Offsets Register Offsets
+ * @brief      EMCC Peripheral Register Offsets from the EMCC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_EMCC_CACHE_ID                ((uint32_t)0x00000000UL) /**< Offset from EMCC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_EMCC_MEMCFG                  ((uint32_t)0x00000004UL) /**< Offset from EMCC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_EMCC_CACHE_CTRL              ((uint32_t)0x00000100UL) /**< Offset from EMCC Base Address: <tt> 0x0100</tt> */ 
+ #define MXC_R_EMCC_INVALIDATE              ((uint32_t)0x00000700UL) /**< Offset from EMCC Base Address: <tt> 0x0700</tt> */ 
+/**@} end of group emcc_registers */
+
+/**
+ * @ingroup  emcc_registers
+ * @defgroup EMCC_CACHE_ID EMCC_CACHE_ID
+ * @brief    Cache ID Register.
+ * @{
+ */
+ #define MXC_F_EMCC_CACHE_ID_RELNUM_POS                 0 /**< CACHE_ID_RELNUM Position */
+ #define MXC_F_EMCC_CACHE_ID_RELNUM                     ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
+
+ #define MXC_F_EMCC_CACHE_ID_PARTNUM_POS                6 /**< CACHE_ID_PARTNUM Position */
+ #define MXC_F_EMCC_CACHE_ID_PARTNUM                    ((uint32_t)(0xFUL << MXC_F_EMCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
+
+ #define MXC_F_EMCC_CACHE_ID_CCHID_POS                  10 /**< CACHE_ID_CCHID Position */
+ #define MXC_F_EMCC_CACHE_ID_CCHID                      ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
+
+/**@} end of group EMCC_CACHE_ID_Register */
+
+/**
+ * @ingroup  emcc_registers
+ * @defgroup EMCC_MEMCFG EMCC_MEMCFG
+ * @brief    Memory Configuration Register.
+ * @{
+ */
+ #define MXC_F_EMCC_MEMCFG_CCHSZ_POS                    0 /**< MEMCFG_CCHSZ Position */
+ #define MXC_F_EMCC_MEMCFG_CCHSZ                        ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
+
+ #define MXC_F_EMCC_MEMCFG_MEMSZ_POS                    16 /**< MEMCFG_MEMSZ Position */
+ #define MXC_F_EMCC_MEMCFG_MEMSZ                        ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
+
+/**@} end of group EMCC_MEMCFG_Register */
+
+/**
+ * @ingroup  emcc_registers
+ * @defgroup EMCC_CACHE_CTRL EMCC_CACHE_CTRL
+ * @brief    Cache Control and Status Register.
+ * @{
+ */
+ #define MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS             0 /**< CACHE_CTRL_CACHE_EN Position */
+ #define MXC_F_EMCC_CACHE_CTRL_CACHE_EN                 ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
+
+ #define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS       1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */
+ #define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN           ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */
+
+ #define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS            2 /**< CACHE_CTRL_CWFST_DIS Position */
+ #define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS                ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */
+
+ #define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS            16 /**< CACHE_CTRL_CACHE_RDY Position */
+ #define MXC_F_EMCC_CACHE_CTRL_CACHE_RDY                ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
+
+/**@} end of group EMCC_CACHE_CTRL_Register */
+
+/**
+ * @ingroup  emcc_registers
+ * @defgroup EMCC_INVALIDATE EMCC_INVALIDATE
+ * @brief    Invalidate All Cache Contents. Any time this register location is written
+ *           (regardless of the data value), the cache controller immediately begins
+ *           invalidating the entire contents of the cache memory. The cache will be in
+ *           bypass mode until the invalidate operation is complete. System software can
+ *           examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the
+ *           invalidate operation is complete. Note that it is not necessary to disable the
+ *           cache controller prior to beginning this operation. Reads from this register
+ *           always return 0.
+ * @{
+ */
+ #define MXC_F_EMCC_INVALIDATE_IA_POS                   0 /**< INVALIDATE_IA Position */
+ #define MXC_F_EMCC_INVALIDATE_IA                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */
+
+/**@} end of group EMCC_INVALIDATE_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _EMCC_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h

@@ -0,0 +1,192 @@
+/**
+ * @file    fcr_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _FCR_REGS_H_
+#define _FCR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     fcr
+ * @defgroup    fcr_registers FCR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
+ * @details Function Control Register.
+ */
+
+/**
+ * @ingroup fcr_registers
+ * Structure type to access the FCR Registers.
+ */
+typedef struct {
+    __IO uint32_t fctrl0;               /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */
+    __IO uint32_t autocal0;             /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */
+    __IO uint32_t autocal1;             /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */
+    __IO uint32_t autocal2;             /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */
+} mxc_fcr_regs_t;
+
+/* Register offsets for module FCR */
+/**
+ * @ingroup    fcr_registers
+ * @defgroup   FCR_Register_Offsets Register Offsets
+ * @brief      FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_FCR_FCTRL0                   ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_FCR_AUTOCAL0                 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_FCR_AUTOCAL1                 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_FCR_AUTOCAL2                 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 
+/**@} end of group fcr_registers */
+
+/**
+ * @ingroup  fcr_registers
+ * @defgroup FCR_FCTRL0 FCR_FCTRL0
+ * @brief    Register 0.
+ * @{
+ */
+ #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS            0 /**< FCTRL0_ERFO_RANGE_SEL Position */
+ #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL                ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) /**< FCTRL0_ERFO_RANGE_SEL Mask */
+
+ #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS        20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */
+ #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */
+
+ #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS        21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */
+ #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */
+
+ #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS        22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */
+ #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */
+
+ #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS        23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */
+ #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */
+
+ #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS        24 /**< FCTRL0_I2C2_SDA_FILTER_EN Position */
+ #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2_SDA_FILTER_EN Mask */
+
+ #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS        25 /**< FCTRL0_I2C2_SCL_FILTER_EN Position */
+ #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2_SCL_FILTER_EN Mask */
+
+/**@} end of group FCR_FCTRL0_Register */
+
+/**
+ * @ingroup  fcr_registers
+ * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0
+ * @brief    Register 1.
+ * @{
+ */
+ #define MXC_F_FCR_AUTOCAL0_SEL_POS                     0 /**< AUTOCAL0_SEL Position */
+ #define MXC_F_FCR_AUTOCAL0_SEL                         ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */
+
+ #define MXC_F_FCR_AUTOCAL0_EN_POS                      1 /**< AUTOCAL0_EN Position */
+ #define MXC_F_FCR_AUTOCAL0_EN                          ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */
+
+ #define MXC_F_FCR_AUTOCAL0_LOAD_POS                    2 /**< AUTOCAL0_LOAD Position */
+ #define MXC_F_FCR_AUTOCAL0_LOAD                        ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */
+
+ #define MXC_F_FCR_AUTOCAL0_INVERT_POS                  3 /**< AUTOCAL0_INVERT Position */
+ #define MXC_F_FCR_AUTOCAL0_INVERT                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */
+
+ #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS                  4 /**< AUTOCAL0_ATOMIC Position */
+ #define MXC_F_FCR_AUTOCAL0_ATOMIC                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */
+
+ #define MXC_F_FCR_AUTOCAL0_GAIN_POS                    8 /**< AUTOCAL0_GAIN Position */
+ #define MXC_F_FCR_AUTOCAL0_GAIN                        ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */
+
+ #define MXC_F_FCR_AUTOCAL0_TRIM_POS                    23 /**< AUTOCAL0_TRIM Position */
+ #define MXC_F_FCR_AUTOCAL0_TRIM                        ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */
+
+/**@} end of group FCR_AUTOCAL0_Register */
+
+/**
+ * @ingroup  fcr_registers
+ * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1
+ * @brief    Register 2.
+ * @{
+ */
+ #define MXC_F_FCR_AUTOCAL1_INITIAL_POS                 0 /**< AUTOCAL1_INITIAL Position */
+ #define MXC_F_FCR_AUTOCAL1_INITIAL                     ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) /**< AUTOCAL1_INITIAL Mask */
+
+/**@} end of group FCR_AUTOCAL1_Register */
+
+/**
+ * @ingroup  fcr_registers
+ * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2
+ * @brief    Register 3.
+ * @{
+ */
+ #define MXC_F_FCR_AUTOCAL2_RUNTIME_POS                 0 /**< AUTOCAL2_RUNTIME Position */
+ #define MXC_F_FCR_AUTOCAL2_RUNTIME                     ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */
+
+ #define MXC_F_FCR_AUTOCAL2_DIV_POS                     8 /**< AUTOCAL2_DIV Position */
+ #define MXC_F_FCR_AUTOCAL2_DIV                         ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */
+
+/**@} end of group FCR_AUTOCAL2_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FCR_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h

@@ -0,0 +1,295 @@
+/**
+ * @file    flc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_REGS_H_
+#define _FLC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     flc
+ * @defgroup    flc_registers FLC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ * @details Flash Memory Control.
+ */
+
+/**
+ * @ingroup flc_registers
+ * Structure type to access the FLC Registers.
+ */
+typedef struct {
+    __IO uint32_t addr;                 /**< <tt>\b 0x00:</tt> FLC ADDR Register */
+    __IO uint32_t clkdiv;               /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x08:</tt> FLC CTRL Register */
+    __I  uint32_t rsv_0xc_0x23[6];
+    __IO uint32_t intr;                 /**< <tt>\b 0x024:</tt> FLC INTR Register */
+    __IO uint32_t eccdata;              /**< <tt>\b 0x028:</tt> FLC ECCDATA Register */
+    __I  uint32_t rsv_0x2c;
+    __IO uint32_t data[4];              /**< <tt>\b 0x30:</tt> FLC DATA Register */
+    __O  uint32_t actrl;                /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
+    __I  uint32_t rsv_0x44_0x7f[15];
+    __IO uint32_t welr0;                /**< <tt>\b 0x80:</tt> FLC WELR0 Register */
+    __I  uint32_t rsv_0x84;
+    __IO uint32_t welr1;                /**< <tt>\b 0x88:</tt> FLC WELR1 Register */
+    __I  uint32_t rsv_0x8c;
+    __IO uint32_t rlr0;                 /**< <tt>\b 0x90:</tt> FLC RLR0 Register */
+    __I  uint32_t rsv_0x94;
+    __IO uint32_t rlr1;                 /**< <tt>\b 0x98:</tt> FLC RLR1 Register */
+} mxc_flc_regs_t;
+
+/* Register offsets for module FLC */
+/**
+ * @ingroup    flc_registers
+ * @defgroup   FLC_Register_Offsets Register Offsets
+ * @brief      FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_FLC_ADDR                     ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_FLC_CLKDIV                   ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_FLC_CTRL                     ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_FLC_INTR                     ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_FLC_ECCDATA                  ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_FLC_DATA                     ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_FLC_ACTRL                    ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_FLC_WELR0                    ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt> 0x0080</tt> */ 
+ #define MXC_R_FLC_WELR1                    ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt> 0x0088</tt> */ 
+ #define MXC_R_FLC_RLR0                     ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: <tt> 0x0090</tt> */ 
+ #define MXC_R_FLC_RLR1                     ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: <tt> 0x0098</tt> */ 
+/**@} end of group flc_registers */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_ADDR FLC_ADDR
+ * @brief    Flash Write Address.
+ * @{
+ */
+ #define MXC_F_FLC_ADDR_ADDR_POS                        0 /**< ADDR_ADDR Position */
+ #define MXC_F_FLC_ADDR_ADDR                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+
+/**@} end of group FLC_ADDR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_CLKDIV FLC_CLKDIV
+ * @brief    Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
+ *           MHz clock for Flash controller.
+ * @{
+ */
+ #define MXC_F_FLC_CLKDIV_CLKDIV_POS                    0 /**< CLKDIV_CLKDIV Position */
+ #define MXC_F_FLC_CLKDIV_CLKDIV                        ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group FLC_CLKDIV_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_CTRL FLC_CTRL
+ * @brief    Flash Control Register.
+ * @{
+ */
+ #define MXC_F_FLC_CTRL_WR_POS                          0 /**< CTRL_WR Position */
+ #define MXC_F_FLC_CTRL_WR                              ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */
+
+ #define MXC_F_FLC_CTRL_ME_POS                          1 /**< CTRL_ME Position */
+ #define MXC_F_FLC_CTRL_ME                              ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */
+
+ #define MXC_F_FLC_CTRL_PGE_POS                         2 /**< CTRL_PGE Position */
+ #define MXC_F_FLC_CTRL_PGE                             ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
+
+ #define MXC_F_FLC_CTRL_ERASE_CODE_POS                  8 /**< CTRL_ERASE_CODE Position */
+ #define MXC_F_FLC_CTRL_ERASE_CODE                      ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
+ #define MXC_V_FLC_CTRL_ERASE_CODE_NOP                  ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
+ #define MXC_S_FLC_CTRL_ERASE_CODE_NOP                  (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
+ #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE            ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
+ #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE            (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
+ #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL             ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
+ #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL             (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
+
+ #define MXC_F_FLC_CTRL_PEND_POS                        24 /**< CTRL_PEND Position */
+ #define MXC_F_FLC_CTRL_PEND                            ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
+
+ #define MXC_F_FLC_CTRL_LVE_POS                         25 /**< CTRL_LVE Position */
+ #define MXC_F_FLC_CTRL_LVE                             ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
+
+ #define MXC_F_FLC_CTRL_UNLOCK_POS                      28 /**< CTRL_UNLOCK Position */
+ #define MXC_F_FLC_CTRL_UNLOCK                          ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
+ #define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED                 ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
+ #define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED                 (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
+ #define MXC_V_FLC_CTRL_UNLOCK_LOCKED                   ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
+ #define MXC_S_FLC_CTRL_UNLOCK_LOCKED                   (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
+
+/**@} end of group FLC_CTRL_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_INTR FLC_INTR
+ * @brief    Flash Interrupt Register.
+ * @{
+ */
+ #define MXC_F_FLC_INTR_DONE_POS                        0 /**< INTR_DONE Position */
+ #define MXC_F_FLC_INTR_DONE                            ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
+
+ #define MXC_F_FLC_INTR_AF_POS                          1 /**< INTR_AF Position */
+ #define MXC_F_FLC_INTR_AF                              ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
+
+ #define MXC_F_FLC_INTR_DONEIE_POS                      8 /**< INTR_DONEIE Position */
+ #define MXC_F_FLC_INTR_DONEIE                          ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
+
+ #define MXC_F_FLC_INTR_AFIE_POS                        9 /**< INTR_AFIE Position */
+ #define MXC_F_FLC_INTR_AFIE                            ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
+
+/**@} end of group FLC_INTR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_ECCDATA FLC_ECCDATA
+ * @brief    ECC Data Register.
+ * @{
+ */
+ #define MXC_F_FLC_ECCDATA_EVEN_POS                     0 /**< ECCDATA_EVEN Position */
+ #define MXC_F_FLC_ECCDATA_EVEN                         ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
+
+ #define MXC_F_FLC_ECCDATA_ODD_POS                      16 /**< ECCDATA_ODD Position */
+ #define MXC_F_FLC_ECCDATA_ODD                          ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
+
+/**@} end of group FLC_ECCDATA_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_DATA FLC_DATA
+ * @brief    Flash Write Data.
+ * @{
+ */
+ #define MXC_F_FLC_DATA_DATA_POS                        0 /**< DATA_DATA Position */
+ #define MXC_F_FLC_DATA_DATA                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group FLC_DATA_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_ACTRL FLC_ACTRL
+ * @brief    Access Control Register. Writing the ACTRL register with the following values in
+ *           the order shown, allows read and write access to the system and user Information
+ *           block:     pflc-actrl = 0x3a7f5ca3;     pflc-actrl = 0xa1e34f20;     pflc-actrl
+ *           = 0x9608b2c1. When unlocked, a write of any word will disable access to system
+ *           and user information block. Readback of this register is always zero.
+ * @{
+ */
+ #define MXC_F_FLC_ACTRL_ACTRL_POS                      0 /**< ACTRL_ACTRL Position */
+ #define MXC_F_FLC_ACTRL_ACTRL                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
+
+/**@} end of group FLC_ACTRL_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_WELR0 FLC_WELR0
+ * @brief    WELR0
+ * @{
+ */
+ #define MXC_F_FLC_WELR0_WELR0_POS                      0 /**< WELR0_WELR0 Position */
+ #define MXC_F_FLC_WELR0_WELR0                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */
+
+/**@} end of group FLC_WELR0_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_WELR1 FLC_WELR1
+ * @brief    WELR1
+ * @{
+ */
+ #define MXC_F_FLC_WELR1_WELR1_POS                      0 /**< WELR1_WELR1 Position */
+ #define MXC_F_FLC_WELR1_WELR1                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */
+
+/**@} end of group FLC_WELR1_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_RLR0 FLC_RLR0
+ * @brief    RLR0
+ * @{
+ */
+ #define MXC_F_FLC_RLR0_RLR0_POS                        0 /**< RLR0_RLR0 Position */
+ #define MXC_F_FLC_RLR0_RLR0                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */
+
+/**@} end of group FLC_RLR0_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_RLR1 FLC_RLR1
+ * @brief    RLR1
+ * @{
+ */
+ #define MXC_F_FLC_RLR1_RLR1_POS                        0 /**< RLR1_RLR1 Position */
+ #define MXC_F_FLC_RLR1_RLR1                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */
+
+/**@} end of group FLC_RLR1_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcfr_regs.h

@@ -0,0 +1,189 @@
+/**
+ * @file    gcfr_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _GCFR_REGS_H_
+#define _GCFR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gcfr
+ * @defgroup    gcfr_registers GCFR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module.
+ * @details Global Control Function Register.
+ */
+
+/**
+ * @ingroup gcfr_registers
+ * Structure type to access the GCFR Registers.
+ */
+typedef struct {
+    __IO uint32_t reg0;                 /**< <tt>\b 0x00:</tt> GCFR REG0 Register */
+    __IO uint32_t reg1;                 /**< <tt>\b 0x04:</tt> GCFR REG1 Register */
+    __IO uint32_t reg2;                 /**< <tt>\b 0x08:</tt> GCFR REG2 Register */
+    __IO uint32_t reg3;                 /**< <tt>\b 0x0C:</tt> GCFR REG3 Register */
+} mxc_gcfr_regs_t;
+
+/* Register offsets for module GCFR */
+/**
+ * @ingroup    gcfr_registers
+ * @defgroup   GCFR_Register_Offsets Register Offsets
+ * @brief      GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_GCFR_REG0                    ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_GCFR_REG1                    ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_GCFR_REG2                    ((uint32_t)0x00000008UL) /**< Offset from GCFR Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_GCFR_REG3                    ((uint32_t)0x0000000CUL) /**< Offset from GCFR Base Address: <tt> 0x000C</tt> */ 
+/**@} end of group gcfr_registers */
+
+/**
+ * @ingroup  gcfr_registers
+ * @defgroup GCFR_REG0 GCFR_REG0
+ * @brief    Register 0.
+ * @{
+ */
+ #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS            0 /**< REG0_CNNX16_0_PWR_EN Position */
+ #define MXC_F_GCFR_REG0_CNNX16_0_PWR_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_0_PWR_EN_POS)) /**< REG0_CNNX16_0_PWR_EN Mask */
+
+ #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS            1 /**< REG0_CNNX16_1_PWR_EN Position */
+ #define MXC_F_GCFR_REG0_CNNX16_1_PWR_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_1_PWR_EN_POS)) /**< REG0_CNNX16_1_PWR_EN Mask */
+
+ #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS            2 /**< REG0_CNNX16_2_PWR_EN Position */
+ #define MXC_F_GCFR_REG0_CNNX16_2_PWR_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_2_PWR_EN_POS)) /**< REG0_CNNX16_2_PWR_EN Mask */
+
+ #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS            3 /**< REG0_CNNX16_3_PWR_EN Position */
+ #define MXC_F_GCFR_REG0_CNNX16_3_PWR_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG0_CNNX16_3_PWR_EN_POS)) /**< REG0_CNNX16_3_PWR_EN Mask */
+
+/**@} end of group GCFR_REG0_Register */
+
+/**
+ * @ingroup  gcfr_registers
+ * @defgroup GCFR_REG1 GCFR_REG1
+ * @brief    Register 1.
+ * @{
+ */
+ #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS            0 /**< REG1_CNNX16_0_RAM_EN Position */
+ #define MXC_F_GCFR_REG1_CNNX16_0_RAM_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_0_RAM_EN_POS)) /**< REG1_CNNX16_0_RAM_EN Mask */
+
+ #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS            1 /**< REG1_CNNX16_1_RAM_EN Position */
+ #define MXC_F_GCFR_REG1_CNNX16_1_RAM_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_1_RAM_EN_POS)) /**< REG1_CNNX16_1_RAM_EN Mask */
+
+ #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS            2 /**< REG1_CNNX16_2_RAM_EN Position */
+ #define MXC_F_GCFR_REG1_CNNX16_2_RAM_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_2_RAM_EN_POS)) /**< REG1_CNNX16_2_RAM_EN Mask */
+
+ #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS            3 /**< REG1_CNNX16_3_RAM_EN Position */
+ #define MXC_F_GCFR_REG1_CNNX16_3_RAM_EN                ((uint32_t)(0x1UL << MXC_F_GCFR_REG1_CNNX16_3_RAM_EN_POS)) /**< REG1_CNNX16_3_RAM_EN Mask */
+
+/**@} end of group GCFR_REG1_Register */
+
+/**
+ * @ingroup  gcfr_registers
+ * @defgroup GCFR_REG2 GCFR_REG2
+ * @brief    Register 2.
+ * @{
+ */
+ #define MXC_F_GCFR_REG2_CNNX16_0_ISO_POS               0 /**< REG2_CNNX16_0_ISO Position */
+ #define MXC_F_GCFR_REG2_CNNX16_0_ISO                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_0_ISO_POS)) /**< REG2_CNNX16_0_ISO Mask */
+
+ #define MXC_F_GCFR_REG2_CNNX16_1_ISO_POS               1 /**< REG2_CNNX16_1_ISO Position */
+ #define MXC_F_GCFR_REG2_CNNX16_1_ISO                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_1_ISO_POS)) /**< REG2_CNNX16_1_ISO Mask */
+
+ #define MXC_F_GCFR_REG2_CNNX16_2_ISO_POS               2 /**< REG2_CNNX16_2_ISO Position */
+ #define MXC_F_GCFR_REG2_CNNX16_2_ISO                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_2_ISO_POS)) /**< REG2_CNNX16_2_ISO Mask */
+
+ #define MXC_F_GCFR_REG2_CNNX16_3_ISO_POS               3 /**< REG2_CNNX16_3_ISO Position */
+ #define MXC_F_GCFR_REG2_CNNX16_3_ISO                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG2_CNNX16_3_ISO_POS)) /**< REG2_CNNX16_3_ISO Mask */
+
+/**@} end of group GCFR_REG2_Register */
+
+/**
+ * @ingroup  gcfr_registers
+ * @defgroup GCFR_REG3 GCFR_REG3
+ * @brief    Register 3.
+ * @{
+ */
+ #define MXC_F_GCFR_REG3_CNNX16_0_RST_POS               0 /**< REG3_CNNX16_0_RST Position */
+ #define MXC_F_GCFR_REG3_CNNX16_0_RST                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_0_RST_POS)) /**< REG3_CNNX16_0_RST Mask */
+
+ #define MXC_F_GCFR_REG3_CNNX16_1_RST_POS               1 /**< REG3_CNNX16_1_RST Position */
+ #define MXC_F_GCFR_REG3_CNNX16_1_RST                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_1_RST_POS)) /**< REG3_CNNX16_1_RST Mask */
+
+ #define MXC_F_GCFR_REG3_CNNX16_2_RST_POS               2 /**< REG3_CNNX16_2_RST Position */
+ #define MXC_F_GCFR_REG3_CNNX16_2_RST                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_2_RST_POS)) /**< REG3_CNNX16_2_RST Mask */
+
+ #define MXC_F_GCFR_REG3_CNNX16_3_RST_POS               3 /**< REG3_CNNX16_3_RST Position */
+ #define MXC_F_GCFR_REG3_CNNX16_3_RST                   ((uint32_t)(0x1UL << MXC_F_GCFR_REG3_CNNX16_3_RST_POS)) /**< REG3_CNNX16_3_RST Mask */
+
+/**@} end of group GCFR_REG3_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GCFR_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h

@@ -0,0 +1,690 @@
+/**
+ * @file    gcr_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _GCR_REGS_H_
+#define _GCR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gcr
+ * @defgroup    gcr_registers GCR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ * @details Global Control Registers.
+ */
+
+/**
+ * @ingroup gcr_registers
+ * Structure type to access the GCR Registers.
+ */
+typedef struct {
+    __IO uint32_t sysctrl;              /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */
+    __IO uint32_t rst0;                 /**< <tt>\b 0x04:</tt> GCR RST0 Register */
+    __IO uint32_t clkctrl;              /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */
+    __IO uint32_t pm;                   /**< <tt>\b 0x0C:</tt> GCR PM Register */
+    __I  uint32_t rsv_0x10_0x17[2];
+    __IO uint32_t pclkdiv;              /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */
+    __I  uint32_t rsv_0x1c_0x23[2];
+    __IO uint32_t pclkdis0;             /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */
+    __IO uint32_t memctrl;              /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */
+    __IO uint32_t memz;                 /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */
+    __I  uint32_t rsv_0x30_0x3f[4];
+    __IO uint32_t sysst;                /**< <tt>\b 0x40:</tt> GCR SYSST Register */
+    __IO uint32_t rst1;                 /**< <tt>\b 0x44:</tt> GCR RST1 Register */
+    __IO uint32_t pclkdis1;             /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */
+    __IO uint32_t eventen;              /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */
+    __I  uint32_t revision;             /**< <tt>\b 0x50:</tt> GCR REVISION Register */
+    __IO uint32_t sysie;                /**< <tt>\b 0x54:</tt> GCR SYSIE Register */
+    __I  uint32_t rsv_0x58_0x63[3];
+    __IO uint32_t eccerr;               /**< <tt>\b 0x64:</tt> GCR ECCERR Register */
+    __IO uint32_t eccced;               /**< <tt>\b 0x68:</tt> GCR ECCCED Register */
+    __IO uint32_t eccie;                /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */
+    __IO uint32_t eccaddr;              /**< <tt>\b 0x70:</tt> GCR ECCADDR Register */
+} mxc_gcr_regs_t;
+
+/* Register offsets for module GCR */
+/**
+ * @ingroup    gcr_registers
+ * @defgroup   GCR_Register_Offsets Register Offsets
+ * @brief      GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_GCR_SYSCTRL                  ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_GCR_RST0                     ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_GCR_CLKCTRL                  ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_GCR_PM                       ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_GCR_PCLKDIV                  ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_GCR_PCLKDIS0                 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_GCR_MEMCTRL                  ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_GCR_MEMZ                     ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_GCR_SYSST                    ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_GCR_RST1                     ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 
+ #define MXC_R_GCR_PCLKDIS1                 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 
+ #define MXC_R_GCR_EVENTEN                  ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 
+ #define MXC_R_GCR_REVISION                 ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 
+ #define MXC_R_GCR_SYSIE                    ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 
+ #define MXC_R_GCR_ECCERR                   ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 
+ #define MXC_R_GCR_ECCCED                   ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 
+ #define MXC_R_GCR_ECCIE                    ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 
+ #define MXC_R_GCR_ECCADDR                  ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 
+/**@} end of group gcr_registers */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSCTRL GCR_SYSCTRL
+ * @brief    System Control.
+ * @{
+ */
+ #define MXC_F_GCR_SYSCTRL_SBUSARB_POS                  1 /**< SYSCTRL_SBUSARB Position */
+ #define MXC_F_GCR_SYSCTRL_SBUSARB                      ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */
+ #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX                  ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */
+ #define MXC_S_GCR_SYSCTRL_SBUSARB_FIX                  (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */
+ #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND                ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */
+ #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND                (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */
+
+ #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS                  5 /**< SYSCTRL_FPU_DIS Position */
+ #define MXC_F_GCR_SYSCTRL_FPU_DIS                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */
+
+ #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS               6 /**< SYSCTRL_ICC0_FLUSH Position */
+ #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH                   ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */
+
+ #define MXC_F_GCR_SYSCTRL_ROMDONE_POS                  12 /**< SYSCTRL_ROMDONE Position */
+ #define MXC_F_GCR_SYSCTRL_ROMDONE                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */
+
+ #define MXC_F_GCR_SYSCTRL_CCHK_POS                     13 /**< SYSCTRL_CCHK Position */
+ #define MXC_F_GCR_SYSCTRL_CCHK                         ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */
+
+ #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS                  14 /**< SYSCTRL_SWD_DIS Position */
+ #define MXC_F_GCR_SYSCTRL_SWD_DIS                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */
+
+ #define MXC_F_GCR_SYSCTRL_CHKRES_POS                   15 /**< SYSCTRL_CHKRES Position */
+ #define MXC_F_GCR_SYSCTRL_CHKRES                       ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */
+
+/**@} end of group GCR_SYSCTRL_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RST0 GCR_RST0
+ * @brief    Reset.
+ * @{
+ */
+ #define MXC_F_GCR_RST0_DMA_POS                         0 /**< RST0_DMA Position */
+ #define MXC_F_GCR_RST0_DMA                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */
+
+ #define MXC_F_GCR_RST0_WDT0_POS                        1 /**< RST0_WDT0 Position */
+ #define MXC_F_GCR_RST0_WDT0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */
+
+ #define MXC_F_GCR_RST0_GPIO0_POS                       2 /**< RST0_GPIO0 Position */
+ #define MXC_F_GCR_RST0_GPIO0                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */
+
+ #define MXC_F_GCR_RST0_GPIO1_POS                       3 /**< RST0_GPIO1 Position */
+ #define MXC_F_GCR_RST0_GPIO1                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */
+
+ #define MXC_F_GCR_RST0_TMR0_POS                        5 /**< RST0_TMR0 Position */
+ #define MXC_F_GCR_RST0_TMR0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */
+
+ #define MXC_F_GCR_RST0_TMR1_POS                        6 /**< RST0_TMR1 Position */
+ #define MXC_F_GCR_RST0_TMR1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */
+
+ #define MXC_F_GCR_RST0_TMR2_POS                        7 /**< RST0_TMR2 Position */
+ #define MXC_F_GCR_RST0_TMR2                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */
+
+ #define MXC_F_GCR_RST0_TMR3_POS                        8 /**< RST0_TMR3 Position */
+ #define MXC_F_GCR_RST0_TMR3                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */
+
+ #define MXC_F_GCR_RST0_UART0_POS                       11 /**< RST0_UART0 Position */
+ #define MXC_F_GCR_RST0_UART0                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */
+
+ #define MXC_F_GCR_RST0_UART1_POS                       12 /**< RST0_UART1 Position */
+ #define MXC_F_GCR_RST0_UART1                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */
+
+ #define MXC_F_GCR_RST0_SPI0_POS                        13 /**< RST0_SPI0 Position */
+ #define MXC_F_GCR_RST0_SPI0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */
+
+ #define MXC_F_GCR_RST0_SPI1_POS                        14 /**< RST0_SPI1 Position */
+ #define MXC_F_GCR_RST0_SPI1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */
+
+ #define MXC_F_GCR_RST0_SPI2_POS                        15 /**< RST0_SPI2 Position */
+ #define MXC_F_GCR_RST0_SPI2                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */
+
+ #define MXC_F_GCR_RST0_I2C0_POS                        16 /**< RST0_I2C0 Position */
+ #define MXC_F_GCR_RST0_I2C0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */
+
+ #define MXC_F_GCR_RST0_RTC_POS                         17 /**< RST0_RTC Position */
+ #define MXC_F_GCR_RST0_RTC                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */
+
+ #define MXC_F_GCR_RST0_TRNG_POS                        24 /**< RST0_TRNG Position */
+ #define MXC_F_GCR_RST0_TRNG                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */
+
+ #define MXC_F_GCR_RST0_UART2_POS                       28 /**< RST0_UART2 Position */
+ #define MXC_F_GCR_RST0_UART2                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */
+
+ #define MXC_F_GCR_RST0_SOFT_POS                        29 /**< RST0_SOFT Position */
+ #define MXC_F_GCR_RST0_SOFT                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */
+
+ #define MXC_F_GCR_RST0_PERIPH_POS                      30 /**< RST0_PERIPH Position */
+ #define MXC_F_GCR_RST0_PERIPH                          ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */
+
+ #define MXC_F_GCR_RST0_SYS_POS                         31 /**< RST0_SYS Position */
+ #define MXC_F_GCR_RST0_SYS                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */
+
+/**@} end of group GCR_RST0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_CLKCTRL GCR_CLKCTRL
+ * @brief    Clock Control.
+ * @{
+ */
+ #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS               6 /**< CLKCTRL_SYSCLK_DIV Position */
+ #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV                   ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1              ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2              ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4              ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8              ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16             ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16             (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32             ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32             (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64             ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64             (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128            ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128            (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */
+
+ #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS               9 /**< CLKCTRL_SYSCLK_SEL Position */
+ #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL                   ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO              ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO              (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO              ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO              (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO               ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO               (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO              ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO              (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO             ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO             (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */
+ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK            ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */
+ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK            (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */
+
+ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS               13 /**< CLKCTRL_SYSCLK_RDY Position */
+ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY                   ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */
+
+ #define MXC_F_GCR_CLKCTRL_IPO_DIV_POS                  14 /**< CLKCTRL_IPO_DIV Position */
+ #define MXC_F_GCR_CLKCTRL_IPO_DIV                      ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */
+ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1                 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */
+ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1                 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */
+ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2                 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */
+ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2                 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */
+ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4                 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */
+ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4                 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */
+ #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8                 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */
+ #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8                 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */
+
+ #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS                  16 /**< CLKCTRL_ERFO_EN Position */
+ #define MXC_F_GCR_CLKCTRL_ERFO_EN                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */
+
+ #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS                 17 /**< CLKCTRL_ERTCO_EN Position */
+ #define MXC_F_GCR_CLKCTRL_ERTCO_EN                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */
+
+ #define MXC_F_GCR_CLKCTRL_IPO_EN_POS                   19 /**< CLKCTRL_IPO_EN Position */
+ #define MXC_F_GCR_CLKCTRL_IPO_EN                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */
+
+ #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS                  20 /**< CLKCTRL_IBRO_EN Position */
+ #define MXC_F_GCR_CLKCTRL_IBRO_EN                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */
+
+ #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS                  21 /**< CLKCTRL_IBRO_VS Position */
+ #define MXC_F_GCR_CLKCTRL_IBRO_VS                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */
+
+ #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS                 24 /**< CLKCTRL_ERFO_RDY Position */
+ #define MXC_F_GCR_CLKCTRL_ERFO_RDY                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */
+
+ #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS                25 /**< CLKCTRL_ERTCO_RDY Position */
+ #define MXC_F_GCR_CLKCTRL_ERTCO_RDY                    ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */
+
+ #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS                  27 /**< CLKCTRL_IPO_RDY Position */
+ #define MXC_F_GCR_CLKCTRL_IPO_RDY                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */
+
+ #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS                 28 /**< CLKCTRL_IBRO_RDY Position */
+ #define MXC_F_GCR_CLKCTRL_IBRO_RDY                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */
+
+ #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS                 29 /**< CLKCTRL_INRO_RDY Position */
+ #define MXC_F_GCR_CLKCTRL_INRO_RDY                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */
+
+ #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS               31 /**< CLKCTRL_EXTCLK_RDY Position */
+ #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY                   ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS)) /**< CLKCTRL_EXTCLK_RDY Mask */
+
+/**@} end of group GCR_CLKCTRL_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PM GCR_PM
+ * @brief    Power Management.
+ * @{
+ */
+ #define MXC_F_GCR_PM_MODE_POS                          0 /**< PM_MODE Position */
+ #define MXC_F_GCR_PM_MODE                              ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
+ #define MXC_V_GCR_PM_MODE_ACTIVE                       ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
+ #define MXC_S_GCR_PM_MODE_ACTIVE                       (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
+ #define MXC_V_GCR_PM_MODE_SHUTDOWN                     ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
+ #define MXC_S_GCR_PM_MODE_SHUTDOWN                     (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
+ #define MXC_V_GCR_PM_MODE_BACKUP                       ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
+ #define MXC_S_GCR_PM_MODE_BACKUP                       (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
+
+ #define MXC_F_GCR_PM_GPIO_WE_POS                       4 /**< PM_GPIO_WE Position */
+ #define MXC_F_GCR_PM_GPIO_WE                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */
+
+ #define MXC_F_GCR_PM_RTC_WE_POS                        5 /**< PM_RTC_WE Position */
+ #define MXC_F_GCR_PM_RTC_WE                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */
+
+ #define MXC_F_GCR_PM_LPTMR0_WE_POS                     6 /**< PM_LPTMR0_WE Position */
+ #define MXC_F_GCR_PM_LPTMR0_WE                         ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS)) /**< PM_LPTMR0_WE Mask */
+
+ #define MXC_F_GCR_PM_LPTMR1_WE_POS                     7 /**< PM_LPTMR1_WE Position */
+ #define MXC_F_GCR_PM_LPTMR1_WE                         ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS)) /**< PM_LPTMR1_WE Mask */
+
+ #define MXC_F_GCR_PM_LPUART0_WE_POS                    8 /**< PM_LPUART0_WE Position */
+ #define MXC_F_GCR_PM_LPUART0_WE                        ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */
+
+ #define MXC_F_GCR_PM_ERFO_PD_POS                       14 /**< PM_ERFO_PD Position */
+ #define MXC_F_GCR_PM_ERFO_PD                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */
+
+ #define MXC_F_GCR_PM_IPO_PD_POS                        16 /**< PM_IPO_PD Position */
+ #define MXC_F_GCR_PM_IPO_PD                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */
+
+ #define MXC_F_GCR_PM_IBRO_PD_POS                       17 /**< PM_IBRO_PD Position */
+ #define MXC_F_GCR_PM_IBRO_PD                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */
+
+ #define MXC_F_GCR_PM_ERFO_BP_POS                       20 /**< PM_ERFO_BP Position */
+ #define MXC_F_GCR_PM_ERFO_BP                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */
+
+/**@} end of group GCR_PM_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PCLKDIV GCR_PCLKDIV
+ * @brief    Peripheral Clock Divider.
+ * @{
+ */
+ #define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS               0 /**< PCLKDIV_AON_CLKDIV Position */
+ #define MXC_F_GCR_PCLKDIV_AON_CLKDIV                   ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */
+ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4              ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV4 Value */
+ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4              (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV4 Setting */
+ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8              ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV8 Value */
+ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8              (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV8 Setting */
+ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16             ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV16 Value */
+ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16             (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV16 Setting */
+ #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32             ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV32 Value */
+ #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32             (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV32 Setting */
+
+ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS         14 /**< PCLKDIV_DIV_CLK_OUT_CTRL Position */
+ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL             ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS)) /**< PCLKDIV_DIV_CLK_OUT_CTRL Mask */
+
+ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS           16 /**< PCLKDIV_DIV_CLK_OUT_EN Position */
+ #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN               ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS)) /**< PCLKDIV_DIV_CLK_OUT_EN Mask */
+
+/**@} end of group GCR_PCLKDIV_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+ #define MXC_F_GCR_PCLKDIS0_GPIO0_POS                   0 /**< PCLKDIS0_GPIO0 Position */
+ #define MXC_F_GCR_PCLKDIS0_GPIO0                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_GPIO1_POS                   1 /**< PCLKDIS0_GPIO1 Position */
+ #define MXC_F_GCR_PCLKDIS0_GPIO1                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_DMA_POS                     5 /**< PCLKDIS0_DMA Position */
+ #define MXC_F_GCR_PCLKDIS0_DMA                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_SPI0_POS                    6 /**< PCLKDIS0_SPI0 Position */
+ #define MXC_F_GCR_PCLKDIS0_SPI0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_SPI1_POS                    7 /**< PCLKDIS0_SPI1 Position */
+ #define MXC_F_GCR_PCLKDIS0_SPI1                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_SPI2_POS                    8 /**< PCLKDIS0_SPI2 Position */
+ #define MXC_F_GCR_PCLKDIS0_SPI2                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_UART0_POS                   9 /**< PCLKDIS0_UART0 Position */
+ #define MXC_F_GCR_PCLKDIS0_UART0                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_UART1_POS                   10 /**< PCLKDIS0_UART1 Position */
+ #define MXC_F_GCR_PCLKDIS0_UART1                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_I2C0_POS                    13 /**< PCLKDIS0_I2C0 Position */
+ #define MXC_F_GCR_PCLKDIS0_I2C0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_TMR0_POS                    15 /**< PCLKDIS0_TMR0 Position */
+ #define MXC_F_GCR_PCLKDIS0_TMR0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_TMR1_POS                    16 /**< PCLKDIS0_TMR1 Position */
+ #define MXC_F_GCR_PCLKDIS0_TMR1                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_TMR2_POS                    17 /**< PCLKDIS0_TMR2 Position */
+ #define MXC_F_GCR_PCLKDIS0_TMR2                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_TMR3_POS                    18 /**< PCLKDIS0_TMR3 Position */
+ #define MXC_F_GCR_PCLKDIS0_TMR3                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */
+
+ #define MXC_F_GCR_PCLKDIS0_I2C1_POS                    28 /**< PCLKDIS0_I2C1 Position */
+ #define MXC_F_GCR_PCLKDIS0_I2C1                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */
+
+/**@} end of group GCR_PCLKDIS0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMCTRL GCR_MEMCTRL
+ * @brief    Memory Clock Control Register.
+ * @{
+ */
+ #define MXC_F_GCR_MEMCTRL_FWS_POS                      0 /**< MEMCTRL_FWS Position */
+ #define MXC_F_GCR_MEMCTRL_FWS                          ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */
+
+ #define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS                 4 /**< MEMCTRL_RAMWS_EN Position */
+ #define MXC_F_GCR_MEMCTRL_RAMWS_EN                     ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */
+
+ #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS                8 /**< MEMCTRL_RAM0LS_EN Position */
+ #define MXC_F_GCR_MEMCTRL_RAM0LS_EN                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */
+
+ #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS                9 /**< MEMCTRL_RAM1LS_EN Position */
+ #define MXC_F_GCR_MEMCTRL_RAM1LS_EN                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */
+
+ #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS                10 /**< MEMCTRL_RAM2LS_EN Position */
+ #define MXC_F_GCR_MEMCTRL_RAM2LS_EN                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */
+
+ #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS                11 /**< MEMCTRL_RAM3LS_EN Position */
+ #define MXC_F_GCR_MEMCTRL_RAM3LS_EN                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */
+
+ #define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS                12 /**< MEMCTRL_ICC0LS_EN Position */
+ #define MXC_F_GCR_MEMCTRL_ICC0LS_EN                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */
+
+ #define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS                 13 /**< MEMCTRL_ROMLS_EN Position */
+ #define MXC_F_GCR_MEMCTRL_ROMLS_EN                     ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */
+
+/**@} end of group GCR_MEMCTRL_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMZ GCR_MEMZ
+ * @brief    Memory Zeroize Control.
+ * @{
+ */
+ #define MXC_F_GCR_MEMZ_RAM_POS                         0 /**< MEMZ_RAM Position */
+ #define MXC_F_GCR_MEMZ_RAM                             ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM_POS)) /**< MEMZ_RAM Mask */
+
+ #define MXC_F_GCR_MEMZ_RAMCB_POS                       1 /**< MEMZ_RAMCB Position */
+ #define MXC_F_GCR_MEMZ_RAMCB                           ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS)) /**< MEMZ_RAMCB Mask */
+
+ #define MXC_F_GCR_MEMZ_ICC0_POS                        2 /**< MEMZ_ICC0 Position */
+ #define MXC_F_GCR_MEMZ_ICC0                            ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */
+
+/**@} end of group GCR_MEMZ_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSST GCR_SYSST
+ * @brief    System Status Register.
+ * @{
+ */
+ #define MXC_F_GCR_SYSST_ICELOCK_POS                    0 /**< SYSST_ICELOCK Position */
+ #define MXC_F_GCR_SYSST_ICELOCK                        ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */
+
+/**@} end of group GCR_SYSST_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RST1 GCR_RST1
+ * @brief    Reset 1.
+ * @{
+ */
+ #define MXC_F_GCR_RST1_I2C1_POS                        0 /**< RST1_I2C1 Position */
+ #define MXC_F_GCR_RST1_I2C1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */
+
+ #define MXC_F_GCR_RST1_WDT1_POS                        8 /**< RST1_WDT1 Position */
+ #define MXC_F_GCR_RST1_WDT1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */
+
+ #define MXC_F_GCR_RST1_CRC_POS                         9 /**< RST1_CRC Position */
+ #define MXC_F_GCR_RST1_CRC                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */
+
+ #define MXC_F_GCR_RST1_AES_POS                         10 /**< RST1_AES Position */
+ #define MXC_F_GCR_RST1_AES                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */
+
+ #define MXC_F_GCR_RST1_AC_POS                          14 /**< RST1_AC Position */
+ #define MXC_F_GCR_RST1_AC                              ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */
+
+ #define MXC_F_GCR_RST1_I2C2_POS                        17 /**< RST1_I2C2 Position */
+ #define MXC_F_GCR_RST1_I2C2                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */
+
+ #define MXC_F_GCR_RST1_I2S_POS                         23 /**< RST1_I2S Position */
+ #define MXC_F_GCR_RST1_I2S                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */
+
+/**@} end of group GCR_RST1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+ #define MXC_F_GCR_PCLKDIS1_UART2_POS                   1 /**< PCLKDIS1_UART2 Position */
+ #define MXC_F_GCR_PCLKDIS1_UART2                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_TRNG_POS                    2 /**< PCLKDIS1_TRNG Position */
+ #define MXC_F_GCR_PCLKDIS1_TRNG                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_WWDT0_POS                   4 /**< PCLKDIS1_WWDT0 Position */
+ #define MXC_F_GCR_PCLKDIS1_WWDT0                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS)) /**< PCLKDIS1_WWDT0 Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_WWDT1_POS                   5 /**< PCLKDIS1_WWDT1 Position */
+ #define MXC_F_GCR_PCLKDIS1_WWDT1                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS)) /**< PCLKDIS1_WWDT1 Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_ICC0_POS                    11 /**< PCLKDIS1_ICC0 Position */
+ #define MXC_F_GCR_PCLKDIS1_ICC0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_CRC_POS                     14 /**< PCLKDIS1_CRC Position */
+ #define MXC_F_GCR_PCLKDIS1_CRC                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_AES_POS                     15 /**< PCLKDIS1_AES Position */
+ #define MXC_F_GCR_PCLKDIS1_AES                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_I2C2_POS                    21 /**< PCLKDIS1_I2C2 Position */
+ #define MXC_F_GCR_PCLKDIS1_I2C2                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */
+
+ #define MXC_F_GCR_PCLKDIS1_I2S_POS                     23 /**< PCLKDIS1_I2S Position */
+ #define MXC_F_GCR_PCLKDIS1_I2S                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */
+
+/**@} end of group GCR_PCLKDIS1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_EVENTEN GCR_EVENTEN
+ * @brief    Event Enable Register.
+ * @{
+ */
+ #define MXC_F_GCR_EVENTEN_DMA_POS                      0 /**< EVENTEN_DMA Position */
+ #define MXC_F_GCR_EVENTEN_DMA                          ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */
+
+ #define MXC_F_GCR_EVENTEN_RX_POS                       1 /**< EVENTEN_RX Position */
+ #define MXC_F_GCR_EVENTEN_RX                           ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */
+
+ #define MXC_F_GCR_EVENTEN_TX_POS                       2 /**< EVENTEN_TX Position */
+ #define MXC_F_GCR_EVENTEN_TX                           ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */
+
+/**@} end of group GCR_EVENTEN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_REVISION GCR_REVISION
+ * @brief    Revision Register.
+ * @{
+ */
+ #define MXC_F_GCR_REVISION_REVISION_POS                0 /**< REVISION_REVISION Position */
+ #define MXC_F_GCR_REVISION_REVISION                    ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */
+
+/**@} end of group GCR_REVISION_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSIE GCR_SYSIE
+ * @brief    System Status Interrupt Enable Register.
+ * @{
+ */
+ #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS                  0 /**< SYSIE_ICEUNLOCK Position */
+ #define MXC_F_GCR_SYSIE_ICEUNLOCK                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */
+
+/**@} end of group GCR_SYSIE_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCERR GCR_ECCERR
+ * @brief    ECC Error Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCERR_RAM_POS                       0 /**< ECCERR_RAM Position */
+ #define MXC_F_GCR_ECCERR_RAM                           ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */
+
+ #define MXC_F_GCR_ECCERR_ICC0_POS                      1 /**< ECCERR_ICC0 Position */
+ #define MXC_F_GCR_ECCERR_ICC0                          ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */
+
+ #define MXC_F_GCR_ECCERR_FLASH_POS                     2 /**< ECCERR_FLASH Position */
+ #define MXC_F_GCR_ECCERR_FLASH                         ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */
+
+/**@} end of group GCR_ECCERR_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCCED GCR_ECCCED
+ * @brief    ECC Not Double Error Detect Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCCED_RAM_POS                       0 /**< ECCCED_RAM Position */
+ #define MXC_F_GCR_ECCCED_RAM                           ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */
+
+ #define MXC_F_GCR_ECCCED_ICC0_POS                      1 /**< ECCCED_ICC0 Position */
+ #define MXC_F_GCR_ECCCED_ICC0                          ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */
+
+ #define MXC_F_GCR_ECCCED_FLASH_POS                     2 /**< ECCCED_FLASH Position */
+ #define MXC_F_GCR_ECCCED_FLASH                         ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */
+
+/**@} end of group GCR_ECCCED_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCIE GCR_ECCIE
+ * @brief    ECC IRQ Enable Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCIE_RAM_POS                        0 /**< ECCIE_RAM Position */
+ #define MXC_F_GCR_ECCIE_RAM                            ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */
+
+ #define MXC_F_GCR_ECCIE_ICC0_POS                       1 /**< ECCIE_ICC0 Position */
+ #define MXC_F_GCR_ECCIE_ICC0                           ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */
+
+ #define MXC_F_GCR_ECCIE_FLASH_POS                      2 /**< ECCIE_FLASH Position */
+ #define MXC_F_GCR_ECCIE_FLASH                          ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH_POS)) /**< ECCIE_FLASH Mask */
+
+/**@} end of group GCR_ECCIE_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_ECCADDR GCR_ECCADDR
+ * @brief    ECC Error Address Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCADDR_DATARAMADDR_POS              0 /**< ECCADDR_DATARAMADDR Position */
+ #define MXC_F_GCR_ECCADDR_DATARAMADDR                  ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */
+
+ #define MXC_F_GCR_ECCADDR_DATARAMBANK_POS              14 /**< ECCADDR_DATARAMBANK Position */
+ #define MXC_F_GCR_ECCADDR_DATARAMBANK                  ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */
+
+ #define MXC_F_GCR_ECCADDR_DATARAMERR_POS               15 /**< ECCADDR_DATARAMERR Position */
+ #define MXC_F_GCR_ECCADDR_DATARAMERR                   ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */
+
+ #define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS               16 /**< ECCADDR_TAGRAMADDR Position */
+ #define MXC_F_GCR_ECCADDR_TAGRAMADDR                   ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */
+
+ #define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS               30 /**< ECCADDR_TAGRAMBANK Position */
+ #define MXC_F_GCR_ECCADDR_TAGRAMBANK                   ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */
+
+ #define MXC_F_GCR_ECCADDR_TAGRAMERR_POS                31 /**< ECCADDR_TAGRAMERR Position */
+ #define MXC_F_GCR_ECCADDR_TAGRAMERR                    ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */
+
+/**@} end of group GCR_ECCADDR_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GCR_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h

@@ -0,0 +1,673 @@
+/**
+ * @file    gpio_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gpio
+ * @defgroup    gpio_registers GPIO_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ * @details Individual I/O for each GPIO
+ */
+
+/**
+ * @ingroup gpio_registers
+ * Structure type to access the GPIO Registers.
+ */
+typedef struct {
+    __IO uint32_t en0;                  /**< <tt>\b 0x00:</tt> GPIO EN0 Register */
+    __IO uint32_t en0_set;              /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */
+    __IO uint32_t en0_clr;              /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */
+    __IO uint32_t outen;                /**< <tt>\b 0x0C:</tt> GPIO OUTEN Register */
+    __IO uint32_t outen_set;            /**< <tt>\b 0x10:</tt> GPIO OUTEN_SET Register */
+    __IO uint32_t outen_clr;            /**< <tt>\b 0x14:</tt> GPIO OUTEN_CLR Register */
+    __IO uint32_t out;                  /**< <tt>\b 0x18:</tt> GPIO OUT Register */
+    __O  uint32_t out_set;              /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
+    __O  uint32_t out_clr;              /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
+    __I  uint32_t in;                   /**< <tt>\b 0x24:</tt> GPIO IN Register */
+    __IO uint32_t intmode;              /**< <tt>\b 0x28:</tt> GPIO INTMODE Register */
+    __IO uint32_t intpol;               /**< <tt>\b 0x2C:</tt> GPIO INTPOL Register */
+    __IO uint32_t inen;                 /**< <tt>\b 0x30:</tt> GPIO INEN Register */
+    __IO uint32_t inten;                /**< <tt>\b 0x34:</tt> GPIO INTEN Register */
+    __IO uint32_t inten_set;            /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */
+    __IO uint32_t inten_clr;            /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */
+    __I  uint32_t intfl;                /**< <tt>\b 0x40:</tt> GPIO INTFL Register */
+    __I  uint32_t rsv_0x44;
+    __IO uint32_t intfl_clr;            /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */
+    __IO uint32_t wken;                 /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */
+    __IO uint32_t wken_set;             /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */
+    __IO uint32_t wken_clr;             /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */
+    __I  uint32_t rsv_0x58;
+    __IO uint32_t dualedge;             /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */
+    __IO uint32_t padctrl0;             /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */
+    __IO uint32_t padctrl1;             /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */
+    __IO uint32_t en1;                  /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
+    __IO uint32_t en1_set;              /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
+    __IO uint32_t en1_clr;              /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
+    __IO uint32_t en2;                  /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
+    __IO uint32_t en2_set;              /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
+    __IO uint32_t en2_clr;              /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
+    __I  uint32_t rsv_0x80_0xa7[10];
+    __IO uint32_t hysen;                /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */
+    __IO uint32_t srsel;                /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */
+    __IO uint32_t ds0;                  /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
+    __IO uint32_t ds1;                  /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
+    __IO uint32_t ps;                   /**< <tt>\b 0xB8:</tt> GPIO PS Register */
+} mxc_gpio_regs_t;
+
+/* Register offsets for module GPIO */
+/**
+ * @ingroup    gpio_registers
+ * @defgroup   GPIO_Register_Offsets Register Offsets
+ * @brief      GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_GPIO_EN0                     ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_GPIO_EN0_SET                 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_GPIO_EN0_CLR                 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_GPIO_OUTEN                   ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_GPIO_OUTEN_SET               ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_GPIO_OUTEN_CLR               ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_GPIO_OUT                     ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_GPIO_OUT_SET                 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_GPIO_OUT_CLR                 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_GPIO_IN                      ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_GPIO_INTMODE                 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_GPIO_INTPOL                  ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_GPIO_INEN                    ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_GPIO_INTEN                   ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_GPIO_INTEN_SET               ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 
+ #define MXC_R_GPIO_INTEN_CLR               ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 
+ #define MXC_R_GPIO_INTFL                   ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_GPIO_INTFL_CLR               ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 
+ #define MXC_R_GPIO_WKEN                    ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 
+ #define MXC_R_GPIO_WKEN_SET                ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 
+ #define MXC_R_GPIO_WKEN_CLR                ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 
+ #define MXC_R_GPIO_DUALEDGE                ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 
+ #define MXC_R_GPIO_PADCTRL0                ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 
+ #define MXC_R_GPIO_PADCTRL1                ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 
+ #define MXC_R_GPIO_EN1                     ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 
+ #define MXC_R_GPIO_EN1_SET                 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 
+ #define MXC_R_GPIO_EN1_CLR                 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 
+ #define MXC_R_GPIO_EN2                     ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 
+ #define MXC_R_GPIO_EN2_SET                 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 
+ #define MXC_R_GPIO_EN2_CLR                 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 
+ #define MXC_R_GPIO_HYSEN                   ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ 
+ #define MXC_R_GPIO_SRSEL                   ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ 
+ #define MXC_R_GPIO_DS0                     ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 
+ #define MXC_R_GPIO_DS1                     ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 
+ #define MXC_R_GPIO_PS                      ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 
+/**@} end of group gpio_registers */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN0 GPIO_EN0
+ * @brief    GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
+ *           GPIO pin on the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_EN0_GPIO_EN_POS                     0 /**< EN0_GPIO_EN Position */
+ #define MXC_F_GPIO_EN0_GPIO_EN                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
+ #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE               ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
+ #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE               (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
+ #define MXC_V_GPIO_EN0_GPIO_EN_GPIO                    ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
+ #define MXC_S_GPIO_EN0_GPIO_EN_GPIO                    (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
+
+/**@} end of group GPIO_EN0_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN0_SET GPIO_EN0_SET
+ * @brief    GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
+ *           register sets the bits in the same positions in GPIO_EN to 1, without affecting
+ *           other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN0_SET_ALL_POS                     0 /**< EN0_SET_ALL Position */
+ #define MXC_F_GPIO_EN0_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
+
+/**@} end of group GPIO_EN0_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR
+ * @brief    GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
+ *           register clears the bits in the same positions in GPIO_EN to 0, without
+ *           affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN0_CLR_ALL_POS                     0 /**< EN0_CLR_ALL Position */
+ #define MXC_F_GPIO_EN0_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN0_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUTEN GPIO_OUTEN
+ * @brief    GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
+ *           GPIO pin in the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_OUTEN_EN_POS                        0 /**< OUTEN_EN Position */
+ #define MXC_F_GPIO_OUTEN_EN                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */
+ #define MXC_V_GPIO_OUTEN_EN_DIS                        ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */
+ #define MXC_S_GPIO_OUTEN_EN_DIS                        (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */
+ #define MXC_V_GPIO_OUTEN_EN_EN                         ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */
+ #define MXC_S_GPIO_OUTEN_EN_EN                         (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */
+
+/**@} end of group GPIO_OUTEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET
+ * @brief    GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
+ *           in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
+ *           without affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUTEN_SET_ALL_POS                   0 /**< OUTEN_SET_ALL Position */
+ #define MXC_F_GPIO_OUTEN_SET_ALL                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */
+
+/**@} end of group GPIO_OUTEN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR
+ * @brief    GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
+ *           bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
+ *           without affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUTEN_CLR_ALL_POS                   0 /**< OUTEN_CLR_ALL Position */
+ #define MXC_F_GPIO_OUTEN_CLR_ALL                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */
+
+/**@} end of group GPIO_OUTEN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT GPIO_OUT
+ * @brief    GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
+ *           associated port.  This register can be written either directly, or by using the
+ *           GPIO_OUT_SET and GPIO_OUT_CLR registers.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_GPIO_OUT_POS                    0 /**< OUT_GPIO_OUT Position */
+ #define MXC_F_GPIO_OUT_GPIO_OUT                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
+ #define MXC_V_GPIO_OUT_GPIO_OUT_LOW                    ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
+ #define MXC_S_GPIO_OUT_GPIO_OUT_LOW                    (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
+ #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                   ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
+ #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                   (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
+
+/**@} end of group GPIO_OUT_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_SET GPIO_OUT_SET
+ * @brief    GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
+ *           in the same positions in GPIO_OUT to 1, without affecting other bits in that
+ *           register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS            0 /**< OUT_SET_GPIO_OUT_SET Position */
+ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
+ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO             ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
+ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO             (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
+ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET            ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
+ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET            (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
+
+/**@} end of group GPIO_OUT_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
+ * @brief    GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
+ *           bits in the same positions in GPIO_OUT to 0, without affecting other bits in
+ *           that register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS            0 /**< OUT_CLR_GPIO_OUT_CLR Position */
+ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
+
+/**@} end of group GPIO_OUT_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_IN GPIO_IN
+ * @brief    GPIO Input Register. Read-only register to read from the logic states of the
+ *           GPIO pins on this port.
+ * @{
+ */
+ #define MXC_F_GPIO_IN_GPIO_IN_POS                      0 /**< IN_GPIO_IN Position */
+ #define MXC_F_GPIO_IN_GPIO_IN                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
+
+/**@} end of group GPIO_IN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTMODE GPIO_INTMODE
+ * @brief    GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
+ *           mode setting for the associated GPIO pin on this port.
+ * @{
+ */
+ #define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS            0 /**< INTMODE_GPIO_INTMODE Position */
+ #define MXC_F_GPIO_INTMODE_GPIO_INTMODE                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */
+ #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL          ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */
+ #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL          (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */
+ #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE           ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */
+ #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE           (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */
+
+/**@} end of group GPIO_INTMODE_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTPOL GPIO_INTPOL
+ * @brief    GPIO Interrupt Polarity Register. Each bit in this register controls the
+ *           interrupt polarity setting for one GPIO pin in the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS              0 /**< INTPOL_GPIO_INTPOL Position */
+ #define MXC_F_GPIO_INTPOL_GPIO_INTPOL                  ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */
+ #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING          ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */
+ #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING          (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */
+ #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING           ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */
+ #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING           (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */
+
+/**@} end of group GPIO_INTPOL_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTEN GPIO_INTEN
+ * @brief    GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
+ *           interrupt enable for the associated pin on the GPIO port.
+ * @{
+ */
+ #define MXC_F_GPIO_INTEN_GPIO_INTEN_POS                0 /**< INTEN_GPIO_INTEN Position */
+ #define MXC_F_GPIO_INTEN_GPIO_INTEN                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */
+ #define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS                ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */
+ #define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS                (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */
+ #define MXC_V_GPIO_INTEN_GPIO_INTEN_EN                 ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */
+ #define MXC_S_GPIO_INTEN_GPIO_INTEN_EN                 (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */
+
+/**@} end of group GPIO_INTEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET
+ * @brief    GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
+ *           the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
+ *           in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS        0 /**< INTEN_SET_GPIO_INTEN_SET Position */
+ #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET            ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */
+ #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO         ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */
+ #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO         (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */
+ #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET        ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */
+ #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET        (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */
+
+/**@} end of group GPIO_INTEN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR
+ * @brief    GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
+ *           clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
+ *           other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS        0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */
+ #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR            ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */
+ #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO         ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */
+ #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO         (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */
+ #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR      ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */
+ #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR      (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */
+
+/**@} end of group GPIO_INTEN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTFL GPIO_INTFL
+ * @brief    GPIO Interrupt Status Register. Each bit in this register contains the pending
+ *           interrupt status for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_INTFL_GPIO_INTFL_POS                0 /**< INTFL_GPIO_INTFL Position */
+ #define MXC_F_GPIO_INTFL_GPIO_INTFL                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */
+ #define MXC_V_GPIO_INTFL_GPIO_INTFL_NO                 ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */
+ #define MXC_S_GPIO_INTFL_GPIO_INTFL_NO                 (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */
+ #define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING            ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */
+ #define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING            (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */
+
+/**@} end of group GPIO_INTFL_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR
+ * @brief    GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
+ *           bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
+ *           in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_INTFL_CLR_ALL_POS                   0 /**< INTFL_CLR_ALL Position */
+ #define MXC_F_GPIO_INTFL_CLR_ALL                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */
+
+/**@} end of group GPIO_INTFL_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WKEN GPIO_WKEN
+ * @brief    GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
+ *           enable for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_WKEN_GPIO_WKEN_POS                  0 /**< WKEN_GPIO_WKEN Position */
+ #define MXC_F_GPIO_WKEN_GPIO_WKEN                      ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */
+ #define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS                  ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */
+ #define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS                  (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */
+ #define MXC_V_GPIO_WKEN_GPIO_WKEN_EN                   ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */
+ #define MXC_S_GPIO_WKEN_GPIO_WKEN_EN                   (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */
+
+/**@} end of group GPIO_WKEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET
+ * @brief    GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
+ *           bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
+ *           that register.
+ * @{
+ */
+ #define MXC_F_GPIO_WKEN_SET_ALL_POS                    0 /**< WKEN_SET_ALL Position */
+ #define MXC_F_GPIO_WKEN_SET_ALL                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */
+
+/**@} end of group GPIO_WKEN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR
+ * @brief    GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
+ *           the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_WKEN_CLR_ALL_POS                    0 /**< WKEN_CLR_ALL Position */
+ #define MXC_F_GPIO_WKEN_CLR_ALL                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */
+
+/**@} end of group GPIO_WKEN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE
+ * @brief    GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
+ *           edge mode for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS          0 /**< DUALEDGE_GPIO_DUALEDGE Position */
+ #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */
+ #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO           ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */
+ #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO           (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */
+ #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN           ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */
+ #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN           (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */
+
+/**@} end of group GPIO_DUALEDGE_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0
+ * @brief    GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
+ *           the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS          0 /**< PADCTRL0_GPIO_PADCTRL0 Position */
+ #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */
+ #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE    ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */
+ #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE    (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */
+ #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU           ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */
+ #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU           (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */
+ #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD           ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */
+ #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD           (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */
+
+/**@} end of group GPIO_PADCTRL0_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1
+ * @brief    GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
+ *           the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS          0 /**< PADCTRL1_GPIO_PADCTRL1 Position */
+ #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */
+ #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE    ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */
+ #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE    (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */
+ #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU           ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */
+ #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU           (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */
+ #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD           ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */
+ #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD           (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */
+
+/**@} end of group GPIO_PADCTRL1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1 GPIO_EN1
+ * @brief    GPIO Alternate Function Enable Register. Each bit in this register selects
+ *           between primary/secondary functions for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_EN1_GPIO_EN1_POS                    0 /**< EN1_GPIO_EN1 Position */
+ #define MXC_F_GPIO_EN1_GPIO_EN1                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
+ #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
+ #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
+ #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY              ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
+ #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY              (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
+
+/**@} end of group GPIO_EN1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1_SET GPIO_EN1_SET
+ * @brief    GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
+ *           sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN1_SET_ALL_POS                     0 /**< EN1_SET_ALL Position */
+ #define MXC_F_GPIO_EN1_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
+
+/**@} end of group GPIO_EN1_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
+ * @brief    GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
+ *           clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN1_CLR_ALL_POS                     0 /**< EN1_CLR_ALL Position */
+ #define MXC_F_GPIO_EN1_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN1_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2 GPIO_EN2
+ * @brief    GPIO Alternate Function Enable Register. Each bit in this register selects
+ *           between primary/secondary functions for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_EN2_GPIO_EN2_POS                    0 /**< EN2_GPIO_EN2 Position */
+ #define MXC_F_GPIO_EN2_GPIO_EN2                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
+ #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
+ #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
+ #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY              ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
+ #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY              (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
+
+/**@} end of group GPIO_EN2_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2_SET GPIO_EN2_SET
+ * @brief    GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
+ *           sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN2_SET_ALL_POS                     0 /**< EN2_SET_ALL Position */
+ #define MXC_F_GPIO_EN2_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
+
+/**@} end of group GPIO_EN2_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
+ * @brief    GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
+ *           register clears the bits in the same positions in GPIO_EN2 to 0, without
+ *           affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN2_CLR_ALL_POS                     0 /**< EN2_CLR_ALL Position */
+ #define MXC_F_GPIO_EN2_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN2_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_HYSEN GPIO_HYSEN
+ * @brief    GPIO Input Hysteresis Enable.
+ * @{
+ */
+ #define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS                0 /**< HYSEN_GPIO_HYSEN Position */
+ #define MXC_F_GPIO_HYSEN_GPIO_HYSEN                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */
+
+/**@} end of group GPIO_HYSEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_SRSEL GPIO_SRSEL
+ * @brief    GPIO Slew Rate Enable Register.
+ * @{
+ */
+ #define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS                0 /**< SRSEL_GPIO_SRSEL Position */
+ #define MXC_F_GPIO_SRSEL_GPIO_SRSEL                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */
+ #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST               ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */
+ #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST               (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */
+ #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW               ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */
+ #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW               (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */
+
+/**@} end of group GPIO_SRSEL_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DS0 GPIO_DS0
+ * @brief    GPIO Drive Strength  Register. Each bit in this register selects the drive
+ *           strength for the associated GPIO pin in this port. Refer to the Datasheet for
+ *           sink/source current of GPIO pins in each mode.
+ * @{
+ */
+ #define MXC_F_GPIO_DS0_GPIO_DS0_POS                    0 /**< DS0_GPIO_DS0 Position */
+ #define MXC_F_GPIO_DS0_GPIO_DS0                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */
+ #define MXC_V_GPIO_DS0_GPIO_DS0_LD                     ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */
+ #define MXC_S_GPIO_DS0_GPIO_DS0_LD                     (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */
+ #define MXC_V_GPIO_DS0_GPIO_DS0_HD                     ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */
+ #define MXC_S_GPIO_DS0_GPIO_DS0_HD                     (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */
+
+/**@} end of group GPIO_DS0_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DS1 GPIO_DS1
+ * @brief    GPIO Drive Strength 1 Register. Each bit in this register selects the drive
+ *           strength for the associated GPIO pin in this port. Refer to the Datasheet for
+ *           sink/source current of GPIO pins in each mode.
+ * @{
+ */
+ #define MXC_F_GPIO_DS1_GPIO_DS1_POS                    0 /**< DS1_GPIO_DS1 Position */
+ #define MXC_F_GPIO_DS1_GPIO_DS1                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */
+
+/**@} end of group GPIO_DS1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PS GPIO_PS
+ * @brief    GPIO Pull Select Mode.
+ * @{
+ */
+ #define MXC_F_GPIO_PS_ALL_POS                          0 /**< PS_ALL Position */
+ #define MXC_F_GPIO_PS_ALL                              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
+
+/**@} end of group GPIO_PS_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h

@@ -0,0 +1,576 @@
+/**
+ * @file    i2c_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _I2C_REGS_H_
+#define _I2C_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     i2c
+ * @defgroup    i2c_registers I2C_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
+ * @details Inter-Integrated Circuit.
+ */
+
+/**
+ * @ingroup i2c_registers
+ * Structure type to access the I2C Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> I2C CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x04:</tt> I2C STATUS Register */
+    __IO uint32_t intfl0;               /**< <tt>\b 0x08:</tt> I2C INTFL0 Register */
+    __IO uint32_t inten0;               /**< <tt>\b 0x0C:</tt> I2C INTEN0 Register */
+    __IO uint32_t intfl1;               /**< <tt>\b 0x10:</tt> I2C INTFL1 Register */
+    __IO uint32_t inten1;               /**< <tt>\b 0x14:</tt> I2C INTEN1 Register */
+    __IO uint32_t fifolen;              /**< <tt>\b 0x18:</tt> I2C FIFOLEN Register */
+    __IO uint32_t rxctrl0;              /**< <tt>\b 0x1C:</tt> I2C RXCTRL0 Register */
+    __IO uint32_t rxctrl1;              /**< <tt>\b 0x20:</tt> I2C RXCTRL1 Register */
+    __IO uint32_t txctrl0;              /**< <tt>\b 0x24:</tt> I2C TXCTRL0 Register */
+    __IO uint32_t txctrl1;              /**< <tt>\b 0x28:</tt> I2C TXCTRL1 Register */
+    __IO uint32_t fifo;                 /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
+    __IO uint32_t mstctrl;              /**< <tt>\b 0x30:</tt> I2C MSTCTRL Register */
+    __IO uint32_t clklo;                /**< <tt>\b 0x34:</tt> I2C CLKLO Register */
+    __IO uint32_t clkhi;                /**< <tt>\b 0x38:</tt> I2C CLKHI Register */
+    __IO uint32_t hsclk;                /**< <tt>\b 0x3C:</tt> I2C HSCLK Register */
+    __IO uint32_t timeout;              /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
+    __IO uint32_t slave;                /**< <tt>\b 0x44:</tt> I2C SLAVE Register */
+    __IO uint32_t dma;                  /**< <tt>\b 0x48:</tt> I2C DMA Register */
+} mxc_i2c_regs_t;
+
+/* Register offsets for module I2C */
+/**
+ * @ingroup    i2c_registers
+ * @defgroup   I2C_Register_Offsets Register Offsets
+ * @brief      I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_I2C_CTRL                     ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_I2C_STATUS                   ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_I2C_INTFL0                   ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_I2C_INTEN0                   ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_I2C_INTFL1                   ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_I2C_INTEN1                   ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_I2C_FIFOLEN                  ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_I2C_RXCTRL0                  ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_I2C_RXCTRL1                  ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_I2C_TXCTRL0                  ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_I2C_TXCTRL1                  ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_I2C_FIFO                     ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_I2C_MSTCTRL                  ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_I2C_CLKLO                    ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_I2C_CLKHI                    ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 
+ #define MXC_R_I2C_HSCLK                    ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ 
+ #define MXC_R_I2C_TIMEOUT                  ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_I2C_SLAVE                    ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */ 
+ #define MXC_R_I2C_DMA                      ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 
+/**@} end of group i2c_registers */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CTRL I2C_CTRL
+ * @brief    Control Register0.
+ * @{
+ */
+ #define MXC_F_I2C_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_I2C_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_I2C_CTRL_MST_MODE_POS                    1 /**< CTRL_MST_MODE Position */
+ #define MXC_F_I2C_CTRL_MST_MODE                        ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */
+
+ #define MXC_F_I2C_CTRL_GC_ADDR_EN_POS                  2 /**< CTRL_GC_ADDR_EN Position */
+ #define MXC_F_I2C_CTRL_GC_ADDR_EN                      ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */
+
+ #define MXC_F_I2C_CTRL_IRXM_EN_POS                     3 /**< CTRL_IRXM_EN Position */
+ #define MXC_F_I2C_CTRL_IRXM_EN                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */
+
+ #define MXC_F_I2C_CTRL_IRXM_ACK_POS                    4 /**< CTRL_IRXM_ACK Position */
+ #define MXC_F_I2C_CTRL_IRXM_ACK                        ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */
+
+ #define MXC_F_I2C_CTRL_SCL_OUT_POS                     6 /**< CTRL_SCL_OUT Position */
+ #define MXC_F_I2C_CTRL_SCL_OUT                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
+
+ #define MXC_F_I2C_CTRL_SDA_OUT_POS                     7 /**< CTRL_SDA_OUT Position */
+ #define MXC_F_I2C_CTRL_SDA_OUT                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
+
+ #define MXC_F_I2C_CTRL_SCL_POS                         8 /**< CTRL_SCL Position */
+ #define MXC_F_I2C_CTRL_SCL                             ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
+
+ #define MXC_F_I2C_CTRL_SDA_POS                         9 /**< CTRL_SDA Position */
+ #define MXC_F_I2C_CTRL_SDA                             ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
+
+ #define MXC_F_I2C_CTRL_BB_MODE_POS                     10 /**< CTRL_BB_MODE Position */
+ #define MXC_F_I2C_CTRL_BB_MODE                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */
+
+ #define MXC_F_I2C_CTRL_READ_POS                        11 /**< CTRL_READ Position */
+ #define MXC_F_I2C_CTRL_READ                            ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
+
+ #define MXC_F_I2C_CTRL_CLKSTR_DIS_POS                  12 /**< CTRL_CLKSTR_DIS Position */
+ #define MXC_F_I2C_CTRL_CLKSTR_DIS                      ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */
+
+ #define MXC_F_I2C_CTRL_ONE_MST_MODE_POS                13 /**< CTRL_ONE_MST_MODE Position */
+ #define MXC_F_I2C_CTRL_ONE_MST_MODE                    ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */
+
+ #define MXC_F_I2C_CTRL_HS_EN_POS                       15 /**< CTRL_HS_EN Position */
+ #define MXC_F_I2C_CTRL_HS_EN                           ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */
+
+/**@} end of group I2C_CTRL_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_STATUS I2C_STATUS
+ * @brief    Status Register.
+ * @{
+ */
+ #define MXC_F_I2C_STATUS_BUSY_POS                      0 /**< STATUS_BUSY Position */
+ #define MXC_F_I2C_STATUS_BUSY                          ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
+
+ #define MXC_F_I2C_STATUS_RX_EM_POS                     1 /**< STATUS_RX_EM Position */
+ #define MXC_F_I2C_STATUS_RX_EM                         ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
+
+ #define MXC_F_I2C_STATUS_RX_FULL_POS                   2 /**< STATUS_RX_FULL Position */
+ #define MXC_F_I2C_STATUS_RX_FULL                       ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+
+ #define MXC_F_I2C_STATUS_TX_EM_POS                     3 /**< STATUS_TX_EM Position */
+ #define MXC_F_I2C_STATUS_TX_EM                         ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
+
+ #define MXC_F_I2C_STATUS_TX_FULL_POS                   4 /**< STATUS_TX_FULL Position */
+ #define MXC_F_I2C_STATUS_TX_FULL                       ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+
+ #define MXC_F_I2C_STATUS_MST_BUSY_POS                  5 /**< STATUS_MST_BUSY Position */
+ #define MXC_F_I2C_STATUS_MST_BUSY                      ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */
+
+/**@} end of group I2C_STATUS_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTFL0 I2C_INTFL0
+ * @brief    Interrupt Status Register.
+ * @{
+ */
+ #define MXC_F_I2C_INTFL0_DONE_POS                      0 /**< INTFL0_DONE Position */
+ #define MXC_F_I2C_INTFL0_DONE                          ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */
+
+ #define MXC_F_I2C_INTFL0_IRXM_POS                      1 /**< INTFL0_IRXM Position */
+ #define MXC_F_I2C_INTFL0_IRXM                          ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */
+
+ #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS             2 /**< INTFL0_GC_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INTFL0_ADDR_MATCH_POS                3 /**< INTFL0_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTFL0_ADDR_MATCH                    ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INTFL0_RX_THD_POS                    4 /**< INTFL0_RX_THD Position */
+ #define MXC_F_I2C_INTFL0_RX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */
+
+ #define MXC_F_I2C_INTFL0_TX_THD_POS                    5 /**< INTFL0_TX_THD Position */
+ #define MXC_F_I2C_INTFL0_TX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */
+
+ #define MXC_F_I2C_INTFL0_STOP_POS                      6 /**< INTFL0_STOP Position */
+ #define MXC_F_I2C_INTFL0_STOP                          ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */
+
+ #define MXC_F_I2C_INTFL0_ADDR_ACK_POS                  7 /**< INTFL0_ADDR_ACK Position */
+ #define MXC_F_I2C_INTFL0_ADDR_ACK                      ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */
+
+ #define MXC_F_I2C_INTFL0_ARB_ERR_POS                   8 /**< INTFL0_ARB_ERR Position */
+ #define MXC_F_I2C_INTFL0_ARB_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */
+
+ #define MXC_F_I2C_INTFL0_TO_ERR_POS                    9 /**< INTFL0_TO_ERR Position */
+ #define MXC_F_I2C_INTFL0_TO_ERR                        ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */
+
+ #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS             10 /**< INTFL0_ADDR_NACK_ERR Position */
+ #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR                 ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */
+
+ #define MXC_F_I2C_INTFL0_DATA_ERR_POS                  11 /**< INTFL0_DATA_ERR Position */
+ #define MXC_F_I2C_INTFL0_DATA_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */
+
+ #define MXC_F_I2C_INTFL0_DNR_ERR_POS                   12 /**< INTFL0_DNR_ERR Position */
+ #define MXC_F_I2C_INTFL0_DNR_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */
+
+ #define MXC_F_I2C_INTFL0_START_ERR_POS                 13 /**< INTFL0_START_ERR Position */
+ #define MXC_F_I2C_INTFL0_START_ERR                     ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */
+
+ #define MXC_F_I2C_INTFL0_STOP_ERR_POS                  14 /**< INTFL0_STOP_ERR Position */
+ #define MXC_F_I2C_INTFL0_STOP_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */
+
+ #define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS                15 /**< INTFL0_TX_LOCKOUT Position */
+ #define MXC_F_I2C_INTFL0_TX_LOCKOUT                    ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */
+
+ #define MXC_F_I2C_INTFL0_MAMI_POS                      16 /**< INTFL0_MAMI Position */
+ #define MXC_F_I2C_INTFL0_MAMI                          ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */
+
+ #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS             22 /**< INTFL0_RD_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS             23 /**< INTFL0_WR_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */
+
+/**@} end of group I2C_INTFL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTEN0 I2C_INTEN0
+ * @brief    Interrupt Enable Register.
+ * @{
+ */
+ #define MXC_F_I2C_INTEN0_DONE_POS                      0 /**< INTEN0_DONE Position */
+ #define MXC_F_I2C_INTEN0_DONE                          ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */
+
+ #define MXC_F_I2C_INTEN0_IRXM_POS                      1 /**< INTEN0_IRXM Position */
+ #define MXC_F_I2C_INTEN0_IRXM                          ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */
+
+ #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS             2 /**< INTEN0_GC_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INTEN0_ADDR_MATCH_POS                3 /**< INTEN0_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTEN0_ADDR_MATCH                    ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INTEN0_RX_THD_POS                    4 /**< INTEN0_RX_THD Position */
+ #define MXC_F_I2C_INTEN0_RX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */
+
+ #define MXC_F_I2C_INTEN0_TX_THD_POS                    5 /**< INTEN0_TX_THD Position */
+ #define MXC_F_I2C_INTEN0_TX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */
+
+ #define MXC_F_I2C_INTEN0_STOP_POS                      6 /**< INTEN0_STOP Position */
+ #define MXC_F_I2C_INTEN0_STOP                          ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */
+
+ #define MXC_F_I2C_INTEN0_ADDR_ACK_POS                  7 /**< INTEN0_ADDR_ACK Position */
+ #define MXC_F_I2C_INTEN0_ADDR_ACK                      ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */
+
+ #define MXC_F_I2C_INTEN0_ARB_ERR_POS                   8 /**< INTEN0_ARB_ERR Position */
+ #define MXC_F_I2C_INTEN0_ARB_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */
+
+ #define MXC_F_I2C_INTEN0_TO_ERR_POS                    9 /**< INTEN0_TO_ERR Position */
+ #define MXC_F_I2C_INTEN0_TO_ERR                        ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */
+
+ #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS             10 /**< INTEN0_ADDR_NACK_ERR Position */
+ #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR                 ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */
+
+ #define MXC_F_I2C_INTEN0_DATA_ERR_POS                  11 /**< INTEN0_DATA_ERR Position */
+ #define MXC_F_I2C_INTEN0_DATA_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */
+
+ #define MXC_F_I2C_INTEN0_DNR_ERR_POS                   12 /**< INTEN0_DNR_ERR Position */
+ #define MXC_F_I2C_INTEN0_DNR_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */
+
+ #define MXC_F_I2C_INTEN0_START_ERR_POS                 13 /**< INTEN0_START_ERR Position */
+ #define MXC_F_I2C_INTEN0_START_ERR                     ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */
+
+ #define MXC_F_I2C_INTEN0_STOP_ERR_POS                  14 /**< INTEN0_STOP_ERR Position */
+ #define MXC_F_I2C_INTEN0_STOP_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */
+
+ #define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS                15 /**< INTEN0_TX_LOCKOUT Position */
+ #define MXC_F_I2C_INTEN0_TX_LOCKOUT                    ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */
+
+ #define MXC_F_I2C_INTEN0_MAMI_POS                      16 /**< INTEN0_MAMI Position */
+ #define MXC_F_I2C_INTEN0_MAMI                          ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */
+
+ #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS             22 /**< INTEN0_RD_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS             23 /**< INTEN0_WR_ADDR_MATCH Position */
+ #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */
+
+/**@} end of group I2C_INTEN0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTFL1 I2C_INTFL1
+ * @brief    Interrupt Status Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_INTFL1_RX_OV_POS                     0 /**< INTFL1_RX_OV Position */
+ #define MXC_F_I2C_INTFL1_RX_OV                         ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */
+
+ #define MXC_F_I2C_INTFL1_TX_UN_POS                     1 /**< INTFL1_TX_UN Position */
+ #define MXC_F_I2C_INTFL1_TX_UN                         ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */
+
+ #define MXC_F_I2C_INTFL1_START_POS                     2 /**< INTFL1_START Position */
+ #define MXC_F_I2C_INTFL1_START                         ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */
+
+/**@} end of group I2C_INTFL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTEN1 I2C_INTEN1
+ * @brief    Interrupt Staus Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_INTEN1_RX_OV_POS                     0 /**< INTEN1_RX_OV Position */
+ #define MXC_F_I2C_INTEN1_RX_OV                         ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */
+
+ #define MXC_F_I2C_INTEN1_TX_UN_POS                     1 /**< INTEN1_TX_UN Position */
+ #define MXC_F_I2C_INTEN1_TX_UN                         ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */
+
+ #define MXC_F_I2C_INTEN1_START_POS                     2 /**< INTEN1_START Position */
+ #define MXC_F_I2C_INTEN1_START                         ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */
+
+/**@} end of group I2C_INTEN1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_FIFOLEN I2C_FIFOLEN
+ * @brief    FIFO Configuration Register.
+ * @{
+ */
+ #define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS                 0 /**< FIFOLEN_RX_DEPTH Position */
+ #define MXC_F_I2C_FIFOLEN_RX_DEPTH                     ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */
+
+ #define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS                 8 /**< FIFOLEN_TX_DEPTH Position */
+ #define MXC_F_I2C_FIFOLEN_TX_DEPTH                     ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */
+
+/**@} end of group I2C_FIFOLEN_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_RXCTRL0 I2C_RXCTRL0
+ * @brief    Receive Control Register 0.
+ * @{
+ */
+ #define MXC_F_I2C_RXCTRL0_DNR_POS                      0 /**< RXCTRL0_DNR Position */
+ #define MXC_F_I2C_RXCTRL0_DNR                          ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */
+
+ #define MXC_F_I2C_RXCTRL0_FLUSH_POS                    7 /**< RXCTRL0_FLUSH Position */
+ #define MXC_F_I2C_RXCTRL0_FLUSH                        ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */
+
+ #define MXC_F_I2C_RXCTRL0_THD_LVL_POS                  8 /**< RXCTRL0_THD_LVL Position */
+ #define MXC_F_I2C_RXCTRL0_THD_LVL                      ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */
+
+/**@} end of group I2C_RXCTRL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_RXCTRL1 I2C_RXCTRL1
+ * @brief    Receive Control Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_RXCTRL1_CNT_POS                      0 /**< RXCTRL1_CNT Position */
+ #define MXC_F_I2C_RXCTRL1_CNT                          ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */
+
+ #define MXC_F_I2C_RXCTRL1_LVL_POS                      8 /**< RXCTRL1_LVL Position */
+ #define MXC_F_I2C_RXCTRL1_LVL                          ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */
+
+/**@} end of group I2C_RXCTRL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TXCTRL0 I2C_TXCTRL0
+ * @brief    Transmit Control Register 0.
+ * @{
+ */
+ #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS             0 /**< TXCTRL0_PRELOAD_MODE Position */
+ #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE                 ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */
+
+ #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS            1 /**< TXCTRL0_TX_READY_MODE Position */
+ #define MXC_F_I2C_TXCTRL0_TX_READY_MODE                ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */
+
+ #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS        2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */
+ #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS            ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS        3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */
+ #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS            ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS        4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */
+ #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS            ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS           5 /**< TXCTRL0_NACK_FLUSH_DIS Position */
+ #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS               ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_TXCTRL0_FLUSH_POS                    7 /**< TXCTRL0_FLUSH Position */
+ #define MXC_F_I2C_TXCTRL0_FLUSH                        ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */
+
+ #define MXC_F_I2C_TXCTRL0_THD_VAL_POS                  8 /**< TXCTRL0_THD_VAL Position */
+ #define MXC_F_I2C_TXCTRL0_THD_VAL                      ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */
+
+/**@} end of group I2C_TXCTRL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TXCTRL1 I2C_TXCTRL1
+ * @brief    Transmit Control Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS              0 /**< TXCTRL1_PRELOAD_RDY Position */
+ #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY                  ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */
+
+ #define MXC_F_I2C_TXCTRL1_LVL_POS                      8 /**< TXCTRL1_LVL Position */
+ #define MXC_F_I2C_TXCTRL1_LVL                          ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */
+
+/**@} end of group I2C_TXCTRL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_FIFO I2C_FIFO
+ * @brief    Data Register.
+ * @{
+ */
+ #define MXC_F_I2C_FIFO_DATA_POS                        0 /**< FIFO_DATA Position */
+ #define MXC_F_I2C_FIFO_DATA                            ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+
+/**@} end of group I2C_FIFO_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_MSTCTRL I2C_MSTCTRL
+ * @brief    Master Control Register.
+ * @{
+ */
+ #define MXC_F_I2C_MSTCTRL_START_POS                    0 /**< MSTCTRL_START Position */
+ #define MXC_F_I2C_MSTCTRL_START                        ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */
+
+ #define MXC_F_I2C_MSTCTRL_RESTART_POS                  1 /**< MSTCTRL_RESTART Position */
+ #define MXC_F_I2C_MSTCTRL_RESTART                      ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */
+
+ #define MXC_F_I2C_MSTCTRL_STOP_POS                     2 /**< MSTCTRL_STOP Position */
+ #define MXC_F_I2C_MSTCTRL_STOP                         ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */
+
+ #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS               7 /**< MSTCTRL_EX_ADDR_EN Position */
+ #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN                   ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */
+
+/**@} end of group I2C_MSTCTRL_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CLKLO I2C_CLKLO
+ * @brief    Clock Low Register.
+ * @{
+ */
+ #define MXC_F_I2C_CLKLO_LO_POS                         0 /**< CLKLO_LO Position */
+ #define MXC_F_I2C_CLKLO_LO                             ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */
+
+/**@} end of group I2C_CLKLO_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CLKHI I2C_CLKHI
+ * @brief    Clock high Register.
+ * @{
+ */
+ #define MXC_F_I2C_CLKHI_HI_POS                         0 /**< CLKHI_HI Position */
+ #define MXC_F_I2C_CLKHI_HI                             ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */
+
+/**@} end of group I2C_CLKHI_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_HSCLK I2C_HSCLK
+ * @brief    Clock high Register.
+ * @{
+ */
+ #define MXC_F_I2C_HSCLK_LO_POS                         0 /**< HSCLK_LO Position */
+ #define MXC_F_I2C_HSCLK_LO                             ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */
+
+ #define MXC_F_I2C_HSCLK_HI_POS                         8 /**< HSCLK_HI Position */
+ #define MXC_F_I2C_HSCLK_HI                             ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */
+
+/**@} end of group I2C_HSCLK_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TIMEOUT I2C_TIMEOUT
+ * @brief    Timeout Register
+ * @{
+ */
+ #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS               0 /**< TIMEOUT_SCL_TO_VAL Position */
+ #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL                   ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */
+
+/**@} end of group I2C_TIMEOUT_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_SLAVE I2C_SLAVE
+ * @brief    Slave Address Register.
+ * @{
+ */
+ #define MXC_F_I2C_SLAVE_ADDR_POS                       0 /**< SLAVE_ADDR Position */
+ #define MXC_F_I2C_SLAVE_ADDR                           ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */
+
+ #define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS                15 /**< SLAVE_EXT_ADDR_EN Position */
+ #define MXC_F_I2C_SLAVE_EXT_ADDR_EN                    ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */
+
+/**@} end of group I2C_SLAVE_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_DMA I2C_DMA
+ * @brief    DMA Register.
+ * @{
+ */
+ #define MXC_F_I2C_DMA_TX_EN_POS                        0 /**< DMA_TX_EN Position */
+ #define MXC_F_I2C_DMA_TX_EN                            ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
+
+ #define MXC_F_I2C_DMA_RX_EN_POS                        1 /**< DMA_RX_EN Position */
+ #define MXC_F_I2C_DMA_RX_EN                            ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
+
+/**@} end of group I2C_DMA_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2C_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h

@@ -0,0 +1,280 @@
+/**
+ * @file    i2s_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the I2S Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _I2S_REGS_H_
+#define _I2S_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     i2s
+ * @defgroup    i2s_registers I2S_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the I2S Peripheral Module.
+ * @details Inter-IC Sound Interface.
+ */
+
+/**
+ * @ingroup i2s_registers
+ * Structure type to access the I2S Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl0ch0;             /**< <tt>\b 0x00:</tt> I2S CTRL0CH0 Register */
+    __I  uint32_t rsv_0x4_0xf[3];
+    __IO uint32_t ctrl1ch0;             /**< <tt>\b 0x10:</tt> I2S CTRL1CH0 Register */
+    __I  uint32_t rsv_0x14_0x2f[7];
+    __IO uint32_t dmach0;               /**< <tt>\b 0x30:</tt> I2S DMACH0 Register */
+    __I  uint32_t rsv_0x34_0x3f[3];
+    __IO uint32_t fifoch0;              /**< <tt>\b 0x40:</tt> I2S FIFOCH0 Register */
+    __I  uint32_t rsv_0x44_0x4f[3];
+    __IO uint32_t intfl;                /**< <tt>\b 0x50:</tt> I2S INTFL Register */
+    __IO uint32_t inten;                /**< <tt>\b 0x54:</tt> I2S INTEN Register */
+    __IO uint32_t extsetup;             /**< <tt>\b 0x58:</tt> I2S EXTSETUP Register */
+} mxc_i2s_regs_t;
+
+/* Register offsets for module I2S */
+/**
+ * @ingroup    i2s_registers
+ * @defgroup   I2S_Register_Offsets Register Offsets
+ * @brief      I2S Peripheral Register Offsets from the I2S Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_I2S_CTRL0CH0                 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_I2S_CTRL1CH0                 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_I2S_DMACH0                   ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_I2S_FIFOCH0                  ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_I2S_INTFL                    ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: <tt> 0x0050</tt> */ 
+ #define MXC_R_I2S_INTEN                    ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: <tt> 0x0054</tt> */ 
+ #define MXC_R_I2S_EXTSETUP                 ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: <tt> 0x0058</tt> */ 
+/**@} end of group i2s_registers */
+
+/**
+ * @ingroup  i2s_registers
+ * @defgroup I2S_CTRL0CH0 I2S_CTRL0CH0
+ * @brief    Global mode channel.
+ * @{
+ */
+ #define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS               1 /**< CTRL0CH0_LSB_FIRST Position */
+ #define MXC_F_I2S_CTRL0CH0_LSB_FIRST                   ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_CH_MODE_POS                 6 /**< CTRL0CH0_CH_MODE Position */
+ #define MXC_F_I2S_CTRL0CH0_CH_MODE                     ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_WS_POL_POS                  8 /**< CTRL0CH0_WS_POL Position */
+ #define MXC_F_I2S_CTRL0CH0_WS_POL                      ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS                 9 /**< CTRL0CH0_MSB_LOC Position */
+ #define MXC_F_I2S_CTRL0CH0_MSB_LOC                     ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_ALIGN_POS                   10 /**< CTRL0CH0_ALIGN Position */
+ #define MXC_F_I2S_CTRL0CH0_ALIGN                       ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS                 11 /**< CTRL0CH0_EXT_SEL Position */
+ #define MXC_F_I2S_CTRL0CH0_EXT_SEL                     ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_STEREO_POS                  12 /**< CTRL0CH0_STEREO Position */
+ #define MXC_F_I2S_CTRL0CH0_STEREO                      ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_WSIZE_POS                   14 /**< CTRL0CH0_WSIZE Position */
+ #define MXC_F_I2S_CTRL0CH0_WSIZE                       ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_TX_EN_POS                   16 /**< CTRL0CH0_TX_EN Position */
+ #define MXC_F_I2S_CTRL0CH0_TX_EN                       ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_RX_EN_POS                   17 /**< CTRL0CH0_RX_EN Position */
+ #define MXC_F_I2S_CTRL0CH0_RX_EN                       ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_FLUSH_POS                   18 /**< CTRL0CH0_FLUSH Position */
+ #define MXC_F_I2S_CTRL0CH0_FLUSH                       ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_RST_POS                     19 /**< CTRL0CH0_RST Position */
+ #define MXC_F_I2S_CTRL0CH0_RST                         ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS                19 /**< CTRL0CH0_FIFO_LSB Position */
+ #define MXC_F_I2S_CTRL0CH0_FIFO_LSB                    ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */
+
+ #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS              24 /**< CTRL0CH0_RX_THD_VAL Position */
+ #define MXC_F_I2S_CTRL0CH0_RX_THD_VAL                  ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */
+
+/**@} end of group I2S_CTRL0CH0_Register */
+
+/**
+ * @ingroup  i2s_registers
+ * @defgroup I2S_CTRL1CH0 I2S_CTRL1CH0
+ * @brief    Local channel Setup.
+ * @{
+ */
+ #define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS               0 /**< CTRL1CH0_BITS_WORD Position */
+ #define MXC_F_I2S_CTRL1CH0_BITS_WORD                   ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */
+
+ #define MXC_F_I2S_CTRL1CH0_EN_POS                      8 /**< CTRL1CH0_EN Position */
+ #define MXC_F_I2S_CTRL1CH0_EN                          ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */
+
+ #define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS                9 /**< CTRL1CH0_SMP_SIZE Position */
+ #define MXC_F_I2S_CTRL1CH0_SMP_SIZE                    ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */
+
+ #define MXC_F_I2S_CTRL1CH0_ADJST_POS                   15 /**< CTRL1CH0_ADJST Position */
+ #define MXC_F_I2S_CTRL1CH0_ADJST                       ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJST_POS)) /**< CTRL1CH0_ADJST Mask */
+
+ #define MXC_F_I2S_CTRL1CH0_CLKDIV_POS                  16 /**< CTRL1CH0_CLKDIV Position */
+ #define MXC_F_I2S_CTRL1CH0_CLKDIV                      ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */
+
+/**@} end of group I2S_CTRL1CH0_Register */
+
+/**
+ * @ingroup  i2s_registers
+ * @defgroup I2S_DMACH0 I2S_DMACH0
+ * @brief    DMA Control.
+ * @{
+ */
+ #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS            0 /**< DMACH0_DMA_TX_THD_VAL Position */
+ #define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL                ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */
+
+ #define MXC_F_I2S_DMACH0_DMA_TX_EN_POS                 7 /**< DMACH0_DMA_TX_EN Position */
+ #define MXC_F_I2S_DMACH0_DMA_TX_EN                     ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */
+
+ #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS            8 /**< DMACH0_DMA_RX_THD_VAL Position */
+ #define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL                ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */
+
+ #define MXC_F_I2S_DMACH0_DMA_RX_EN_POS                 15 /**< DMACH0_DMA_RX_EN Position */
+ #define MXC_F_I2S_DMACH0_DMA_RX_EN                     ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */
+
+ #define MXC_F_I2S_DMACH0_TX_LVL_POS                    16 /**< DMACH0_TX_LVL Position */
+ #define MXC_F_I2S_DMACH0_TX_LVL                        ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */
+
+ #define MXC_F_I2S_DMACH0_RX_LVL_POS                    24 /**< DMACH0_RX_LVL Position */
+ #define MXC_F_I2S_DMACH0_RX_LVL                        ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */
+
+/**@} end of group I2S_DMACH0_Register */
+
+/**
+ * @ingroup  i2s_registers
+ * @defgroup I2S_FIFOCH0 I2S_FIFOCH0
+ * @brief    I2S Fifo.
+ * @{
+ */
+ #define MXC_F_I2S_FIFOCH0_DATA_POS                     0 /**< FIFOCH0_DATA Position */
+ #define MXC_F_I2S_FIFOCH0_DATA                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */
+
+/**@} end of group I2S_FIFOCH0_Register */
+
+/**
+ * @ingroup  i2s_registers
+ * @defgroup I2S_INTFL I2S_INTFL
+ * @brief    ISR Status.
+ * @{
+ */
+ #define MXC_F_I2S_INTFL_RX_OV_CH0_POS                  0 /**< INTFL_RX_OV_CH0 Position */
+ #define MXC_F_I2S_INTFL_RX_OV_CH0                      ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */
+
+ #define MXC_F_I2S_INTFL_RX_THD_CH0_POS                 1 /**< INTFL_RX_THD_CH0 Position */
+ #define MXC_F_I2S_INTFL_RX_THD_CH0                     ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */
+
+ #define MXC_F_I2S_INTFL_TX_OB_CH0_POS                  2 /**< INTFL_TX_OB_CH0 Position */
+ #define MXC_F_I2S_INTFL_TX_OB_CH0                      ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */
+
+ #define MXC_F_I2S_INTFL_TX_HE_CH0_POS                  3 /**< INTFL_TX_HE_CH0 Position */
+ #define MXC_F_I2S_INTFL_TX_HE_CH0                      ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */
+
+/**@} end of group I2S_INTFL_Register */
+
+/**
+ * @ingroup  i2s_registers
+ * @defgroup I2S_INTEN I2S_INTEN
+ * @brief    Interrupt Enable.
+ * @{
+ */
+ #define MXC_F_I2S_INTEN_RX_OV_CH0_POS                  0 /**< INTEN_RX_OV_CH0 Position */
+ #define MXC_F_I2S_INTEN_RX_OV_CH0                      ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */
+
+ #define MXC_F_I2S_INTEN_RX_THD_CH0_POS                 1 /**< INTEN_RX_THD_CH0 Position */
+ #define MXC_F_I2S_INTEN_RX_THD_CH0                     ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */
+
+ #define MXC_F_I2S_INTEN_TX_OB_CH0_POS                  2 /**< INTEN_TX_OB_CH0 Position */
+ #define MXC_F_I2S_INTEN_TX_OB_CH0                      ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */
+
+ #define MXC_F_I2S_INTEN_TX_HE_CH0_POS                  3 /**< INTEN_TX_HE_CH0 Position */
+ #define MXC_F_I2S_INTEN_TX_HE_CH0                      ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */
+
+/**@} end of group I2S_INTEN_Register */
+
+/**
+ * @ingroup  i2s_registers
+ * @defgroup I2S_EXTSETUP I2S_EXTSETUP
+ * @brief    Ext Control.
+ * @{
+ */
+ #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS           0 /**< EXTSETUP_EXT_BITS_WORD Position */
+ #define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD               ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */
+
+/**@} end of group I2S_EXTSETUP_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2S_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h

@@ -0,0 +1,167 @@
+/**
+ * @file    icc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _ICC_REGS_H_
+#define _ICC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     icc
+ * @defgroup    icc_registers ICC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
+ * @details Instruction Cache Controller Registers
+ */
+
+/**
+ * @ingroup icc_registers
+ * Structure type to access the ICC Registers.
+ */
+typedef struct {
+    __I  uint32_t info;                 /**< <tt>\b 0x0000:</tt> ICC INFO Register */
+    __I  uint32_t sz;                   /**< <tt>\b 0x0004:</tt> ICC SZ Register */
+    __I  uint32_t rsv_0x8_0xff[62];
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x0100:</tt> ICC CTRL Register */
+    __I  uint32_t rsv_0x104_0x6ff[383];
+    __IO uint32_t invalidate;           /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
+} mxc_icc_regs_t;
+
+/* Register offsets for module ICC */
+/**
+ * @ingroup    icc_registers
+ * @defgroup   ICC_Register_Offsets Register Offsets
+ * @brief      ICC Peripheral Register Offsets from the ICC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_ICC_INFO                     ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_ICC_SZ                       ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_ICC_CTRL                     ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */ 
+ #define MXC_R_ICC_INVALIDATE               ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */ 
+/**@} end of group icc_registers */
+
+/**
+ * @ingroup  icc_registers
+ * @defgroup ICC_INFO ICC_INFO
+ * @brief    Cache ID Register.
+ * @{
+ */
+ #define MXC_F_ICC_INFO_RELNUM_POS                      0 /**< INFO_RELNUM Position */
+ #define MXC_F_ICC_INFO_RELNUM                          ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */
+
+ #define MXC_F_ICC_INFO_PARTNUM_POS                     6 /**< INFO_PARTNUM Position */
+ #define MXC_F_ICC_INFO_PARTNUM                         ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */
+
+ #define MXC_F_ICC_INFO_ID_POS                          10 /**< INFO_ID Position */
+ #define MXC_F_ICC_INFO_ID                              ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */
+
+/**@} end of group ICC_INFO_Register */
+
+/**
+ * @ingroup  icc_registers
+ * @defgroup ICC_SZ ICC_SZ
+ * @brief    Memory Configuration Register.
+ * @{
+ */
+ #define MXC_F_ICC_SZ_CCH_POS                           0 /**< SZ_CCH Position */
+ #define MXC_F_ICC_SZ_CCH                               ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */
+
+ #define MXC_F_ICC_SZ_MEM_POS                           16 /**< SZ_MEM Position */
+ #define MXC_F_ICC_SZ_MEM                               ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */
+
+/**@} end of group ICC_SZ_Register */
+
+/**
+ * @ingroup  icc_registers
+ * @defgroup ICC_CTRL ICC_CTRL
+ * @brief    Cache Control and Status Register.
+ * @{
+ */
+ #define MXC_F_ICC_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_ICC_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_ICC_CTRL_RDY_POS                         16 /**< CTRL_RDY Position */
+ #define MXC_F_ICC_CTRL_RDY                             ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
+
+/**@} end of group ICC_CTRL_Register */
+
+/**
+ * @ingroup  icc_registers
+ * @defgroup ICC_INVALIDATE ICC_INVALIDATE
+ * @brief    Invalidate All Registers.
+ * @{
+ */
+ #define MXC_F_ICC_INVALIDATE_INVALID_POS               0 /**< INVALIDATE_INVALID Position */
+ #define MXC_F_ICC_INVALIDATE_INVALID                   ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */
+
+/**@} end of group ICC_INVALIDATE_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICC_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h

@@ -0,0 +1,581 @@
+/*******************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ ******************************************************************************/
+#ifndef _MAX32670_REGS_H_
+#define _MAX32670_REGS_H_
+
+#ifndef TARGET_NUM
+#define TARGET_NUM  32670
+#endif 
+
+#define MXC_NUMCORES 1
+
+#include <stdint.h>
+
+#ifndef  FALSE
+#define  FALSE      (0)
+#endif
+
+#ifndef  TRUE
+#define  TRUE       (1)
+#endif
+
+/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
+#if defined ( __GNUC__ )
+#define __weak __attribute__((weak))
+
+#elif defined ( __CC_ARM)
+ 
+#define inline __inline
+#pragma anon_unions
+
+#endif
+
+typedef enum {
+    NonMaskableInt_IRQn    = -14,
+    HardFault_IRQn         = -13,
+    MemoryManagement_IRQn  = -12,
+    BusFault_IRQn          = -11,
+    UsageFault_IRQn        = -10,
+    SVCall_IRQn            = -5,
+    DebugMonitor_IRQn      = -4,
+    PendSV_IRQn            = -2,
+    SysTick_IRQn           = -1,
+
+    /* Device-specific interrupt sources (external to ARM core)                 */
+    /*                      table entry number                                  */
+    /*                      ||||                                                */
+    /*                      ||||  table offset address                          */
+    /*                      vvvv  vvvvvv                                        */
+
+    PF_IRQn = 0,            /* 0x10  0x0040  16: Power Fail */
+    WDT0_IRQn,              /* 0x11  0x0044  17: Watchdog 0 */
+    RSV02_IRQn,             /* 0x12  0x0048  18: Reserved */
+    RTC_IRQn,               /* 0x13  0x004C  19: RTC */
+    TRNG_IRQn,              /* 0x14  0x0050  20: True Random Number Generator */
+    TMR0_IRQn,              /* 0x15  0x0054  21: Timer 0 */
+    TMR1_IRQn,              /* 0x16  0x0058  22: Timer 1 */
+    TMR2_IRQn,              /* 0x17  0x005C  23: Timer 2 */
+    TMR3_IRQn,              /* 0x18  0x0060  24: Timer 3 */
+    TMR4_IRQn,              /* 0x19  0x0064  25: Timer 4 */
+    TMR5_IRQn,              /* 0x1A  0x0068  26: Timer 5 */
+    RSV11_IRQn,             /* 0x1B  0x006C  27: Reserved */
+    RSV12_IRQn,             /* 0x1C  0x0070  28: Reserved */
+    I2C0_IRQn,              /* 0x1D  0x0074  29: I2C0 */
+    UART0_IRQn,             /* 0x1E  0x0078  30: UART 0 */
+    UART1_IRQn,             /* 0x1F  0x007C  31: UART 1 */
+    SPI0_IRQn,              /* 0x20  0x0080  32: SPI0 */
+    SPI1_IRQn,              /* 0x21  0x0084  33: SPI1 */
+    SPI2_IRQn,              /* 0x22  0x0088  34: SPI2 */
+    RSV19_IRQn,             /* 0x23  0x008C  35: Reserved */
+    RSV20_IRQn,             /* 0x24  0x0090  36: Reserved */
+    RSV21_IRQn,             /* 0x25  0x0094  37: Reserved */
+    RSV22_IRQn,             /* 0x26  0x0098  38: Magstripe DSP */
+    FLC0_IRQn,              /* 0x27  0x009C  39: Flash Controller 0 */
+    GPIO0_IRQn,             /* 0x28  0x00A0  40: GPIO0 */
+    GPIO1_IRQn,             /* 0x29  0x00A4  41: GPIO2 */
+    RSV26_IRQn,             /* 0x2A  0x00A8  42: Reserved */
+    RSV27_IRQn,             /* 0x2B  0x00AC  43: Reserved */
+    DMA0_IRQn,              /* 0x2C  0x00B0  44: DMA0 */
+    DMA1_IRQn,              /* 0x2D  0x00B4  45: DMA1 */
+    DMA2_IRQn,              /* 0x2E  0x00B8  46: DMA2 */
+    DMA3_IRQn,              /* 0x2F  0x00BC  47: DMA3 */
+    RSV32_IRQn,             /* 0x30  0x00C0  48: Reserved */
+    RSV33_IRQn,             /* 0x31  0x00C4  49: Reserved */
+    UART2_IRQn,             /* 0x32  0x00C8  50: UART 2 */
+    RSV35_IRQn,             /* 0x33  0x00CC  51: Contactless Link Control */
+    I2C1_IRQn,              /* 0x34  0x00D0  52: I2C1 */
+    RSV37_IRQn,             /* 0x35  0x00D4  53: Smart Card 1 */
+    RSV38_IRQn,             /* 0x36  0x00D8  54: Reserved */
+    RSV39_IRQn,             /* 0x37  0x00DC  55: Reserved */
+    RSV40_IRQn,             /* 0x38  0x00E0  56: Reserved */
+    RSV41_IRQn,             /* 0x39  0x00E4  57: Reserved */
+    RSV42_IRQn,             /* 0x3A  0x00E8  58: Reserved */
+    RSV43_IRQn,             /* 0x3B  0x00EC  59: Reserved */
+    RSV44_IRQn,             /* 0x3C  0x00F0  60: Reserved */
+    RSV45_IRQn,             /* 0x3D  0x00F4  61: Reserved */
+    RSV46_IRQn,             /* 0x3E  0x00F8  62: Reserved */
+    RSV47_IRQn,             /* 0x3F  0x00FC  63: Reserved */
+    RSV48_IRQn,             /* 0x40  0x0100  64: Reserved */
+    RSV49_IRQn,             /* 0x41  0x0104  65: Reserved */
+    RSV50_IRQn,             /* 0x42  0x0108  66: Reserved */
+    RSV51_IRQn,             /* 0x43  0x010C  67: Reserved */
+    RSV52_IRQn,             /* 0x44  0x0110  68: Reserved */
+    RSV53_IRQn,             /* 0x45  0x0114  69: Reserved */
+    GPIOWAKE_IRQn,          /* 0x46  0x0118  70: GPIOWAKE */
+    RSV55_IRQn,             /* 0x47  0x011C  71: Reserved */
+    RSV56_IRQn,             /* 0x48  0x0120  72: Reserved */
+    WDT1_IRQn,              /* 0x49  0x0124  73: Watchdog 1 */
+    RSV57_IRQn,             /* 0x4A  0x0128  74: Reserved */
+    RSV58_IRQn,             /* 0x4B  0x012C  75: Reserved */
+    RSV59_IRQn,             /* 0x4C  0x0130  76: Reserved */
+    RSV61_IRQn,             /* 0x4D  0x0134  77: Reserved */
+    I2C2_IRQn,              /* 0x4E  0x0138  78: I2C 2 */
+    RSV63_IRQn,             /* 0x4F  0x013C  79: Reserved */
+    RSV64_IRQn,             /* 0x50  0x0140  80: Reserved */
+    RSV65_IRQn,             /* 0x51  0x0144  81: Reserved */
+    RSV66_IRQn,             /* 0x52  0x0148  82: Reserved */
+    RSV67_IRQn,             /* 0x53  0x014C  83: One Wire Master */
+    DMA4_IRQn,              /* 0x54  0x0150  84: DMA4 */
+    DMA5_IRQn,              /* 0x55  0x0154  85: DMA5 */
+    DMA6_IRQn,              /* 0x56  0x0158  86: DMA6 */
+    DMA7_IRQn,              /* 0x57  0x015C  87: DMA7 */
+    DMA8_IRQn,              /* 0x58  0x0160  88: DMA8 */
+    DMA9_IRQn,              /* 0x59  0x0164  89: DMA9 */
+    DMA10_IRQn,             /* 0x5A  0x0168  90: DMA10 */
+    DMA11_IRQn,             /* 0x5B  0x016C  91: DMA11 */
+    DMA12_IRQn,             /* 0x5C  0x0170  92: DMA12 */
+    DMA13_IRQn,             /* 0x5D  0x0174  93: DMA13 */
+    DMA14_IRQn,             /* 0x5E  0x0178  94: DMA14 */
+    DMA15_IRQn,             /* 0x5F  0x017C  95: DMA15 */
+    RSV80_IRQn,             /* 0x60  0x0180  96: Reserved */
+    RSV81_IRQn,             /* 0x61  0x0184  97: Reserved */
+    ECC_IRQn,               /* 0x62  0x0188  98: Error Correction */
+    RSV83_IRQn,             /* 0x63  0x018C  99: Reserved */
+    RSV84_IRQn,             /* 0x64  0x0190  100: Reserved */
+    RSV85_IRQn,             /* 0x65  0x0194  101: Reserved */
+    RSV86_IRQn,             /* 0x66  0x0198  102: Reserved */
+    RSV87_IRQn,             /* 0x67  0x019C  103: Reserved */
+    UART3_IRQn,             /* 0x68  0x01A0  104: UART 3 */
+    RSV89_IRQn,             /* 0x69  0x01A4  105: Reserved */
+    RSV90_IRQn,             /* 0x6A  0x01A8  106: Reserved */
+    RSV91_IRQn,             /* 0x6B  0x01AC  107: Reserved */
+    RSV92_IRQn,             /* 0x6C  0x01B0  108: Reserved */
+    RSV93_IRQn,           	/* 0x6D  0x01B4  109: Reserved */
+    RSV94_IRQn,           	/* 0x6E  0x01B8  110: Reserved */
+    RSV95_IRQn,           	/* 0x6F  0x01BC  111: Reserved */
+    RSV96_IRQn,           	/* 0x70  0x01C0  112: Reserved */
+    AES_IRQn,           	/* 0x71  0x01C4  113: AES */
+    CRC_IRQn,           	/* 0x72  0x01C8  114: CRC */
+    I2S_IRQn,           	/* 0x73  0x01CC  115: I2S */    
+    MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------------  Configuration of the Cortex-M Processor and Core Peripherals  ---------------------- */
+#define __CM4_REV                       0x0100          /*!< Cortex-M4 Core Revision                                */
+#define __MPU_PRESENT                   1               /*!< MPU present or not                                     */
+#define __NVIC_PRIO_BITS                3               /*!< Number of Bits used for Priority Levels                */
+#define __Vendor_SysTickConfig          0               /*!< Set to 1 if different SysTick Config is used           */
+#define __FPU_PRESENT                   1               /*!< FPU present or not                                     */
+
+#include <core_cm4.h>                                   /*!< Cortex-M4 processor and core peripherals               */
+#include "system_max32670.h"                            /*!< System Header                                          */
+
+
+/* ================================================================================ */
+/* ==================       Device Specific Memory Section       ================== */
+/* ================================================================================ */
+
+#define MXC_ROM_MEM_BASE                0x00000000UL
+#define MXC_ROM_MEM_SIZE                0x00020000UL
+#define MXC_XIP_MEM_BASE                0x08000000UL
+#define MXC_XIP_MEM_SIZE                0x08000000UL
+#define MXC_FLASH0_MEM_BASE             0x10000000UL
+#define MXC_FLASH_MEM_BASE              MXC_FLASH0_MEM_BASE
+#define MXC_FLASH_PAGE_SIZE             0x00002000UL
+#define MXC_FLASH_MEM_SIZE              (0x00060000UL - MXC_FLASH_PAGE_SIZE)
+#define MXC_INFO0_MEM_BASE              0x10800000UL
+#define MXC_INFO_MEM_BASE               MXC_INFO0_MEM_BASE
+#define MXC_INFO_MEM_SIZE               0x00004000UL
+#define MXC_SRAM_MEM_BASE               0x20000000UL
+#define MXC_SRAM_MEM_SIZE               0x00028000UL
+#define MXC_XIP_DATA_MEM_BASE           0x80000000UL
+#define MXC_XIP_DATA_MEM_SIZE           0x20000000UL
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+/*
+   Base addresses and configuration settings for all MAX32670 peripheral modules.
+*/
+
+/******************************************************************************/
+/*                                                             Global control */
+#define MXC_BASE_GCR                    ((uint32_t)0x40000000UL)
+#define MXC_GCR                         ((mxc_gcr_regs_t*)MXC_BASE_GCR)
+
+/******************************************************************************/
+/*                                            Non-battery backed SI Registers */
+#define MXC_BASE_SIR                    ((uint32_t)0x40000400UL)
+#define MXC_SIR                         ((mxc_sir_regs_t*)MXC_BASE_SIR)
+
+/******************************************************************************/
+/*                                        Non-battery backed Function Control */
+#define MXC_BASE_FCR                    ((uint32_t)0x40000800UL)
+#define MXC_FCR                         ((mxc_fcr_regs_t*)MXC_BASE_FCR)
+
+/******************************************************************************/
+/*                                        Trim System Initalization Register */
+#define MXC_BASE_TRIMSIR                ((uint32_t)0x40005400UL)
+#define MXC_TRIMSIR                     ((mxc_trimsir_regs_t*)MXC_BASE_TRIMSIR)
+
+/******************************************************************************/
+/*                                                                   Watchdog */
+#define MXC_BASE_WDT0                   ((uint32_t)0x40003000UL)
+#define MXC_WDT0                        ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
+#define MXC_BASE_WDT1                   ((uint32_t)0x40003400UL)
+#define MXC_WDT1                        ((mxc_wdt_regs_t*)MXC_BASE_WDT1)
+
+/******************************************************************************/
+/*                                                            Real Time Clock */
+#define MXC_BASE_RTC                    ((uint32_t)0x40106000UL)
+#define MXC_RTC                         ((mxc_rtc_regs_t*)MXC_BASE_RTC)
+
+/******************************************************************************/
+/*                                                            Power Sequencer */
+#define MXC_BASE_PWRSEQ                 ((uint32_t)0x40106800UL)
+#define MXC_PWRSEQ                      ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
+
+/******************************************************************************/
+/*                                                              MISC Control  */
+#define MXC_BASE_MCR                    ((uint32_t)0x40106C00UL)
+#define MXC_MCR                         ((mxc_mcr_regs_t*)MXC_BASE_MCR)
+
+
+/******************************************************************************/
+/*                                                      Error Correcting Code */
+#define MXC_BASE_ECC                    ((uint32_t)0x40105400UL)
+#define MXC_ECC                         ((mxc_ecc_regs_t*)MXC_BASE_ECC)
+
+
+/******************************************************************************/
+/*                                                                       GPIO */
+#define MXC_CFG_GPIO_INSTANCES          (2)
+#define MXC_CFG_GPIO_PINS_PORT          (32)
+
+#define MXC_BASE_GPIO0                  ((uint32_t)0x40008000UL)
+#define MXC_GPIO0                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
+#define MXC_BASE_GPIO1                  ((uint32_t)0x40009000UL)
+#define MXC_GPIO1                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)
+
+#define MXC_GPIO_GET_IDX(p)             ((p) == MXC_GPIO0 ? 0 :                \
+                                            (p) == MXC_GPIO1 ? 1 : -1)
+
+#define MXC_GPIO_GET_GPIO(i)            ((i) == 0 ? MXC_GPIO0 :                \
+                                            (i) == 1 ? MXC_GPIO1 : 0)
+
+#define MXC_GPIO_GET_IRQ(i)             ((i) == 0 ? GPIO0_IRQn :               \
+                                            (i) == 1 ? GPIO1_IRQn : 0)
+
+/******************************************************************************/
+  
+
+
+
+#define SEC(s)            (((unsigned long)s) * 1000000UL) 
+#define MSEC(ms)          (ms * 1000UL)
+#define USEC(us)          (us)
+/*                                                                      Timer */
+#define MXC_CFG_TMR_INSTANCES           (6)
+
+#define MXC_BASE_TMR0                   ((uint32_t)0x40010000UL)
+#define MXC_TMR0                        ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
+#define MXC_BASE_TMR1                   ((uint32_t)0x40011000UL)
+#define MXC_TMR1                        ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
+#define MXC_BASE_TMR2                   ((uint32_t)0x40012000UL)
+#define MXC_TMR2                        ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
+#define MXC_BASE_TMR3                   ((uint32_t)0x40013000UL)
+#define MXC_TMR3                        ((mxc_tmr_regs_t*)MXC_BASE_TMR3)
+#define MXC_BASE_TMR4                   ((uint32_t)0x40114000UL)
+#define MXC_TMR4                        ((mxc_tmr_regs_t*)MXC_BASE_TMR4)
+#define MXC_BASE_TMR5                   ((uint32_t)0x40115000UL)
+#define MXC_TMR5                        ((mxc_tmr_regs_t*)MXC_BASE_TMR5)
+
+#define MXC_TMR_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? TMR0_IRQn :     \
+                                            (i) == 1 ? TMR1_IRQn :             \
+                                            (i) == 2 ? TMR2_IRQn :             \
+                                            (i) == 3 ? TMR3_IRQn :             \
+                                            (i) == 4 ? TMR4_IRQn :             \
+                                            (i) == 5 ? TMR5_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i)             ((i) == 0 ? MXC_BASE_TMR0 :            \
+                                            (i) == 1 ? MXC_BASE_TMR1 :         \
+                                            (i) == 2 ? MXC_BASE_TMR2 :         \
+                                            (i) == 3 ? MXC_BASE_TMR3 :         \
+                                            (i) == 4 ? MXC_BASE_TMR4 :         \
+                                            (i) == 5 ? MXC_BASE_TMR5 : 0)
+
+#define MXC_TMR_GET_TMR(i)              ((i) == 0 ? MXC_TMR0 :                 \
+                                            (i) == 1 ? MXC_TMR1 :              \
+                                            (i) == 2 ? MXC_TMR2 :              \
+                                            (i) == 3 ? MXC_TMR3 :              \
+                                            (i) == 4 ? MXC_TMR4 :              \
+                                            (i) == 5 ? MXC_TMR5 : 0)
+
+#define MXC_TMR_GET_IDX(p)              ((p) == MXC_TMR0 ? 0 :                 \
+                                            (p) == MXC_TMR1 ? 1 :              \
+                                            (p) == MXC_TMR2 ? 2 :              \
+                                            (p) == MXC_TMR3 ? 3 :              \
+                                            (p) == MXC_TMR4 ? 4 :              \
+                                            (p) == MXC_TMR5 ? 5 : -1)
+
+/******************************************************************************/
+/*                                                                        I2C */
+#define MXC_I2C_INSTANCES               (3)
+
+#define MXC_BASE_I2C0                   ((uint32_t)0x4001D000UL)
+#define MXC_I2C0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
+#define MXC_BASE_I2C1                   ((uint32_t)0x4001E000UL)
+#define MXC_I2C1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
+#define MXC_BASE_I2C2                   ((uint32_t)0x4001F000UL)
+#define MXC_I2C2                        ((mxc_i2c_regs_t*)MXC_BASE_I2C2)
+
+
+#define MXC_I2C_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? I2C0_IRQn :     \
+                                            (i) == 1 ? I2C1_IRQn :             \
+                                            (i) == 2 ? I2C2_IRQn : 0)
+
+#define MXC_I2C_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2C0 :            \
+                                            (i) == 1 ? MXC_BASE_I2C1 :         \
+                                            (i) == 2 ? MXC_BASE_I2C2 : 0)
+
+#define MXC_I2C_GET_I2C(i)              ((i) == 0 ? MXC_I2C0 :                 \
+                                            (i) == 1 ? MXC_I2C1 :              \
+                                            (i) == 2 ? MXC_I2C2 : 0)
+
+#define MXC_I2C_GET_IDX(p)              ((p) == MXC_I2C0 ? 0 :                 \
+                                            (p) == MXC_I2C1 ? 1 :              \
+                                            (p) == MXC_I2C2 ? 2 : -1)
+#define MXC_I2C_FIFO_DEPTH              (8)
+
+
+/******************************************************************************/
+/*                                                                        DMA */
+#define MXC_DMA_CHANNELS                (8)
+#define MXC_DMA_INSTANCES               (1)
+
+#define MXC_BASE_DMA                    ((uint32_t)0x40028000UL)
+#define MXC_DMA                         ((mxc_dma_regs_t*)MXC_BASE_DMA)
+
+#define MXC_DMA_GET_IDX(p)              ((p) == MXC_DMA ? 0 : -1)
+
+/******************************************************************************/
+/*                                                                        FLC */
+#define MXC_FLC_INSTANCES               (1)
+
+#define MXC_BASE_FLC0                   ((uint32_t)0x40029000UL)
+#define MXC_FLC0                        ((mxc_flc_regs_t*)MXC_BASE_FLC0)
+
+
+#define MXC_FLC_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
+
+#define MXC_FLC_GET_BASE(i)             ((i) == 0 ? MXC_BASE_FLC0 : 0)
+
+#define MXC_FLC_GET_FLC(i)              ((i) == 0 ? MXC_FLC0 :  0)
+
+#define MXC_FLC_GET_IDX(p)              ((p) == MXC_FLC0 ? 0 : -1)
+/******************************************************************************/
+/*                                                          Instruction Cache */
+
+#define MXC_BASE_ICC                    ((uint32_t)0x4002A000UL)
+#define MXC_ICC                         ((mxc_icc_regs_t*)MXC_BASE_ICC)
+
+/******************************************************************************/
+/*                                                                 Data Cache */
+#define MXC_BASE_EMCC                   ((uint32_t)0x40033000UL)
+#define MXC_EMCC                        ((mxc_emcc_regs_t*)MXC_BASE_EMCC)
+
+/******************************************************************************/
+/*                                                     XXX Actually reserved! */
+#define MXC_BASE_RESERVED               ((uint32_t)0x40035000UL)
+
+/******************************************************************************/
+/*                                                            One Wire Master */
+#define MXC_BASE_OWM                    ((uint32_t)0x4003D000UL)
+#define MXC_OWM                         ((mxc_owm_regs_t*)MXC_BASE_OWM)
+
+/******************************************************************************/
+/*                                               UART / Serial Port Interface */
+
+#define MXC_UART_INSTANCES              (4)
+#define MXC_UART_FIFO_DEPTH             (8)
+
+#define MXC_BASE_UART0                  ((uint32_t)0x40042000UL)
+#define MXC_UART0                       ((mxc_uart_regs_t*)MXC_BASE_UART0)
+#define MXC_BASE_UART1                  ((uint32_t)0x40043000UL)
+#define MXC_UART1                       ((mxc_uart_regs_t*)MXC_BASE_UART1)
+#define MXC_BASE_UART2                  ((uint32_t)0x40044000UL)
+#define MXC_UART2                       ((mxc_uart_regs_t*)MXC_BASE_UART2)
+#define MXC_BASE_UART3                  ((uint32_t)0x40145000UL)
+#define MXC_UART3                       ((mxc_uart_regs_t*)MXC_BASE_UART3)
+
+#define MXC_UART_GET_IRQ(i)             (IRQn_Type)((i) == 0 ? UART0_IRQn :    \
+                                            (i) == 1 ? UART1_IRQn :            \
+                                            (i) == 2 ? UART2_IRQn :            \
+                                            (i) == 3 ? UART3_IRQn :  0)
+
+#define MXC_UART_GET_BASE(i)            ((i) == 0 ? MXC_BASE_UART0 :           \
+                                            (i) == 1 ? MXC_BASE_UART1 :        \
+                                            (i) == 2 ? MXC_BASE_UART2 :        \
+                                            (i) == 3 ? MXC_BASE_UART3 : 0)
+
+#define MXC_UART_GET_UART(i)            ((i) == 0 ? MXC_UART0 :                \
+                                            (i) == 1 ? MXC_UART1 :             \
+                                            (i) == 2 ? MXC_UART2 :             \
+                                            (i) == 3 ? MXC_UART3 : 0)
+
+#define MXC_UART_GET_IDX(p)             ((p) == MXC_UART0 ? 0 :                \
+                                            (p) == MXC_UART1 ? 1 :             \
+                                            (p) == MXC_UART2 ? 2 :               \
+                                            (p) == MXC_UART3 ? 3 : -1)
+ 
+/******************************************************************************/
+/*                                                                        SPI */
+
+#define MXC_SPI_INSTANCES               (3)
+#define MXC_SPI_SS_INSTANCES            (4)
+#define MXC_SPI_FIFO_DEPTH              (32)
+
+#define MXC_BASE_SPI0                   ((uint32_t)0x40046000UL)
+#define MXC_SPI0                        ((mxc_spi_regs_t*)MXC_BASE_SPI0)
+#define MXC_BASE_SPI1                   ((uint32_t)0x40047000UL)
+#define MXC_SPI1                        ((mxc_spi_regs_t*)MXC_BASE_SPI1)
+#define MXC_BASE_SPI2                   ((uint32_t)0x40048000UL)
+#define MXC_SPI2                        ((mxc_spi_regs_t*)MXC_BASE_SPI2)
+
+
+
+#define MXC_SPI_GET_IDX(p)              ((p) == MXC_SPI0 ? 0 :              \
+                                          (p) == MXC_SPI1 ? 1 :              \
+                                          (p) == MXC_SPI2 ? 2 :	 -1)
+
+#define MXC_SPI_GET_BASE(i)             ((i) == 0 ? MXC_BASE_SPI0 :         \
+                                          (i) == 1 ? MXC_BASE_SPI1 :         \
+                                          (i) == 2 ? MXC_BASE_SPI2 : 0)
+
+#define MXC_SPI_GET_SPI(i)              ((i) == 0 ? MXC_SPI0 :              \
+                                          (i) == 1 ? MXC_SPI1 :              \
+                                          (i) == 2 ? MXC_SPI2 : 0)
+
+#define MXC_SPI_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? SPI0_IRQn :   \
+                                          (i) == 1 ? SPI1_IRQn :             \
+                                          (i) == 2 ? SPI2_IRQn : 0)
+
+
+/******************************************************************************/
+/*                                                                       TRNG */
+#define MXC_BASE_TRNG                   ((uint32_t)0x4004D000UL)
+#define MXC_TRNG                        ((mxc_trng_regs_t*)MXC_BASE_TRNG)
+
+/******************************************************************************/
+/*                                                                        AES */
+#define MXC_BASE_AES                    ((uint32_t)0x40007400UL)
+#define MXC_AES                         ((mxc_aes_regs_t*)MXC_BASE_AES)
+
+/******************************************************************************/
+/*                                                                   AES Keys */
+#define MXC_BASE_AESKEY                 ((uint32_t)0x40005000UL)
+#define MXC_AESKEY                      ((mxc_aes_key_regs_t*)MXC_BASE_AESKEY)
+
+/******************************************************************************/
+/*                                                                        CRC */
+#define MXC_BASE_CRC                    ((uint32_t)0x4000F000UL)
+#define MXC_CRC                         ((mxc_crc_regs_t*)MXC_BASE_CRC)
+
+/******************************************************************************/
+#define MXC_BASE_I2S                    ((uint32_t)0x40060000UL)
+#define MXC_I2S                         ((mxc_i2s_regs_t*)MXC_BASE_I2S)
+
+/******************************************************************************/
+/*                                                                       BBFC */
+#define MXC_BASE_BBFC                   ((uint32_t)0x40005800UL)
+#define MXC_BBFC                        ((mxc_bbfc_regs_t*)MXC_BASE_BBFC)
+
+
+/******************************************************************************/
+/*                                                               Bit Shifting */
+
+#define MXC_F_BIT_0                     (1 << 0)
+#define MXC_F_BIT_1                     (1 << 1)
+#define MXC_F_BIT_2                     (1 << 2)
+#define MXC_F_BIT_3                     (1 << 3)
+#define MXC_F_BIT_4                     (1 << 4)
+#define MXC_F_BIT_5                     (1 << 5)
+#define MXC_F_BIT_6                     (1 << 6)
+#define MXC_F_BIT_7                     (1 << 7)
+#define MXC_F_BIT_8                     (1 << 8)
+#define MXC_F_BIT_9                     (1 << 9)
+#define MXC_F_BIT_10                    (1 << 10)
+#define MXC_F_BIT_11                    (1 << 11)
+#define MXC_F_BIT_12                    (1 << 12)
+#define MXC_F_BIT_13                    (1 << 13)
+#define MXC_F_BIT_14                    (1 << 14)
+#define MXC_F_BIT_15                    (1 << 15)
+#define MXC_F_BIT_16                    (1 << 16)
+#define MXC_F_BIT_17                    (1 << 17)
+#define MXC_F_BIT_18                    (1 << 18)
+#define MXC_F_BIT_19                    (1 << 19)
+#define MXC_F_BIT_20                    (1 << 20)
+#define MXC_F_BIT_21                    (1 << 21)
+#define MXC_F_BIT_22                    (1 << 22)
+#define MXC_F_BIT_23                    (1 << 23)
+#define MXC_F_BIT_24                    (1 << 24)
+#define MXC_F_BIT_25                    (1 << 25)
+#define MXC_F_BIT_26                    (1 << 26)
+#define MXC_F_BIT_27                    (1 << 27)
+#define MXC_F_BIT_28                    (1 << 28)
+#define MXC_F_BIT_29                    (1 << 29)
+#define MXC_F_BIT_30                    (1 << 30)
+#define MXC_F_BIT_31                    (1 << 31)
+
+/******************************************************************************/
+/*                                                               Bit Banding  */
+
+
+#define BITBAND(reg, bit)               ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
+                                            (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+
+#define MXC_CLRBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
+#define MXC_SETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
+#define MXC_GETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit))
+
+#define MXC_SETFIELD(reg, mask, setting)  (reg = (reg & ~mask) | (setting & mask))
+
+/******************************************************************************/
+/*                                                                  SCB CPACR */
+
+/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
+#define SCB_CPACR_CP10_Pos              20                              /*!< SCB CPACR: Coprocessor 10 Position */
+#define SCB_CPACR_CP10_Msk              (0x3UL << SCB_CPACR_CP10_Pos)   /*!< SCB CPACR: Coprocessor 10 Mask */
+#define SCB_CPACR_CP11_Pos              22                              /*!< SCB CPACR: Coprocessor 11 Position */
+#define SCB_CPACR_CP11_Msk              (0x3UL << SCB_CPACR_CP11_Pos)   /*!< SCB CPACR: Coprocessor 11 Mask */
+
+#endif  /* _MAX32670_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h

@@ -0,0 +1,141 @@
+/**
+ * @file    mcr_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the MCR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _MCR_REGS_H_
+#define _MCR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     mcr
+ * @defgroup    mcr_registers MCR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the MCR Peripheral Module.
+ * @details Misc Control.
+ */
+
+/**
+ * @ingroup mcr_registers
+ * Structure type to access the MCR Registers.
+ */
+typedef struct {
+    __I  uint32_t rsv_0x0;
+    __IO uint32_t rst;                  /**< <tt>\b 0x04:</tt> MCR RST Register */
+    __I  uint32_t rsv_0x8_0x23[7];
+    __IO uint32_t clkdis;               /**< <tt>\b 0x24:</tt> MCR CLKDIS Register */
+} mxc_mcr_regs_t;
+
+/* Register offsets for module MCR */
+/**
+ * @ingroup    mcr_registers
+ * @defgroup   MCR_Register_Offsets Register Offsets
+ * @brief      MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_MCR_RST                      ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_MCR_CLKDIS                   ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: <tt> 0x0024</tt> */ 
+/**@} end of group mcr_registers */
+
+/**
+ * @ingroup  mcr_registers
+ * @defgroup MCR_RST MCR_RST
+ * @brief    Reset Control Register
+ * @{
+ */
+ #define MXC_F_MCR_RST_LPTMR0_POS                       0 /**< RST_LPTMR0 Position */
+ #define MXC_F_MCR_RST_LPTMR0                           ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */
+
+ #define MXC_F_MCR_RST_LPTMR1_POS                       1 /**< RST_LPTMR1 Position */
+ #define MXC_F_MCR_RST_LPTMR1                           ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */
+
+ #define MXC_F_MCR_RST_LPUART0_POS                      2 /**< RST_LPUART0 Position */
+ #define MXC_F_MCR_RST_LPUART0                          ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */
+
+/**@} end of group MCR_RST_Register */
+
+/**
+ * @ingroup  mcr_registers
+ * @defgroup MCR_CLKDIS MCR_CLKDIS
+ * @brief    Low Power Peripheral Clock Disable.
+ * @{
+ */
+ #define MXC_F_MCR_CLKDIS_LPTMR0_POS                    0 /**< CLKDIS_LPTMR0 Position */
+ #define MXC_F_MCR_CLKDIS_LPTMR0                        ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR0_POS)) /**< CLKDIS_LPTMR0 Mask */
+
+ #define MXC_F_MCR_CLKDIS_LPTMR1_POS                    1 /**< CLKDIS_LPTMR1 Position */
+ #define MXC_F_MCR_CLKDIS_LPTMR1                        ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR1_POS)) /**< CLKDIS_LPTMR1 Mask */
+
+ #define MXC_F_MCR_CLKDIS_LPUART0_POS                   2 /**< CLKDIS_LPUART0 Position */
+ #define MXC_F_MCR_CLKDIS_LPUART0                       ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPUART0_POS)) /**< CLKDIS_LPUART0 Mask */
+
+/**@} end of group MCR_CLKDIS_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MCR_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h

@@ -0,0 +1,271 @@
+/**
+ * @file    pwrseq_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _PWRSEQ_REGS_H_
+#define _PWRSEQ_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     pwrseq
+ * @defgroup    pwrseq_registers PWRSEQ_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
+ * @details Power Sequencer / Low Power Control Register.
+ */
+
+/**
+ * @ingroup pwrseq_registers
+ * Structure type to access the PWRSEQ Registers.
+ */
+typedef struct {
+    __IO uint32_t lpcn;                 /**< <tt>\b 0x00:</tt> PWRSEQ LPCN Register */
+    __IO uint32_t lpwkst0;              /**< <tt>\b 0x04:</tt> PWRSEQ LPWKST0 Register */
+    __IO uint32_t lpwken0;              /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */
+    __IO uint32_t lpwkst1;              /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */
+    __IO uint32_t lpwken1;              /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */
+    __I  uint32_t rsv_0x14_0x2f[7];
+    __IO uint32_t lppwkst;              /**< <tt>\b 0x30:</tt> PWRSEQ LPPWKST Register */
+    __IO uint32_t lppwken;              /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */
+    __I  uint32_t rsv_0x38_0x3f[2];
+    __IO uint32_t lpmemsd;              /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
+} mxc_pwrseq_regs_t;
+
+/* Register offsets for module PWRSEQ */
+/**
+ * @ingroup    pwrseq_registers
+ * @defgroup   PWRSEQ_Register_Offsets Register Offsets
+ * @brief      PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_PWRSEQ_LPCN                  ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_PWRSEQ_LPWKST0               ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_PWRSEQ_LPWKEN0               ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_PWRSEQ_LPWKST1               ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_PWRSEQ_LPWKEN1               ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_PWRSEQ_LPPWKST               ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_PWRSEQ_LPPWKEN               ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_PWRSEQ_LPMEMSD               ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 
+/**@} end of group pwrseq_registers */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN
+ * @brief    Low Power Control Register.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS               0 /**< LPCN_RAM0RET_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) /**< LPCN_RAM0RET_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS               1 /**< LPCN_RAM1RET_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) /**< LPCN_RAM1RET_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS               2 /**< LPCN_RAM2RET_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) /**< LPCN_RAM2RET_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS               3 /**< LPCN_RAM3RET_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) /**< LPCN_RAM3RET_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_OVR_POS                      4 /**< LPCN_OVR Position */
+ #define MXC_F_PWRSEQ_LPCN_OVR                          ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */
+ #define MXC_V_PWRSEQ_LPCN_OVR_0_9V                     ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */
+ #define MXC_S_PWRSEQ_LPCN_OVR_0_9V                     (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */
+ #define MXC_V_PWRSEQ_LPCN_OVR_1_0V                     ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */
+ #define MXC_S_PWRSEQ_LPCN_OVR_1_0V                     (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */
+ #define MXC_V_PWRSEQ_LPCN_OVR_1_1V                     ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */
+ #define MXC_S_PWRSEQ_LPCN_OVR_1_1V                     (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */
+
+ #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS         6 /**< LPCN_VCORE_DET_BYPASS Position */
+ #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) /**< LPCN_VCORE_DET_BYPASS Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS                8 /**< LPCN_RETREG_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_RETREG_EN                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS               9 /**< LPCN_STORAGE_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_STORAGE_EN                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) /**< LPCN_STORAGE_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS                10 /**< LPCN_FASTWK_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_FASTWK_EN                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_BG_DIS_POS                   11 /**< LPCN_BG_DIS Position */
+ #define MXC_F_PWRSEQ_LPCN_BG_DIS                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS             12 /**< LPCN_VCOREPOR_DIS Position */
+ #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS                  16 /**< LPCN_LDO_DIS Position */
+ #define MXC_F_PWRSEQ_LPCN_LDO_DIS                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS                17 /**< LPCN_VCORE_EXT Position */
+ #define MXC_F_PWRSEQ_LPCN_VCORE_EXT                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) /**< LPCN_VCORE_EXT Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS             20 /**< LPCN_VCOREMON_DIS Position */
+ #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS              22 /**< LPCN_VDDAMON_DIS Position */
+ #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS            25 /**< LPCN_PORVDDMON_DIS Position */
+ #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS                ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) /**< LPCN_PORVDDMON_DIS Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_INRO_EN_POS                  28 /**< LPCN_INRO_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_INRO_EN                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) /**< LPCN_INRO_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS                 29 /**< LPCN_ERTCO_EN Position */
+ #define MXC_F_PWRSEQ_LPCN_ERTCO_EN                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS                30 /**< LPCN_TM_LPMODE Position */
+ #define MXC_F_PWRSEQ_LPCN_TM_LPMODE                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS)) /**< LPCN_TM_LPMODE Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS                31 /**< LPCN_TM_PWRSEQ Position */
+ #define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS)) /**< LPCN_TM_PWRSEQ Mask */
+
+/**@} end of group PWRSEQ_LPCN_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0
+ * @brief    Low Power I/O Wakeup Status Register 0. This register indicates the low power
+ *           wakeup status for GPIO0.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPWKST0_ST_POS                    0 /**< LPWKST0_ST Position */
+ #define MXC_F_PWRSEQ_LPWKST0_ST                        ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */
+
+/**@} end of group PWRSEQ_LPWKST0_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0
+ * @brief    Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup
+ *           functionality for GPIO0.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPWKEN0_EN_POS                    0 /**< LPWKEN0_EN Position */
+ #define MXC_F_PWRSEQ_LPWKEN0_EN                        ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */
+
+/**@} end of group PWRSEQ_LPWKEN0_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPPWKST PWRSEQ_LPPWKST
+ * @brief    Low Power Peripheral Wakeup Status Register.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS                0 /**< LPPWKST_LPTMR0 Position */
+ #define MXC_F_PWRSEQ_LPPWKST_LPTMR0                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS)) /**< LPPWKST_LPTMR0 Mask */
+
+ #define MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS                1 /**< LPPWKST_LPTMR1 Position */
+ #define MXC_F_PWRSEQ_LPPWKST_LPTMR1                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS)) /**< LPPWKST_LPTMR1 Mask */
+
+ #define MXC_F_PWRSEQ_LPPWKST_LPUART0_POS               2 /**< LPPWKST_LPUART0 Position */
+ #define MXC_F_PWRSEQ_LPPWKST_LPUART0                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPUART0_POS)) /**< LPPWKST_LPUART0 Mask */
+
+/**@} end of group PWRSEQ_LPPWKST_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPPWKEN PWRSEQ_LPPWKEN
+ * @brief    Low Power Peripheral Wakeup Enable Register.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS                0 /**< LPPWKEN_LPTMR0 Position */
+ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */
+
+ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS                1 /**< LPPWKEN_LPTMR1 Position */
+ #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS)) /**< LPPWKEN_LPTMR1 Mask */
+
+ #define MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS               2 /**< LPPWKEN_LPUART0 Position */
+ #define MXC_F_PWRSEQ_LPPWKEN_LPUART0                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS)) /**< LPPWKEN_LPUART0 Mask */
+
+/**@} end of group PWRSEQ_LPPWKEN_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD
+ * @brief    Low Power Memory Shutdown Control.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS                  0 /**< LPMEMSD_RAM0 Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM0                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */
+
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS                  1 /**< LPMEMSD_RAM1 Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM1                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */
+
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS                  2 /**< LPMEMSD_RAM2 Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM2                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */
+
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS                  3 /**< LPMEMSD_RAM3 Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_RAM3                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */
+
+/**@} end of group PWRSEQ_LPMEMSD_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PWRSEQ_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h

@@ -0,0 +1,241 @@
+/**
+ * @file    rtc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _RTC_REGS_H_
+#define _RTC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     rtc
+ * @defgroup    rtc_registers RTC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
+ * @details Real Time Clock and Alarm.
+ */
+
+/**
+ * @ingroup rtc_registers
+ * Structure type to access the RTC Registers.
+ */
+typedef struct {
+    __IO uint32_t sec;                  /**< <tt>\b 0x00:</tt> RTC SEC Register */
+    __IO uint32_t ssec;                 /**< <tt>\b 0x04:</tt> RTC SSEC Register */
+    __IO uint32_t toda;                 /**< <tt>\b 0x08:</tt> RTC TODA Register */
+    __IO uint32_t sseca;                /**< <tt>\b 0x0C:</tt> RTC SSECA Register */
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x10:</tt> RTC CTRL Register */
+    __IO uint32_t trim;                 /**< <tt>\b 0x14:</tt> RTC TRIM Register */
+    __IO uint32_t oscctrl;              /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
+} mxc_rtc_regs_t;
+
+/* Register offsets for module RTC */
+/**
+ * @ingroup    rtc_registers
+ * @defgroup   RTC_Register_Offsets Register Offsets
+ * @brief      RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_RTC_SEC                      ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_RTC_SSEC                     ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_RTC_TODA                     ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_RTC_SSECA                    ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_RTC_CTRL                     ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_RTC_TRIM                     ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_RTC_OSCCTRL                  ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ 
+/**@} end of group rtc_registers */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_SEC RTC_SEC
+ * @brief    RTC Second Counter. This register contains the 32-bit second counter.
+ * @{
+ */
+ #define MXC_F_RTC_SEC_SEC_POS                          0 /**< SEC_SEC Position */
+ #define MXC_F_RTC_SEC_SEC                              ((uint32_t)(0xFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */
+
+/**@} end of group RTC_SEC_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_SSEC RTC_SSEC
+ * @brief    RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented
+ *           when this register rolls over from 0xFF to 0x00.
+ * @{
+ */
+ #define MXC_F_RTC_SSEC_SSEC_POS                        0 /**< SSEC_SSEC Position */
+ #define MXC_F_RTC_SSEC_SSEC                            ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */
+
+/**@} end of group RTC_SSEC_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_TODA RTC_TODA
+ * @brief    Time-of-day Alarm.
+ * @{
+ */
+ #define MXC_F_RTC_TODA_TOD_ALARM_POS                   0 /**< TODA_TOD_ALARM Position */
+ #define MXC_F_RTC_TODA_TOD_ALARM                       ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */
+
+/**@} end of group RTC_TODA_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_SSECA RTC_SSECA
+ * @brief    RTC sub-second alarm.  This register contains the reload value for the sub-
+ *           second alarm.
+ * @{
+ */
+ #define MXC_F_RTC_SSECA_SSEC_ALARM_POS                 0 /**< SSECA_SSEC_ALARM Position */
+ #define MXC_F_RTC_SSECA_SSEC_ALARM                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */
+
+/**@} end of group RTC_SSECA_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_CTRL RTC_CTRL
+ * @brief    RTC Control Register.
+ * @{
+ */
+ #define MXC_F_RTC_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_RTC_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS                1 /**< CTRL_TOD_ALARM_IE Position */
+ #define MXC_F_RTC_CTRL_TOD_ALARM_IE                    ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */
+
+ #define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS               2 /**< CTRL_SSEC_ALARM_IE Position */
+ #define MXC_F_RTC_CTRL_SSEC_ALARM_IE                   ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */
+
+ #define MXC_F_RTC_CTRL_BUSY_POS                        3 /**< CTRL_BUSY Position */
+ #define MXC_F_RTC_CTRL_BUSY                            ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
+
+ #define MXC_F_RTC_CTRL_RDY_POS                         4 /**< CTRL_RDY Position */
+ #define MXC_F_RTC_CTRL_RDY                             ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
+
+ #define MXC_F_RTC_CTRL_RDY_IE_POS                      5 /**< CTRL_RDY_IE Position */
+ #define MXC_F_RTC_CTRL_RDY_IE                          ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */
+
+ #define MXC_F_RTC_CTRL_TOD_ALARM_POS                   6 /**< CTRL_TOD_ALARM Position */
+ #define MXC_F_RTC_CTRL_TOD_ALARM                       ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */
+
+ #define MXC_F_RTC_CTRL_SSEC_ALARM_POS                  7 /**< CTRL_SSEC_ALARM Position */
+ #define MXC_F_RTC_CTRL_SSEC_ALARM                      ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */
+
+ #define MXC_F_RTC_CTRL_SQW_EN_POS                      8 /**< CTRL_SQW_EN Position */
+ #define MXC_F_RTC_CTRL_SQW_EN                          ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */
+
+ #define MXC_F_RTC_CTRL_SQW_SEL_POS                     9 /**< CTRL_SQW_SEL Position */
+ #define MXC_F_RTC_CTRL_SQW_SEL                         ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */
+ #define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ                 ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */
+ #define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ                 (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */
+ #define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ               ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */
+ #define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ               (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */
+ #define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ                ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */
+ #define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ                (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */
+ #define MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8                 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */
+ #define MXC_S_RTC_CTRL_SQW_SEL_CLKDIV8                 (MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */
+
+ #define MXC_F_RTC_CTRL_RD_EN_POS                       14 /**< CTRL_RD_EN Position */
+ #define MXC_F_RTC_CTRL_RD_EN                           ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */
+
+ #define MXC_F_RTC_CTRL_WR_EN_POS                       15 /**< CTRL_WR_EN Position */
+ #define MXC_F_RTC_CTRL_WR_EN                           ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */
+
+/**@} end of group RTC_CTRL_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_TRIM RTC_TRIM
+ * @brief    RTC Trim Register.
+ * @{
+ */
+ #define MXC_F_RTC_TRIM_TRIM_POS                        0 /**< TRIM_TRIM Position */
+ #define MXC_F_RTC_TRIM_TRIM                            ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
+
+ #define MXC_F_RTC_TRIM_VRTC_TMR_POS                    8 /**< TRIM_VRTC_TMR Position */
+ #define MXC_F_RTC_TRIM_VRTC_TMR                        ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */
+
+/**@} end of group RTC_TRIM_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_OSCCTRL RTC_OSCCTRL
+ * @brief    RTC Oscillator Control Register.
+ * @{
+ */
+ #define MXC_F_RTC_OSCCTRL_BYPASS_POS                   4 /**< OSCCTRL_BYPASS Position */
+ #define MXC_F_RTC_OSCCTRL_BYPASS                       ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
+
+ #define MXC_F_RTC_OSCCTRL_SQW_32K_POS                  5 /**< OSCCTRL_SQW_32K Position */
+ #define MXC_F_RTC_OSCCTRL_SQW_32K                      ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */
+
+/**@} end of group RTC_OSCCTRL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTC_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h

@@ -0,0 +1,132 @@
+/**
+ * @file    sir_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _SIR_REGS_H_
+#define _SIR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     sir
+ * @defgroup    sir_registers SIR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
+ * @details System Initialization Registers.
+ */
+
+/**
+ * @ingroup sir_registers
+ * Structure type to access the SIR Registers.
+ */
+typedef struct {
+    __I  uint32_t sir_status;           /**< <tt>\b 0x00:</tt> SIR SIR_STATUS Register */
+    __I  uint32_t sir_addr;             /**< <tt>\b 0x04:</tt> SIR SIR_ADDR Register */
+} mxc_sir_regs_t;
+
+/* Register offsets for module SIR */
+/**
+ * @ingroup    sir_registers
+ * @defgroup   SIR_Register_Offsets Register Offsets
+ * @brief      SIR Peripheral Register Offsets from the SIR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_SIR_SIR_STATUS               ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SIR_SIR_ADDR                 ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */ 
+/**@} end of group sir_registers */
+
+/**
+ * @ingroup  sir_registers
+ * @defgroup SIR_SIR_STATUS SIR_SIR_STATUS
+ * @brief    System Initialization Status Register.
+ * @{
+ */
+ #define MXC_F_SIR_SIR_STATUS_CFG_VALID_POS             0 /**< SIR_STATUS_CFG_VALID Position */
+ #define MXC_F_SIR_SIR_STATUS_CFG_VALID                 ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_VALID_POS)) /**< SIR_STATUS_CFG_VALID Mask */
+
+ #define MXC_F_SIR_SIR_STATUS_CFG_ERR_POS               1 /**< SIR_STATUS_CFG_ERR Position */
+ #define MXC_F_SIR_SIR_STATUS_CFG_ERR                   ((uint32_t)(0x1UL << MXC_F_SIR_SIR_STATUS_CFG_ERR_POS)) /**< SIR_STATUS_CFG_ERR Mask */
+
+/**@} end of group SIR_SIR_STATUS_Register */
+
+/**
+ * @ingroup  sir_registers
+ * @defgroup SIR_SIR_ADDR SIR_SIR_ADDR
+ * @brief    Read-only field set by the SIB block if a CRC error occurs during the read of
+ *           the OTP memory. Contains the failing address in OTP memory (when CRCERR equals
+ *           1).
+ * @{
+ */
+ #define MXC_F_SIR_SIR_ADDR_ADDR_POS                    0 /**< SIR_ADDR_ADDR Position */
+ #define MXC_F_SIR_SIR_ADDR_ADDR                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_SIR_ADDR_ADDR_POS)) /**< SIR_ADDR_ADDR Mask */
+
+/**@} end of group SIR_SIR_ADDR_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SIR_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h

@@ -0,0 +1,483 @@
+/**
+ * @file    spi_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _SPI_REGS_H_
+#define _SPI_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     spi
+ * @defgroup    spi_registers SPI_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.
+ * @details SPI peripheral.
+ */
+
+/**
+ * @ingroup spi_registers
+ * Structure type to access the SPI Registers.
+ */
+typedef struct {
+  union{
+    __IO uint32_t fifo32;               /**< <tt>\b 0x00:</tt> SPI FIFO32 Register */
+    __IO uint16_t fifo16[2];            /**< <tt>\b 0x00:</tt> SPI FIFO16 Register */
+    __IO uint8_t  fifo8[4];             /**< <tt>\b 0x00:</tt> SPI FIFO8 Register */
+  };
+    __IO uint32_t ctrl0;                /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */
+    __IO uint32_t ctrl1;                /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */
+    __IO uint32_t ctrl2;                /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
+    __IO uint32_t sstime;               /**< <tt>\b 0x10:</tt> SPI SSTIME Register */
+    __IO uint32_t clkctrl;              /**< <tt>\b 0x14:</tt> SPI CLKCTRL Register */
+    __I  uint32_t rsv_0x18;
+    __IO uint32_t dma;                  /**< <tt>\b 0x1C:</tt> SPI DMA Register */
+    __IO uint32_t intfl;                /**< <tt>\b 0x20:</tt> SPI INTFL Register */
+    __IO uint32_t inten;                /**< <tt>\b 0x24:</tt> SPI INTEN Register */
+    __IO uint32_t wkfl;                 /**< <tt>\b 0x28:</tt> SPI WKFL Register */
+    __IO uint32_t wken;                 /**< <tt>\b 0x2C:</tt> SPI WKEN Register */
+    __I  uint32_t stat;                 /**< <tt>\b 0x30:</tt> SPI STAT Register */
+} mxc_spi_regs_t;
+
+/* Register offsets for module SPI */
+/**
+ * @ingroup    spi_registers
+ * @defgroup   SPI_Register_Offsets Register Offsets
+ * @brief      SPI Peripheral Register Offsets from the SPI Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_SPI_FIFO32                   ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPI_FIFO16                   ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPI_FIFO8                    ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPI_CTRL0                    ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_SPI_CTRL1                    ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_SPI_CTRL2                    ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_SPI_SSTIME                   ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_SPI_CLKCTRL                  ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_SPI_DMA                      ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_SPI_INTFL                    ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_SPI_INTEN                    ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_SPI_WKFL                     ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_SPI_WKEN                     ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_SPI_STAT                     ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */ 
+/**@} end of group spi_registers */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_FIFO32 SPI_FIFO32
+ * @brief    Register for reading and writing the FIFO.
+ * @{
+ */
+ #define MXC_F_SPI_FIFO32_DATA_POS                      0 /**< FIFO32_DATA Position */
+ #define MXC_F_SPI_FIFO32_DATA                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */
+
+/**@} end of group SPI_FIFO32_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_FIFO16 SPI_FIFO16
+ * @brief    Register for reading and writing the FIFO.
+ * @{
+ */
+ #define MXC_F_SPI_FIFO16_DATA_POS                      0 /**< FIFO16_DATA Position */
+ #define MXC_F_SPI_FIFO16_DATA                          ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */
+
+/**@} end of group SPI_FIFO16_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_FIFO8 SPI_FIFO8
+ * @brief    Register for reading and writing the FIFO.
+ * @{
+ */
+ #define MXC_F_SPI_FIFO8_DATA_POS                       0 /**< FIFO8_DATA Position */
+ #define MXC_F_SPI_FIFO8_DATA                           ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */
+
+/**@} end of group SPI_FIFO8_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_CTRL0 SPI_CTRL0
+ * @brief    Register for controlling SPI peripheral.
+ * @{
+ */
+ #define MXC_F_SPI_CTRL0_EN_POS                         0 /**< CTRL0_EN Position */
+ #define MXC_F_SPI_CTRL0_EN                             ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */
+
+ #define MXC_F_SPI_CTRL0_MST_MODE_POS                   1 /**< CTRL0_MST_MODE Position */
+ #define MXC_F_SPI_CTRL0_MST_MODE                       ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */
+
+ #define MXC_F_SPI_CTRL0_SS_IO_POS                      4 /**< CTRL0_SS_IO Position */
+ #define MXC_F_SPI_CTRL0_SS_IO                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
+
+ #define MXC_F_SPI_CTRL0_START_POS                      5 /**< CTRL0_START Position */
+ #define MXC_F_SPI_CTRL0_START                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */
+
+ #define MXC_F_SPI_CTRL0_SS_CTRL_POS                    8 /**< CTRL0_SS_CTRL Position */
+ #define MXC_F_SPI_CTRL0_SS_CTRL                        ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
+
+ #define MXC_F_SPI_CTRL0_SS_ACTIVE_POS                  16 /**< CTRL0_SS_ACTIVE Position */
+ #define MXC_F_SPI_CTRL0_SS_ACTIVE                      ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */
+ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0                  ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */
+ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0                  (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */
+ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1                  ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */
+ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1                  (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */
+ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2                  ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */
+ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2                  (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */
+ #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3                  ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */
+ #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3                  (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */
+
+/**@} end of group SPI_CTRL0_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_CTRL1 SPI_CTRL1
+ * @brief    Register for controlling SPI peripheral.
+ * @{
+ */
+ #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS                0 /**< CTRL1_TX_NUM_CHAR Position */
+ #define MXC_F_SPI_CTRL1_TX_NUM_CHAR                    ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
+
+ #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS                16 /**< CTRL1_RX_NUM_CHAR Position */
+ #define MXC_F_SPI_CTRL1_RX_NUM_CHAR                    ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
+
+/**@} end of group SPI_CTRL1_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_CTRL2 SPI_CTRL2
+ * @brief    Register for controlling SPI peripheral.
+ * @{
+ */
+ #define MXC_F_SPI_CTRL2_CLKPHA_POS                     0 /**< CTRL2_CLKPHA Position */
+ #define MXC_F_SPI_CTRL2_CLKPHA                         ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */
+
+ #define MXC_F_SPI_CTRL2_CLKPOL_POS                     1 /**< CTRL2_CLKPOL Position */
+ #define MXC_F_SPI_CTRL2_CLKPOL                         ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */
+
+ #define MXC_F_SPI_CTRL2_NUMBITS_POS                    8 /**< CTRL2_NUMBITS Position */
+ #define MXC_F_SPI_CTRL2_NUMBITS                        ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */
+ #define MXC_V_SPI_CTRL2_NUMBITS_0                      ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */
+ #define MXC_S_SPI_CTRL2_NUMBITS_0                      (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */
+
+ #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS                 12 /**< CTRL2_DATA_WIDTH Position */
+ #define MXC_F_SPI_CTRL2_DATA_WIDTH                     ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
+ #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO                ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
+ #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO                (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
+ #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL                ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
+ #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL                (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
+ #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD                ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
+ #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD                (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
+
+ #define MXC_F_SPI_CTRL2_THREE_WIRE_POS                 15 /**< CTRL2_THREE_WIRE Position */
+ #define MXC_F_SPI_CTRL2_THREE_WIRE                     ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
+
+ #define MXC_F_SPI_CTRL2_SS_POL_POS                     16 /**< CTRL2_SS_POL Position */
+ #define MXC_F_SPI_CTRL2_SS_POL                         ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
+ #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH                ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */
+ #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */
+ #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH                ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */
+ #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */
+ #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH                ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */
+ #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */
+ #define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH                ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */
+ #define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */
+
+/**@} end of group SPI_CTRL2_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_SSTIME SPI_SSTIME
+ * @brief    Register for controlling SPI peripheral/Slave Select Timing.
+ * @{
+ */
+ #define MXC_F_SPI_SSTIME_PRE_POS                       0 /**< SSTIME_PRE Position */
+ #define MXC_F_SPI_SSTIME_PRE                           ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */
+ #define MXC_V_SPI_SSTIME_PRE_256                       ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */
+ #define MXC_S_SPI_SSTIME_PRE_256                       (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */
+
+ #define MXC_F_SPI_SSTIME_POST_POS                      8 /**< SSTIME_POST Position */
+ #define MXC_F_SPI_SSTIME_POST                          ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */
+ #define MXC_V_SPI_SSTIME_POST_256                      ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */
+ #define MXC_S_SPI_SSTIME_POST_256                      (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */
+
+ #define MXC_F_SPI_SSTIME_INACT_POS                     16 /**< SSTIME_INACT Position */
+ #define MXC_F_SPI_SSTIME_INACT                         ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */
+ #define MXC_V_SPI_SSTIME_INACT_256                     ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */
+ #define MXC_S_SPI_SSTIME_INACT_256                     (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */
+
+/**@} end of group SPI_SSTIME_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_CLKCTRL SPI_CLKCTRL
+ * @brief    Register for controlling SPI clock rate.
+ * @{
+ */
+ #define MXC_F_SPI_CLKCTRL_LO_POS                       0 /**< CLKCTRL_LO Position */
+ #define MXC_F_SPI_CLKCTRL_LO                           ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */
+ #define MXC_V_SPI_CLKCTRL_LO_DIS                       ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */
+ #define MXC_S_SPI_CLKCTRL_LO_DIS                       (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */
+
+ #define MXC_F_SPI_CLKCTRL_HI_POS                       8 /**< CLKCTRL_HI Position */
+ #define MXC_F_SPI_CLKCTRL_HI                           ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */
+ #define MXC_V_SPI_CLKCTRL_HI_DIS                       ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */
+ #define MXC_S_SPI_CLKCTRL_HI_DIS                       (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */
+
+ #define MXC_F_SPI_CLKCTRL_CLKDIV_POS                   16 /**< CLKCTRL_CLKDIV Position */
+ #define MXC_F_SPI_CLKCTRL_CLKDIV                       ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */
+
+/**@} end of group SPI_CLKCTRL_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_DMA SPI_DMA
+ * @brief    Register for controlling DMA.
+ * @{
+ */
+ #define MXC_F_SPI_DMA_TX_THD_VAL_POS                   0 /**< DMA_TX_THD_VAL Position */
+ #define MXC_F_SPI_DMA_TX_THD_VAL                       ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */
+
+ #define MXC_F_SPI_DMA_TX_FIFO_EN_POS                   6 /**< DMA_TX_FIFO_EN Position */
+ #define MXC_F_SPI_DMA_TX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
+
+ #define MXC_F_SPI_DMA_TX_FLUSH_POS                     7 /**< DMA_TX_FLUSH Position */
+ #define MXC_F_SPI_DMA_TX_FLUSH                         ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */
+
+ #define MXC_F_SPI_DMA_TX_LVL_POS                       8 /**< DMA_TX_LVL Position */
+ #define MXC_F_SPI_DMA_TX_LVL                           ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */
+
+ #define MXC_F_SPI_DMA_DMA_TX_EN_POS                    15 /**< DMA_DMA_TX_EN Position */
+ #define MXC_F_SPI_DMA_DMA_TX_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */
+
+ #define MXC_F_SPI_DMA_RX_THD_VAL_POS                   16 /**< DMA_RX_THD_VAL Position */
+ #define MXC_F_SPI_DMA_RX_THD_VAL                       ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */
+
+ #define MXC_F_SPI_DMA_RX_FIFO_EN_POS                   22 /**< DMA_RX_FIFO_EN Position */
+ #define MXC_F_SPI_DMA_RX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
+
+ #define MXC_F_SPI_DMA_RX_FLUSH_POS                     23 /**< DMA_RX_FLUSH Position */
+ #define MXC_F_SPI_DMA_RX_FLUSH                         ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */
+
+ #define MXC_F_SPI_DMA_RX_LVL_POS                       24 /**< DMA_RX_LVL Position */
+ #define MXC_F_SPI_DMA_RX_LVL                           ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */
+
+ #define MXC_F_SPI_DMA_DMA_RX_EN_POS                    31 /**< DMA_DMA_RX_EN Position */
+ #define MXC_F_SPI_DMA_DMA_RX_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */
+
+/**@} end of group SPI_DMA_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_INTFL SPI_INTFL
+ * @brief    Register for reading and clearing interrupt flags. All bits are write 1 to
+ *           clear.
+ * @{
+ */
+ #define MXC_F_SPI_INTFL_TX_THD_POS                     0 /**< INTFL_TX_THD Position */
+ #define MXC_F_SPI_INTFL_TX_THD                         ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */
+
+ #define MXC_F_SPI_INTFL_TX_EM_POS                      1 /**< INTFL_TX_EM Position */
+ #define MXC_F_SPI_INTFL_TX_EM                          ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */
+
+ #define MXC_F_SPI_INTFL_RX_THD_POS                     2 /**< INTFL_RX_THD Position */
+ #define MXC_F_SPI_INTFL_RX_THD                         ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */
+
+ #define MXC_F_SPI_INTFL_RX_FULL_POS                    3 /**< INTFL_RX_FULL Position */
+ #define MXC_F_SPI_INTFL_RX_FULL                        ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */
+
+ #define MXC_F_SPI_INTFL_SSA_POS                        4 /**< INTFL_SSA Position */
+ #define MXC_F_SPI_INTFL_SSA                            ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */
+
+ #define MXC_F_SPI_INTFL_SSD_POS                        5 /**< INTFL_SSD Position */
+ #define MXC_F_SPI_INTFL_SSD                            ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */
+
+ #define MXC_F_SPI_INTFL_FAULT_POS                      8 /**< INTFL_FAULT Position */
+ #define MXC_F_SPI_INTFL_FAULT                          ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */
+
+ #define MXC_F_SPI_INTFL_ABORT_POS                      9 /**< INTFL_ABORT Position */
+ #define MXC_F_SPI_INTFL_ABORT                          ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */
+
+ #define MXC_F_SPI_INTFL_MST_DONE_POS                   11 /**< INTFL_MST_DONE Position */
+ #define MXC_F_SPI_INTFL_MST_DONE                       ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */
+
+ #define MXC_F_SPI_INTFL_TX_OV_POS                      12 /**< INTFL_TX_OV Position */
+ #define MXC_F_SPI_INTFL_TX_OV                          ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */
+
+ #define MXC_F_SPI_INTFL_TX_UN_POS                      13 /**< INTFL_TX_UN Position */
+ #define MXC_F_SPI_INTFL_TX_UN                          ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */
+
+ #define MXC_F_SPI_INTFL_RX_OV_POS                      14 /**< INTFL_RX_OV Position */
+ #define MXC_F_SPI_INTFL_RX_OV                          ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */
+
+ #define MXC_F_SPI_INTFL_RX_UN_POS                      15 /**< INTFL_RX_UN Position */
+ #define MXC_F_SPI_INTFL_RX_UN                          ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */
+
+/**@} end of group SPI_INTFL_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_INTEN SPI_INTEN
+ * @brief    Register for enabling interrupts.
+ * @{
+ */
+ #define MXC_F_SPI_INTEN_TX_THD_POS                     0 /**< INTEN_TX_THD Position */
+ #define MXC_F_SPI_INTEN_TX_THD                         ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */
+
+ #define MXC_F_SPI_INTEN_TX_EM_POS                      1 /**< INTEN_TX_EM Position */
+ #define MXC_F_SPI_INTEN_TX_EM                          ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */
+
+ #define MXC_F_SPI_INTEN_RX_THD_POS                     2 /**< INTEN_RX_THD Position */
+ #define MXC_F_SPI_INTEN_RX_THD                         ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */
+
+ #define MXC_F_SPI_INTEN_RX_FULL_POS                    3 /**< INTEN_RX_FULL Position */
+ #define MXC_F_SPI_INTEN_RX_FULL                        ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */
+
+ #define MXC_F_SPI_INTEN_SSA_POS                        4 /**< INTEN_SSA Position */
+ #define MXC_F_SPI_INTEN_SSA                            ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */
+
+ #define MXC_F_SPI_INTEN_SSD_POS                        5 /**< INTEN_SSD Position */
+ #define MXC_F_SPI_INTEN_SSD                            ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */
+
+ #define MXC_F_SPI_INTEN_FAULT_POS                      8 /**< INTEN_FAULT Position */
+ #define MXC_F_SPI_INTEN_FAULT                          ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */
+
+ #define MXC_F_SPI_INTEN_ABORT_POS                      9 /**< INTEN_ABORT Position */
+ #define MXC_F_SPI_INTEN_ABORT                          ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */
+
+ #define MXC_F_SPI_INTEN_MST_DONE_POS                   11 /**< INTEN_MST_DONE Position */
+ #define MXC_F_SPI_INTEN_MST_DONE                       ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */
+
+ #define MXC_F_SPI_INTEN_TX_OV_POS                      12 /**< INTEN_TX_OV Position */
+ #define MXC_F_SPI_INTEN_TX_OV                          ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */
+
+ #define MXC_F_SPI_INTEN_TX_UN_POS                      13 /**< INTEN_TX_UN Position */
+ #define MXC_F_SPI_INTEN_TX_UN                          ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */
+
+ #define MXC_F_SPI_INTEN_RX_OV_POS                      14 /**< INTEN_RX_OV Position */
+ #define MXC_F_SPI_INTEN_RX_OV                          ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */
+
+ #define MXC_F_SPI_INTEN_RX_UN_POS                      15 /**< INTEN_RX_UN Position */
+ #define MXC_F_SPI_INTEN_RX_UN                          ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */
+
+/**@} end of group SPI_INTEN_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_WKFL SPI_WKFL
+ * @brief    Register for wake up flags. All bits in this register are write 1 to clear.
+ * @{
+ */
+ #define MXC_F_SPI_WKFL_TX_THD_POS                      0 /**< WKFL_TX_THD Position */
+ #define MXC_F_SPI_WKFL_TX_THD                          ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */
+
+ #define MXC_F_SPI_WKFL_TX_EM_POS                       1 /**< WKFL_TX_EM Position */
+ #define MXC_F_SPI_WKFL_TX_EM                           ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */
+
+ #define MXC_F_SPI_WKFL_RX_THD_POS                      2 /**< WKFL_RX_THD Position */
+ #define MXC_F_SPI_WKFL_RX_THD                          ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */
+
+ #define MXC_F_SPI_WKFL_RX_FULL_POS                     3 /**< WKFL_RX_FULL Position */
+ #define MXC_F_SPI_WKFL_RX_FULL                         ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */
+
+/**@} end of group SPI_WKFL_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_WKEN SPI_WKEN
+ * @brief    Register for wake up enable.
+ * @{
+ */
+ #define MXC_F_SPI_WKEN_TX_THD_POS                      0 /**< WKEN_TX_THD Position */
+ #define MXC_F_SPI_WKEN_TX_THD                          ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */
+
+ #define MXC_F_SPI_WKEN_TX_EM_POS                       1 /**< WKEN_TX_EM Position */
+ #define MXC_F_SPI_WKEN_TX_EM                           ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */
+
+ #define MXC_F_SPI_WKEN_RX_THD_POS                      2 /**< WKEN_RX_THD Position */
+ #define MXC_F_SPI_WKEN_RX_THD                          ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */
+
+ #define MXC_F_SPI_WKEN_RX_FULL_POS                     3 /**< WKEN_RX_FULL Position */
+ #define MXC_F_SPI_WKEN_RX_FULL                         ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */
+
+/**@} end of group SPI_WKEN_Register */
+
+/**
+ * @ingroup  spi_registers
+ * @defgroup SPI_STAT SPI_STAT
+ * @brief    SPI Status register.
+ * @{
+ */
+ #define MXC_F_SPI_STAT_BUSY_POS                        0 /**< STAT_BUSY Position */
+ #define MXC_F_SPI_STAT_BUSY                            ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
+
+/**@} end of group SPI_STAT_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPI_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/system_max32670.h

@@ -0,0 +1,114 @@
+/*******************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _SYSTEM_MAX32670_H_
+#define _SYSTEM_MAX32670_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+/* NOTE: HIRC was previously named CRYPTO */
+#ifdef CRYPTO_FREQ
+#warning WARNING: CRYPTO_FREQ does not exist in MAX32670, replace with HIRC_FREQ!
+#define HIRC_FREQ CRYPTO_FREQ
+#endif
+
+/* NOTE: EXTCLK needs to be defined by user based on the clock they supply */
+#ifndef EXTCLK_FREQ
+#define EXTCLK_FREQ               75000000
+#endif
+
+/* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip. 
+         Update if use of this oscillator requires precise timing.*/
+/* NOTE: INRO was previously named NANORING */
+#ifndef INRO_FREQ
+#define INRO_FREQ                 80000
+#endif
+//NOTE: IPO clock bit is documented as 96MHz, but SR says this will be 100.
+#ifndef IPO_FREQ
+#define IPO_FREQ                  100000000
+#endif
+
+#ifndef IBRO_FREQ
+#define IBRO_FREQ                 7372800
+#endif
+
+/* NOTE: ERFO_FREQ (16MHz-32MHz) needs to be defined by user based on the clock they supply */
+#ifndef ERFO_FREQ
+#define ERFO_FREQ                 32000000
+#endif
+
+#ifndef ERTCO_FREQ
+#define ERTCO_FREQ                32768
+#endif
+	
+#ifndef HIRC_FREQ
+#define HIRC_FREQ                 IPO_FREQ
+#endif
+
+extern uint32_t SystemCoreClock;                            /*!< System Clock Frequency (Core Clock)  */
+#ifdef PeripheralClock
+#warning PeripheralClock define is being overidden.
+#else
+#define         PeripheralClock     (SystemCoreClock /2)    /*!< Peripheral Clock Frequency */
+#endif
+
+/*
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/*
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MAX32670_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h

@@ -0,0 +1,441 @@
+/**
+ * @file    tmr_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _TMR_REGS_H_
+#define _TMR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     tmr
+ * @defgroup    tmr_registers TMR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
+ * @details Low-Power Configurable Timer
+ */
+
+/**
+ * @ingroup tmr_registers
+ * Structure type to access the TMR Registers.
+ */
+typedef struct {
+    __IO uint32_t cnt;                  /**< <tt>\b 0x00:</tt> TMR CNT Register */
+    __IO uint32_t cmp;                  /**< <tt>\b 0x04:</tt> TMR CMP Register */
+    __IO uint32_t pwm;                  /**< <tt>\b 0x08:</tt> TMR PWM Register */
+    __IO uint32_t intfl;                /**< <tt>\b 0x0C:</tt> TMR INTFL Register */
+    __IO uint32_t ctrl0;                /**< <tt>\b 0x10:</tt> TMR CTRL0 Register */
+    __IO uint32_t nolcmp;               /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */
+    __IO uint32_t ctrl1;                /**< <tt>\b 0x18:</tt> TMR CTRL1 Register */
+    __IO uint32_t wkfl;                 /**< <tt>\b 0x1C:</tt> TMR WKFL Register */
+} mxc_tmr_regs_t;
+
+/* Register offsets for module TMR */
+/**
+ * @ingroup    tmr_registers
+ * @defgroup   TMR_Register_Offsets Register Offsets
+ * @brief      TMR Peripheral Register Offsets from the TMR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_TMR_CNT                      ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_TMR_CMP                      ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_TMR_PWM                      ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_TMR_INTFL                    ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_TMR_CTRL0                    ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_TMR_NOLCMP                   ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_TMR_CTRL1                    ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_TMR_WKFL                     ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: <tt> 0x001C</tt> */ 
+/**@} end of group tmr_registers */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_CNT TMR_CNT
+ * @brief    Timer Counter Register.
+ * @{
+ */
+ #define MXC_F_TMR_CNT_COUNT_POS                        0 /**< CNT_COUNT Position */
+ #define MXC_F_TMR_CNT_COUNT                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
+
+/**@} end of group TMR_CNT_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_CMP TMR_CMP
+ * @brief    Timer Compare Register.
+ * @{
+ */
+ #define MXC_F_TMR_CMP_COMPARE_POS                      0 /**< CMP_COMPARE Position */
+ #define MXC_F_TMR_CMP_COMPARE                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */
+
+/**@} end of group TMR_CMP_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_PWM TMR_PWM
+ * @brief    Timer PWM Register.
+ * @{
+ */
+ #define MXC_F_TMR_PWM_PWM_POS                          0 /**< PWM_PWM Position */
+ #define MXC_F_TMR_PWM_PWM                              ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */
+
+/**@} end of group TMR_PWM_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_INTFL TMR_INTFL
+ * @brief    Timer Interrupt Status Register.
+ * @{
+ */
+ #define MXC_F_TMR_INTFL_IRQ_A_POS                      0 /**< INTFL_IRQ_A Position */
+ #define MXC_F_TMR_INTFL_IRQ_A                          ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */
+
+ #define MXC_F_TMR_INTFL_WRDONE_A_POS                   8 /**< INTFL_WRDONE_A Position */
+ #define MXC_F_TMR_INTFL_WRDONE_A                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */
+
+ #define MXC_F_TMR_INTFL_WR_DIS_A_POS                   9 /**< INTFL_WR_DIS_A Position */
+ #define MXC_F_TMR_INTFL_WR_DIS_A                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */
+
+ #define MXC_F_TMR_INTFL_IRQ_B_POS                      16 /**< INTFL_IRQ_B Position */
+ #define MXC_F_TMR_INTFL_IRQ_B                          ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */
+
+ #define MXC_F_TMR_INTFL_WRDONE_B_POS                   24 /**< INTFL_WRDONE_B Position */
+ #define MXC_F_TMR_INTFL_WRDONE_B                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */
+
+ #define MXC_F_TMR_INTFL_WR_DIS_B_POS                   25 /**< INTFL_WR_DIS_B Position */
+ #define MXC_F_TMR_INTFL_WR_DIS_B                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */
+
+/**@} end of group TMR_INTFL_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_CTRL0 TMR_CTRL0
+ * @brief    Timer Control Register.
+ * @{
+ */
+ #define MXC_F_TMR_CTRL0_MODE_A_POS                     0 /**< CTRL0_MODE_A Position */
+ #define MXC_F_TMR_CTRL0_MODE_A                         ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */
+ #define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT                ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT                (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS              ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS              (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_COUNTER                 ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_COUNTER                 (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_PWM                     ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_PWM                     (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_CAPTURE                 ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_CAPTURE                 (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_COMPARE                 ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_COMPARE                 (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_GATED                   ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_GATED                   (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP                 ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP                 (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE               ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE               (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */
+ #define MXC_V_TMR_CTRL0_MODE_A_IGATED                  ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */
+ #define MXC_S_TMR_CTRL0_MODE_A_IGATED                  (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */
+
+ #define MXC_F_TMR_CTRL0_CLKDIV_A_POS                   4 /**< CTRL0_CLKDIV_A Position */
+ #define MXC_F_TMR_CTRL0_CLKDIV_A                       ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1              ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2              ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4              ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8              ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16             ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16             (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32             ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32             (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64             ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64             (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128            ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128            (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256            ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256            (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512            ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512            (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024           ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024           (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048           ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048           (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096           ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096           (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */
+
+ #define MXC_F_TMR_CTRL0_POL_A_POS                      8 /**< CTRL0_POL_A Position */
+ #define MXC_F_TMR_CTRL0_POL_A                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */
+
+ #define MXC_F_TMR_CTRL0_PWMSYNC_A_POS                  9 /**< CTRL0_PWMSYNC_A Position */
+ #define MXC_F_TMR_CTRL0_PWMSYNC_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */
+
+ #define MXC_F_TMR_CTRL0_NOLHPOL_A_POS                  10 /**< CTRL0_NOLHPOL_A Position */
+ #define MXC_F_TMR_CTRL0_NOLHPOL_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */
+
+ #define MXC_F_TMR_CTRL0_NOLLPOL_A_POS                  11 /**< CTRL0_NOLLPOL_A Position */
+ #define MXC_F_TMR_CTRL0_NOLLPOL_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */
+
+ #define MXC_F_TMR_CTRL0_PWMCKBD_A_POS                  12 /**< CTRL0_PWMCKBD_A Position */
+ #define MXC_F_TMR_CTRL0_PWMCKBD_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */
+
+ #define MXC_F_TMR_CTRL0_RST_A_POS                      13 /**< CTRL0_RST_A Position */
+ #define MXC_F_TMR_CTRL0_RST_A                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */
+
+ #define MXC_F_TMR_CTRL0_CLKEN_A_POS                    14 /**< CTRL0_CLKEN_A Position */
+ #define MXC_F_TMR_CTRL0_CLKEN_A                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */
+
+ #define MXC_F_TMR_CTRL0_EN_A_POS                       15 /**< CTRL0_EN_A Position */
+ #define MXC_F_TMR_CTRL0_EN_A                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */
+
+ #define MXC_F_TMR_CTRL0_MODE_B_POS                     16 /**< CTRL0_MODE_B Position */
+ #define MXC_F_TMR_CTRL0_MODE_B                         ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */
+ #define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT                ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT                (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS              ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS              (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_COUNTER                 ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_COUNTER                 (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_PWM                     ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_PWM                     (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_CAPTURE                 ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_CAPTURE                 (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_COMPARE                 ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_COMPARE                 (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_GATED                   ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_GATED                   (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP                 ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP                 (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE               ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE               (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */
+ #define MXC_V_TMR_CTRL0_MODE_B_IGATED                  ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */
+ #define MXC_S_TMR_CTRL0_MODE_B_IGATED                  (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */
+
+ #define MXC_F_TMR_CTRL0_CLKDIV_B_POS                   20 /**< CTRL0_CLKDIV_B Position */
+ #define MXC_F_TMR_CTRL0_CLKDIV_B                       ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1              ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2              ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4              ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8              ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16             ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16             (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32             ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32             (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64             ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64             (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128            ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128            (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256            ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256            (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512            ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512            (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024           ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024           (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048           ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048           (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */
+ #define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096           ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */
+ #define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096           (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */
+
+ #define MXC_F_TMR_CTRL0_POL_B_POS                      24 /**< CTRL0_POL_B Position */
+ #define MXC_F_TMR_CTRL0_POL_B                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */
+
+ #define MXC_F_TMR_CTRL0_PWMSYNC_B_POS                  25 /**< CTRL0_PWMSYNC_B Position */
+ #define MXC_F_TMR_CTRL0_PWMSYNC_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */
+
+ #define MXC_F_TMR_CTRL0_NOLHPOL_B_POS                  26 /**< CTRL0_NOLHPOL_B Position */
+ #define MXC_F_TMR_CTRL0_NOLHPOL_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */
+
+ #define MXC_F_TMR_CTRL0_NOLLPOL_B_POS                  27 /**< CTRL0_NOLLPOL_B Position */
+ #define MXC_F_TMR_CTRL0_NOLLPOL_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */
+
+ #define MXC_F_TMR_CTRL0_PWMCKBD_B_POS                  28 /**< CTRL0_PWMCKBD_B Position */
+ #define MXC_F_TMR_CTRL0_PWMCKBD_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */
+
+ #define MXC_F_TMR_CTRL0_RST_B_POS                      29 /**< CTRL0_RST_B Position */
+ #define MXC_F_TMR_CTRL0_RST_B                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */
+
+ #define MXC_F_TMR_CTRL0_CLKEN_B_POS                    30 /**< CTRL0_CLKEN_B Position */
+ #define MXC_F_TMR_CTRL0_CLKEN_B                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */
+
+ #define MXC_F_TMR_CTRL0_EN_B_POS                       31 /**< CTRL0_EN_B Position */
+ #define MXC_F_TMR_CTRL0_EN_B                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */
+
+/**@} end of group TMR_CTRL0_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_NOLCMP TMR_NOLCMP
+ * @brief    Timer Non-Overlapping Compare Register.
+ * @{
+ */
+ #define MXC_F_TMR_NOLCMP_LO_A_POS                      0 /**< NOLCMP_LO_A Position */
+ #define MXC_F_TMR_NOLCMP_LO_A                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */
+
+ #define MXC_F_TMR_NOLCMP_HI_A_POS                      8 /**< NOLCMP_HI_A Position */
+ #define MXC_F_TMR_NOLCMP_HI_A                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */
+
+ #define MXC_F_TMR_NOLCMP_LO_B_POS                      16 /**< NOLCMP_LO_B Position */
+ #define MXC_F_TMR_NOLCMP_LO_B                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */
+
+ #define MXC_F_TMR_NOLCMP_HI_B_POS                      24 /**< NOLCMP_HI_B Position */
+ #define MXC_F_TMR_NOLCMP_HI_B                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */
+
+/**@} end of group TMR_NOLCMP_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_CTRL1 TMR_CTRL1
+ * @brief    Timer Configuration Register.
+ * @{
+ */
+ #define MXC_F_TMR_CTRL1_CLKSEL_A_POS                   0 /**< CTRL1_CLKSEL_A Position */
+ #define MXC_F_TMR_CTRL1_CLKSEL_A                       ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */
+
+ #define MXC_F_TMR_CTRL1_CLKEN_A_POS                    2 /**< CTRL1_CLKEN_A Position */
+ #define MXC_F_TMR_CTRL1_CLKEN_A                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */
+
+ #define MXC_F_TMR_CTRL1_CLKRDY_A_POS                   3 /**< CTRL1_CLKRDY_A Position */
+ #define MXC_F_TMR_CTRL1_CLKRDY_A                       ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */
+
+ #define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS                4 /**< CTRL1_EVENT_SEL_A Position */
+ #define MXC_F_TMR_CTRL1_EVENT_SEL_A                    ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */
+
+ #define MXC_F_TMR_CTRL1_NEGTRIG_A_POS                  7 /**< CTRL1_NEGTRIG_A Position */
+ #define MXC_F_TMR_CTRL1_NEGTRIG_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */
+
+ #define MXC_F_TMR_CTRL1_IE_A_POS                       8 /**< CTRL1_IE_A Position */
+ #define MXC_F_TMR_CTRL1_IE_A                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */
+
+ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS             9 /**< CTRL1_CAPEVENT_SEL_A Position */
+ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A                 ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */
+
+ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS              11 /**< CTRL1_SW_CAPEVENT_A Position */
+ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_A                  ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */
+
+ #define MXC_F_TMR_CTRL1_WE_A_POS                       12 /**< CTRL1_WE_A Position */
+ #define MXC_F_TMR_CTRL1_WE_A                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */
+
+ #define MXC_F_TMR_CTRL1_OUTEN_A_POS                    13 /**< CTRL1_OUTEN_A Position */
+ #define MXC_F_TMR_CTRL1_OUTEN_A                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */
+
+ #define MXC_F_TMR_CTRL1_OUTBEN_A_POS                   14 /**< CTRL1_OUTBEN_A Position */
+ #define MXC_F_TMR_CTRL1_OUTBEN_A                       ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+
+ #define MXC_F_TMR_CTRL1_CLKSEL_B_POS                   16 /**< CTRL1_CLKSEL_B Position */
+ #define MXC_F_TMR_CTRL1_CLKSEL_B                       ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
+
+ #define MXC_F_TMR_CTRL1_CLKEN_B_POS                    18 /**< CTRL1_CLKEN_B Position */
+ #define MXC_F_TMR_CTRL1_CLKEN_B                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */
+
+ #define MXC_F_TMR_CTRL1_CLKRDY_B_POS                   19 /**< CTRL1_CLKRDY_B Position */
+ #define MXC_F_TMR_CTRL1_CLKRDY_B                       ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */
+
+ #define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS                20 /**< CTRL1_EVENT_SEL_B Position */
+ #define MXC_F_TMR_CTRL1_EVENT_SEL_B                    ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */
+
+ #define MXC_F_TMR_CTRL1_NEGTRIG_B_POS                  23 /**< CTRL1_NEGTRIG_B Position */
+ #define MXC_F_TMR_CTRL1_NEGTRIG_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */
+
+ #define MXC_F_TMR_CTRL1_IE_B_POS                       24 /**< CTRL1_IE_B Position */
+ #define MXC_F_TMR_CTRL1_IE_B                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */
+
+ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS             25 /**< CTRL1_CAPEVENT_SEL_B Position */
+ #define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B                 ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */
+
+ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS              27 /**< CTRL1_SW_CAPEVENT_B Position */
+ #define MXC_F_TMR_CTRL1_SW_CAPEVENT_B                  ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */
+
+ #define MXC_F_TMR_CTRL1_WE_B_POS                       28 /**< CTRL1_WE_B Position */
+ #define MXC_F_TMR_CTRL1_WE_B                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */
+
+ #define MXC_F_TMR_CTRL1_CASCADE_POS                    31 /**< CTRL1_CASCADE Position */
+ #define MXC_F_TMR_CTRL1_CASCADE                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */
+
+/**@} end of group TMR_CTRL1_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_WKFL TMR_WKFL
+ * @brief    Timer Wakeup Status Register.
+ * @{
+ */
+ #define MXC_F_TMR_WKFL_A_POS                           0 /**< WKFL_A Position */
+ #define MXC_F_TMR_WKFL_A                               ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */
+
+ #define MXC_F_TMR_WKFL_B_POS                           16 /**< WKFL_B Position */
+ #define MXC_F_TMR_WKFL_B                               ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */
+
+/**@} end of group TMR_WKFL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TMR_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h

@@ -0,0 +1,148 @@
+/**
+ * @file    trng_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _TRNG_REGS_H_
+#define _TRNG_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     trng
+ * @defgroup    trng_registers TRNG_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module.
+ * @details Random Number Generator.
+ */
+
+/**
+ * @ingroup trng_registers
+ * Structure type to access the TRNG Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> TRNG CTRL Register */
+    __I  uint32_t status;               /**< <tt>\b 0x04:</tt> TRNG STATUS Register */
+    __I  uint32_t data;                 /**< <tt>\b 0x08:</tt> TRNG DATA Register */
+} mxc_trng_regs_t;
+
+/* Register offsets for module TRNG */
+/**
+ * @ingroup    trng_registers
+ * @defgroup   TRNG_Register_Offsets Register Offsets
+ * @brief      TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_TRNG_CTRL                    ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_TRNG_STATUS                  ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_TRNG_DATA                    ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: <tt> 0x0008</tt> */ 
+/**@} end of group trng_registers */
+
+/**
+ * @ingroup  trng_registers
+ * @defgroup TRNG_CTRL TRNG_CTRL
+ * @brief    TRNG Control Register.
+ * @{
+ */
+ #define MXC_F_TRNG_CTRL_RND_IE_POS                     1 /**< CTRL_RND_IE Position */
+ #define MXC_F_TRNG_CTRL_RND_IE                         ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */
+
+ #define MXC_F_TRNG_CTRL_KEYGEN_POS                     3 /**< CTRL_KEYGEN Position */
+ #define MXC_F_TRNG_CTRL_KEYGEN                         ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYGEN_POS)) /**< CTRL_KEYGEN Mask */
+
+ #define MXC_F_TRNG_CTRL_KEYWIPE_POS                    15 /**< CTRL_KEYWIPE Position */
+ #define MXC_F_TRNG_CTRL_KEYWIPE                        ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */
+
+/**@} end of group TRNG_CTRL_Register */
+
+/**
+ * @ingroup  trng_registers
+ * @defgroup TRNG_STATUS TRNG_STATUS
+ * @brief    Data. The content of this register is valid only when RNG_IS = 1. When TRNG is
+ *           disabled, read returns 0x0000 0000.
+ * @{
+ */
+ #define MXC_F_TRNG_STATUS_RDY_POS                      0 /**< STATUS_RDY Position */
+ #define MXC_F_TRNG_STATUS_RDY                          ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */
+
+/**@} end of group TRNG_STATUS_Register */
+
+/**
+ * @ingroup  trng_registers
+ * @defgroup TRNG_DATA TRNG_DATA
+ * @brief    Data. The content of this register is valid only when RNG_IS = 1. When TRNG is
+ *           disabled, read returns 0x0000 0000.
+ * @{
+ */
+ #define MXC_F_TRNG_DATA_DATA_POS                       0 /**< DATA_DATA Position */
+ #define MXC_F_TRNG_DATA_DATA                           ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group TRNG_DATA_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TRNG_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h

@@ -0,0 +1,403 @@
+/**
+ * @file    uart_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _UART_REGS_H_
+#define _UART_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     uart
+ * @defgroup    uart_registers UART_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
+ * @details UART Low Power Registers
+ */
+
+/**
+ * @ingroup uart_registers
+ * Structure type to access the UART Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x0000:</tt> UART CTRL Register */
+    __I  uint32_t status;               /**< <tt>\b 0x0004:</tt> UART STATUS Register */
+    __IO uint32_t int_en;               /**< <tt>\b 0x0008:</tt> UART INT_EN Register */
+    __IO uint32_t int_fl;               /**< <tt>\b 0x000C:</tt> UART INT_FL Register */
+    __IO uint32_t clkdiv;               /**< <tt>\b 0x0010:</tt> UART CLKDIV Register */
+    __IO uint32_t osr;                  /**< <tt>\b 0x0014:</tt> UART OSR Register */
+    __IO uint32_t txpeek;               /**< <tt>\b 0x0018:</tt> UART TXPEEK Register */
+    __IO uint32_t pnr;                  /**< <tt>\b 0x001C:</tt> UART PNR Register */
+    __IO uint32_t fifo;                 /**< <tt>\b 0x0020:</tt> UART FIFO Register */
+    __I  uint32_t rsv_0x24_0x2f[3];
+    __IO uint32_t dma;                  /**< <tt>\b 0x0030:</tt> UART DMA Register */
+    __IO uint32_t wken;                 /**< <tt>\b 0x0034:</tt> UART WKEN Register */
+    __IO uint32_t wkfl;                 /**< <tt>\b 0x0038:</tt> UART WKFL Register */
+} mxc_uart_regs_t;
+
+/* Register offsets for module UART */
+/**
+ * @ingroup    uart_registers
+ * @defgroup   UART_Register_Offsets Register Offsets
+ * @brief      UART Peripheral Register Offsets from the UART Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_UART_CTRL                    ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_UART_STATUS                  ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_UART_INT_EN                  ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_UART_INT_FL                  ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_UART_CLKDIV                  ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_UART_OSR                     ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_UART_TXPEEK                  ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_UART_PNR                     ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_UART_FIFO                    ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_UART_DMA                     ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_UART_WKEN                    ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_UART_WKFL                    ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: <tt> 0x0038</tt> */ 
+/**@} end of group uart_registers */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_CTRL UART_CTRL
+ * @brief    Control register
+ * @{
+ */
+ #define MXC_F_UART_CTRL_RX_THD_VAL_POS                 0 /**< CTRL_RX_THD_VAL Position */
+ #define MXC_F_UART_CTRL_RX_THD_VAL                     ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */
+
+ #define MXC_F_UART_CTRL_PAR_EN_POS                     4 /**< CTRL_PAR_EN Position */
+ #define MXC_F_UART_CTRL_PAR_EN                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */
+
+ #define MXC_F_UART_CTRL_PAR_EO_POS                     5 /**< CTRL_PAR_EO Position */
+ #define MXC_F_UART_CTRL_PAR_EO                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */
+
+ #define MXC_F_UART_CTRL_PAR_MD_POS                     6 /**< CTRL_PAR_MD Position */
+ #define MXC_F_UART_CTRL_PAR_MD                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */
+
+ #define MXC_F_UART_CTRL_CTS_DIS_POS                    7 /**< CTRL_CTS_DIS Position */
+ #define MXC_F_UART_CTRL_CTS_DIS                        ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */
+
+ #define MXC_F_UART_CTRL_TX_FLUSH_POS                   8 /**< CTRL_TX_FLUSH Position */
+ #define MXC_F_UART_CTRL_TX_FLUSH                       ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
+
+ #define MXC_F_UART_CTRL_RX_FLUSH_POS                   9 /**< CTRL_RX_FLUSH Position */
+ #define MXC_F_UART_CTRL_RX_FLUSH                       ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
+
+ #define MXC_F_UART_CTRL_CHAR_SIZE_POS                  10 /**< CTRL_CHAR_SIZE Position */
+ #define MXC_F_UART_CTRL_CHAR_SIZE                      ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_5BITS                ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_5BITS                (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_6BITS                ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_6BITS                (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_7BITS                ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_7BITS                (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_8BITS                ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_8BITS                (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */
+
+ #define MXC_F_UART_CTRL_STOPBITS_POS                   12 /**< CTRL_STOPBITS Position */
+ #define MXC_F_UART_CTRL_STOPBITS                       ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
+
+ #define MXC_F_UART_CTRL_HFC_EN_POS                     13 /**< CTRL_HFC_EN Position */
+ #define MXC_F_UART_CTRL_HFC_EN                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */
+
+ #define MXC_F_UART_CTRL_RTSDC_POS                      14 /**< CTRL_RTSDC Position */
+ #define MXC_F_UART_CTRL_RTSDC                          ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */
+
+ #define MXC_F_UART_CTRL_BCLKEN_POS                     15 /**< CTRL_BCLKEN Position */
+ #define MXC_F_UART_CTRL_BCLKEN                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */
+
+ #define MXC_F_UART_CTRL_BCLKSRC_POS                    16 /**< CTRL_BCLKSRC Position */
+ #define MXC_F_UART_CTRL_BCLKSRC                        ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */
+ #define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK       ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */
+ #define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK       (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */
+ #define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK         ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */
+ #define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK         (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */
+ #define MXC_V_UART_CTRL_BCLKSRC_CLK2                   ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */
+ #define MXC_S_UART_CTRL_BCLKSRC_CLK2                   (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */
+ #define MXC_V_UART_CTRL_BCLKSRC_CLK3                   ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */
+ #define MXC_S_UART_CTRL_BCLKSRC_CLK3                   (MXC_V_UART_CTRL_BCLKSRC_CLK3 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */
+
+ #define MXC_F_UART_CTRL_DPFE_EN_POS                    18 /**< CTRL_DPFE_EN Position */
+ #define MXC_F_UART_CTRL_DPFE_EN                        ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */
+
+ #define MXC_F_UART_CTRL_BCLKRDY_POS                    19 /**< CTRL_BCLKRDY Position */
+ #define MXC_F_UART_CTRL_BCLKRDY                        ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */
+
+ #define MXC_F_UART_CTRL_UCAGM_POS                      20 /**< CTRL_UCAGM Position */
+ #define MXC_F_UART_CTRL_UCAGM                          ((uint32_t)(0x1UL << MXC_F_UART_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */
+
+ #define MXC_F_UART_CTRL_FDM_POS                        21 /**< CTRL_FDM Position */
+ #define MXC_F_UART_CTRL_FDM                            ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FDM_POS)) /**< CTRL_FDM Mask */
+
+ #define MXC_F_UART_CTRL_DESM_POS                       22 /**< CTRL_DESM Position */
+ #define MXC_F_UART_CTRL_DESM                           ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DESM_POS)) /**< CTRL_DESM Mask */
+
+/**@} end of group UART_CTRL_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_STATUS UART_STATUS
+ * @brief    Status register
+ * @{
+ */
+ #define MXC_F_UART_STATUS_TX_BUSY_POS                  0 /**< STATUS_TX_BUSY Position */
+ #define MXC_F_UART_STATUS_TX_BUSY                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
+
+ #define MXC_F_UART_STATUS_RX_BUSY_POS                  1 /**< STATUS_RX_BUSY Position */
+ #define MXC_F_UART_STATUS_RX_BUSY                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
+
+ #define MXC_F_UART_STATUS_RX_EM_POS                    4 /**< STATUS_RX_EM Position */
+ #define MXC_F_UART_STATUS_RX_EM                        ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
+
+ #define MXC_F_UART_STATUS_RX_FULL_POS                  5 /**< STATUS_RX_FULL Position */
+ #define MXC_F_UART_STATUS_RX_FULL                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+
+ #define MXC_F_UART_STATUS_TX_EM_POS                    6 /**< STATUS_TX_EM Position */
+ #define MXC_F_UART_STATUS_TX_EM                        ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
+
+ #define MXC_F_UART_STATUS_TX_FULL_POS                  7 /**< STATUS_TX_FULL Position */
+ #define MXC_F_UART_STATUS_TX_FULL                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+
+ #define MXC_F_UART_STATUS_RX_LVL_POS                   8 /**< STATUS_RX_LVL Position */
+ #define MXC_F_UART_STATUS_RX_LVL                       ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */
+
+ #define MXC_F_UART_STATUS_TX_LVL_POS                   12 /**< STATUS_TX_LVL Position */
+ #define MXC_F_UART_STATUS_TX_LVL                       ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */
+
+/**@} end of group UART_STATUS_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_INT_EN UART_INT_EN
+ * @brief    Interrupt Enable control register
+ * @{
+ */
+ #define MXC_F_UART_INT_EN_RX_FERR_POS                  0 /**< INT_EN_RX_FERR Position */
+ #define MXC_F_UART_INT_EN_RX_FERR                      ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */
+
+ #define MXC_F_UART_INT_EN_RX_PAR_POS                   1 /**< INT_EN_RX_PAR Position */
+ #define MXC_F_UART_INT_EN_RX_PAR                       ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */
+
+ #define MXC_F_UART_INT_EN_CTS_EV_POS                   2 /**< INT_EN_CTS_EV Position */
+ #define MXC_F_UART_INT_EN_CTS_EV                       ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */
+
+ #define MXC_F_UART_INT_EN_RX_OV_POS                    3 /**< INT_EN_RX_OV Position */
+ #define MXC_F_UART_INT_EN_RX_OV                        ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */
+
+ #define MXC_F_UART_INT_EN_RX_THD_POS                   4 /**< INT_EN_RX_THD Position */
+ #define MXC_F_UART_INT_EN_RX_THD                       ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */
+
+ #define MXC_F_UART_INT_EN_TX_HE_POS                    6 /**< INT_EN_TX_HE Position */
+ #define MXC_F_UART_INT_EN_TX_HE                        ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */
+
+/**@} end of group UART_INT_EN_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_INT_FL UART_INT_FL
+ * @brief    Interrupt status flags Control register
+ * @{
+ */
+ #define MXC_F_UART_INT_FL_RX_FERR_POS                  0 /**< INT_FL_RX_FERR Position */
+ #define MXC_F_UART_INT_FL_RX_FERR                      ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */
+
+ #define MXC_F_UART_INT_FL_RX_PAR_POS                   1 /**< INT_FL_RX_PAR Position */
+ #define MXC_F_UART_INT_FL_RX_PAR                       ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */
+
+ #define MXC_F_UART_INT_FL_CTS_EV_POS                   2 /**< INT_FL_CTS_EV Position */
+ #define MXC_F_UART_INT_FL_CTS_EV                       ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */
+
+ #define MXC_F_UART_INT_FL_RX_OV_POS                    3 /**< INT_FL_RX_OV Position */
+ #define MXC_F_UART_INT_FL_RX_OV                        ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */
+
+ #define MXC_F_UART_INT_FL_RX_THD_POS                   4 /**< INT_FL_RX_THD Position */
+ #define MXC_F_UART_INT_FL_RX_THD                       ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */
+
+ #define MXC_F_UART_INT_FL_TX_HE_POS                    6 /**< INT_FL_TX_HE Position */
+ #define MXC_F_UART_INT_FL_TX_HE                        ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */
+
+/**@} end of group UART_INT_FL_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_CLKDIV UART_CLKDIV
+ * @brief    Clock Divider register
+ * @{
+ */
+ #define MXC_F_UART_CLKDIV_CLKDIV_POS                   0 /**< CLKDIV_CLKDIV Position */
+ #define MXC_F_UART_CLKDIV_CLKDIV                       ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group UART_CLKDIV_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_OSR UART_OSR
+ * @brief    Over Sampling Rate register
+ * @{
+ */
+ #define MXC_F_UART_OSR_OSR_POS                         0 /**< OSR_OSR Position */
+ #define MXC_F_UART_OSR_OSR                             ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */
+
+/**@} end of group UART_OSR_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_TXPEEK UART_TXPEEK
+ * @brief    TX FIFO Output Peek register
+ * @{
+ */
+ #define MXC_F_UART_TXPEEK_DATA_POS                     0 /**< TXPEEK_DATA Position */
+ #define MXC_F_UART_TXPEEK_DATA                         ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */
+
+/**@} end of group UART_TXPEEK_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_PNR UART_PNR
+ * @brief     Pin register
+ * @{
+ */
+ #define MXC_F_UART_PNR_CTS_POS                         0 /**< PNR_CTS Position */
+ #define MXC_F_UART_PNR_CTS                             ((uint32_t)(0x1UL << MXC_F_UART_PNR_CTS_POS)) /**< PNR_CTS Mask */
+
+ #define MXC_F_UART_PNR_RTS_POS                         1 /**< PNR_RTS Position */
+ #define MXC_F_UART_PNR_RTS                             ((uint32_t)(0x1UL << MXC_F_UART_PNR_RTS_POS)) /**< PNR_RTS Mask */
+
+/**@} end of group UART_PNR_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_FIFO UART_FIFO
+ * @brief    FIFO Read/Write register
+ * @{
+ */
+ #define MXC_F_UART_FIFO_DATA_POS                       0 /**< FIFO_DATA Position */
+ #define MXC_F_UART_FIFO_DATA                           ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+
+ #define MXC_F_UART_FIFO_RX_PAR_POS                     8 /**< FIFO_RX_PAR Position */
+ #define MXC_F_UART_FIFO_RX_PAR                         ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */
+
+/**@} end of group UART_FIFO_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_DMA UART_DMA
+ * @brief    DMA Configuration register
+ * @{
+ */
+ #define MXC_F_UART_DMA_TX_THD_VAL_POS                  0 /**< DMA_TX_THD_VAL Position */
+ #define MXC_F_UART_DMA_TX_THD_VAL                      ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */
+
+ #define MXC_F_UART_DMA_TX_EN_POS                       4 /**< DMA_TX_EN Position */
+ #define MXC_F_UART_DMA_TX_EN                           ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
+
+ #define MXC_F_UART_DMA_RX_THD_VAL_POS                  5 /**< DMA_RX_THD_VAL Position */
+ #define MXC_F_UART_DMA_RX_THD_VAL                      ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */
+
+ #define MXC_F_UART_DMA_RX_EN_POS                       9 /**< DMA_RX_EN Position */
+ #define MXC_F_UART_DMA_RX_EN                           ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
+
+/**@} end of group UART_DMA_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_WKEN UART_WKEN
+ * @brief    Wake up enable Control register
+ * @{
+ */
+ #define MXC_F_UART_WKEN_RX_NE_POS                      0 /**< WKEN_RX_NE Position */
+ #define MXC_F_UART_WKEN_RX_NE                          ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */
+
+ #define MXC_F_UART_WKEN_RX_FULL_POS                    1 /**< WKEN_RX_FULL Position */
+ #define MXC_F_UART_WKEN_RX_FULL                        ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */
+
+ #define MXC_F_UART_WKEN_RX_THD_POS                     2 /**< WKEN_RX_THD Position */
+ #define MXC_F_UART_WKEN_RX_THD                         ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */
+
+/**@} end of group UART_WKEN_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_WKFL UART_WKFL
+ * @brief    Wake up Flags register
+ * @{
+ */
+ #define MXC_F_UART_WKFL_RX_NE_POS                      0 /**< WKFL_RX_NE Position */
+ #define MXC_F_UART_WKFL_RX_NE                          ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */
+
+ #define MXC_F_UART_WKFL_RX_FULL_POS                    1 /**< WKFL_RX_FULL Position */
+ #define MXC_F_UART_WKFL_RX_FULL                        ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */
+
+ #define MXC_F_UART_WKFL_RX_THD_POS                     2 /**< WKFL_RX_THD Position */
+ #define MXC_F_UART_WKFL_RX_THD                         ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */
+
+/**@} end of group UART_WKFL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UART_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h

@@ -0,0 +1,324 @@
+/**
+ * @file    wdt_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _WDT_REGS_H_
+#define _WDT_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     wdt
+ * @defgroup    wdt_registers WDT_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
+ * @details Windowed Watchdog Timer
+ */
+
+/**
+ * @ingroup wdt_registers
+ * Structure type to access the WDT Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> WDT CTRL Register */
+    __O  uint32_t rst;                  /**< <tt>\b 0x04:</tt> WDT RST Register */
+    __IO uint32_t clksel;               /**< <tt>\b 0x08:</tt> WDT CLKSEL Register */
+    __I  uint32_t cnt;                  /**< <tt>\b 0x0C:</tt> WDT CNT Register */
+} mxc_wdt_regs_t;
+
+/* Register offsets for module WDT */
+/**
+ * @ingroup    wdt_registers
+ * @defgroup   WDT_Register_Offsets Register Offsets
+ * @brief      WDT Peripheral Register Offsets from the WDT Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_WDT_CTRL                     ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_WDT_RST                      ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_WDT_CLKSEL                   ((uint32_t)0x00000008UL) /**< Offset from WDT Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_WDT_CNT                      ((uint32_t)0x0000000CUL) /**< Offset from WDT Base Address: <tt> 0x000C</tt> */ 
+/**@} end of group wdt_registers */
+
+/**
+ * @ingroup  wdt_registers
+ * @defgroup WDT_CTRL WDT_CTRL
+ * @brief    Watchdog Timer Control Register.
+ * @{
+ */
+ #define MXC_F_WDT_CTRL_INT_LATE_VAL_POS                0 /**< CTRL_INT_LATE_VAL Position */
+ #define MXC_F_WDT_CTRL_INT_LATE_VAL                    ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_LATE_VAL_POS)) /**< CTRL_INT_LATE_VAL Mask */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31          ((uint32_t)0x0UL) /**< CTRL_INT_LATE_VAL_WDT2POW31 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW31 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30          ((uint32_t)0x1UL) /**< CTRL_INT_LATE_VAL_WDT2POW30 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW30 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29          ((uint32_t)0x2UL) /**< CTRL_INT_LATE_VAL_WDT2POW29 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW29 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28          ((uint32_t)0x3UL) /**< CTRL_INT_LATE_VAL_WDT2POW28 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW28 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27          ((uint32_t)0x4UL) /**< CTRL_INT_LATE_VAL_WDT2POW27 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW27 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26          ((uint32_t)0x5UL) /**< CTRL_INT_LATE_VAL_WDT2POW26 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW26 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25          ((uint32_t)0x6UL) /**< CTRL_INT_LATE_VAL_WDT2POW25 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW25 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24          ((uint32_t)0x7UL) /**< CTRL_INT_LATE_VAL_WDT2POW24 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW24 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23          ((uint32_t)0x8UL) /**< CTRL_INT_LATE_VAL_WDT2POW23 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW23 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22          ((uint32_t)0x9UL) /**< CTRL_INT_LATE_VAL_WDT2POW22 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW22 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21          ((uint32_t)0xAUL) /**< CTRL_INT_LATE_VAL_WDT2POW21 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW21 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20          ((uint32_t)0xBUL) /**< CTRL_INT_LATE_VAL_WDT2POW20 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW20 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19          ((uint32_t)0xCUL) /**< CTRL_INT_LATE_VAL_WDT2POW19 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW19 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18          ((uint32_t)0xDUL) /**< CTRL_INT_LATE_VAL_WDT2POW18 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW18 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17          ((uint32_t)0xEUL) /**< CTRL_INT_LATE_VAL_WDT2POW17 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW17 Setting */
+ #define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16          ((uint32_t)0xFUL) /**< CTRL_INT_LATE_VAL_WDT2POW16 Value */
+ #define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16          (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW16 Setting */
+
+ #define MXC_F_WDT_CTRL_RST_LATE_VAL_POS                4 /**< CTRL_RST_LATE_VAL Position */
+ #define MXC_F_WDT_CTRL_RST_LATE_VAL                    ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_LATE_VAL_POS)) /**< CTRL_RST_LATE_VAL Mask */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31          ((uint32_t)0x0UL) /**< CTRL_RST_LATE_VAL_WDT2POW31 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW31          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW31 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30          ((uint32_t)0x1UL) /**< CTRL_RST_LATE_VAL_WDT2POW30 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW30          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW30 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29          ((uint32_t)0x2UL) /**< CTRL_RST_LATE_VAL_WDT2POW29 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW29          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW29 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28          ((uint32_t)0x3UL) /**< CTRL_RST_LATE_VAL_WDT2POW28 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW28          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW28 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27          ((uint32_t)0x4UL) /**< CTRL_RST_LATE_VAL_WDT2POW27 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW27          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW27 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26          ((uint32_t)0x5UL) /**< CTRL_RST_LATE_VAL_WDT2POW26 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW26          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW26 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25          ((uint32_t)0x6UL) /**< CTRL_RST_LATE_VAL_WDT2POW25 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW25          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW25 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24          ((uint32_t)0x7UL) /**< CTRL_RST_LATE_VAL_WDT2POW24 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW24          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW24 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23          ((uint32_t)0x8UL) /**< CTRL_RST_LATE_VAL_WDT2POW23 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW23          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW23 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22          ((uint32_t)0x9UL) /**< CTRL_RST_LATE_VAL_WDT2POW22 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW22          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW22 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21          ((uint32_t)0xAUL) /**< CTRL_RST_LATE_VAL_WDT2POW21 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW21          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW21 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20          ((uint32_t)0xBUL) /**< CTRL_RST_LATE_VAL_WDT2POW20 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW20          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW20 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19          ((uint32_t)0xCUL) /**< CTRL_RST_LATE_VAL_WDT2POW19 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW19          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW19 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18          ((uint32_t)0xDUL) /**< CTRL_RST_LATE_VAL_WDT2POW18 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW18          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW18 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17          ((uint32_t)0xEUL) /**< CTRL_RST_LATE_VAL_WDT2POW17 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW17          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW17 Setting */
+ #define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16          ((uint32_t)0xFUL) /**< CTRL_RST_LATE_VAL_WDT2POW16 Value */
+ #define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW16          (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW16 Setting */
+
+ #define MXC_F_WDT_CTRL_EN_POS                          8 /**< CTRL_EN Position */
+ #define MXC_F_WDT_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_WDT_CTRL_INT_LATE_POS                    9 /**< CTRL_INT_LATE Position */
+ #define MXC_F_WDT_CTRL_INT_LATE                        ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_LATE_POS)) /**< CTRL_INT_LATE Mask */
+
+ #define MXC_F_WDT_CTRL_WDT_INT_EN_POS                  10 /**< CTRL_WDT_INT_EN Position */
+ #define MXC_F_WDT_CTRL_WDT_INT_EN                      ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_INT_EN_POS)) /**< CTRL_WDT_INT_EN Mask */
+
+ #define MXC_F_WDT_CTRL_WDT_RST_EN_POS                  11 /**< CTRL_WDT_RST_EN Position */
+ #define MXC_F_WDT_CTRL_WDT_RST_EN                      ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_RST_EN_POS)) /**< CTRL_WDT_RST_EN Mask */
+
+ #define MXC_F_WDT_CTRL_INT_EARLY_POS                   12 /**< CTRL_INT_EARLY Position */
+ #define MXC_F_WDT_CTRL_INT_EARLY                       ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EARLY_POS)) /**< CTRL_INT_EARLY Mask */
+
+ #define MXC_F_WDT_CTRL_INT_EARLY_VAL_POS               16 /**< CTRL_INT_EARLY_VAL Position */
+ #define MXC_F_WDT_CTRL_INT_EARLY_VAL                   ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS)) /**< CTRL_INT_EARLY_VAL Mask */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31         ((uint32_t)0x0UL) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW31         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30         ((uint32_t)0x1UL) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW30         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29         ((uint32_t)0x2UL) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW29         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28         ((uint32_t)0x3UL) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW28         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27         ((uint32_t)0x4UL) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW27         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26         ((uint32_t)0x5UL) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW26         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25         ((uint32_t)0x6UL) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW25         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24         ((uint32_t)0x7UL) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW24         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23         ((uint32_t)0x8UL) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW23         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22         ((uint32_t)0x9UL) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW22         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21         ((uint32_t)0xAUL) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW21         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20         ((uint32_t)0xBUL) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW20         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19         ((uint32_t)0xCUL) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW19         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18         ((uint32_t)0xDUL) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW18         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17         ((uint32_t)0xEUL) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW17         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Setting */
+ #define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16         ((uint32_t)0xFUL) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Value */
+ #define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW16         (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Setting */
+
+ #define MXC_F_WDT_CTRL_RST_EARLY_VAL_POS               20 /**< CTRL_RST_EARLY_VAL Position */
+ #define MXC_F_WDT_CTRL_RST_EARLY_VAL                   ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS)) /**< CTRL_RST_EARLY_VAL Mask */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31         ((uint32_t)0x0UL) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW31         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30         ((uint32_t)0x1UL) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW30         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29         ((uint32_t)0x2UL) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW29         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28         ((uint32_t)0x3UL) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW28         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27         ((uint32_t)0x4UL) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW27         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26         ((uint32_t)0x5UL) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW26         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25         ((uint32_t)0x6UL) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW25         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24         ((uint32_t)0x7UL) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW24         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23         ((uint32_t)0x8UL) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW23         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22         ((uint32_t)0x9UL) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW22         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21         ((uint32_t)0xAUL) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW21         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20         ((uint32_t)0xBUL) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW20         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19         ((uint32_t)0xCUL) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW19         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18         ((uint32_t)0xDUL) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW18         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17         ((uint32_t)0xEUL) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW17         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Setting */
+ #define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16         ((uint32_t)0xFUL) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Value */
+ #define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW16         (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Setting */
+
+ #define MXC_F_WDT_CTRL_CLKRDY_IE_POS                   27 /**< CTRL_CLKRDY_IE Position */
+ #define MXC_F_WDT_CTRL_CLKRDY_IE                       ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_IE_POS)) /**< CTRL_CLKRDY_IE Mask */
+
+ #define MXC_F_WDT_CTRL_CLKRDY_POS                      28 /**< CTRL_CLKRDY Position */
+ #define MXC_F_WDT_CTRL_CLKRDY                          ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_POS)) /**< CTRL_CLKRDY Mask */
+
+ #define MXC_F_WDT_CTRL_WIN_EN_POS                      29 /**< CTRL_WIN_EN Position */
+ #define MXC_F_WDT_CTRL_WIN_EN                          ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WIN_EN_POS)) /**< CTRL_WIN_EN Mask */
+
+ #define MXC_F_WDT_CTRL_RST_EARLY_POS                   30 /**< CTRL_RST_EARLY Position */
+ #define MXC_F_WDT_CTRL_RST_EARLY                       ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EARLY_POS)) /**< CTRL_RST_EARLY Mask */
+
+ #define MXC_F_WDT_CTRL_RST_LATE_POS                    31 /**< CTRL_RST_LATE Position */
+ #define MXC_F_WDT_CTRL_RST_LATE                        ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_LATE_POS)) /**< CTRL_RST_LATE Mask */
+
+/**@} end of group WDT_CTRL_Register */
+
+/**
+ * @ingroup  wdt_registers
+ * @defgroup WDT_RST WDT_RST
+ * @brief    Windowed Watchdog Timer Reset Register.
+ * @{
+ */
+ #define MXC_F_WDT_RST_RESET_POS                        0 /**< RST_RESET Position */
+ #define MXC_F_WDT_RST_RESET                            ((uint32_t)(0xFFUL << MXC_F_WDT_RST_RESET_POS)) /**< RST_RESET Mask */
+ #define MXC_V_WDT_RST_RESET_SEQ0                       ((uint32_t)0xA5UL) /**< RST_RESET_SEQ0 Value */
+ #define MXC_S_WDT_RST_RESET_SEQ0                       (MXC_V_WDT_RST_RESET_SEQ0 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ0 Setting */
+ #define MXC_V_WDT_RST_RESET_SEQ1                       ((uint32_t)0x5AUL) /**< RST_RESET_SEQ1 Value */
+ #define MXC_S_WDT_RST_RESET_SEQ1                       (MXC_V_WDT_RST_RESET_SEQ1 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ1 Setting */
+
+/**@} end of group WDT_RST_Register */
+
+/**
+ * @ingroup  wdt_registers
+ * @defgroup WDT_CLKSEL WDT_CLKSEL
+ * @brief    Windowed Watchdog Timer Clock Select Register.
+ * @{
+ */
+ #define MXC_F_WDT_CLKSEL_SOURCE_POS                    0 /**< CLKSEL_SOURCE Position */
+ #define MXC_F_WDT_CLKSEL_SOURCE                        ((uint32_t)(0x7UL << MXC_F_WDT_CLKSEL_SOURCE_POS)) /**< CLKSEL_SOURCE Mask */
+
+/**@} end of group WDT_CLKSEL_Register */
+
+/**
+ * @ingroup  wdt_registers
+ * @defgroup WDT_CNT WDT_CNT
+ * @brief    Windowed Watchdog Timer Count Register.
+ * @{
+ */
+ #define MXC_F_WDT_CNT_COUNT_POS                        0 /**< CNT_COUNT Position */
+ #define MXC_F_WDT_CNT_COUNT                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_WDT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
+
+/**@} end of group WDT_CNT_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WDT_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c

@@ -0,0 +1,143 @@
+/*******************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ ******************************************************************************/
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "max32670.h"
+#include "gcr_regs.h"
+#include "mxc_sys.h"
+
+
+uint32_t SystemCoreClock = HIRC_FREQ;
+
+__weak void SystemCoreClockUpdate(void)
+{
+    uint32_t base_freq, div, clk_src;
+
+    // Get the clock source and frequency
+    clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL);
+    switch (clk_src)
+    {
+        case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK:
+            base_freq = EXTCLK_FREQ;
+            break;
+        case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO:
+            base_freq = ERFO_FREQ;
+            break;
+        case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO:
+            base_freq = INRO_FREQ;
+            break;
+        case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO:
+        base_freq = IPO_FREQ;
+            break;
+        case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO:
+        base_freq = IBRO_FREQ;
+            break;
+        case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO:
+            base_freq = ERTCO_FREQ;
+            break;
+        default:
+            // Codes 001 and 111 are reserved.
+            // This code should never execute, however, initialize to safe value.
+            base_freq = HIRC_FREQ;
+            break;
+    }
+    // Get the clock divider
+    if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO)
+    {
+        base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV)>> MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
+    }
+    div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS;
+
+    SystemCoreClock = base_freq >> div;
+}
+
+/* This function is called before C runtime initialization and can be
+ * implemented by the application for early initializations. If a value other
+ * than '0' is returned, the C runtime initialization will be skipped.
+ *
+ * You may over-ride this function in your program by defining a custom 
+ *  PreInit(), but care should be taken to reproduce the initialization steps
+ *  or a non-functional system may result.
+ */
+__weak int PreInit(void)
+{
+    /* Do nothing */
+    return 0;
+}
+
+/* This function can be implemented by the application to initialize the board */
+__weak int Board_Init(void)
+{
+    /* Do nothing */
+    return 0;
+}
+
+/* Override this function for early platform initialization */
+__weak void low_level_init(void)
+{
+    /* Do nothing */
+    return;
+}
+
+/* This function is called just before control is transferred to main().
+ *
+ * You may over-ride this function in your program by defining a custom 
+ *  SystemInit(), but care should be taken to reproduce the initialization
+ *  steps or a non-functional system may result.
+ */
+__weak void SystemInit(void)
+{
+    /* Make sure interrupts are enabled. */
+    __enable_irq();
+
+#if (__FPU_PRESENT == 1)
+    /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
+    /* Grant full access, per "Table B3-24 CPACR bit assignments". */
+    /* DDI0403D "ARMv7-M Architecture Reference Manual" */
+    SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
+    __DSB();
+    __ISB();
+#endif
+
+    /* Change system clock source to the main high-speed clock */
+    MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO);
+    SystemCoreClockUpdate();
+
+    MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); 
+    MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); 
+ 
+    low_level_init();
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/crc.h

@@ -0,0 +1,185 @@
+/**
+ * @file    crc.h
+ * @brief   cyclic redundancy check driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ * 
+ *************************************************************************** */
+
+#ifndef _CRC_H_
+#define _CRC_H_
+
+/***** Includes *****/
+#include "crc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup crc CRC
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** CRC Definitions *****/
+/**
+  * @brief  Structure used to set up CRC request
+  *
+  */
+typedef struct _mxc_crc_req_t {
+    uint32_t* dataBuffer;     ///< Pointer to the data 
+    uint32_t dataLen;         ///< Length of the data
+    uint32_t resultCRC;       ///< Calculated CRC value
+} mxc_crc_req_t;
+
+/** 
+ * @brief CRC data bit order
+ *  
+ */
+typedef enum {
+    CRC_LSB_FIRST,
+    CRC_MSB_FIRST
+} mxc_crc_bitorder_t;
+
+/***** Function Prototypes *****/
+
+/* ************************************************************************* */
+/* Global Control/Configuration functions                                    */
+/* ************************************************************************* */
+
+/**
+ * @brief   Enable portions of the CRC
+ *
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_CRC_Init (void);
+
+/**
+ * @brief   Disable and reset portions of the CRC
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_CRC_Shutdown (void);
+
+/**
+ * @brief   This function should be called from the CRC ISR Handler
+ *          when using Async functions
+ * @param   ch      DMA channel
+ * @param   error   error
+ */
+void MXC_CRC_Handler (int ch, int error);
+
+/**
+ * @brief   Set the bit-order of CRC calculation
+ *
+ * @param   bitOrder  The direction to perform CRC calculation in
+ */
+void MXC_CRC_SetDirection (mxc_crc_bitorder_t bitOrder);
+
+/**
+ * @brief   Set the bit-order of CRC calculation
+ *
+ * @return  The direction of calculation, 1 for MSB first, 0 for LSB first
+ */
+mxc_crc_bitorder_t MXC_CRC_GetDirection (void);
+
+/**
+ * @brief   Byte Swap CRC Data Input
+ *
+ * @param   bitOrder  The direction to perform CRC calculation in
+ */
+void MXC_CRC_SwapDataIn (mxc_crc_bitorder_t bitOrder);
+
+/**
+ * @brief   Byte Swap CRC Data output
+ *
+ * @param   bitOrder  The direction to perform CRC calculation in
+ */
+void MXC_CRC_SwapDataOut (mxc_crc_bitorder_t bitOrder);
+
+/**
+ * @brief   Set the Polynomial for CRC calculation
+ *
+ * @param   poly  The polynomial to use for CRC calculation
+ */
+void MXC_CRC_SetPoly (uint32_t poly);
+
+/**
+ * @brief   Get the polynomial for CRC calculation
+ *
+ * @return  The polynomial used in calculation
+ */
+uint32_t MXC_CRC_GetPoly (void);
+
+/**
+ * @brief   Get the result of a CRC calculation
+ *
+ * @return  The calculated CRC value
+ */
+uint32_t MXC_CRC_GetResult (void);
+
+/*******************************/
+/* High Level Functions        */
+/*******************************/
+
+/**
+ * @brief   Perform a CRC computation
+ * @note    The result of the CRC calculation will be placed in the
+ *          mxc_crc_req_t structure
+ *
+ * @param   req   Structure containing the data for calculation
+ *
+ * @return  see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_CRC_Compute (mxc_crc_req_t* req);
+
+/**
+ * @brief   Perform a CRC computation using DMA
+ * @note    The result of the CRC calculation will be placed in the
+ *          mxc_crc_req_t structure. The user must call
+ *          MXC_DMA_Handler() in the ISR
+ *
+ * @param   req   Structure containing the data for calculation
+ * 
+ * @return  see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_CRC_ComputeAsync (mxc_crc_req_t* req);
+
+#ifdef __cplusplus
+}
+#endif
+/**@} end of group crc */
+
+#endif  /* _CRC_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/dma.h

@@ -0,0 +1,437 @@
+/**
+ * @file    dma.h
+ * @brief   Direct Memory Access (DMA) driver function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ * 
+ *************************************************************************** */
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+/* **** Includes **** */
+#include <stdbool.h>
+#include "mxc_device.h"
+#include "dma_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup dma Direct Memory Access (DMA)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * @brief   Enumeration for the DMA Channel's priority level.
+ *
+ */
+typedef enum {
+    MXC_DMA_PRIO_HIGH    = MXC_V_DMA_CTRL_PRI_HIGH,      ///< High Priority */
+    MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH,   ///< Medium High Priority */
+    MXC_DMA_PRIO_MEDLOW  = MXC_V_DMA_CTRL_PRI_MEDLOW,    ///< Medium Low Priority */
+    MXC_DMA_PRIO_LOW     = MXC_V_DMA_CTRL_PRI_LOW,       ///< Low Priority */
+} mxc_dma_priority_t;
+
+/** @brief DMA request select */
+typedef enum {
+    MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM,  ///< Memory to Memory DMA Request Selection 
+    MXC_DMA_REQUEST_SPI0RX   = MXC_S_DMA_CTRL_REQUEST_SPI0RX,    ///< SPI0 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_SPI1RX   = MXC_S_DMA_CTRL_REQUEST_SPI1RX,    ///< SPI1 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_SPI2RX   = MXC_S_DMA_CTRL_REQUEST_SPI2RX,    ///< SPI2 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_UART0RX  = MXC_S_DMA_CTRL_REQUEST_UART0RX,   ///< UART0 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_UART1RX  = MXC_S_DMA_CTRL_REQUEST_UART1RX,   ///< UART1 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_I2C0RX   = MXC_S_DMA_CTRL_REQUEST_I2C0RX,    ///< I2C0 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_I2C1RX   = MXC_S_DMA_CTRL_REQUEST_I2C1RX,    ///< I2C1 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_I2C2RX   = MXC_S_DMA_CTRL_REQUEST_I2C2RX,    ///< I2C2 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_UART2RX  = MXC_S_DMA_CTRL_REQUEST_UART2RX,   ///< UART2 Receive DMA Request Selection 
+    MXC_DMA_REQUEST_AESRX    = MXC_S_DMA_CTRL_REQUEST_AESRX,     ///< AES Receive DMA Request Selection 
+    MXC_DMA_REQUEST_UART3RX  = MXC_S_DMA_CTRL_REQUEST_UART3RX,   ///< UART3 Receive DMA Request Selection     
+    MXC_DMA_REQUEST_I2SRX    = MXC_S_DMA_CTRL_REQUEST_I2SRX,     ///< I2S Receive DMA Request Selection 
+    MXC_DMA_REQUEST_SPI0TX   = MXC_S_DMA_CTRL_REQUEST_SPI0TX,    ///< SPI0 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_SPI1TX   = MXC_S_DMA_CTRL_REQUEST_SPI1TX,    ///< SPI1 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_SPI2TX   = MXC_S_DMA_CTRL_REQUEST_SPI2TX,    ///< SPI2 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_UART0TX  = MXC_S_DMA_CTRL_REQUEST_UART0TX,   ///< UART0 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_UART1TX  = MXC_S_DMA_CTRL_REQUEST_UART1TX,   ///< UART1 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_I2C0TX   = MXC_S_DMA_CTRL_REQUEST_I2C0TX,    ///< I2C0 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_I2C1TX   = MXC_S_DMA_CTRL_REQUEST_I2C1TX,    ///< I2C1 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_I2C2TX   = MXC_S_DMA_CTRL_REQUEST_I2C2TX,    ///< I2C2 Transmit DMA Request Selection     
+    MXC_DMA_REQUEST_CRCTX    = MXC_S_DMA_CTRL_REQUEST_CRCTX,     ///< CRC Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_UART2TX  = MXC_S_DMA_CTRL_REQUEST_UART2TX,   ///< UART2 Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_AESTX    = MXC_S_DMA_CTRL_REQUEST_AESTX,     ///< AES Transmit DMA Request Selection 
+    MXC_DMA_REQUEST_UART3TX  = MXC_S_DMA_CTRL_REQUEST_UART3TX,   ///< UART3 Transmit DMA Request Selection     
+    MXC_DMA_REQUEST_I2STX    = MXC_S_DMA_CTRL_REQUEST_I2STX,     ///< I2S Transmit DMA Request Selection     
+} mxc_dma_reqsel_t;
+
+/** @brief Enumeration for the DMA prescaler */
+typedef enum {
+    MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS,     ///< Prescaler disabled 
+    MXC_DMA_PRESCALE_DIV256  = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256,  ///< Divide by 256 
+    MXC_DMA_PRESCALE_DIV64K  = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K,  ///< Divide by 65,536 
+    MXC_DMA_PRESCALE_DIV16M  = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M,  ///< Divide by 16,777,216 
+} mxc_dma_prescale_t;
+
+/** @brief Enumeration for the DMA timeout value */
+typedef enum {
+    MXC_DMA_TIMEOUT_4_CLK   = MXC_S_DMA_CTRL_TO_PER_TO4,      ///< DMA timeout of 4 clocks 
+    MXC_DMA_TIMEOUT_8_CLK   = MXC_S_DMA_CTRL_TO_PER_TO8,      ///< DMA timeout of 8 clocks 
+    MXC_DMA_TIMEOUT_16_CLK  = MXC_S_DMA_CTRL_TO_PER_TO16,     ///< DMA timeout of 16 clocks 
+    MXC_DMA_TIMEOUT_32_CLK  = MXC_S_DMA_CTRL_TO_PER_TO32,     ///< DMA timeout of 32 clocks 
+    MXC_DMA_TIMEOUT_64_CLK  = MXC_S_DMA_CTRL_TO_PER_TO64,     ///< DMA timeout of 64 clocks 
+    MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128,    ///< DMA timeout of 128 clocks
+    MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256,    ///< DMA timeout of 256 clocks
+    MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512,    ///< DMA timeout of 512 clocks
+} mxc_dma_timeout_t;
+
+/** @brief DMA transfer data width */
+typedef enum {
+    /* Using the '_V_' define instead of the '_S_' since these same values will be used to
+       specify the DSTWD also.  The API functions will shift the value the correct amount
+       prior to writing the cfg register. */
+    MXC_DMA_WIDTH_BYTE     = MXC_V_DMA_CTRL_SRCWD_BYTE,      ///< DMA transfer in bytes 
+    MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD,  ///< DMA transfer in 16-bit half-words 
+    MXC_DMA_WIDTH_WORD     = MXC_V_DMA_CTRL_SRCWD_WORD,      ///< DMA transfer in 32-bit words 
+} mxc_dma_width_t;
+
+/**
+ * @brief   The basic configuration information to set up a DMA channel
+ *          and prepare it for transfers.
+ *
+ */
+typedef struct {
+    int ch;                 ///< The channel to load the configuration data into
+    mxc_dma_reqsel_t reqsel;///< The request select line to be used (mem2mem, peripheral)
+    mxc_dma_width_t srcwd;  ///< The source width (could be dependent on FIFO width)
+    mxc_dma_width_t dstwd;  ///< The destination width (could be dependent on FIFO width)
+    int srcinc_en;          ///< Whether to increment the source address during the transfer
+    int dstinc_en;          ///< Whether to increment the source address during the transfer
+} mxc_dma_config_t;
+
+/**
+ * @brief   The information needed to complete a DMA transfer
+ *
+ */
+typedef struct {
+    int ch;                 ///< The channel to use for the transfer
+    void* source;           ///< Pointer to the source address, if applicable
+    void* dest;             ///< Pointer to the destination address, if applicable
+    int len;                ///< Number of bytes to transfer
+} mxc_dma_srcdst_t;
+
+/**
+ * @brief   The advanced configuration options, these are optional but could
+ *          be needed in cases where multiple DMA channels are running concurrently
+ *          or DMA is being used with low bandwidth peripherals.
+ *
+ */
+typedef struct {
+    int ch;                     ///< The channel to use for the transfer
+    mxc_dma_priority_t prio;    ///< The DMA priority for the channel
+    unsigned int reqwait_en;    ///< Delay the timeout timer start until after first transfer
+    mxc_dma_timeout_t tosel;    ///< Number of prescaled clocks seen by the channel before a timeout
+    mxc_dma_prescale_t pssel;   ///< Prescaler for the timeout timer
+    unsigned int burst_size;    ///< Number of bytes moved in a single burst
+} mxc_dma_adv_config_t;
+
+/**
+ * @brief   The callback called on completion of a DMA_MemCpy() transfer
+ *
+ * @param   dest    Pointer to the destination of the copy
+ */
+typedef void (*mxc_dma_complete_cb_t) (void* dest);
+
+/**
+ * @brief   The callback called on completion of a transfer,
+ * @note    This callback is used with MXC_DMA_DoTransfer()
+ *          to allow the user to chain an unlimited number of
+ *          DMA Transfers.
+ *
+ * @param   trans    Struct of the completed transfer
+ *
+ * @return  Returns the next transfer to be completed, or NULL
+ *          if no more transfers will be done
+ */
+typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest);
+
+/* **** Function Prototypes **** */
+/*************************/
+/* Low Level Functions   */
+/*************************/
+/**
+ * @brief      Initialize DMA resources
+ * @details    This initialization is required before using the DMA driver functions.
+ * @return     #E_NO_ERROR if successful
+ */
+int MXC_DMA_Init (void);
+
+/**
+ * @brief      Request DMA channel
+ * @details    Returns a handle to the first free DMA channel, which can be used via API calls
+ *             or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function.
+ * @return     Non-negative channel handle (inclusive of zero).
+ * @return     #E_NONE_AVAIL    All channels in use.
+ * @return     #E_BAD_STATE     DMA is not initialized, call MXC_DMA_Init() first.
+ * @return     #E_BUSY          DMA is currently busy (locked), try again later.
+ */
+int MXC_DMA_AcquireChannel (void);
+
+/**
+ * @brief      Release DMA channel
+ * @details    Stops any DMA operation on the channel and returns it to the pool of free channels.
+ *
+ * @param          ch   channel handle to release
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_ReleaseChannel (int ch);
+
+/**
+ * @brief      Configure the DMA channel
+ * @details    Configures the channel, which was previously requested by MXC_DMA_Getchannel()
+ *
+ * @param      config   Struct containing DMA configuration parameters
+ * @param      srcdst   Struct containing pointers and length of DMA operation
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
+
+/**
+ * @brief      Configure the DMA channel with more advanced parameters
+ *
+ * @param      advConfig    Struct containing advanced DMA parameters
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig);
+
+/**
+ * @brief      Set channel source, destination, and count for the transfer
+ * @param      srcdst Struct containing the channel, source, destination, and count for the channel
+ * @note       Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM,
+ *             either src_addr or dst_addr will be ignored by the DMA engine.
+ *             In these cases, the address is a don't-care. See the User's
+ *             Guide for more information.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst);
+
+/**
+ * @brief      Get channel source, destination, and count for transfer
+ *
+ * @param      srcdst Pointer to struct with the correct channel number
+ *
+ * @return     See \ref MXC_Error_Codes for a list of return values
+ */
+int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t* srcdst);
+
+/**
+ * @brief      Set channel reload source, destination, and count for the transfer
+ * @param      srcdstReload Struct containing the channel, source, destination, and count for the channel
+ * @note       Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM,
+ *             either src_addr or dst_addr will be ignored by the DMA engine.
+ *             In these cases, the address is a don't-care. See the User's
+ *             Guide for more information.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload);
+
+/**
+ * @brief      Get channel reload source, destination, and count for transfer
+ *
+ * @param      srcdstReload Pointer to struct with the correct channel number
+ *
+ * @return     See \ref MXC_Error_Codes for a list of return values
+ */
+int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t* srcdstReload);
+
+/**
+ * @brief      Set channel interrupt callback
+ * @param      ch        channel handle
+ * @param      callback  Pointer to a function to call when the channel
+ *                       interrupt flag is set and interrupts are enabled or
+ *                       when DMA is shutdown by the driver.
+ * @details    Configures the channel interrupt callback. The @p callback
+ *             function is called for two conditions:
+ *               -# When the channel's interrupt flag is set and DMA interrupts
+ *                  are enabled.
+ *               -# If the driver calls the MXC_DMA_Shutdown() function. The
+ *                  callback function prototype is:
+ * @code
+ *             void callback_fn(int ch, int reason);
+ * @endcode
+ *             @p ch indicates the channel that generated the callback, @p
+ *             reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN
+ *             if the DMA is being shutdown.
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR
+ *             otherwise
+ */
+int MXC_DMA_SetCallback (int ch, void (*callback) (int, int));
+
+/**
+ * @brief      Set channel interrupt
+ * @note       Each channel has two interrupts (complete, and count to zero).
+ *             To enable complete, pass true for chdis. To enable count to zero,
+ *             pass true for ctz.
+ * @param      ch Channel Handle
+ * @param      chdis Enable channel complete interrupt
+ * @param      ctz Enable channel count to zero interrupt.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
+
+/**
+ * @brief      Enable channel interrupt
+ * @note       Each channel has two interrupts (complete, and count to zero)
+               which must also be enabled with MXC_DMA_SetChannelInterruptEn()
+ * @param      ch   channel handle
+ * @param      flags The flags to enable
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_ChannelEnableInt (int ch, int flags);
+
+/**
+ * @brief      Disable channel interrupt
+ * @param      ch   channel handle
+ * @param      flags The flags to disable
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_ChannelDisableInt (int ch, int flags);
+
+/**
+ * @brief      Read channel interrupt flags
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise
+ */
+int MXC_DMA_ChannelGetFlags (int ch);
+
+/**
+ * @brief      Clear channel interrupt flags
+ * @param      ch   channel handle
+ * @param      flags The flags to clear
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_ChannelClearFlags (int ch, int flags);
+
+/**
+ * @brief      Enable channel interrupt
+ * @note       Each channel has two interrupts (complete, and count to zero)
+               which must also be enabled with MXC_DMA_SetChannelInterruptEn()
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_EnableInt (int ch);
+
+/**
+ * @brief      Disable channel interrupt
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_DisableInt (int ch);
+
+/**
+ * @brief      Start transfer
+ * @param      ch   channel handle
+ * @details    Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_Start (int ch);
+
+/**
+ * @brief      Stop DMA transfer, irrespective of status (complete or in-progress)
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int MXC_DMA_Stop (int ch);
+
+/**
+ * @brief      Get a pointer to the DMA channel registers
+ * @param      ch   channel handle
+ * @details    If direct access to DMA channel registers is required, this
+ *             function can be used on a channel handle returned by MXC_DMA_AcquireChannel().
+ * @return     NULL if an unused or invalid channel handle, or a valid pointer otherwise
+ */
+mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs (int ch);
+
+/**
+ * @brief      Interrupt handler function
+ * @details    Call this function as the ISR for each DMA channel under driver control.
+ *             Interrupt flags for channel ch will be automatically cleared before return.
+ */
+void MXC_DMA_Handler();
+
+/*************************/
+/* High Level Functions  */
+/*************************/
+
+/**
+ * @brief      Performs a memcpy, using DMA, optionally asynchronous
+ * @note       The user must have the DMA interrupt enabled and call
+ *             MXC_DMA_Handler() from the ISR.
+ *
+ * @param      dest     pointer to destination memory
+ * @param      src      pointer to source memory
+ * @param      len      number of bytes to copy
+ * @param      callback function to call when transfer is complete
+ *
+ * @return     see \ref MXC_Error_Codes
+ */
+int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
+
+/**
+ * @brief      Performs a memcpy, using DMA, optionally asynchronous
+ * @note       The user must have the DMA interrupt enabled and call
+ *             MXC_DMA_Handler() from the ISR.
+ *
+ * @param      config   The channel config struct
+ * @param      firstSrcDst  The source, destination, and count for the first transfer
+ * @param      callback function is called when transfer is complete
+ *
+ * @return     see \ref MXC_Error_Codes
+ */
+int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);
+/**
+ * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver
+ */
+
+/**@} end of group dma */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DMA_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/flc.h

@@ -0,0 +1,188 @@
+/**
+ * @file       flc.h
+ * @brief      Flash Controller driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_H_
+#define _FLC_H_
+
+/* **** Includes **** */
+#include "flc_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup flc Flash Controller  (FLC)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+/// Bit mask that can be used to find the starting address of a page in flash
+#define MXC_FLASH_PAGE_MASK         ~(MXC_FLASH_PAGE_SIZE - 1)
+
+/// Calculate the address of a page in flash from the page number
+#define MXC_FLASH_PAGE_ADDR(page)   (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief      Initializes the Flash Controller for erase/write operations
+ * @return     #E_NO_ERROR if successful.
+ */
+int MXC_FLC_Init();
+
+/**
+ * @brief      Checks if Flash Controller is busy.
+ * @details    Reading or executing from flash is not possible if flash is busy
+ *             with an erase or write operation.
+ * @return     If non-zero, flash operation is in progress
+ */
+int MXC_FLC_Busy (void);
+
+/**
+ * @brief      Erases the entire flash array.
+ * @note       This function must be executed from RAM.
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int MXC_FLC_MassErase (void);
+
+/**
+ * @brief      Erases the page of flash at the specified address.
+ * @note       This function must be executed from RAM.
+ * @param      address  Any address within the page to erase.
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int MXC_FLC_PageErase (uint32_t address);
+
+/**
+ * @brief      Read Data out of Flash from an address
+ *
+ * @param[in]  address  The address to read from
+ * @param      buffer   The buffer to read the data into
+ * @param[in]  len      The length of the buffer
+ *
+ */
+void MXC_FLC_Read (int address, void* buffer, int len);
+
+/**
+ * @brief      Writes data to flash.
+ * @note       This function must be executed from RAM.
+ * @param      address  Address in flash to start writing from.
+ * @param      length   Number of bytes to be written.
+ * @param      buffer     Pointer to data to be written to flash.
+ * @return     #E_NO_ERROR If function is successful.
+ * @note       make sure to disable ICC with ICC_Disable(); before Running this function
+ */
+int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer);
+
+/**
+ * @brief      Writes 32 bits of data to flash.
+ * @note       This function must be executed from RAM.
+ * @param      address  Address in flash to start writing from.
+ * @param      data     Pointer to data to be written to flash.
+ * @return     #E_NO_ERROR If function is successful.
+ * @note       make sure to disable ICC with ICC_Disable(); before Running this function
+ */
+int MXC_FLC_Write32 (uint32_t address, uint32_t data);
+
+/**
+ * @brief      Writes 128 bits of data to flash.
+ * @note       This function must be executed from RAM.
+ * @param      address  Address in flash to start writing from.
+ * @param      data     Pointer to data to be written to flash.
+ * @return     #E_NO_ERROR If function is successful.
+ * @note       make sure to disable ICC with ICC_Disable(); before Running this function
+ */
+int MXC_FLC_Write128 (uint32_t address, uint32_t *data);
+
+/**
+ * @brief      Enable flash interrupts
+ * @param      flags   Interrupts to enable
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int MXC_FLC_EnableInt (uint32_t flags);
+
+/**
+ * @brief      Disable flash interrupts
+ * @param      flags   Interrupts to disable
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int MXC_FLC_DisableInt (uint32_t flags);
+
+/**
+ * @brief      Retrieve flash interrupt flags
+ * @return     Interrupt flags registers
+ */
+int MXC_FLC_GetFlags (void);
+
+/**
+ * @brief      Clear flash interrupt flags
+ * @note       Provide the bit position to clear, even if the flag is write-0-to-clear
+ * @param      flags Flag bit(s) to clear
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int MXC_FLC_ClearFlags (uint32_t flags);
+
+/**
+ * @brief      Unlock info block
+ *
+ * @param[in]  address  The address in the info block needing written to
+ *
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int MXC_FLC_UnlockInfoBlock (uint32_t address);
+
+/**
+ * @brief      Lock info block
+ *
+ * @param[in]  address  The address in the info block that was written to
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int MXC_FLC_LockInfoBlock (uint32_t address);
+
+/**@} end of group flc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/gpio.h

@@ -0,0 +1,331 @@
+/**
+ * @file    gpio.h
+ * @brief   General-Purpose Input/Output (GPIO) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+/* **** Includes **** */
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup gpio General-Purpose Input/Output (GPIO)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+/**
+ * @defgroup gpio_port_pin Port and Pin Definitions
+ * @ingroup gpio
+ * @{
+ * @defgroup gpio_port Port Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define MXC_GPIO_PORT_0      ((uint32_t)(1UL << 0))        ///< Port 0  Define
+#define MXC_GPIO_PORT_1      ((uint32_t)(1UL << 1))        ///< Port 1  Define
+#define MXC_GPIO_PORT_2      ((uint32_t)(1UL << 2))        ///< Port 2  Define
+#define MXC_GPIO_PORT_3      ((uint32_t)(1UL << 3))        ///< Port 3  Define
+/**@} end of gpio_port group*/
+/**
+ * @defgroup gpio_pin Pin Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define MXC_GPIO_PIN_0       ((uint32_t)(1UL << 0))       ///< Pin 0 Define 
+#define MXC_GPIO_PIN_1       ((uint32_t)(1UL << 1))       ///< Pin 1 Define 
+#define MXC_GPIO_PIN_2       ((uint32_t)(1UL << 2))       ///< Pin 2 Define 
+#define MXC_GPIO_PIN_3       ((uint32_t)(1UL << 3))       ///< Pin 3 Define 
+#define MXC_GPIO_PIN_4       ((uint32_t)(1UL << 4))       ///< Pin 4 Define 
+#define MXC_GPIO_PIN_5       ((uint32_t)(1UL << 5))       ///< Pin 5 Define 
+#define MXC_GPIO_PIN_6       ((uint32_t)(1UL << 6))       ///< Pin 6 Define 
+#define MXC_GPIO_PIN_7       ((uint32_t)(1UL << 7))       ///< Pin 7 Define 
+#define MXC_GPIO_PIN_8       ((uint32_t)(1UL << 8))       ///< Pin 8 Define 
+#define MXC_GPIO_PIN_9       ((uint32_t)(1UL << 9))       ///< Pin 9 Define 
+#define MXC_GPIO_PIN_10      ((uint32_t)(1UL << 10))      ///< Pin 10 Define 
+#define MXC_GPIO_PIN_11      ((uint32_t)(1UL << 11))      ///< Pin 11 Define 
+#define MXC_GPIO_PIN_12      ((uint32_t)(1UL << 12))      ///< Pin 12 Define 
+#define MXC_GPIO_PIN_13      ((uint32_t)(1UL << 13))      ///< Pin 13 Define 
+#define MXC_GPIO_PIN_14      ((uint32_t)(1UL << 14))      ///< Pin 14 Define 
+#define MXC_GPIO_PIN_15      ((uint32_t)(1UL << 15))      ///< Pin 15 Define 
+#define MXC_GPIO_PIN_16      ((uint32_t)(1UL << 16))      ///< Pin 16 Define 
+#define MXC_GPIO_PIN_17      ((uint32_t)(1UL << 17))      ///< Pin 17 Define 
+#define MXC_GPIO_PIN_18      ((uint32_t)(1UL << 18))      ///< Pin 18 Define 
+#define MXC_GPIO_PIN_19      ((uint32_t)(1UL << 19))      ///< Pin 19 Define 
+#define MXC_GPIO_PIN_20      ((uint32_t)(1UL << 20))      ///< Pin 20 Define 
+#define MXC_GPIO_PIN_21      ((uint32_t)(1UL << 21))      ///< Pin 21 Define 
+#define MXC_GPIO_PIN_22      ((uint32_t)(1UL << 22))      ///< Pin 22 Define 
+#define MXC_GPIO_PIN_23      ((uint32_t)(1UL << 23))      ///< Pin 23 Define 
+#define MXC_GPIO_PIN_24      ((uint32_t)(1UL << 24))      ///< Pin 24 Define 
+#define MXC_GPIO_PIN_25      ((uint32_t)(1UL << 25))      ///< Pin 25 Define 
+#define MXC_GPIO_PIN_26      ((uint32_t)(1UL << 26))      ///< Pin 26 Define 
+#define MXC_GPIO_PIN_27      ((uint32_t)(1UL << 27))      ///< Pin 27 Define 
+#define MXC_GPIO_PIN_28      ((uint32_t)(1UL << 28))      ///< Pin 28 Define 
+#define MXC_GPIO_PIN_29      ((uint32_t)(1UL << 29))      ///< Pin 29 Define 
+#define MXC_GPIO_PIN_30      ((uint32_t)(1UL << 30))      ///< Pin 30 Define 
+#define MXC_GPIO_PIN_31      ((uint32_t)(1UL << 31))      ///< Pin 31 Define 
+/**@} end of gpio_pin group */
+/**@} end of gpio_port_pin group */
+
+/**
+ * @brief      Type alias for a GPIO callback function with prototype:
+ * @code
+    void callback_fn(void *cbdata);
+ * @endcode
+ * @param      cbdata  A void pointer to the data type as registered when
+ *                     MXC_GPIO_RegisterCallback() was called.
+ */
+typedef void (*mxc_gpio_callback_fn) (void *cbdata);
+
+/**
+ * @brief   Enumeration type for the GPIO Function Type
+ */
+typedef enum {
+    MXC_GPIO_FUNC_IN,       ///< GPIO Input 
+    MXC_GPIO_FUNC_OUT,      ///< GPIO Output 
+    MXC_GPIO_FUNC_ALT1,     ///< Alternate Function Selection 
+    MXC_GPIO_FUNC_ALT2,     ///< Alternate Function Selection 
+    MXC_GPIO_FUNC_ALT3,     ///< Alternate Function Selection 
+    MXC_GPIO_FUNC_ALT4,     ///< Alternate Function Selection 
+} mxc_gpio_func_t;
+
+/**
+ * @brief   Enumeration type for the voltage level on a given pin.
+ */
+typedef enum {
+    MXC_GPIO_VSSEL_VDDIO,        ///< Set pin to VIDDIO voltage 
+    MXC_GPIO_VSSEL_VDDIOH,       ///< Set pin to VIDDIOH voltage 
+} mxc_gpio_vssel_t;
+
+/**
+ * @brief   Enumeration type for the type of GPIO pad on a given pin.
+ */
+typedef enum {
+    MXC_GPIO_PAD_NONE,          ///< No pull-up or pull-down 
+    MXC_GPIO_PAD_PULL_UP,       ///< Set pad to weak pull-up 
+    MXC_GPIO_PAD_PULL_DOWN,     ///< Set pad to weak pull-down 
+} mxc_gpio_pad_t;
+
+/**
+ * @brief   Structure type for configuring a GPIO port.
+ */
+typedef struct {
+    mxc_gpio_regs_t* port;      ///< Pointer to GPIO regs 
+    uint32_t mask;              ///< Pin mask (multiple pins may be set) 
+    mxc_gpio_func_t func;       ///< Function type 
+    mxc_gpio_pad_t pad;         ///< Pad type 
+    mxc_gpio_vssel_t vssel;     ///< Voltage select 
+} mxc_gpio_cfg_t;
+
+/**
+ * @brief   Enumeration type for the interrupt modes.
+ */
+typedef enum {
+    MXC_GPIO_INT_LEVEL,   ///< Interrupt is level sensitive 
+    MXC_GPIO_INT_EDGE     ///< Interrupt is edge sensitive 
+} mxc_gpio_int_mode_t;
+
+/**
+ * @brief   Enumeration type for the interrupt polarity.
+ */
+typedef enum {
+    MXC_GPIO_INT_FALLING,                 ///< Interrupt triggers on falling edge 
+    MXC_GPIO_INT_HIGH,                    ///< Interrupt triggers when level is high 
+    MXC_GPIO_INT_RISING,                  ///< Interrupt triggers on rising edge 
+    MXC_GPIO_INT_LOW,                     ///< Interrupt triggers when level is low 
+    MXC_GPIO_INT_BOTH                     ///< Interrupt triggers on either edge 
+} mxc_gpio_int_pol_t;
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize GPIO.
+ * @param      portMask     Mask for the port to be initialized
+ * @return     #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_GPIO_Init (uint32_t portMask);
+
+/**
+ * @brief      Shutdown GPIO.
+ * @param      portMask     Mask for the port to be initialized
+ * @return     #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_GPIO_Shutdown (uint32_t portMask);
+
+/**
+ * @brief      Reset GPIO.
+ * @param      portMask     Mask for the port to be initialized
+ * @return     #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_GPIO_Reset (uint32_t portMask);
+
+/**
+ * @brief      Configure GPIO pin(s).
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @return     #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg);
+
+/**
+ * @brief      Gets the pin(s) input state.
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  Mask of the pin to read
+ * @return     The requested pin state.
+ */
+uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask);
+
+/**
+ * @brief      Sets the pin(s) to a high level output.
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  Mask of the pin to set
+ */
+void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask);
+
+/**
+ * @brief      Clears the pin(s) to a low level output.
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  Mask of the pin to clear
+ */
+void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask);
+
+/**
+ * @brief      Gets the pin(s) output state.
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  Mask of the pin to read the output state of
+ * @return     The state of the requested pin.
+ *
+ */
+uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask);
+
+/**
+ * @brief      Write the pin(s) to a desired output level.
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  Mask of the pin to set output level of
+ * @param      val   Desired output level of the pin(s). This will be masked
+ *                   with the configuration mask.
+ */
+void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val);
+
+/**
+ * @brief      Toggles the the pin(s) output level.
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  Mask of the pin to toggle the output
+ */
+void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask);
+
+/**
+ * @brief      Configure GPIO interrupt(s)
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @param      pol   Requested interrupt polarity.
+ * @return     #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
+
+/**
+ * @brief      Enables the specified GPIO interrupt
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  mask of the pin to enable interrupt
+ * 
+ */
+void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask);
+
+/**
+ * @brief      Disables the specified GPIO interrupt.
+ * @param      port  Pointer to GPIO port.
+ * @param      mask  mask of the pin to disable interrupt
+ */
+void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask);
+
+/**
+ * @brief      Gets the interrupt(s) status on a GPIO port
+ *
+ * @param      port  Pointer to GPIO port.
+ *
+ * @return     The requested interrupt status.
+ */
+uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port);
+
+/**
+ * @brief      Gets the interrupt(s) status on a GPIO port
+ *
+ * @param      port  Pointer to GPIO port.
+ * @param      flags  The flags to clear
+ */
+void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags);
+
+/**
+ * @brief      Registers a callback for the interrupt on a given port and pin.
+ * @param      cfg       Pointer to configuration structure describing the pin
+ * @param      callback  A pointer to a function of type #callback_fn.
+ * @param      cbdata    The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs.
+ *
+ */
+void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
+
+/**
+ * @brief      GPIO IRQ Handler. @note If a callback is registered for a given
+ *             interrupt, the callback function will be called.
+ *
+ * @param      port number of the port that generated the interrupt service routine.
+ *
+ */
+void MXC_GPIO_Handler (unsigned int port);
+
+/**
+ * @brief      Set Voltage select for pins to VDDIO or VDDIOH
+ *
+ * @param      port   The GPIO port
+ * @param[in]  vssel  VDDIO or VDDIOH to set the voltatge to
+ * @param[in]  mask   Pins in the GPIO port that will be set to the voltage.
+ * 
+ * @return     #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask);
+
+/**@} end of group gpio */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/i2s.h

@@ -0,0 +1,246 @@
+/**
+ * @file    i2s.h
+ * @brief   I2S (Inter-Integrated Sound) driver function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#ifndef _I2S_H_
+#define _I2S_H_
+
+/* **** Includes **** */
+#include "mxc_sys.h"
+#include "dma.h"
+#include "i2s_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup i2s Inter-Integrated Sound (I2S)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/** @brief I2S stereo mode select */
+typedef enum {
+    MXC_I2S_MONO_LEFT_CH = 2,
+    MXC_I2S_MONO_RIGHT_CH = 3
+} mxc_i2s_stereo_t;
+
+/** @brief I2S polarity configuration */
+typedef enum {
+    MXC_I2S_POL_NORMAL,
+    MXC_I2S_POL_INVERSE
+} mxc_i2s_polarity_t;
+
+/** @brief I2S transaction bit order */
+typedef enum {
+    MXC_I2S_MSB_FIRST,
+    MXC_I2S_LSB_FIRST
+} mxc_i2s_bitorder_t;
+
+/** @brief I2S transaction justify order */
+typedef enum {
+    MXC_I2S_MSB_JUSTIFY,
+    MXC_I2S_LSB_JUSTIFY
+} mxc_i2s_justify_t;
+
+/** @brief  I2S transaction word size */
+typedef enum {
+    MXC_I2S_DATASIZE_BYTE,
+    MXC_I2S_DATASIZE_HALFWORD,
+    MXC_I2S_DATASIZE_WORD
+} mxc_i2s_wsize_t;
+
+/** @brief  I2S transaction sample size */
+typedef enum {
+    MXC_I2S_SAMPLESIZE_EIGHT,
+    MXC_I2S_SAMPLESIZE_SIXTEEN,
+    MXC_I2S_SAMPLESIZE_TWENTY,
+    MXC_I2S_SAMPLESIZE_TWENTYFOUR,
+    MXC_I2S_SAMPLESIZE_THIRTYTWO,
+} mxc_i2s_samplesize_t;
+
+/** @brief  I2S channel mode */
+typedef enum {
+    MXC_I2S_INTERNAL_SCK_WS_0,
+    MXC_I2S_INTERNAL_SCK_WS_1,
+    MXC_I2S_EXTERNAL_SCK_INTERNAL_WS,
+    MXC_I2S_EXTERNAL_SCK_EXTERNAL_WS,
+} mxc_i2s_ch_mode_t;
+
+/** @brief I2S Configuration Struct */
+typedef struct {
+    mxc_i2s_ch_mode_t       channelMode;
+    mxc_i2s_stereo_t        stereoMode;
+    mxc_i2s_wsize_t         wordSize;
+    mxc_i2s_justify_t       justify;
+    mxc_i2s_bitorder_t      bitOrder;
+    mxc_i2s_polarity_t      wsPolarity;
+    mxc_i2s_samplesize_t    sampleSize;
+    uint16_t                clkdiv;  
+    void                    *rawData;
+    void                    *txData;
+    void                    *rxData;
+    uint32_t                length;
+} mxc_i2s_req_t;
+    
+/* **** Function Prototypes **** */
+
+/**
+ * @brief   Initialize I2S resources 
+ * 
+ * @param   req           see \ref mxc_i2s_req_t I2S Request Struct 
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2S_Init(mxc_i2s_req_t *req);
+
+/**
+ * @brief   Release I2S, clear configuration and flush FIFOs
+ * 
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */  
+int MXC_I2S_Shutdown(void);
+
+/**
+ * @brief   Configure data to be transmitted based on word and sample size
+ * 
+ * @param   req           see \ref mxc_i2s_req_t I2S Request Struct 
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.   
+ */ 
+int MXC_I2S_ConfigData(mxc_i2s_req_t *req);
+
+/**
+ * @brief   Enable TX channel
+ */
+void MXC_I2S_TXEnable(void);
+
+/**
+ * @brief   Disable TX channel
+ */
+void MXC_I2S_TXDisable(void);
+
+/**
+ * @brief   Enable RX channel
+ */
+void MXC_I2S_RXEnable(void);
+
+/**
+ * @brief   Disable RX channel
+ */
+void MXC_I2S_RXDisable(void);
+
+/**
+ * @brief   Set threshold for RX FIFO  
+ * 
+ * @param   threshold  RX FIFO interrupt threshold.
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2S_SetRXThreshold(uint8_t threshold);
+
+/**
+ * @brief   Set I2S Frequency, automatically called by I2S_Init
+ * 
+ * @param   mode    Channel mode to select clock
+ * @param   clkdiv  clock divider to set baudrate
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */  
+int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv);
+
+/**
+ * @brief   Flush I2S FIFO
+ * 
+ */  
+void MXC_I2S_Flush(void);
+
+/**
+ * @brief   Enable Interrupts
+ * 
+ * @param   flags   Interrupt mask 
+ */
+void MXC_I2S_EnableInt(uint32_t flags);
+
+/**
+ * @brief   Disable Interrupt
+ * 
+ * @param   flags   Interrupt mask
+ */
+void MXC_I2S_DisableInt(uint32_t flags);
+
+/**
+ * @brief   Get the set interrupt flags
+ * 
+ * @return  int     return the mask of the set interrupt flags     
+ */
+int MXC_I2S_GetFlags(void);
+
+/**
+ * @brief   Clears Interrupt Flags
+ * 
+ * @param   flags   Interrupt flags to be cleared
+ */  
+void MXC_I2S_ClearFlags(uint32_t flags);
+
+/**
+ * @brief   Configure TX DMA transaction
+ * 
+ * @param   src_addr    source address of data
+ * @param   len         length od the data to be transmitted    
+ */
+void MXC_I2S_TXDMAConfig(void *src_addr, int len);
+
+/**
+ * @brief   Configure RX DMA transaction
+ * 
+ * @param   dest_addr   destination address
+ * @param   len         length of the data to be received
+ */
+void MXC_I2S_RXDMAConfig(void *dest_addr, int len);
+
+/**
+ * @brief   Set the callback function pointer for I2S DMA transactions
+ * 
+ * @param   callback    Function pointer to the DMA callback function
+ */
+void MXC_I2S_RegisterDMACallback(void(*callback)(int, int));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2S_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/icc.h

@@ -0,0 +1,94 @@
+/**
+ * @file    icc.h
+ * @brief   Instruction Controller Cache(ICC) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _ICC_H_
+#define _ICC_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "icc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup icc ICC
+ * @ingroup periphlibs
+ * @{
+ */
+
+/**
+ * @brief Enumeration type for the Cache ID Register
+ */
+typedef enum {
+    ICC_INFO_RELNUM,    ///< Identifies the RTL release version
+    ICC_INFO_PARTNUM,   ///< Specifies the value of C_ID Port Number
+    ICC_INFO_ID         ///< Specifies the value of Cache ID
+} mxc_icc_info_t;
+
+/**
+ * @brief   Reads the data from the Cache Id Register.
+ * @param   cid Enumeration type for Cache Id Register.
+ * @retval  Returns the contents of Cache Id Register.
+ */
+int MXC_ICC_ID (mxc_icc_info_t cid);
+
+/**
+ * @brief   Enable the instruction cache controller.
+ */
+void MXC_ICC_Enable (void);
+
+/**
+ * @brief   Disable the instruction cache controller.
+ */
+void MXC_ICC_Disable (void);
+
+/**
+ * @brief   Flush the instruction cache controller.
+ */
+void MXC_ICC_Flush (void);
+
+/**@} end of group icc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICC_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/lp.h

@@ -0,0 +1,541 @@
+/**
+ * @file    lp.h
+ * @brief   Low Power(LP) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _LP_H_
+#define _LP_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "pwrseq_regs.h"
+#include "mcr_regs.h"
+#include "gcr_regs.h"
+#include "gpio.h"
+#include "tmr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup pwrseq Low Power (LP)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/**
+ * @brief   Enumeration type for voltage selection
+ *
+ */
+typedef enum {
+    MXC_LP_V0_9 = 0,
+    MXC_LP_V1_0,
+    MXC_LP_V1_1
+} mxc_lp_ovr_t;
+
+/**
+ * @brief   Enumeration type for PM Mode
+ *
+ */
+typedef enum {
+    MXC_LP_IPO  = MXC_F_GCR_PM_IPO_PD,
+    MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD,
+    MXC_LP_XRFO = MXC_F_GCR_PM_ERFO_PD
+} mxc_lp_cfg_ds_pd_t;
+
+/**
+ * @brief      Places the device into SLEEP mode.  This function returns once an RTC or external interrupt occur.
+ */
+void MXC_LP_EnterSleepMode (void);
+
+/**
+ * @brief      Places the device into DEEPSLEEP mode.  This function returns once an RTC or external interrupt occur.
+ */
+void MXC_LP_EnterDeepSleepMode (void);
+
+/**
+ * @brief      Places the device into BACKUP mode.  CPU state is not maintained in this mode, so this function never returns.
+ *             Instead, the device will restart once an RTC or external interrupt occur.
+ */
+void MXC_LP_EnterBackupMode (void);
+
+/**
+ * @brief      Places the device into Storage mode.  CPU state is not maintained in this mode, so this function never returns.
+ *             Instead, the device will restart once an RTC or external interrupt occur.
+ */
+void MXC_LP_EnterStorageMode (void);
+
+/**
+ * @brief      Places the device into Shutdown mode.  CPU state is not maintained in this mode, so this function never returns.
+ *             Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur.
+ */
+void MXC_LP_EnterShutDownMode (void);
+
+/**
+ * @brief      Set ovr bits to set the voltage the micro will run at.
+ *
+ * @param[in]  ovr   The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t
+ */
+void MXC_LP_SetOVR (mxc_lp_ovr_t ovr);
+
+/**
+ * @brief      Enable retention regulator
+ */
+void MXC_LP_RetentionRegEnable (void);
+
+/**
+ * @brief      Disable retention regulator
+ */
+void MXC_LP_RetentionRegDisable (void);
+
+/**
+ * @brief      Is the retention regulator enabled
+ *
+ * @return     1 = enabled 0 =  disabled
+ */
+int  MXC_LP_RetentionRegIsEnabled (void);
+
+/**
+ * @brief      Turn bandgap on
+ */
+void MXC_LP_BandgapOn (void);
+
+/**
+ * @brief      Turn bandgap off
+ */
+void MXC_LP_BandgapOff (void);
+
+/**
+ * @brief      Is the bandgap on or off
+ *
+ * @return     1 = bandgap on , 0 = bandgap off
+ */
+int MXC_LP_BandgapIsOn (void);
+
+/**
+ * @brief      Enable Power on Reset VDD Core Monitor
+ */
+void MXC_LP_PORVCOREoreMonitorEnable (void);
+
+/**
+ * @brief      Disable Power on Reset VDD Core Monitor
+ */
+void MXC_LP_PORVCOREoreMonitorDisable (void);
+
+/**
+ * @brief      Is Power on Reset VDD Core Monitor enabled
+ *
+ * @return     1 = enabled , 0 = disabled
+ */
+int MXC_LP_PORVCOREoreMonitorIsEnabled (void);
+
+/**
+ * @brief      Enable LDO
+ */
+void MXC_LP_LDOEnable (void);
+
+/**
+ * @brief      Disable LDO
+ */
+void MXC_LP_LDODisable (void);
+
+/**
+ * @brief      Is LDO enabled
+ *
+ * @return     1 = enabled , 0 = disabled
+ */
+int  MXC_LP_LDOIsEnabled (void);
+
+/**
+ * @brief      Enable Fast wakeup
+ */
+void MXC_LP_FastWakeupEnable (void);
+
+/**
+ * @brief      Disable Fast wakeup
+ */
+void MXC_LP_FastWakeupDisable (void);
+
+/**
+ * @brief      Is Fast wake up is Enabled
+ *
+ * @return     1 = enabled , 0 = disabled
+ */
+int  MXC_LP_FastWakeupIsEnabled (void);
+
+/**
+ * @brief      clear all wake up status
+ */
+void MXC_LP_ClearWakeStatus (void);
+
+/**
+ * @brief      Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
+ *             Call this function multiple times to enable pins on multiple ports.  This function does not configure
+ *             the GPIO pins nor does it setup their interrupt functionality.
+ * @param      port      The port to configure as wakeup sources.
+ * @param      mask      The pins to configure as wakeup sources.
+ */
+void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);
+
+/**
+ * @brief      Disables the selected GPIO port and its selected pins as a wake up source.
+ *             Call this function multiple times to disable pins on multiple ports.
+ * @param      port      The port to configure as wakeup sources.
+ * @param      mask      The pins to configure as wakeup sources.
+ */
+void MXC_LP_DisableGPIOWakeup (unsigned int port, unsigned int mask);
+
+/**
+ * @brief      Enables the RTC alarm to wake up the device from any low power mode.
+ */
+void MXC_LP_EnableRTCAlarmWakeup (void);
+
+/**
+ * @brief      Disables the RTC alarm from waking up the device.
+ */
+void MXC_LP_DisableRTCAlarmWakeup (void);
+
+/**
+ * @brief      Enables Timer to wakeup from any low power mode. 
+ * 
+ * @param      tmr  Pointer to timer module.
+ */
+void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief      Disables Timer from waking up device.  
+ * 
+ * @param      tmr  Pointer to timer module.
+ */
+void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief      Enables the USB to wake up the device from any low power mode.
+ */
+void MXC_LP_EnableUSBWakeup (void);
+
+/**
+ * @brief      Disables the USB from waking up the device.
+ */
+void MXC_LP_DisableUSBWakeup (void);
+
+/**
+ * @brief      Enables the HA0 to wake up the device from any low power mode.
+ */
+void MXC_LP_EnableHA0Wakeup (void);
+
+/**
+ * @brief      Disables the HA)0 from waking up the device.
+ */
+void MXC_LP_DisableHA0Wakeup (void);
+/**
+ * @brief      Enables the HA1 to wake up the device from any low power mode.
+ */
+void MXC_LP_EnableHA1Wakeup (void);
+
+/**
+ * @brief      Disables the HA1 from waking up the device.
+ */
+void MXC_LP_DisableHA1Wakeup (void);
+
+/**
+ * @brief      Configure which clocks are powered down at deep sleep and which are not affected.
+ *
+ * @note       Need to configure all clocks at once any clock not passed in the mask will be unaffected by Deepsleep.  This will
+ *             always overwrite the previous settings of ALL clocks.
+ *
+ * @param[in]  mask  The mask of the clocks to power down when part goes into deepsleep
+ *
+ * @return     #E_NO_ERROR or error based on \ref MXC_Error_Codes
+ */
+int MXC_LP_ConfigDeepSleepClocks (uint32_t mask);
+
+/**
+ * @brief      Enable NFC Oscilator Bypass
+ */
+void MXC_LP_NFCOscBypassEnable (void);
+
+/**
+ * @brief      Disable NFC Oscilator Bypass
+ */
+void MXC_LP_NFCOscBypassDisable (void);
+
+/**
+ * @brief      Is NFC Oscilator Bypass Enabled
+ *
+ * @return     1 = enabled, 0 = disabled
+ */
+int MXC_LP_NFCOscBypassIsEnabled (void);
+
+/**
+ * @brief Enable System Ram 0 in light sleep
+ */
+void MXC_LP_SysRam0LightSleepEnable (void);
+
+/**
+ * @brief Enable System Ram 1 in light sleep
+ */
+void MXC_LP_SysRam1LightSleepEnable (void);
+
+/**
+ * @brief Enable System Ram 2 in light sleep
+ */
+void MXC_LP_SysRam2LightSleepEnable (void);
+
+/**
+ * @brief Enable System Ram 3 in light sleep
+ */
+void MXC_LP_SysRam3LightSleepEnable (void);
+
+/**
+ * @brief Enable System Ram 4 in light sleep
+ */
+void MXC_LP_SysRam4LightSleepEnable (void);
+
+/**
+ * @brief Enable System Ram 5 in light sleep
+ */
+void MXC_LP_SysRam5LightSleepEnable (void);
+
+/**
+ * @brief Enable Icache 0 in light sleep
+ */
+void MXC_LP_ICache0LightSleepEnable (void);
+
+/**
+ * @brief Enable Icache XIP in light sleep
+ */
+void MXC_LP_ICacheXIPLightSleepEnable (void);
+
+/**
+ * @brief Enable System Cache in light sleep
+ */
+void MXC_LP_SRCCLightSleepEnable (void);
+
+/**
+ * @brief Enable Crypto in light sleep
+ */
+void MXC_LP_CryptoLightSleepEnable (void);
+
+/**
+ * @brief Enable USB in light sleep
+ */
+void MXC_LP_USBFIFOLightSleepEnable (void);
+
+/**
+ * @brief Enable ROM 0 in light sleep
+ */
+void MXC_LP_ROMLightSleepEnable (void);
+
+/**
+ * @brief Disable System Ram 0 in light sleep
+ */
+void MXC_LP_SysRam0LightSleepDisable (void);
+
+/**
+ * @brief Disable System Ram 1 in light sleep
+ */
+void MXC_LP_SysRam1LightSleepDisable (void);
+
+/**
+ * @brief Disable System Ram 2 in light sleep
+ */
+void MXC_LP_SysRam2LightSleepDisable (void);
+
+/**
+ * @brief Disable System Ram 3 in light sleep
+ */
+void MXC_LP_SysRam3LightSleepDisable (void);
+
+/**
+ * @brief Disable System Ram 4 in light sleep
+ */
+void MXC_LP_SysRam4LightSleepDisable (void);
+
+/**
+ * @brief Disable System Ram 5 in light sleep
+ */
+void MXC_LP_SysRam5LightSleepDisable (void);
+
+/**
+ * @brief Disable Icache 0 in light sleep
+ */
+void MXC_LP_ICache0LightSleepDisable (void);
+
+/**
+ * @brief Disable Icache XIP in light sleep
+ */
+void MXC_LP_ICacheXIPLightSleepDisable (void);
+
+/**
+ * @brief Disable System Cache in light sleep
+ */
+void MXC_LP_SRCCLightSleepDisable (void);
+
+/**
+ * @brief Disable Crypto in light sleep
+ */
+void MXC_LP_CryptoLightSleepDisable (void);
+
+/**
+ * @brief Disable USB in light sleep
+ */
+void MXC_LP_USBFIFOLightSleepDisable (void);
+
+/**
+ * @brief Disable ROM 0 in light sleep
+ */
+void MXC_LP_ROMLightSleepDisable (void);
+
+/**
+ * @brief Shutdown System Ram 0
+ */
+void MXC_LP_SysRam0Shutdown (void);
+
+/**
+ * @brief Wakeup System Ram 0
+ */
+void MXC_LP_SysRam0PowerUp (void);
+
+/**
+ * @brief Shutdown System Ram 1
+ */
+void MXC_LP_SysRam1Shutdown (void);
+
+/**
+ * @brief PowerUp System Ram 1
+ */
+void MXC_LP_SysRam1PowerUp (void);
+
+/**
+ * @brief Shutdown System Ram 2
+ */
+void MXC_LP_SysRam2Shutdown (void);
+
+/**
+ * @brief PowerUp System Ram 2
+ */
+void MXC_LP_SysRam2PowerUp (void);
+
+/**
+ * @brief Shutdown System Ram 3
+ */
+void MXC_LP_SysRam3Shutdown (void);
+
+/**
+ * @brief PowerUp System Ram 3
+ */
+void MXC_LP_SysRam3PowerUp (void);
+
+/**
+ * @brief Shutdown System Ram 4
+ */
+void MXC_LP_SysRam4Shutdown (void);
+
+/**
+ * @brief PowerUp System Ram 4
+ */
+void MXC_LP_SysRam4PowerUp (void);
+
+/**
+ * @brief Shutdown System Ram 5
+ */
+void MXC_LP_SysRam5Shutdown (void);
+
+/**
+ * @brief PowerUp System Ram 5
+ */
+void MXC_LP_SysRam5PowerUp (void);
+
+/**
+ * @brief Shutdown Internal Cache
+ */
+void MXC_LP_ICache0Shutdown (void);
+
+/**
+ * @brief PowerUp Internal Cache
+ */
+void MXC_LP_ICache0PowerUp (void);
+
+/**
+ * @brief Shutdown Internal Cache XIP
+ */
+void MXC_LP_ICacheXIPShutdown (void);
+
+/**
+ * @brief PowerUp Internal Cache XIP
+ */
+void MXC_LP_ICacheXIPPowerUp (void);
+
+/**
+ * @brief Shutdown SRCC
+ */
+void MXC_LP_SRCCShutdown (void);
+
+/**
+ * @brief PowerUp SRCC
+ */
+void MXC_LP_SRCCPowerUp (void);
+
+/**
+ * @brief Shutdown USB FIFO
+ */
+void MXC_LP_USBFIFOShutdown (void);
+
+/**
+ * @brief PowerUp USB FIFO
+ */
+void MXC_LP_USBFIFOPowerUp (void);
+
+/**
+ * @brief Shutdown ROM
+ */
+void MXC_LP_ROMShutdown (void);
+
+/**
+ * @brief PowerUp ROM
+ */
+void MXC_LP_ROMPowerUp (void);
+
+/**@} end of group pwrseq */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LP_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_aes.h

@@ -0,0 +1,318 @@
+/**
+ * @file
+ * @brief   Trust Protection Unit driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#ifndef _MXC_AES_H_
+#define _MXC_AES_H_
+
+/***** Includes *****/
+#include "aes_regs.h"
+#include "aes_key_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup aes AES
+ * @ingroup periphlibs
+ * @{
+ */
+/*@} end of group aes */
+
+/***** Definitions *****/
+
+typedef void (*mxc_aes_complete_t) (void* req, int result);
+
+/* ************************************************************************* */
+/* Cipher Definitions                                                                          */
+/* ************************************************************************* */
+
+/**
+  * @brief  Enumeration type to select AES key
+  *
+  */
+typedef enum {
+    MXC_AES_128BITS        = MXC_S_AES_CTRL_KEY_SIZE_AES128,    ///< Select AES-128 bit key
+    MXC_AES_192BITS        = MXC_S_AES_CTRL_KEY_SIZE_AES192,    ///< Select AES-192 bit key
+    MXC_AES_256BITS        = MXC_S_AES_CTRL_KEY_SIZE_AES256,    ///< Select AES-256 bit key
+} mxc_aes_keys_t;
+
+/**
+  * @brief  Enumeration type to select AES key source and encryption type
+  *
+  */
+typedef enum {
+    MXC_AES_ENCRYPT_EXT_KEY  = 0,   ///< Encryption using External key
+    MXC_AES_DECRYPT_EXT_KEY  = 1,   ///< Encryption using internal key
+    MXC_AES_DECRYPT_INT_KEY  = 2    ///< Decryption using internal key
+} mxc_aes_enc_type_t;
+
+/**
+  * @brief  Structure used to set up AES request
+  *
+  */
+typedef struct _mxc_aes_cipher_req_t {
+    uint32_t length;                ///< Length of the data
+    uint32_t *inputData;            ///< Pointer to input data
+    uint32_t *resultData;           ///< Pointer to encrypted data
+    mxc_aes_keys_t keySize;         ///< Size of AES key
+    mxc_aes_enc_type_t encryption;  ///< Encrytion type or \ref mxc_aes_enc_type_t
+    mxc_aes_complete_t callback;    ///< Callback function
+} mxc_aes_req_t;
+
+/***** Function Prototypes *****/
+
+/* ************************************************************************* */
+/* Global Control/Configuration functions                                    */
+/* ************************************************************************* */
+
+/**
+ * @brief   Enable portions of the AES
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_Init (void);
+
+/**
+ * @brief   Enable AES Interrupts
+ * 
+ * @param   interrupt interrupt to enable
+ */
+void MXC_AES_EnableInt (uint32_t interrupt);
+
+/**
+ * @brief   Disable AES Interrupts
+ * 
+ * @param   interrupt interrupt to disable
+ */
+void MXC_AES_DisableInt (uint32_t interrupt);
+
+/**
+ * @brief   Checks the global AES Busy Status
+ *
+ * @return  E_BUSY if busy and E_NO_ERROR otherwise, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_IsBusy (void);
+
+/**
+ * @brief   Disable and reset portions of the AES
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_Shutdown (void);
+
+/**
+ * @brief   This function should be called from the DMA Handler
+ *          when using Async functions
+ */
+void MXC_AES_DMACallback (int ch, int error);
+
+/**
+ * @brief   This function should be called before encryption to genrate external key
+ */
+void MXC_AES_GenerateKey (void);
+
+/**
+ * @brief   Set Key size for encryption or decryption
+ * 
+ * @param   key Key size, see \ref mxc_aes_keys_t for a list of keys
+ */
+void MXC_AES_SetKeySize (mxc_aes_keys_t key);
+
+/**
+ * @brief   Get the currently set key size
+ * 
+ * @return  mxc_aes_keys_t see \ref mxc_aes_keys_t
+ */
+mxc_aes_keys_t MXC_AES_GetKeySize (void);
+
+/**
+ * @brief   Flush Input Data FIFO
+ * 
+ */
+void MXC_AES_FlushInputFIFO (void);
+
+/**
+ * @brief   Flush Output Data FIFO
+ * 
+ */
+void MXC_AES_FlushOutputFIFO (void);
+
+/**
+ * @brief   Start AES Calculations
+ * 
+ */
+void MXC_AES_Start (void);
+
+/**
+ * @brief   Get Interrupt flags set
+ * 
+ * @return  return the flags set in intfl register
+ */
+uint32_t MXC_AES_GetFlags (void);
+
+/**
+ * @brief   Clear the interrupts
+ * 
+ * @param   flags flags to be cleared
+ */
+void MXC_AES_ClearFlags (uint32_t flags);
+
+/**
+ * @brief 
+ * @note    The result will be stored in the req structure
+ *
+ * @param   req  Structure containing data for the encryption
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_Generic (mxc_aes_req_t* req);
+
+/**
+ * @brief   Perform an encryption
+ * @note    The result will be stored in the req structure
+ *
+ * @param   req  Structure containing data for the encryption
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_Encrypt (mxc_aes_req_t* req);
+
+/**
+ * @brief   Perform a decryption
+ * @note    The result will be stored in the req structure
+ *
+ * @param   req  Structure containing data for the decryption
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_Decrypt (mxc_aes_req_t* req);
+
+/**
+ * @brief   Perform AES TX using DMA. Configures DMA request and starts the transmission.
+ * 
+ * @param   src_addr  source address
+ * @param   len       number of words of data
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 
+ */
+int MXC_AES_TXDMAConfig (void *src_addr, int len);
+
+/**
+ * @brief   Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO.
+ * 
+ * @param   dest_addr destination address
+ * @param   len       number of words of data
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 
+ */
+int MXC_AES_RXDMAConfig (void *dest_addr, int len);
+
+/**
+ * @brief   Perform encryption or decryption using DMA 
+ * 
+ * @param   req The result will be stored in the req structure. The user needs
+ *              to call MXC_AES_Handler() in the ISR
+ * @param   enc 0 for encryption and 1 for decryption
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_GenericAsync (mxc_aes_req_t* req, uint8_t enc);
+
+/**
+ * @brief   Perform an encryption using Interrupt
+ * @note    The result will be stored in the req structure. The user needs
+ *          to call MXC_AES_Handler() in the ISR
+ *
+ * @param   req  Structure containing data for the encryption
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_EncryptAsync (mxc_aes_req_t* req);
+
+/**
+ * @brief   Perform a decryption using Interrupt
+ * @note    The result will be stored in the req structure. The user needs
+ *          to call MXC_AES_Handler() in the ISR
+ *
+ * @param   req  Structure containing data for the decryption
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_DecryptAsync (mxc_aes_req_t* req);
+
+/**
+ * @brief   Set the external key
+ * @param   key  Buffer for the key.
+ * @param   len  Key size.
+ */
+void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len);
+
+/**
+ * @brief   Set the key that will be loaded into the AES key registers on a POR event.
+ * @param   key  Buffer for the key.
+ * @param   len  Key size.
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len);
+
+/**
+ * @brief   Clears the key that will be loaded into the AES key registers on a POR event.
+ *          On subsequent POR events after this function is called, the AES key registers
+ *          will be loaded with all zeroes.
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_AES_ClearPORKey();
+
+/**
+ * @brief   Transfers the POR key from the storage memory to the AES key registers.
+ *          This happens automatically after each POR.  This function should be used
+ *          if application code overwrites the key registers and wants to switch back
+ *          to the POR value.
+ * @param   len  Key size.
+ */
+void MXC_AES_CopyPORKeyToKeyRegisters(mxc_aes_keys_t len);
+
+/**
+ * @brief   Checks to see if a POR key has been programmed.
+ * @return  1 if a key has been installed, 0 if not.
+ */
+int MXC_AES_HasPORKey();
+
+
+#ifdef __cplusplus
+}
+#endif
+/**@} end of group aes */
+
+#endif  /* _MXC_AES_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_assert.h

@@ -0,0 +1,109 @@
+/**
+ * @file    mxc_assert.h
+ * @brief   Assertion checks for debugging.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ASSERT_H_
+#define _MXC_ASSERT_H_
+
+/* **** Includes **** */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup    syscfg
+ * @defgroup   mxc_assertions Assertion Checks for Debugging
+ * @brief      Assertion checks for debugging.
+ * @{
+ */
+/* **** Definitions **** */
+/**
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+///@cond
+#ifdef MXC_ASSERT_ENABLE
+/**
+ * Macro that checks the expression for true and generates an assertion.
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+#define MXC_ASSERT(expr)                                \
+if (!(expr))                                            \
+{                                                       \
+    mxc_assert(#expr, __FILE__, __LINE__);              \
+}
+/**
+ * Macro that generates an assertion with the message "FAIL".
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__);
+#else
+#define MXC_ASSERT(expr)
+#define MXC_ASSERT_FAIL()
+#endif
+///@endcond
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Assert an error when the given expression fails during debugging.
+ * @param      expr  String with the expression that failed the assertion.
+ * @param      file  File containing the failed assertion.
+ * @param      line  Line number for the failed assertion.
+ * @note       This is defined as a weak function and can be overridden at the
+ *             application layer to print the debugging information.
+ *             @code
+ *             printf("%s, file: %s, line %d\n", expr, file, line);
+ *             @endcode
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+void mxc_assert (const char *expr, const char *file, int line);
+
+/**@} end of group MXC_Assertions*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ASSERT_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_delay.h

@@ -0,0 +1,130 @@
+/**
+ * @file    mxc_delay.h
+ * @brief   Asynchronous delay routines based on the SysTick Timer.
+*/
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _DELAY_H_
+#define _DELAY_H_
+
+/**
+ * @ingroup devicelibs
+ * @defgroup    MXC_delay Delay Utility Functions
+ * @brief       Asynchronous delay routines based on the SysTick Timer
+ * @{
+ */
+
+/***** Definitions *****/
+/**
+ * Macro used to specify a microsecond timing parameter in seconds.
+ * \code
+ * x = SEC(3) // 3 seconds -> x = 3,000,000
+ * \endcode
+ */
+#define MXC_DELAY_SEC(s)            (((unsigned long)s) * 1000000UL)
+/**
+ * Macro used to specify a microsecond timing parameter in milliseconds.
+ * \code
+ * x = MSEC(3) // 3ms -> x = 3,000
+ * \endcode
+ */
+#define MXC_DELAY_MSEC(ms)          (ms * 1000UL)
+/**
+ * Macro used to specify a microsecond timing parameter.
+ * \code
+ * x = USEC(3) // 3us -> x = 3
+ * \endcode
+ */
+#define MXC_DELAY_USEC(us)          (us)
+
+/**
+ * @brief   The callback routine used by MXC_DelayAsync() when the delay is complete
+ *          or aborted early.
+ *
+ * @param   result      See \ref MXC_Error_Codes for the list of error codes.
+ */
+typedef void (*mxc_delay_complete_t) (int result);
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief      Blocks and delays for the specified number of microseconds.
+ * @details    Uses the SysTick to create the requested delay. If the SysTick is
+ *             running, the current settings will be used. If the SysTick is not
+ *             running, it will be started.
+ * @param      us    microseconds to delay
+ * @return     #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int MXC_Delay (unsigned long us);
+
+/**
+ * @brief      Starts a non-blocking delay for the specified number of
+ *             microseconds.
+ * @details    Uses the SysTick to time the requested delay. If the SysTick is
+ *             running, the current settings will be used. If the SysTick is not
+ *             running, it will be started.
+ * @note       MXC_Delay_handler() must be called from the SysTick interrupt service
+ *             routine or at a rate greater than the SysTick overflow rate.
+ * @param      us    microseconds to delay
+ * @param      callback  Function pointer to function called upon delay completion.
+ * @return     #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
+ *             delay request.
+ */
+int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback);
+
+/**
+ * @brief      Returns the status of a non-blocking delay request
+ * @pre        Start the asynchronous delay by calling MXC_Delay_start().
+ * @return     #E_BUSY until the requested delay time has expired.
+ */
+int MXC_DelayCheck (void);
+
+/**
+ * @brief      Stops an asynchronous delay previously started.
+ * @pre        Start the asynchronous delay by calling MXC_Delay_start().
+ */
+void MXC_DelayAbort (void);
+
+/**
+ * @brief      Processes the delay interrupt.
+ * @details    This function must be called from the SysTick IRQ or polled at a
+ *             rate greater than the SysTick overflow rate.
+ */
+void MXC_DelayHandler (void);
+
+/**@} end of group MXC_delay */
+
+#endif /* _DELAY_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_device.h

@@ -0,0 +1,76 @@
+/**
+ * @file    mxc_device.h
+ * @brief   Device specific header file.
+*/
+
+/*******************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_DEVICE_H_
+#define _MXC_DEVICE_H_
+
+#include "max32670.h"
+#include "mxc_errors.h"
+#include "mxc_pins.h"
+
+#if defined ( __ICCARM__ ) || (__CC_ARM)
+#include "RTE_Components.h"
+#endif 
+
+#ifndef TARGET
+#error TARGET NOT DEFINED
+#endif
+
+// Create a string definition for the TARGET
+#define STRING_ARG(arg) #arg
+#define STRING_NAME(name) STRING_ARG(name)
+#if MBED_VERSION && MBED_VERSION < 51200
+#define TARGET_NAME STRING_NAME(TARGET)
+#endif
+
+// Define which revisions of the IP we are using
+#ifndef TARGET_REV
+#error TARGET_REV NOT DEFINED
+#endif
+
+#if(TARGET_REV == 0x4131)
+// A1
+#define MXC_TMR_REV         0
+#define MXC_UART_REV        0
+#else
+
+#error TARGET_REV NOT SUPPORTED
+
+#endif /* if(TARGET_REV == ...) */
+
+#endif  /* _MXC_DEVICE_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_errors.h

@@ -0,0 +1,92 @@
+/**
+ * @file    mxc_errors.h
+ * @brief   List of common error return codes for Maxim Integrated libraries.
+*/
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ERRORS_H_
+#define _MXC_ERRORS_H_
+
+/**
+ * @ingroup syscfg
+ * @defgroup MXC_Error_Codes Error Codes
+ * @brief      A list of common error codes used by the API.
+ * @note       A Negative Error Convention is used to avoid conflict with
+ *             positive, Non-Error, returns.
+ * @{
+ */
+
+/** No Error */
+#define     E_NO_ERROR      0
+/** No Error, success */
+#define     E_SUCCESS       0
+/** Pointer is NULL */
+#define     E_NULL_PTR      -1
+/** No such device */
+#define     E_NO_DEVICE     -2
+/** Parameter not acceptable */
+#define     E_BAD_PARAM     -3
+/** Value not valid or allowed */
+#define     E_INVALID       -4
+/** Module not initialized */
+#define     E_UNINITIALIZED -5
+/** Busy now, try again later */
+#define     E_BUSY          -6
+/** Operation not allowed in current state */
+#define     E_BAD_STATE     -7
+/** Generic error */
+#define     E_UNKNOWN       -8
+/** General communications error */
+#define     E_COMM_ERR      -9
+/** Operation timed out */
+#define     E_TIME_OUT      -10
+/** Expected response did not occur */
+#define     E_NO_RESPONSE   -11
+/** Operations resulted in unexpected overflow */
+#define     E_OVERFLOW      -12
+/** Operations resulted in unexpected underflow */
+#define     E_UNDERFLOW     -13
+/** Data or resource not available at this time */
+#define     E_NONE_AVAIL    -14
+/** Event was shutdown */
+#define     E_SHUTDOWN      -15
+/** Event was aborted */
+#define     E_ABORT         -16
+/** The requested operation is not supported */
+#define     E_NOT_SUPPORTED -17
+/**@} end of MXC_Error_Codes group */
+
+#endif /* _MXC_ERRORS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_i2c.h

@@ -0,0 +1,879 @@
+/**
+* @file     i2c.h
+* @brief    Inter-integrated circuit (I2C) communications interface driver.
+*/
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_I2C_H_
+#define _MXC_I2C_H_
+
+#include <stdint.h>
+#include "mxc_sys.h"
+#include "i2c_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup i2c I2C
+ * @ingroup periphlibs
+ * @{
+ */
+
+typedef struct _i2c_req_t mxc_i2c_req_t;
+
+/**
+ * @brief   The callback used by the MXC_I2C_ReadByteInteractive() function.
+ *
+ * The callback routine used by the MXC_I2C_ReadByteInteractive() function. This
+ * function allows the application to determine whether the byte received
+ * should be acknowledged or not.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   byte        The byte received.
+ *
+ * @return  0 if the byte should not be acknowledged (NACK), non-zero to
+ *          acknowledge the byte.
+ */
+typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte);
+
+/**
+ * @brief   The callback routine used by the MXC_I2C_MasterTransactionAsync()
+ *          function to indicate the transaction has completed.
+ *
+ * @param   req         The details of the transaction.
+ * @param   result      0 if all bytes are acknowledged, 1 if any byte
+ *                      transmitted is not acknowledged, negative if error.
+ *                      See \ref MXC_Error_Codes for the list of error codes.
+ */
+typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result);
+
+/**
+ * @brief   The callback routine used by the I2C Read/Write FIFO DMA
+ *          functions to indicate the transaction has completed.
+ *
+ * @param   len         The length of data actually read/written
+ * @param   result      See \ref MXC_Error_Codes for the list of error codes.
+ */
+typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result);
+
+/**
+ * @brief   The information required to perform a complete I2C transaction as
+ *          the bus master.
+ *
+ * The information required to perform a complete I2C transaction as the bus
+ * master. This structure is used by the MXC_I2C_MasterTransaction() and
+ * MXC_I2C_MasterTransactionAsync() functions.
+ */
+struct _i2c_req_t {
+    mxc_i2c_regs_t* i2c;        ///< Pointer to I2C registers (selects the
+    ///< I2C block used.)
+    unsigned int addr;          ///< The 7-bit or 10-bit address of the slave.
+    unsigned char* tx_buf;      ///< The buffer containing the bytes to write.
+    unsigned int tx_len;        ///< The number of bytes to write. On return
+    ///< from the function, this will be set to
+    ///< the number of bytes actually transmitted.
+    unsigned char* rx_buf;      ///< The buffer to read the data into.
+    unsigned int rx_len;        ///< The number of bytes to read.  On return
+    ///< from the function, this will be set to
+    ///< the number of bytes actually received.
+    int restart;                ///< Controls whether the transaction is
+    ///< terminated with a stop or repeated start
+    ///< condition.  Use 0 for a stop, non-zero
+    ///< for repeated start.
+    mxc_i2c_complete_cb_t callback;    ///< The callback used to indicate the
+    ///< transaction is complete or an error has
+    ///< occurred. This field may be set to NULL
+    ///< if no indication is necessary. This
+    ///< field is only used by the
+    ///< MXC_I2C_MasterTransactionAsync() function.
+    ///< MXC_I2C_MasterTransaction() ignores the
+    ///< callback field.
+};
+
+/**
+ * @brief   The list of events reported by the MXC_I2C_SlaveTransaction() and
+ *          MXC_I2C_SlaveTransactionAsync() functions.
+ *
+ * The list of events reported by the MXC_I2C_SlaveTransaction() and
+ * MXC_I2C_SlaveTransactionAsync() functions.  It is up to the calling
+ * application to handle these events.
+ */
+typedef enum {
+    MXC_I2C_EVT_MASTER_WR,  ///< A slave address match occurred with the master
+    ///< requesting a write to the slave.
+    MXC_I2C_EVT_MASTER_RD,  ///< A slave address match occurred with the master
+    ///< requesting a read from the slave.
+    MXC_I2C_EVT_RX_THRESH,  ///< The receive FIFO contains more bytes than its
+    ///< threshold level.
+    MXC_I2C_EVT_TX_THRESH,  ///< The transmit FIFO contains fewer bytes than its
+    ///< threshold level.
+    MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended.
+    MXC_I2C_EVT_UNDERFLOW,  ///< The master has attempted a read when the
+    ///< transmit FIFO was empty.
+    MXC_I2C_EVT_OVERFLOW,   ///< The master has written data when the receive
+    ///< FIFO was already full.
+} mxc_i2c_slave_event_t;
+
+/**
+ * @brief   The callback routine used by the MXC_I2C_SlaveTransaction() and
+ *          MXC_I2C_SlaveTransactionAsync functions to handle the various I2C
+ *          slave events.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   event       The event that occurred to trigger this callback.
+ * @param   data        This field is used to pass Success/Fail for the
+ *                      MXC_I2C_EVT_TRANS_COMP event.
+ *
+ * @return  The return value is only used in the case of an MXC_I2C_EVT_RX_THRESH
+ *          event. In this case, the return specifies if the last byte
+ *          received should be acknowledged or not. Return 0 to acknowledge,
+ *          non-zero to not acknowledge.  The return value is ignored for all
+ *          other event types.
+ */
+typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c,
+                                        mxc_i2c_slave_event_t event, void* data);
+                                        
+/***** Function Prototypes *****/
+
+/* ************************************************************************* */
+/* Control/Configuration functions                                           */
+/* ************************************************************************* */
+
+/**
+ * @brief   Initialize and enable I2C peripheral.
+ * @note    This function sets the I2C Speed to 100kHz,  if another speed is
+ *          desired use the MXC_I2C_SetFrequency() function to set it.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   masterMode  Whether to put the device in master or slave mode. Use
+ *                      non-zero
+ *                      for master mode, and zero for slave mode.
+ * @param   slaveAddr   7-bit or 10-bit address to use when in slave mode.
+ *                      This parameter is ignored when masterMode is non-zero.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr);
+
+/**
+ * @brief   Initialize and enable I2C peripheral.
+ * @note    Set idx to 0, multiple I2C instances acting as slaves is not yet
+ *          supported.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   slaveAddr   7-bit or 10-bit address to use when in slave mode.
+ *                      This parameter is ignored when masterMode is non-zero.
+ * @param   idx         Index of the I2C slave instance.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx);
+
+/**
+ * @brief   Disable and shutdown I2C peripheral.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Reset the I2C peripheral.
+ * @note    The peripheral will need to be initialized with MXC_I2C_Init() before use
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_Reset (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Set the frequency of the I2C interface.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   hz          The desired frequency in Hertz.
+ *
+ * @return  Negative if error, otherwise actual speed set. See \ref
+ *          MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz);
+
+/**
+ * @brief   Get the frequency of the I2C interface.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  The I2C bus frequency in Hertz
+ */
+unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Checks if the given I2C bus can be placed in sleep more.
+ *
+ * This functions checks to see if there are any on-going I2C transactions in
+ * progress. If there are transactions in progress, the application should
+ * wait until the I2C bus is free before entering a low-power state.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
+ *          MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Enables or disables clock stretching by the slave.
+ *
+ * Enables or disables clock stretching by the slave. This function has no
+ * affect when operating as the master.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   enable      Enables clock stretching if non-zero, disables if zero.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable);
+
+/**
+ * @brief   Determines if clock stretching has been enabled.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  Zero if clock stretching is disabled, non-zero otherwise
+ */
+int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c);
+
+/* ************************************************************************* */
+/* Low-level functions                                                       */
+/* ************************************************************************* */
+
+/**
+ * @brief   Generate a start (or repeated start) condition on the I2C bus.
+ *
+ * Generate a start (or repeated start) condition on the I2C bus. This
+ * function may opt to delay the actual generation of the start condition
+ * until data is actually transferred.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_Start (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Generate a stop condition on the I2C bus.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_Stop (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Write a single byte to the I2C bus.
+ *
+ * Write a single byte to the I2C bus. This function assumes the I2C bus is
+ * already in the proper state (i.e. a start condition has already been
+ * generated and the bus is in the write phase of an I2C transaction). If any
+ * bytes are pending in the FIFO (i.e. in the case of clock stretching), this
+ * function will return E_OVERFLOW.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   byte        The byte to transmit.
+ *
+ * @return  0 if byte is acknowledged, 1 if not acknowledged, negative if
+ *          error. See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte);
+
+/**
+ * @brief   Read a single byte from the I2C bus.
+ *
+ * Read a single byte from the I2C bus. This function assumes the I2C bus is
+ * already in the proper state (i.e. a start condition has already been
+ * generated and the bus is in the read phase of an I2C transaction). If the FIFO
+ * is empty, this function will return E_UNDERFLOW.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   byte        Pointer to the byte to read into.
+ * @param   ack         Whether or not to acknowledge the byte once received.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack);
+
+/**
+ * @brief   Read a single byte from the I2C bus.
+ *
+ * Read a single byte from the I2C bus. After the byte is received, the
+ * provided callback will be used to determine if the byte should be
+ * acknowledged or not before continuing with the rest of the transaction.
+ * This function assumes the I2C bus is already in the proper state (i.e. a
+ * start condition has already been generated and the bus is in the read
+ * phase of an I2C transaction). This function must be called with clock
+ * stretching enabled.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   byte        Pointer to the byte to read into.
+ * @param   getAck      A function to be called to determine whether or not
+ *                      to acknowledge the byte once received.  A non-zero
+ *                      return value will acknowledge the byte.  If this
+ *                      parameter is set to NULL or its return value is 0,
+ *                      the byte received will not be acknowledged (i.e., it
+ *                      will be NACKed).
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte,
+                                 mxc_i2c_getAck_t getAck);
+                                 
+/**
+ * @brief   Write multiple bytes to the I2C bus.
+ *
+ * Write multiple bytes to the I2C bus.  This function assumes the I2C bus is
+ * already in the proper state (i.e. a start condition has already been
+ * generated and the bus is in the write phase of an I2C transaction).
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   bytes       The buffer containing the bytes to transmit.
+ * @param   len         The number of bytes to write. On return from the
+ *                      function, this will be set to the number of bytes
+ *                      actually transmitted.
+ *
+ * @return  0 if all bytes are acknowledged, 1 if any byte transmitted is not
+ *          acknowledged, negative if error. See \ref MXC_Error_Codes for the
+ *          list of error return codes.
+ */
+int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len);
+
+/**
+ * @brief   Read multiple bytes from the I2C bus.
+ *
+ * Read multiple byte from the I2C bus.  This function assumes the I2C bus is
+ * already in the proper state (i.e. a start condition has already been
+ * generated and the bus is in the read phase of an I2C transaction).
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   bytes       The buffer to read the data into.
+ * @param   len         The number of bytes to read. On return from the
+ *                      function, this will be set to the number of bytes
+ *                      actually received.
+ * @param   ack         Whether or not to acknowledge the last byte once it is
+ *                      received.  All previous bytes will be acknowledged.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len,
+                  int ack);
+                  
+/**
+ * @brief   Unloads bytes from the receive FIFO.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   bytes       The buffer to read the data into.
+ * @param   len         The number of bytes to read.
+ *
+ * @return  The number of bytes actually read.
+ */
+int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
+                                 unsigned int len);
+                                 
+/**
+ * @brief   Unloads bytes from the receive FIFO using DMA for longer reads.
+ *
+ * @note    The operation is not complete until the callback has been called
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   bytes       The buffer to read the data into.
+ * @param   len         The number of bytes to read.
+ * @param   callback    The function to call when the read is complete
+ *
+ * @return  See \ref MXC_Error_Codes for a list of return values.
+ */
+int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
+                           unsigned int len, mxc_i2c_dma_complete_cb_t callback);
+                           
+/**
+ * @brief   Get the number of bytes currently available in the receive FIFO.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  The number of bytes available.
+ */
+int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Loads bytes into the transmit FIFO.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   bytes       The buffer containing the bytes to write
+ * @param   len         The number of bytes to write.
+ *
+ * @return  The number of bytes actually written.
+ */
+int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes,
+                                  unsigned int len);
+                                  
+/**
+ * @brief   Loads bytes into the transmit FIFO using DMA for longer writes.
+ *
+ * @note    The operation is not complete until the callback has been called
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   bytes       The buffer containing the bytes to write
+ * @param   len         The number of bytes to write.
+ * @param   callback    The function to call when the read is complete
+ *
+ * @return  See \ref MXC_Error_Codes for a list of return values
+ */
+int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes,
+                            unsigned int len, mxc_i2c_dma_complete_cb_t callback);
+                            
+/**
+ * @brief   Get the amount of free space available in the transmit FIFO.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  The number of bytes available.
+ */
+int MXC_I2C_GetTXFIFOAvailable (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Removes and discards all bytes currently in the receive FIFO.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_ClearRXFIFO (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Removes and discards all bytes currently in the transmit FIFO.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Get the presently set interrupt flags.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   flags0      Pointer to store flags currently set in interrupt register intfl0.
+ * @param   flags1      Pointer to store flags currently set in interrupt register intfl1.
+ *
+ * @return  See \ref MXC_Error_Codes for a list of return values
+ */
+int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1);
+
+/**
+ * @brief   Clears the Interrupt Flags.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   flags0      Flags to be cleared in interrupt register intfl0.
+ * @param   flags1      Flags to be cleared in interrupt register intfl1.
+ */
+void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
+
+/**
+ * @brief   Enable Interrupts.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   flags0      Interrupts to be enabled in int->en0
+ * @param   flags1      Interrupts to be enabled in int->en1
+ */
+void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
+
+/**
+ * @brief   Disable Interrupts.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   flags0      Interrupts to be disabled in int->en0
+ * @param   flags1      Interrupts to be disabled in int->en1
+ */
+void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1);
+
+/**
+ * @brief   Enables the slave preload mode
+ *
+ * Use this mode to preload the slave TX FIFO with data that can be sent when
+ * the slave is addressed for a read operation without software intervention.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Disable the slave preload mode
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Enables the slave to respond to the general call address
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Prevents the slave from responding to the general call address
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Set the I2C Timeout
+ *
+ * The I2C timeout determines the amount of time the master will wait while the
+ * slave is stretching the clock, and the amount of time the slave will stretch
+ * the clock while waiting for software to unload the fifo.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   timeout     Timeout in uS
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout);
+
+/**
+ * @brief   Get the current I2C timeout
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  The current timeout in uS
+ */
+unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Attempts to recover the I2C bus, ensuring the I2C lines are idle.
+ *
+ * Attempts to recover and reset an I2C bus by sending I2C clocks. During
+ * each clock cycle, the SDA line is cycled to determine if the master has
+ * control of the line. The following steps are performed to create one SCL
+ * clock cycle:
+ *   1. Drive SCL low
+ *   2. Verify SCL is low
+ *   3. Drive SDA low
+ *   4. Verify SDA is low
+ *   5. Release SDA allowing it to return high
+ *   6. Verify SDA is high
+ *   7. Release SCL allowing it to return high.
+ *   8. Verify SCL is high
+ * If any of the steps fail, the bus is considered to still be busy and the
+ * sequence is repeated up to the requested number of times. If all steps
+ * succeed, a final stop condition is generated on the I2C bus.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   retries     Number of times to attempt the clock cycle sequence.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries);
+
+/* ************************************************************************* */
+/* Transaction level functions                                               */
+/* ************************************************************************* */
+
+/**
+ * @brief   Performs a blocking I2C Master transaction.
+ *
+ * Performs a blocking I2C transaction.  These actions will be performed:
+ *   1. If necessary, generate a start condition on the bus.
+ *   2. Send the slave address with the low bit set to 0 (indicating a write).
+ *   3. Transmit req->tx_len bytes of req->tx_buff.
+ *   4. Generate a repeated start condition on the bus.
+ *   5. Send the slave address with the low bit set to 1 (indicating a read).
+ *   6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte.
+ *   7. Generate a stop (or repeated start) condition on the bus.
+ *   Steps 3-6 will be skipped if req->tx_len and req->rx_len are both 0.
+ *   Steps 2-4 will be skipped if req->tx_len equals 0.
+ *   Steps 4-6 will be skipped if req->rx_len equals 0.
+ *
+ * @param   req         Pointer to details of the transaction
+ *
+ * @return  0 if all bytes are acknowledged, 1 if any byte transmitted is not
+ *          acknowledged, negative if error. See \ref MXC_Error_Codes for the
+ *          list of error return codes.
+ */
+int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req);
+
+/**
+ * @brief   Performs a non-blocking I2C Master transaction.
+ *
+ * Performs a non-blocking I2C transaction.  These actions will be performed:
+ *   1. If necessary, generate a start condition on the bus.
+ *   2. Send the slave address with the low bit set to 0 (indicating a write).
+ *   3. Transmit req->tx_len bytes of req->tx_buff.
+ *   4. Generate a repeated start condition on the bus.
+ *   5. Send the slave address with the low bit set to 1 (indicating a read).
+ *   6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte.
+ *   7. Generate a stop (or repeated start) condition on the bus.
+ *   8. Execute req->callback to indicate the transaction is complete.
+ *   Steps 3-6 will be skipped if tx_len and rx_len are both 0.
+ *   Steps 2-4 will be skipped if tx_len equals 0.
+ *   Steps 4-6 will be skipped if rx_len equals 0.
+ *
+ * @note    MXC_I2C_AsyncHandler() must be called periodically for this function
+ *          to operate properly. Ideally from the I2C ISR.
+ *
+ * @param   req         Pointer to details of the transaction.  The memory
+ *                      used by this parameter must remain available until
+ *                      the callback is executed.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req);
+
+/**
+ * @brief   Performs a non-blocking I2C Master transaction using DMA for reduced time
+ *          in the ISR.
+ *
+ * Performs a non-blocking I2C transaction.  These actions will be performed:
+ *   1. If necessary, generate a start condition on the bus.
+ *   2. Send the slave address with the low bit set to 0 (indicating a write).
+ *   3. Transmit req->tx_len bytes of req->tx_buff.
+ *   4. Generate a repeated start condition on the bus.
+ *   5. Send the slave address with the low bit set to 1 (indicating a read).
+ *   6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte.
+ *   7. Generate a stop (or repeated start) condition on the bus.
+ *   8. Execute req->callback to indicate the transaction is complete.
+ *   Steps 3-6 will be skipped if tx_len and rx_len are both 0.
+ *   Steps 2-4 will be skipped if tx_len equals 0.
+ *   Steps 4-6 will be skipped if rx_len equals 0.
+ *
+ * @note    MXC_I2C_AsyncHandler() must be called periodically for this function
+ *          to operate properly. Ideally from the I2C ISR.
+ *
+ * @param   req         Pointer to details of the transaction.  The memory
+ *                      used by this parameter must remain available until
+ *                      the callback is executed.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req);
+
+/**
+ * @brief   Performs a blocking I2C Slave transaction.
+ *
+ * Performs a blocking I2C transaction. This function will block until a
+ * complete transaction with this slave has been performed. A transaction
+ * begins with the master addressing the slave and ends with a repeated start
+ * condition, a stop condition, or a bus error. The provided callback
+ * function will be called for these events:
+ *      - A slave address match occurs with the master requesting a write to
+ *        the slave.
+ *      - A slave address match occurs with the master requesting a read from
+ *        the slave.
+ *      - The receive FIFO crosses the set threshold (see
+ *        MXC_I2C_SetRXThreshold()). The callback code should unload the receive
+ *        FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data.
+ *        The return value of the callback function will determine if the
+ *        last byte received should be acknowledged or not. Return 0 to
+ *        acknowledge, non-zero to not acknowledge.
+ *      - The transmit FIFO crosses the set threshold (see
+ *        MXC_I2C_SetTXThreshold()). If the master is expected to read more
+ *        data from this slave, the callback code should add data to the
+ *        transmit FIFO (see MXC_I2C_WriteFIFO()).
+ *      - The transaction ends.  If the master was writing to the slave, the
+ *        receive FIFO may still contain valid data that needs to be
+ *        retreived (see MXC_I2C_ReadFIFO()).
+ *      - The transmit FIFO underflows because the master requests data when
+ *        the transmit FIFO is empty.
+ *      - The receive FIFO overflows because the master writes data while the
+ *        receive FIFO was full.
+ *
+ * If clock stretching is disabled, careful attention must be paid to the timing
+ * of the callback to avoid losing data on write or unintentionally nacking a read.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   callback    The function to be called when an I2C event occurs.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback);
+
+/**
+ * @brief   Performs a non-blocking I2C Slave transaction.
+ *
+ * Performs a non-blocking I2C transaction. This request will remain active
+ * until a complete transaction with this slave has been performed.  A
+ * transaction begins with the master  begins with the master addressing the
+ * slave and ends with a repeated start condition, a stop condition, or a bus
+ * error. The provided callback function will be called for these events:
+ *      - A slave address match occurs with the master requesting a write to
+ *        the slave.
+ *      - A slave address match occurs with the master requesting a read from
+ *        the slave.
+ *      - The receive FIFO crosses the set threshold (see
+ *        MXC_I2C_SetRXThreshold()). The callback code should unload the receive
+ *        FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data.
+ *        The return value of the callback function will determine if the
+ *        last byte received should be acknowledged or not. Return 0 to
+ *        acknowledge, non-zero to not acknowledge.
+ *      - The transmit FIFO crosses the set threshold (see
+ *        MXC_I2C_SetTXThreshold()). If the master is expected to read more
+ *        data from this slave, the callback code should add data to the
+ *        transmit FIFO (see MXC_I2C_WriteFIFO()).
+ *      - The transaction ends.  If the master was writing to the slave, the
+ *        receive FIFO may still contain valid data that needs to be
+ *        retreived (see MXC_I2C_ReadFIFO()).
+ *      - The transmit FIFO underflows because the master requests data when
+ *        the transmit FIFO is empty.
+ *      - The receive FIFO overflows because the master writes data while the
+ *        receive FIFO was full.
+ *
+ * If clock stretching is disabled, careful attention must be paid to the timing
+ * of the callback to avoid losing data on write or unintentionally nacking a read.
+ *
+ * @note    MXC_I2C_AsyncHandler() must be called peridocally for this function
+ *          to operate properly.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   callback    The function to be called when an I2C event occurs.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback);
+
+/**
+ * @brief   Set the receive threshold level.
+ *
+ * When operating as a master, the function sets the receive threshold level
+ * for when the master should unload the receive FIFO. Smaller values may
+ * consume more CPU cycles, but decrease the chances of the master delaying
+ * the generation of I2C bus clocks because it has no room in the FIFO to
+ * receive data. Larger values may consume fewer CPU cycles, but risk delays
+ * of the I2C clock. When operating as a slave, this function sets the number
+ * of bytes the slave transaction  functions should receive before issuing a
+ * call to their callback function. Smaller values may consume more CPU
+ * cycles, but reduce the risk of missing data from the master due to the
+ * recieve FIFO being full. Larger values may reduce the number of CPU
+ * cycles, but may cause bytes sent from the master to be missed.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   numBytes    The threshold level to set. This value must be
+ *                      between 0 and 8 inclusive.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
+
+/**
+ * @brief   Get the current receive threshold level.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  The receive threshold value (in bytes).
+ */
+unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Set the transmit threshold level.
+ *
+ * When operating as a master, the function sets the transmit threshold level
+ * for when the master should add additional bytes to the transmit FIFO.
+ * Larger values may consume more CPU cycles, but decrease the chances of the
+ * master delaying the generation of I2C bus clocks because it has no data in
+ * the FIFO to transmit. Smaller values may consume fewer CPU cycles, but
+ * risk delays of the I2C clock. When operating as a slave, this function
+ * sets the number of bytes the slave transaction functions should transmit
+ * before issuing a call to their callback function. Larger values may
+ * consume more CPU cycles, but reduce the risk of not having data ready when
+ * the master requests it.  Smaller values may reduce the number of CPU
+ * cycles, but may cause the master to read from an empty FIFO.  (The master
+ * will read 0xFF in this case.)
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ * @param   numBytes    The threshold level to set.  This value must be
+ *                      between 0 and 8 inclusive.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes);
+
+/**
+ * @brief   Get the current transmit threshold level.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ *
+ * @return  The transmit threshold value (in bytes).
+ */
+unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   Abort any asynchronous requests in progress.
+ *
+ * Abort any asynchronous requests in progress. Any callbacks associated with
+ * the active transaction will be executed to indicate when the transaction
+ * has been terminated.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   The processing function for asynchronous transactions.
+ *
+ * When using the asynchronous functions, the application must call this
+ * function periodically. This can be done from within the I2C interrupt
+ * handler or periodically by the application if I2C interrupts are disabled.
+ *
+ * @param   i2c         Pointer to I2C registers (selects the I2C block used.)
+ */
+void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c);
+
+/**
+ * @brief   The processing function for DMA transactions.
+ *
+ * When using the DMA functions, the application must call this
+ * function periodically. This can be done from within the DMA Interrupt Handler.
+ *
+ * @param   ch          DMA channel
+ * @param   error       Error status
+ */
+void MXC_I2C_DMACallback (int ch, int error);
+
+
+/**@} end of group i2c */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_I2C_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_lock.h

@@ -0,0 +1,104 @@
+/**
+ * @file    mxc_lock.h
+ * @brief   Exclusive access lock utility functions.
+*/
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_LOCK_H_
+#define _MXC_LOCK_H_
+
+// To enable disable this module
+#define USE_LOCK_IN_DRIVERS  0
+
+#if USE_LOCK_IN_DRIVERS
+
+/* **** Includes **** */
+#include "mxc_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup    syscfg
+ * @defgroup   mxc_lock_utilities Exclusive Access Locks
+ * @brief      Lock functions to obtain and release a variable for exclusive
+ *             access. These functions are marked interrupt safe if they are
+ *             interrupt safe.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Attempts to acquire the lock.
+ * @details    This in an interrupt safe function that can be used as a mutex.
+ *             The lock variable must remain in scope until the lock is
+ *             released. Will not block if another thread has already acquired
+ *             the lock.
+ * @param      lock   Pointer to variable that is used for the lock.
+ * @param      value  Value to be place in the lock. Can not be 0.
+ *
+ * @return     #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
+ */
+int MXC_GetLock (uint32_t *lock, uint32_t value);
+
+/**
+ * @brief         Free the given lock.
+ * @param[in,out] lock  Pointer to the variable used for the lock. When the lock
+ *                      is free, the value pointed to by @p lock is set to zero.
+ */
+void MXC_FreeLock (uint32_t *lock);
+
+/**@} end of group mxc_lock_utilities */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#else // USE_LOCK_IN_DRIVERS
+
+#define MXC_GetLock(x, y)  E_NO_ERROR
+#define MXC_FreeLock(x)    
+
+#endif // USE_LOCK_IN_DRIVERS
+
+#endif /* _MXC_LOCK_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_pins.h

@@ -0,0 +1,116 @@
+/**
+ * @file    mxc_pins.h
+ * @brief   This file contains constant pin configurations for the peripherals.
+ */
+
+/* *****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+
+#ifndef _MXC_PINS_H_
+#define _MXC_PINS_H_
+
+#include "gpio.h"
+
+typedef enum {
+    MAP_A,
+    MAP_B,
+    MAP_C
+} sys_map_t;
+
+/***** Global Variables *****/
+// Predefined GPIO Configurations
+extern const mxc_gpio_cfg_t gpio_cfg_extclk;
+extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
+extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
+extern const mxc_gpio_cfg_t gpio_cfg_i2c2;
+extern const mxc_gpio_cfg_t gpio_cfg_i2c2b;
+extern const mxc_gpio_cfg_t gpio_cfg_i2c2c;
+
+
+extern const mxc_gpio_cfg_t gpio_cfg_uart0a;
+extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow;
+extern const mxc_gpio_cfg_t gpio_cfg_uart0a_flow_disable;
+extern const mxc_gpio_cfg_t gpio_cfg_uart0b;
+extern const mxc_gpio_cfg_t gpio_cfg_uart0b_flow;
+extern const mxc_gpio_cfg_t gpio_cfg_uart0b_flow_disable;
+
+extern const mxc_gpio_cfg_t gpio_cfg_uart1a;
+extern const mxc_gpio_cfg_t gpio_cfg_uart1a_flow;
+extern const mxc_gpio_cfg_t gpio_cfg_uart1a_flow_disable;
+extern const mxc_gpio_cfg_t gpio_cfg_uart1b;
+extern const mxc_gpio_cfg_t gpio_cfg_uart1b_flow;
+extern const mxc_gpio_cfg_t gpio_cfg_uart1b_flow_disable;
+
+extern const mxc_gpio_cfg_t gpio_cfg_uart2b;
+extern const mxc_gpio_cfg_t gpio_cfg_uart2b_flow;
+extern const mxc_gpio_cfg_t gpio_cfg_uart2b_flow_disable;
+
+extern const mxc_gpio_cfg_t gpio_cfg_uart3;
+extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow;
+extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable;
+
+
+extern const mxc_gpio_cfg_t gpio_cfg_spi0;
+// NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself.
+extern const mxc_gpio_cfg_t gpio_cfg_spi1;
+// NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2
+extern const mxc_gpio_cfg_t gpio_cfg_spi2;
+extern const mxc_gpio_cfg_t gpio_cfg_spi2b;
+// NOTE: SPI3 defined here with SS0 only, and NOT SS1, SS2, or SS3
+extern const mxc_gpio_cfg_t gpio_cfg_spi3;
+
+// Timers are only defined once, depending on package, each timer could be mapped to other pins
+extern const mxc_gpio_cfg_t gpio_cfg_tmr0;
+extern const mxc_gpio_cfg_t gpio_cfg_tmr1;
+extern const mxc_gpio_cfg_t gpio_cfg_tmr2;
+extern const mxc_gpio_cfg_t gpio_cfg_tmr3;
+extern const mxc_gpio_cfg_t gpio_cfg_tmr4;
+extern const mxc_gpio_cfg_t gpio_cfg_tmr5;
+
+extern const mxc_gpio_cfg_t gpio_cfg_i2s0;
+
+extern const mxc_gpio_cfg_t gpio_cfg_rtcsqw;
+extern const mxc_gpio_cfg_t gpio_cfg_rtcsqwb;
+
+extern const mxc_gpio_cfg_t gpio_cfg_lc1;
+extern const mxc_gpio_cfg_t gpio_cfg_mon_lc1;
+extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc1;
+extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc1;
+extern const mxc_gpio_cfg_t gpio_cfg_lc2;
+extern const mxc_gpio_cfg_t gpio_cfg_mon_lc2;
+extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2;
+extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2;
+
+#endif /* _MXC_PINS_H_ */
+

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h

@@ -0,0 +1,656 @@
+/**
+ * @file    spi.h
+ * @brief   Serial Peripheral Interface (SPI) communications driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+#ifndef _SPI_H_
+#define _SPI_H_
+
+/***** includes *******/
+#include "spi_regs.h"
+#include "mxc_sys.h"
+#include "mxc_assert.h"
+#include "gpio.h"
+#include "mxc_pins.h"
+#include "mxc_lock.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup spi SPI
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+/**
+ * @brief   The list of SPI Widths supported
+ *
+ * The SPI Width can be set on a per-transaction basis.
+ * An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is
+ * given.
+ *
+ * Using a MAX31865 RTD-to-SPI IC, read back the temperature
+ * The IC requires a SPI Read to be executed as
+ * 1. Assert SS
+ * 2. Write an 8bit register address
+ * 3. Read back the 8 bit register
+ * 4. Deassert SS
+ * This can be accomplished with the STANDARD_HALFDUPLEX width
+ * 1. set txData to the address, txLen=1
+ * 2. set rxData to a buffer of 1 byte, rxLen=1
+ * 3. The driver will transmit the txData, and after completion of
+ *    txData begin to recieve data, padding MOSI with DefaultTXData
+ *
+ */
+typedef enum {
+    SPI_WIDTH_3WIRE,                ///< 1 Data line, half duplex
+    SPI_WIDTH_STANDARD,             ///< MISO/MOSI, full duplex
+    SPI_WIDTH_DUAL,                 ///< 2 Data lines, half duplex
+    SPI_WIDTH_QUAD,                 ///< 4 Data lines, half duplex
+} mxc_spi_width_t;
+
+/**
+ * @brief The list of SPI modes
+ * 
+ * SPI supports four combinations of clock and phase polarity
+ * 
+ * Clock polarity is controlled using the bit SPIn_CTRL2.cpol 
+ * and determines if the clock is active high or active low
+ * 
+ * Clock phase determines when the data must be stable for sampling
+ *  
+ */
+typedef enum {
+    SPI_MODE_0,                     ///< clock phase = 0, clock polarity = 0 
+    SPI_MODE_1,                     ///< clock phase = 0, clock polarity = 1
+    SPI_MODE_2,                     ///< clock phase = 1, clock polarity = 0
+    SPI_MODE_3,                     ///< clock phase = 1, clock polarity = 1
+} mxc_spi_mode_t;
+
+typedef struct _mxc_spi_req_t mxc_spi_req_t;
+
+/**
+ * @brief   The callback routine used to indicate the transaction has terminated.
+ *
+ * @param   req         The details of the transaction.
+ * @param   result      See \ref MXC_Error_Codes for the list of error codes.
+ */
+typedef void (*spi_complete_cb_t) (void * req, int result);
+
+/**
+ * @brief   The information required to perform a complete SPI transaction
+ *
+ * This structure is used by blocking, async, and DMA based transactions.
+ * @note    "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions.
+ */
+struct _mxc_spi_req_t {
+    mxc_spi_regs_t*     spi;            ///<Point to SPI registers
+    int                 ssIdx;          ///< Slave select line to use (Master only, ignored in slave mode)
+    int                 ssDeassert;     ///< 1 - Deassert SS at end of transaction, 0 - leave SS asserted
+    uint8_t            *txData;         ///< Buffer containing transmit data. For character sizes
+    ///< < 8 bits, pad the MSB of each byte with zeros. For
+    ///< character sizes > 8 bits, use two bytes per character
+    ///< and pad the MSB of the upper byte with zeros
+    uint8_t            *rxData;         ///< Buffer to store received data For character sizes
+    ///< < 8 bits, pad the MSB of each byte with zeros. For
+    ///< character sizes > 8 bits, use two bytes per character
+    ///< and pad the MSB of the upper byte with zeros
+    uint32_t            txLen;          ///< Number of bytes to be sent from txData
+    uint32_t            rxLen;          ///< Number of bytes to be stored in rxData
+    uint32_t            txCnt;          ///< Number of bytes actually transmitted from txData
+    uint32_t            rxCnt;          ///< Number of bytes stored in rxData
+
+    spi_complete_cb_t   completeCB;     ///< Pointer to function called when transaction is complete
+};
+
+/* ************************************************************************* */
+/* Control/Configuration functions                                           */
+/* ************************************************************************* */
+
+/**
+ * @brief   Initialize and enable SPI peripheral.
+ *
+ * This function initializes everything necessary to call a SPI transaction function.
+ * Some parameters are set to defaults as follows:
+ * SPI Mode - 0
+ * SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set)
+ *
+ * These parameters can be modified after initialization using low level functions
+ *
+ * @param   spi             Pointer to SPI registers (selects the SPI block used.)
+ * @param   masterMode      Whether to put the device in master or slave mode. Use
+ *                          non-zero for master mode, and zero for slave mode.
+ * @param   quadModeUsed    Whether to obtain control of the SDIO2/3 pins. Use
+ *                          non-zero if the pins are needed (if Quad Mode will
+ *                          be used), and zero if they are not needed (quad mode
+ *                          will never be used).
+ * @param   numSlaves       The number of slaves used, if in master mode. This
+ *                          is used to obtain control of the necessary SS pins.
+ *                          In slave mode this is ignored and SS1 is used.
+ * @param   ssPolarity      This field sets the SS active polarity for each
+ *                          slave, each bit position corresponds to each SS line.
+ * @param   hz              The requested clock frequency. The actual clock frequency
+ *                          will be returned by the function if successful. Used in
+ *                          master mode only.
+ *
+ * @return  If successful, the actual clock frequency is returned. Otherwise, see
+ *          \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
+                  unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel);
+
+/**
+ * @brief   Disable and shutdown SPI peripheral.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_Shutdown (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Checks if the given SPI bus can be placed in sleep mode.
+ *
+ * This functions checks to see if there are any on-going SPI transactions in
+ * progress. If there are transactions in progress, the application should
+ * wait until the SPI bus is free before entering a low-power state.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
+ *          MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Returns the frequency of the clock used as the bit rate generator for a given SPI instance.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  Frequency of the clock used as the bit rate generator
+ */
+int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Set the frequency of the SPI interface.
+ *
+ * This function is applicable in Master mode only
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   hz          The desired frequency in Hertz.
+ *
+ * @return  Negative if error, otherwise actual speed set. See \ref
+ *          MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz);
+
+/**
+ * @brief   Get the frequency of the SPI interface.
+ *
+ * This function is applicable in Master mode only
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  The SPI bus frequency in Hertz
+ */
+unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Sets the number of bits per character
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   dataSize    The number of bits per character
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize);
+
+/**
+ * @brief   Gets the number of bits per character
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi);
+
+
+/* ************************************************************************* */
+/* Low-level functions                                                       */
+/* ************************************************************************* */
+
+/**
+ * @brief   Sets the slave select (SS) line used for transmissions
+ *
+ * This function is applicable in Master mode only
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   ssIdx       Slave select index
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx);
+
+/**
+ * @brief   Gets the slave select (SS) line used for transmissions
+ *
+ * This function is applicable in Master mode only
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  slave slect
+ */
+int MXC_SPI_GetSlave (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Sets the SPI width used for transmissions
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   spiWidth    SPI Width (3-Wire, Standard, Dual SPI, Quad SPI)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth);
+
+/**
+ * @brief   Gets the SPI width used for transmissions
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  Spi Width   \ref mxc_spi_width_t
+ */
+mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Sets the spi mode using clock polarity and clock phase
+ * 
+ * @param spi           Pointer to SPI registers (selects the SPI block used.)
+ * @param spiMode       \ref mxc_spi_mode_t
+ *  
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 
+ */
+int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode);
+
+/**
+ * @brief   Gets the spi mode
+ * 
+ * @param spi           Pointer to SPI registers (selects the SPI block used.)
+ * 
+ * @return mxc_spi_mode_t   \ref mxc_spi_mode_t
+ */
+mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Starts a SPI Transmission
+ *
+ * This function is applicable in Master mode only
+ *
+ * The user must ensure that there are no ongoing transmissions before
+ * calling this function
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Checks the SPI Peripheral for an ongoing transmission
+ *
+ * This function is applicable in Master mode only
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_GetActive (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Aborts an ongoing SPI Transmission
+ *
+ * This function is applicable in Master mode only
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Unloads bytes from the receive FIFO.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   bytes       The buffer to read the data into.
+ * @param   len         The number of bytes to read.
+ *
+ * @return  The number of bytes actually read.
+ */
+unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
+                                 unsigned int len);
+
+/**
+ * @brief   Get the number of bytes currently available in the receive FIFO.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  The number of bytes available.
+ */
+unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Loads bytes into the transmit FIFO.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   bytes       The buffer containing the bytes to write
+ * @param   len         The number of bytes to write.
+ *
+ * @return  The number of bytes actually written.
+ */
+unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes,
+                                  unsigned int len);
+
+/**
+ * @brief   Get the amount of free space available in the transmit FIFO.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  The number of bytes available.
+ */
+unsigned int MXC_SPI_GetTXFIFOAvailable (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Removes and discards all bytes currently in the receive FIFO.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ */
+void MXC_SPI_ClearRXFIFO (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Removes and discards all bytes currently in the transmit FIFO.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ */
+void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Set the receive threshold level.
+ *
+ * RX FIFO Receive threshold. Smaller values will cause
+ * interrupts to occur more often, but reduce the possibility
+ * of losing data because of a FIFO overflow. Larger values
+ * will reduce the time required by the ISR, but increase the
+ * possibility of data loss. Passing an invalid value will
+ * cause the driver to use the value already set in the
+ * appropriate register.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   numBytes    The threshold level to set. This value must be
+ *                      between 0 and 8 inclusive.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
+
+/**
+ * @brief   Get the current receive threshold level.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  The receive threshold value (in bytes).
+ */
+unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Set the transmit threshold level.
+ *
+ * TX FIFO threshold. Smaller values will cause interrupts
+ * to occur more often, but reduce the possibility of terminating
+ * a transaction early in master mode, or transmitting invalid data
+ * in slave mode. Larger values will reduce the time required by
+ * the ISR, but increase the possibility errors occurring. Passing
+ * an invalid value will cause the driver to use the value already
+ * set in the appropriate register.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   numBytes    The threshold level to set.  This value must be
+ *                      between 0 and 8 inclusive.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes);
+
+/**
+ * @brief   Get the current transmit threshold level.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return  The transmit threshold value (in bytes).
+ */
+unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Gets the interrupt flags that are currently set
+ *
+ * These functions should not be used while using non-blocking Transaction Level
+ * functions (Async or DMA)
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ *
+ * @return The interrupt flags
+ */
+unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Clears the interrupt flags that are currently set
+ *
+ * These functions should not be used while using non-blocking Transaction Level
+ * functions (Async or DMA)
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ */
+void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   Enables specific interrupts
+ *
+ * These functions should not be used while using non-blocking Transaction Level
+ * functions (Async or DMA)
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   mask        The interrupts to be enabled
+ */
+void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask);
+
+/**
+ * @brief   Disables specific interrupts
+ *
+ * These functions should not be used while using non-blocking Transaction Level
+ * functions (Async or DMA)
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ * @param   mask        The interrupts to be disabled
+ */
+void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask);
+
+/* ************************************************************************* */
+/* Transaction level functions                                               */
+/* ************************************************************************* */
+
+/**
+ * @brief   Performs a blocking SPI transaction.
+ *
+ * Performs a blocking SPI transaction.
+ * These actions will be performed in Master Mode:
+ * 1. Assert the specified SS
+ * 2. In Full Duplex Modes, send TX data while receiving RX Data
+ *      if rxLen > txLen, pad txData with DefaultTXData
+ *      if txLen > rxLen, discard rxData where rxCnt > rxLen
+ * 3. In Half Duplex Modes, send TX Data, then receive RX Data
+ * 4. Deassert the specified SS
+ *
+ * These actions will be performed in Slave Mode:
+ * 1. Fill FIFO with txData
+ * 2. Wait for SS Assert
+ * 3. If needed, pad txData with DefaultTXData
+ * 4. Unload RX FIFO as needed
+ * 5. On SS Deassert, return
+ *
+ * @param   req         Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_MasterTransaction (mxc_spi_req_t* req);
+
+/**
+ * @brief   Setup an interrupt-driven SPI transaction
+ *
+ * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
+ * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
+ *
+ * @param   req         Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req);
+
+/**
+ * @brief   Setup a DMA driven SPI transaction
+ *
+ * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
+ * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
+ *
+ * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and
+ * set up to load/unload the FIFOs with as few interrupt-based events as
+ * possible. The channel will be reset and returned to the system at the end of
+ * the transaction.
+ *
+ * @param   req             Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req);
+
+/**
+ * @brief   Performs a blocking SPI transaction.
+ *
+ * Performs a blocking SPI transaction.
+ * These actions will be performed in Slave Mode:
+ * 1. Fill FIFO with txData
+ * 2. Wait for SS Assert
+ * 3. If needed, pad txData with DefaultTXData
+ * 4. Unload RX FIFO as needed
+ * 5. On SS Deassert, return
+ *
+ * @param   req         Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req);
+
+/**
+ * @brief   Setup an interrupt-driven SPI transaction
+ *
+ * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
+ * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
+ *
+ * @param   req         Pointer to details of the transactionz
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req);
+
+/**
+ * @brief   Setup a DMA driven SPI transaction
+ *
+ * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary
+ * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc)
+ *
+ * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and
+ * set up to load/unload the FIFOs with as few interrupt-based events as
+ * possible. The channel will be reset and returned to the system at the end of
+ * the transaction.
+ *
+ * @param   req             Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req);
+
+/**
+ * @brief   Sets the TX data to transmit as a 'dummy' byte
+ *
+ * In single wire master mode, this data is transmitted on MOSI when performing
+ * an RX (MISO) only transaction. This defaults to 0.
+ *
+ * @param   spi             Pointer to SPI registers (selects the SPI block used.)
+ * @param   defaultTXData   Data to shift out in RX-only transactions
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData);
+
+/**
+ * @brief   Abort any asynchronous requests in progress.
+ *
+ * Abort any asynchronous requests in progress. Any callbacks associated with
+ * the active transaction will be executed to indicate when the transaction
+ * has been terminated.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ */
+void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi);
+
+/**
+ * @brief   The processing function for asynchronous transactions.
+ *
+ * When using the asynchronous functions, the application must call this
+ * function periodically. This can be done from within the SPI interrupt
+ * handler or periodically by the application if SPI interrupts are disabled.
+ *
+ * @param   spi         Pointer to SPI registers (selects the SPI block used.)
+ */
+void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi);
+
+/**@} end of group spi */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PT_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_sys.h

@@ -0,0 +1,208 @@
+/**
+ * @file    mxc_sys.h
+ * @brief   System level header file.
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_MXC_SYS_H_
+#define _MXC_MXC_SYS_H_
+
+#include "mxc_device.h"
+#include "gcr_regs.h"
+#include "mcr_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
+typedef enum {
+    MXC_SYS_RESET0_DMA       = MXC_F_GCR_RST0_DMA_POS,             /**< Reset DMA */
+    MXC_SYS_RESET0_WDT0      = MXC_F_GCR_RST0_WDT0_POS,            /**< Reset WDT */
+    MXC_SYS_RESET0_GPIO0     = MXC_F_GCR_RST0_GPIO0_POS,           /**< Reset GPIO0 */
+    MXC_SYS_RESET0_GPIO1     = MXC_F_GCR_RST0_GPIO1_POS,           /**< Reset GPIO1 */
+    MXC_SYS_RESET0_TMR0      = MXC_F_GCR_RST0_TMR0_POS,            /**< Reset TIMER0 */
+    MXC_SYS_RESET0_TMR1      = MXC_F_GCR_RST0_TMR1_POS,            /**< Reset TIMER1 */
+    MXC_SYS_RESET0_TMR2      = MXC_F_GCR_RST0_TMR2_POS,            /**< Reset TIMER2 */
+    MXC_SYS_RESET0_TMR3      = MXC_F_GCR_RST0_TMR3_POS,            /**< Reset TIMER3 */
+    MXC_SYS_RESET0_UART0     = MXC_F_GCR_RST0_UART0_POS,           /**< Reset UART0 */
+    MXC_SYS_RESET0_UART1     = MXC_F_GCR_RST0_UART1_POS,           /**< Reset UART1 */
+    MXC_SYS_RESET0_SPI0      = MXC_F_GCR_RST0_SPI0_POS,            /**< Reset SPI0 */
+    MXC_SYS_RESET0_SPI1      = MXC_F_GCR_RST0_SPI1_POS,            /**< Reset SPI1 */
+    MXC_SYS_RESET0_SPI2      = MXC_F_GCR_RST0_SPI2_POS,            /**< Reset SPI2 */
+    MXC_SYS_RESET0_I2C0      = MXC_F_GCR_RST0_I2C0_POS,            /**< Reset I2C0 */
+    MXC_SYS_RESET0_RTC       = MXC_F_GCR_RST0_RTC_POS,             /**< Reset RTC */
+    MXC_SYS_RESET0_TRNG      = MXC_F_GCR_RST0_TRNG_POS,            /**< Reset TRNG */
+    MXC_SYS_RESET0_UART2     = MXC_F_GCR_RST0_UART2_POS,           /**< Reset UART2 */
+    MXC_SYS_RESET0_SRST      = MXC_F_GCR_RST0_SOFT_POS,            /**< Soft reset */
+    MXC_SYS_RESET0_PRST      = MXC_F_GCR_RST0_PERIPH_POS,          /**< Peripheral reset */
+    MXC_SYS_RESET0_SYS       = MXC_F_GCR_RST0_SYS_POS,             /**< System reset */
+    /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
+    MXC_SYS_RESET1_I2C1      = (MXC_F_GCR_RST1_I2C1_POS + 32),     /**< Reset I2C1 */
+    MXC_SYS_RESET1_WDT1      = (MXC_F_GCR_RST1_WDT1_POS + 32),     /**< Reset WDT1 */
+    MXC_SYS_RESET1_AES       = (MXC_F_GCR_RST1_AES_POS + 32),      /**< Reset WDT1 */
+    MXC_SYS_RESET1_CRC       = (MXC_F_GCR_RST1_CRC_POS + 32),      /**< Reset WDT1 */
+    MXC_SYS_RESET1_I2C2      = (MXC_F_GCR_RST1_I2C2_POS + 32),     /**< Reset */
+    MXC_SYS_RESET1_I2S       = (MXC_F_GCR_RST1_I2S_POS + 32),      /**< Reset */
+    /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
+    MXC_SYS_RESET_TMR4       = (MXC_F_MCR_RST_LPTMR0_POS + 64),        /**< Reset TMR4 */
+    MXC_SYS_RESET_TMR5       = (MXC_F_MCR_RST_LPTMR1_POS + 64),        /**< Reset TMR5 */
+    MXC_SYS_RESET_UART3      = (MXC_F_MCR_RST_LPUART0_POS + 64),       /**< Reset UART3 */
+} mxc_sys_reset_t;
+
+/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
+typedef enum {
+    MXC_SYS_PERIPH_CLOCK_GPIO0       = MXC_F_GCR_PCLKDIS0_GPIO0_POS,                    /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
+    MXC_SYS_PERIPH_CLOCK_GPIO1       = MXC_F_GCR_PCLKDIS0_GPIO1_POS,                    /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
+    MXC_SYS_PERIPH_CLOCK_DMA         = MXC_F_GCR_PCLKDIS0_DMA_POS,                      /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
+    MXC_SYS_PERIPH_CLOCK_SPI0        = MXC_F_GCR_PCLKDIS0_SPI0_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
+    MXC_SYS_PERIPH_CLOCK_SPI1        = MXC_F_GCR_PCLKDIS0_SPI1_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
+    MXC_SYS_PERIPH_CLOCK_SPI2        = MXC_F_GCR_PCLKDIS0_SPI2_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */
+    MXC_SYS_PERIPH_CLOCK_UART0       = MXC_F_GCR_PCLKDIS0_UART0_POS,                    /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
+    MXC_SYS_PERIPH_CLOCK_UART1       = MXC_F_GCR_PCLKDIS0_UART1_POS,                    /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
+    MXC_SYS_PERIPH_CLOCK_I2C0        = MXC_F_GCR_PCLKDIS0_I2C0_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
+    MXC_SYS_PERIPH_CLOCK_TMR0        = MXC_F_GCR_PCLKDIS0_TMR0_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */
+    MXC_SYS_PERIPH_CLOCK_TMR1        = MXC_F_GCR_PCLKDIS0_TMR1_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */
+    MXC_SYS_PERIPH_CLOCK_TMR2        = MXC_F_GCR_PCLKDIS0_TMR2_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */
+    MXC_SYS_PERIPH_CLOCK_TMR3        = MXC_F_GCR_PCLKDIS0_TMR3_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
+    MXC_SYS_PERIPH_CLOCK_I2C1        = MXC_F_GCR_PCLKDIS0_I2C1_POS,                     /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
+    /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
+    MXC_SYS_PERIPH_CLOCK_UART2       = (MXC_F_GCR_PCLKDIS1_UART2_POS + 32),             /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
+    MXC_SYS_PERIPH_CLOCK_TRNG        = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32),              /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
+    MXC_SYS_PERIPH_CLOCK_WDT0        = (MXC_F_GCR_PCLKDIS1_WWDT0_POS + 32),             /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
+    MXC_SYS_PERIPH_CLOCK_WDT1        = (MXC_F_GCR_PCLKDIS1_WWDT1_POS + 32),             /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */
+    MXC_SYS_PERIPH_CLOCK_ICACHE      = (MXC_F_GCR_PCLKDIS1_ICC0_POS + 32),              /**< Disable MXC_F_GCR_PCLKDIS1_ICACHE clock */
+    MXC_SYS_PERIPH_CLOCK_CRC         = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32),               /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */
+    MXC_SYS_PERIPH_CLOCK_AES         = (MXC_F_GCR_PCLKDIS1_AES_POS + 32),               /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */
+    MXC_SYS_PERIPH_CLOCK_I2C2        = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32),              /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
+    MXC_SYS_PERIPH_CLOCK_I2S         = (MXC_F_GCR_PCLKDIS1_I2S_POS + 32),               /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
+    /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
+    MXC_SYS_PERIPH_CLOCK_TMR4        = (MXC_F_MCR_CLKDIS_LPTMR0_POS + 64),                  /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
+    MXC_SYS_PERIPH_CLOCK_TMR5        = (MXC_F_MCR_CLKDIS_LPTMR1_POS + 64),                  /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
+    MXC_SYS_PERIPH_CLOCK_UART3       = (MXC_F_MCR_CLKDIS_LPUART0_POS + 64),                 /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
+} mxc_sys_periph_clock_t;
+
+/** @brief Enumeration to select System Clock source */
+typedef enum {
+    MXC_SYS_CLOCK_IPO     = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO,
+    MXC_SYS_CLOCK_IBRO    = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO,
+    MXC_SYS_CLOCK_ERFO    = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO,
+    MXC_SYS_CLOCK_INRO    = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO,
+    MXC_SYS_CLOCK_ERTCO   = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO,
+    MXC_SYS_CLOCK_EXTCLK  = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK
+} mxc_sys_system_clock_t;
+
+#define MXC_SYS_USN_CHECKSUM_LEN    16
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief Reads the device USN.
+ * @param usn       Pointer to store the USN.
+ * @param checksum  Optional pointer to store the AES checksum.
+ * @returns       E_NO_ERROR if everything is successful.
+ */
+int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
+
+/**
+ * @brief Determines if the selected peripheral clock is enabled.
+ * @param clock   Enumeration for desired clock.
+ * @returns       0 is the clock is disabled, non 0 if the clock is enabled.
+ */
+int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock);
+
+/**
+ * @brief Disables the selected peripheral clock.
+ * @param clock   Enumeration for desired clock.
+ */
+void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock);
+
+/**
+ * @brief Enables the selected peripheral clock.
+ * @param clock   Enumeration for desired clock.
+ */
+void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock);
+
+/**
+ * @brief Enables the 32kHz oscillator
+ * @param mxc_sys_cfg   Not used, may be NULL.
+ */
+void MXC_SYS_RTCClockEnable (void);
+
+/**
+ * @brief Disables the 32kHz oscillator
+ * @returns         E_NO_ERROR if everything is successful
+ */
+int MXC_SYS_RTCClockDisable();
+
+/**
+ * @brief Enable System Clock Source without switching to it
+ * @param      clock The clock to enable
+ * @return     E_NO_ERROR if everything is successful
+ */
+int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock);
+
+/**
+ * @brief Disable System Clock Source
+ * @param      clock The clock to disable
+ * @return     E_NO_ERROR if everything is successful
+ */
+int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock);
+
+/**
+ * @brief Select the system clock.
+ * @param clock     Enumeration for desired clock.
+ * @param tmr       Optional tmr pointer for timeout. NULL if undesired.
+ * @returns         E_NO_ERROR if everything is successful.
+ */
+int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock);
+
+/**
+ * @brief Wait for a clock to enable with timeout
+ * @param      ready The clock to wait for
+ * @return     E_NO_ERROR if ready, E_TIME_OUT if timeout
+ */
+int MXC_SYS_Clock_Timeout (uint32_t ready);
+/**
+ * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register.
+ * @param           Enumeration for what to reset. Can reset multiple items at once.
+ */
+void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_MXC_SYS_H_*/

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/rtc.h

@@ -0,0 +1,205 @@
+/**
+ * @file    rtc.h
+ * @brief   Real Time Clock (RTC) functions and prototypes.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _RTC_H_
+#define _RTC_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "mxc_device.h"
+#include "rtc_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup rtc Real Time Clock (RTC)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+/**
+ * @brief   Bitmasks for each of the RTC's Frequency.
+ */
+typedef enum {
+    MXC_RTC_F_1HZ   = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ,   ///< 1Hz (Compensated)   
+    MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, ///< 512Hz (Compensated) 
+    MXC_RTC_F_4KHZ  = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ,  ///< 4Khz                
+    MXC_RTC_F_32KHZ = 32,                               ///< 32Khz               
+} mxc_rtc_freq_sel_t;
+
+/**
+ * @brief   Bitmasks for each of the RTC's interrupt enables.
+ */
+typedef enum {
+    MXC_RTC_INT_EN_LONG  = MXC_F_RTC_CTRL_TOD_ALARM_IE,     ///< Long-interval alarm interrupt enable 
+    MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IE,    ///< Short-interval alarm interrupt enable 
+    MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE,           ///< Timer ready interrupt enable 
+} mxc_rtc_int_en_t;
+
+/**
+ * @brief     Bitmasks for each of the RTC's interrupt flags.
+ */
+typedef enum {
+    MXC_RTC_INT_FL_LONG  = MXC_F_RTC_CTRL_TOD_ALARM,        ///< Long-interval alarm interrupt flag 
+    MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM,       ///< Short-interval alarm interrupt flag 
+    MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY,              ///< Timer ready interrupt flag 
+} mxc_rtc_int_fl_t;
+
+/**
+ * @brief     Set Time-of-Day alarm value and enable Interrupt
+ * @param     ras    20-bit value 0-0xFFFFF
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_SetTimeofdayAlarm (uint32_t ras);
+
+/**
+ * @brief     Set Sub-Second alarm value and enable interrupt,
+ * @brief     this is to be called after the init_rtc() function
+ * @param     rssa   32-bit value 0-0xFFFFFFFF
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_SetSubsecondAlarm (uint32_t rssa);
+
+/**
+ * @brief     Start the Real Time Clock (Blocking function)
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_Start (void);
+/**
+ * @brief     Stop the Real Time Clock (Blocking function)
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_Stop (void);
+
+/**
+ * @brief     Initialize the sec and ssec registers and enable RTC (Blocking function)
+ * @param     sec    set the RTC Sec counter (32-bit)
+ * @param     ssec   set the RTC Sub-second counter (8-bit)
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_Init (uint32_t sec, uint8_t ssec);
+
+/**
+ * @brief     Allow generation of Square Wave on the SQW pin (Blocking function)
+ * @param     fq     Frequency output selection
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq);
+                             
+/**
+ * @brief     Stop the generation of square wave (Blocking function)
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_SquareWaveStop (void);
+
+/**
+ * @brief     Set Trim register value (Blocking function)
+ * @param     trm    set the RTC Trim (8-bit, +/- 127)
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_Trim (int8_t trm);
+
+/**
+ * @brief     Enable Interurpts (Blocking function)
+ * @param     mask   The bitwise OR of interrupts to enable.
+ *                   See #mxc_rtc_int_en_t for available choices.
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_EnableInt (uint32_t mask);
+
+/**
+ * @brief     Disable Interurpts (Blocking function)
+ * @param     mask   The mask of interrupts to disable.
+ *                   See #mxc_rtc_int_en_t for available choices.
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_DisableInt (uint32_t mask);
+
+/**
+ * @brief     Gets interrupt flags.
+ * @retval    The bitwise OR of any interrupts flags that are
+ *            currently set. See \ref mxc_rtc_int_fl_t for the list
+ *            of possible flags.
+ */
+int MXC_RTC_GetFlags (void);
+
+/**
+ * @brief     Clear interrupt flags.
+ * @param     flags The bitwise OR of the interrupts flags to cleear.
+ *            See #mxc_rtc_int_fl_t for the list of possible flags.
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_ClearFlags (int flags);
+
+/**
+ * @brief     Get SubSecond
+ * @retval    Returns subsecond value or E_BUSY, see /ref MXC_ERROR_CODES
+ */
+int MXC_RTC_GetSubSecond (void);
+
+/**
+ * @brief     Get Second
+ * @retval    returns second value or E_BUSY, see /ref MXC_ERROR_CODES
+ */
+int MXC_RTC_GetSecond (void);
+
+/**
+ * @brief     Get the time using nuclear fusion. Or atomically. Something like that.
+ * @param     sec pointer to store seconds value
+ * @param     subsec pointer to store subseconds value
+ * @retval    returns Success or Fail, see \ref MXC_Error_Codes
+ */
+int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec);
+
+/**
+ * @brief     Get RTC busy flag.
+ * @retval    returns Success or E_BUSY, see /ref MXC_ERROR_CODES
+ */
+int MXC_RTC_GetBusyFlag(void);
+
+/**@} end of group rtc */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTC_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/tmr.h

@@ -0,0 +1,364 @@
+/**
+ * @file    tmr.h
+ * @brief   Timer (TMR) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _TMR_H_
+#define _TMR_H_
+
+/* **** Includes **** */
+#include "mxc_device.h"
+#include "tmr_regs.h"
+#include "mxc_sys.h"
+#include "gcr_regs.h"
+#include "mcr_regs.h"
+#include "stdbool.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup tmr Timer (TMR)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/**
+ * @brief Timer prescaler values
+ */
+typedef enum {
+    TMR_PRES_1      = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1,           ///< Divide input clock by 1 
+    TMR_PRES_2      = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2,           ///< Divide input clock by 2 
+    TMR_PRES_4      = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4,           ///< Divide input clock by 4  
+    TMR_PRES_8      = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8,           ///< Divide input clock by 8 
+    TMR_PRES_16     = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16,          ///< Divide input clock by 16 
+    TMR_PRES_32     = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32,          ///< Divide input clock by 32 
+    TMR_PRES_64     = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64,          ///< Divide input clock by 64 
+    TMR_PRES_128    = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128,         ///< Divide input clock by 128 
+    TMR_PRES_256    = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256,         ///< Divide input clock by 256 
+    TMR_PRES_512    = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512,         ///< Divide input clock by 512 
+    TMR_PRES_1024   = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024,        ///< Divide input clock by 1024 
+    TMR_PRES_2048   = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048,        ///< Divide input clock by 2048 
+    TMR_PRES_4096   = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096         ///< Divide input clock by 4096 
+} mxc_tmr_pres_t;
+
+/**
+ * @brief Timer modes
+ */
+typedef enum {
+    TMR_MODE_ONESHOT          = MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT,      ///< Timer Mode ONESHOT 
+    TMR_MODE_CONTINUOUS       = MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS,    ///< Timer Mode CONTINUOUS 
+    TMR_MODE_COUNTER          = MXC_S_TMR_CTRL0_MODE_A_COUNTER,       ///< Timer Mode COUNTER 
+    TMR_MODE_PWM              = MXC_S_TMR_CTRL0_MODE_A_PWM,           ///< Timer Mode PWM 
+    TMR_MODE_CAPTURE          = MXC_S_TMR_CTRL0_MODE_A_CAPTURE,       ///< Timer Mode CAPTURE 
+    TMR_MODE_COMPARE          = MXC_S_TMR_CTRL0_MODE_A_COMPARE,       ///< Timer Mode COMPARE 
+    TMR_MODE_GATED            = MXC_S_TMR_CTRL0_MODE_A_GATED,         ///< Timer Mode GATED 
+    TMR_MODE_CAPTURE_COMPARE  = MXC_S_TMR_CTRL0_MODE_A_CAPCOMP        ///< Timer Mode CAPTURECOMPARE 
+} mxc_tmr_mode_t;
+
+/**
+ * @brief Timer bit mode 
+ * 
+ */
+typedef enum {
+    TMR_BIT_MODE_32,            ///< Timer Mode 32 bit  
+    TMR_BIT_MODE_16A,           ///< Timer Mode Lower 16 bit 
+    TMR_BIT_MODE_16B,           ///< Timer Mode Upper 16 bit 
+} mxc_tmr_bit_mode_t;
+
+/**
+ * @brief Timer units of time enumeration
+ */
+typedef enum {
+    TMR_UNIT_NANOSEC,           ///< Nanosecond Unit Indicator 
+    TMR_UNIT_MICROSEC,          ///< Microsecond Unit Indicator 
+    TMR_UNIT_MILLISEC,          ///< Millisecond Unit Indicator 
+    TMR_UNIT_SEC,               ///< Second Unit Indicator 
+} mxc_tmr_unit_t;
+
+/**
+ * @brief       Clock settings 
+ * @note        8M and 32M clocks can be used for Timers 0,1,2 and 3
+ *              32K and 80K clocks can only be used for Timers 4 and 5
+ */
+typedef enum {
+    MXC_TMR_APB_CLK,            ///< PCLK CLock                               
+    MXC_TMR_EXT_CLK,            ///< External Clock
+    MXC_TMR_8M_CLK ,            ///< 8MHz Clock
+    MXC_TMR_32M_CLK,            ///< 32MHz Clock
+    MXC_TMR_32K_CLK,            ///< 32KHz Clock
+    MXC_TMR_80K_CLK,            ///< 80KHz Clock                    
+} mxc_tmr_clock_t;
+
+/**
+ * @brief Timer Configuration
+ */
+typedef struct {
+    mxc_tmr_pres_t pres;           ///< Desired timer prescaler 
+    mxc_tmr_mode_t mode;           ///< Desired timer mode 
+    mxc_tmr_bit_mode_t bitMode;    ///< Desired timer bits  
+    mxc_tmr_clock_t clock;         ///< Desired clock source 
+    uint32_t cmp_cnt;              ///< Compare register value in timer ticks 
+    unsigned pol;                  ///< Polarity (0 or 1) 
+} mxc_tmr_cfg_t;
+
+/* **** Definitions **** */
+typedef void (*mxc_tmr_complete_t) (int error);
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief   Initialize timer module clock.
+ * @param   tmr        Pointer to timer module to initialize.
+ * @param   cfg        System configuration object
+ * @param   init_pins  True will initialize pins corresponding to the TMR and False will not if pins are pinned out otherwise it will not
+ *                     be used 
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg, bool init_pins);
+
+/**
+ * @brief   Shutdown timer module clock.
+ * @param   tmr  Pointer to timer module to initialize.
+ */
+void MXC_TMR_Shutdown (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Start the timer counting.
+ * @param   tmr  Pointer to timer module to initialize.
+ */
+void MXC_TMR_Start (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Stop the timer.
+ * @param   tmr  Pointer to timer module to initialize.
+ */
+void MXC_TMR_Stop (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Set the value of the first transition in PWM mode
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   pwm     New pwm count.
+ * @note    Will block until safe to change the period count.
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_TMR_SetPWM (mxc_tmr_regs_t* tmr, uint32_t pwm);
+
+/**
+ * @brief   Get the timer compare count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the current compare count.
+ */
+uint32_t MXC_TMR_GetCompare (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Get the timer capture count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the most recent capture count.
+ */
+uint32_t MXC_TMR_GetCapture (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Get the timer count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the current count.
+ */
+uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Calculate count for required frequency.
+ * @param   tmr         Timer
+ * @param   clock       Clock source.
+ * @param   prescalar   prescalar
+ * @param   frequency   required frequency.
+ * @return  Returns the period count.
+ */
+uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency);
+
+/**
+ * @brief   Clear the timer interrupt.
+ * @param   tmr     Pointer to timer module to initialize.
+ */
+void MXC_TMR_ClearFlags (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Get the timer interrupt status.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the interrupt status. 1 if interrupt has occured.
+ */
+uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   enable interupt
+ *
+ * @param   tmr   Pointer to timer module to initialize.
+ */
+void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   disable interupt
+ *
+ * @param   tmr   Pointer to timer module to initialize.
+ */
+void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Enable wakeup from sleep
+ * 
+ * @param   tmr   Pointer to timer module to initialize.
+ * @param   cfg   System configuration object  
+ */
+void MXC_TMR_EnableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg);
+
+/**
+ * @brief   Disable wakeup from sleep
+ * 
+ * @param   tmr   Pointer to timer module to initialize.
+ * @param   cfg   System configuration object
+ */
+void MXC_TMR_DisableWakeup (mxc_tmr_regs_t* tmr, mxc_tmr_cfg_t* cfg);
+
+/**
+ * @brief   Set the timer compare count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   cmp_cnt New compare count.
+ * @note    In PWM Mode use this to set the value of the second transition.
+ */
+void MXC_TMR_SetCompare (mxc_tmr_regs_t *tmr, uint32_t cmp_cnt);
+
+/**
+ * @brief   Set the timer count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   cnt     New count.
+ */
+void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt);
+
+/**
+ * @brief   Dealay for a set periord of time measured in microseconds
+ *
+ * @param   tmr   The timer
+ * @param   us    microseconds to delay for
+ */
+void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us);
+
+/**
+ * @brief   Start a timer that will time out after a certain number of microseconds
+ * @note    This uses the 32-it Timer
+ * 
+ * @param   tmr   The timer
+ * @param   us    microseconds to time out after
+ */
+void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us);
+
+/**
+ * @brief   Check on time out timer
+ *
+ * @param   tmr   The timer
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_TMR_TO_Check (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Stop the Timeout timer
+ *
+ * @param   tmr   The timer
+ */
+void MXC_TMR_TO_Stop (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Clear timeout timer back to zero
+ *
+ * @param   tmr   The timer
+ */
+void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Get elapsed time of timeout timer
+ *
+ * @param   tmr   The timer
+ *
+ * @return  Time that has elapsed in timeout timer
+ */
+unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Amount of time remaining until timeour
+ *
+ * @param   tmr   The timer
+ *
+ * @return  Time that is left until timeout
+ */
+unsigned int MXC_TMR_TO_Remaining (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Start stopwatch
+ *
+ * @param   tmr      The timer
+ */
+void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Stopwatch stop
+ *
+ * @param   tmr   The timer
+ *
+ * @return  the time when the stopwatch is stopped.
+ */
+unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief   Get time from timer
+ *
+ * @param   tmr    The timer
+ * @param   ticks  The ticks
+ * @param   time   The time
+ * @param   units  The units
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units);
+
+/**@} end of group tmr */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TMR_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/trng.h

@@ -0,0 +1,137 @@
+/**
+ * @file    trng.h
+ * @brief   Random number generator driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#ifndef _TRNG_H_
+#define _TRNG_H_
+
+/***** Includes *****/
+#include "trng_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup trng TRNG
+ * @ingroup periphlibs
+ * @{
+ */
+
+
+/***** Function Prototypes *****/
+typedef void (*mxc_trng_complete_t) (void* req, int result);
+
+/* ************************************************************************* */
+/* Global Control/Configuration functions                                    */
+/* ************************************************************************* */
+
+/**
+ * @brief   Enable portions of the TRNG
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_TRNG_Init (void);
+
+/**
+ * @brief   Enable TRNG Interrupts
+ *
+ */
+void MXC_TRNG_EnableInt ();
+
+/**
+ * @brief   Disable TRNG Interrupts
+ *
+ */
+void MXC_TRNG_DisableInt ();
+
+/**
+ * @brief   Disable and reset portions of the TRNG
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_TRNG_Shutdown (void);
+
+/**
+ * @brief   This function should be called from the TRNG ISR Handler
+ *          when using Async functions
+ */
+void MXC_TRNG_Handler (void);
+
+/* ************************************************************************* */
+/* True Random Number Generator (TRNG) functions                             */
+/* ************************************************************************* */
+
+/**
+ * @brief   Get a random number
+ *
+ * @return  A random 32-bit number
+ */
+int MXC_TRNG_RandomInt (void);
+
+/**
+ * @brief   Get a random number of length len
+ *
+ * @param   data    Pointer to a location to store the number
+ * @param   len     Length of random number in bytes
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_TRNG_Random (uint8_t* data, uint32_t len);
+
+/**
+ * @brief   Get a random number of length len, do not block while generating data
+ * @note    The user must call MXC_TRNG_Handler() in the ISR
+ *
+ * @param   data      Pointer to a location to store the number
+ * @param   len       Length of random number in bytes
+ * @param   callback  Function that will be called when all data has been generated
+ *
+ */
+void MXC_TRNG_RandomAsync (uint8_t* data, uint32_t len, mxc_trng_complete_t callback);
+
+/**
+ * @brief   Generate an AES key and transfer to the AES block
+ */
+void MXC_TRNG_GenerateKey(void);
+
+#ifdef __cplusplus
+}
+#endif
+/**@} end of group trng */
+
+#endif  /* _TRNG_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/uart.h

@@ -0,0 +1,681 @@
+/**
+ * @file    uart.h
+ * @brief   Serial Peripheral Interface (UART) communications driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+ 
+ /* Define to prevent redundant inclusion */
+#ifndef _MXC_UART_H_
+#define _MXC_UART_H_
+
+/***** Definitions *****/
+#include "uart_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup uart UART
+ * @ingroup periphlibs
+ * @{
+ */
+
+typedef struct _mxc_uart_req_t mxc_uart_req_t;
+/**
+ * @brief   The list of UART stop bit lengths supported
+ * 
+ */
+typedef enum {
+    MXC_UART_STOP_1,    ///< UART Stop 1 clock cycle 
+    MXC_UART_STOP_2,    ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters)
+} mxc_uart_stop_t;
+
+/**
+ * @brief   The list of UART Parity options supported
+ * 
+ */
+typedef enum {
+    MXC_UART_PARITY_DISABLE,    ///< UART Parity Disabled
+    MXC_UART_PARITY_EVEN_0,     ///< UART Parity Even, 0 based
+    MXC_UART_PARITY_EVEN_1,     ///< UART Parity Even, 1 based
+    MXC_UART_PARITY_ODD_0,      ///< UART Parity Odd, 0 based
+    MXC_UART_PARITY_ODD_1,      ///< UART Parity Odd, 1 based
+} mxc_uart_parity_t;
+
+/**
+ * @brief   The list of UART flow control options supported
+ * 
+ */
+typedef enum {
+    MXC_UART_FLOW_DIS,      ///< UART Flow Control Disabled
+    MXC_UART_FLOW_EN,       ///< UART Flow Control Enabled
+} mxc_uart_flow_t;
+
+/**
+ * @brief      Clock settings */
+typedef enum {
+    MXC_UART_APB_CLK = 0,                                          
+    MXC_UART_EXT_CLK = 1,              
+    /*8M (IBRO) and 32M (EFRO) clocks can be used for UARTs 0,1 and 2*/
+    MXC_UART_IBRO_CLK = 2,  
+    MXC_UART_ERFO_CLK = 3,
+    /*32K (ERTCO) and INRO clocks can only be used for UART3*/
+    MXC_UART_ERTCO_CLK = 4,
+    MXC_UART_INRO_CLK = 5,                   
+} mxc_uart_clock_t;
+
+/**
+ * @brief   The callback routine used to indicate the transaction has terminated.
+ *
+ * @param   req          The details of the transaction.
+ * @param   result       See \ref MXC_Error_Codes for the list of error codes.
+ */
+typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t* req, int result);
+
+/**
+ * @brief   The callback routine used to indicate the transaction has terminated.
+ *
+ * @param   req          The details of the transaction.
+ * @param   num          The number of characters actually copied
+ * @param   result       See \ref MXC_Error_Codes for the list of error codes.
+ */
+typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t* req, int num, int result);
+
+/**
+ * @brief   The information required to perform a complete UART transaction
+ *
+ * This structure is used by blocking, async, and DMA based transactions.
+ * @note    "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions.
+ */
+struct _mxc_uart_req_t {
+    mxc_uart_regs_t* uart;      ///<Point to UART registers
+    const uint8_t  *txData;     ///< Buffer containing transmit data. For character sizes
+                                ///< < 8 bits, pad the MSB of each byte with zeros. For 
+                                ///< character sizes > 8 bits, use two bytes per character
+                                ///< and pad the MSB of the upper byte with zeros
+    uint8_t        *rxData;     ///< Buffer to store received data For character sizes
+                                ///< < 8 bits, pad the MSB of each byte with zeros. For 
+                                ///< character sizes > 8 bits, use two bytes per character
+                                ///< and pad the MSB of the upper byte with zeros
+    uint32_t        txLen;      ///< Number of bytes to be sent from txData
+    uint32_t        rxLen;      ///< Number of bytes to be stored in rxData
+    volatile uint32_t        txCnt;      ///< Number of bytes actually transmitted from txData
+    volatile uint32_t        rxCnt;      ///< Number of bytes stored in rxData
+
+    mxc_uart_complete_cb_t callback;  ///< Pointer to function called when transaction is complete
+};
+
+/***** Function Prototypes *****/
+
+/* ************************************************************************* */
+/* Control/Configuration functions                                           */
+/* ************************************************************************* */
+
+/**
+ * @brief   Initialize and enable UART peripheral.
+ * 
+ * This function initializes everything necessary to call a UART transaction function.
+ * Some parameters are set to defaults as follows:
+ * UART Data Size    - 8 bits
+ * UART Stop Bits    - 1 bit
+ * UART Parity       - None
+ * UART Flow Control - None
+ * 
+ * These parameters can be modified after initialization using low level functions
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   baud         The requested clock frequency. The actual clock frequency
+ *                       will be returned by the function if successful.
+ * @param   clock        Clock source
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_Init(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock, sys_map_t map);
+
+/**
+ * @brief   Disable and shutdown UART peripheral.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_Shutdown(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Checks if the given UART bus can be placed in sleep more.
+ *
+ * @note    This functions checks to see if there are any on-going UART transactions in
+ *          progress. If there are transactions in progress, the application should
+ *          wait until the UART bus is free before entering a low-power state.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  #E_NO_ERROR if ready, and non-zero if busy or error. See \ref
+ *          MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_ReadyForSleep(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Set the frequency of the UART interface.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   baud         The desired baud rate
+ * @param   clock        Clock source
+ *
+ * @return  Negative if error, otherwise actual speed set. See \ref
+ *          MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_SetFrequency(mxc_uart_regs_t* uart, unsigned int baud, mxc_uart_clock_t clock);
+
+/**
+ * @brief   Get the frequency of the UART interface.
+ *
+ * @note    This function is applicable in Master mode only
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  The UART baud rate
+ */
+int MXC_UART_GetFrequency(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Sets the number of bits per character
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   dataSize     The number of bits per character (5-8 bits/character are valid)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_SetDataSize(mxc_uart_regs_t* uart, int dataSize);
+
+/**
+ * @brief   Sets the number of stop bits sent at the end of a character
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   stopBits     The number of stop bits used
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_SetStopBits(mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits);
+
+/**
+ * @brief   Sets the type of parity generation used
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   parity       see \ref UART Parity Types for details
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_SetParity(mxc_uart_regs_t* uart, mxc_uart_parity_t parity);
+
+/**
+ * @brief   Sets the flow control used
+ * 
+ * @param   uart            Pointer to UART registers (selects the UART block used.)
+ * @param   flowCtrl        see \ref UART Flow Control Types for details
+ * @param   rtsThreshold    Number of bytes remaining in the RX FIFO when RTS is asserted
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_SetFlowCtrl(mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold, sys_map_t map);
+
+/**
+ * @brief   Sets the clock source for the baud rate generator
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   clock        Clock source
+ *
+ * @return  Actual baud rate if successful, otherwise see \ref MXC_Error_Codes 
+ *          for a list of return codes.
+ */
+int MXC_UART_SetClockSource(mxc_uart_regs_t* uart, mxc_uart_clock_t clock);
+
+/* ************************************************************************* */
+/* Low-level functions                                                       */
+/* ************************************************************************* */
+
+/**
+ * @brief   Checks the UART Peripheral for an ongoing transmission
+ *
+ * @note    This function is applicable in Master mode only
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  Active/Inactive, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_GetActive(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Aborts an ongoing UART Transmission
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_AbortTransmission(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Reads the next available character. If no character is available, this function
+ *          will return an error.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Writes a character on the UART. If the character cannot be written because the
+ *          transmit FIFO is currently full, this function returns an error.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   character         The character to write
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character);
+
+/**
+ * @brief   Reads the next available character
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_ReadCharacter(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Writes a character on the UART
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   character    The character to write 
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character);
+
+/**
+ * @brief   Reads the next available character
+ * @note    This function blocks until len characters are received
+ *          See MXC_UART_TransactionAsync() for a non-blocking version
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   buffer       Buffer to store data in
+ * @param   len          Number of characters 
+ *
+ * @return  The character read, otherwise see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_Read(mxc_uart_regs_t* uart, uint8_t* buffer, int* len);
+
+/**
+ * @brief   Writes a byte on the UART
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   byte         The buffer of characters to write 
+ * @param   len          The number of characters to write
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_Write(mxc_uart_regs_t* uart, const uint8_t* byte, int* len);
+
+/**
+ * @brief   Unloads bytes from the receive FIFO.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   bytes        The buffer to read the data into.
+ * @param   len          The number of bytes to read.
+ *
+ * @return  The number of bytes actually read.
+ */
+unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t* uart, unsigned char* bytes,
+                                    unsigned int len);
+
+/**
+ * @brief   Unloads bytes from the receive FIFO user DMA for longer reads.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   bytes        The buffer to read the data into.
+ * @param   len          The number of bytes to read.
+ * @param   callback     The function to call when the read is complete
+ *
+ * @return  See \ref MXC_ERROR_CODES for a list of return values
+ */
+int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t* uart, unsigned char* bytes,
+                            unsigned int len, mxc_uart_dma_complete_cb_t callback);
+
+/**
+ * @brief   Get the number of bytes currently available in the receive FIFO.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  The number of bytes available.
+ */
+unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Loads bytes into the transmit FIFO.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   bytes        The buffer containing the bytes to write
+ * @param   len          The number of bytes to write.
+ *
+ * @return  The number of bytes actually written.
+ */
+unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t* uart, const unsigned char* bytes,
+                                    unsigned int len);
+
+/**
+ * @brief   Loads bytes into the transmit FIFO using DMA for longer writes
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   bytes        The buffer containing the bytes to write
+ * @param   len          The number of bytes to write.
+ * @param   callback     The function to call when the write is complete
+ *
+ * @return  See \ref MXC_ERROR_CODES for a list of return values
+ */
+int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t* uart, const unsigned char* bytes,
+                                unsigned int len, mxc_uart_dma_complete_cb_t callback);
+
+/**
+ * @brief   Get the amount of free space available in the transmit FIFO.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ *
+ * @return  The number of bytes available.
+ */
+unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Removes and discards all bytes currently in the receive FIFO.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_ClearRXFIFO(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Removes and discards all bytes currently in the transmit FIFO.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_ClearTXFIFO(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Set the receive threshold level.
+ * 
+ * @note    RX FIFO Receive threshold. Smaller values will cause
+ *          interrupts to occur more often, but reduce the possibility
+ *          of losing data because of a FIFO overflow. Larger values
+ *          will reduce the time required by the ISR, but increase the 
+ *          possibility of data loss. Passing an invalid value will
+ *          cause the driver to use the value already set in the 
+ *          appropriate register.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   numBytes     The threshold level to set. This value must be
+ *                       between 0 and 8 inclusive.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_SetRXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes);
+
+/**
+ * @brief   Get the current receive threshold level.
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  The receive threshold value (in bytes).
+ */
+unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Set the transmit threshold level.
+ * 
+ * @note    TX FIFO threshold. Smaller values will cause interrupts
+ *          to occur more often, but reduce the possibility of terminating
+ *          a transaction early in master mode, or transmitting invalid data
+ *          in slave mode. Larger values will reduce the time required by
+ *          the ISR, but increase the possibility errors occurring. Passing 
+ *          an invalid value will cause the driver to use the value already 
+ *          set in the appropriate register.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   numBytes     The threshold level to set.  This value must be
+ *                       between 0 and 8 inclusive.
+ *
+ * @return  Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_UART_SetTXThreshold(mxc_uart_regs_t* uart, unsigned int numBytes);
+
+/**
+ * @brief   Get the current transmit threshold level.
+ * 
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  The transmit threshold value (in bytes).
+ */
+unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Gets the interrupt flags that are currently set
+ *
+ * @note    These functions should not be used while using non-blocking Transaction Level 
+ *          functions (Async or DMA)
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return The interrupt flags
+ */
+unsigned int MXC_UART_GetFlags(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Clears the interrupt flags that are currently set
+ *
+ * @note    These functions should not be used while using non-blocking Transaction Level 
+ *          functions (Async or DMA)
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   flags        mask of flags to clear
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_ClearFlags(mxc_uart_regs_t* uart, unsigned int flags);
+
+/**
+ * @brief   Enables specific interrupts
+ *
+ * @note    These functions should not be used while using non-blocking Transaction Level 
+ *          functions (Async or DMA)
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   mask         The interrupts to be enabled
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_EnableInt(mxc_uart_regs_t* uart, unsigned int mask);
+
+/**
+ * @brief   Disables specific interrupts
+ *
+ * @note    These functions should not be used while using non-blocking Transaction Level 
+ *          functions (Async or DMA)
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * @param   mask         The interrupts to be disabled
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_DisableInt(mxc_uart_regs_t* uart, unsigned int mask);
+
+/**
+ * @brief   Gets the status flags that are currently set
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  The status flags
+ */
+unsigned int MXC_UART_GetStatus(mxc_uart_regs_t* uart);
+
+/* ************************************************************************* */
+/* Transaction level functions                                               */
+/* ************************************************************************* */
+
+/**
+ * @brief   Performs a blocking UART transaction.   
+ * 
+ * @note    Performs a blocking UART transaction as follows.
+ *          If tx_len is non-zero, transmit TX data
+ *          Once tx_len has been sent, if rx_len is non-zero, receive data
+ *
+ * @param   req          Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_Transaction(mxc_uart_req_t* req);
+
+/**
+ * @brief   Setup an interrupt-driven UART transaction
+ * 
+ * @note    The TX FIFO will be filled with txData if necessary
+ *          Relevant interrupts will be enabled
+ *
+ * @param   req          Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_TransactionAsync(mxc_uart_req_t* req);
+
+/**
+ * @brief   Setup a DMA driven UART transaction
+ * 
+ * @note    The TX FIFO will be filled with txData if necessary
+ *          Relevant interrupts will be enabled
+ *          The DMA channel indicated by the request will be set up to load/unload the FIFOs 
+ *          with as few interrupt-based events as possible. The channel will be reset and 
+ *          returned to the system at the end of the transaction.
+ *
+ * @param   req          Pointer to details of the transaction
+ *
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_TransactionDMA(mxc_uart_req_t* req);
+
+/**
+ * @brief   The processing function for DMA transactions.
+ * 
+ * When using the DMA functions, the application must call this
+ * function periodically. This can be done from within the DMA Interrupt Handler.
+ *
+ * @param   ch          DMA channel
+ * @param   error       Error status
+ */
+void MXC_UART_DMACallback (int ch, int error);
+
+/**
+ * @brief   Async callback 
+ *
+ * @param   uart      The uart
+ * @param   retVal    The ret value
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal);
+
+/**
+ * @brief   stop any async callbacks
+ *
+ * @param   uart      The uart
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_AsyncStop (mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Abort any asynchronous requests in progress.
+ *
+ * @note    Abort any asynchronous requests in progress. Any callbacks associated with
+ *          the active transaction will be executed to indicate when the transaction
+ *          has been terminated.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_AbortAsync(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   The processing function for asynchronous transactions.
+ *
+ * @note    When using the asynchronous functions, the application must call this
+ *          function periodically. This can be done from within the UART interrupt
+ *          handler or periodically by the application if UART interrupts are disabled.
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  See \ref MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_UART_AsyncHandler(mxc_uart_regs_t* uart);
+
+/**
+ * @brief   Provide TXCount for asynchronous transactions..
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  Returns transmit bytes (in FIFO).
+ */
+uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t* req);
+
+/**
+ * @brief   Provide RXCount for asynchronous transactions..
+ *
+ * @param   uart         Pointer to UART registers (selects the UART block used.)
+ * 
+ * @return  Returns receive bytes (in FIFO).
+ */
+uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t* req);
+
+/**@} end of group uart */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_UART_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/wdt.h

@@ -0,0 +1,224 @@
+/**
+ * @file    wdt.h
+ * @brief   Watchdog timer (WDT) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _WDT_H_
+#define _WDT_H_
+
+#ifdef __CC_ARM 
+#pragma diag_suppress 66  // enumeration value is out of "int" range
+#endif
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "mxc_device.h"
+#include "wdt_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup wdt WDT
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/** @brief Watchdog upper limit period enumeration.
+    Used to configure the period of the watchdog interrupt */
+typedef enum {
+    MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31, ///< Period 2^31 
+    MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30, ///< Period 2^30 
+    MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29, ///< Period 2^29 
+    MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28, ///< Period 2^28 
+    MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27, ///< Period 2^27 
+    MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26, ///< Period 2^26 
+    MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25, ///< Period 2^25 
+    MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24, ///< Period 2^24 
+    MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23, ///< Period 2^23 
+    MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22, ///< Period 2^22 
+    MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21, ///< Period 2^21 
+    MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20, ///< Period 2^20 
+    MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19, ///< Period 2^19 
+    MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18, ///< Period 2^18 
+    MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17, ///< Period 2^17 
+    MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16, ///< Period 2^16 
+} mxc_wdt_period_t;
+
+/**
+ * @brief Watchdog interrupt flag enumeration
+ */
+typedef enum {
+    MXC_WDT_INT_TOO_LATE = MXC_F_WDT_CTRL_INT_LATE,
+    MXC_WDT_INT_TOO_SOON = MXC_F_WDT_CTRL_INT_EARLY,
+} mxc_wdt_int_t;
+
+/**
+ * @brief Watchdog reset flag enumeration
+ */
+typedef enum {
+    MXC_WDT_RST_TOO_LATE = MXC_F_WDT_CTRL_RST_LATE,
+    MXC_WDT_RST_TOO_SOON = MXC_F_WDT_CTRL_RST_EARLY,
+} mxc_wdt_rst_t;
+
+/**
+ * @brief Watchdog mode enumeration
+ */
+typedef enum {
+    MXC_WDT_COMPATIBILITY = 0,
+    MXC_WDT_WINDOWED = 1,
+} mxc_wdt_mode_t;
+
+/**
+ * @brief Timer Configuration
+ */
+typedef struct {
+    mxc_wdt_mode_t   mode;               ///< WDT mode
+    mxc_wdt_period_t upperResetPeriod;   ///< Reset upper limit
+    mxc_wdt_period_t lowerResetPeriod;   ///< Reset lower limit
+    mxc_wdt_period_t upperIntPeriod;     ///< Interrupt upper limit
+    mxc_wdt_period_t lowerIntPeriod;     ///< Interrupt lower limit
+} mxc_wdt_cfg_t;
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize the Watchdog Timer
+ * @param       wdt     Pointer to the watchdog registers
+ * @param       cfg     watchdog configuration
+ * @return      See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_WDT_Init (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg);
+
+/**
+ * @brief Shutdown the Watchdog Timer
+ * @param       wdt     Pointer to the watchdog registers
+ * @return      See \ref MXC_Error_Codes for the list of error codes.
+ */
+int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Set the period of the watchdog interrupt.
+ * @param       wdt     Pointer to watchdog registers.
+ * @param       cfg     watchdog configuration.
+ */
+void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg);
+
+/**
+ * @brief       Set the period of the watchdog reset.
+ * @param       wdt     Pointer to watchdog registers.
+ * @param       cfg     watchdog configuration.
+ */
+void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_cfg_t *cfg);
+
+/**
+ * @brief       Enable the watchdog timer.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_Enable (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Disable the watchdog timer.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_Disable (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Enable the watchdog interrupt.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Disable the watchdog interrupt.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Enable the watchdog reset.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Disable the watchdog reset.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Reset the watchdog timer.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Get the status of the reset flag.
+ * @param       wdt     Pointer to watchdog registers.
+ * @returns     1 if the previous reset was caused by the watchdog, 0 otherwise.
+ */
+int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Clears the reset flag.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Get the status of the interrupt flag.
+ * @param       wdt     Pointer to watchdog registers.
+ * @returns     1 if the interrupt is pending, 0 otherwise.
+ */
+int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Clears the interrupt flag.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt);
+
+/**@} end of group wdt */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WDT_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_key_revb_regs.h

@@ -0,0 +1,120 @@
+/**
+ * @file    aes_key_revb_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _AES_KEY_REVB_REGS_H_
+#define _AES_KEY_REVB_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     aes_key_revb
+ * @defgroup    aes_key_revb_registers AES_KEY_REVB_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the AES_KEY_REVB Peripheral Module.
+ * @details AES Key Registers.
+ */
+
+/**
+ * @ingroup aes_key_revb_registers
+ * Structure type to access the AES_KEY_REVB Registers.
+ */
+typedef struct {
+    __IO uint32_t aes_key0;             /**< <tt>\b 0x00:</tt> AES_KEY_REVB AES_KEY0 Register */
+    __IO uint32_t aes_key1;             /**< <tt>\b 0x04:</tt> AES_KEY_REVB AES_KEY1 Register */
+    __IO uint32_t aes_key2;             /**< <tt>\b 0x08:</tt> AES_KEY_REVB AES_KEY2 Register */
+    __IO uint32_t aes_key3;             /**< <tt>\b 0x0C:</tt> AES_KEY_REVB AES_KEY3 Register */
+    __IO uint32_t aes_key4;             /**< <tt>\b 0x10:</tt> AES_KEY_REVB AES_KEY4 Register */
+    __IO uint32_t aes_key5;             /**< <tt>\b 0x14:</tt> AES_KEY_REVB AES_KEY5 Register */
+    __IO uint32_t aes_key6;             /**< <tt>\b 0x18:</tt> AES_KEY_REVB AES_KEY6 Register */
+    __IO uint32_t aes_key7;             /**< <tt>\b 0x1C:</tt> AES_KEY_REVB AES_KEY7 Register */
+} mxc_aes_key_revb_regs_t;
+
+/* Register offsets for module AES_KEY_REVB */
+/**
+ * @ingroup    aes_key_revb_registers
+ * @defgroup   AES_KEY_REVB_Register_Offsets Register Offsets
+ * @brief      AES_KEY_REVB Peripheral Register Offsets from the AES_KEY_REVB Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_AES_KEY_REVB_AES_KEY0        ((uint32_t)0x00000000UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_AES_KEY_REVB_AES_KEY1        ((uint32_t)0x00000004UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_AES_KEY_REVB_AES_KEY2        ((uint32_t)0x00000008UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_AES_KEY_REVB_AES_KEY3        ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_AES_KEY_REVB_AES_KEY4        ((uint32_t)0x00000010UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_AES_KEY_REVB_AES_KEY5        ((uint32_t)0x00000014UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_AES_KEY_REVB_AES_KEY6        ((uint32_t)0x00000018UL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_AES_KEY_REVB_AES_KEY7        ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY_REVB Base Address: <tt> 0x001C</tt> */ 
+/**@} end of group aes_key_revb_registers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AES_KEY_REVB_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_me15.c

@@ -0,0 +1,305 @@
+/**
+ * @file
+ * @brief   Trust Protection Unit driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "aes_revb.h"
+#include "trng.h"
+#include "flc.h"
+#include "string.h"
+
+#define KEY_ADDR 0x10802008
+#define FMV_ADDR 0x10802000
+static const uint32_t fmv[2] = {0x2B86D479, 0x2B86D479};
+
+static void reverse_key(const void* key, uint8_t* keyr, int len)
+{
+    int i;
+    uint8_t tmp;
+    uint8_t* k = (uint8_t*)key;
+    for(i = 0; i < len; i++)
+    {
+        tmp = k[i];
+        k[i] = keyr[len - i - 1];
+        keyr[len - i - 1] = tmp;
+    }
+}
+
+/* ************************************************************************* */
+/* Global Control/Configuration functions                                    */
+/* ************************************************************************* */
+
+int MXC_AES_Init(void)
+{
+    MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_AES);
+    MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG);
+    
+    MXC_AES->ctrl = 0x00;
+    // Start with a randomly generated key.
+    MXC_AES_GenerateKey();
+
+    MXC_AES_RevB_Init((mxc_aes_revb_regs_t*) MXC_AES);
+    
+    return E_NO_ERROR;
+}
+
+void MXC_AES_EnableInt (uint32_t interrupt)
+{
+    MXC_AES_RevB_EnableInt((mxc_aes_revb_regs_t*) MXC_AES, interrupt);
+}
+
+void MXC_AES_DisableInt (uint32_t interrupt)
+{
+    MXC_AES_RevB_DisableInt((mxc_aes_revb_regs_t*) MXC_AES, interrupt);
+}
+
+int MXC_AES_IsBusy(void)
+{
+    return MXC_AES_RevB_IsBusy((mxc_aes_revb_regs_t*) MXC_AES);
+}
+
+int MXC_AES_Shutdown (void)
+{
+    int error = MXC_AES_RevB_Shutdown ((mxc_aes_revb_regs_t*) MXC_AES);
+    
+    MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_AES);
+    
+    return error;
+}
+
+void MXC_AES_DMACallback(int ch, int error)
+{
+    MXC_AES_RevB_DMACallback(ch, error);
+}
+
+void MXC_AES_GenerateKey(void)
+{
+    // Generating a random key is part of the TRNG block
+    MXC_TRNG_GenerateKey();
+}
+
+void MXC_AES_SetKeySize(mxc_aes_keys_t key)
+{
+    MXC_AES_RevB_SetKeySize((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_keys_t) key);
+}
+
+mxc_aes_keys_t MXC_AES_GetKeySize(void)
+{
+    return MXC_AES_RevB_GetKeySize((mxc_aes_revb_regs_t*) MXC_AES);
+}
+
+void MXC_AES_FlushInputFIFO(void)
+{
+    MXC_AES_RevB_FlushInputFIFO((mxc_aes_revb_regs_t*) MXC_AES);
+}
+
+void MXC_AES_FlushOutputFIFO(void)
+{
+    MXC_AES_RevB_FlushOutputFIFO((mxc_aes_revb_regs_t*) MXC_AES);
+}
+
+void MXC_AES_Start(void)
+{
+    MXC_AES_RevB_Start((mxc_aes_revb_regs_t*) MXC_AES);
+}
+
+uint32_t MXC_AES_GetFlags(void)
+{
+    return MXC_AES_RevB_GetFlags((mxc_aes_revb_regs_t*) MXC_AES);
+}
+
+void MXC_AES_ClearFlags(uint32_t flags)
+{
+    MXC_AES_RevB_ClearFlags((mxc_aes_revb_regs_t*) MXC_AES, flags);
+}
+
+int MXC_AES_Generic(mxc_aes_req_t* req)
+{
+    return MXC_AES_RevB_Generic((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req);
+}
+
+int MXC_AES_Encrypt(mxc_aes_req_t* req)
+{
+    return MXC_AES_RevB_Encrypt((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req);
+}
+
+int MXC_AES_Decrypt(mxc_aes_req_t* req)
+{
+    return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req);
+}
+
+int MXC_AES_TXDMAConfig(void* src_addr, int len)
+{
+    return MXC_AES_RevB_TXDMAConfig(src_addr, len);
+}
+
+int MXC_AES_RXDMAConfig(void* dest_addr, int len)
+{
+    return MXC_AES_RevB_RXDMAConfig(dest_addr, len);
+}
+
+int MXC_AES_GenericAsync(mxc_aes_req_t* req, uint8_t enc)
+{
+    return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req, enc);
+}
+
+int MXC_AES_EncryptAsync(mxc_aes_req_t* req)
+{
+    return MXC_AES_RevB_EncryptAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req);
+}
+
+int MXC_AES_DecryptAsync(mxc_aes_req_t* req)
+{
+    return MXC_AES_RevB_DecryptAsync((mxc_aes_revb_regs_t*) MXC_AES, (mxc_aes_revb_req_t*) req);
+}
+
+void MXC_AES_SetExtKey(const void* key, mxc_aes_keys_t len)
+{
+    MXC_AES_RevB_SetExtKey((mxc_aes_key_revb_regs_t*) MXC_AESKEY, key, len);
+}
+
+int MXC_AES_SetPORKey(const void* key, mxc_aes_keys_t len)
+{
+    int err = E_BAD_PARAM;
+    uint8_t keyr[32];
+
+    // Make the key location readable/writable
+    MXC_FLC_UnlockInfoBlock(KEY_ADDR);
+
+    // Write the key
+    switch(len)
+    {
+        case MXC_AES_128BITS:   
+            reverse_key(key, keyr, 16);
+            err = MXC_FLC_Write(KEY_ADDR, 16, (uint32_t*)keyr);
+            break;
+        case MXC_AES_192BITS:   
+            reverse_key(key, keyr, 24);
+            err = MXC_FLC_Write(KEY_ADDR, 24, (uint32_t*)keyr);
+            break;
+        case MXC_AES_256BITS:   
+            reverse_key(key, keyr, 32);
+            err = MXC_FLC_Write(KEY_ADDR, 32, (uint32_t*)keyr);
+            break;
+    }
+    
+    if(err == E_NO_ERROR) {
+        // Write the magic value to activate the key
+        err = MXC_FLC_Write(FMV_ADDR, sizeof(fmv), (uint32_t *)fmv);
+
+        // Lock the key region from reads/writes
+        MXC_FLC_LockInfoBlock(KEY_ADDR);
+        return err;
+    }
+
+    // Lock the key region from reads/writes
+    MXC_FLC_LockInfoBlock(KEY_ADDR);
+    return err;
+}
+
+int MXC_AES_ClearPORKey()
+{
+    int err;
+
+    // The first 40 bytes of the page contain the FMV and AES key, no
+    //  need to save those.
+    uint8_t page[MXC_FLASH_PAGE_SIZE - 40];
+
+    // Make the key location readable/writable
+    MXC_FLC_UnlockInfoBlock(FMV_ADDR);
+
+    // Copy the current memory contents
+    memcpy(page, (uint8_t*)FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40);
+    
+    err = MXC_FLC_PageErase(FMV_ADDR);
+    if(err != E_NO_ERROR) {
+        // Couldn't erase the memory.  Abort.
+        // Lock the key region from reads/writes
+        MXC_FLC_LockInfoBlock(FMV_ADDR);
+        return err;
+    }
+
+    // Write the old contents (minus the fmv and key) back to the part
+    err = MXC_FLC_Write(FMV_ADDR + 40, MXC_FLASH_PAGE_SIZE - 40, (uint32_t*)page);
+
+    // Lock the key region from reads/writes
+    MXC_FLC_LockInfoBlock(FMV_ADDR);
+
+    return err;
+}
+
+void MXC_AES_CopyPORKeyToKeyRegisters(mxc_aes_keys_t len)
+{
+    // Make the key location readable/writable
+    MXC_FLC_UnlockInfoBlock(KEY_ADDR);
+
+    // Copy the values to the key register
+    switch(len)
+    {
+        case MXC_AES_128BITS:   
+            memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 16);
+            break;
+        case MXC_AES_192BITS:   
+            memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 24);
+            break;
+        case MXC_AES_256BITS:   
+            memcpy(MXC_AESKEY, (uint8_t*)KEY_ADDR, 32);
+            break;
+    }
+
+    // Lock the key region from reads/writes
+    MXC_FLC_LockInfoBlock(KEY_ADDR);
+}
+
+int MXC_AES_HasPORKey()
+{
+    int res;
+    
+    // Make the key location readable/writable
+    MXC_FLC_UnlockInfoBlock(FMV_ADDR);
+    
+    // Look for the magic value.
+    res = memcmp((uint8_t*)FMV_ADDR, (uint8_t*)fmv, 8);
+
+    // Lock the key region from reads/writes
+    MXC_FLC_LockInfoBlock(FMV_ADDR);
+
+    return !res;
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.c

@@ -0,0 +1,436 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+#ifdef __CC_ARM  // Keil 
+ #pragma diag_suppress 188  // enumerated type mixed with another type
+#endif
+
+#include <stdlib.h>
+#include <string.h>
+#include "mxc_sys.h"
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+
+#include "dma.h"
+#include "aes_regs.h"
+#include "aes_key_regs.h"
+#include "aes_revb.h"
+#include "trng_revb.h"
+
+/* **** Variable Declaration **** */
+typedef struct {
+    uint8_t enc;
+    uint8_t channelRX;
+    uint8_t channelTX;
+    uint32_t remain;    
+    uint32_t* inputText;
+    uint32_t* outputText;
+} mxc_aes_revb_dma_req_t;
+
+static mxc_aes_revb_dma_req_t dma_state;
+
+#define SWAP_BYTES(x) ((((x) >> 24) & 0x000000FF) | (((x) >>  8) & 0x0000FF00) | (((x) <<  8) & 0x00FF0000) | (((x) << 24) & 0xFF000000))
+
+static void memcpy32r(uint32_t * dst, const uint32_t * src, unsigned int len)
+{
+  uint32_t * dstr = dst + (len/4) - 1;
+  while (len) {
+    *dstr = SWAP_BYTES(*src);
+    dstr--;
+    src++;
+    len -= 4;
+  }
+}
+
+int MXC_AES_RevB_Init(mxc_aes_revb_regs_t* aes)
+{
+  aes->ctrl = 0x00;
+
+  while (MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR);
+
+  aes->ctrl |= MXC_F_AES_REVB_CTRL_EN;
+
+  return E_NO_ERROR;
+}
+
+int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes)
+{
+    MXC_AES_RevB_FlushInputFIFO(aes);
+	MXC_AES_RevB_FlushOutputFIFO(aes);
+
+    while(MXC_AES_RevB_IsBusy(aes) != E_NO_ERROR) ;
+    
+    aes->ctrl = 0x00;
+
+  return E_NO_ERROR;
+}
+
+int MXC_AES_RevB_IsBusy (mxc_aes_revb_regs_t* aes)
+{
+    if(aes->status & MXC_F_AES_REVB_STATUS_BUSY)
+    {
+        return E_BUSY;
+    }
+
+  return E_NO_ERROR;
+}
+
+void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t* aes, mxc_aes_revb_keys_t key)
+{
+    while(MXC_AES_IsBusy() != E_NO_ERROR);
+    aes->ctrl |= key;
+}
+
+mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t* aes)
+{
+    return (aes->ctrl & MXC_F_AES_REVB_CTRL_KEY_SIZE);
+}
+
+void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t* aes)
+{
+    while(MXC_AES_IsBusy() != E_NO_ERROR);
+    aes->ctrl |= MXC_F_AES_REVB_CTRL_INPUT_FLUSH;
+}
+
+void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t* aes)
+{
+    while(MXC_AES_IsBusy() != E_NO_ERROR);
+    aes->ctrl |= MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH;
+}
+
+void MXC_AES_RevB_Start(mxc_aes_revb_regs_t* aes)
+{
+    while(MXC_AES_IsBusy() != E_NO_ERROR);  
+    aes->ctrl |= MXC_F_AES_REVB_CTRL_START;  
+}
+
+void MXC_AES_RevB_EnableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt)
+{
+    aes->inten |= (interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \
+                        MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV));
+}
+
+void MXC_AES_RevB_DisableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt)
+{
+    aes->inten &= ~(interrupt & (MXC_F_AES_REVB_INTEN_DONE | MXC_F_AES_REVB_INTEN_KEY_CHANGE | \
+                        MXC_F_AES_REVB_INTEN_KEY_ZERO | MXC_F_AES_REVB_INTEN_OV));
+}
+
+uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t* aes)
+{
+    return aes->intfl;
+}
+
+void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t* aes, uint32_t flags)
+{
+    aes->intfl = (flags & (MXC_F_AES_REVB_INTFL_DONE | MXC_F_AES_REVB_INTFL_KEY_CHANGE | \
+                        MXC_F_AES_REVB_INTFL_KEY_ZERO | MXC_F_AES_REVB_INTFL_OV));
+}
+
+int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
+{
+    int i;
+    int remain;
+
+    if(req == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->inputData == NULL || req->resultData == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->length == 0) {
+        return E_BAD_PARAM;
+    }
+
+    remain = req->length;
+    
+    MXC_AES_RevB_FlushInputFIFO(aes);
+	MXC_AES_RevB_FlushOutputFIFO(aes);
+
+    MXC_AES_RevB_SetKeySize(aes, req->keySize);
+
+    while(MXC_AES_IsBusy() != E_NO_ERROR);
+    
+    MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
+
+    while(remain/4)
+    {
+        for(i = 0; i < 4; i++) {
+            aes->fifo = SWAP_BYTES(req->inputData[3-i]);
+        }
+        req->inputData += 4;
+
+        while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE));
+        aes->intfl |= MXC_F_AES_REVB_INTFL_DONE;
+
+        for(i = 0; i < 4; i++) {
+            uint32_t tmp = aes->fifo;
+            req->resultData[3-i] = SWAP_BYTES(tmp);
+        }        
+        req->resultData += 4;
+
+        remain -= 4;
+    }
+
+    if(remain%4)
+    {
+        for(i = 0; i < remain; i++) {
+            aes->fifo = SWAP_BYTES(req->inputData[remain-1-i]);
+        }
+        req->inputData += remain;
+
+        // Pad last block with 0's
+        for(i = remain; i < 4; i++) {
+            aes->fifo = 0;
+        }
+
+        while(!(aes->intfl & MXC_F_AES_REVB_INTFL_DONE));
+        aes->intfl |= MXC_F_AES_REVB_INTFL_DONE;
+
+        for(i = 0; i < 4; i++) {
+            uint32_t tmp = aes->fifo;
+            req->resultData[3-i] = SWAP_BYTES(tmp);
+        }        
+        req->resultData += 4;
+    }
+    return E_NO_ERROR;
+}
+
+int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
+{
+    return MXC_AES_RevB_Generic(aes, req);
+}
+
+int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
+{
+    return MXC_AES_RevB_Generic(aes, req);
+}
+
+int MXC_AES_RevB_TXDMAConfig(void* src_addr, int len)
+{
+    uint8_t channel;
+    mxc_dma_config_t config;
+    mxc_dma_srcdst_t srcdst;
+
+    if (src_addr == NULL) {
+      return E_NULL_PTR;
+    }
+
+    if (len == 0) {
+      return E_BAD_PARAM;
+    }
+
+    MXC_DMA_Init();
+
+    channel = MXC_DMA_AcquireChannel();
+    dma_state.channelTX = channel;
+
+    config.reqsel = MXC_DMA_REQUEST_AESTX;
+    
+    config.ch = channel;
+    
+    config.srcwd = MXC_DMA_WIDTH_WORD;
+    config.dstwd = MXC_DMA_WIDTH_WORD;
+    
+    config.srcinc_en = 1;
+    config.dstinc_en = 0;
+    
+    srcdst.ch = channel;
+    srcdst.source = src_addr;
+    
+    if(dma_state.enc == 1) {
+        srcdst.len = 4;
+    }
+    else if(len > 4) {
+        srcdst.len = 4;
+    }
+    else{
+        srcdst.len = len;
+    }
+
+    MXC_DMA_ConfigChannel (config, srcdst);
+    MXC_DMA_SetCallback (channel, MXC_AES_RevB_DMACallback);
+    
+    MXC_DMA_EnableInt (channel);
+    MXC_DMA_Start (channel);
+    //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;
+    MXC_DMA_SetChannelInterruptEn(channel, 0, 1);
+
+    return E_NO_ERROR;
+}
+
+int MXC_AES_RevB_RXDMAConfig(void* dest_addr, int len)
+{
+    if (dest_addr == NULL) {
+      return E_NULL_PTR;
+    }
+
+    if (len == 0) {
+      return E_BAD_PARAM;
+    }
+
+    uint8_t channel;
+    mxc_dma_config_t config;
+    mxc_dma_srcdst_t srcdst;
+
+    MXC_DMA_Init();
+
+    channel = MXC_DMA_AcquireChannel();
+    dma_state.channelRX = channel;
+
+    config.reqsel = MXC_DMA_REQUEST_AESRX;
+    
+    config.ch = channel;
+    
+    config.srcwd = MXC_DMA_WIDTH_WORD;
+    config.dstwd = MXC_DMA_WIDTH_WORD;
+    
+    config.srcinc_en = 0;
+    config.dstinc_en = 1;
+    
+    srcdst.ch = channel;
+    srcdst.dest = dest_addr;
+
+    if(dma_state.enc == 0) {
+        srcdst.len = 4;
+    }
+    else if(len > 4) {
+        srcdst.len = 4;
+    }
+    else{
+        srcdst.len = len;
+    }
+    
+    MXC_DMA_ConfigChannel (config, srcdst);
+    MXC_DMA_SetCallback (channel, MXC_AES_RevB_DMACallback);
+    
+    MXC_DMA_EnableInt (channel);
+    MXC_DMA_Start (channel);
+    //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;
+    MXC_DMA_SetChannelInterruptEn(channel, 0, 1);
+
+    return E_NO_ERROR;
+}
+
+int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req, uint8_t enc)
+{
+    if(req == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->inputData == NULL || req->resultData == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->length == 0) {
+        return E_BAD_PARAM;
+    }
+
+    MXC_AES_RevB_FlushInputFIFO(aes);
+	  MXC_AES_RevB_FlushOutputFIFO(aes);
+
+    MXC_AES_RevB_SetKeySize(aes, req->keySize);
+
+    MXC_AES_IsBusy();
+    MXC_SETFIELD (aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, req->encryption << MXC_F_AES_REVB_CTRL_TYPE_POS);
+
+    dma_state.enc = enc;
+    dma_state.remain = req->length;
+    dma_state.inputText = req->inputData;
+    dma_state.outputText = req->resultData;
+
+    aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN;              //Enable AES DMA    
+    aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN;              //Enable AES DMA    
+
+    if(MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) {
+        return E_BAD_PARAM;
+    }
+
+    return E_NO_ERROR;
+}
+ 
+int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
+{
+    return MXC_AES_RevB_GenericAsync(aes, req, 0);
+}
+
+int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req)
+{
+    return MXC_AES_RevB_GenericAsync(aes, req, 1);
+}
+
+void MXC_AES_RevB_DMACallback(int ch, int error)
+{
+    if(error != E_NO_ERROR) {
+
+    } 
+    else {
+      if (dma_state.channelTX == ch) {
+        MXC_DMA_ReleaseChannel(dma_state.channelTX);
+        if (dma_state.remain < 4) {
+          MXC_AES_Start();
+        }
+        MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain);
+        } 
+      else if (dma_state.channelRX == ch) {
+        if (dma_state.remain > 4) {
+          dma_state.remain -= 4;
+        } else if (dma_state.remain > 0) {
+          dma_state.remain = 0;
+        }
+        MXC_DMA_ReleaseChannel(dma_state.channelRX);
+        if (dma_state.remain > 0) {
+          MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain);
+        }
+      }
+    }
+}
+
+void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len)
+{
+  int numBytes;
+
+  if(len == MXC_AES_128BITS) {
+    numBytes = 16;
+  } else if (len == MXC_AES_192BITS) {
+    numBytes = 24;
+  } else {
+    numBytes = 32;
+  }
+
+  /* TODO: Figure out if this is the correct byte ordering */
+  memcpy32r((void*)&(aeskey->aes_key0), key, numBytes);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb.h

@@ -0,0 +1,96 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include <stdint.h>
+#include "mxc_aes.h"
+#include "aes_revb_regs.h"
+#include "aes_key_revb_regs.h"
+#include "trng_revb_regs.h"
+
+/**
+  * @brief  Enumeration type to select AES key
+  *
+  */
+typedef enum {
+    MXC_AES_REVB_128BITS    = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES128,    ///< Select AES-128 bit key
+    MXC_AES_REVB_192BITS    = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES192,    ///< Select AES-192 bit key
+    MXC_AES_REVB_256BITS    = MXC_S_AES_REVB_CTRL_KEY_SIZE_AES256,    ///< Select AES-256 bit key
+} mxc_aes_revb_keys_t;
+
+/**
+  * @brief  Enumeration type to select AES key source and encryption type
+  *
+  */
+typedef enum {
+    MXC_AES_REVB_ENCRYPT_EXT_KEY  = 0,   ///< Encryption using External key
+    MXC_AES_REVB_DECRYPT_EXT_KEY  = 1,   ///< Encryption using internal key
+    MXC_AES_REVB_DECRYPT_INT_KEY  = 2    ///< Decryption using internal key
+} mxc_aes_revb_enc_type_t;
+
+/**
+  * @brief  Structure used to set up AES request
+  *
+  */
+typedef struct _mxc_aes_revb_cipher_req_t {
+    uint32_t length;                ///< Length of the data
+    uint32_t *inputData;            ///< Pointer to input data
+    uint32_t *resultData;           ///< Pointer to encrypted data
+    mxc_aes_revb_keys_t keySize;         ///< Size of AES key
+    mxc_aes_revb_enc_type_t encryption;  ///< Encrytion type or \ref mxc_aes_enc_type_t
+    mxc_aes_complete_t callback;    ///< Callback function
+} mxc_aes_revb_req_t;
+
+
+int MXC_AES_RevB_Init (mxc_aes_revb_regs_t* aes);
+void MXC_AES_RevB_EnableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt);
+void MXC_AES_RevB_DisableInt (mxc_aes_revb_regs_t* aes, uint32_t interrupt);
+int MXC_AES_RevB_IsBusy (mxc_aes_revb_regs_t* aes);
+int MXC_AES_RevB_Shutdown (mxc_aes_revb_regs_t* aes);
+void MXC_AES_RevB_GenerateKey(mxc_trng_revb_regs_t* trng);
+void MXC_AES_RevB_SetKeySize(mxc_aes_revb_regs_t* aes, mxc_aes_revb_keys_t key);
+mxc_aes_keys_t MXC_AES_RevB_GetKeySize(mxc_aes_revb_regs_t* aes);
+void MXC_AES_RevB_FlushInputFIFO(mxc_aes_revb_regs_t* aes);
+void MXC_AES_RevB_FlushOutputFIFO(mxc_aes_revb_regs_t* aes);
+void MXC_AES_RevB_Start(mxc_aes_revb_regs_t* aes);
+uint32_t MXC_AES_RevB_GetFlags(mxc_aes_revb_regs_t* aes);
+void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t* aes, uint32_t flags);
+int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req);
+int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req);
+int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req);
+int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len);
+int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len);
+int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req, uint8_t enc);
+int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req);
+int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t* aes, mxc_aes_revb_req_t* req);
+void MXC_AES_RevB_DMACallback (int ch, int error);
+void MXC_AES_RevB_SetExtKey(mxc_aes_key_revb_regs_t* aeskey, const void* key, mxc_aes_keys_t len);

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/AES/aes_revb_regs.h

@@ -0,0 +1,226 @@
+/**
+ * @file    aes_revb_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _AES_REVB_REGS_H_
+#define _AES_REVB_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     aes_revb
+ * @defgroup    aes_revb_registers AES_REVB_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the AES_REVB Peripheral Module.
+ * @details AES Keys.
+ */
+
+/**
+ * @ingroup aes_revb_registers
+ * Structure type to access the AES_REVB Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x0000:</tt> AES_REVB CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x0004:</tt> AES_REVB STATUS Register */
+    __IO uint32_t intfl;                /**< <tt>\b 0x0008:</tt> AES_REVB INTFL Register */
+    __IO uint32_t inten;                /**< <tt>\b 0x000C:</tt> AES_REVB INTEN Register */
+    __IO uint32_t fifo;                 /**< <tt>\b 0x0010:</tt> AES_REVB FIFO Register */
+} mxc_aes_revb_regs_t;
+
+/* Register offsets for module AES_REVB */
+/**
+ * @ingroup    aes_revb_registers
+ * @defgroup   AES_REVB_Register_Offsets Register Offsets
+ * @brief      AES_REVB Peripheral Register Offsets from the AES_REVB Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_AES_REVB_CTRL                ((uint32_t)0x00000000UL) /**< Offset from AES_REVB Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_AES_REVB_STATUS              ((uint32_t)0x00000004UL) /**< Offset from AES_REVB Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_AES_REVB_INTFL               ((uint32_t)0x00000008UL) /**< Offset from AES_REVB Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_AES_REVB_INTEN               ((uint32_t)0x0000000CUL) /**< Offset from AES_REVB Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_AES_REVB_FIFO                ((uint32_t)0x00000010UL) /**< Offset from AES_REVB Base Address: <tt> 0x0010</tt> */ 
+/**@} end of group aes_revb_registers */
+
+/**
+ * @ingroup  aes_revb_registers
+ * @defgroup AES_REVB_CTRL AES_REVB_CTRL
+ * @brief    AES Control Register
+ * @{
+ */
+ #define MXC_F_AES_REVB_CTRL_EN_POS                     0 /**< CTRL_EN Position */
+ #define MXC_F_AES_REVB_CTRL_EN                         ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_AES_REVB_CTRL_DMA_RX_EN_POS              1 /**< CTRL_DMA_RX_EN Position */
+ #define MXC_F_AES_REVB_CTRL_DMA_RX_EN                  ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */
+
+ #define MXC_F_AES_REVB_CTRL_DMA_TX_EN_POS              2 /**< CTRL_DMA_TX_EN Position */
+ #define MXC_F_AES_REVB_CTRL_DMA_TX_EN                  ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */
+
+ #define MXC_F_AES_REVB_CTRL_START_POS                  3 /**< CTRL_START Position */
+ #define MXC_F_AES_REVB_CTRL_START                      ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_START_POS)) /**< CTRL_START Mask */
+
+ #define MXC_F_AES_REVB_CTRL_INPUT_FLUSH_POS            4 /**< CTRL_INPUT_FLUSH Position */
+ #define MXC_F_AES_REVB_CTRL_INPUT_FLUSH                ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */
+
+ #define MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH_POS           5 /**< CTRL_OUTPUT_FLUSH Position */
+ #define MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH               ((uint32_t)(0x1UL << MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */
+
+ #define MXC_F_AES_REVB_CTRL_KEY_SIZE_POS               6 /**< CTRL_KEY_SIZE Position */
+ #define MXC_F_AES_REVB_CTRL_KEY_SIZE                   ((uint32_t)(0x3UL << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */
+ #define MXC_V_AES_REVB_CTRL_KEY_SIZE_AES128            ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */
+ #define MXC_S_AES_REVB_CTRL_KEY_SIZE_AES128            (MXC_V_AES_REVB_CTRL_KEY_SIZE_AES128 << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */
+ #define MXC_V_AES_REVB_CTRL_KEY_SIZE_AES192            ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */
+ #define MXC_S_AES_REVB_CTRL_KEY_SIZE_AES192            (MXC_V_AES_REVB_CTRL_KEY_SIZE_AES192 << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */
+ #define MXC_V_AES_REVB_CTRL_KEY_SIZE_AES256            ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */
+ #define MXC_S_AES_REVB_CTRL_KEY_SIZE_AES256            (MXC_V_AES_REVB_CTRL_KEY_SIZE_AES256 << MXC_F_AES_REVB_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */
+
+ #define MXC_F_AES_REVB_CTRL_TYPE_POS                   8 /**< CTRL_TYPE Position */
+ #define MXC_F_AES_REVB_CTRL_TYPE                       ((uint32_t)(0x3UL << MXC_F_AES_REVB_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */
+
+/**@} end of group AES_REVB_CTRL_Register */
+
+/**
+ * @ingroup  aes_revb_registers
+ * @defgroup AES_REVB_STATUS AES_REVB_STATUS
+ * @brief    AES Status Register
+ * @{
+ */
+ #define MXC_F_AES_REVB_STATUS_BUSY_POS                 0 /**< STATUS_BUSY Position */
+ #define MXC_F_AES_REVB_STATUS_BUSY                     ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
+
+ #define MXC_F_AES_REVB_STATUS_INPUT_EM_POS             1 /**< STATUS_INPUT_EM Position */
+ #define MXC_F_AES_REVB_STATUS_INPUT_EM                 ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */
+
+ #define MXC_F_AES_REVB_STATUS_INPUT_FULL_POS           2 /**< STATUS_INPUT_FULL Position */
+ #define MXC_F_AES_REVB_STATUS_INPUT_FULL               ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */
+
+ #define MXC_F_AES_REVB_STATUS_OUTPUT_EM_POS            3 /**< STATUS_OUTPUT_EM Position */
+ #define MXC_F_AES_REVB_STATUS_OUTPUT_EM                ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */
+
+ #define MXC_F_AES_REVB_STATUS_OUTPUT_FULL_POS          4 /**< STATUS_OUTPUT_FULL Position */
+ #define MXC_F_AES_REVB_STATUS_OUTPUT_FULL              ((uint32_t)(0x1UL << MXC_F_AES_REVB_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */
+
+/**@} end of group AES_REVB_STATUS_Register */
+
+/**
+ * @ingroup  aes_revb_registers
+ * @defgroup AES_REVB_INTFL AES_REVB_INTFL
+ * @brief    AES Interrupt Flag Register
+ * @{
+ */
+ #define MXC_F_AES_REVB_INTFL_DONE_POS                  0 /**< INTFL_DONE Position */
+ #define MXC_F_AES_REVB_INTFL_DONE                      ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_DONE_POS)) /**< INTFL_DONE Mask */
+
+ #define MXC_F_AES_REVB_INTFL_KEY_CHANGE_POS            1 /**< INTFL_KEY_CHANGE Position */
+ #define MXC_F_AES_REVB_INTFL_KEY_CHANGE                ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */
+
+ #define MXC_F_AES_REVB_INTFL_KEY_ZERO_POS              2 /**< INTFL_KEY_ZERO Position */
+ #define MXC_F_AES_REVB_INTFL_KEY_ZERO                  ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */
+
+ #define MXC_F_AES_REVB_INTFL_OV_POS                    3 /**< INTFL_OV Position */
+ #define MXC_F_AES_REVB_INTFL_OV                        ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTFL_OV_POS)) /**< INTFL_OV Mask */
+
+/**@} end of group AES_REVB_INTFL_Register */
+
+/**
+ * @ingroup  aes_revb_registers
+ * @defgroup AES_REVB_INTEN AES_REVB_INTEN
+ * @brief    AES Interrupt Enable Register
+ * @{
+ */
+ #define MXC_F_AES_REVB_INTEN_DONE_POS                  0 /**< INTEN_DONE Position */
+ #define MXC_F_AES_REVB_INTEN_DONE                      ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_DONE_POS)) /**< INTEN_DONE Mask */
+
+ #define MXC_F_AES_REVB_INTEN_KEY_CHANGE_POS            1 /**< INTEN_KEY_CHANGE Position */
+ #define MXC_F_AES_REVB_INTEN_KEY_CHANGE                ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */
+
+ #define MXC_F_AES_REVB_INTEN_KEY_ZERO_POS              2 /**< INTEN_KEY_ZERO Position */
+ #define MXC_F_AES_REVB_INTEN_KEY_ZERO                  ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */
+
+ #define MXC_F_AES_REVB_INTEN_OV_POS                    3 /**< INTEN_OV Position */
+ #define MXC_F_AES_REVB_INTEN_OV                        ((uint32_t)(0x1UL << MXC_F_AES_REVB_INTEN_OV_POS)) /**< INTEN_OV Mask */
+
+/**@} end of group AES_REVB_INTEN_Register */
+
+/**
+ * @ingroup  aes_revb_registers
+ * @defgroup AES_REVB_FIFO AES_REVB_FIFO
+ * @brief    AES Data Register
+ * @{
+ */
+ #define MXC_F_AES_REVB_FIFO_DATA_POS                   0 /**< FIFO_DATA Position */
+ #define MXC_F_AES_REVB_FIFO_DATA                       ((uint32_t)(0x1UL << MXC_F_AES_REVB_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+
+/**@} end of group AES_REVB_FIFO_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AES_REVB_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_me15.c

@@ -0,0 +1,113 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+
+#include "crc.h"
+#include "crc_reva.h"
+
+
+/* ************************************************************************* */
+/* Global Control/Configuration functions                                    */
+/* ************************************************************************* */
+
+int MXC_CRC_Init(void)
+{
+    MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC);
+
+    MXC_CRC_RevA_Init((mxc_crc_reva_regs_t*) MXC_CRC);
+
+    return E_NO_ERROR;
+}
+
+int MXC_CRC_Shutdown(void)
+{
+    int error = MXC_CRC_RevA_Shutdown((mxc_crc_reva_regs_t*) MXC_CRC);
+    
+    MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_CRC);
+    
+    return error;
+}
+
+void MXC_CRC_Handler (int ch, int error)
+{
+    MXC_CRC_RevA_Handler(ch, error);
+}
+
+void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder)
+{
+    MXC_CRC_RevA_SetDirection((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder);
+}
+
+mxc_crc_bitorder_t MXC_CRC_GetDirection(void)
+{
+    return MXC_CRC_RevA_GetDirection((mxc_crc_reva_regs_t*) MXC_CRC);
+}
+
+void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder)
+{
+    MXC_CRC_RevA_SwapDataIn((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder);
+}
+
+void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder)
+{
+    MXC_CRC_RevA_SwapDataOut((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_bitorder_t) bitOrder);
+}
+
+void MXC_CRC_SetPoly(uint32_t poly)
+{
+    MXC_CRC_RevA_SetPoly((mxc_crc_reva_regs_t*) MXC_CRC, poly);
+}
+
+uint32_t MXC_CRC_GetPoly(void)
+{
+    return MXC_CRC_RevA_GetPoly((mxc_crc_reva_regs_t*) MXC_CRC);
+}
+
+uint32_t MXC_CRC_GetResult(void)
+{
+    return MXC_CRC_RevA_GetResult((mxc_crc_reva_regs_t*) MXC_CRC);
+}
+
+int MXC_CRC_Compute(mxc_crc_req_t* req)
+{
+    return MXC_CRC_RevA_Compute((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_req_t*) req);
+}
+
+int MXC_CRC_ComputeAsync(mxc_crc_req_t* req)
+{
+    return MXC_CRC_RevA_ComputeAsync((mxc_crc_reva_regs_t*) MXC_CRC, (mxc_crc_reva_req_t*) req);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.c

@@ -0,0 +1,209 @@
+/* ****************************************************************************
+ * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+ 
+#ifdef __CC_ARM
+#pragma diag_suppress 188
+#endif
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "mxc_sys.h"
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+
+#include "dma.h"
+#include "crc_regs.h"
+#include "crc_reva.h"
+
+
+/***** Global Variables *****/
+static mxc_crc_reva_req_t *CRCreq;
+
+/* ************************************************************************* */
+/* Global Control/Configuration functions                                    */
+/* ************************************************************************* */
+
+int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t* crc)
+{
+    crc->ctrl = 0x00;
+    crc->val  = 0xFFFFFFFF;
+    return E_NO_ERROR;
+}
+
+int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t* crc)
+{
+    crc->ctrl &= ~MXC_F_CRC_REVA_CTRL_EN;
+    return E_NO_ERROR;
+}
+
+int MXC_CRC_RevA_Handler(int ch, int error)
+{
+    if(error == E_NO_ERROR) {
+        CRCreq->resultCRC = MXC_CRC_GetResult();
+    }
+    return error;
+}
+
+/* ************************************************************************* */
+/* Cyclic Redundancy Check(CRC) functions                                   */
+/* ************************************************************************* */
+
+/*******************************/
+/* Low Level Functions         */
+/*******************************/
+
+void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder)
+{
+    MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_MSB, bitOrder << MXC_F_CRC_REVA_CTRL_MSB_POS);
+}
+
+mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t* crc)
+{
+    return !!(crc->ctrl & MXC_F_CRC_REVA_CTRL_MSB);
+}
+
+void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder)
+{
+    MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS);    
+}
+
+void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder)
+{
+    MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT, bitOrder << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS);
+}
+
+void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t* crc, uint32_t poly)
+{
+    crc->poly = poly;
+}
+
+uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t* crc)
+{
+    return crc->poly;
+}
+
+uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t* crc)
+{
+    return crc->val;
+}
+
+/*******************************/
+/* High Level Functions        */
+/*******************************/
+
+int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req)
+{
+    int i = 0;
+    volatile int length;
+
+    if(req == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->dataBuffer == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->dataLen == 0) {
+        return E_INVALID;
+    }
+
+    crc->ctrl |= MXC_F_CRC_REVA_CTRL_EN;
+
+    length = req->dataLen;
+    
+    while(length--)
+    {
+        crc->datain32 = req->dataBuffer[i++];
+        while(crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY);
+    }
+    
+    // Store the crc value
+    req->resultCRC = MXC_CRC_GetResult();
+    
+    return E_NO_ERROR;
+}
+
+int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req)
+{
+    uint8_t channel;
+    mxc_dma_config_t config;
+    mxc_dma_srcdst_t srcdst;
+
+    if(req == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->dataBuffer == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(req->dataLen == 0) {
+        return E_INVALID;
+    }
+    
+    CRCreq = req;
+    
+    MXC_DMA_Init();
+    
+    channel = MXC_DMA_AcquireChannel();
+    
+    config.reqsel = MXC_DMA_REQUEST_CRCTX;
+    
+    config.ch = channel;
+    
+    config.srcwd = MXC_DMA_WIDTH_BYTE;
+    config.dstwd = MXC_DMA_WIDTH_BYTE;
+    
+    config.srcinc_en = 1;
+    config.dstinc_en = 0;
+    
+    srcdst.ch = channel;
+    srcdst.source = (uint8_t*) req->dataBuffer;         //transfering bytes
+    srcdst.len = req->dataLen * 4;                      //number of bytes
+    
+    MXC_CRC->ctrl |= MXC_F_CRC_CTRL_DMA_EN;
+    MXC_CRC->ctrl |= MXC_F_CRC_CTRL_EN;
+
+    MXC_DMA_ConfigChannel(config,srcdst);
+    MXC_DMA_SetCallback(channel,(void *) MXC_CRC_Handler);
+    MXC_DMA_EnableInt(channel);
+    MXC_DMA_Start(channel);
+    //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;
+    MXC_DMA_SetChannelInterruptEn(channel, 0, 1);
+    
+    return E_NO_ERROR;
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva.h

@@ -0,0 +1,70 @@
+/* ****************************************************************************
+ * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include "crc.h"
+#include "crc_reva_regs.h"
+
+
+/***** CRC Definitions *****/
+/**
+  * @brief  Structure used to set up CRC request
+  *
+  */
+typedef struct _mxc_crc_reva_req_t {
+    uint32_t* dataBuffer;     ///< Pointer to the data 
+    uint32_t dataLen;         ///< Length of the data
+    uint32_t resultCRC;       ///< Calculated CRC value
+} mxc_crc_reva_req_t;
+
+/** 
+ * @brief CRC data bit order
+ *  
+ */
+typedef enum {
+    CRC_REVA_LSB_FIRST,
+    CRC_REVA_MSB_FIRST
+} mxc_crc_reva_bitorder_t;
+
+
+int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t* crc);
+int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t* crc);
+int MXC_CRC_RevA_Handler(int ch, int error);
+void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder);
+mxc_crc_bitorder_t MXC_CRC_RevA_GetDirection(mxc_crc_reva_regs_t* crc);
+void MXC_CRC_RevA_SwapDataIn(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder);
+void MXC_CRC_RevA_SwapDataOut(mxc_crc_reva_regs_t* crc, mxc_crc_reva_bitorder_t bitOrder);
+void MXC_CRC_RevA_SetPoly(mxc_crc_reva_regs_t* crc, uint32_t poly);
+uint32_t MXC_CRC_RevA_GetPoly(mxc_crc_reva_regs_t* crc);
+uint32_t MXC_CRC_RevA_GetResult(mxc_crc_reva_regs_t* crc);
+int MXC_CRC_RevA_Compute(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req);
+int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t* crc, mxc_crc_reva_req_t* req);

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/CRC/crc_reva_regs.h

@@ -0,0 +1,199 @@
+/**
+ * @file    crc_reva_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the CRC_REVA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _CRC_REVA_REGS_H_
+#define _CRC_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     crc_reva
+ * @defgroup    crc_reva_registers CRC_REVA_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the CRC_REVA Peripheral Module.
+ * @details CRC Registers.
+ */
+
+/**
+ * @ingroup crc_reva_registers
+ * Structure type to access the CRC_REVA Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x0000:</tt> CRC_REVA CTRL Register */
+  union{
+    __IO uint32_t datain32;             /**< <tt>\b 0x0004:</tt> CRC_REVA DATAIN32 Register */
+    __IO uint16_t datain16[2];          /**< <tt>\b 0x0004:</tt> CRC_REVA DATAIN16 Register */
+    __IO uint8_t  datain8[4];           /**< <tt>\b 0x0004:</tt> CRC_REVA DATAIN8 Register */
+  };
+    __IO uint32_t poly;                 /**< <tt>\b 0x0008:</tt> CRC_REVA POLY Register */
+    __IO uint32_t val;                  /**< <tt>\b 0x000C:</tt> CRC_REVA VAL Register */
+} mxc_crc_reva_regs_t;
+
+/* Register offsets for module CRC_REVA */
+/**
+ * @ingroup    crc_reva_registers
+ * @defgroup   CRC_REVA_Register_Offsets Register Offsets
+ * @brief      CRC_REVA Peripheral Register Offsets from the CRC_REVA Base Peripheral Address.
+ * @{
+ */
+ #define MXC_R_CRC_REVA_CTRL                ((uint32_t)0x00000000UL) /**< Offset from CRC_REVA Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_CRC_REVA_DATAIN32            ((uint32_t)0x00000004UL) /**< Offset from CRC_REVA Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_CRC_REVA_DATAIN16            ((uint32_t)0x00000004UL) /**< Offset from CRC_REVA Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_CRC_REVA_DATAIN8             ((uint32_t)0x00000004UL) /**< Offset from CRC_REVA Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_CRC_REVA_POLY                ((uint32_t)0x00000008UL) /**< Offset from CRC_REVA Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_CRC_REVA_VAL                 ((uint32_t)0x0000000CUL) /**< Offset from CRC_REVA Base Address: <tt> 0x000C</tt> */ 
+/**@} end of group crc_reva_registers */
+
+/**
+ * @ingroup  crc_reva_registers
+ * @defgroup CRC_REVA_CTRL CRC_REVA_CTRL
+ * @brief    CRC Control
+ * @{
+ */
+ #define MXC_F_CRC_REVA_CTRL_EN_POS                     0 /**< CTRL_EN Position */
+ #define MXC_F_CRC_REVA_CTRL_EN                         ((uint32_t)(0x1UL << MXC_F_CRC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_CRC_REVA_CTRL_DMA_EN_POS                 1 /**< CTRL_DMA_EN Position */
+ #define MXC_F_CRC_REVA_CTRL_DMA_EN                     ((uint32_t)(0x1UL << MXC_F_CRC_REVA_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */
+
+ #define MXC_F_CRC_REVA_CTRL_MSB_POS                    2 /**< CTRL_MSB Position */
+ #define MXC_F_CRC_REVA_CTRL_MSB                        ((uint32_t)(0x1UL << MXC_F_CRC_REVA_CTRL_MSB_POS)) /**< CTRL_MSB Mask */
+
+ #define MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS           3 /**< CTRL_BYTE_SWAP_IN Position */
+ #define MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN               ((uint32_t)(0x1UL << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */
+
+ #define MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS          4 /**< CTRL_BYTE_SWAP_OUT Position */
+ #define MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT              ((uint32_t)(0x1UL << MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */
+
+ #define MXC_F_CRC_REVA_CTRL_BUSY_POS                   16 /**< CTRL_BUSY Position */
+ #define MXC_F_CRC_REVA_CTRL_BUSY                       ((uint32_t)(0x1UL << MXC_F_CRC_REVA_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
+
+/**@} end of group CRC_REVA_CTRL_Register */
+
+/**
+ * @ingroup  crc_reva_registers
+ * @defgroup CRC_REVA_DATAIN32 CRC_REVA_DATAIN32
+ * @brief    CRC Data Input
+ * @{
+ */
+ #define MXC_F_CRC_REVA_DATAIN32_DATA_POS               0 /**< DATAIN32_DATA Position */
+ #define MXC_F_CRC_REVA_DATAIN32_DATA                   ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_REVA_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */
+
+/**@} end of group CRC_REVA_DATAIN32_Register */
+
+/**
+ * @ingroup  crc_reva_registers
+ * @defgroup CRC_REVA_DATAIN16 CRC_REVA_DATAIN16
+ * @brief    CRC Data Input
+ * @{
+ */
+ #define MXC_F_CRC_REVA_DATAIN16_DATA_POS               0 /**< DATAIN16_DATA Position */
+ #define MXC_F_CRC_REVA_DATAIN16_DATA                   ((uint16_t)(0xFFFFUL << MXC_F_CRC_REVA_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */
+
+/**@} end of group CRC_REVA_DATAIN16_Register */
+
+/**
+ * @ingroup  crc_reva_registers
+ * @defgroup CRC_REVA_DATAIN8 CRC_REVA_DATAIN8
+ * @brief    CRC Data Input
+ * @{
+ */
+ #define MXC_F_CRC_REVA_DATAIN8_DATA_POS                0 /**< DATAIN8_DATA Position */
+ #define MXC_F_CRC_REVA_DATAIN8_DATA                    ((uint8_t)(0xFFUL << MXC_F_CRC_REVA_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */
+
+/**@} end of group CRC_REVA_DATAIN8_Register */
+
+/**
+ * @ingroup  crc_reva_registers
+ * @defgroup CRC_REVA_POLY CRC_REVA_POLY
+ * @brief    CRC Polynomial
+ * @{
+ */
+ #define MXC_F_CRC_REVA_POLY_POLY_POS                   0 /**< POLY_POLY Position */
+ #define MXC_F_CRC_REVA_POLY_POLY                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_REVA_POLY_POLY_POS)) /**< POLY_POLY Mask */
+
+/**@} end of group CRC_REVA_POLY_Register */
+
+/**
+ * @ingroup  crc_reva_registers
+ * @defgroup CRC_REVA_VAL CRC_REVA_VAL
+ * @brief    Current CRC Value
+ * @{
+ */
+ #define MXC_F_CRC_REVA_VAL_VALUE_POS                   0 /**< VAL_VALUE Position */
+ #define MXC_F_CRC_REVA_VAL_VALUE                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_REVA_VAL_VALUE_POS)) /**< VAL_VALUE Mask */
+
+/**@} end of group CRC_REVA_VAL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CRC_REVA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_me15.c

@@ -0,0 +1,164 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/****** Includes *******/
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "dma.h"
+#include "dma_reva.h"
+
+/****** Functions ******/
+
+int MXC_DMA_Init(void)
+{
+	if(!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) {
+		MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA);
+    	MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA);
+	}
+
+    return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t*) MXC_DMA);
+}
+
+int MXC_DMA_AcquireChannel(void)
+{
+    return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t*) MXC_DMA);
+}
+
+int MXC_DMA_ReleaseChannel(int ch)
+{
+    return MXC_DMA_RevA_ReleaseChannel(ch);
+}
+
+int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
+{
+    return MXC_DMA_RevA_ConfigChannel(config, srcdst);
+}
+
+int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
+{
+    return MXC_DMA_RevA_AdvConfigChannel(advConfig);
+}
+
+int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst)
+{
+    return MXC_DMA_RevA_SetSrcDst(srcdst);
+}
+
+int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t* srcdst)
+{
+    return MXC_DMA_RevA_GetSrcDst(srcdst);
+}
+
+int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdst)
+{
+    return MXC_DMA_RevA_SetSrcReload(srcdst);
+}
+
+int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdst)
+{
+    return MXC_DMA_RevA_GetSrcReload(srcdst);
+}
+
+int MXC_DMA_SetCallback(int ch, void (*callback)(int, int))
+{
+    return MXC_DMA_RevA_SetCallback(ch, callback);
+}
+
+int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
+{
+	return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz);
+}
+
+int MXC_DMA_ChannelEnableInt(int ch, int flags)
+{
+    return MXC_DMA_RevA_ChannelEnableInt(ch, flags);
+}
+
+int MXC_DMA_ChannelDisableInt(int ch, int flags)
+{
+    return MXC_DMA_RevA_ChannelDisableInt(ch, flags);
+}
+
+int MXC_DMA_ChannelGetFlags(int ch)
+{
+    return MXC_DMA_RevA_ChannelGetFlags(ch);
+}
+
+int MXC_DMA_ChannelClearFlags(int ch, int flags)
+{
+    return MXC_DMA_RevA_ChannelClearFlags(ch, flags);
+}
+
+int MXC_DMA_EnableInt(int ch)
+{
+    return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch);
+}
+
+int MXC_DMA_DisableInt(int ch)
+{
+    return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch);
+}
+
+int MXC_DMA_Start(int ch)
+{
+    return MXC_DMA_RevA_Start(ch);
+}
+
+int MXC_DMA_Stop(int ch)
+{
+    return MXC_DMA_RevA_Stop(ch);
+}
+
+mxc_dma_ch_regs_t* MXC_DMA_GetCHRegs(int ch)
+{
+    return MXC_DMA_RevA_GetCHRegs(ch);
+}
+
+void MXC_DMA_Handler(void)
+{
+    MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t*) MXC_DMA);
+}
+
+int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
+{
+    return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t*) MXC_DMA, dest, src, len, callback);
+}
+
+int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
+{
+    return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t*) MXC_DMA, config, firstSrcDst, callback);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.c

@@ -0,0 +1,584 @@
+/* ****************************************************************************
+ * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+#ifdef __CC_ARM  // Keil 
+#pragma diag_suppress 68  // integer conversion resulted in a change of sign
+#endif
+
+/****** Includes *******/
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "dma.h"
+#include "dma_reva.h"
+#include "dma_reva_regs.h"
+
+/***** Definitions *****/
+#define CHECK_HANDLE(x)((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid))
+
+typedef struct {
+    void*  userCallback;    // user given callback
+    void*  dest;            // memcpy destination
+} mxc_dma_highlevel_t;
+
+typedef struct {
+    unsigned int valid;         // Flag to invalidate this resource 
+    unsigned int instance;      // Hardware instance of this DMA controller 
+    unsigned int id;            // Channel ID, which matches the index into the underlying hardware 
+    mxc_dma_reva_ch_regs_t *regs;    // Pointer to the registers for this channel
+    void(*cb)(int, int);      // Pointer to a callback function type 
+} mxc_dma_channel_t;
+
+/******* Globals *******/
+static unsigned int dma_initialized[MXC_DMA_INSTANCES] = {0};
+static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS];
+static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS];
+#if USE_LOCK_IN_DRIVERS
+    static uint32_t dma_lock;
+#endif
+
+/****** Functions ******/
+static void memcpy_callback(int ch, int error);
+static void transfer_callback(int ch, int error);
+
+int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma)
+{
+    int i, numCh, offset;
+#if TARGET_NUM == 32665
+    numCh = MXC_DMA_CH_OFFSET;
+    offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
+#else
+    numCh = MXC_DMA_CHANNELS;
+    offset = 0;
+#endif
+    
+    if(dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) {
+        return E_BAD_STATE;
+    }
+    
+#ifndef __riscv
+        /* Initialize mutex */
+        MXC_FreeLock(&dma_lock);
+        
+        if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
+            return E_BUSY;
+        }
+#endif
+    
+    /* Ensure all channels are disabled at start, clear flags, init handles */
+    dma->inten = 0;
+    
+    for(i = offset; i < (offset + numCh); i++) {
+        dma_resource[i].valid = 0;
+        dma_resource[i].instance = 0;
+        dma_resource[i].id = i;
+        dma_resource[i].regs = (mxc_dma_reva_ch_regs_t*) &(dma->ch[(i % numCh)]);
+        dma_resource[i].regs->ctrl = 0;
+        dma_resource[i].regs->status = dma_resource[i].regs->status;
+        
+        dma_resource[i].cb = NULL;
+    }
+    
+    dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]++;
+#ifndef __riscv
+        MXC_FreeLock(&dma_lock);
+#endif
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma)
+{
+    int i, channel, numCh, offset;
+    
+    /* Check for initialization */
+    if(!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) {
+        return E_BAD_STATE;
+    }
+    
+#if TARGET_NUM == 32665
+    numCh = MXC_DMA_CH_OFFSET;
+    offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
+#else
+    numCh = MXC_DMA_CHANNELS;
+    offset = 0;
+#endif
+
+#ifndef __riscv
+    /* If DMA is locked return busy */
+    if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+#endif
+    /* Default is no channel available */
+    channel = E_NONE_AVAIL;
+    
+    for(i = offset; i < (offset + numCh); i++) {
+        if(!dma_resource[i].valid) {
+            /* Found one */
+            channel = i;
+            dma_resource[i].valid = 1;
+            dma_resource[i].regs->ctrl = 0;
+            dma_resource[i].regs->cntrld = 0; /* Used by DMA_Start() to conditionally set RLDEN */
+            break;
+        }
+    }
+#ifndef __riscv
+    MXC_FreeLock(&dma_lock);
+#endif
+
+    return channel;
+}
+
+int MXC_DMA_RevA_ReleaseChannel(int ch)
+{
+    if(CHECK_HANDLE(ch)) {
+        if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) {
+            return E_BUSY;
+        }
+        
+        dma_resource[ch].valid = 0;
+        dma_resource[ch].regs->ctrl = 0;
+        dma_resource[ch].regs->status = dma_resource[ch].regs->status;
+        MXC_FreeLock(&dma_lock);
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst)
+{
+    if(CHECK_HANDLE(config.ch)) {
+        /* Designed to be safe, not speedy. Should not be called often */
+        dma_resource[config.ch].regs->ctrl =
+             ((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0)   |
+              (config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0)   |
+              config.reqsel |
+              (config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) |
+              (config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return MXC_DMA_RevA_SetSrcDst(srcdst);
+}
+
+
+int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig)
+{
+    if(CHECK_HANDLE(advConfig.ch) &&(advConfig.burst_size > 0)) {
+        dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here
+        /* Designed to be safe, not speedy. Should not be called often */
+        dma_resource[advConfig.ch].regs->ctrl |=
+              ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) |
+              advConfig.prio | advConfig.tosel | advConfig.pssel |
+              (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE));
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+
+int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst)
+{
+    if(CHECK_HANDLE(srcdst.ch)) {
+        dma_resource[srcdst.ch].regs->src = (unsigned int) srcdst.source;
+        dma_resource[srcdst.ch].regs->dst = (unsigned int) srcdst.dest;
+        dma_resource[srcdst.ch].regs->cnt = srcdst.len;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+
+int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t* srcdst)
+{
+    if (CHECK_HANDLE(srcdst->ch)) {
+        srcdst->source = (void*) dma_resource[srcdst->ch].regs->src;
+        srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dst;
+        srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+
+int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst)
+{
+    if(CHECK_HANDLE(srcdst.ch)) {
+        dma_resource[srcdst.ch].regs->srcrld = (unsigned int) srcdst.source;
+        dma_resource[srcdst.ch].regs->dstrld = (unsigned int) srcdst.dest;
+        
+        if(dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) {
+            /* If channel is already running, set RLDEN to enable next reload */
+            dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len;
+        }
+        else {
+            /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
+            dma_resource[srcdst.ch].regs->cntrld = srcdst.len;
+        }
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+
+int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t* srcdst)
+{
+    if (CHECK_HANDLE(srcdst->ch)) {
+        srcdst->source = (void*) dma_resource[srcdst->ch].regs->srcrld;
+        srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dstrld;
+        srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+
+int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int))
+{
+    if(CHECK_HANDLE(ch)) {
+        /* Callback for interrupt handler, no checking is done, as NULL is valid for(none)  */
+        dma_resource[ch].cb = callback;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz)
+{
+    if(CHECK_HANDLE(ch)) {
+    	if(chdis){
+    		dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE);
+    	}
+    	if(ctz){
+    		dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE);
+    	}
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+
+    return E_NO_ERROR;
+}
+
+
+int MXC_DMA_RevA_GetChannelInterruptEn(int ch)
+{
+    return E_NOT_SUPPORTED;
+}
+
+int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags)
+{
+    if(CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags)
+{
+    if(CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE));
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch)
+{
+    if(CHECK_HANDLE(ch)) {
+      #if TARGET_NUM == 32665
+        ch %= MXC_DMA_CH_OFFSET;
+      #endif
+    	dma->inten |= (1 << ch);
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch)
+{
+    if(CHECK_HANDLE(ch)) {
+      #if TARGET_NUM == 32665
+        ch %= MXC_DMA_CH_OFFSET;
+      #endif
+    	dma->inten &= ~(1 << ch);
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_ChannelGetFlags(int ch)
+{
+    if(CHECK_HANDLE(ch)) {
+        return dma_resource[ch].regs->status;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags)
+{
+    if(CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->status |= (flags & 0x5F);  // Mask for Interrupt flags 
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_Start(int ch)
+{
+    if(CHECK_HANDLE(ch)) {
+        MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch));
+        
+        if(dma_resource[ch].regs->cntrld) {
+            dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN);
+        }
+        else {
+            dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN;
+        }
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_DMA_RevA_Stop(int ch)
+{
+    if(CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch)
+{
+    if(CHECK_HANDLE(ch)) {
+        return(mxc_dma_ch_regs_t*) dma_resource[ch].regs;
+    }
+    else {
+        return NULL;
+    }
+}
+
+void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma)
+{
+    int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES;
+    int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma);
+    /* Do callback, if enabled */
+    for(int i = offset; i < (offset + numCh); i++) {
+        if(CHECK_HANDLE(i)) {
+            if(dma->intfl &(0x1 << (i % numCh))) {
+                if(dma_resource[i].cb != NULL) {
+                    dma_resource[i].cb(i, E_NO_ERROR);
+                }
+                
+                MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i));
+                break;
+            }
+        }
+    }
+}
+
+void memcpy_callback(int ch, int error)
+{
+    mxc_dma_complete_cb_t callback;
+    callback = (mxc_dma_complete_cb_t) memcpy_resource[ch].userCallback;
+    
+    if(error != E_NO_ERROR) {
+        callback(NULL);
+    }
+    
+    callback(memcpy_resource[ch].dest);
+    
+    callback = NULL;
+    MXC_DMA_ReleaseChannel(ch);
+}
+
+int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback)
+{
+    int retval;
+    mxc_dma_config_t config;
+    mxc_dma_srcdst_t transfer;
+    int channel;
+
+  #if TARGET_NUM == 32665
+    channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma);
+  #else
+    channel = MXC_DMA_AcquireChannel();
+  #endif
+    
+    if(memcpy_resource[channel].userCallback != NULL) {
+        // We acquired a channel we haven't cleared yet
+        MXC_DMA_ReleaseChannel(channel);
+        return E_UNKNOWN;
+    }
+    
+    transfer.ch = channel;
+    transfer.source = src;
+    transfer.dest = dest;
+    transfer.len = len;
+    
+    config.ch = channel;
+    config.reqsel = MXC_DMA_REQUEST_MEMTOMEM;
+    config.srcwd = MXC_DMA_WIDTH_WORD;
+    config.dstwd = MXC_DMA_WIDTH_WORD;
+    config.srcinc_en = 1;
+    config.dstinc_en = 1;
+    
+    retval = MXC_DMA_ConfigChannel(config, transfer);
+    
+    if(retval != E_NO_ERROR) {
+        return retval;
+    }
+    
+    retval = MXC_DMA_EnableInt(channel);
+    
+    if(retval != E_NO_ERROR) {
+        return retval;
+    }
+    
+    retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
+    
+    if(retval != E_NO_ERROR) {
+        return retval;
+    }
+    
+    MXC_DMA_SetCallback(channel, memcpy_callback);
+    
+    memcpy_resource[channel].userCallback = (void*) callback;
+    memcpy_resource[channel].dest = dest;
+    
+    return MXC_DMA_Start(channel);
+}
+
+void transfer_callback(int ch, int error)
+{
+    // Unimplemented
+    // Check for reason
+    // Call user callback for next transfer
+    // determine whether to load into the transfer slot or reload slot
+    // continue on or stop
+    while(1);
+}
+
+int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback)
+{
+    int retval, channel;
+
+  #if TARGET_NUM == 32665
+    channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma);
+  #else
+    channel = MXC_DMA_AcquireChannel();
+  #endif
+    
+    if(memcpy_resource[channel].userCallback != NULL) {
+        // We acquired a channel we haven't cleared yet
+        MXC_DMA_ReleaseChannel(channel);
+        return E_UNKNOWN;
+    }
+    
+    retval = MXC_DMA_ConfigChannel(config, firstSrcDst);
+    
+    if(retval != E_NO_ERROR) {
+        return retval;
+    }
+    
+    retval = MXC_DMA_EnableInt(channel);
+    
+    if(retval != E_NO_ERROR) {
+        return retval;
+    }
+    
+    retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE);
+    
+    if(retval != E_NO_ERROR) {
+        return retval;
+    }
+    
+    MXC_DMA_SetCallback(channel, transfer_callback);
+    
+    memcpy_resource[channel].userCallback = (void*) callback;
+    
+    return MXC_DMA_Start(channel);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva.h

@@ -0,0 +1,65 @@
+/* ****************************************************************************
+ * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/****** Includes *******/
+#include "dma_reva_regs.h"
+#include <stdbool.h>
+
+/***** Definitions *****/
+
+/******* Globals *******/
+
+/****** Functions ******/
+int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma);
+int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma);
+int MXC_DMA_RevA_ReleaseChannel(int ch);
+int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst);
+int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
+int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst);
+int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst);
+int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst);
+int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst);
+int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int));
+int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz);
+int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags);
+int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags);
+int MXC_DMA_RevA_ChannelGetFlags(int ch);
+int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags);
+int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch);
+int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch);
+int MXC_DMA_RevA_Start(int ch);
+int MXC_DMA_RevA_Stop(int ch);
+mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch);
+void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma);
+int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback);
+int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback);

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h

@@ -0,0 +1,532 @@
+/**
+ * @file    dma_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _DMA_REVA_REGS_H_
+#define _DMA_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     dma
+ * @defgroup    dma_registers DMA_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
+ * @details DMA Controller Fully programmable, chaining capable DMA channels.
+ */
+
+/**
+ * @ingroup dma_registers
+ * Structure type to access the DMA Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x100:</tt> DMA CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x104:</tt> DMA STATUS Register */
+    __IO uint32_t src;                  /**< <tt>\b 0x108:</tt> DMA SRC Register */
+    __IO uint32_t dst;                  /**< <tt>\b 0x10C:</tt> DMA DST Register */
+    __IO uint32_t cnt;                  /**< <tt>\b 0x110:</tt> DMA CNT Register */
+    __IO uint32_t srcrld;               /**< <tt>\b 0x114:</tt> DMA SRCRLD Register */
+    __IO uint32_t dstrld;               /**< <tt>\b 0x118:</tt> DMA DSTRLD Register */
+    __IO uint32_t cntrld;               /**< <tt>\b 0x11C:</tt> DMA CNTRLD Register */
+} mxc_dma_reva_ch_regs_t;
+
+typedef struct {
+    __IO uint32_t inten;                /**< <tt>\b 0x000:</tt> DMA INTEN Register */
+    __I  uint32_t intfl;                /**< <tt>\b 0x004:</tt> DMA INTFL Register */
+    __R  uint32_t rsv_0x8_0xff[62];
+    __IO mxc_dma_reva_ch_regs_t    ch[8];    /**< <tt>\b 0x100:</tt> DMA CH Register */
+} mxc_dma_reva_regs_t;
+
+/* Register offsets for module DMA */
+/**
+ * @ingroup    dma_registers
+ * @defgroup   DMA_Register_Offsets Register Offsets
+ * @brief      DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_DMA_REVA_CTRL                     ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
+ #define MXC_R_DMA_REVA_STATUS                   ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
+ #define MXC_R_DMA_REVA_SRC                      ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
+ #define MXC_R_DMA_REVA_DST                      ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
+ #define MXC_R_DMA_REVA_CNT                      ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
+ #define MXC_R_DMA_REVA_SRCRLD                   ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
+ #define MXC_R_DMA_REVA_DSTRLD                   ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
+ #define MXC_R_DMA_REVA_CNTRLD                   ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
+ #define MXC_R_DMA_REVA_INTEN                    ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
+ #define MXC_R_DMA_REVA_INTFL                    ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
+ #define MXC_R_DMA_REVA_CH                       ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
+/**@} end of group dma_registers */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_INTEN DMA_INTEN
+ * @brief    DMA Control Register.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_INTEN_CH0_POS                        0 /**< INTEN_CH0 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH1_POS                        1 /**< INTEN_CH1 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH2_POS                        2 /**< INTEN_CH2 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH3_POS                        3 /**< INTEN_CH3 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH4_POS                        4 /**< INTEN_CH4 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH4                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH5_POS                        5 /**< INTEN_CH5 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH5                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH6_POS                        6 /**< INTEN_CH6 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH6                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH7_POS                        7 /**< INTEN_CH7 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH7                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH8_POS                        8 /**< INTEN_CH8 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH8                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH8_POS)) /**< INTEN_CH8 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH9_POS                        9 /**< INTEN_CH9 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH9                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH9_POS)) /**< INTEN_CH9 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH10_POS                       10 /**< INTEN_CH10 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH10                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH10_POS)) /**< INTEN_CH10 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH11_POS                       11 /**< INTEN_CH11 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH11                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH11_POS)) /**< INTEN_CH11 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH12_POS                       12 /**< INTEN_CH12 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH12                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH12_POS)) /**< INTEN_CH12 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH13_POS                       13 /**< INTEN_CH13 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH13                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH13_POS)) /**< INTEN_CH13 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH14_POS                       14 /**< INTEN_CH14 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH14                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH14_POS)) /**< INTEN_CH14 Mask */
+
+ #define MXC_F_DMA_REVA_INTEN_CH15_POS                       15 /**< INTEN_CH15 Position */
+ #define MXC_F_DMA_REVA_INTEN_CH15                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH15_POS)) /**< INTEN_CH15 Mask */
+
+/**@} end of group DMA_INTEN_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_INTFL DMA_INTFL
+ * @brief    DMA Interrupt Register.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_INTFL_CH0_POS                        0 /**< INTFL_CH0 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH1_POS                        1 /**< INTFL_CH1 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH2_POS                        2 /**< INTFL_CH2 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH3_POS                        3 /**< INTFL_CH3 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH4_POS                        4 /**< INTFL_CH4 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH4                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH5_POS                        5 /**< INTFL_CH5 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH5                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH6_POS                        6 /**< INTFL_CH6 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH6                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH7_POS                        7 /**< INTFL_CH7 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH7                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH8_POS                        8 /**< INTFL_CH8 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH8                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH8_POS)) /**< INTFL_CH8 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH9_POS                        9 /**< INTFL_CH9 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH9                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH9_POS)) /**< INTFL_CH9 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH10_POS                       10 /**< INTFL_CH10 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH10                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH10_POS)) /**< INTFL_CH10 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH11_POS                       11 /**< INTFL_CH11 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH11                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH11_POS)) /**< INTFL_CH11 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH12_POS                       12 /**< INTFL_CH12 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH12                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH12_POS)) /**< INTFL_CH12 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH13_POS                       13 /**< INTFL_CH13 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH13                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH13_POS)) /**< INTFL_CH13 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH14_POS                       14 /**< INTFL_CH14 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH14                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH14_POS)) /**< INTFL_CH14 Mask */
+
+ #define MXC_F_DMA_REVA_INTFL_CH15_POS                       15 /**< INTFL_CH15 Position */
+ #define MXC_F_DMA_REVA_INTFL_CH15                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH15_POS)) /**< INTFL_CH15 Mask */
+
+/**@} end of group DMA_INTFL_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CTRL DMA_CTRL
+ * @brief    DMA Channel Control Register.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_DMA_REVA_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_DMA_REVA_CTRL_RLDEN_POS                       1 /**< CTRL_RLDEN Position */
+ #define MXC_F_DMA_REVA_CTRL_RLDEN                           ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */
+
+ #define MXC_F_DMA_REVA_CTRL_PRI_POS                         2 /**< CTRL_PRI Position */
+ #define MXC_F_DMA_REVA_CTRL_PRI                             ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */
+ #define MXC_V_DMA_REVA_CTRL_PRI_HIGH                        ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */
+ #define MXC_S_DMA_REVA_CTRL_PRI_HIGH                        (MXC_V_DMA_REVA_CTRL_PRI_HIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */
+ #define MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH                     ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */
+ #define MXC_S_DMA_REVA_CTRL_PRI_MEDHIGH                     (MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */
+ #define MXC_V_DMA_REVA_CTRL_PRI_MEDLOW                      ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */
+ #define MXC_S_DMA_REVA_CTRL_PRI_MEDLOW                      (MXC_V_DMA_REVA_CTRL_PRI_MEDLOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */
+ #define MXC_V_DMA_REVA_CTRL_PRI_LOW                         ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */
+ #define MXC_S_DMA_REVA_CTRL_PRI_LOW                         (MXC_V_DMA_REVA_CTRL_PRI_LOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */
+
+ #define MXC_F_DMA_REVA_CTRL_REQUEST_POS                     4 /**< CTRL_REQUEST Position */
+ #define MXC_F_DMA_REVA_CTRL_REQUEST                         ((uint32_t)(0x3FUL << MXC_F_DMA_REVA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM                ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_MEMTOMEM                (MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX                  ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0RX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX                  ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1RX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX                  ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2RX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX                 ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_UART0RX                 (MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX                 ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_UART1RX                 (MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX                  ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0RX                  (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX                  ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1RX                  (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_ADC                     ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_ADC                     (MXC_V_DMA_REVA_CTRL_REQUEST_ADC << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX                 ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_UART2RX                 (MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX                  ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3RX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX              ((uint32_t)0x10UL) /**< CTRL_REQUEST_SPI_MSS0RX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX              (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0RX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1                ((uint32_t)0x11UL) /**< CTRL_REQUEST_USBRXEP1 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP1                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP1 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2                ((uint32_t)0x12UL) /**< CTRL_REQUEST_USBRXEP2 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP2                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP2 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3                ((uint32_t)0x13UL) /**< CTRL_REQUEST_USBRXEP3 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP3                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP3 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4                ((uint32_t)0x14UL) /**< CTRL_REQUEST_USBRXEP4 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP4                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP4 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5                ((uint32_t)0x15UL) /**< CTRL_REQUEST_USBRXEP5 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP5                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP5 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6                ((uint32_t)0x16UL) /**< CTRL_REQUEST_USBRXEP6 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP6                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP6 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7                ((uint32_t)0x17UL) /**< CTRL_REQUEST_USBRXEP7 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP7                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP7 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8                ((uint32_t)0x18UL) /**< CTRL_REQUEST_USBRXEP8 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP8                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP8 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9                ((uint32_t)0x19UL) /**< CTRL_REQUEST_USBRXEP9 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP9                (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP9 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10               ((uint32_t)0x1AUL) /**< CTRL_REQUEST_USBRXEP10 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP10               (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP10 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11               ((uint32_t)0x1BUL) /**< CTRL_REQUEST_USBRXEP11 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP11               (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP11 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX                  ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0TX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX                  ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1TX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX                  ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2TX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX                 ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_UART0TX                 (MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX                 ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_UART1TX                 (MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX                  ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0TX                  (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX                  ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1TX                  (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX                 ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_UART2TX                 (MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX                  ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3TX                  (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX              ((uint32_t)0x30UL) /**< CTRL_REQUEST_SPI_MSS0TX Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX              (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0TX Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1                ((uint32_t)0x31UL) /**< CTRL_REQUEST_USBTXEP1 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP1                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP1 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2                ((uint32_t)0x32UL) /**< CTRL_REQUEST_USBTXEP2 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP2                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP2 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3                ((uint32_t)0x33UL) /**< CTRL_REQUEST_USBTXEP3 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP3                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP3 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4                ((uint32_t)0x34UL) /**< CTRL_REQUEST_USBTXEP4 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP4                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP4 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5                ((uint32_t)0x35UL) /**< CTRL_REQUEST_USBTXEP5 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP5                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP5 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6                ((uint32_t)0x36UL) /**< CTRL_REQUEST_USBTXEP6 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP6                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP6 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7                ((uint32_t)0x37UL) /**< CTRL_REQUEST_USBTXEP7 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP7                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP7 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8                ((uint32_t)0x38UL) /**< CTRL_REQUEST_USBTXEP8 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP8                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP8 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9                ((uint32_t)0x39UL) /**< CTRL_REQUEST_USBTXEP9 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP9                (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP9 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10               ((uint32_t)0x3AUL) /**< CTRL_REQUEST_USBTXEP10 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP10               (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP10 Setting */
+ #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11               ((uint32_t)0x3BUL) /**< CTRL_REQUEST_USBTXEP11 Value */
+ #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP11               (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP11 Setting */
+
+ #define MXC_F_DMA_REVA_CTRL_TO_WAIT_POS                     10 /**< CTRL_TO_WAIT Position */
+ #define MXC_F_DMA_REVA_CTRL_TO_WAIT                         ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */
+
+ #define MXC_F_DMA_REVA_CTRL_TO_PER_POS                      11 /**< CTRL_TO_PER Position */
+ #define MXC_F_DMA_REVA_CTRL_TO_PER                          ((uint32_t)(0x7UL << MXC_F_DMA_REVA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO4                      ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO4                      (MXC_V_DMA_REVA_CTRL_TO_PER_TO4 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO8                      ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO8                      (MXC_V_DMA_REVA_CTRL_TO_PER_TO8 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO16                     ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO16                     (MXC_V_DMA_REVA_CTRL_TO_PER_TO16 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO32                     ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO32                     (MXC_V_DMA_REVA_CTRL_TO_PER_TO32 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO64                     ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO64                     (MXC_V_DMA_REVA_CTRL_TO_PER_TO64 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO128                    ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO128                    (MXC_V_DMA_REVA_CTRL_TO_PER_TO128 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO256                    ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO256                    (MXC_V_DMA_REVA_CTRL_TO_PER_TO256 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_PER_TO512                    ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_PER_TO512                    (MXC_V_DMA_REVA_CTRL_TO_PER_TO512 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */
+
+ #define MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS                   14 /**< CTRL_TO_CLKDIV Position */
+ #define MXC_F_DMA_REVA_CTRL_TO_CLKDIV                       ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */
+ #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS                   ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIS                   (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256                ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV256                (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K                ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV64K                (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */
+ #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M                ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */
+ #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV16M                (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */
+
+ #define MXC_F_DMA_REVA_CTRL_SRCWD_POS                       16 /**< CTRL_SRCWD Position */
+ #define MXC_F_DMA_REVA_CTRL_SRCWD                           ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */
+ #define MXC_V_DMA_REVA_CTRL_SRCWD_BYTE                      ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */
+ #define MXC_S_DMA_REVA_CTRL_SRCWD_BYTE                      (MXC_V_DMA_REVA_CTRL_SRCWD_BYTE << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */
+ #define MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD                  ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */
+ #define MXC_S_DMA_REVA_CTRL_SRCWD_HALFWORD                  (MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */
+ #define MXC_V_DMA_REVA_CTRL_SRCWD_WORD                      ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */
+ #define MXC_S_DMA_REVA_CTRL_SRCWD_WORD                      (MXC_V_DMA_REVA_CTRL_SRCWD_WORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */
+
+ #define MXC_F_DMA_REVA_CTRL_SRCINC_POS                      18 /**< CTRL_SRCINC Position */
+ #define MXC_F_DMA_REVA_CTRL_SRCINC                          ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */
+
+ #define MXC_F_DMA_REVA_CTRL_DSTWD_POS                       20 /**< CTRL_DSTWD Position */
+ #define MXC_F_DMA_REVA_CTRL_DSTWD                           ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */
+ #define MXC_V_DMA_REVA_CTRL_DSTWD_BYTE                      ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */
+ #define MXC_S_DMA_REVA_CTRL_DSTWD_BYTE                      (MXC_V_DMA_REVA_CTRL_DSTWD_BYTE << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */
+ #define MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD                  ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */
+ #define MXC_S_DMA_REVA_CTRL_DSTWD_HALFWORD                  (MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */
+ #define MXC_V_DMA_REVA_CTRL_DSTWD_WORD                      ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */
+ #define MXC_S_DMA_REVA_CTRL_DSTWD_WORD                      (MXC_V_DMA_REVA_CTRL_DSTWD_WORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */
+
+ #define MXC_F_DMA_REVA_CTRL_DSTINC_POS                      22 /**< CTRL_DSTINC Position */
+ #define MXC_F_DMA_REVA_CTRL_DSTINC                          ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */
+
+ #define MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS                  24 /**< CTRL_BURST_SIZE Position */
+ #define MXC_F_DMA_REVA_CTRL_BURST_SIZE                      ((uint32_t)(0x1FUL << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */
+
+ #define MXC_F_DMA_REVA_CTRL_DIS_IE_POS                      30 /**< CTRL_DIS_IE Position */
+ #define MXC_F_DMA_REVA_CTRL_DIS_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */
+
+ #define MXC_F_DMA_REVA_CTRL_CTZ_IE_POS                      31 /**< CTRL_CTZ_IE Position */
+ #define MXC_F_DMA_REVA_CTRL_CTZ_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */
+
+/**@} end of group DMA_CTRL_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_STATUS DMA_STATUS
+ * @brief    DMA Channel Status Register.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_STATUS_STATUS_POS                    0 /**< STATUS_STATUS Position */
+ #define MXC_F_DMA_REVA_STATUS_STATUS                        ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
+
+ #define MXC_F_DMA_REVA_STATUS_IPEND_POS                     1 /**< STATUS_IPEND Position */
+ #define MXC_F_DMA_REVA_STATUS_IPEND                         ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */
+
+ #define MXC_F_DMA_REVA_STATUS_CTZ_IF_POS                    2 /**< STATUS_CTZ_IF Position */
+ #define MXC_F_DMA_REVA_STATUS_CTZ_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */
+
+ #define MXC_F_DMA_REVA_STATUS_RLD_IF_POS                    3 /**< STATUS_RLD_IF Position */
+ #define MXC_F_DMA_REVA_STATUS_RLD_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */
+
+ #define MXC_F_DMA_REVA_STATUS_BUS_ERR_POS                   4 /**< STATUS_BUS_ERR Position */
+ #define MXC_F_DMA_REVA_STATUS_BUS_ERR                       ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */
+
+ #define MXC_F_DMA_REVA_STATUS_TO_IF_POS                     6 /**< STATUS_TO_IF Position */
+ #define MXC_F_DMA_REVA_STATUS_TO_IF                         ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */
+
+/**@} end of group DMA_STATUS_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_SRC DMA_SRC
+ * @brief    Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or
+ *           4, depending on the data width of each AHB cycle. For peripheral transfers, some
+ *           or all of the actual address bits are fixed. If SRCINC=0, this register remains
+ *           constant. In the case where a count-to-zero condition occurs while RLDEN=1, the
+ *           register is reloaded with the contents of DMA_SRC_RLD.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_SRC_ADDR_POS                         0 /**< SRC_ADDR Position */
+ #define MXC_F_DMA_REVA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */
+
+/**@} end of group DMA_SRC_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_DST DMA_DST
+ * @brief    Destination Device Address. For peripheral transfers, some or all of the actual
+ *           address bits are fixed. If DSTINC=1, this register is incremented on every AHB
+ *           write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the
+ *           data width of each AHB cycle. In the case where a count-to-zero condition occurs
+ *           while RLDEN=1, the register is reloaded with DMA_DST_RLD.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_DST_ADDR_POS                         0 /**< DST_ADDR Position */
+ #define MXC_F_DMA_REVA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_DST_ADDR_POS)) /**< DST_ADDR Mask */
+
+/**@} end of group DMA_DST_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CNT DMA_CNT
+ * @brief    DMA Counter. The user loads this register with the number of bytes to transfer.
+ *           This counter decreases on every AHB cycle into the DMA FIFO. The decrement will
+ *           be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter
+ *           reaches 0, a count-to-zero condition is triggered.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_CNT_CNT_POS                          0 /**< CNT_CNT Position */
+ #define MXC_F_DMA_REVA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNT_CNT_POS)) /**< CNT_CNT Mask */
+
+/**@} end of group DMA_CNT_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_SRCRLD DMA_SRCRLD
+ * @brief    Source Address Reload Value. The value of this register is loaded into DMA0_SRC
+ *           upon a count-to-zero condition.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_SRCRLD_ADDR_POS                      0 /**< SRCRLD_ADDR Position */
+ #define MXC_F_DMA_REVA_SRCRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */
+
+/**@} end of group DMA_SRCRLD_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_DSTRLD DMA_DSTRLD
+ * @brief    Destination Address Reload Value. The value of this register is loaded into
+ *           DMA0_DST upon a count-to-zero condition.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_DSTRLD_ADDR_POS                      0 /**< DSTRLD_ADDR Position */
+ #define MXC_F_DMA_REVA_DSTRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */
+
+/**@} end of group DMA_DSTRLD_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CNTRLD DMA_CNTRLD
+ * @brief    DMA Channel Count Reload Register.
+ * @{
+ */
+ #define MXC_F_DMA_REVA_CNTRLD_CNT_POS                       0 /**< CNTRLD_CNT Position */
+ #define MXC_F_DMA_REVA_CNTRLD_CNT                           ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */
+
+ #define MXC_F_DMA_REVA_CNTRLD_EN_POS                        31 /**< CNTRLD_EN Position */
+ #define MXC_F_DMA_REVA_CNTRLD_EN                            ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */
+
+/**@} end of group DMA_CNTRLD_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DMA_REVA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.c

@@ -0,0 +1,170 @@
+/**
+ * @file flc.h
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "flc.h"
+#include "stdlib.h"
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+// Length is number of 32-bit words
+int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data)
+{
+    volatile uint32_t* ptr;
+    
+    
+    for (ptr = (uint32_t*) address; ptr < (((uint32_t*)(address)) + length); ptr++, data++) {
+        if (*ptr != *data) {
+            return E_BAD_STATE;
+        }
+    }
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+// make sure to disable ICC with ICC_Disable(); before Running this function
+int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer)
+{
+    int err;
+    uint32_t bytes_written;
+
+    uint32_t current_data_32;
+    uint8_t* current_data = (uint8_t*) &current_data_32;
+    uint8_t* buffer8 = (uint8_t*)buffer;
+
+    // Align the address to a word boundary and read/write if we have to
+    if (address & 0x3) {
+    
+        // Figure out how many bytes we have to write to round up the address
+        bytes_written = 4 - (address & 0x3);
+        
+        // Save the data currently in the flash
+        memcpy(current_data, (void*)(address & (~0x3)), 4);
+        
+        // Modify current_data to insert the data from buffer
+        memcpy(&current_data[4 - bytes_written], buffer8, bytes_written);
+        
+        // Write the modified data
+        if ((err = MXC_FLC_Write32(address - (address % 4), current_data_32)) != E_NO_ERROR) {
+            return err;
+        }
+        
+        address += bytes_written;
+        length -= bytes_written;
+        buffer8 += bytes_written;
+    }
+    
+    // Align the address to a 4-word (128bit) boundary
+    while ((length >= 4) && ((address & 0xF) != 0)) {
+        memcpy(current_data, buffer8, 4);
+        if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
+            return err;
+        }
+        
+        address += 4;
+        length -= 4;
+        buffer8 += 4;
+    }
+    
+    if (length >= 16) {
+        uint32_t buff128[4];
+        while (length >= 16) {
+            memcpy(buff128, buffer8, 16);
+            if ((err = MXC_FLC_Write128(address, buff128)) != E_NO_ERROR) {
+                return err;
+            }
+            
+            address += 16;
+            length -= 16;
+            buffer8 += 16;
+        }
+        
+    }
+    
+    while (length >= 4) {
+        memcpy(current_data, buffer8, 4);
+        if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
+            return err;
+        }
+        
+        address += 4;
+        length -= 4;
+        buffer8 += 4;
+    }
+    
+    if (length > 0) {
+        // Save the data currently in the flash
+        memcpy(current_data, (void*)(address), 4);
+        
+        // Modify current_data to insert the data from buffer
+        memcpy(current_data, buffer8, length);
+        
+        if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) {
+            return err;
+        }
+    }
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+void MXC_FLC_Com_Read(int address, void* buffer, int len)
+{
+    memcpy(buffer, (void*) address, len);
+}
+

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_common.h

@@ -0,0 +1,72 @@
+/**
+ * @file       flc.h
+ * @brief      Flash Controller driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+
+/* **** Includes **** */
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup flc Flash Controller  (FLC)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+
+
+/***** Function Prototypes *****/
+
+int MXC_FLC_Com_VerifyData (uint32_t address, uint32_t length, uint32_t * data);
+
+int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer);
+
+void MXC_FLC_Com_Read (int address, void* buffer, int len);
+
+/**@} end of group flc */
+
+
+#ifdef __cplusplus
+}
+#endif

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_me15.c

@@ -0,0 +1,314 @@
+/**
+ * @file flc.h
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "flc.h"
+#include "flc_revb.h"
+#include "flc_common.h"
+#include "ecc_regs.h" // For ECCEN registers.
+#include "mcr_regs.h" // For ECCEN registers.
+
+//******************************************************************************
+void MXC_FLC_ME15_Flash_Operation(void)
+{
+    /* Flush all instruction caches */
+    MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH;
+    
+    /* Wait for flush to complete */
+    while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {
+    }
+}
+
+//******************************************************************************
+int MXC_FLC_ME15_GetByAddress(mxc_flc_regs_t** flc, uint32_t addr)
+{
+
+    if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
+        *flc =  MXC_FLC0;
+    }
+    else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
+        *flc = MXC_FLC0;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+int MXC_FLC_ME15_GetPhysicalAddress (uint32_t addr, uint32_t *result)
+{
+    if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) {
+        *result = addr - MXC_FLASH_MEM_BASE;
+    }
+    else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) {
+        /* For ME15, the info block base was located at the next power of 2 address beyond the main flash.
+           The ME15 ends at 0x5FFFF, so the info block starts at 0x80000. */
+        *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + 0x80000;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+   
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+
+int MXC_FLC_Init()
+{
+    return E_NO_ERROR;
+}
+
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_Busy(void)
+{
+    return MXC_FLC_RevB_Busy();
+}
+
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_ME15_PageErase(uint32_t address)
+{
+    int err;
+    uint32_t addr;
+    mxc_flc_regs_t* flc = NULL;
+
+    // Get FLC Instance
+    if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
+        return err;
+    }
+
+    if ((err = MXC_FLC_ME15_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
+        return err;
+    }
+
+    err = MXC_FLC_RevB_PageErase ((mxc_flc_revb_regs_t*) flc, addr);
+    // Flush the cache
+    MXC_FLC_ME15_Flash_Operation();
+    
+    return err;
+}
+
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+// make sure to disable ICC with ICC_Disable(); before Running this function
+int MXC_FLC_ME15_Write128(uint32_t address, uint32_t* data)
+{
+    int err;
+    mxc_flc_regs_t* flc = NULL;
+    uint32_t addr;
+    
+    // Address checked if it is 128-bit aligned
+    if (address & 0xF) {
+        return E_BAD_PARAM;
+    }
+    
+    // Get FLC Instance
+    if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    if ((err = MXC_FLC_ME15_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) {
+        return err;
+    }
+    
+    if((err= MXC_FLC_RevB_Write128 ((mxc_flc_revb_regs_t*) flc, addr, data)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    // Flush the cache
+    MXC_FLC_ME15_Flash_Operation();
+    
+    if ((err = MXC_FLC_Com_VerifyData(address, 4, data)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+int MXC_FLC_ME15_Write32(uint32_t address, uint32_t data)
+{
+    uint32_t addr, aligned;
+    int err;
+    mxc_flc_regs_t* flc = NULL;
+    
+    // Address checked if it is byte addressable
+    if (address & 0x3) {
+        return E_BAD_PARAM;
+    }
+    
+    // Align address to 128-bit word
+    aligned = address & 0xfffffff0;
+    
+    // Get FLC Instance
+    if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    if ((err = MXC_FLC_ME15_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) {
+        return err;
+    }
+    
+    if (MXC_ECC->en & MXC_F_ECC_EN_FLASH) {
+    
+        return E_BAD_STATE;
+    }
+    
+    return MXC_FLC_RevB_Write32 ((mxc_flc_revb_regs_t*) flc, address, data, addr);
+    
+}
+
+int MXC_FLC_ME15_MassErase(void)
+{
+    int err, i;
+    mxc_flc_regs_t* flc;
+    
+    for (i=0; i<MXC_FLC_INSTANCES; i++) {
+        flc = MXC_FLC_GET_FLC (i);
+        err = MXC_FLC_RevB_MassErase((mxc_flc_revb_regs_t*) flc);
+        
+        if (err != E_NO_ERROR) {
+            return err;
+        }
+        
+        MXC_FLC_ME15_Flash_Operation();
+    }
+    
+    return E_NO_ERROR;
+    
+    
+}
+int MXC_FLC_ME15_UnlockInfoBlock(uint32_t address)
+{
+    int err;
+    mxc_flc_regs_t* flc;
+    
+    if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    return MXC_FLC_RevB_UnlockInfoBlock ((mxc_flc_revb_regs_t*) flc, address);
+}
+int MXC_FLC_ME15_LockInfoBlock(uint32_t address)
+{
+    int err;
+    mxc_flc_regs_t* flc;
+    
+    if ((err = MXC_FLC_ME15_GetByAddress(&flc, address)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    return MXC_FLC_RevB_LockInfoBlock ((mxc_flc_revb_regs_t*) flc, address);
+}
+/* ****************************************************************************** */
+int MXC_FLC_MassErase(void)
+{
+    return MXC_FLC_ME15_MassErase();
+}
+
+int MXC_FLC_PageErase(uint32_t address)
+{
+    return MXC_FLC_ME15_PageErase(address);
+}
+
+int MXC_FLC_Write32(uint32_t address, uint32_t data)
+{
+    return MXC_FLC_ME15_Write32(address, data);
+}
+
+int MXC_FLC_Write128(uint32_t address, uint32_t* data)
+{
+    return MXC_FLC_ME15_Write128(address, data);
+}
+
+int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t* buffer)
+{
+    return MXC_FLC_Com_Write(address, length, buffer);
+}
+void MXC_FLC_Read(int address, void* buffer, int len)
+{
+    MXC_FLC_Com_Read(address, buffer, len);
+}
+
+int MXC_FLC_EnableInt(uint32_t flags)
+{
+    return MXC_FLC_RevB_EnableInt(flags);
+}
+
+int MXC_FLC_DisableInt(uint32_t flags)
+{
+    return MXC_FLC_RevB_DisableInt(flags);
+}
+
+int MXC_FLC_GetFlags(void)
+{
+    return MXC_FLC_RevB_GetFlags();
+}
+
+int MXC_FLC_ClearFlags(uint32_t flags)
+{
+    return MXC_FLC_RevB_ClearFlags(flags);
+}
+
+int MXC_FLC_UnlockInfoBlock(uint32_t address)
+{
+    return MXC_FLC_ME15_UnlockInfoBlock(address);
+}
+
+int MXC_FLC_LockInfoBlock(uint32_t address)
+{
+    return MXC_FLC_ME15_LockInfoBlock(address);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.c

@@ -0,0 +1,395 @@
+/**
+ * @file flc.h
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "flc_reva.h"
+#include "flc.h"
+
+/**
+ * @ingroup flc
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+#ifdef MXC_FLC0
+static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t*) MXC_FLC0;
+#else
+static mxc_flc_reva_regs_t *flc_int = (mxc_flc_reva_regs_t*) MXC_FLC;
+#endif
+
+/* **** Functions **** */
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+static int MXC_busy_flc(mxc_flc_reva_regs_t* flc)
+{
+    return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE));
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc)
+{
+    /* Check if the flash controller is busy */
+    if (MXC_busy_flc(flc)) {
+        return E_BUSY;
+    }
+    
+    // Set flash clock divider to generate a 1MHz clock from the APB clock
+    flc->clkdiv = SystemCoreClock / 1000000;
+    
+    /* Clear stale errors */
+    if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
+        flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
+    }
+    
+    /* Unlock flash */
+    flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED;
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_RevA_Busy(void)
+{
+    uint32_t flc_cn = 0;
+    int i;
+    mxc_flc_reva_regs_t *flc;
+    
+    for (i = 0; i < MXC_FLC_INSTANCES; i++) {
+        flc = (mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC (i);
+        flc_cn = MXC_busy_flc (flc);
+        
+        if (flc_cn != 0) {
+            break;
+        }
+    }
+    
+    return flc_cn;
+}
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc)
+{
+    int err;
+    
+    if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    /* Write mass erase code */
+    flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL;
+    
+    /* Issue mass erase command */
+    flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME;
+    
+    /* Wait until flash operation is complete */
+    while (MXC_busy_flc(flc));
+    
+    /* Lock flash */
+    flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
+    
+    /* Check access violations */
+    if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
+        flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
+        return E_BAD_STATE;
+    }
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr)
+{
+    int err;
+
+    if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
+        return err;
+    }
+
+    /* Write page erase code */
+    flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE;
+    /* Issue page erase command */
+    flc->addr = addr;
+    flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE;
+    
+    /* Wait until flash operation is complete */
+    while (MXC_FLC_Busy());
+    
+    /* Lock flash */
+    flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
+    
+    /* Check access violations */
+    if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
+        flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
+        return E_BAD_STATE;
+    }
+    
+    return E_NO_ERROR;
+}
+
+
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+// make sure to disable ICC with ICC_Disable(); before Running this function
+int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
+{
+    int err, i = 0;
+    uint32_t byte;
+    volatile uint32_t* ptr;
+    uint32_t current_data[4] = {0, 0, 0, 0};
+    
+    // Address checked if it is byte addressable
+    if (logicAddr & 0x3) {
+        return E_BAD_PARAM;
+    }
+    
+    // Check if the location trying to be written has 1's in to be written to 0's
+    if ((* (uint32_t*) logicAddr & data) != data) {
+        return E_BAD_STATE;
+    }
+    
+    // Get byte idx within 128-bit word
+    byte = (logicAddr & 0xf);
+    // Align address to 128-bit word
+    logicAddr = logicAddr & 0xfffffff0;
+    
+    if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    // Get current data stored in flash
+    for (ptr = (uint32_t*) logicAddr; ptr < (uint32_t*)(logicAddr + 16); ptr++, i++) {
+        current_data[i] = *ptr;
+    }
+    
+    // write the data
+    flc->addr = physicalAddr;
+    
+    if (byte < 4) {
+        current_data[0] = data;
+    }
+    else if (byte < 8) {
+        current_data[1] = data;
+    }
+    else if (byte < 12) {
+        current_data[2] = data;
+    }
+    else {
+        current_data[3] = data;
+    }
+    
+    return MXC_FLC_Write128(logicAddr, current_data);
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+// make sure to disable ICC with ICC_Disable(); before Running this function
+int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data)
+{
+    int err;
+    
+    // Address checked if it is 128-bit aligned
+    if (addr & 0xF) {
+        return E_BAD_PARAM;
+    }
+    
+    if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    // write 128-bits
+    flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_WDTH;
+    
+    // write the data
+    flc->addr = addr;
+    flc->data[0] = data[0];
+    flc->data[1] = data[1];
+    flc->data[2] = data[2];
+    flc->data[3] = data[3];
+    flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR;
+
+    /* Wait until flash operation is complete */
+    while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND)!=0){}
+    while (MXC_busy_flc (flc)){}
+    
+    /* Lock flash */
+    flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK;
+    
+    /* Check access violations */
+    if (flc->intr & MXC_F_FLC_REVA_INTR_AF) {
+        flc->intr &= ~MXC_F_FLC_REVA_INTR_AF;
+        return E_BAD_STATE;
+    }
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+void MXC_FLC_RevA_SetFLCInt(mxc_flc_reva_regs_t *flc)
+{
+    flc_int = flc;
+}
+
+//******************************************************************************
+mxc_flc_reva_regs_t* MXC_FLC_RevA_GetFLCInt(void)
+{
+    return flc_int;
+}
+
+//******************************************************************************
+int MXC_FLC_RevA_EnableInt(uint32_t mask)
+{
+    mask &= (MXC_F_FLC_REVA_INTR_DONEIE |  MXC_F_FLC_REVA_INTR_AFIE);
+    
+    if (!mask) {
+        /* No bits set? Wasn't something we can enable. */
+        return E_BAD_PARAM;
+    }
+    
+    /* Apply enables and write back, preserving the flags */
+    flc_int->intr |= mask;
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+int MXC_FLC_RevA_DisableInt(uint32_t mask)
+{
+    mask &= (MXC_F_FLC_REVA_INTR_DONEIE |  MXC_F_FLC_REVA_INTR_AFIE);
+    
+    if (!mask) {
+        /* No bits set? Wasn't something we can disable. */
+        return E_BAD_PARAM;
+    }
+    
+    /* Apply disables and write back, preserving the flags */
+    flc_int->intr &= ~mask;
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+int MXC_FLC_RevA_GetFlags(void)
+{
+    return (flc_int->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF));
+}
+
+//******************************************************************************
+int MXC_FLC_RevA_ClearFlags(uint32_t mask)
+{
+    mask &= (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF);
+    
+    if (!mask) {
+        /* No bits set? Wasn't something we can clear. */
+        return E_BAD_PARAM;
+    }
+    
+    /* Both flags are write zero clear */
+    flc_int->intr ^= mask;
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
+{
+    if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
+        return E_BAD_PARAM;
+    }
+
+    /* Make sure the info block is locked */
+    flc->actrl = 0x1234;
+    
+    /* Write the unlock sequence */
+    flc->actrl = 0x3a7f5ca3;
+    flc->actrl = 0xa1e34f20;
+    flc->actrl = 0x9608b2c1;
+    
+    return E_NO_ERROR;
+}
+
+//******************************************************************************
+int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address)
+{
+    if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
+        return E_BAD_PARAM;
+    }
+    
+    flc->actrl = 0xDEADBEEF;
+    return E_NO_ERROR;
+}
+/**@} end of group flc */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva.h

@@ -0,0 +1,89 @@
+/**
+ * @file flc.h
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "flc.h"
+#include "flc_reva_regs.h"
+
+/**
+ * @ingroup flc
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+int MXC_FLC_RevA_Busy (void);
+
+int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc);
+
+int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc,uint32_t addr);
+
+int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
+
+int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data);
+
+void MXC_FLC_RevA_SetFLCInt (mxc_flc_reva_regs_t *flc);
+
+mxc_flc_reva_regs_t* MXC_FLC_RevA_GetFLCInt (void);
+
+int MXC_FLC_RevA_EnableInt (uint32_t mask);
+
+int MXC_FLC_RevA_DisableInt (uint32_t mask);
+
+int MXC_FLC_RevA_GetFlags (void);
+
+int MXC_FLC_RevA_ClearFlags (uint32_t mask);
+
+int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address);
+
+int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address);
+/**@} end of group flc */
+
+
+#ifdef __cplusplus
+}
+#endif

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h

@@ -0,0 +1,246 @@
+/**
+ * @file    flc_reva_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_REVA_REGS_H_
+#define _FLC_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     flc_reva
+ * @defgroup    flc_reva_registers FLC_REVA_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module.
+ * @details Flash Memory Control.
+ */
+
+/**
+ * @ingroup flc_reva_registers
+ * Structure type to access the FLC_REVA Registers.
+ */
+typedef struct {
+    __IO uint32_t addr;                 /**< <tt>\b 0x00:</tt> FLC_REVA ADDR Register */
+    __IO uint32_t clkdiv;               /**< <tt>\b 0x04:</tt> FLC_REVA CLKDIV Register */
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x08:</tt> FLC_REVA CTRL Register */
+    __R  uint32_t rsv_0xc_0x23[6];
+    __IO uint32_t intr;                 /**< <tt>\b 0x024:</tt> FLC_REVA INTR Register */
+    __IO uint32_t eccdata;              /**< <tt>\b 0x028:</tt> FLC_REVA ECCDATA Register */
+    __R  uint32_t rsv_0x2c;
+    __IO uint32_t data[4];              /**< <tt>\b 0x30:</tt> FLC_REVA DATA Register */
+    __O  uint32_t actrl;                /**< <tt>\b 0x40:</tt> FLC_REVA ACTRL Register */
+} mxc_flc_reva_regs_t;
+
+/* Register offsets for module FLC_REVA */
+/**
+ * @ingroup    flc_reva_registers
+ * @defgroup   FLC_REVA_Register_Offsets Register Offsets
+ * @brief      FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_FLC_REVA_ADDR                ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_FLC_REVA_CLKDIV              ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_FLC_REVA_CTRL                ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_FLC_REVA_INTR                ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_FLC_REVA_ECCDATA             ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_FLC_REVA_DATA                ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_FLC_REVA_ACTRL               ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: <tt> 0x0040</tt> */ 
+/**@} end of group flc_reva_registers */
+
+/**
+ * @ingroup  flc_reva_registers
+ * @defgroup FLC_REVA_ADDR FLC_REVA_ADDR
+ * @brief    Flash Write Address.
+ * @{
+ */
+ #define MXC_F_FLC_REVA_ADDR_ADDR_POS                   0 /**< ADDR_ADDR Position */
+ #define MXC_F_FLC_REVA_ADDR_ADDR                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+
+/**@} end of group FLC_REVA_ADDR_Register */
+
+/**
+ * @ingroup  flc_reva_registers
+ * @defgroup FLC_REVA_CLKDIV FLC_REVA_CLKDIV
+ * @brief    Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
+ *           MHz clock for Flash controller.
+ * @{
+ */
+ #define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS               0 /**< CLKDIV_CLKDIV Position */
+ #define MXC_F_FLC_REVA_CLKDIV_CLKDIV                   ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group FLC_REVA_CLKDIV_Register */
+
+/**
+ * @ingroup  flc_reva_registers
+ * @defgroup FLC_REVA_CTRL FLC_REVA_CTRL
+ * @brief    Flash Control Register.
+ * @{
+ */
+ #define MXC_F_FLC_REVA_CTRL_WR_POS                     0 /**< CTRL_WR Position */
+ #define MXC_F_FLC_REVA_CTRL_WR                         ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */
+
+ #define MXC_F_FLC_REVA_CTRL_ME_POS                     1 /**< CTRL_ME Position */
+ #define MXC_F_FLC_REVA_CTRL_ME                         ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */
+
+ #define MXC_F_FLC_REVA_CTRL_PGE_POS                    2 /**< CTRL_PGE Position */
+ #define MXC_F_FLC_REVA_CTRL_PGE                        ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
+
+ #define MXC_F_FLC_REVA_CTRL_WDTH_POS                   4 /**< CTRL_WDTH Position */
+ #define MXC_F_FLC_REVA_CTRL_WDTH                       ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
+
+ #define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS             8 /**< CTRL_ERASE_CODE Position */
+ #define MXC_F_FLC_REVA_CTRL_ERASE_CODE                 ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
+ #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP             ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
+ #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP             (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
+ #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE       ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
+ #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE       (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
+ #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL        ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
+ #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL        (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
+
+ #define MXC_F_FLC_REVA_CTRL_PEND_POS                   24 /**< CTRL_PEND Position */
+ #define MXC_F_FLC_REVA_CTRL_PEND                       ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
+
+ #define MXC_F_FLC_REVA_CTRL_LVE_POS                    25 /**< CTRL_LVE Position */
+ #define MXC_F_FLC_REVA_CTRL_LVE                        ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
+
+ #define MXC_F_FLC_REVA_CTRL_UNLOCK_POS                 28 /**< CTRL_UNLOCK Position */
+ #define MXC_F_FLC_REVA_CTRL_UNLOCK                     ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
+ #define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED            ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
+ #define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED            (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
+ #define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED              ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
+ #define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED              (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
+
+/**@} end of group FLC_REVA_CTRL_Register */
+
+/**
+ * @ingroup  flc_reva_registers
+ * @defgroup FLC_REVA_INTR FLC_REVA_INTR
+ * @brief    Flash Interrupt Register.
+ * @{
+ */
+ #define MXC_F_FLC_REVA_INTR_DONE_POS                   0 /**< INTR_DONE Position */
+ #define MXC_F_FLC_REVA_INTR_DONE                       ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */
+
+ #define MXC_F_FLC_REVA_INTR_AF_POS                     1 /**< INTR_AF Position */
+ #define MXC_F_FLC_REVA_INTR_AF                         ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */
+
+ #define MXC_F_FLC_REVA_INTR_DONEIE_POS                 8 /**< INTR_DONEIE Position */
+ #define MXC_F_FLC_REVA_INTR_DONEIE                     ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
+
+ #define MXC_F_FLC_REVA_INTR_AFIE_POS                   9 /**< INTR_AFIE Position */
+ #define MXC_F_FLC_REVA_INTR_AFIE                       ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
+
+/**@} end of group FLC_REVA_INTR_Register */
+
+/**
+ * @ingroup  flc_reva_registers
+ * @defgroup FLC_REVA_ECCDATA FLC_REVA_ECCDATA
+ * @brief    ECC Data Register.
+ * @{
+ */
+ #define MXC_F_FLC_REVA_ECCDATA_EVEN_POS                0 /**< ECCDATA_EVEN Position */
+ #define MXC_F_FLC_REVA_ECCDATA_EVEN                    ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
+
+ #define MXC_F_FLC_REVA_ECCDATA_ODD_POS                 16 /**< ECCDATA_ODD Position */
+ #define MXC_F_FLC_REVA_ECCDATA_ODD                     ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
+
+/**@} end of group FLC_REVA_ECCDATA_Register */
+
+/**
+ * @ingroup  flc_reva_registers
+ * @defgroup FLC_REVA_DATA FLC_REVA_DATA
+ * @brief    Flash Write Data.
+ * @{
+ */
+ #define MXC_F_FLC_REVA_DATA_DATA_POS                   0 /**< DATA_DATA Position */
+ #define MXC_F_FLC_REVA_DATA_DATA                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group FLC_REVA_DATA_Register */
+
+/**
+ * @ingroup  flc_reva_registers
+ * @defgroup FLC_REVA_ACTRL FLC_REVA_ACTRL
+ * @brief    Access Control Register. Writing the ACTRL register with the following values in
+ *           the order shown, allows read and write access to the system and user Information
+ *           block:                 pflc-actrl = 0x3a7f5ca3;                 pflc-actrl =
+ *           0xa1e34f20;                 pflc-actrl = 0x9608b2c1. When unlocked, a write of
+ *           any word will disable access to system and user information block. Readback of
+ *           this register is always zero.
+ * @{
+ */
+ #define MXC_F_FLC_REVA_ACTRL_ACTRL_POS                 0 /**< ACTRL_ACTRL Position */
+ #define MXC_F_FLC_REVA_ACTRL_ACTRL                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
+
+/**@} end of group FLC_REVA_ACTRL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_REVA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.c

@@ -0,0 +1,154 @@
+/**
+ * @file flc.h
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "flc.h"
+#include "flc_revb.h"   
+#include "flc_reva.h"
+
+/**
+ * @ingroup flc
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_RevB_Busy(void)
+{
+    return MXC_FLC_RevA_Busy();
+}
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_RevB_MassErase(mxc_flc_revb_regs_t* flc)
+{
+    return MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*)flc);
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+int MXC_FLC_RevB_PageErase(mxc_flc_revb_regs_t* flc, uint32_t addr)
+{    
+    return MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*)flc,addr);
+}
+
+
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+// make sure to disable ICC with ICC_Disable(); before Running this function
+int MXC_FLC_RevB_Write32(mxc_flc_revb_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr)
+{
+    return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*)flc, logicAddr, data, physicalAddr);
+}
+
+//******************************************************************************
+#if IAR_PRAGMAS
+#pragma section=".flashprog"
+#else
+__attribute__((section(".flashprog")))
+#endif
+// make sure to disable ICC with ICC_Disable(); before Running this function
+int MXC_FLC_RevB_Write128(mxc_flc_revb_regs_t* flc, uint32_t addr, uint32_t* data)
+{
+    return MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*)flc, addr, data);
+}
+
+//******************************************************************************
+int MXC_FLC_RevB_EnableInt(uint32_t mask)
+{
+    return MXC_FLC_RevA_EnableInt(mask);
+}
+
+//******************************************************************************
+int MXC_FLC_RevB_DisableInt(uint32_t mask)
+{    
+    return MXC_FLC_RevA_DisableInt(mask);
+}
+
+//******************************************************************************
+int MXC_FLC_RevB_GetFlags(void)
+{
+    return MXC_FLC_RevA_GetFlags();
+}
+
+//******************************************************************************
+int MXC_FLC_RevB_ClearFlags(uint32_t mask)
+{
+    return MXC_FLC_RevA_ClearFlags(mask);
+}
+
+//******************************************************************************
+int MXC_FLC_RevB_UnlockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address)
+{
+    return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*)flc, address);
+}
+
+//******************************************************************************
+int MXC_FLC_RevB_LockInfoBlock(mxc_flc_revb_regs_t* flc, uint32_t address)
+{
+    return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*)flc, address);
+}
+/**@} end of group flc */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb.h

@@ -0,0 +1,85 @@
+/**
+ * @file flc.h
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "flc_revb_regs.h"
+#include "mcr_regs.h" // For ECCEN registers.
+
+/**
+ * @ingroup flc
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+int MXC_FLC_RevB_Busy (void);
+
+int MXC_FLC_RevB_MassErase (mxc_flc_revb_regs_t *flc);
+
+int MXC_FLC_RevB_PageErase (mxc_flc_revb_regs_t *flc,uint32_t addr);
+
+int MXC_FLC_RevB_Write32 (mxc_flc_revb_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr);
+
+int MXC_FLC_RevB_Write128 (mxc_flc_revb_regs_t *flc, uint32_t addr, uint32_t *data);
+
+int MXC_FLC_RevB_EnableInt (uint32_t mask);
+
+int MXC_FLC_RevB_DisableInt (uint32_t mask);
+
+int MXC_FLC_RevB_GetFlags (void);
+
+int MXC_FLC_RevB_ClearFlags (uint32_t mask);
+
+int MXC_FLC_RevB_UnlockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address);
+
+int MXC_FLC_RevB_LockInfoBlock (mxc_flc_revb_regs_t *flc, uint32_t address);
+/**@} end of group flc */
+
+
+#ifdef __cplusplus
+}
+#endif

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/FLC/flc_revb_regs.h

@@ -0,0 +1,301 @@
+/**
+ * @file    flc_revb_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_REVB_REGS_H_
+#define _FLC_REVB_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     flc_revb
+ * @defgroup    flc_revb_registers FLC_REVB_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the FLC_REVB Peripheral Module.
+ * @details Flash Memory Control.
+ */
+
+/**
+ * @ingroup flc_revb_registers
+ * Structure type to access the FLC_REVB Registers.
+ */
+typedef struct {
+    __IO uint32_t addr;                 /**< <tt>\b 0x00:</tt> FLC_REVB ADDR Register */
+    __IO uint32_t clkdiv;               /**< <tt>\b 0x04:</tt> FLC_REVB CLKDIV Register */
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x08:</tt> FLC_REVB CTRL Register */
+    __R  uint32_t rsv_0xc_0x23[6];
+    __IO uint32_t intr;                 /**< <tt>\b 0x024:</tt> FLC_REVB INTR Register */
+    __IO uint32_t eccdata;              /**< <tt>\b 0x028:</tt> FLC_REVB ECCDATA Register */
+    __R  uint32_t rsv_0x2c;
+    __IO uint32_t data[4];              /**< <tt>\b 0x30:</tt> FLC_REVB DATA Register */
+    __O  uint32_t actrl;                /**< <tt>\b 0x40:</tt> FLC_REVB ACTRL Register */
+    __R  uint32_t rsv_0x44_0x7f[15];
+    __IO uint32_t welr0;                /**< <tt>\b 0x80:</tt> FLC_REVB WELR0 Register */
+    __R  uint32_t rsv_0x84;
+    __IO uint32_t welr1;                /**< <tt>\b 0x88:</tt> FLC_REVB WELR1 Register */
+    __R  uint32_t rsv_0x8c;
+    __IO uint32_t rlr0;                 /**< <tt>\b 0x90:</tt> FLC_REVB RLR0 Register */
+    __R  uint32_t rsv_0x94;
+    __IO uint32_t rlr1;                 /**< <tt>\b 0x98:</tt> FLC_REVB RLR1 Register */
+} mxc_flc_revb_regs_t;
+
+/* Register offsets for module FLC_REVB */
+/**
+ * @ingroup    flc_revb_registers
+ * @defgroup   FLC_REVB_Register_Offsets Register Offsets
+ * @brief      FLC_REVB Peripheral Register Offsets from the FLC_REVB Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_FLC_REVB_ADDR                ((uint32_t)0x00000000UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_FLC_REVB_CLKDIV              ((uint32_t)0x00000004UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_FLC_REVB_CTRL                ((uint32_t)0x00000008UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_FLC_REVB_INTR                ((uint32_t)0x00000024UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_FLC_REVB_ECCDATA             ((uint32_t)0x00000028UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_FLC_REVB_DATA                ((uint32_t)0x00000030UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_FLC_REVB_ACTRL               ((uint32_t)0x00000040UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_FLC_REVB_WELR0               ((uint32_t)0x00000080UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0080</tt> */ 
+ #define MXC_R_FLC_REVB_WELR1               ((uint32_t)0x00000088UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0088</tt> */ 
+ #define MXC_R_FLC_REVB_RLR0                ((uint32_t)0x00000090UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0090</tt> */ 
+ #define MXC_R_FLC_REVB_RLR1                ((uint32_t)0x00000098UL) /**< Offset from FLC_REVB Base Address: <tt> 0x0098</tt> */ 
+/**@} end of group flc_revb_registers */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_ADDR FLC_REVB_ADDR
+ * @brief    Flash Write Address.
+ * @{
+ */
+ #define MXC_F_FLC_REVB_ADDR_ADDR_POS                   0 /**< ADDR_ADDR Position */
+ #define MXC_F_FLC_REVB_ADDR_ADDR                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+
+/**@} end of group FLC_REVB_ADDR_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_CLKDIV FLC_REVB_CLKDIV
+ * @brief    Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
+ *           MHz clock for Flash controller.
+ * @{
+ */
+ #define MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS               0 /**< CLKDIV_CLKDIV Position */
+ #define MXC_F_FLC_REVB_CLKDIV_CLKDIV                   ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group FLC_REVB_CLKDIV_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_CTRL FLC_REVB_CTRL
+ * @brief    Flash Control Register.
+ * @{
+ */
+ #define MXC_F_FLC_REVB_CTRL_WR_POS                     0 /**< CTRL_WR Position */
+ #define MXC_F_FLC_REVB_CTRL_WR                         ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WR_POS)) /**< CTRL_WR Mask */
+
+ #define MXC_F_FLC_REVB_CTRL_ME_POS                     1 /**< CTRL_ME Position */
+ #define MXC_F_FLC_REVB_CTRL_ME                         ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_ME_POS)) /**< CTRL_ME Mask */
+
+ #define MXC_F_FLC_REVB_CTRL_PGE_POS                    2 /**< CTRL_PGE Position */
+ #define MXC_F_FLC_REVB_CTRL_PGE                        ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PGE_POS)) /**< CTRL_PGE Mask */
+
+ #define MXC_F_FLC_REVB_CTRL_WDTH_POS                   4 /**< CTRL_WDTH Position */
+ #define MXC_F_FLC_REVB_CTRL_WDTH                       ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */
+
+ #define MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS             8 /**< CTRL_ERASE_CODE Position */
+ #define MXC_F_FLC_REVB_CTRL_ERASE_CODE                 ((uint32_t)(0xFFUL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
+ #define MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP             ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
+ #define MXC_S_FLC_REVB_CTRL_ERASE_CODE_NOP             (MXC_V_FLC_REVB_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
+ #define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE       ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
+ #define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE       (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
+ #define MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL        ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
+ #define MXC_S_FLC_REVB_CTRL_ERASE_CODE_ERASEALL        (MXC_V_FLC_REVB_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVB_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
+
+ #define MXC_F_FLC_REVB_CTRL_PEND_POS                   24 /**< CTRL_PEND Position */
+ #define MXC_F_FLC_REVB_CTRL_PEND                       ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_PEND_POS)) /**< CTRL_PEND Mask */
+
+ #define MXC_F_FLC_REVB_CTRL_LVE_POS                    25 /**< CTRL_LVE Position */
+ #define MXC_F_FLC_REVB_CTRL_LVE                        ((uint32_t)(0x1UL << MXC_F_FLC_REVB_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
+
+ #define MXC_F_FLC_REVB_CTRL_UNLOCK_POS                 28 /**< CTRL_UNLOCK Position */
+ #define MXC_F_FLC_REVB_CTRL_UNLOCK                     ((uint32_t)(0xFUL << MXC_F_FLC_REVB_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */
+ #define MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED            ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */
+ #define MXC_S_FLC_REVB_CTRL_UNLOCK_UNLOCKED            (MXC_V_FLC_REVB_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */
+ #define MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED              ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */
+ #define MXC_S_FLC_REVB_CTRL_UNLOCK_LOCKED              (MXC_V_FLC_REVB_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVB_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */
+
+/**@} end of group FLC_REVB_CTRL_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_INTR FLC_REVB_INTR
+ * @brief    Flash Interrupt Register.
+ * @{
+ */
+ #define MXC_F_FLC_REVB_INTR_DONE_POS                   0 /**< INTR_DONE Position */
+ #define MXC_F_FLC_REVB_INTR_DONE                       ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONE_POS)) /**< INTR_DONE Mask */
+
+ #define MXC_F_FLC_REVB_INTR_AF_POS                     1 /**< INTR_AF Position */
+ #define MXC_F_FLC_REVB_INTR_AF                         ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AF_POS)) /**< INTR_AF Mask */
+
+ #define MXC_F_FLC_REVB_INTR_DONEIE_POS                 8 /**< INTR_DONEIE Position */
+ #define MXC_F_FLC_REVB_INTR_DONEIE                     ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
+
+ #define MXC_F_FLC_REVB_INTR_AFIE_POS                   9 /**< INTR_AFIE Position */
+ #define MXC_F_FLC_REVB_INTR_AFIE                       ((uint32_t)(0x1UL << MXC_F_FLC_REVB_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
+
+/**@} end of group FLC_REVB_INTR_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_ECCDATA FLC_REVB_ECCDATA
+ * @brief    ECC Data Register.
+ * @{
+ */
+ #define MXC_F_FLC_REVB_ECCDATA_EVEN_POS                0 /**< ECCDATA_EVEN Position */
+ #define MXC_F_FLC_REVB_ECCDATA_EVEN                    ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */
+
+ #define MXC_F_FLC_REVB_ECCDATA_ODD_POS                 16 /**< ECCDATA_ODD Position */
+ #define MXC_F_FLC_REVB_ECCDATA_ODD                     ((uint32_t)(0x1FFUL << MXC_F_FLC_REVB_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */
+
+/**@} end of group FLC_REVB_ECCDATA_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_DATA FLC_REVB_DATA
+ * @brief    Flash Write Data.
+ * @{
+ */
+ #define MXC_F_FLC_REVB_DATA_DATA_POS                   0 /**< DATA_DATA Position */
+ #define MXC_F_FLC_REVB_DATA_DATA                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group FLC_REVB_DATA_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_ACTRL FLC_REVB_ACTRL
+ * @brief    Access Control Register. Writing the ACTRL register with the following values in
+ *           the order shown, allows read and write access to the system and user Information
+ *           block:     pflc-actrl = 0x3a7f5ca3;     pflc-actrl = 0xa1e34f20;     pflc-actrl
+ *           = 0x9608b2c1. When unlocked, a write of any word will disable access to system
+ *           and user information block. Readback of this register is always zero.
+ * @{
+ */
+ #define MXC_F_FLC_REVB_ACTRL_ACTRL_POS                 0 /**< ACTRL_ACTRL Position */
+ #define MXC_F_FLC_REVB_ACTRL_ACTRL                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
+
+/**@} end of group FLC_REVB_ACTRL_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_WELR0 FLC_REVB_WELR0
+ * @brief    WELR0
+ * @{
+ */
+ #define MXC_F_FLC_REVB_WELR0_WELR0_POS                 0 /**< WELR0_WELR0 Position */
+ #define MXC_F_FLC_REVB_WELR0_WELR0                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */
+
+/**@} end of group FLC_REVB_WELR0_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_WELR1 FLC_REVB_WELR1
+ * @brief    WELR1
+ * @{
+ */
+ #define MXC_F_FLC_REVB_WELR1_WELR1_POS                 0 /**< WELR1_WELR1 Position */
+ #define MXC_F_FLC_REVB_WELR1_WELR1                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */
+
+/**@} end of group FLC_REVB_WELR1_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_RLR0 FLC_REVB_RLR0
+ * @brief    RLR0
+ * @{
+ */
+ #define MXC_F_FLC_REVB_RLR0_RLR0_POS                   0 /**< RLR0_RLR0 Position */
+ #define MXC_F_FLC_REVB_RLR0_RLR0                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */
+
+/**@} end of group FLC_REVB_RLR0_Register */
+
+/**
+ * @ingroup  flc_revb_registers
+ * @defgroup FLC_REVB_RLR1 FLC_REVB_RLR1
+ * @brief    RLR1
+ * @{
+ */
+ #define MXC_F_FLC_REVB_RLR1_RLR1_POS                   0 /**< RLR1_RLR1 Position */
+ #define MXC_F_FLC_REVB_RLR1_RLR1                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVB_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */
+
+/**@} end of group FLC_REVB_RLR1_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_REVB_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c

@@ -0,0 +1,107 @@
+/* *****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "gpio.h"
+#include <stddef.h>
+
+/* **** Globals **** */
+static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void*);
+static void* cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT];
+static uint8_t initialized = 0;
+
+/* **** Functions **** */
+int MXC_GPIO_Common_Init(uint32_t portmask)
+{
+    if (!initialized) {
+        int i, j;
+        
+        for (i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) {
+            // Initialize call back arrays
+            for (j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) {
+                callback[i][j] = NULL;
+            }
+        }
+        
+        initialized = 1;
+    }
+    
+    return E_NO_ERROR;
+}
+
+void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata)
+{
+    uint32_t mask;
+    unsigned int pin;
+    
+    mask = cfg->mask;
+    pin = 0;
+    
+    while (mask) {
+        if (mask & 1) {
+            callback[MXC_GPIO_GET_IDX(cfg->port)][pin] = func;
+            cbparam[MXC_GPIO_GET_IDX(cfg->port)][pin] = cbdata;
+        }
+        
+        pin++;
+        mask >>= 1;
+    }
+}
+
+void MXC_GPIO_Common_Handler(unsigned int port)
+{
+    uint32_t stat;
+    unsigned int pin;
+    
+    MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES);
+    
+    mxc_gpio_regs_t* gpio = MXC_GPIO_GET_GPIO(port);
+    
+    stat = MXC_GPIO_GetFlags(gpio);
+    MXC_GPIO_ClearFlags(gpio, stat);
+    
+    pin = 0;
+    
+    while (stat) {
+        if (stat & 1) {
+            if (callback[port][pin]) {
+                callback[port][pin](cbparam[port][pin]);
+            }
+        }
+        
+        pin++;
+        stat >>= 1;
+    }
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h

@@ -0,0 +1,52 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* **** Function Prototypes **** */
+
+int MXC_GPIO_Common_Init (uint32_t portmask);
+void MXC_GPIO_Common_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata);
+void MXC_GPIO_Common_Handler (unsigned int port);
+
+/**@} end of group gpio */
+
+#ifdef __cplusplus
+}
+#endif
+

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c

@@ -0,0 +1,187 @@
+/* *****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "gpio.h"
+#include "gpio_reva.h"
+#include "gpio_common.h"
+#include <stddef.h>
+#include "mxc_sys.h"
+
+/* **** Functions **** */
+
+int MXC_GPIO_Init(uint32_t portmask)
+{
+    if (portmask & MXC_GPIO_PORT_0) {
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
+    }
+    
+    if (portmask & MXC_GPIO_PORT_1) {
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1);
+    }
+    
+    return MXC_GPIO_Common_Init(portmask);
+}
+
+int MXC_GPIO_Shutdown(uint32_t portmask)
+{
+    if (portmask & MXC_GPIO_PORT_0) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0);
+    }
+    
+    if (portmask & MXC_GPIO_PORT_1) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1);
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_GPIO_Reset(uint32_t portmask)
+{
+    if (portmask & MXC_GPIO_PORT_0) {
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0);
+    }
+    
+    if (portmask & MXC_GPIO_PORT_1) {
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO1);
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_GPIO_Config(const mxc_gpio_cfg_t* cfg)
+{
+    int error;
+    mxc_gpio_regs_t *gpio = cfg->port;
+
+    // Configure alternate function
+    error = MXC_GPIO_RevA_SetAF ((mxc_gpio_reva_regs_t*)gpio, cfg->func, cfg->mask);
+    
+    if(error != E_NO_ERROR) {
+        return error;
+    }
+
+    // Configure the pad
+    switch (cfg->pad) {
+    case MXC_GPIO_PAD_NONE:
+    	gpio->padctrl0 &= ~cfg->mask;
+        break;
+        
+    case MXC_GPIO_PAD_PULL_UP:
+    	gpio->padctrl0 |=  cfg->mask;
+        gpio->ps |=  cfg->mask;
+        break;
+        
+    case MXC_GPIO_PAD_PULL_DOWN:
+    	gpio->padctrl0 |=  cfg->mask;
+        gpio->ps &= ~cfg->mask;
+        break;
+        
+    default:
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t* port, uint32_t mask)
+{
+    return MXC_GPIO_RevA_InGet ((mxc_gpio_reva_regs_t*) port, mask);
+}
+
+void MXC_GPIO_OutSet(mxc_gpio_regs_t* port, uint32_t mask)
+{
+    MXC_GPIO_RevA_OutSet ((mxc_gpio_reva_regs_t*) port, mask);
+}
+
+void MXC_GPIO_OutClr(mxc_gpio_regs_t* port, uint32_t mask)
+{
+    MXC_GPIO_RevA_OutClr ((mxc_gpio_reva_regs_t*) port, mask);
+}
+
+uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t* port, uint32_t mask)
+{
+    return MXC_GPIO_RevA_OutGet ((mxc_gpio_reva_regs_t*) port, mask);
+}
+
+void MXC_GPIO_OutPut(mxc_gpio_regs_t* port, uint32_t mask, uint32_t val)
+{
+    MXC_GPIO_RevA_OutPut ((mxc_gpio_reva_regs_t*) port, mask, val);
+}
+
+void MXC_GPIO_OutToggle(mxc_gpio_regs_t* port, uint32_t mask)
+{
+    MXC_GPIO_RevA_OutToggle ((mxc_gpio_reva_regs_t*) port, mask);
+}
+
+int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol)
+{
+    return MXC_GPIO_RevA_IntConfig(cfg, pol);
+}
+
+void MXC_GPIO_EnableInt(mxc_gpio_regs_t* port, uint32_t mask)
+{
+    MXC_GPIO_RevA_EnableInt ((mxc_gpio_reva_regs_t*) port, mask);
+}
+
+void MXC_GPIO_DisableInt(mxc_gpio_regs_t* port, uint32_t mask)
+{
+    MXC_GPIO_RevA_DisableInt ((mxc_gpio_reva_regs_t*) port, mask);
+}
+
+void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata)
+{
+    MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata);
+}
+
+void MXC_GPIO_Handler(unsigned int port)
+{
+    MXC_GPIO_Common_Handler(port);
+}
+
+void MXC_GPIO_ClearFlags(mxc_gpio_regs_t* port, uint32_t flags)
+{
+    MXC_GPIO_RevA_ClearFlags ((mxc_gpio_reva_regs_t*) port, flags);
+}
+
+uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t* port)
+{
+    return MXC_GPIO_RevA_GetFlags ((mxc_gpio_reva_regs_t*) port);
+}
+
+int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask)
+{
+    return E_NOT_SUPPORTED;
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c

@@ -0,0 +1,204 @@
+/* *****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_errors.h"
+#include "gpio.h"
+#include "gpio_reva.h"
+#include "gpio_common.h"
+#include <stddef.h>
+
+/* **** Functions **** */
+uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask)
+{
+    return (port->in & mask);
+}
+
+void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask)
+{
+    port->out_set = mask;
+}
+
+void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask)
+{
+    port->out_clr = mask;
+}
+
+uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask)
+{
+    return (port->out & mask);
+}
+
+void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val)
+{
+    port->out = (port->out & ~mask) | (val & mask);
+}
+
+void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask)
+{
+    port->out ^= mask;
+}
+
+int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol)
+{
+    mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t*) cfg->port;
+    
+    switch (pol) {
+    case MXC_GPIO_INT_HIGH:
+        gpio->intpol   &= ~cfg->mask;
+        gpio->dualedge &= ~cfg->mask;
+        gpio->intmode  &= ~cfg->mask;
+        break;
+        
+    case MXC_GPIO_INT_FALLING:  /* MXC_GPIO_INT_HIGH */
+    	gpio->intpol   &= ~cfg->mask;
+    	gpio->dualedge &= ~cfg->mask;
+    	gpio->intmode  |= cfg->mask;
+        break;
+        
+    case MXC_GPIO_INT_LOW:   /* MXC_GPIO_INT_LOW */
+    	gpio->intpol   |= cfg->mask;
+    	gpio->dualedge &= ~cfg->mask;
+    	gpio->intmode  &= ~cfg->mask;
+        break;
+        
+    case MXC_GPIO_INT_RISING:   /* MXC_GPIO_INT_LOW */
+        gpio->intpol   |= cfg->mask;
+        gpio->dualedge &= ~cfg->mask;
+        gpio->intmode  |= cfg->mask;
+        break;
+        
+    case MXC_GPIO_INT_BOTH:
+    	gpio->dualedge |= cfg->mask;
+    	gpio->intmode  |= cfg->mask;
+        break;
+        
+    default:
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask)
+{
+    port->inten_set = mask;
+}
+
+void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask)
+{
+    port->inten_clr = mask;
+}
+
+void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags)
+{
+	port->intfl_clr = flags;
+}
+
+uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port)
+{
+    return port->intfl;
+}
+
+int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask)
+{
+    // Configure the vssel
+    switch (vssel) {
+    case MXC_GPIO_VSSEL_VDDIO:
+        port->vssel &= ~mask;
+        break;
+        
+    case MXC_GPIO_VSSEL_VDDIOH:
+        port->vssel |= mask;
+        break;
+        
+    default:
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask)
+{
+	//This is required for new devices going forward.
+	port->inen |=  mask;
+	
+    switch (func) {
+    case MXC_GPIO_FUNC_IN:
+        port->outen_clr  = mask;
+        port->en0_set    = mask;
+        port->en1_clr    = mask;
+        port->en2_clr    = mask;
+        break;
+        
+    case MXC_GPIO_FUNC_OUT:
+        port->outen_set  = mask;
+        port->en0_set    = mask;
+        port->en1_clr    = mask;
+        port->en2_clr    = mask;
+        break;
+        
+    case MXC_GPIO_FUNC_ALT1:
+        port->en2_clr    = mask;
+        port->en1_clr    = mask;
+        port->en0_clr    = mask;
+        break;
+        
+    case MXC_GPIO_FUNC_ALT2:
+        port->en2_clr    = mask;
+        port->en1_set    = mask;
+        port->en0_clr    = mask;
+        break;
+
+  #if TARGET_NUM != 32650
+    case MXC_GPIO_FUNC_ALT3:
+        port->en2_set    = mask;
+        port->en1_clr    = mask;
+        port->en0_clr    = mask;
+        break;
+        
+    case MXC_GPIO_FUNC_ALT4:
+        port->en2_set    = mask;
+        port->en1_set    = mask;
+        port->en0_clr    = mask;
+        break;
+  #endif
+    default:
+        return E_BAD_PARAM;
+    }
+
+    return E_NO_ERROR;    
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h

@@ -0,0 +1,71 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "gpio_reva_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * @brief   Enumeration type for the pullup strength on a given pin.
+ */
+typedef enum {
+    MXC_GPIO_PS_NONE,           /**< No pull-up or pull-down strength required*/
+    MXC_GPIO_PS_PULL_SELECT,    /**< Selct pull-up or pull-down strength*/         
+} mxc_gpio_ps_t;
+
+/* **** Function Prototypes **** */
+
+uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask);
+void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask);
+void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask);
+uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask);
+void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val);
+void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask);
+int MXC_GPIO_RevA_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol);
+void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask);
+void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask);
+void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags);
+uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port);
+int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask);
+int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask);
+
+/**@} end of group gpio */
+
+#ifdef __cplusplus
+}
+#endif

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h

@@ -0,0 +1,690 @@
+/**
+ * @file    gpio_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _GPIO_REVA_REGS_H_
+#define _GPIO_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gpio
+ * @defgroup    gpio_registers GPIO_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ * @details Individual I/O for each GPIO
+ */
+
+/**
+ * @ingroup gpio_registers
+ * Structure type to access the GPIO Registers.
+ */
+typedef struct {
+    __IO uint32_t en0;                  /**< <tt>\b 0x00:</tt> GPIO EN0 Register */
+    __IO uint32_t en0_set;              /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */
+    __IO uint32_t en0_clr;              /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */
+    __IO uint32_t outen;                /**< <tt>\b 0x0C:</tt> GPIO OUTEN Register */
+    __IO uint32_t outen_set;            /**< <tt>\b 0x10:</tt> GPIO OUTEN_SET Register */
+    __IO uint32_t outen_clr;            /**< <tt>\b 0x14:</tt> GPIO OUTEN_CLR Register */
+    __IO uint32_t out;                  /**< <tt>\b 0x18:</tt> GPIO OUT Register */
+    __O  uint32_t out_set;              /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
+    __O  uint32_t out_clr;              /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
+    __I  uint32_t in;                   /**< <tt>\b 0x24:</tt> GPIO IN Register */
+    __IO uint32_t intmode;              /**< <tt>\b 0x28:</tt> GPIO INTMODE Register */
+    __IO uint32_t intpol;               /**< <tt>\b 0x2C:</tt> GPIO INTPOL Register */
+    __IO uint32_t inen;                 /**< <tt>\b 0x30:</tt> GPIO INEN Register */
+    __IO uint32_t inten;                /**< <tt>\b 0x34:</tt> GPIO INTEN Register */
+    __IO uint32_t inten_set;            /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */
+    __IO uint32_t inten_clr;            /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */
+    __I  uint32_t intfl;                /**< <tt>\b 0x40:</tt> GPIO INTFL Register */
+    __R  uint32_t rsv_0x44;
+    __IO uint32_t intfl_clr;            /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */
+    __IO uint32_t wken;                 /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */
+    __IO uint32_t wken_set;             /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */
+    __IO uint32_t wken_clr;             /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */
+    __R  uint32_t rsv_0x58;
+    __IO uint32_t dualedge;             /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */
+    __IO uint32_t padctrl0;             /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */
+    __IO uint32_t padctrl1;             /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */
+    __IO uint32_t en1;                  /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
+    __IO uint32_t en1_set;              /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
+    __IO uint32_t en1_clr;              /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
+    __IO uint32_t en2;                  /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
+    __IO uint32_t en2_set;              /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
+    __IO uint32_t en2_clr;              /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
+    __R  uint32_t rsv_0x80_0xa7[10];
+    __IO uint32_t hysen;                /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */
+    __IO uint32_t srsel;                /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */
+    __IO uint32_t ds0;                  /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
+    __IO uint32_t ds1;                  /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
+    __IO uint32_t ps;                   /**< <tt>\b 0xB8:</tt> GPIO PS Register */
+    __R  uint32_t rsv_0xbc;
+    __IO uint32_t vssel;                /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
+} mxc_gpio_reva_regs_t;
+
+/* Register offsets for module GPIO */
+/**
+ * @ingroup    gpio_registers
+ * @defgroup   GPIO_Register_Offsets Register Offsets
+ * @brief      GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_GPIO_REVA_EN0                     ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
+ #define MXC_R_GPIO_REVA_EN0_SET                 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
+ #define MXC_R_GPIO_REVA_EN0_CLR                 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
+ #define MXC_R_GPIO_REVA_OUTEN                   ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
+ #define MXC_R_GPIO_REVA_OUTEN_SET               ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
+ #define MXC_R_GPIO_REVA_OUTEN_CLR               ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
+ #define MXC_R_GPIO_REVA_OUT                     ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
+ #define MXC_R_GPIO_REVA_OUT_SET                 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
+ #define MXC_R_GPIO_REVA_OUT_CLR                 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
+ #define MXC_R_GPIO_REVA_IN                      ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
+ #define MXC_R_GPIO_REVA_INTMODE                 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
+ #define MXC_R_GPIO_REVA_INTPOL                  ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
+ #define MXC_R_GPIO_REVA_INEN                    ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
+ #define MXC_R_GPIO_REVA_INTEN                   ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
+ #define MXC_R_GPIO_REVA_INTEN_SET               ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
+ #define MXC_R_GPIO_REVA_INTEN_CLR               ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
+ #define MXC_R_GPIO_REVA_INTFL                   ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
+ #define MXC_R_GPIO_REVA_INTFL_CLR               ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
+ #define MXC_R_GPIO_REVA_WKEN                    ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
+ #define MXC_R_GPIO_REVA_WKEN_SET                ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
+ #define MXC_R_GPIO_REVA_WKEN_CLR                ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
+ #define MXC_R_GPIO_REVA_DUALEDGE                ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
+ #define MXC_R_GPIO_REVA_PADCTRL0                ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
+ #define MXC_R_GPIO_REVA_PADCTRL1                ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
+ #define MXC_R_GPIO_REVA_EN1                     ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
+ #define MXC_R_GPIO_REVA_EN1_SET                 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
+ #define MXC_R_GPIO_REVA_EN1_CLR                 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
+ #define MXC_R_GPIO_REVA_EN2                     ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
+ #define MXC_R_GPIO_REVA_EN2_SET                 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
+ #define MXC_R_GPIO_REVA_EN2_CLR                 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
+ #define MXC_R_GPIO_REVA_HYSEN                   ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
+ #define MXC_R_GPIO_REVA_SRSEL                   ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
+ #define MXC_R_GPIO_REVA_DS0                     ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
+ #define MXC_R_GPIO_REVA_DS1                     ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
+ #define MXC_R_GPIO_REVA_PS                      ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
+ #define MXC_R_GPIO_REVA_VSSEL                   ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
+/**@} end of group gpio_registers */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN0 GPIO_EN0
+ * @brief    GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
+ *           GPIO pin on the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS                     0 /**< EN0_GPIO_REVA_EN Position */
+ #define MXC_F_GPIO_REVA_EN0_GPIO_EN                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */
+ #define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE               ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */
+ #define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE               (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */
+ #define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO                    ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */
+ #define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO                    (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */
+
+/**@} end of group GPIO_EN0_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN0_SET GPIO_EN0_SET
+ * @brief    GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
+ *           register sets the bits in the same positions in GPIO_EN to 1, without affecting
+ *           other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN0_SET_ALL_POS                     0 /**< EN0_SET_ALL Position */
+ #define MXC_F_GPIO_REVA_EN0_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */
+
+/**@} end of group GPIO_EN0_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR
+ * @brief    GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
+ *           register clears the bits in the same positions in GPIO_EN to 0, without
+ *           affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS                     0 /**< EN0_CLR_ALL Position */
+ #define MXC_F_GPIO_REVA_EN0_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN0_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUTEN GPIO_OUTEN
+ * @brief    GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
+ *           GPIO pin in the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_OUTEN_EN_POS                        0 /**< OUTEN_EN Position */
+ #define MXC_F_GPIO_REVA_OUTEN_EN                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */
+ #define MXC_V_GPIO_REVA_OUTEN_EN_DIS                        ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */
+ #define MXC_S_GPIO_REVA_OUTEN_EN_DIS                        (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */
+ #define MXC_V_GPIO_REVA_OUTEN_EN_EN                         ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */
+ #define MXC_S_GPIO_REVA_OUTEN_EN_EN                         (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */
+
+/**@} end of group GPIO_OUTEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET
+ * @brief    GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
+ *           in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
+ *           without affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS                   0 /**< OUTEN_SET_ALL Position */
+ #define MXC_F_GPIO_REVA_OUTEN_SET_ALL                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */
+
+/**@} end of group GPIO_OUTEN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR
+ * @brief    GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
+ *           bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
+ *           without affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS                   0 /**< OUTEN_CLR_ALL Position */
+ #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */
+
+/**@} end of group GPIO_OUTEN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT GPIO_OUT
+ * @brief    GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
+ *           associated port.  This register can be written either directly, or by using the
+ *           GPIO_OUT_SET and GPIO_OUT_CLR registers.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS                    0 /**< OUT_GPIO_OUT Position */
+ #define MXC_F_GPIO_REVA_OUT_GPIO_OUT                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
+ #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW                    ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
+ #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW                    (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
+ #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH                   ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
+ #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH                   (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
+
+/**@} end of group GPIO_OUT_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_SET GPIO_OUT_SET
+ * @brief    GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
+ *           in the same positions in GPIO_OUT to 1, without affecting other bits in that
+ *           register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS            0 /**< OUT_SET_GPIO_OUT_SET Position */
+ #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
+ #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO             ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
+ #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO             (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
+ #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET            ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
+ #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET            (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
+
+/**@} end of group GPIO_OUT_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
+ * @brief    GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
+ *           bits in the same positions in GPIO_OUT to 0, without affecting other bits in
+ *           that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS            0 /**< OUT_CLR_GPIO_OUT_CLR Position */
+ #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
+
+/**@} end of group GPIO_OUT_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_IN GPIO_IN
+ * @brief    GPIO Input Register. Read-only register to read from the logic states of the
+ *           GPIO pins on this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_IN_GPIO_IN_POS                      0 /**< IN_GPIO_IN Position */
+ #define MXC_F_GPIO_REVA_IN_GPIO_IN                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
+
+/**@} end of group GPIO_IN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTMODE GPIO_INTMODE
+ * @brief    GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
+ *           mode setting for the associated GPIO pin on this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS            0 /**< INTMODE_GPIO_INTMODE Position */
+ #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */
+ #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL          ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */
+ #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL          (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */
+ #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE           ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */
+ #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE           (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */
+
+/**@} end of group GPIO_INTMODE_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTPOL GPIO_INTPOL
+ * @brief    GPIO Interrupt Polarity Register. Each bit in this register controls the
+ *           interrupt polarity setting for one GPIO pin in the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS              0 /**< INTPOL_GPIO_INTPOL Position */
+ #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL                  ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */
+ #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING          ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */
+ #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING          (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */
+ #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING           ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */
+ #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING           (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */
+
+/**@} end of group GPIO_INTPOL_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTEN GPIO_INTEN
+ * @brief    GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
+ *           interrupt enable for the associated pin on the GPIO port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS                0 /**< INTEN_GPIO_REVA_INTEN Position */
+ #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */
+ #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS                ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */
+ #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS                (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */
+ #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN                 ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */
+ #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN                 (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */
+
+/**@} end of group GPIO_INTEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET
+ * @brief    GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
+ *           the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
+ *           in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS        0 /**< INTEN_SET_GPIO_INTEN_SET Position */
+ #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET            ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */
+ #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO         ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */
+ #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO         (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */
+ #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET        ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */
+ #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET        (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */
+
+/**@} end of group GPIO_INTEN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR
+ * @brief    GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
+ *           clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
+ *           other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS        0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */
+ #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR            ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */
+ #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO         ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */
+ #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO         (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */
+ #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR      ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */
+ #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR      (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */
+
+/**@} end of group GPIO_INTEN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTFL GPIO_INTFL
+ * @brief    GPIO Interrupt Status Register. Each bit in this register contains the pending
+ *           interrupt status for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS                0 /**< INTFL_GPIO_INTFL Position */
+ #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */
+ #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO                 ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */
+ #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO                 (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */
+ #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING            ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */
+ #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING            (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */
+
+/**@} end of group GPIO_INTFL_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR
+ * @brief    GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
+ *           bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
+ *           in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS                   0 /**< INTFL_CLR_ALL Position */
+ #define MXC_F_GPIO_REVA_INTFL_CLR_ALL                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */
+
+/**@} end of group GPIO_INTFL_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WKEN GPIO_WKEN
+ * @brief    GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
+ *           enable for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS                  0 /**< WKEN_GPIO_WKEN Position */
+ #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN                      ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */
+ #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS                  ((uint32_t)0x0UL) /**< WKEN_GPIO_REVA_WKEN_DIS Value */
+ #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS                  (MXC_V_GPIO_WKEN_REVA_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */
+ #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN                   ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */
+ #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN                   (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */
+
+/**@} end of group GPIO_WKEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET
+ * @brief    GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
+ *           bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
+ *           that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS                    0 /**< WKEN_SET_ALL Position */
+ #define MXC_F_GPIO_REVA_WKEN_SET_ALL                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */
+
+/**@} end of group GPIO_WKEN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR
+ * @brief    GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
+ *           the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS                    0 /**< WKEN_CLR_ALL Position */
+ #define MXC_F_GPIO_REVA_WKEN_CLR_ALL                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */
+
+/**@} end of group GPIO_WKEN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE
+ * @brief    GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
+ *           edge mode for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS          0 /**< DUALEDGE_GPIO_DUALEDGE Position */
+ #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */
+ #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO           ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */
+ #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO           (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */
+ #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN           ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */
+ #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN           (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */
+
+/**@} end of group GPIO_DUALEDGE_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0
+ * @brief    GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
+ *           the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS          0 /**< PADCTRL0_GPIO_PADCTRL0 Position */
+ #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */
+ #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE    ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */
+ #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE    (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */
+ #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU           ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */
+ #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU           (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */
+ #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD           ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */
+ #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD           (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */
+
+/**@} end of group GPIO_PADCTRL0_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1
+ * @brief    GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
+ *           the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS          0 /**< PADCTRL1_GPIO_PADCTRL1 Position */
+ #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */
+ #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE    ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */
+ #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE    (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */
+ #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU           ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */
+ #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU           (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */
+ #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD           ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */
+ #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD           (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */
+
+/**@} end of group GPIO_PADCTRL1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1 GPIO_EN1
+ * @brief    GPIO Alternate Function Enable Register. Each bit in this register selects
+ *           between primary/secondary functions for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS                    0 /**< EN1_GPIO_EN1 Position */
+ #define MXC_F_GPIO_REVA_EN1_GPIO_EN1                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
+ #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY                ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
+ #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY                (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
+ #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY              ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
+ #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY              (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
+
+/**@} end of group GPIO_EN1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1_SET GPIO_EN1_SET
+ * @brief    GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
+ *           sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN1_SET_ALL_POS                     0 /**< EN1_SET_ALL Position */
+ #define MXC_F_GPIO_REVA_EN1_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
+
+/**@} end of group GPIO_EN1_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
+ * @brief    GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
+ *           clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS                     0 /**< EN1_CLR_ALL Position */
+ #define MXC_F_GPIO_REVA_EN1_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN1_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2 GPIO_EN2
+ * @brief    GPIO Alternate Function Enable Register. Each bit in this register selects
+ *           between primary/secondary functions for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS                    0 /**< EN2_GPIO_EN2 Position */
+ #define MXC_F_GPIO_REVA_EN2_GPIO_EN2                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
+ #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY                ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
+ #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY                (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
+ #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY              ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
+ #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY              (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
+
+/**@} end of group GPIO_EN2_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2_SET GPIO_EN2_SET
+ * @brief    GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
+ *           sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN2_SET_ALL_POS                     0 /**< EN2_SET_ALL Position */
+ #define MXC_F_GPIO_REVA_EN2_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
+
+/**@} end of group GPIO_EN2_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
+ * @brief    GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
+ *           register clears the bits in the same positions in GPIO_EN2 to 0, without
+ *           affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS                     0 /**< EN2_CLR_ALL Position */
+ #define MXC_F_GPIO_REVA_EN2_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN2_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_HYSEN GPIO_HYSEN
+ * @brief    GPIO Input Hysteresis Enable.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS                0 /**< HYSEN_GPIO_HYSEN Position */
+ #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */
+
+/**@} end of group GPIO_HYSEN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_SRSEL GPIO_SRSEL
+ * @brief    GPIO Slew Rate Enable Register.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS                0 /**< SRSEL_GPIO_SRSEL Position */
+ #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */
+ #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST               ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */
+ #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST               (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */
+ #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW               ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */
+ #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW               (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */
+
+/**@} end of group GPIO_SRSEL_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DS0 GPIO_DS0
+ * @brief    GPIO Drive Strength  Register. Each bit in this register selects the drive
+ *           strength for the associated GPIO pin in this port. Refer to the Datasheet for
+ *           sink/source current of GPIO pins in each mode.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS                    0 /**< DS0_GPIO_DS0 Position */
+ #define MXC_F_GPIO_REVA_DS0_GPIO_DS0                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */
+ #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD                     ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */
+ #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD                     (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */
+ #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD                     ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */
+ #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD                     (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */
+
+/**@} end of group GPIO_DS0_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DS1 GPIO_DS1
+ * @brief    GPIO Drive Strength 1 Register. Each bit in this register selects the drive
+ *           strength for the associated GPIO pin in this port. Refer to the Datasheet for
+ *           sink/source current of GPIO pins in each mode.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS                    0 /**< DS1_GPIO_DS1 Position */
+ #define MXC_F_GPIO_REVA_DS1_GPIO_DS1                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */
+
+/**@} end of group GPIO_DS1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PS GPIO_PS
+ * @brief    GPIO Pull Select Mode.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_PS_ALL_POS                          0 /**< PS_ALL Position */
+ #define MXC_F_GPIO_REVA_PS_ALL                              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */
+
+/**@} end of group GPIO_PS_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_VSSEL GPIO_VSSEL
+ * @brief    GPIO Voltage Select.
+ * @{
+ */
+ #define MXC_F_GPIO_REVA_VSSEL_ALL_POS                       0 /**< VSSEL_ALL Position */
+ #define MXC_F_GPIO_REVA_VSSEL_ALL                           ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
+
+/**@} end of group GPIO_VSSEL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_REVA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c

@@ -0,0 +1,412 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+
+#include <stdio.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "mxc_pins.h"
+#include "mxc_delay.h"
+#include "i2c_regs.h"
+#include "dma_regs.h"
+#include "mxc_i2c.h"
+#include "i2c_reva.h"
+
+
+/* **** Definitions **** */
+#define MXC_I2C_FASTPLUS_SPEED 1000000
+
+/* **** Variable Declaration **** */
+uint32_t interruptCheck = MXC_F_I2C_INTFL0_ADDR_MATCH | MXC_F_I2C_INTFL0_DNR_ERR;
+
+/* **** Function Prototypes **** */
+
+/* ************************************************************************* */
+/* Control/Configuration functions                                           */
+/* ************************************************************************* */
+int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr)
+{
+    if (i2c == NULL) {
+        return E_NULL_PTR;
+    }
+    
+    MXC_I2C_Shutdown(i2c);  // Clear everything out
+    
+    if (i2c == MXC_I2C0) {
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0);
+        MXC_GPIO_Config(&gpio_cfg_i2c0);
+    }
+  #if TARGET_NUM != 32675
+    else if (i2c == MXC_I2C1) {
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1);
+        MXC_GPIO_Config(&gpio_cfg_i2c1);
+    }
+  #endif
+    else if (i2c == MXC_I2C2) {
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2);
+        MXC_GPIO_Config(&gpio_cfg_i2c2);
+    }
+    else {
+        return E_NO_DEVICE;
+    }
+    
+    return MXC_I2C_RevA_Init ((mxc_i2c_reva_regs_t*) i2c, masterMode, slaveAddr);
+}
+
+int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx)
+{
+    if(i2c == NULL) {
+        return E_NULL_PTR;
+    }
+
+    if(idx != 0) {
+        // Multiple slaves are not supported yet
+        return E_NOT_SUPPORTED;
+    }
+
+    if(slaveAddr > MXC_F_I2C_SLAVE_ADDR) {
+        // Only support addresses up to 10 bits
+        return E_BAD_PARAM;
+    }
+
+    i2c->slave = 0;
+
+    if(slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) {
+        // Set for 10bit addressing mode
+        i2c->slave = MXC_F_I2C_SLAVE_EXT_ADDR_EN;
+    }
+
+    i2c->slave |= slaveAddr;
+
+    return E_NO_ERROR;
+}
+
+int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c)
+{
+    // Configure GPIO for I2C
+    if (i2c == MXC_I2C0) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0);
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0);
+    }
+    else if (i2c == MXC_I2C1) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1);
+    }
+    else if (i2c == MXC_I2C2) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2);
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2);
+    }
+    else {
+        return E_NO_DEVICE;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_I2C_Reset (mxc_i2c_regs_t* i2c)
+{
+    // Configure GPIO for I2C
+    if(i2c == MXC_I2C0) {
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0);
+    }
+    else if(i2c == MXC_I2C1) {
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1);
+    }
+    else if(i2c == MXC_I2C2) {
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2);
+    }
+    else {
+        return E_NO_DEVICE;
+    }
+    
+    return E_NO_ERROR;    
+}
+
+int MXC_I2C_SetFrequency(mxc_i2c_regs_t* i2c, unsigned int hz)
+{
+    // ME13 doesn't support high speed more
+    if (hz > MXC_I2C_FASTPLUS_SPEED) {
+        return E_NOT_SUPPORTED;
+    }
+    
+    return MXC_I2C_RevA_SetFrequency ((mxc_i2c_reva_regs_t*) i2c, hz);
+}
+
+unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_GetFrequency ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_ReadyForSleep ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_SetClockStretching(mxc_i2c_regs_t* i2c, int enable)
+{
+    return MXC_I2C_RevA_SetClockStretching ((mxc_i2c_reva_regs_t*) i2c, enable);
+}
+
+int MXC_I2C_GetClockStretching(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_GetClockStretching ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+/* ************************************************************************* */
+/* Low-level functions                                                       */
+/* ************************************************************************* */
+int MXC_I2C_Start(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_Start ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_Stop(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_Stop ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_WriteByte(mxc_i2c_regs_t* i2c, unsigned char byte)
+{
+    return MXC_I2C_RevA_WriteByte ((mxc_i2c_reva_regs_t*) i2c, byte);
+}
+
+int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack)
+{
+    return MXC_I2C_RevA_ReadByte ((mxc_i2c_reva_regs_t*) i2c, byte, ack);
+}
+    // return MXC_I2C_RevA_ReadByteInteractive ((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck);
+// }
+
+int MXC_I2C_Write(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len)
+{
+    return MXC_I2C_RevA_Write ((mxc_i2c_reva_regs_t*) i2c, bytes, len);
+}
+
+int MXC_I2C_Read(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack)
+{
+    return MXC_I2C_RevA_Read ((mxc_i2c_reva_regs_t*) i2c, bytes, len, ack);
+}
+
+int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len)
+{
+    return MXC_I2C_RevA_ReadRXFIFO ((mxc_i2c_reva_regs_t*) i2c, bytes, len);
+}
+
+int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback)
+{
+    uint8_t i2cNum;
+    mxc_dma_config_t config;
+    
+    i2cNum = MXC_I2C_GET_IDX(i2c);
+    
+    switch (i2cNum) {
+    case 0:
+        config.reqsel = MXC_DMA_REQUEST_I2C0RX;
+        break;
+        
+    case 1:
+        config.reqsel = MXC_DMA_REQUEST_I2C1RX;
+        break;
+    
+    default:
+        return E_BAD_PARAM;
+    }
+    
+    return MXC_I2C_RevA_ReadRXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA);
+}
+
+int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_GetRXFIFOAvailable ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len)
+{
+    return MXC_I2C_RevA_WriteTXFIFO ((mxc_i2c_reva_regs_t*) i2c, bytes, len);
+}
+
+int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback)
+{
+    uint8_t i2cNum;
+    mxc_dma_config_t config;
+    
+    i2cNum = MXC_I2C_GET_IDX(i2c);
+    
+    switch (i2cNum) {
+    case 0:
+        config.reqsel = MXC_DMA_REQUEST_I2C0TX;
+        break;
+        
+    case 1:
+        config.reqsel = MXC_DMA_REQUEST_I2C1TX;
+        break;
+    
+    default:
+        return E_BAD_PARAM;
+    }
+
+    return MXC_I2C_RevA_WriteTXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA);
+}
+
+int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_GetTXFIFOAvailable ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t* i2c)
+{
+    MXC_I2C_RevA_ClearRXFIFO ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t* i2c)
+{
+    MXC_I2C_RevA_ClearTXFIFO ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_GetFlags(mxc_i2c_regs_t* i2c, unsigned int* flags0, unsigned int* flags1)
+{
+    return MXC_I2C_RevA_GetFlags ((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
+}
+
+void MXC_I2C_ClearFlags(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1)
+{
+    MXC_I2C_RevA_ClearFlags ((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
+}
+
+void MXC_I2C_EnableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1)
+{
+    MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
+}
+
+void MXC_I2C_DisableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1)
+{
+    MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1);
+}
+
+void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c)
+{
+    MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t*) i2c);
+}
+
+void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c)
+{
+    MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t*) i2c);
+}
+
+void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c)
+{
+    MXC_I2C_RevA_EnableGeneralCall ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c)
+{
+    MXC_I2C_RevA_DisableGeneralCall ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout)
+{
+    MXC_I2C_RevA_SetTimeout ((mxc_i2c_reva_regs_t*) i2c, timeout);
+}
+
+unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_GetTimeout ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_Recover(mxc_i2c_regs_t* i2c, unsigned int retries)
+{
+    return MXC_I2C_RevA_Recover ((mxc_i2c_reva_regs_t*) i2c, retries);
+}
+
+/* ************************************************************************* */
+/* Transaction level functions                                               */
+/* ************************************************************************* */
+
+int MXC_I2C_MasterTransaction(mxc_i2c_req_t* req)
+{
+    return MXC_I2C_RevA_MasterTransaction ((mxc_i2c_reva_req_t*) req);
+}
+
+int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t* req)
+{
+    return MXC_I2C_RevA_MasterTransactionAsync ((mxc_i2c_reva_req_t*) req);
+}
+
+int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req)
+{
+    return MXC_I2C_RevA_MasterTransactionDMA ((mxc_i2c_reva_req_t*) req, MXC_DMA);
+}
+
+int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback)
+{
+    return MXC_I2C_RevA_SlaveTransaction ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck);
+}
+
+int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback)
+{
+    return MXC_I2C_RevA_SlaveTransactionAsync ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck);
+}
+
+int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes)
+{
+    return MXC_I2C_RevA_SetRXThreshold ((mxc_i2c_reva_regs_t*) i2c, numBytes);
+}
+
+unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_GetRXThreshold ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes)
+{
+    return MXC_I2C_RevA_SetTXThreshold ((mxc_i2c_reva_regs_t*) i2c, numBytes);
+}
+
+unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t* i2c)
+{
+    return MXC_I2C_RevA_GetTXThreshold ((mxc_i2c_reva_regs_t*) i2c);
+}
+
+void MXC_I2C_AsyncHandler(mxc_i2c_regs_t* i2c)
+{
+    MXC_I2C_RevA_AsyncHandler ((mxc_i2c_reva_regs_t*) i2c, interruptCheck);
+}
+
+void MXC_I2C_DMACallback(int ch, int error)
+{
+    MXC_I2C_RevA_DMACallback(ch, error);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h

@@ -0,0 +1,159 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#ifndef _I2C_REVA_H_
+#define _I2C_REVA_H_
+
+#include <stdio.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "i2c_regs.h"
+#include "i2c_reva_regs.h"
+#include "dma.h"
+
+
+/* **** Definitions **** */
+#define MXC_I2C_REVA_MAX_ADDR_WIDTH  0x7F
+#define MXC_I2C_REVA_STD_MODE        100000
+#define MXC_I2C_REVA_FAST_SPEED      400000
+#define MXC_I2C_REVA_FASTPLUS_SPEED  1000000
+#define MXC_I2C_REVA_HS_MODE         3400000
+
+#define MXC_I2C_REVA_INTFL0_MASK     0x00FFFFFF
+#define MXC_I2C_REVA_INTFL1_MASK     0x00000007
+
+#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION    256
+
+#define MXC_I2C_REVA_ERROR   (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \
+                            MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \
+                            MXC_F_I2C_REVA_INTFL0_STOP_ERR)
+
+typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t;
+typedef int (*mxc_i2c_reva_getAck_t) (mxc_i2c_reva_regs_t* i2c, unsigned char byte);
+typedef void (*mxc_i2c_reva_complete_cb_t) (mxc_i2c_reva_req_t* req, int result);
+typedef void (*mxc_i2c_reva_dma_complete_cb_t) (int len, int result);
+struct _i2c_reva_req_t {
+    mxc_i2c_reva_regs_t* i2c;
+    unsigned int addr;
+    unsigned char* tx_buf;
+    unsigned int tx_len;
+    unsigned char* rx_buf;
+    unsigned int rx_len;
+    int restart;
+    mxc_i2c_reva_complete_cb_t callback;
+};
+typedef enum {
+    MXC_I2C_REVA_EVT_MASTER_WR,
+    MXC_I2C_REVA_EVT_MASTER_RD,
+    MXC_I2C_REVA_EVT_RX_THRESH,
+    MXC_I2C_REVA_EVT_TX_THRESH,
+    MXC_I2C_REVA_EVT_TRANS_COMP,
+    MXC_I2C_REVA_EVT_UNDERFLOW,
+    MXC_I2C_REVA_EVT_OVERFLOW,
+} mxc_i2c_reva_slave_event_t;
+typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c,
+                                        mxc_i2c_reva_slave_event_t event, void* data);
+/* **** Variable Declaration **** */
+
+extern void* AsyncRequests[MXC_I2C_INSTANCES];
+
+/* **** Function Prototypes **** */
+
+/* ************************************************************************* */
+/* Control/Configuration functions                                           */
+/* ************************************************************************* */
+int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr);
+int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx);
+int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz);
+unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable);
+int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c);
+
+/* ************************************************************************* */
+/* Low-level functions                                                       */
+/* ************************************************************************* */
+int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte);
+int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack);
+int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck);
+int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len);
+int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack);
+int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len);
+int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma);
+int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len);
+int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma);
+int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1);
+void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1);
+void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1);
+void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1);
+void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout);
+unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries);
+
+/* ************************************************************************* */
+/* Transaction level functions                                               */
+/* ************************************************************************* */
+int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req);
+int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req);
+int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma);
+int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck);
+int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck);
+int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes);
+unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c);
+int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes);
+unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal);
+void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c);
+void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum);
+unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal);
+void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck);
+void MXC_I2C_RevA_DMACallback (int ch, int error);
+
+#endif /* _I2C_REVA_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h

@@ -0,0 +1,580 @@
+/**
+ * @file    i2c_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _I2C_REVA_REGS_H_
+#define _I2C_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     i2c
+ * @defgroup    i2c_registers I2C_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
+ * @details Inter-Integrated Circuit.
+ */
+
+/**
+ * @ingroup i2c_registers
+ * Structure type to access the I2C Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> I2C CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x04:</tt> I2C STATUS Register */
+    __IO uint32_t intfl0;               /**< <tt>\b 0x08:</tt> I2C INTFL0 Register */
+    __IO uint32_t inten0;               /**< <tt>\b 0x0C:</tt> I2C INTEN0 Register */
+    __IO uint32_t intfl1;               /**< <tt>\b 0x10:</tt> I2C INTFL1 Register */
+    __IO uint32_t inten1;               /**< <tt>\b 0x14:</tt> I2C INTEN1 Register */
+    __IO uint32_t fifolen;              /**< <tt>\b 0x18:</tt> I2C FIFOLEN Register */
+    __IO uint32_t rxctrl0;              /**< <tt>\b 0x1C:</tt> I2C RXCTRL0 Register */
+    __IO uint32_t rxctrl1;              /**< <tt>\b 0x20:</tt> I2C RXCTRL1 Register */
+    __IO uint32_t txctrl0;              /**< <tt>\b 0x24:</tt> I2C TXCTRL0 Register */
+    __IO uint32_t txctrl1;              /**< <tt>\b 0x28:</tt> I2C TXCTRL1 Register */
+    __IO uint32_t fifo;                 /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
+    __IO uint32_t mstctrl;              /**< <tt>\b 0x30:</tt> I2C MSTCTRL Register */
+    __IO uint32_t clklo;                /**< <tt>\b 0x34:</tt> I2C CLKLO Register */
+    __IO uint32_t clkhi;                /**< <tt>\b 0x38:</tt> I2C CLKHI Register */
+    __IO uint32_t hsclk;                /**< <tt>\b 0x3C:</tt> I2C HSCLK Register */
+    __IO uint32_t timeout;              /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
+    __R  uint32_t rsv_0x44;
+    __IO uint32_t dma;                  /**< <tt>\b 0x48:</tt> I2C DMA Register */
+    __IO uint32_t slave;                /**< <tt>\b 0x4C:</tt> I2C SLAVE Register */
+} mxc_i2c_reva_regs_t;
+
+/* Register offsets for module I2C */
+/**
+ * @ingroup    i2c_registers
+ * @defgroup   I2C_Register_Offsets Register Offsets
+ * @brief      I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_I2C_REVA_CTRL                     ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_I2C_REVA_STATUS                   ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_I2C_REVA_INTFL0                   ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_I2C_REVA_INTEN0                   ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_I2C_REVA_INTFL1                   ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_I2C_REVA_INTEN1                   ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_I2C_REVA_FIFOLEN                  ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_I2C_REVA_RXCTRL0                  ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_I2C_REVA_RXCTRL1                  ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_I2C_REVA_TXCTRL0                  ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_I2C_REVA_TXCTRL1                  ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_I2C_REVA_FIFO                     ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_I2C_REVA_MSTCTRL                  ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_I2C_REVA_CLKLO                    ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_I2C_REVA_CLKHI                    ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 
+ #define MXC_R_I2C_REVA_HSCLK                    ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ 
+ #define MXC_R_I2C_REVA_TIMEOUT                  ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_I2C_REVA_DMA                      ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 
+ #define MXC_R_I2C_REVA_SLAVE                    ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: <tt> 0x004C</tt> */ 
+/**@} end of group i2c_registers */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CTRL I2C_CTRL
+ * @brief    Control Register0.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_I2C_REVA_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_MST_MODE_POS                    1 /**< CTRL_MST_MODE Position */
+ #define MXC_F_I2C_REVA_CTRL_MST_MODE                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS                  2 /**< CTRL_GC_ADDR_EN Position */
+ #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS                     3 /**< CTRL_IRXM_EN Position */
+ #define MXC_F_I2C_REVA_CTRL_IRXM_EN                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS                    4 /**< CTRL_IRXM_ACK Position */
+ #define MXC_F_I2C_REVA_CTRL_IRXM_ACK                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS                     6 /**< CTRL_SCL_OUT Position */
+ #define MXC_F_I2C_REVA_CTRL_SCL_OUT                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS                     7 /**< CTRL_SDA_OUT Position */
+ #define MXC_F_I2C_REVA_CTRL_SDA_OUT                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_SCL_POS                         8 /**< CTRL_SCL Position */
+ #define MXC_F_I2C_REVA_CTRL_SCL                             ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_SDA_POS                         9 /**< CTRL_SDA Position */
+ #define MXC_F_I2C_REVA_CTRL_SDA                             ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_BB_MODE_POS                     10 /**< CTRL_BB_MODE Position */
+ #define MXC_F_I2C_REVA_CTRL_BB_MODE                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_READ_POS                        11 /**< CTRL_READ Position */
+ #define MXC_F_I2C_REVA_CTRL_READ                            ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS                  12 /**< CTRL_CLKSTR_DIS Position */
+ #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS                13 /**< CTRL_ONE_MST_MODE Position */
+ #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE                    ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */
+
+ #define MXC_F_I2C_REVA_CTRL_HS_EN_POS                       15 /**< CTRL_HS_EN Position */
+ #define MXC_F_I2C_REVA_CTRL_HS_EN                           ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */
+
+/**@} end of group I2C_CTRL_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_STATUS I2C_STATUS
+ * @brief    Status Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_STATUS_BUSY_POS                      0 /**< STATUS_BUSY Position */
+ #define MXC_F_I2C_REVA_STATUS_BUSY                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
+
+ #define MXC_F_I2C_REVA_STATUS_RX_EM_POS                     1 /**< STATUS_RX_EM Position */
+ #define MXC_F_I2C_REVA_STATUS_RX_EM                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
+
+ #define MXC_F_I2C_REVA_STATUS_RX_FULL_POS                   2 /**< STATUS_RX_FULL Position */
+ #define MXC_F_I2C_REVA_STATUS_RX_FULL                       ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+
+ #define MXC_F_I2C_REVA_STATUS_TX_EM_POS                     3 /**< STATUS_TX_EM Position */
+ #define MXC_F_I2C_REVA_STATUS_TX_EM                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
+
+ #define MXC_F_I2C_REVA_STATUS_TX_FULL_POS                   4 /**< STATUS_TX_FULL Position */
+ #define MXC_F_I2C_REVA_STATUS_TX_FULL                       ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+
+ #define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS                  5 /**< STATUS_MST_BUSY Position */
+ #define MXC_F_I2C_REVA_STATUS_MST_BUSY                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */
+
+/**@} end of group I2C_STATUS_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTFL0 I2C_INTFL0
+ * @brief    Interrupt Status Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_INTFL0_DONE_POS                      0 /**< INTFL0_DONE Position */
+ #define MXC_F_I2C_REVA_INTFL0_DONE                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_IRXM_POS                      1 /**< INTFL0_IRXM Position */
+ #define MXC_F_I2C_REVA_INTFL0_IRXM                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS             2 /**< INTFL0_GC_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS                3 /**< INTFL0_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH                    ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_RX_THD_POS                    4 /**< INTFL0_RX_THD Position */
+ #define MXC_F_I2C_REVA_INTFL0_RX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_TX_THD_POS                    5 /**< INTFL0_TX_THD Position */
+ #define MXC_F_I2C_REVA_INTFL0_TX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_STOP_POS                      6 /**< INTFL0_STOP Position */
+ #define MXC_F_I2C_REVA_INTFL0_STOP                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS                  7 /**< INTFL0_ADDR_ACK Position */
+ #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS                   8 /**< INTFL0_ARB_ERR Position */
+ #define MXC_F_I2C_REVA_INTFL0_ARB_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS                    9 /**< INTFL0_TO_ERR Position */
+ #define MXC_F_I2C_REVA_INTFL0_TO_ERR                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS             10 /**< INTFL0_ADDR_NACK_ERR Position */
+ #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS                  11 /**< INTFL0_DATA_ERR Position */
+ #define MXC_F_I2C_REVA_INTFL0_DATA_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS                   12 /**< INTFL0_DNR_ERR Position */
+ #define MXC_F_I2C_REVA_INTFL0_DNR_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_START_ERR_POS                 13 /**< INTFL0_START_ERR Position */
+ #define MXC_F_I2C_REVA_INTFL0_START_ERR                     ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS                  14 /**< INTFL0_STOP_ERR Position */
+ #define MXC_F_I2C_REVA_INTFL0_STOP_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS                15 /**< INTFL0_TX_LOCKOUT Position */
+ #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT                    ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_MAMI_POS                      16 /**< INTFL0_MAMI Position */
+ #define MXC_F_I2C_REVA_INTFL0_MAMI                          ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS             22 /**< INTFL0_RD_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS             23 /**< INTFL0_WR_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */
+
+/**@} end of group I2C_INTFL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTEN0 I2C_INTEN0
+ * @brief    Interrupt Enable Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_INTEN0_DONE_POS                      0 /**< INTEN0_DONE Position */
+ #define MXC_F_I2C_REVA_INTEN0_DONE                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_IRXM_POS                      1 /**< INTEN0_IRXM Position */
+ #define MXC_F_I2C_REVA_INTEN0_IRXM                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS             2 /**< INTEN0_GC_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS                3 /**< INTEN0_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH                    ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_RX_THD_POS                    4 /**< INTEN0_RX_THD Position */
+ #define MXC_F_I2C_REVA_INTEN0_RX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_TX_THD_POS                    5 /**< INTEN0_TX_THD Position */
+ #define MXC_F_I2C_REVA_INTEN0_TX_THD                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_STOP_POS                      6 /**< INTEN0_STOP Position */
+ #define MXC_F_I2C_REVA_INTEN0_STOP                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS                  7 /**< INTEN0_ADDR_ACK Position */
+ #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS                   8 /**< INTEN0_ARB_ERR Position */
+ #define MXC_F_I2C_REVA_INTEN0_ARB_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS                    9 /**< INTEN0_TO_ERR Position */
+ #define MXC_F_I2C_REVA_INTEN0_TO_ERR                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS             10 /**< INTEN0_ADDR_NACK_ERR Position */
+ #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS                  11 /**< INTEN0_DATA_ERR Position */
+ #define MXC_F_I2C_REVA_INTEN0_DATA_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS                   12 /**< INTEN0_DNR_ERR Position */
+ #define MXC_F_I2C_REVA_INTEN0_DNR_ERR                       ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_START_ERR_POS                 13 /**< INTEN0_START_ERR Position */
+ #define MXC_F_I2C_REVA_INTEN0_START_ERR                     ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS                  14 /**< INTEN0_STOP_ERR Position */
+ #define MXC_F_I2C_REVA_INTEN0_STOP_ERR                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS                15 /**< INTEN0_TX_LOCKOUT Position */
+ #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT                    ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_MAMI_POS                      16 /**< INTEN0_MAMI Position */
+ #define MXC_F_I2C_REVA_INTEN0_MAMI                          ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS             22 /**< INTEN0_RD_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS             23 /**< INTEN0_WR_ADDR_MATCH Position */
+ #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */
+
+/**@} end of group I2C_INTEN0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTFL1 I2C_INTFL1
+ * @brief    Interrupt Status Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_INTFL1_RX_OV_POS                     0 /**< INTFL1_RX_OV Position */
+ #define MXC_F_I2C_REVA_INTFL1_RX_OV                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */
+
+ #define MXC_F_I2C_REVA_INTFL1_TX_UN_POS                     1 /**< INTFL1_TX_UN Position */
+ #define MXC_F_I2C_REVA_INTFL1_TX_UN                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */
+
+ #define MXC_F_I2C_REVA_INTFL1_START_POS                     2 /**< INTFL1_START Position */
+ #define MXC_F_I2C_REVA_INTFL1_START                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */
+
+/**@} end of group I2C_INTFL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INTEN1 I2C_INTEN1
+ * @brief    Interrupt Staus Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_INTEN1_RX_OV_POS                     0 /**< INTEN1_RX_OV Position */
+ #define MXC_F_I2C_REVA_INTEN1_RX_OV                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */
+
+ #define MXC_F_I2C_REVA_INTEN1_TX_UN_POS                     1 /**< INTEN1_TX_UN Position */
+ #define MXC_F_I2C_REVA_INTEN1_TX_UN                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */
+
+ #define MXC_F_I2C_REVA_INTEN1_START_POS                     2 /**< INTEN1_START Position */
+ #define MXC_F_I2C_REVA_INTEN1_START                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */
+
+/**@} end of group I2C_INTEN1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_FIFOLEN I2C_FIFOLEN
+ * @brief    FIFO Configuration Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS                 0 /**< FIFOLEN_RX_DEPTH Position */
+ #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH                     ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */
+
+ #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS                 8 /**< FIFOLEN_TX_DEPTH Position */
+ #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH                     ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */
+
+/**@} end of group I2C_FIFOLEN_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_RXCTRL0 I2C_RXCTRL0
+ * @brief    Receive Control Register 0.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_RXCTRL0_DNR_POS                      0 /**< RXCTRL0_DNR Position */
+ #define MXC_F_I2C_REVA_RXCTRL0_DNR                          ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */
+
+ #define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS                    7 /**< RXCTRL0_FLUSH Position */
+ #define MXC_F_I2C_REVA_RXCTRL0_FLUSH                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */
+
+ #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS                  8 /**< RXCTRL0_THD_LVL Position */
+ #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL                      ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */
+
+/**@} end of group I2C_RXCTRL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_RXCTRL1 I2C_RXCTRL1
+ * @brief    Receive Control Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_RXCTRL1_CNT_POS                      0 /**< RXCTRL1_CNT Position */
+ #define MXC_F_I2C_REVA_RXCTRL1_CNT                          ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */
+
+ #define MXC_F_I2C_REVA_RXCTRL1_LVL_POS                      8 /**< RXCTRL1_LVL Position */
+ #define MXC_F_I2C_REVA_RXCTRL1_LVL                          ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */
+
+/**@} end of group I2C_RXCTRL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TXCTRL0 I2C_TXCTRL0
+ * @brief    Transmit Control Register 0.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS             0 /**< TXCTRL0_PRELOAD_MODE Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE                 ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS            1 /**< TXCTRL0_TX_READY_MODE Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE                ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS        2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS            ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS        3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS            ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS        4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS            ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS           5 /**< TXCTRL0_NACK_FLUSH_DIS Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS               ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS                    7 /**< TXCTRL0_FLUSH Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_FLUSH                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS                  8 /**< TXCTRL0_THD_LVL Position */
+ #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL                      ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */
+
+/**@} end of group I2C_TXCTRL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TXCTRL1 I2C_TXCTRL1
+ * @brief    Transmit Control Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS              0 /**< TXCTRL1_PRELOAD_RDY Position */
+ #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY                  ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */
+
+ #define MXC_F_I2C_REVA_TXCTRL1_LVL_POS                      8 /**< TXCTRL1_LVL Position */
+ #define MXC_F_I2C_REVA_TXCTRL1_LVL                          ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */
+
+/**@} end of group I2C_TXCTRL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_FIFO I2C_FIFO
+ * @brief    Data Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_FIFO_DATA_POS                        0 /**< FIFO_DATA Position */
+ #define MXC_F_I2C_REVA_FIFO_DATA                            ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+
+/**@} end of group I2C_FIFO_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_MSTCTRL I2C_MSTCTRL
+ * @brief    Master Control Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_MSTCTRL_START_POS                    0 /**< MSTCTRL_START Position */
+ #define MXC_F_I2C_REVA_MSTCTRL_START                        ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */
+
+ #define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS                  1 /**< MSTCTRL_RESTART Position */
+ #define MXC_F_I2C_REVA_MSTCTRL_RESTART                      ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */
+
+ #define MXC_F_I2C_REVA_MSTCTRL_STOP_POS                     2 /**< MSTCTRL_STOP Position */
+ #define MXC_F_I2C_REVA_MSTCTRL_STOP                         ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */
+
+ #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS               7 /**< MSTCTRL_EX_ADDR_EN Position */
+ #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN                   ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */
+
+/**@} end of group I2C_MSTCTRL_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CLKLO I2C_CLKLO
+ * @brief    Clock Low Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_CLKLO_LO_POS                         0 /**< CLKLO_LO Position */
+ #define MXC_F_I2C_REVA_CLKLO_LO                             ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */
+
+/**@} end of group I2C_CLKLO_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CLKHI I2C_CLKHI
+ * @brief    Clock high Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_CLKHI_HI_POS                         0 /**< CLKHI_HI Position */
+ #define MXC_F_I2C_REVA_CLKHI_HI                             ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */
+
+/**@} end of group I2C_CLKHI_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_HSCLK I2C_HSCLK
+ * @brief    Clock high Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_HSCLK_LO_POS                         0 /**< HSCLK_LO Position */
+ #define MXC_F_I2C_REVA_HSCLK_LO                             ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */
+
+ #define MXC_F_I2C_REVA_HSCLK_HI_POS                         8 /**< HSCLK_HI Position */
+ #define MXC_F_I2C_REVA_HSCLK_HI                             ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */
+
+/**@} end of group I2C_HSCLK_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TIMEOUT I2C_TIMEOUT
+ * @brief    Timeout Register
+ * @{
+ */
+ #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS               0 /**< TIMEOUT_SCL_TO_VAL Position */
+ #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL                   ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */
+
+/**@} end of group I2C_TIMEOUT_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_DMA I2C_DMA
+ * @brief    DMA Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_DMA_TX_EN_POS                        0 /**< DMA_TX_EN Position */
+ #define MXC_F_I2C_REVA_DMA_TX_EN                            ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
+
+ #define MXC_F_I2C_REVA_DMA_RX_EN_POS                        1 /**< DMA_RX_EN Position */
+ #define MXC_F_I2C_REVA_DMA_RX_EN                            ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
+
+/**@} end of group I2C_DMA_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_SLAVE I2C_SLAVE
+ * @brief    Slave Address Register.
+ * @{
+ */
+ #define MXC_F_I2C_REVA_SLAVE_ADDR_POS                       0 /**< SLAVE_ADDR Position */
+ #define MXC_F_I2C_REVA_SLAVE_ADDR                           ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */
+
+ #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS                15 /**< SLAVE_EXT_ADDR_EN Position */
+ #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN                    ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */
+
+/**@} end of group I2C_SLAVE_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2C_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_me15.c

@@ -0,0 +1,140 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include <stdio.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "dma.h"
+#include "i2s.h"
+#include "i2s_reva.h"
+#include "i2s_regs.h"
+
+int MXC_I2S_Init(mxc_i2s_req_t* req)
+{
+    MXC_I2S_Shutdown();
+
+    MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO);  
+    MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_I2S);
+    MXC_GPIO_Config (&gpio_cfg_i2s0);
+
+    return MXC_I2S_RevA_Init ((mxc_i2s_reva_regs_t*) MXC_I2S, req);
+}
+ 
+int MXC_I2S_Shutdown(void) {
+    MXC_I2S_RevA_Shutdown((mxc_i2s_reva_regs_t*) MXC_I2S);
+
+    MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_I2S);
+    MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2S);
+    
+    return E_NO_ERROR;
+}
+
+int MXC_I2S_ConfigData(mxc_i2s_req_t *req) 
+{
+    return MXC_I2S_RevA_ConfigData((mxc_i2s_reva_regs_t*) MXC_I2S, req);
+}
+
+void MXC_I2S_TXEnable(void) 
+{
+    MXC_I2S_RevA_TXEnable((mxc_i2s_reva_regs_t*) MXC_I2S);
+}
+
+void MXC_I2S_TXDisable(void) 
+{
+    MXC_I2S_RevA_TXDisable((mxc_i2s_reva_regs_t*) MXC_I2S);
+}
+
+void MXC_I2S_RXEnable(void) 
+{
+    MXC_I2S_RevA_RXEnable((mxc_i2s_reva_regs_t*) MXC_I2S);
+}
+
+void MXC_I2S_RXDisable(void) 
+{
+    MXC_I2S_RevA_RXDisable((mxc_i2s_reva_regs_t*) MXC_I2S);
+}
+
+int MXC_I2S_SetRXThreshold(uint8_t threshold)
+{
+    return MXC_I2S_RevA_SetRXThreshold((mxc_i2s_reva_regs_t*) MXC_I2S, threshold);
+}
+
+int MXC_I2S_SetFrequency(mxc_i2s_ch_mode_t mode, uint16_t clkdiv) 
+{
+    return MXC_I2S_RevA_SetFrequency((mxc_i2s_reva_regs_t*) MXC_I2S, mode, clkdiv);
+}
+
+void MXC_I2S_Flush(void) 
+{
+    MXC_I2S_RevA_Flush((mxc_i2s_reva_regs_t*) MXC_I2S);
+}
+
+void MXC_I2S_EnableInt(uint32_t flags)
+{
+    MXC_I2S_RevA_EnableInt((mxc_i2s_reva_regs_t*) MXC_I2S, flags);
+}
+
+void MXC_I2S_DisableInt(uint32_t flags)
+{
+    MXC_I2S_RevA_DisableInt((mxc_i2s_reva_regs_t*) MXC_I2S, flags);
+}
+
+int MXC_I2S_GetFlags(void)
+{
+    return MXC_I2S_RevA_GetFlags((mxc_i2s_reva_regs_t*) MXC_I2S);
+}
+
+void MXC_I2S_ClearFlags(uint32_t flags) 
+{
+    MXC_I2S_RevA_ClearFlags((mxc_i2s_reva_regs_t*) MXC_I2S, flags);
+}
+
+void MXC_I2S_TXDMAConfig(void *src_addr, int len) 
+{
+    MXC_I2S_RevA_TXDMAConfig((mxc_i2s_reva_regs_t*) MXC_I2S, src_addr, len);
+}
+
+void MXC_I2S_RXDMAConfig(void *dest_addr, int len) 
+{
+    MXC_I2S_RevA_RXDMAConfig((mxc_i2s_reva_regs_t*) MXC_I2S, dest_addr, len);
+}
+
+void MXC_I2S_RegisterDMACallback(void(*callback)(int, int))
+{
+    MXC_I2S_RevA_RegisterDMACallback(callback);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.c

@@ -0,0 +1,469 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include <stdio.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "dma.h"
+#include "i2s_reva.h"
+#include "i2s.h"
+
+/* ***** Definitions ***** */
+#define DATALENGTH_EIGHT        (8 - 1)
+#define DATALENGTH_SIXTEEN      (16 - 1)
+#define DATALENGTH_TWENTY       (20 - 1)
+#define DATALENGTH_TWENTYFOUR   (24 - 1)
+#define DATALENGTH_THIRTYTWO    (32 - 1)
+
+/* ****** Globals ****** */
+static mxc_i2s_req_t* request;
+static void* dma_cb = NULL;
+
+/* ****** Functions ****** */
+int MXC_I2S_RevA_Init(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t* req)
+{
+    if (((req->txData == NULL) || (req->rawData == NULL)) && (req->rxData == NULL)) {
+        return E_NULL_PTR;
+    }
+    
+    if (req->length == 0) {
+        return E_BAD_PARAM;
+    }
+
+    request = req;
+    
+    if (req->stereoMode) {
+        i2s->ctrl0ch0 |= (req->stereoMode << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS);
+    }
+    
+    //Set RX Threshold 2 (default)
+    i2s->ctrl0ch0 |= (2 << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS);
+    
+    //Set justify
+    MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_ALIGN, (req->justify) << MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS);
+    
+    if (MXC_I2S_ConfigData((mxc_i2s_req_t*) req) != E_NO_ERROR) {
+        return E_BAD_PARAM;
+    }
+    
+    MXC_I2S_SetFrequency(req->channelMode, req->clkdiv);
+    
+    return E_NO_ERROR;
+}
+
+int MXC_I2S_RevA_Shutdown(mxc_i2s_reva_regs_t *i2s)
+{
+    MXC_I2S_DisableInt(0xFF);
+    
+    //Disable I2S TX and RX channel
+    MXC_I2S_TXDisable();
+    MXC_I2S_RXDisable();
+    
+    MXC_I2S_Flush();
+    
+    //Clear all the registers. Not cleared on reset
+    i2s->ctrl0ch0 = 0x00;
+    i2s->dmach0   = 0x00;
+    i2s->ctrl1ch0 = 0x00;
+    
+    i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_RST;             //Reset channel
+    
+    return E_NO_ERROR;
+}
+
+int MXC_I2S_RevA_ConfigData(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t* req)
+{
+    uint32_t dataMask;
+    
+    //Data pointers
+    uint8_t  *txdata_8   = (uint8_t*) req->txData;
+    uint16_t *txdata_16  = (uint16_t*) req->txData;
+    uint32_t *txdata_32  = (uint32_t*) req->txData;
+    uint8_t  *rawdata_8  = (uint8_t*) req->rawData;
+    uint16_t *rawdata_16 = (uint16_t*) req->rawData;    
+    uint32_t *rawdata_32 = (uint32_t*) req->rawData;
+
+    if ((req->txData == NULL) & (req->rxData == NULL)) {
+        return E_NULL_PTR;
+    }
+    
+    if (req->length == 0) {
+        return E_BAD_PARAM;
+    }
+    
+    // Clear configuration bits
+    i2s->ctrl0ch0 &= ~MXC_F_I2S_REVA_CTRL0CH0_WSIZE;
+    i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD;
+    i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE;
+    
+    switch (req->sampleSize) {
+    case MXC_I2S_SAMPLESIZE_EIGHT:
+        if (req->wordSize == MXC_I2S_DATASIZE_WORD) {
+            //Set word length
+            i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        }
+        else if (req->wordSize == MXC_I2S_DATASIZE_HALFWORD) {
+            //Set word length
+            i2s->ctrl1ch0 |= (DATALENGTH_SIXTEEN << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        }
+        else {
+            //Set word length
+            i2s->ctrl1ch0 |= (DATALENGTH_EIGHT << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        }
+        
+        //Set sample length
+        i2s->ctrl1ch0 |= (DATALENGTH_EIGHT << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS);
+        
+        //Set datasize to load in FIFO
+        MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_BYTE) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS);
+        
+        dataMask =  0x000000ff;
+        
+        if ((req->rawData != NULL) && (req->txData != NULL)) {
+            for (uint32_t i = 0; i < req->length ; i++) {
+                *txdata_8++ = *rawdata_8++ & dataMask;
+            }
+        }
+        
+        break;
+        
+    case MXC_I2S_SAMPLESIZE_SIXTEEN:
+        if (req->wordSize == MXC_I2S_DATASIZE_WORD) {
+            //Set word length
+            i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        }
+        else {
+            //Set word length
+            i2s->ctrl1ch0 |= (DATALENGTH_SIXTEEN << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        }
+        
+        //Set sample length
+        i2s->ctrl1ch0 |= (DATALENGTH_SIXTEEN << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS);
+        
+        //Set datasize
+        MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_HALFWORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS);
+        
+        dataMask = 0x0000ffff;
+        
+        if ((req->rawData != NULL) && (req->txData != NULL)) {
+            for (uint32_t i = 0; i < req->length ; i++) {
+                *txdata_16++ = *rawdata_16++ & dataMask;
+            }
+        }
+        
+        break;
+        
+    case MXC_I2S_SAMPLESIZE_TWENTY:
+        //Set word length
+        i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        
+        //Set sample length
+        i2s->ctrl1ch0 |= (DATALENGTH_TWENTY << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS);
+        
+        //Set datasize
+        MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS);
+        
+        dataMask = 0x00fffff;
+        
+        if ((req->rawData != NULL) && (req->txData != NULL)) {
+            for (uint32_t i = 0; i < req->length ; i++) {
+                *txdata_32++ = (*rawdata_32++ & dataMask) << 12;
+            }
+        }
+        
+        break;
+        
+    case MXC_I2S_SAMPLESIZE_TWENTYFOUR:
+        //Set word length
+        i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        
+        //Set sample length
+        i2s->ctrl1ch0 |= (DATALENGTH_TWENTYFOUR << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS);
+        
+        //Set datasize
+        MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS);
+        
+        dataMask = 0x00ffffff;
+        
+        if ((req->rawData != NULL) && (req->txData != NULL)) {
+            for (uint32_t i = 0; i < req->length ; i++) {
+                *txdata_32++ = (*rawdata_32++ & dataMask) << 8;
+            }
+        }
+        
+        break;
+        
+    case MXC_I2S_SAMPLESIZE_THIRTYTWO:
+        //Set word length
+        i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS);
+        
+        //Set sample length
+        i2s->ctrl1ch0 |= (DATALENGTH_THIRTYTWO << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS);
+        
+        //Set datasize
+        MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, (MXC_I2S_DATASIZE_WORD) << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS);
+        
+        dataMask = 0xffffffff;
+        
+        if ((req->rawData != NULL) && (req->txData != NULL)) {
+            for (uint32_t i = 0; i < req->length ; i++) {
+                *txdata_32++ = *rawdata_32++ & dataMask;
+            }
+        }
+        
+        break;
+        
+    default:
+        return E_BAD_PARAM;
+        break;
+    }
+    
+    return E_NO_ERROR;
+}
+
+void MXC_I2S_RevA_TXEnable(mxc_i2s_reva_regs_t *i2s)
+{
+    MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, 1 << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS);
+}
+
+void MXC_I2S_RevA_TXDisable(mxc_i2s_reva_regs_t *i2s)
+{
+    MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, 0 << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS);
+}
+
+void MXC_I2S_RevA_RXEnable(mxc_i2s_reva_regs_t *i2s)
+{
+    MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, 1 << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS);
+}
+
+void MXC_I2S_RevA_RXDisable(mxc_i2s_reva_regs_t *i2s)
+{
+    MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, 0 << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS);
+}
+
+int MXC_I2S_RevA_SetRXThreshold(mxc_i2s_reva_regs_t *i2s, uint8_t threshold)
+{
+    if ((threshold == 0) || (threshold > 8)) {
+        return E_NOT_SUPPORTED;
+    }
+    
+    i2s->ctrl0ch0 |= (threshold << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS);
+    
+    return E_NO_ERROR;
+}
+
+int MXC_I2S_RevA_SetFrequency(mxc_i2s_reva_regs_t *i2s, mxc_i2s_ch_mode_t mode, uint16_t clkdiv)
+{
+    i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN;
+    
+    MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_CH_MODE, (mode) << MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS);
+    
+    i2s->ctrl1ch0 |= ((uint32_t) clkdiv) << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS;
+    
+    i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN;
+    
+    return E_NO_ERROR;
+}
+
+void MXC_I2S_RevA_Flush(mxc_i2s_reva_regs_t *i2s)
+{
+    i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_FLUSH;
+    
+    while (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_FLUSH);
+}
+
+void MXC_I2S_RevA_EnableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags)
+{
+    i2s->inten |= flags;
+}
+
+void MXC_I2S_RevA_DisableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags)
+{
+    i2s->inten &= ~flags;
+}
+
+int MXC_I2S_RevA_GetFlags(mxc_i2s_reva_regs_t *i2s)
+{
+    return (i2s->intfl & 0xF);
+}
+
+void MXC_I2S_RevA_ClearFlags(mxc_i2s_reva_regs_t *i2s, uint32_t flags)
+{
+    i2s->intfl |= flags;
+}
+
+void MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void* src_addr, int len)
+{
+    uint8_t channel;
+    mxc_dma_config_t config;
+    mxc_dma_adv_config_t advConfig;
+    mxc_dma_srcdst_t srcdst;
+    
+    MXC_DMA_Init();
+    
+    i2s->dmach0 |= (2 << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS);     //TX DMA Threshold
+    
+    channel = MXC_DMA_AcquireChannel();
+    
+    config.reqsel = MXC_DMA_REQUEST_I2STX;
+    
+    config.ch = channel;
+    
+    switch(request->wordSize) {
+    case MXC_I2S_DATASIZE_WORD:
+        config.srcwd = MXC_DMA_WIDTH_WORD;
+        config.dstwd = MXC_DMA_WIDTH_WORD;
+        advConfig.burst_size = 4;
+        break;
+
+    case MXC_I2S_DATASIZE_HALFWORD:
+        config.srcwd = MXC_DMA_WIDTH_HALFWORD;
+        config.dstwd = MXC_DMA_WIDTH_HALFWORD;
+        advConfig.burst_size = 2;
+        break;
+
+    case MXC_I2S_DATASIZE_BYTE:
+        config.srcwd = MXC_DMA_WIDTH_BYTE;
+        config.dstwd = MXC_DMA_WIDTH_BYTE;
+        advConfig.burst_size = 1;
+        break;
+
+    default:
+        config.srcwd = MXC_DMA_WIDTH_BYTE;
+        config.dstwd = MXC_DMA_WIDTH_BYTE;
+        advConfig.burst_size = 1;
+        break;
+    }
+    
+    config.srcinc_en = 1;
+    config.dstinc_en = 0;
+    
+    advConfig.ch = channel;
+    advConfig.prio = 0;
+    advConfig.reqwait_en = 0;
+    advConfig.tosel = 0;
+    advConfig.pssel = 0;
+
+    srcdst.ch = channel;
+    srcdst.source = src_addr;
+    srcdst.len = len;
+    
+    MXC_DMA_ConfigChannel(config, srcdst);
+    MXC_DMA_AdvConfigChannel(advConfig);
+    MXC_DMA_SetCallback(channel, dma_cb);
+    
+    MXC_I2S_TXEnable();                                 //Enable I2S TX
+    i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_TX_EN;      //Enable I2S DMA
+    
+    MXC_DMA_EnableInt(channel);
+    MXC_DMA_Start(channel);
+    MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;
+}
+
+void MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void* dest_addr, int len)
+{
+    uint8_t channel;
+    mxc_dma_config_t config;
+    mxc_dma_adv_config_t advConfig;
+    mxc_dma_srcdst_t srcdst;
+    
+    MXC_DMA_Init();
+    
+    i2s->dmach0 |= (6 << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS);     //RX DMA Threshold
+    
+    channel = MXC_DMA_AcquireChannel();
+    
+    config.reqsel = MXC_DMA_REQUEST_I2SRX;
+    
+    config.ch = channel;
+    
+    switch(request->wordSize) {
+    case MXC_I2S_DATASIZE_WORD:
+        config.srcwd = MXC_DMA_WIDTH_WORD;
+        config.dstwd = MXC_DMA_WIDTH_WORD;
+        advConfig.burst_size = 4;
+        break;
+
+    case MXC_I2S_DATASIZE_HALFWORD:
+        config.srcwd = MXC_DMA_WIDTH_HALFWORD;
+        config.dstwd = MXC_DMA_WIDTH_HALFWORD;
+        advConfig.burst_size = 2;
+        break;
+
+    case MXC_I2S_DATASIZE_BYTE:
+        config.srcwd = MXC_DMA_WIDTH_BYTE;
+        config.dstwd = MXC_DMA_WIDTH_BYTE;
+        advConfig.burst_size = 1;
+        break;
+
+    default:
+        config.srcwd = MXC_DMA_WIDTH_BYTE;
+        config.dstwd = MXC_DMA_WIDTH_BYTE;
+        advConfig.burst_size = 1;
+        break;
+    }
+    
+    config.srcinc_en = 0;
+    config.dstinc_en = 1;
+
+    advConfig.ch = channel;
+    advConfig.prio = 0;
+    advConfig.reqwait_en = 0;
+    advConfig.tosel = 0;
+    advConfig.pssel = 0;
+    
+    srcdst.ch = channel;
+    srcdst.dest = dest_addr;
+    srcdst.len = len;
+    
+    MXC_DMA_ConfigChannel(config, srcdst);
+    MXC_DMA_AdvConfigChannel(advConfig);
+    MXC_DMA_SetCallback(channel, dma_cb);
+    
+    MXC_I2S_RXEnable();                                 //Enable I2S RX
+    i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_RX_EN;      //Enable I2S DMA
+    
+    MXC_DMA_EnableInt(channel);
+    MXC_DMA_Start(channel);
+    MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE;
+}
+
+void MXC_I2S_RevA_RegisterDMACallback(void(*callback)(int, int))
+{
+    dma_cb = callback;
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva.h

@@ -0,0 +1,83 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <stdio.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "dma.h"
+#include "i2s_regs.h"
+#include "i2s.h"
+#include "i2s_reva_regs.h"
+
+
+/* **** Functions **** */
+
+int MXC_I2S_RevA_Init(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req);
+
+int MXC_I2S_RevA_Shutdown(mxc_i2s_reva_regs_t *i2s);
+
+int MXC_I2S_RevA_ConfigData(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req);
+
+void MXC_I2S_RevA_TXEnable(mxc_i2s_reva_regs_t *i2s);
+
+void MXC_I2S_RevA_TXDisable(mxc_i2s_reva_regs_t *i2s);
+
+void MXC_I2S_RevA_RXEnable(mxc_i2s_reva_regs_t *i2s);
+
+void MXC_I2S_RevA_RXDisable(mxc_i2s_reva_regs_t *i2s);
+
+int MXC_I2S_RevA_SetRXThreshold(mxc_i2s_reva_regs_t *i2s, uint8_t threshold);
+
+int MXC_I2S_RevA_SetFrequency(mxc_i2s_reva_regs_t *i2s, mxc_i2s_ch_mode_t mode, uint16_t clkdiv);
+
+void MXC_I2S_RevA_Flush(mxc_i2s_reva_regs_t *i2s);
+
+void MXC_I2S_RevA_EnableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags);
+
+void MXC_I2S_RevA_DisableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags);
+
+int MXC_I2S_RevA_GetFlags(mxc_i2s_reva_regs_t *i2s);
+
+void MXC_I2S_RevA_ClearFlags(mxc_i2s_reva_regs_t *i2s, uint32_t flags);
+
+void MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *src_addr, int len);
+
+void MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *dest_addr, int len);
+
+void MXC_I2S_RevA_RegisterDMACallback(void(*callback)(int, int));

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2S/i2s_reva_regs.h

@@ -0,0 +1,283 @@
+/**
+ * @file    i2s_reva_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the I2S_REVA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _I2S_REVA_REGS_H_
+#define _I2S_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     i2s_reva
+ * @defgroup    i2s_reva_registers I2S_REVA_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the I2S_REVA Peripheral Module.
+ * @details Inter-IC Sound Interface.
+ */
+
+/**
+ * @ingroup i2s_reva_registers
+ * Structure type to access the I2S_REVA Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl0ch0;             /**< <tt>\b 0x00:</tt> I2S_REVA CTRL0CH0 Register */
+    __R  uint32_t rsv_0x4_0xf[3];
+    __IO uint32_t ctrl1ch0;             /**< <tt>\b 0x10:</tt> I2S_REVA CTRL1CH0 Register */
+    __R  uint32_t rsv_0x14_0x2f[7];
+    __IO uint32_t dmach0;               /**< <tt>\b 0x30:</tt> I2S_REVA DMACH0 Register */
+    __R  uint32_t rsv_0x34_0x3f[3];
+    __IO uint32_t fifoch0;              /**< <tt>\b 0x40:</tt> I2S_REVA FIFOCH0 Register */
+    __R  uint32_t rsv_0x44_0x4f[3];
+    __IO uint32_t intfl;                /**< <tt>\b 0x50:</tt> I2S_REVA INTFL Register */
+    __IO uint32_t inten;                /**< <tt>\b 0x54:</tt> I2S_REVA INTEN Register */
+    __IO uint32_t extsetup;             /**< <tt>\b 0x58:</tt> I2S_REVA EXTSETUP Register */
+} mxc_i2s_reva_regs_t;
+
+/* Register offsets for module I2S_REVA */
+/**
+ * @ingroup    i2s_reva_registers
+ * @defgroup   I2S_REVA_Register_Offsets Register Offsets
+ * @brief      I2S_REVA Peripheral Register Offsets from the I2S_REVA Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_I2S_REVA_CTRL0CH0            ((uint32_t)0x00000000UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_I2S_REVA_CTRL1CH0            ((uint32_t)0x00000010UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_I2S_REVA_DMACH0              ((uint32_t)0x00000030UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_I2S_REVA_FIFOCH0             ((uint32_t)0x00000040UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_I2S_REVA_INTFL               ((uint32_t)0x00000050UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0050</tt> */ 
+ #define MXC_R_I2S_REVA_INTEN               ((uint32_t)0x00000054UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0054</tt> */ 
+ #define MXC_R_I2S_REVA_EXTSETUP            ((uint32_t)0x00000058UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0058</tt> */ 
+/**@} end of group i2s_reva_registers */
+
+/**
+ * @ingroup  i2s_reva_registers
+ * @defgroup I2S_REVA_CTRL0CH0 I2S_REVA_CTRL0CH0
+ * @brief    Global mode channel.
+ * @{
+ */
+ #define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS          1 /**< CTRL0CH0_LSB_FIRST Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST              ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS            6 /**< CTRL0CH0_CH_MODE Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE                ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS             8 /**< CTRL0CH0_WS_POL Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_WS_POL                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS            9 /**< CTRL0CH0_MSB_LOC Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC                ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS              10 /**< CTRL0CH0_ALIGN Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_ALIGN                  ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS            11 /**< CTRL0CH0_EXT_SEL Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL                ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS             12 /**< CTRL0CH0_STEREO Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_STEREO                 ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS              14 /**< CTRL0CH0_WSIZE Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_WSIZE                  ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS              16 /**< CTRL0CH0_TX_EN Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_TX_EN                  ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS              17 /**< CTRL0CH0_RX_EN Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_RX_EN                  ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS              18 /**< CTRL0CH0_FLUSH Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_FLUSH                  ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_RST_POS                19 /**< CTRL0CH0_RST Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_RST                    ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS           19 /**< CTRL0CH0_FIFO_LSB Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB               ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */
+
+ #define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS         24 /**< CTRL0CH0_RX_THD_VAL Position */
+ #define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL             ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */
+
+/**@} end of group I2S_REVA_CTRL0CH0_Register */
+
+/**
+ * @ingroup  i2s_reva_registers
+ * @defgroup I2S_REVA_CTRL1CH0 I2S_REVA_CTRL1CH0
+ * @brief    Local channel Setup.
+ * @{
+ */
+ #define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS          0 /**< CTRL1CH0_BITS_WORD Position */
+ #define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD              ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */
+
+ #define MXC_F_I2S_REVA_CTRL1CH0_EN_POS                 8 /**< CTRL1CH0_EN Position */
+ #define MXC_F_I2S_REVA_CTRL1CH0_EN                     ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */
+
+ #define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS           9 /**< CTRL1CH0_SMP_SIZE Position */
+ #define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE               ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */
+
+ #define MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS             15 /**< CTRL1CH0_ADJUST Position */
+ #define MXC_F_I2S_REVA_CTRL1CH0_ADJUST                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */
+
+ #define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS             16 /**< CTRL1CH0_CLKDIV Position */
+ #define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV                 ((uint32_t)(0xFFFFUL << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */
+
+/**@} end of group I2S_REVA_CTRL1CH0_Register */
+
+/**
+ * @ingroup  i2s_reva_registers
+ * @defgroup I2S_REVA_DMACH0 I2S_REVA_DMACH0
+ * @brief    DMA Control.
+ * @{
+ */
+ #define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS       0 /**< DMACH0_DMA_TX_THD_VAL Position */
+ #define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL           ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */
+
+ #define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS            7 /**< DMACH0_DMA_TX_EN Position */
+ #define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN                ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */
+
+ #define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS       8 /**< DMACH0_DMA_RX_THD_VAL Position */
+ #define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL           ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */
+
+ #define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS            15 /**< DMACH0_DMA_RX_EN Position */
+ #define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN                ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */
+
+ #define MXC_F_I2S_REVA_DMACH0_TX_LVL_POS               16 /**< DMACH0_TX_LVL Position */
+ #define MXC_F_I2S_REVA_DMACH0_TX_LVL                   ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */
+
+ #define MXC_F_I2S_REVA_DMACH0_RX_LVL_POS               24 /**< DMACH0_RX_LVL Position */
+ #define MXC_F_I2S_REVA_DMACH0_RX_LVL                   ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */
+
+/**@} end of group I2S_REVA_DMACH0_Register */
+
+/**
+ * @ingroup  i2s_reva_registers
+ * @defgroup I2S_REVA_FIFOCH0 I2S_REVA_FIFOCH0
+ * @brief    I2S Fifo.
+ * @{
+ */
+ #define MXC_F_I2S_REVA_FIFOCH0_DATA_POS                0 /**< FIFOCH0_DATA Position */
+ #define MXC_F_I2S_REVA_FIFOCH0_DATA                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_REVA_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */
+
+/**@} end of group I2S_REVA_FIFOCH0_Register */
+
+/**
+ * @ingroup  i2s_reva_registers
+ * @defgroup I2S_REVA_INTFL I2S_REVA_INTFL
+ * @brief    ISR Status.
+ * @{
+ */
+ #define MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS             0 /**< INTFL_RX_OV_CH0 Position */
+ #define MXC_F_I2S_REVA_INTFL_RX_OV_CH0                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */
+
+ #define MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS            1 /**< INTFL_RX_THD_CH0 Position */
+ #define MXC_F_I2S_REVA_INTFL_RX_THD_CH0                ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */
+
+ #define MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS             2 /**< INTFL_TX_OB_CH0 Position */
+ #define MXC_F_I2S_REVA_INTFL_TX_OB_CH0                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */
+
+ #define MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS             3 /**< INTFL_TX_HE_CH0 Position */
+ #define MXC_F_I2S_REVA_INTFL_TX_HE_CH0                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */
+
+/**@} end of group I2S_REVA_INTFL_Register */
+
+/**
+ * @ingroup  i2s_reva_registers
+ * @defgroup I2S_REVA_INTEN I2S_REVA_INTEN
+ * @brief    Interrupt Enable.
+ * @{
+ */
+ #define MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS             0 /**< INTEN_RX_OV_CH0 Position */
+ #define MXC_F_I2S_REVA_INTEN_RX_OV_CH0                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */
+
+ #define MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS            1 /**< INTEN_RX_THD_CH0 Position */
+ #define MXC_F_I2S_REVA_INTEN_RX_THD_CH0                ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */
+
+ #define MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS             2 /**< INTEN_TX_OB_CH0 Position */
+ #define MXC_F_I2S_REVA_INTEN_TX_OB_CH0                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */
+
+ #define MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS             3 /**< INTEN_TX_HE_CH0 Position */
+ #define MXC_F_I2S_REVA_INTEN_TX_HE_CH0                 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */
+
+/**@} end of group I2S_REVA_INTEN_Register */
+
+/**
+ * @ingroup  i2s_reva_registers
+ * @defgroup I2S_REVA_EXTSETUP I2S_REVA_EXTSETUP
+ * @brief    Ext Control.
+ * @{
+ */
+ #define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS      0 /**< EXTSETUP_EXT_BITS_WORD Position */
+ #define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD          ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */
+
+/**@} end of group I2S_REVA_EXTSETUP_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2S_REVA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.c

@@ -0,0 +1,46 @@
+/* *****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "icc.h"
+#include "icc_reva.h"
+
+void MXC_ICC_Com_Flush(void)
+{
+    MXC_ICC_Disable();
+    MXC_ICC_Enable();
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_common.h

@@ -0,0 +1,50 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   Flush the instruction cache controller.
+ */
+void MXC_ICC_Com_Flush(void);
+
+/**@} end of group icc */
+
+#ifdef __cplusplus
+}
+#endif

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_me15.c

@@ -0,0 +1,63 @@
+/* *****************************************************************************
+ * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "icc.h"
+#include "icc_reva.h"
+#include "icc_common.h"
+
+/* **** Functions **** */
+
+int MXC_ICC_ID(mxc_icc_info_t cid)
+{
+    return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t*) MXC_ICC, cid);
+}
+
+void MXC_ICC_Enable(void)
+{
+    MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t*) MXC_ICC);
+}
+
+void MXC_ICC_Disable(void)
+{
+    MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t*) MXC_ICC);
+}
+
+void MXC_ICC_Flush(void)
+{
+    MXC_ICC_Com_Flush();
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.c

@@ -0,0 +1,91 @@
+/* *****************************************************************************
+ * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "icc.h"
+#include "icc_reva_regs.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+static int MXC_ICC_Ready(mxc_icc_reva_regs_t* icc)
+{
+    return (icc->ctrl & MXC_F_ICC_REVA_CTRL_RDY);
+}
+
+int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid)
+{
+    if(icc == NULL) {
+        return E_NULL_PTR;
+    }
+
+    switch(cid) {
+    case ICC_INFO_RELNUM:
+        return ((icc->info & MXC_F_ICC_REVA_INFO_RELNUM) >> MXC_F_ICC_REVA_INFO_RELNUM_POS);
+        
+    case ICC_INFO_PARTNUM:
+        return ((icc->info & MXC_F_ICC_REVA_INFO_PARTNUM) >> MXC_F_ICC_REVA_INFO_PARTNUM_POS);
+        
+    case ICC_INFO_ID:
+        return ((icc->info & MXC_F_ICC_REVA_INFO_ID) >> MXC_F_ICC_REVA_INFO_ID_POS);
+        
+    default:
+        return E_BAD_PARAM;
+    }
+}
+
+void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc)
+{
+    // Invalidate cache and wait until ready
+    icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN;
+    icc->invalidate = 1;
+    
+    while(!(MXC_ICC_Ready(icc)));
+    
+    // Enable Cache
+    icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN;
+    while(!(MXC_ICC_Ready(icc)));
+}
+
+void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t* icc)
+{
+    // Disable Cache
+    icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN;
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva.h

@@ -0,0 +1,50 @@
+/* *****************************************************************************
+ * Copyright (C); 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software");,
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "icc.h"
+#include "icc_reva_regs.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+int MXC_ICC_RevA_ID (mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid);
+void MXC_ICC_RevA_Enable (mxc_icc_reva_regs_t* icc);
+void MXC_ICC_RevA_Disable (mxc_icc_reva_regs_t* icc);

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h

@@ -0,0 +1,159 @@
+/**
+ * @file    icc_reva_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _ICC_REVA_REGS_H_
+#define _ICC_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     icc_reva
+ * @defgroup    icc_reva_registers ICC_REVA_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module.
+ * @details Instruction Cache Controller Registers
+ */
+
+/**
+ * @ingroup icc_reva_registers
+ * Structure type to access the ICC_REVA Registers.
+ */
+typedef struct {
+    __I  uint32_t info;                 /**< <tt>\b 0x0000:</tt> ICC_REVA INFO Register */
+    __I  uint32_t sz;                   /**< <tt>\b 0x0004:</tt> ICC_REVA SZ Register */
+    __R  uint32_t rsv_0x8_0xff[62];
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x0100:</tt> ICC_REVA CTRL Register */
+    __R  uint32_t rsv_0x104_0x6ff[383];
+    __IO uint32_t invalidate;           /**< <tt>\b 0x0700:</tt> ICC_REVA INVALIDATE Register */
+} mxc_icc_reva_regs_t;
+
+/* Register offsets for module ICC_REVA */
+/**
+ * @ingroup    icc_reva_registers
+ * @defgroup   ICC_REVA_Register_Offsets Register Offsets
+ * @brief      ICC_REVA Peripheral Register Offsets from the ICC_REVA Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_ICC_REVA_INFO                ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_ICC_REVA_SZ                  ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_ICC_REVA_CTRL                ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0100</tt> */ 
+ #define MXC_R_ICC_REVA_INVALIDATE          ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: <tt> 0x0700</tt> */ 
+/**@} end of group icc_reva_registers */
+
+/**
+ * @ingroup  icc_reva_registers
+ * @defgroup ICC_REVA_INFO ICC_REVA_INFO
+ * @brief    Cache ID Register.
+ * @{
+ */
+ #define MXC_F_ICC_REVA_INFO_RELNUM_POS                 0 /**< INFO_RELNUM Position */
+ #define MXC_F_ICC_REVA_INFO_RELNUM                     ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */
+
+ #define MXC_F_ICC_REVA_INFO_PARTNUM_POS                6 /**< INFO_PARTNUM Position */
+ #define MXC_F_ICC_REVA_INFO_PARTNUM                    ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */
+
+ #define MXC_F_ICC_REVA_INFO_ID_POS                     10 /**< INFO_ID Position */
+ #define MXC_F_ICC_REVA_INFO_ID                         ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */
+
+/**@} end of group ICC_REVA_INFO_Register */
+
+/**
+ * @ingroup  icc_reva_registers
+ * @defgroup ICC_REVA_SZ ICC_REVA_SZ
+ * @brief    Memory Configuration Register.
+ * @{
+ */
+ #define MXC_F_ICC_REVA_SZ_CCH_POS                      0 /**< SZ_CCH Position */
+ #define MXC_F_ICC_REVA_SZ_CCH                          ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */
+
+ #define MXC_F_ICC_REVA_SZ_MEM_POS                      16 /**< SZ_MEM Position */
+ #define MXC_F_ICC_REVA_SZ_MEM                          ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */
+
+/**@} end of group ICC_REVA_SZ_Register */
+
+/**
+ * @ingroup  icc_reva_registers
+ * @defgroup ICC_REVA_CTRL ICC_REVA_CTRL
+ * @brief    Cache Control and Status Register.
+ * @{
+ */
+ #define MXC_F_ICC_REVA_CTRL_EN_POS                     0 /**< CTRL_EN Position */
+ #define MXC_F_ICC_REVA_CTRL_EN                         ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_ICC_REVA_CTRL_RDY_POS                    16 /**< CTRL_RDY Position */
+ #define MXC_F_ICC_REVA_CTRL_RDY                        ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
+
+/**@} end of group ICC_REVA_CTRL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICC_REVA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/LP/lp_me15.c

@@ -0,0 +1,355 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "gcr_regs.h"
+#include "lp.h"
+
+void MXC_LP_EnterSleepMode(void)
+{
+    MXC_LP_ClearWakeStatus();
+    
+    // set block detect bit
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS;
+    
+    // Clear SLEEPDEEP bit
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    
+    // Go into Sleep mode and wait for an interrupt to wake the processor
+    __WFI();
+}
+
+void MXC_LP_EnterDeepSleepMode(void)
+{
+    MXC_LP_ClearWakeStatus();
+    
+    // set block detect bit
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS;
+    
+    // Set SLEEPDEEP bit
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+    
+    // Go into Deepsleep mode and wait for an interrupt to wake the processor
+    __WFI();
+}
+
+void MXC_LP_EnterBackupMode(void)
+{
+    MXC_LP_ClearWakeStatus();
+    
+    // set block detect bit
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS;
+    
+    MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
+    MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
+    
+    while (1); // Should never reach this line - device will jump to backup vector on exit from background mode.
+}
+
+void MXC_LP_EnterStorageMode(void)
+{
+    MXC_LP_ClearWakeStatus();
+    /*set block detect bit */
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS;
+    
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_STORAGE_EN;
+    MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
+    MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
+    
+    while (1); // Should never reach this line - device will jump to backup vector on exit from background mode.
+}
+
+void MXC_LP_EnterShutDownMode(void)
+{
+    MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
+    MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN;
+    
+    while (1); // Should never reach this line - device will reset on exit from shutdown mode.
+}
+
+void MXC_LP_SetOVR(mxc_lp_ovr_t ovr)
+{
+    //not supported yet
+}
+
+void MXC_LP_RetentionRegEnable(void)
+{
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_RETREG_EN;
+}
+
+void MXC_LP_RetentionRegDisable(void)
+{
+    MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_RETREG_EN;
+}
+
+int  MXC_LP_RetentionRegIsEnabled(void)
+{
+    return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_RETREG_EN);
+}
+
+void MXC_LP_BandgapOn(void)
+{
+    MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_BG_DIS;
+}
+
+void MXC_LP_BandgapOff(void)
+{
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_BG_DIS;
+}
+
+int MXC_LP_BandgapIsOn(void)
+{
+    return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_BG_DIS);
+}
+
+void MXC_LP_PORVCOREoreMonitorEnable(void)
+{
+    MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS;
+}
+
+void MXC_LP_PORVCOREoreMonitorDisable(void)
+{
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS;
+}
+
+int MXC_LP_PORVCOREoreMonitorIsEnabled(void)
+{
+    return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS);
+}
+
+void MXC_LP_LDOEnable(void)
+{
+    MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_LDO_DIS;
+}
+
+void MXC_LP_LDODisable(void)
+{
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_LDO_DIS;
+}
+
+int  MXC_LP_LDOIsEnabled(void)
+{
+    return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_LDO_DIS);
+}
+
+void MXC_LP_FastWakeupEnable(void)
+{
+    MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_FASTWK_EN;
+}
+
+void MXC_LP_FastWakeupDisable(void)
+{
+    MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_FASTWK_EN;
+}
+
+int  MXC_LP_FastWakeupIsEnabled(void)
+{
+    return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_FASTWK_EN);
+}
+
+void MXC_LP_ClearWakeStatus(void)
+{
+    // Write 1 to clear
+    MXC_PWRSEQ->lpwkst0 = 0xFFFFFFFF;
+    MXC_PWRSEQ->lpwkst1 = 0xFFFFFFFF;
+    MXC_PWRSEQ->lppwkst  = 0xFFFFFFFF;
+}
+
+void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask)
+{
+    MXC_GCR->pm |= MXC_F_GCR_PM_GPIO_WE;
+    
+    switch (1 << port) {
+    case MXC_GPIO_PORT_0:
+        MXC_PWRSEQ->lpwken0 |= mask;
+        break;
+        
+    case MXC_GPIO_PORT_1:
+        MXC_PWRSEQ->lpwken1 |= mask;
+        break;
+    }
+}
+
+void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask)
+{
+    switch (1 << port) {
+    case MXC_GPIO_PORT_0:
+        MXC_PWRSEQ->lpwken0 &= ~mask;
+        break;
+        
+    case MXC_GPIO_PORT_1:
+        MXC_PWRSEQ->lpwken1 &= ~mask;
+        break;
+    }
+    
+    if (MXC_PWRSEQ->lpwken1 == 0 && MXC_PWRSEQ->lpwken0 == 0) {
+        MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIO_WE;
+    }
+}
+
+void MXC_LP_EnableRTCAlarmWakeup(void)
+{
+    MXC_GCR->pm |= MXC_F_GCR_PM_RTC_WE;
+}
+
+void MXC_LP_DisableRTCAlarmWakeup(void)
+{
+    MXC_GCR->pm &= ~MXC_F_GCR_PM_RTC_WE;
+}
+
+void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t* tmr)
+{
+    MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3);
+
+    if(tmr == MXC_TMR4) {
+        MXC_PWRSEQ->lppwken  |= MXC_F_PWRSEQ_LPPWKEN_LPTMR0;
+    }
+    else {
+        MXC_PWRSEQ->lppwken  |= MXC_F_PWRSEQ_LPPWKEN_LPTMR1;
+    }
+}
+
+void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t* tmr)
+{
+    MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3);
+
+    if(tmr == MXC_TMR4) {
+        MXC_PWRSEQ->lppwken  &= ~MXC_F_PWRSEQ_LPPWKEN_LPTMR0;
+    }
+    else {
+        MXC_PWRSEQ->lppwken  &= ~MXC_F_PWRSEQ_LPPWKEN_LPTMR1;
+    }
+}
+
+int MXC_LP_ConfigDeepSleepClocks(uint32_t mask)
+{
+    if (!(mask & (MXC_F_GCR_PM_IBRO_PD | MXC_F_GCR_PM_IPO_PD
+                  | MXC_F_GCR_PM_ERFO_PD))) {
+        return E_BAD_PARAM;
+    }
+    
+    MXC_GCR->pm |= mask;
+    return E_NO_ERROR;
+}
+
+void MXC_LP_SysRam0LightSleepEnable(void)
+{
+    MXC_GCR->memctrl |= MXC_F_GCR_MEMCTRL_RAM0LS_EN;
+}
+
+void MXC_LP_SysRam1LightSleepEnable(void)
+{
+    MXC_GCR->memctrl |= MXC_F_GCR_MEMCTRL_RAM1LS_EN;
+}
+
+void MXC_LP_SysRam2LightSleepEnable(void)
+{
+    MXC_GCR->memctrl |= MXC_F_GCR_MEMCTRL_RAM2LS_EN;
+}
+
+void MXC_LP_SysRam3LightSleepEnable(void)
+{
+    MXC_GCR->memctrl |= MXC_F_GCR_MEMCTRL_RAM3LS_EN;
+}
+
+void MXC_LP_ROMLightSleepEnable(void)
+{
+    MXC_GCR->memctrl |= MXC_F_GCR_MEMCTRL_ROMLS_EN;
+}
+
+void MXC_LP_SysRam0LightSleepDisable(void)
+{
+    MXC_GCR->memctrl &= ~MXC_F_GCR_MEMCTRL_RAM0LS_EN;
+}
+
+void MXC_LP_SysRam1LightSleepDisable(void)
+{
+    MXC_GCR->memctrl &= ~MXC_F_GCR_MEMCTRL_RAM1LS_EN;
+}
+
+void MXC_LP_SysRam2LightSleepDisable(void)
+{
+    MXC_GCR->memctrl &= ~MXC_F_GCR_MEMCTRL_RAM2LS_EN;
+}
+
+void MXC_LP_SysRam3LightSleepDisable(void)
+{
+    MXC_GCR->memctrl &= ~MXC_F_GCR_MEMCTRL_RAM3LS_EN;
+}
+
+void MXC_LP_ROMLightSleepDisable(void)
+{
+    MXC_GCR->memctrl &= ~MXC_F_GCR_MEMCTRL_RAM0LS_EN;
+}
+
+void MXC_LP_SysRam0Shutdown(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_RAM0;
+}
+
+void MXC_LP_SysRam0PowerUp(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_RAM0;
+}
+
+void MXC_LP_SysRam1Shutdown(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_RAM1;
+}
+
+void MXC_LP_SysRam1PowerUp(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_RAM1;
+}
+
+void MXC_LP_SysRam2Shutdown(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_RAM2;
+}
+
+void MXC_LP_SysRam2PowerUp(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_RAM2;
+}
+
+void MXC_LP_SysRam3Shutdown(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_RAM3;
+}
+
+void MXC_LP_SysRam3PowerUp(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_RAM3;
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_me15.c

@@ -0,0 +1,148 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+#include "mxc_device.h"
+#include "rtc_regs.h"
+#include "rtc.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "gpio_regs.h"
+#include "mxc_errors.h"
+#include "mcr_regs.h"
+#include "rtc_reva.h"
+
+/* ***** Functions ***** */
+
+int MXC_RTC_EnableInt(uint32_t mask)
+{
+    return MXC_RTC_RevA_EnableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask);
+}
+
+int MXC_RTC_DisableInt(uint32_t mask)
+{
+    return MXC_RTC_RevA_DisableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask);
+}
+
+int MXC_RTC_SetTimeofdayAlarm(uint32_t ras)
+{
+    return MXC_RTC_RevA_SetTimeofdayAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, ras);
+}
+
+int MXC_RTC_SetSubsecondAlarm(uint32_t rssa)
+{
+    return MXC_RTC_RevA_SetSubsecondAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, rssa);
+}
+
+int MXC_RTC_Start(void)
+{
+    return MXC_RTC_RevA_Start ((mxc_rtc_reva_regs_t*) MXC_RTC);
+}
+
+int MXC_RTC_Stop(void)
+{
+    return MXC_RTC_RevA_Stop ((mxc_rtc_reva_regs_t*) MXC_RTC);
+}
+
+int MXC_RTC_Init(uint32_t sec, uint8_t ssec)
+{
+    // Enable clock
+    MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN;
+    
+    return MXC_RTC_RevA_Init ((mxc_rtc_reva_regs_t*) MXC_RTC, sec, ssec);
+}
+
+int MXC_RTC_SquareWave (mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
+{
+  #if TARGET_NUM != 32675
+    MXC_GPIO_Config(&gpio_cfg_rtcsqw);
+    
+    return MXC_RTC_RevA_SquareWave ((mxc_rtc_reva_regs_t*) MXC_RTC, sqe, ft);
+  #else 
+    return E_NOT_SUPPORTED;
+  #endif
+}
+
+int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq)
+{
+  #if TARGET_NUM != 32675
+    MXC_GPIO_Config(&gpio_cfg_rtcsqw);
+    return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t*) MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED, fq);
+  #else 
+    return E_NOT_SUPPORTED;
+  #endif
+}
+
+int MXC_RTC_SquareWaveStop (void)
+{
+  #if TARGET_NUM != 32675    
+	return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t*) MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0);
+  #else 
+    return E_NOT_SUPPORTED;
+  #endif
+}
+
+
+int MXC_RTC_Trim(int8_t trm)
+{
+    return MXC_RTC_RevA_Trim ((mxc_rtc_reva_regs_t*) MXC_RTC, trm);
+}
+
+int MXC_RTC_GetFlags(void)
+{
+    return MXC_RTC_RevA_GetFlags();
+}
+
+int MXC_RTC_ClearFlags(int flags)
+{
+    return MXC_RTC_RevA_ClearFlags(flags);
+}
+
+int MXC_RTC_GetSubSecond(void)
+{
+    return MXC_RTC_RevA_GetSubSecond();
+}
+
+int MXC_RTC_GetSecond(void)
+{
+    return MXC_RTC_RevA_GetSecond();
+}
+
+int MXC_RTC_GetTime(uint32_t* sec, uint32_t* subsec)
+{
+    return MXC_RTC_RevA_GetTime(sec, subsec);
+}
+
+int MXC_RTC_GetBusyFlag(void)
+{
+    return MXC_RTC_RevA_GetBusyFlag();
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c

@@ -0,0 +1,353 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+#include <stddef.h>
+#include "mxc_device.h"
+#include "rtc.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "gpio_regs.h"
+#include "mxc_errors.h"
+#include "rtc_reva.h"
+
+#if TARGET_NUM == 32650
+    #include "pwrseq_regs.h"
+#endif
+
+void MXC_RTC_Wait_BusyToClear(void)
+{
+    while (MXC_RTC_REVA_IS_BUSY) {
+
+    }
+}
+
+int MXC_RTC_RevA_GetBusyFlag (void)
+{
+    if (MXC_RTC_REVA_IS_BUSY) {
+        return E_BUSY;
+    }
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
+{
+    mask &= (MXC_RTC_INT_EN_LONG |  MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
+    
+    if (!mask) {
+        /* No bits set? Wasn't something we can enable. */
+        return E_BAD_PARAM;
+    }
+	
+    MXC_RTC_Wait_BusyToClear();
+	
+    rtc->ctrl |= mask;
+	
+    /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/    
+    mask &= ~MXC_RTC_INT_EN_READY;
+
+    if (mask) {
+        MXC_RTC_Wait_BusyToClear();
+    }	
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask)
+{
+    mask &= (MXC_RTC_INT_EN_LONG |  MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY);
+    
+    if (!mask) {
+        /* No bits set? Wasn't something we can enable. */
+        return E_BAD_PARAM;
+    }
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl &= ~mask;
+    
+    /* If TOD and SSEC interrupt enable, check busy after CTRL register write*/    
+    mask &= ~MXC_RTC_INT_EN_READY;
+
+    if (mask) {
+        MXC_RTC_Wait_BusyToClear();
+    }	
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras)
+{
+    // ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0);
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+    
+    rtc->toda = (ras << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS) & MXC_F_RTC_REVA_TODA_TOD_ALARM;
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa)
+{
+    // ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0);
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+    
+    rtc->sseca = (rssa << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS) & MXC_F_RTC_REVA_SSECA_SSEC_ALARM;
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc)
+{
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+    
+    rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;       // Allow writing to registers
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    // Can only write if WE=1 and BUSY=0
+    rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN;    // setting RTCE = 1
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN;       // Prevent Writing...
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc)
+{
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+    
+    rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;      // Allow writing to registers
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    // Can only write if WE=1 and BUSY=0
+    rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN;  // setting RTCE = 0
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN;       // Prevent Writing...
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec)
+{
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+    
+    rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN;        //  Allow Writes
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT;  // Start with a Clean Register
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;      // Set Write Enable, allow writing to reg.
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ssec = ssec;
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->sec = sec;
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN;       // Prevent Writing...
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft)
+{
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+    
+    rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;   // Allow writing to registers
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    if (sqe == MXC_RTC_REVA_SQUARE_WAVE_ENABLED) {
+        if (ft == MXC_RTC_F_32KHZ) {       // if 32KHz output is selected...
+            rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K;   // Enable 32KHz wave
+            
+            MXC_RTC_Wait_BusyToClear();
+            
+            rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN;                  // Enable output on the pin
+        }
+        else {                    // if 1Hz, 512Hz, 4KHz output is selected
+        
+            rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K;  // Must make sure that the 32KHz is disabled
+            
+            MXC_RTC_Wait_BusyToClear();
+            
+            rtc->ctrl &= ~ MXC_F_RTC_REVA_CTRL_SQW_SEL;
+            
+            MXC_RTC_Wait_BusyToClear();
+            
+            rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft);  // Enable Sq. wave,
+        }
+        
+        MXC_RTC_Wait_BusyToClear();
+        
+        rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN;     // Enable Real Time Clock
+    }
+    else {   // Turn off the square wave output on the pin
+    
+        rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K;     // Must make sure that the 32KHz is disabled
+        
+        MXC_RTC_Wait_BusyToClear();
+        
+        rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN;  // No sq. wave output
+    }
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN;       // Disable Writing to register
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trim)
+{
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+    
+    rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN;
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    MXC_SETFIELD (rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS);
+    
+    MXC_RTC_Wait_BusyToClear();
+    
+    rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN;       // Disable Writing to register
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_GetFlags(void)
+{
+    return MXC_RTC->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY);
+}
+
+int MXC_RTC_RevA_ClearFlags(int flags)
+{    
+    MXC_RTC->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY));
+    
+    return E_SUCCESS;
+}
+
+int MXC_RTC_RevA_GetSubSecond(void)
+{
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+
+#if TARGET_NUM == 32650
+    int ssec;
+    if(ChipRevision > 0xA1){
+        ssec = ((MXC_PWRSEQ->ctrl >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF);
+    }else{
+        ssec = MXC_RTC->ssec;
+    }
+        return ssec;
+#else
+    return MXC_RTC->ssec;
+#endif
+}
+
+int MXC_RTC_RevA_GetSecond(void)
+{
+    if (MXC_RTC_RevA_GetBusyFlag()) {
+        return E_BUSY;
+    }
+	
+    return MXC_RTC->sec;
+}
+
+int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec)
+{
+    uint32_t temp_sec = 0;
+    
+    if (sec == NULL || subsec == NULL) {
+        return E_NULL_PTR;
+    }
+    
+    do {
+        // Check if an update is about to happen.
+        if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
+            return E_BUSY;
+        }
+        
+        // Read the seconds count.
+        temp_sec = MXC_RTC_RevA_GetSecond();
+
+        if ((int)temp_sec == E_BUSY) {
+            return E_BUSY;
+        }
+        
+        // Check if an update is about to happen.
+        if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
+            return E_BUSY;
+        }
+        
+        // Read the sub-seconds count.
+        *subsec = MXC_RTC_RevA_GetSubSecond();
+        
+        // Check if an update is about to happen.
+        if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) {
+            return E_BUSY;
+        }
+        
+        // Read the seconds count.
+        *sec = MXC_RTC_RevA_GetSecond();
+        
+        // Repeat until a steady state is reached.
+    }
+    while (temp_sec != *sec);
+    
+    return E_NO_ERROR;
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h

@@ -0,0 +1,67 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+#include "mxc_device.h"
+#include "rtc_reva_regs.h"
+#include "rtc.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "gpio.h"
+#include "mxc_errors.h"
+
+typedef enum {
+    MXC_RTC_REVA_SQUARE_WAVE_DISABLED, ///< Sq. wave output disabled
+    MXC_RTC_REVA_SQUARE_WAVE_ENABLED,  ///< Sq. wave output enabled
+} mxc_rtc_reva_sqwave_en_t;
+
+#define MXC_RTC_REVA_CTRL_RESET_DEFAULT (0x0000UL)
+#define MXC_RTC_REVA_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_BUSY)
+#define MXC_RTC_REVA_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RTCE)
+
+#define MXC_BUSY_TIMEOUT 1000   // Timeout counts for the Busy bit
+
+int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec);
+int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask);
+int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask);
+int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras);
+int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa);
+int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc);
+int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc);
+int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft);
+int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trm);
+int MXC_RTC_RevA_GetFlags (void);
+int MXC_RTC_RevA_ClearFlags (int flags);
+int MXC_RTC_RevA_GetSubSecond (void);
+int MXC_RTC_RevA_GetSecond (void);
+int MXC_RTC_RevA_GetTime (uint32_t* sec, uint32_t* subsec);
+int MXC_RTC_RevA_GetBusyFlag (void);

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h

@@ -0,0 +1,244 @@
+/**
+ * @file    rtc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _RTC_REVA_REGS_H_
+#define _RTC_REVA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     rtc
+ * @defgroup    rtc_registers RTC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
+ * @details Real Time Clock and Alarm.
+ */
+
+/**
+ * @ingroup rtc_registers
+ * Structure type to access the RTC Registers.
+ */
+typedef struct {
+    __IO uint32_t sec;                  /**< <tt>\b 0x00:</tt> RTC SEC Register */
+    __IO uint32_t ssec;                 /**< <tt>\b 0x04:</tt> RTC SSEC Register */
+    __IO uint32_t toda;                 /**< <tt>\b 0x08:</tt> RTC TODA Register */
+    __IO uint32_t sseca;                /**< <tt>\b 0x0C:</tt> RTC SSECA Register */
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x10:</tt> RTC CTRL Register */
+    __IO uint32_t trim;                 /**< <tt>\b 0x14:</tt> RTC TRIM Register */
+    __IO uint32_t oscctrl;              /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
+} mxc_rtc_reva_regs_t;
+
+/* Register offsets for module RTC */
+/**
+ * @ingroup    rtc_registers
+ * @defgroup   RTC_Register_Offsets Register Offsets
+ * @brief      RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_RTC_REVA_SEC                      ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
+ #define MXC_R_RTC_REVA_SSEC                     ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
+ #define MXC_R_RTC_REVA_TODA                     ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
+ #define MXC_R_RTC_REVA_SSECA                    ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
+ #define MXC_R_RTC_REVA_CTRL                     ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
+ #define MXC_R_RTC_REVA_TRIM                     ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
+ #define MXC_R_RTC_REVA_OSCCTRL                  ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
+/**@} end of group rtc_registers */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_SEC RTC_SEC
+ * @brief    RTC Second Counter. This register contains the 32-bit second counter.
+ * @{
+ */
+ #define MXC_F_RTC_REVA_SEC_SEC_POS                          0 /**< SEC_SEC Position */
+ #define MXC_F_RTC_REVA_SEC_SEC                              ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SEC_SEC_POS)) /**< SEC_SEC Mask */
+
+/**@} end of group RTC_SEC_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_SSEC RTC_SSEC
+ * @brief    RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented
+ *           when this register rolls over from 0xFF to 0x00.
+ * @{
+ */
+ #define MXC_F_RTC_REVA_SSEC_SSEC_POS                        0 /**< SSEC_SSEC Position */
+ #define MXC_F_RTC_REVA_SSEC_SSEC                            ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */
+
+/**@} end of group RTC_SSEC_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_TODA RTC_TODA
+ * @brief    Time-of-day Alarm.
+ * @{
+ */
+ #define MXC_F_RTC_REVA_TODA_TOD_ALARM_POS                   0 /**< TODA_TOD_ALARM Position */
+ #define MXC_F_RTC_REVA_TODA_TOD_ALARM                       ((uint32_t)(0xFFFFFUL << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */
+
+/**@} end of group RTC_TODA_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_SSECA RTC_SSECA
+ * @brief    RTC sub-second alarm.  This register contains the reload value for the sub-
+ *           second alarm.
+ * @{
+ */
+ #define MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS                 0 /**< SSECA_SSEC_ALARM Position */
+ #define MXC_F_RTC_REVA_SSECA_SSEC_ALARM                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */
+
+/**@} end of group RTC_SSECA_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_CTRL RTC_CTRL
+ * @brief    RTC Control Register.
+ * @{
+ */
+ #define MXC_F_RTC_REVA_CTRL_EN_POS                          0 /**< CTRL_EN Position */
+ #define MXC_F_RTC_REVA_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS                1 /**< CTRL_TOD_ALARM_IE Position */
+ #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE                    ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS               2 /**< CTRL_SSEC_ALARM_IE Position */
+ #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE                   ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_BUSY_POS                        3 /**< CTRL_BUSY Position */
+ #define MXC_F_RTC_REVA_CTRL_BUSY                            ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_RDY_POS                         4 /**< CTRL_RDY Position */
+ #define MXC_F_RTC_REVA_CTRL_RDY                             ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_RDY_IE_POS                      5 /**< CTRL_RDY_IE Position */
+ #define MXC_F_RTC_REVA_CTRL_RDY_IE                          ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS                   6 /**< CTRL_TOD_ALARM Position */
+ #define MXC_F_RTC_REVA_CTRL_TOD_ALARM                       ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS                  7 /**< CTRL_SSEC_ALARM Position */
+ #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM                      ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_SQW_EN_POS                      8 /**< CTRL_SQW_EN Position */
+ #define MXC_F_RTC_REVA_CTRL_SQW_EN                          ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_SQW_SEL_POS                     9 /**< CTRL_SQW_SEL Position */
+ #define MXC_F_RTC_REVA_CTRL_SQW_SEL                         ((uint32_t)(0x3UL << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */
+ #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ                 ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */
+ #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ                 (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */
+ #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ               ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */
+ #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ               (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */
+ #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ                ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */
+ #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ                (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */
+ #define MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8                 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */
+ #define MXC_S_RTC_REVA_CTRL_SQW_SEL_CLKDIV8                 (MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */
+
+ #define MXC_F_RTC_REVA_CTRL_RD_EN_POS                       14 /**< CTRL_RD_EN Position */
+ #define MXC_F_RTC_REVA_CTRL_RD_EN                           ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */
+
+ #define MXC_F_RTC_REVA_CTRL_WR_EN_POS                       15 /**< CTRL_WR_EN Position */
+ #define MXC_F_RTC_REVA_CTRL_WR_EN                           ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */
+
+/**@} end of group RTC_CTRL_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_TRIM RTC_TRIM
+ * @brief    RTC Trim Register.
+ * @{
+ */
+ #define MXC_F_RTC_REVA_TRIM_TRIM_POS                        0 /**< TRIM_TRIM Position */
+ #define MXC_F_RTC_REVA_TRIM_TRIM                            ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
+
+ #define MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS                    8 /**< TRIM_VRTC_TMR Position */
+ #define MXC_F_RTC_REVA_TRIM_VRTC_TMR                        ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */
+
+/**@} end of group RTC_TRIM_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_OSCCTRL RTC_OSCCTRL
+ * @brief    RTC Oscillator Control Register.
+ * @{
+ */
+ #define MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS                   4 /**< OSCCTRL_BYPASS Position */
+ #define MXC_F_RTC_REVA_OSCCTRL_BYPASS                       ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
+
+ #define MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS                  5 /**< OSCCTRL_SQW_32K Position */
+ #define MXC_F_RTC_REVA_OSCCTRL_SQW_32K                      ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */
+
+/**@} end of group RTC_OSCCTRL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTC_REVA_REGS_H_ */

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c

@@ -0,0 +1,396 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+#ifdef __CC_ARM //Keil
+#pragma diag_suppress 550  // variable xxx was set but never used.
+#endif
+
+#include <stdio.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "spi_reva.h"
+#include "dma.h"
+
+
+/* **** Functions **** */
+
+int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
+                 unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel)
+{
+
+    if (numSlaves > MXC_SPI_SS_INSTANCES) {
+        return E_BAD_PARAM;
+    }
+    
+    // Check if frequency is too high
+    if (hz > PeripheralClock) {
+        return E_BAD_PARAM;
+    }
+    
+    // Configure GPIO for spi
+    if (spi == MXC_SPI0) {
+      #if TARGET_NUM != 32675
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI0);
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI0);
+        MXC_GPIO_Config(&gpio_cfg_spi0);
+      #endif
+    }
+    else if (spi == MXC_SPI1) {
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1);
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI1);
+        MXC_GPIO_Config(&gpio_cfg_spi1);
+    }
+    else if (spi == MXC_SPI2) {
+        MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI2);
+        MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI2);
+        MXC_GPIO_Config(&gpio_cfg_spi2);
+    }
+    else {
+        return E_NO_DEVICE;
+    }
+    
+    return MXC_SPI_RevA_Init ((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel);
+}
+
+int MXC_SPI_Shutdown(mxc_spi_regs_t* spi)
+{    
+    MXC_SPI_RevA_Shutdown ((mxc_spi_reva_regs_t*) spi);
+    
+    if (spi == MXC_SPI0) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0);
+    }
+    else if (spi == MXC_SPI1) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1);
+    }
+    else if (spi == MXC_SPI2) {
+        MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI2);
+    }
+    else {
+        return E_INVALID;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int MXC_SPI_ReadyForSleep(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_ReadyForSleep ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi)
+{
+    if(MXC_SPI_GET_IDX(spi) != -1) {
+        return PeripheralClock;
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+    return E_NO_ERROR;
+}
+
+int MXC_SPI_SetFrequency(mxc_spi_regs_t* spi, unsigned int hz)
+{
+    return MXC_SPI_RevA_SetFrequency ((mxc_spi_reva_regs_t*) spi, hz);
+}
+
+unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetFrequency ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_SetDataSize(mxc_spi_regs_t* spi, int dataSize)
+{
+    return MXC_SPI_RevA_SetDataSize ((mxc_spi_reva_regs_t*) spi, dataSize);
+}
+
+int MXC_SPI_GetDataSize(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetDataSize ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_SetSlave(mxc_spi_regs_t* spi, int ssIdx)
+{
+    return MXC_SPI_RevA_SetSlave ((mxc_spi_reva_regs_t*) spi, ssIdx);
+}
+
+int MXC_SPI_GetSlave(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetSlave ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_SetWidth(mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth)
+{
+    return MXC_SPI_RevA_SetWidth ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_width_t) spiWidth);
+}
+
+mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t* spi)
+{
+    return ((mxc_spi_width_t) MXC_SPI_RevA_GetWidth ((mxc_spi_reva_regs_t*) spi));
+}
+
+int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode)
+{
+    return MXC_SPI_RevA_SetMode ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_mode_t) spiMode);
+}
+
+mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi)
+{
+    return ((mxc_spi_mode_t) MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t*) spi));
+}
+
+int MXC_SPI_StartTransmission(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_StartTransmission ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_GetActive(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetActive ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_AbortTransmission(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_AbortTransmission ((mxc_spi_reva_regs_t*) spi);
+}
+
+unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
+                                unsigned int len)
+{
+    return MXC_SPI_RevA_ReadRXFIFO ((mxc_spi_reva_regs_t*) spi, bytes, len);
+}
+
+unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetRXFIFOAvailable ((mxc_spi_reva_regs_t*) spi);
+}
+
+unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes,
+                                 unsigned int len)
+{
+    return MXC_SPI_RevA_WriteTXFIFO ((mxc_spi_reva_regs_t*) spi, bytes, len);
+}
+
+unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetTXFIFOAvailable ((mxc_spi_reva_regs_t*) spi);
+}
+
+void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t* spi)
+{
+    MXC_SPI_RevA_ClearRXFIFO ((mxc_spi_reva_regs_t*) spi);
+}
+
+void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t* spi)
+{
+    MXC_SPI_RevA_ClearTXFIFO ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_SetRXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes)
+{
+    return MXC_SPI_RevA_SetRXThreshold ((mxc_spi_reva_regs_t*) spi, numBytes);
+}
+
+unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetRXThreshold ((mxc_spi_reva_regs_t*) spi);
+}
+
+int MXC_SPI_SetTXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes)
+{
+    return MXC_SPI_RevA_SetTXThreshold ((mxc_spi_reva_regs_t*) spi, numBytes);
+}
+
+unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetTXThreshold ((mxc_spi_reva_regs_t*) spi);
+}
+
+unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t* spi)
+{
+    return MXC_SPI_RevA_GetFlags ((mxc_spi_reva_regs_t*) spi);
+}
+
+void MXC_SPI_ClearFlags(mxc_spi_regs_t* spi)
+{
+    MXC_SPI_RevA_ClearFlags ((mxc_spi_reva_regs_t*) spi);
+}
+
+void MXC_SPI_EnableInt(mxc_spi_regs_t* spi, unsigned int mask)
+{
+    MXC_SPI_RevA_EnableInt ((mxc_spi_reva_regs_t*) spi, mask);
+}
+
+void MXC_SPI_DisableInt(mxc_spi_regs_t* spi, unsigned int mask)
+{
+    MXC_SPI_RevA_DisableInt ((mxc_spi_reva_regs_t*) spi, mask);
+}
+
+int MXC_SPI_MasterTransaction(mxc_spi_req_t* req)
+{
+    return MXC_SPI_RevA_MasterTransaction ((mxc_spi_reva_req_t*) req);
+}
+
+int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t* req)
+{
+    return MXC_SPI_RevA_MasterTransactionAsync ((mxc_spi_reva_req_t*) req);
+}
+
+int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req)
+{
+    int reqselTx = -1;
+    int reqselRx = -1;
+    
+    int spi_num;
+    
+    spi_num = MXC_SPI_GET_IDX(req->spi);
+    MXC_ASSERT(spi_num >= 0);
+    
+    if (req->txData != NULL) {
+        switch (spi_num) {
+        case 0:
+            reqselTx = MXC_DMA_REQUEST_SPI0TX;
+            break;
+            
+        case 1:
+            reqselTx = MXC_DMA_REQUEST_SPI1TX;
+            break;
+            
+        case 2:
+            reqselTx = MXC_DMA_REQUEST_SPI2TX;
+            break;
+            
+        default:
+            return E_BAD_PARAM;
+        }
+    }
+    
+    if (req->rxData != NULL) {
+        switch (spi_num) {
+        case 0:
+            reqselRx = MXC_DMA_REQUEST_SPI0RX;
+            break;
+            
+        case 1:
+            reqselRx = MXC_DMA_REQUEST_SPI1RX;
+            break;
+            
+        case 2:
+            reqselRx = MXC_DMA_REQUEST_SPI2RX;
+            break;
+            
+        default:
+            return E_BAD_PARAM;
+        }
+    }
+
+    return MXC_SPI_RevA_MasterTransactionDMA ((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA);
+}
+
+int MXC_SPI_SlaveTransaction(mxc_spi_req_t* req)
+{
+    return MXC_SPI_RevA_SlaveTransaction ((mxc_spi_reva_req_t*) req);
+}
+
+int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t* req)
+{
+    return MXC_SPI_RevA_SlaveTransactionAsync ((mxc_spi_reva_req_t*) req);
+}
+
+int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req)
+{
+    int reqselTx = -1;
+    int reqselRx = -1;
+    
+    int spi_num;
+    
+    spi_num = MXC_SPI_GET_IDX(req->spi);
+    MXC_ASSERT(spi_num >= 0);
+    
+    if (req->txData != NULL) {
+        switch (spi_num) {
+        case 0:
+            reqselTx = MXC_DMA_REQUEST_SPI0TX;
+            break;
+            
+        case 1:
+            reqselTx = MXC_DMA_REQUEST_SPI1TX;
+            break;
+            
+        case 2:
+            reqselTx = MXC_DMA_REQUEST_SPI2TX;
+            break;
+            
+        default:
+            return E_BAD_PARAM;
+        }
+    }
+    
+    if (req->rxData != NULL) {
+        switch (spi_num) {
+        case 0:
+            reqselRx = MXC_DMA_REQUEST_SPI0RX;
+            break;
+            
+        case 1:
+            reqselRx = MXC_DMA_REQUEST_SPI1RX;
+            break;
+            
+        case 2:
+            reqselRx = MXC_DMA_REQUEST_SPI2RX;
+            break;
+            
+        default:
+            return E_BAD_PARAM;
+        }
+    }
+    return MXC_SPI_RevA_SlaveTransactionDMA ((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA);
+}
+
+int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t* spi, unsigned int defaultTXData)
+{
+    return MXC_SPI_RevA_SetDefaultTXData ((mxc_spi_reva_regs_t*) spi, defaultTXData);
+}
+
+void MXC_SPI_AbortAsync(mxc_spi_regs_t* spi)
+{
+    MXC_SPI_RevA_AbortAsync ((mxc_spi_reva_regs_t*) spi);
+}
+
+void MXC_SPI_AsyncHandler(mxc_spi_regs_t* spi)
+{
+    MXC_SPI_RevA_AsyncHandler ((mxc_spi_reva_regs_t*) spi);
+}

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h

@@ -0,0 +1,118 @@
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+#include <stdio.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_device.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "spi_regs.h"
+#include "spi_reva_regs.h"
+#include "mxc_spi.h"
+#include "dma.h"
+
+typedef enum {
+    SPI_REVA_WIDTH_3WIRE,
+    SPI_REVA_WIDTH_STANDARD,
+    SPI_REVA_WIDTH_DUAL,
+    SPI_REVA_WIDTH_QUAD,
+} mxc_spi_reva_width_t;
+
+typedef enum {
+    SPI_REVA_MODE_0, 
+    SPI_REVA_MODE_1,
+    SPI_REVA_MODE_2,
+    SPI_REVA_MODE_3,
+} mxc_spi_reva_mode_t;
+
+typedef struct _mxc_spi_reva_req_t mxc_spi_reva_req_t;
+
+struct _mxc_spi_reva_req_t {
+    mxc_spi_reva_regs_t*     spi;
+    int                      ssIdx;
+    int                      ssDeassert;
+    uint8_t                  *txData;
+    uint8_t                  *rxData;
+    uint32_t                 txLen;
+    uint32_t                 rxLen;
+    uint32_t                 txCnt;
+    uint32_t                 rxCnt;
+    spi_complete_cb_t        completeCB;
+};
+
+int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
+                       unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
+int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz);
+unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize);
+int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx);
+int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth);
+mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode);
+mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi);
+unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes,
+                                      unsigned int len);
+unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes,
+                                       unsigned int len);
+unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi);
+unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi);
+void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi);
+void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes);
+unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi);
+int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes);
+unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi);
+unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi);
+void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi);
+void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int mask);
+void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int mask);
+int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req);
+int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req);
+int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
+int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req);
+int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req);
+int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma);
+void MXC_SPI_RevA_DMACallback (int ch, int error);
+int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData);
+void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi);
+void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi);