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Merge pull request #835 from masaohamanaka/master 

RZ_A1H - Fix some bugs about InterruptIn, SPI, I2C and modify some settings.
pull/842/head
Martin Kojtal 2015-01-12 08:14:02 +00:00
parent 3ec2247713 596d0e9b78
commit 47725f9123
8 changed files with 77 additions and 44 deletions
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9
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct
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@ -24,13 +24,13 @@ SFLASH 0x18000000 (0x08000000)
* (+RO-CODE) ; Application RO code (.text) * (+RO-CODE) ; Application RO code (.text)
} }
RO_DATA +0 RO_DATA +0
{ * (+RO-DATA) } ; Application RO data (.constdata) { * (+RO-DATA) } ; Application RO data (.constdata)
RW_DATA 0x20600000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20060000 to 0x206FFFFF) RW_DATA 0x20020000
{ * (+RW) } ; Application RW data (.data) { * (+RW) } ; Application RW data (.data)
ZI_DATA 0x20100000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20010000 to 0x201FFFFF) ZI_DATA +0 ALIGN 0x400
{ * (+ZI) } ; Application ZI data (.bss) { * (+ZI) } ; Application ZI data (.bss)
RW_DATA_NC 0x60900000 0x00100000 RW_DATA_NC 0x60900000 0x00100000
@ -38,9 +38,6 @@ SFLASH 0x18000000 (0x08000000)
ZI_DATA_NC +0 ZI_DATA_NC +0
{ * (NC_BSS) } ; Application ZI data Non cached area { * (NC_BSS) } ; Application ZI data Non cached area
;HEAP 0x90000000
;{ * (HEAP) }
} }

8
libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h
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@ -16,6 +16,14 @@
#ifndef MBED_DEVICE_H #ifndef MBED_DEVICE_H
#define MBED_DEVICE_H #define MBED_DEVICE_H
/* ->Take measures about optimization problems of web compiler */
/* Web compiler has problem that inlining code may not be generated correctly */
/* when "-O3 -Otime" was specified. */
#if defined(__arm__) && (__ARMCC_VERSION <= 5040027)
#pragma Ospace
#endif
/* <-Take measures about optimization problems of web compiler */
#define DEVICE_PORTIN 1 #define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1 #define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1 #define DEVICE_PORTINOUT 1

49
libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c
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@ -58,27 +58,28 @@ static const IRQHandler irq_tbl[CHANNEL_NUM] = {
static const PinMap PinMap_IRQ[] = { static const PinMap PinMap_IRQ[] = {
{P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4}, {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
{P1_3, IRQ3, 4}, {P1_5, IRQ5, 4}, {P1_7, IRQ7, 4}, {P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4},
{P1_8, IRQ2, 3}, {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3},
{P1_11, IRQ5, 3}, // 9 {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
{P2_0, IRQ5, 6}, {P2_13, IRQ7, 8}, {P2_14, IRQ0, 8}, {P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
{P2_15, IRQ1, 8}, // 13 {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
{P3_0, IRQ2, 3}, {P3_3, IRQ4, 3}, // 15 {P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3},
{P3_9, IRQ6, 8}, // 20
{P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8}, {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
{P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8}, {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
{P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 23 {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
{P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 26 {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31
{P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4}, {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
{P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8}, {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
{P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8}, {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
{P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8}, {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
{P6_15, IRQ7, 8}, // 39 {P6_15, IRQ7, 8}, // 44
{P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8}, {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
{P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8}, {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
{P7_14, IRQ6, 8}, // 46 {P7_14, IRQ6, 8}, // 51
{P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4}, {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
{P9_1, IRQ0, 4}, // 50 {P9_1, IRQ0, 4}, // 55
{P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 52 {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
{NC, NC, 0} {NC, NC, 0}
}; };
@ -167,6 +168,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
INTCICR1 |= (0x3 << shift); INTCICR1 |= (0x3 << shift);
GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5); GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
obj->int_enable = 1;
__enable_irq(); __enable_irq();
return 0; return 0;
@ -181,8 +183,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
uint16_t val = event == IRQ_RISE ? 2 : uint16_t val = event == IRQ_RISE ? 2 :
event == IRQ_FALL ? 1 : 0; event == IRQ_FALL ? 1 : 0;
uint16_t work_icr_val; uint16_t work_icr_val;
uint16_t work_irqrr_val;
/* check edge interrupt setting */ /* check edge interrupt setting */
work_icr_val = INTCICR1; work_icr_val = INTCICR1;
if (enable == 1) { if (enable == 1) {
@ -192,25 +193,33 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
/* Clear interrupt serect */ /* Clear interrupt serect */
work_icr_val &= ~(val << shift); work_icr_val &= ~(val << shift);
} }
if ((work_icr_val & (3 << shift)) == 0) { if ((work_icr_val & (3 << shift)) == 0) {
/* No edge interrupt setting */ /* No edge interrupt setting */
GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
/* Clear Interrupt flags */ /* Clear Interrupt flags */
work_irqrr_val = INTCIRQRR; INTCIRQRR &= ~(1 << obj->ch);
INTCIRQRR = (work_irqrr_val & ~(1 << obj->ch)); } else if (obj->int_enable == 1) {
GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
} else { } else {
/* Edge interrupt setting */ /* Do Nothing */
GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
} }
INTCICR1 = work_icr_val; INTCICR1 = work_icr_val;
} }
void gpio_irq_enable(gpio_irq_t *obj) { void gpio_irq_enable(gpio_irq_t *obj) {
GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); int shift = obj->ch*2;
uint16_t work_icr_val = INTCICR1;
/* check edge interrupt setting */
if ((work_icr_val & (3 << shift)) != 0) {
GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
}
obj->int_enable = 1;
} }
void gpio_irq_disable(gpio_irq_t *obj) { void gpio_irq_disable(gpio_irq_t *obj) {
GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
obj->int_enable = 0;
} }

36
libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c
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@ -462,16 +462,25 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
i2c_set_err_noslave(obj); i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE; return I2C_ERROR_NO_SLAVE;
} }
/* RIICnSR2.STOP = 0 */ /* If not repeated start, send stop. */
REG(SR2.UINT32) &= ~SR2_STOP; if (stop) {
/* RIICnCR2.SP = 1 */ /* RIICnSR2.STOP = 0 */
REG(CR2.UINT32) |= CR2_SP; REG(SR2.UINT32) &= ~SR2_STOP;
/* RIICnDRR read */ /* RIICnCR2.SP = 1 */
value = REG(DRR.UINT32) & 0xFF; REG(CR2.UINT32) |= CR2_SP;
data[count] = (char)value; /* RIICnDRR read */
/* RIICnMR3.WAIT = 0 */ value = REG(DRR.UINT32) & 0xFF;
REG(MR3.UINT32) &= ~MR3_WAIT; data[count] = (char)value;
(void)i2c_wait_STOP(obj); /* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
} else {
/* RIICnDRR read */
value = REG(DRR.UINT32) & 0xFF;
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
}
i2c_set_NACKF_STOP(obj); i2c_set_NACKF_STOP(obj);
return length; return length;
@ -506,8 +515,11 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
i2c_set_err_noslave(obj); i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE; return I2C_ERROR_NO_SLAVE;
} }
i2c_stop(obj); /* If not repeated start, send stop. */
(void)i2c_wait_STOP(obj); if (stop) {
i2c_stop(obj);
(void)i2c_wait_STOP(obj);
}
i2c_set_NACKF_STOP(obj); i2c_set_NACKF_STOP(obj);
return length; return length;

1
libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h
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@ -46,6 +46,7 @@ struct gpio_irq_s {
uint32_t port; uint32_t port;
uint32_t pin; uint32_t pin;
uint32_t ch; uint32_t ch;
uint8_t int_enable;
}; };
struct port_s { struct port_s {

2
libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c
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@ -31,7 +31,6 @@ void pin_function(PinName pin, int function) {
*PMC(n) &= ~bitmask; *PMC(n) &= ~bitmask;
} else { } else {
// alt-function mode // alt-function mode
*PMC(n) |= bitmask;
--function; --function;
if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;}
@ -42,6 +41,7 @@ void pin_function(PinName pin, int function) {
if (P1_0 <= pin && pin <= P1_7 && function == 0) { if (P1_0 <= pin && pin <= P1_7 && function == 0) {
*PBDC(n) |= bitmask; *PBDC(n) |= bitmask;
} }
*PMC(n) |= bitmask;
} }
} else { } else {
gpio_multi_guard = (PinName)NC; gpio_multi_guard = (PinName)NC;

14
libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c
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@ -117,6 +117,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
int phase = (mode & 0x1) ? 1 : 0; int phase = (mode & 0x1) ? 1 : 0;
uint16_t tmp = 0; uint16_t tmp = 0;
uint16_t mask = 0xf03; uint16_t mask = 0xf03;
uint16_t wk_spcmd0;
uint8_t splw; uint8_t splw;
switch (mode) { switch (mode) {
@ -154,8 +155,10 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
obj->bits = bits; obj->bits = bits;
spi_disable(obj); spi_disable(obj);
obj->spi->SPCMD0 &= ~mask; wk_spcmd0 = obj->spi->SPCMD0;
obj->spi->SPCMD0 |= (mask & tmp); wk_spcmd0 &= ~mask;
wk_spcmd0 |= (mask & tmp);
obj->spi->SPCMD0 = wk_spcmd0;
obj->spi->SPDCR = splw; obj->spi->SPDCR = splw;
if (slave) { if (slave) {
obj->spi->SPCR &=~(1 << 3); // MSTR to 0 obj->spi->SPCR &=~(1 << 3); // MSTR to 0
@ -172,6 +175,7 @@ void spi_frequency(spi_t *obj, int hz) {
uint32_t hz_max; uint32_t hz_max;
uint32_t hz_min; uint32_t hz_min;
uint16_t mask = 0x000c; uint16_t mask = 0x000c;
uint16_t wk_spcmd0;
/* set PCLK */ /* set PCLK */
if (RZ_A1_IsClockMode0() == false) { if (RZ_A1_IsClockMode0() == false) {
@ -197,8 +201,10 @@ void spi_frequency(spi_t *obj, int hz) {
spi_disable(obj); spi_disable(obj);
obj->spi->SPBR = div; obj->spi->SPBR = div;
obj->spi->SPCMD0 &= ~mask; wk_spcmd0 = obj->spi->SPCMD0;
obj->spi->SPCMD0 |= (mask & brdv); wk_spcmd0 &= ~mask;
wk_spcmd0 |= (mask & brdv);
obj->spi->SPCMD0 = wk_spcmd0;
spi_enable(obj); spi_enable(obj);
} }

2
libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c
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@ -75,7 +75,7 @@
// <i> Defines the combined stack size for threads with user-provided stack size. // <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0 // <i> Default: 0
#ifndef OS_PRIVSTKSIZE #ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 4096 #define OS_PRIVSTKSIZE 8192
#endif #endif
// <q>Check for stack overflow // <q>Check for stack overflow