mirror of https://github.com/ARMmbed/mbed-os.git
psoc64: Update TF-M release image
- Fix key derivation issue - Update PSoC64 BSP - Replace IPC semaphore spin-lock with IPC lock Signed-off-by: Charley Chu <haoc@cypress.com>pull/13418/head
Charley Chu
parent
d8a50aa21e
commit
4749e176d7
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@ -13,7 +13,6 @@
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#include "cy_ipc_drv.h"
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#include "cy_sysint.h"
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#include "cy_ipc_sema.h"
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#include "ns_ipc_config.h"
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#include "tfm_ns_mailbox.h"
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@ -52,21 +51,6 @@ int32_t tfm_ns_mailbox_hal_notify_peer(void)
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}
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}
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static int32_t mailbox_sema_init(void)
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{
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#if defined(CY_IPC_DEFAULT_CFG_DISABLE)
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/* semaphore data */
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static uint32_t tfm_sema __attribute__((section("TFM_SHARED_DATA")));
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if (Cy_IPC_Sema_Init(PLATFORM_MAILBOX_IPC_CHAN_SEMA,
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sizeof(tfm_sema) * CHAR_BIT,
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&tfm_sema) != CY_IPC_SEMA_SUCCESS) {
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return PLATFORM_MAILBOX_INIT_ERROR;
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}
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#endif
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return PLATFORM_MAILBOX_SUCCESS;
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}
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int32_t tfm_ns_mailbox_hal_init(struct ns_mailbox_queue_t *queue)
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{
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uint32_t stage;
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@ -75,10 +59,6 @@ int32_t tfm_ns_mailbox_hal_init(struct ns_mailbox_queue_t *queue)
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return MAILBOX_INVAL_PARAMS;
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}
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/* Init semaphores used for critical sections */
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if (mailbox_sema_init() != PLATFORM_MAILBOX_SUCCESS)
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return MAILBOX_INIT_ERROR;
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/*
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* FIXME
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* Further verification of mailbox queue address may be required according
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@ -120,7 +100,7 @@ int32_t tfm_ns_mailbox_hal_init(struct ns_mailbox_queue_t *queue)
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const void *tfm_ns_mailbox_get_task_handle(void)
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{
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return osThreadGetId();;
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return osThreadGetId();
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}
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void tfm_ns_mailbox_hal_wait_reply(mailbox_msg_handle_t handle)
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@ -128,137 +108,39 @@ void tfm_ns_mailbox_hal_wait_reply(mailbox_msg_handle_t handle)
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osThreadFlagsWait(handle, osFlagsWaitAll, osWaitForever);
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}
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static cy_en_ipcsema_status_t mailbox_raw_spin_lock(uint32_t ipc_channel,
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uint32_t sema_num)
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{
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uint32_t semaIndex;
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uint32_t semaMask;
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cy_stc_ipc_sema_t *semaStruct;
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cy_en_ipcdrv_status_t acqStatus;
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cy_en_ipcsema_status_t ret = CY_IPC_SEMA_BAD_PARAM;
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bool is_lock = false;
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IPC_STRUCT_Type *semaIpcStruct;
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/* Get IPC register structure */
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semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipc_channel);
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/* Get pointer to structure */
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semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(semaIpcStruct);
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if (sema_num < semaStruct->maxSema) {
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semaIndex = sema_num / CY_IPC_SEMA_PER_WORD;
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semaMask = (uint32_t)(1ul << (sema_num - \
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(semaIndex * CY_IPC_SEMA_PER_WORD)));
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while (!is_lock) {
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/* Check to make sure the IPC channel is released
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If so, check if specific channel can be locked. */
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do {
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acqStatus = Cy_IPC_Drv_LockAcquire(semaIpcStruct);
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} while (acqStatus != CY_IPC_DRV_SUCCESS);
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if ((semaStruct->arrayPtr[semaIndex] & semaMask) == 0ul) {
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semaStruct->arrayPtr[semaIndex] |= semaMask;
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is_lock = true;
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}
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/* Release, but do not trigger a release event */
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(void)Cy_IPC_Drv_LockRelease(semaIpcStruct,
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CY_IPC_NO_NOTIFICATION);
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if (!is_lock) {
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/*
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* The secure core is occupying this lock. Insert a small delay
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* to give the secure core a chance to acquire the IPC channel
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* and release the lock.
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* Otherwise, the secure core may not be able to release the
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* lock if non-secure core has higher CPU frequency. It will
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* generate a deadlock.
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* This delay won't harm performance too much since non-secure
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* core has to busy wait here anyway.
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* Alternatively, non-secure core can wait for release
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* notification event from secure core. However, it is more
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* complex and requires more code and more modifications.
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*/
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volatile uint32_t count = 1000;
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while(count > 0) {
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count--;
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}
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Cy_IPC_Sema_Status(sema_num);
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}
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}
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ret = CY_IPC_SEMA_SUCCESS;
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}
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return ret;
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}
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static cy_en_ipcsema_status_t mailbox_raw_spin_unlock(uint32_t ipc_channel,
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uint32_t sema_num)
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{
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uint32_t semaIndex;
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uint32_t semaMask;
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cy_stc_ipc_sema_t *semaStruct;
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cy_en_ipcdrv_status_t acqStatus;
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cy_en_ipcsema_status_t ret = CY_IPC_SEMA_BAD_PARAM;
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bool is_unlock = false;
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IPC_STRUCT_Type *semaIpcStruct;
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/* Get IPC register structure */
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semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipc_channel);
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/* Get pointer to structure */
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semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(semaIpcStruct);
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if (sema_num < semaStruct->maxSema) {
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semaIndex = sema_num / CY_IPC_SEMA_PER_WORD;
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semaMask = (uint32_t)(1ul << (sema_num - \
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(semaIndex * CY_IPC_SEMA_PER_WORD)));
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while (!is_unlock) {
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/* Check to make sure the IPC channel is released
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If so, check if specific channel can be locked. */
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do {
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acqStatus = Cy_IPC_Drv_LockAcquire(semaIpcStruct);
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} while (acqStatus != CY_IPC_DRV_SUCCESS);
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if ((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul) {
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semaStruct->arrayPtr[semaIndex] &= ~semaMask;
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is_unlock = true;
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}
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/* Release, but do not trigger a release event */
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(void)Cy_IPC_Drv_LockRelease(semaIpcStruct,
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CY_IPC_NO_NOTIFICATION);
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}
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ret = CY_IPC_SEMA_SUCCESS;
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}
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return ret;
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}
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void tfm_ns_mailbox_hal_enter_critical(void)
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{
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saved_irq_state = Cy_SysLib_EnterCriticalSection();
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mailbox_raw_spin_lock(CY_IPC_CHAN_SEMA, MAILBOX_SEMAPHORE_NUM);
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IPC_STRUCT_Type* ipc_struct =
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Cy_IPC_Drv_GetIpcBaseAddress(IPC_PSA_MAILBOX_LOCK_CHAN);
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while(CY_IPC_DRV_SUCCESS != Cy_IPC_Drv_LockAcquire (ipc_struct))
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{
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}
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}
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void tfm_ns_mailbox_hal_exit_critical(void)
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{
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mailbox_raw_spin_unlock(CY_IPC_CHAN_SEMA, MAILBOX_SEMAPHORE_NUM);
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IPC_STRUCT_Type* ipc_struct =
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Cy_IPC_Drv_GetIpcBaseAddress(IPC_PSA_MAILBOX_LOCK_CHAN);
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Cy_IPC_Drv_LockRelease(ipc_struct, CY_IPC_NO_NOTIFICATION);
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Cy_SysLib_ExitCriticalSection(saved_irq_state);
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}
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void tfm_ns_mailbox_hal_enter_critical_isr(void)
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{
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mailbox_raw_spin_lock(CY_IPC_CHAN_SEMA, MAILBOX_SEMAPHORE_NUM);
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IPC_STRUCT_Type* ipc_struct =
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Cy_IPC_Drv_GetIpcBaseAddress(IPC_PSA_MAILBOX_LOCK_CHAN);
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while(CY_IPC_DRV_SUCCESS != Cy_IPC_Drv_LockAcquire (ipc_struct))
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{
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}
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}
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void tfm_ns_mailbox_hal_exit_critical_isr(void)
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{
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mailbox_raw_spin_unlock(CY_IPC_CHAN_SEMA, MAILBOX_SEMAPHORE_NUM);
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IPC_STRUCT_Type* ipc_struct =
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Cy_IPC_Drv_GetIpcBaseAddress(IPC_PSA_MAILBOX_LOCK_CHAN);
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Cy_IPC_Drv_LockRelease(ipc_struct, CY_IPC_NO_NOTIFICATION);
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}
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static bool mailbox_clear_intr(void)
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@ -1 +1 @@
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eecaad9e4014
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9fd2fd6250d5
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@ -24,6 +24,8 @@
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#define IPC_PSA_CLIENT_REPLY_NOTIFY_MASK (1 << IPC_PSA_CLIENT_REPLY_INTR_STRUCT)
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#define IPC_PSA_CLIENT_REPLY_IPC_INTR cpuss_interrupts_ipc_8_IRQn
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#define IPC_PSA_MAILBOX_LOCK_CHAN (10)
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#define IPC_RX_RELEASE_MASK (0)
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#define CY_IPC_NOTIFY_SHIFT (16)
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@ -1 +1 @@
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e90e02327eb3
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9fd2fd6250d5
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