mirror of https://github.com/ARMmbed/mbed-os.git
Remove MTS_GAMBIT target
Marcelo Salazar
parent
a3dc513d35
commit
470293c2e8
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@ -1,133 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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OSC32KCLK = 0,
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} RTCName;
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typedef enum {
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UART_0 = 0,
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UART_2 = 2,
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UART_3 = 3,
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UART_5 = 5,
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} UARTName;
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#define STDIO_UART_TX USBTX
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#define STDIO_UART_RX USBRX
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#define STDIO_UART UART_0
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typedef enum {
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I2C_0 = 0,
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I2C_1 = 1,
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} I2CName;
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#define TPM_SHIFT 8
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typedef enum {
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PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
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PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
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PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
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PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
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PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
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PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
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PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
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PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
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PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
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PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
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PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
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PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
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PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
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PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
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PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
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PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
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PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
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PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
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PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
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PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
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PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
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PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
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PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
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PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
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// could be 4 or could be 3... not sure what register
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// this is for... too much abstraction
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PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
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PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
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PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
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PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
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PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
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PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
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PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
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PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
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} PWMName;
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#define ADC_INSTANCE_SHIFT 8
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#define ADC_B_CHANNEL_SHIFT 5
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typedef enum {
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ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
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ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
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ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
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ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
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ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
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ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
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ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
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ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
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ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
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ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
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ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
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ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
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ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
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ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4,
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ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5,
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ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6,
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ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7,
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ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
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ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
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ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
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ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
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ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
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ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
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ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
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ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
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ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
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} ADCName;
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typedef enum {
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DAC_0 = 0
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} DACName;
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typedef enum {
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SPI_0 = 0,
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SPI_1 = 1,
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} SPIName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -1,112 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "PeripheralPins.h"
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/************RTC***************/
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const PinMap PinMap_RTC[] = {
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{NC, OSC32KCLK, 0},
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};
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/************I2C***************/
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const PinMap PinMap_I2C_SDA[] = {
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{PTE25, I2C_0, 5},
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{PTB1 , I2C_0, 2},
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{PTB3 , I2C_0, 2},
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{PTC11, I2C_1, 2},
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{PTD3 , I2C_0, 7},
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{PTE0 , I2C_1, 6},
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{NC , NC , 0}
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};
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const PinMap PinMap_I2C_SCL[] = {
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{PTE24, I2C_0, 5},
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{PTB0 , I2C_0, 2},
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{PTB2 , I2C_0, 2},
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{PTC10, I2C_1, 2},
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{PTD2 , I2C_0, 7},
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{PTE1 , I2C_1, 6},
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{NC , NC , 0}
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};
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/************UART***************/
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const PinMap PinMap_UART_TX[] = {
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{PTB17, UART_0, 3},
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{PTC17, UART_3, 3},
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{PTD7 , UART_0, 3},
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{PTD3 , UART_2, 3},
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{PTB11, UART_3, 3},
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{PTA14, UART_0, 3},
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{PTE4 , UART_3, 3},
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{PTE8 , UART_5, 3},
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{NC , NC , 0}
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};
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const PinMap PinMap_UART_RX[] = {
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{PTB16, UART_0, 3},
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{PTE5 , UART_3, 3},
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{PTA15, UART_0, 3},
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{PTC16, UART_3, 3},
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{PTB10, UART_3, 3},
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{PTD2 , UART_2, 3},
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{PTC6 , UART_0, 3},
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{PTE9 , UART_5, 3},
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{NC , NC , 0}
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};
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/************SPI***************/
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const PinMap PinMap_SPI_SCLK[] = {
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{PTD1 , SPI_0, 2},
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{PTE2 , SPI_1, 2},
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{PTA15, SPI_0, 2},
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{PTB11, SPI_1, 2},
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{PTC5 , SPI_0, 2},
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{PTD5 , SPI_1, 7},
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{NC , NC , 0}
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};
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const PinMap PinMap_SPI_MOSI[] = {
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{PTD2 , SPI_0, 2},
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{PTE1 , SPI_1, 2},
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{PTE3 , SPI_1, 7},
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{PTA16, SPI_0, 2},
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{PTB16, SPI_1, 2},
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{PTC6 , SPI_0, 2},
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{PTD6 , SPI_1, 7},
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{NC , NC , 0}
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};
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const PinMap PinMap_SPI_MISO[] = {
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{PTD3 , SPI_0, 2},
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{PTE1 , SPI_1, 7},
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{PTE3 , SPI_1, 2},
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{PTA17, SPI_0, 2},
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{PTB17, SPI_1, 2},
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{PTC7 , SPI_0, 2},
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{PTD7 , SPI_1, 7},
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{NC , NC , 0}
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};
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const PinMap PinMap_SPI_SSEL[] = {
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{PTD0 , SPI_0, 2},
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{PTE4 , SPI_1, 2},
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{PTA14, SPI_0, 2},
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{PTB10, SPI_1, 2},
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{PTC4 , SPI_0, 2},
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{PTD4 , SPI_1, 7},
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{NC , NC , 0}
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};
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@ -1,268 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PINNAMES_H
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#define MBED_PINNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PIN_INPUT,
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PIN_OUTPUT
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} PinDirection;
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#define GPIO_PORT_SHIFT 12
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typedef enum {
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PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
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PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
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PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
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PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
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PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
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PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
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PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
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PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
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PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
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PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
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PTA10 = (0 << GPIO_PORT_SHIFT | 10),
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PTA11 = (0 << GPIO_PORT_SHIFT | 11),
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PTA12 = (0 << GPIO_PORT_SHIFT | 12),
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PTA13 = (0 << GPIO_PORT_SHIFT | 13),
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PTA14 = (0 << GPIO_PORT_SHIFT | 14),
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PTA15 = (0 << GPIO_PORT_SHIFT | 15),
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PTA16 = (0 << GPIO_PORT_SHIFT | 16),
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PTA17 = (0 << GPIO_PORT_SHIFT | 17),
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PTA18 = (0 << GPIO_PORT_SHIFT | 18),
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PTA19 = (0 << GPIO_PORT_SHIFT | 19),
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PTA20 = (0 << GPIO_PORT_SHIFT | 20),
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PTA21 = (0 << GPIO_PORT_SHIFT | 21),
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PTA22 = (0 << GPIO_PORT_SHIFT | 22),
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PTA23 = (0 << GPIO_PORT_SHIFT | 23),
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PTA24 = (0 << GPIO_PORT_SHIFT | 24),
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PTA25 = (0 << GPIO_PORT_SHIFT | 25),
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PTA26 = (0 << GPIO_PORT_SHIFT | 26),
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PTA27 = (0 << GPIO_PORT_SHIFT | 27),
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PTA28 = (0 << GPIO_PORT_SHIFT | 28),
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PTA29 = (0 << GPIO_PORT_SHIFT | 29),
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PTA30 = (0 << GPIO_PORT_SHIFT | 30),
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PTA31 = (0 << GPIO_PORT_SHIFT | 31),
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PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
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PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
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PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
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PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
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PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
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PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
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PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
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PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
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PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
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PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
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PTB10 = (1 << GPIO_PORT_SHIFT | 10),
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PTB11 = (1 << GPIO_PORT_SHIFT | 11),
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PTB12 = (1 << GPIO_PORT_SHIFT | 12),
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PTB13 = (1 << GPIO_PORT_SHIFT | 13),
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PTB14 = (1 << GPIO_PORT_SHIFT | 14),
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PTB15 = (1 << GPIO_PORT_SHIFT | 15),
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PTB16 = (1 << GPIO_PORT_SHIFT | 16),
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PTB17 = (1 << GPIO_PORT_SHIFT | 17),
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PTB18 = (1 << GPIO_PORT_SHIFT | 18),
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PTB19 = (1 << GPIO_PORT_SHIFT | 19),
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PTB20 = (1 << GPIO_PORT_SHIFT | 20),
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PTB21 = (1 << GPIO_PORT_SHIFT | 21),
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PTB22 = (1 << GPIO_PORT_SHIFT | 22),
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PTB23 = (1 << GPIO_PORT_SHIFT | 23),
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PTB24 = (1 << GPIO_PORT_SHIFT | 24),
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PTB25 = (1 << GPIO_PORT_SHIFT | 25),
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PTB26 = (1 << GPIO_PORT_SHIFT | 26),
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PTB27 = (1 << GPIO_PORT_SHIFT | 27),
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PTB28 = (1 << GPIO_PORT_SHIFT | 28),
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PTB29 = (1 << GPIO_PORT_SHIFT | 29),
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PTB30 = (1 << GPIO_PORT_SHIFT | 30),
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PTB31 = (1 << GPIO_PORT_SHIFT | 31),
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PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
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PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
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PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
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PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
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PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
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PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
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PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
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PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
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PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
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PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
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PTC10 = (2 << GPIO_PORT_SHIFT | 10),
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PTC11 = (2 << GPIO_PORT_SHIFT | 11),
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PTC12 = (2 << GPIO_PORT_SHIFT | 12),
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PTC13 = (2 << GPIO_PORT_SHIFT | 13),
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PTC14 = (2 << GPIO_PORT_SHIFT | 14),
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PTC15 = (2 << GPIO_PORT_SHIFT | 15),
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PTC16 = (2 << GPIO_PORT_SHIFT | 16),
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PTC17 = (2 << GPIO_PORT_SHIFT | 17),
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PTC18 = (2 << GPIO_PORT_SHIFT | 18),
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PTC19 = (2 << GPIO_PORT_SHIFT | 19),
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PTC20 = (2 << GPIO_PORT_SHIFT | 20),
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PTC21 = (2 << GPIO_PORT_SHIFT | 21),
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PTC22 = (2 << GPIO_PORT_SHIFT | 22),
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PTC23 = (2 << GPIO_PORT_SHIFT | 23),
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PTC24 = (2 << GPIO_PORT_SHIFT | 24),
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PTC25 = (2 << GPIO_PORT_SHIFT | 25),
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PTC26 = (2 << GPIO_PORT_SHIFT | 26),
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PTC27 = (2 << GPIO_PORT_SHIFT | 27),
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PTC28 = (2 << GPIO_PORT_SHIFT | 28),
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PTC29 = (2 << GPIO_PORT_SHIFT | 29),
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PTC30 = (2 << GPIO_PORT_SHIFT | 30),
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PTC31 = (2 << GPIO_PORT_SHIFT | 31),
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PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
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PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
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PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
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PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
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PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
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PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
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PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
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PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
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PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
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PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
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PTD10 = (3 << GPIO_PORT_SHIFT | 10),
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PTD11 = (3 << GPIO_PORT_SHIFT | 11),
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PTD12 = (3 << GPIO_PORT_SHIFT | 12),
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PTD13 = (3 << GPIO_PORT_SHIFT | 13),
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PTD14 = (3 << GPIO_PORT_SHIFT | 14),
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PTD15 = (3 << GPIO_PORT_SHIFT | 15),
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PTD16 = (3 << GPIO_PORT_SHIFT | 16),
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PTD17 = (3 << GPIO_PORT_SHIFT | 17),
|
||||
PTD18 = (3 << GPIO_PORT_SHIFT | 18),
|
||||
PTD19 = (3 << GPIO_PORT_SHIFT | 19),
|
||||
PTD20 = (3 << GPIO_PORT_SHIFT | 20),
|
||||
PTD21 = (3 << GPIO_PORT_SHIFT | 21),
|
||||
PTD22 = (3 << GPIO_PORT_SHIFT | 22),
|
||||
PTD23 = (3 << GPIO_PORT_SHIFT | 23),
|
||||
PTD24 = (3 << GPIO_PORT_SHIFT | 24),
|
||||
PTD25 = (3 << GPIO_PORT_SHIFT | 25),
|
||||
PTD26 = (3 << GPIO_PORT_SHIFT | 26),
|
||||
PTD27 = (3 << GPIO_PORT_SHIFT | 27),
|
||||
PTD28 = (3 << GPIO_PORT_SHIFT | 28),
|
||||
PTD29 = (3 << GPIO_PORT_SHIFT | 29),
|
||||
PTD30 = (3 << GPIO_PORT_SHIFT | 30),
|
||||
PTD31 = (3 << GPIO_PORT_SHIFT | 31),
|
||||
PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
|
||||
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
|
||||
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
|
||||
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
|
||||
PTE14 = (4 << GPIO_PORT_SHIFT | 14),
|
||||
PTE15 = (4 << GPIO_PORT_SHIFT | 15),
|
||||
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
|
||||
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
|
||||
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
|
||||
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
|
||||
PTE20 = (4 << GPIO_PORT_SHIFT | 20),
|
||||
PTE21 = (4 << GPIO_PORT_SHIFT | 21),
|
||||
PTE22 = (4 << GPIO_PORT_SHIFT | 22),
|
||||
PTE23 = (4 << GPIO_PORT_SHIFT | 23),
|
||||
PTE24 = (4 << GPIO_PORT_SHIFT | 24),
|
||||
PTE25 = (4 << GPIO_PORT_SHIFT | 25),
|
||||
PTE26 = (4 << GPIO_PORT_SHIFT | 26),
|
||||
PTE27 = (4 << GPIO_PORT_SHIFT | 27),
|
||||
PTE28 = (4 << GPIO_PORT_SHIFT | 28),
|
||||
PTE29 = (4 << GPIO_PORT_SHIFT | 29),
|
||||
PTE30 = (4 << GPIO_PORT_SHIFT | 30),
|
||||
PTE31 = (4 << GPIO_PORT_SHIFT | 31),
|
||||
|
||||
// led color naming
|
||||
LED_GREEN = PTC0,
|
||||
|
||||
// mbed original LED naming
|
||||
LED1 = PTD15,
|
||||
LED2 = PTD14,
|
||||
LED3 = PTD13,
|
||||
LED4 = PTD11,
|
||||
LED5 = PTD12,
|
||||
STATUS = LED_GREEN,
|
||||
|
||||
// USB Pins
|
||||
USBTX = PTB17,
|
||||
USBRX = PTB16,
|
||||
|
||||
// SPI Pins
|
||||
SPI0_SOUT = PTC6,
|
||||
SPI0_SIN = PTC7,
|
||||
SPI0_SCK = PTC5,
|
||||
|
||||
SPI1_SOUT = PTE3,
|
||||
SPI1_SIN = PTE1,
|
||||
SPI1_SCK = PTE2,
|
||||
|
||||
// SPI Chip Select Pins
|
||||
SPI0_NCS0 = PTC4,
|
||||
SPI0_NCS1 = PTC3,
|
||||
SPI0_NCS2 = PTC2,
|
||||
SPI0_NCS3 = PTC1,
|
||||
|
||||
SPI1_NCS0 = PTE4,
|
||||
SPI1_NCS1 = PTE0,
|
||||
SPI1_NCS2 = PTE5,
|
||||
SPI1_NCS3 = PTE6,
|
||||
|
||||
// GPIO's
|
||||
AP1_GPIO1 = PTB7,
|
||||
AP1_GPIO2 = PTB6,
|
||||
AP1_GPIO3 = PTB5,
|
||||
AP1_GPIO4 = PTB4,
|
||||
|
||||
AP2_GPIO1 = PTA27,
|
||||
AP2_GPIO2 = PTA26,
|
||||
AP2_GPIO3 = PTA25,
|
||||
AP2_GPIO4 = PTA24,
|
||||
|
||||
// Cellular Radio Serial Pins
|
||||
RADIO_SERIAL_TX = PTE8,
|
||||
RADIO_SERIAL_RX = PTE9,
|
||||
RADIO_SERIAL_RTS = PTE11,
|
||||
RADIO_SERIAL_CTS = PTE10,
|
||||
RADIO_SERIAL_DTR = PTE26,
|
||||
RADIO_SERIAL_DSR = PTE25,
|
||||
RADIO_SERIAL_RI = PTE24,
|
||||
RADIO_SERIAL_CD = PTE12,
|
||||
|
||||
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 2,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define DEVICE_ID_LENGTH 24
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_smc.h"
|
||||
#include "fsl_clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Clock configuration structure. */
|
||||
typedef struct _clock_config
|
||||
{
|
||||
mcg_config_t mcgConfig; /*!< MCG configuration. */
|
||||
sim_clock_config_t simConfig; /*!< SIM configuration. */
|
||||
osc_config_t oscConfig; /*!< OSC configuration. */
|
||||
uint32_t coreClock; /*!< core clock frequency. */
|
||||
} clock_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* Configuration for enter VLPR mode. Core clock = 4MHz. */
|
||||
const clock_config_t g_defaultClockConfigVlpr = {
|
||||
.mcgConfig =
|
||||
{
|
||||
.mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
|
||||
.ircs = kMCG_IrcFast, /* Select IRC4M. */
|
||||
.fcrdiv = 0U, /* FCRDIV is 0. */
|
||||
|
||||
.frdiv = 0U,
|
||||
.drs = kMCG_DrsLow, /* Low frequency range. */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
|
||||
.oscsel = kMCG_OscselOsc, /* Select OSC. */
|
||||
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = 0U, /* Don't eanble PLL. */
|
||||
.prdiv = 0U,
|
||||
.vdiv = 0U,
|
||||
},
|
||||
},
|
||||
.simConfig =
|
||||
{
|
||||
.pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
|
||||
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
|
||||
.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
|
||||
},
|
||||
.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
|
||||
.capLoad = 0,
|
||||
.workMode = kOSC_ModeExt,
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable,
|
||||
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
|
||||
.erclkDiv = 0U,
|
||||
#endif
|
||||
}},
|
||||
.coreClock = 4000000U, /* Core clock frequency */
|
||||
};
|
||||
|
||||
/* Configuration for enter RUN mode. Core clock = 120MHz. */
|
||||
const clock_config_t g_defaultClockConfigRun = {
|
||||
.mcgConfig =
|
||||
{
|
||||
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
|
||||
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
|
||||
.fcrdiv = 0U, /* FCRDIV is 0. */
|
||||
|
||||
.frdiv = 7U,
|
||||
.drs = kMCG_DrsLow, /* Low frequency range. */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
|
||||
.oscsel = kMCG_OscselOsc, /* Select OSC. */
|
||||
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U,
|
||||
},
|
||||
},
|
||||
.simConfig =
|
||||
{
|
||||
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
|
||||
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
|
||||
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
|
||||
},
|
||||
.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
|
||||
.capLoad = 0,
|
||||
.workMode = kOSC_ModeExt,
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable,
|
||||
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
|
||||
.erclkDiv = 0U,
|
||||
#endif
|
||||
}},
|
||||
.coreClock = 120000000U, /* Core clock frequency */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
|
||||
* and flash clock are in allowed range during clock mode switch.
|
||||
*
|
||||
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
|
||||
*
|
||||
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
|
||||
* internal reference clock(MCGIRCLK). Follow the steps to setup:
|
||||
*
|
||||
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
|
||||
*
|
||||
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
|
||||
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
|
||||
* explicitly to setup MCGIRCLK.
|
||||
*
|
||||
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
|
||||
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
|
||||
* if the target mode is not FLL mode, the FLL is disabled.
|
||||
*
|
||||
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
|
||||
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
|
||||
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
|
||||
*
|
||||
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
|
||||
*/
|
||||
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
|
||||
g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
|
||||
|
||||
CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
|
||||
|
||||
SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
|
||||
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeVlpr(SMC, false);
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
|
||||
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
|
||||
|
||||
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
|
||||
&g_defaultClockConfigRun.mcgConfig.pll0Config);
|
||||
|
||||
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
|
||||
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
|
||||
|
||||
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
|
||||
|
||||
SystemCoreClock = g_defaultClockConfigRun.coreClock;
|
||||
}
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* DEFINITION
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 50000000U
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
void BOARD_BootClockVLPR(void);
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_api.h"
|
||||
#include "fsl_rtc.h"
|
||||
#include "fsl_clock_config.h"
|
||||
|
||||
// called before main
|
||||
void mbed_sdk_init()
|
||||
{
|
||||
rtc_config_t rtc_basic_config;
|
||||
uint32_t u32cTPR_counter = 0;
|
||||
|
||||
BOARD_BootClockRUN();
|
||||
|
||||
CLOCK_EnableClock(kCLOCK_Rtc0);
|
||||
|
||||
/* Check if the Rtc oscillator is enabled */
|
||||
if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
|
||||
/*Init the RTC with default configuration*/
|
||||
RTC_GetDefaultConfig(&rtc_basic_config);
|
||||
|
||||
/* Setup the 32K RTC OSC */
|
||||
RTC_Init(RTC, &rtc_basic_config);
|
||||
|
||||
/* Enable the RTC 32KHz oscillator */
|
||||
RTC->CR |= RTC_CR_OSCE_MASK;
|
||||
|
||||
/* Start the RTC time counter */
|
||||
RTC_StartTimer(RTC);
|
||||
|
||||
/* Verify TPR register reaches 4096 counts */
|
||||
while (u32cTPR_counter < 4096) {
|
||||
u32cTPR_counter = RTC->TPR;
|
||||
}
|
||||
/* 32kHz Oscillator is ready. */
|
||||
RTC_Deinit(RTC);
|
||||
}
|
||||
|
||||
CLOCK_DisableClock(kCLOCK_Rtc0);
|
||||
}
|
||||
|
||||
|
|
@ -1123,53 +1123,6 @@
|
|||
],
|
||||
"bootloader_supported": true
|
||||
},
|
||||
"MTS_GAMBIT": {
|
||||
"inherits": [
|
||||
"Target"
|
||||
],
|
||||
"core": "Cortex-M4F",
|
||||
"supported_toolchains": [
|
||||
"ARM",
|
||||
"GCC_ARM"
|
||||
],
|
||||
"extra_labels": [
|
||||
"Freescale",
|
||||
"MCUXpresso_MCUS",
|
||||
"KSDK2_MCUS",
|
||||
"KPSDK_MCUS",
|
||||
"KPSDK_CODE",
|
||||
"MCU_K64F"
|
||||
],
|
||||
"is_disk_virtual": true,
|
||||
"macros": [
|
||||
"CPU_MK64FN1M0VMD12",
|
||||
"FSL_RTOS_MBED",
|
||||
"TARGET_K64F"
|
||||
],
|
||||
"device_has": [
|
||||
"USTICKER",
|
||||
"LPTICKER",
|
||||
"RTC",
|
||||
"I2C",
|
||||
"I2CSLAVE",
|
||||
"INTERRUPTIN",
|
||||
"PORTIN",
|
||||
"PORTINOUT",
|
||||
"PORTOUT",
|
||||
"SERIAL",
|
||||
"SERIAL_ASYNCH",
|
||||
"SLEEP",
|
||||
"SPI",
|
||||
"SPI_ASYNCH",
|
||||
"SPISLAVE",
|
||||
"STDIO_MESSAGES",
|
||||
"FLASH"
|
||||
],
|
||||
"device_name": "MK64FN1M0xxx12",
|
||||
"detect_code": [
|
||||
"0300"
|
||||
]
|
||||
},
|
||||
"HEXIWEAR": {
|
||||
"inherits": [
|
||||
"Target"
|
||||
|
|
|
|||
Loading…
Reference in New Issue