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[M2351] Link register base with partition file & correct heap size in linker file

pull/7302/head
cyliangtw 2017-09-29 18:16:40 +08:00 committed by ccli8
parent 5985dcd268
commit 46f948aa6f
8 changed files with 96 additions and 18 deletions
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37
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/PeripheralNames.h
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@ -18,6 +18,7 @@
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "partition_M2351.h"
#ifdef __cplusplus
extern "C" {
@ -67,12 +68,36 @@ typedef enum {
} ADCName;
typedef enum {
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<16))
UART_0 = (int) NU_MODNAME(UART0_BASE + NS_OFFSET, 0, 0),
#else
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<17))
UART_1 = (int) NU_MODNAME(UART1_BASE + NS_OFFSET, 1, 0),
#else
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<18))
UART_2 = (int) NU_MODNAME(UART2_BASE + NS_OFFSET, 2, 0),
#else
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<19))
UART_3 = (int) NU_MODNAME(UART3_BASE + NS_OFFSET, 3, 0),
#else
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<20))
UART_4 = (int) NU_MODNAME(UART4_BASE + NS_OFFSET, 4, 0),
#else
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
UART_5 = (int) NU_MODNAME((UART5_BASE + NS_OFFSET), 5, 0), // UART 5 is the stdio, set as non-secure
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<21))
UART_5 = (int) NU_MODNAME(UART5_BASE + NS_OFFSET, 5, 0),
#else
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
#endif
// NOTE: board-specific
STDIO_UART = UART_3
} UARTName;
@ -124,10 +149,16 @@ typedef enum {
} PWMName;
typedef enum {
TIMER_0 = (int) NU_MODNAME(TMR01_BASE + NS_OFFSET, 0, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + NS_OFFSET + 0x100, 1, 0),
// TIME 0 & TIME 1 only support secure mode
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0),
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (0x01<<17))
TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0),
#else
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x100, 3, 0),
#endif
} TIMERName;
typedef enum {

4
targets/TARGET_NUVOTON/TARGET_M2351/device/M2351.h
View File

@ -31226,11 +31226,7 @@ typedef struct
/* Peripheral and SRAM base address */
#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define NS_OFFSET (0x10000000UL)
#if (__DOMAIN_NS == 1U)
#define PERIPH_BASE (0x40000000UL + NS_OFFSET) /*!< (Peripheral) Base Address */
#else
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
#endif
/* Peripheral memory map */
#define AHBPERIPH_BASE PERIPH_BASE

3
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld
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@ -263,11 +263,10 @@ SECTIONS
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
__HeapLimit = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));

8
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h
View File

@ -367,7 +367,7 @@
//
*/
#define NVIC_INIT_ITNS1_VAL 0x0F
#define NVIC_INIT_ITNS1_VAL 0x0C
/*
Initialize ITNS 2 (Interrupts 0..31)
@ -432,7 +432,7 @@
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/*
max 128 SAU regions.
SAU regions are defined in partition.h
@ -539,7 +539,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
/* repeat this for all possible ITNS elements */
}
#endif
/*
// <h> Peripheral Secure Attribution Configuration
@ -584,7 +584,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
// <o.26> BPWM0 <0=> Secure <1=> Non-Secure
// <o.27> BPWM1 <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET2_VAL 0x00000002
#define SCU_INIT_PNSSET2_VAL 0x00020002
/*
PNSSET3
*/

21
targets/TARGET_NUVOTON/TARGET_M2351/gpio_object.h
View File

@ -22,6 +22,7 @@
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "partition_M2351.h"
#ifdef __cplusplus
extern "C" {
@ -37,8 +38,16 @@ static inline void gpio_write(gpio_t *obj, int value)
MBED_ASSERT(obj->pin != (PinName)NC);
uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
#if defined (NVIC_INIT_ITNS0_VAL)
if( NVIC_INIT_ITNS0_VAL & (0x01 << (16 + port_index)) )
{
GPIO_PIN_DATA_NS(port_index, pin_index) = value ? 1 : 0;
} else {
GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0;
}
#else
GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0;
#endif
}
static inline int gpio_read(gpio_t *obj)
@ -46,8 +55,16 @@ static inline int gpio_read(gpio_t *obj)
MBED_ASSERT(obj->pin != (PinName)NC);
uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
#if defined (NVIC_INIT_ITNS0_VAL)
if( NVIC_INIT_ITNS0_VAL & (0x01 << (16 + port_index)) )
{
return (GPIO_PIN_DATA_NS(port_index, pin_index) ? 1 : 0);
} else {
return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0);
}
#else
return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0);
#endif
}
#ifdef __cplusplus

3
targets/TARGET_NUVOTON/TARGET_M2351/lp_ticker.c
View File

@ -50,6 +50,8 @@ static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLK
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void lp_ticker_init(void)
{
if (lp_ticker_inited) {
@ -104,6 +106,7 @@ void lp_ticker_init(void)
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
}
#endif
timestamp_t lp_ticker_read()
{

19
targets/TARGET_NUVOTON/TARGET_M2351/port_api.c
View File

@ -18,6 +18,7 @@
#include "gpio_api.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "partition_M2351.h"
#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT
@ -79,8 +80,17 @@ void port_write(port_t *obj, int value)
for (i = 0; i < GPIO_PIN_MAX; i++) {
if (obj->mask & (1 << i)) {
#if defined (NVIC_INIT_ITNS0_VAL)
if( NVIC_INIT_ITNS0_VAL & (0x01 << (16 + port_index)) )
{
GPIO_PIN_DATA_NS(port_index, i) = (value & obj->mask) ? 1 : 0;
} else {
GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0;
}
#else
GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0;
#endif
}
}
}
@ -92,8 +102,17 @@ int port_read(port_t *obj)
for (i = 0; i < GPIO_PIN_MAX; i++) {
if (obj->mask & (1 << i)) {
#if defined (NVIC_INIT_ITNS0_VAL)
if( NVIC_INIT_ITNS0_VAL & (0x01 << (16 + port_index)) )
{
value = value | (GPIO_PIN_DATA_NS(port_index, i) << i);
} else {
value = value | (GPIO_PIN_DATA(port_index, i) << i);
}
#else
value = value | (GPIO_PIN_DATA(port_index, i) << i);
#endif
}
}
return value;

15
targets/TARGET_NUVOTON/TARGET_M2351/us_ticker.c
View File

@ -21,6 +21,7 @@
#include "nu_miscutil.h"
#include "mbed_critical.h"
// us_ticker tick = us = timestamp
#define US_PER_TICK 1
#define US_PER_SEC (1000 * 1000)
@ -50,13 +51,15 @@ static volatile uint32_t cd_minor_us = 0;
// 2. HXT: Less accurate and cannot pass mbed-drivers test.
// 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void us_ticker_init(void)
{
if (us_ticker_inited) {
@ -100,7 +103,10 @@ void us_ticker_init(void)
TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
}
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
uint32_t us_ticker_read()
{
if (! us_ticker_inited) {
@ -138,17 +144,22 @@ uint32_t us_ticker_read()
}
while (0);
}
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void us_ticker_disable_interrupt(void)
{
TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
}
__attribute__((cmse_nonsecure_entry))
void us_ticker_clear_interrupt(void)
{
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
}
__attribute__((cmse_nonsecure_entry))
void us_ticker_set_interrupt(timestamp_t timestamp)
{
TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
@ -158,6 +169,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
us_ticker_arm_cd();
}
__attribute__((cmse_nonsecure_entry))
void us_ticker_fire_interrupt(void)
{
cd_major_minor_us = cd_minor_us = 0;
@ -167,6 +179,7 @@ void us_ticker_fire_interrupt(void)
*/
NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
}
#endif
static void tmr0_vec(void)
{