diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h
index aa60b4f95f..cd1ac6e342 100644
--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h
@@ -125,19 +125,19 @@ enum smsc9220_mac_reg_offsets_t{
  *
  */
 enum phy_reg_offsets_t{
-    SMSC9220_PHY_REG_OFFSET_BCTRL =      0x0U,
-    SMSC9220_PHY_REG_OFFSET_BSTATUS =    0x1U,
-    SMSC9220_PHY_REG_OFFSET_ID1 =        0x2U,
-    SMSC9220_PHY_REG_OFFSET_ID2 =        0x3U,
-    SMSC9220_PHY_REG_OFFSET_ANEG_ADV =   0x4U,
-    SMSC9220_PHY_REG_OFFSET_ANEG_LPA =   0x5U,
-    SMSC9220_PHY_REG_OFFSET_ANEG_EXP =   0x6U,
-    SMSC9220_PHY_REG_OFFSET_MCONTROL =   0x17U,
-    SMSC9220_PHY_REG_OFFSET_MSTATUS =    0x18U,
-    SMSC9220_PHY_REG_OFFSET_CSINDICATE = 0x27U,
-    SMSC9220_PHY_REG_OFFSET_INTSRC =     0x29U,
-    SMSC9220_PHY_REG_OFFSET_INTMASK =    0x30U,
-    SMSC9220_PHY_REG_OFFSET_CS =         0x31U
+    SMSC9220_PHY_REG_OFFSET_BCTRL =      0U,
+    SMSC9220_PHY_REG_OFFSET_BSTATUS =    1U,
+    SMSC9220_PHY_REG_OFFSET_ID1 =        2U,
+    SMSC9220_PHY_REG_OFFSET_ID2 =        3U,
+    SMSC9220_PHY_REG_OFFSET_ANEG_ADV =   4U,
+    SMSC9220_PHY_REG_OFFSET_ANEG_LPA =   5U,
+    SMSC9220_PHY_REG_OFFSET_ANEG_EXP =   6U,
+    SMSC9220_PHY_REG_OFFSET_MCONTROL =   17U,
+    SMSC9220_PHY_REG_OFFSET_MSTATUS =    18U,
+    SMSC9220_PHY_REG_OFFSET_CSINDICATE = 27U,
+    SMSC9220_PHY_REG_OFFSET_INTSRC =     29U,
+    SMSC9220_PHY_REG_OFFSET_INTMASK =    30U,
+    SMSC9220_PHY_REG_OFFSET_CS =         31U
 };
 
 /* Bit definitions for PHY Basic Status Register */