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RTX5: Cortex-A exception handlers updated (VFP register count detection)

pull/5628/head
Robert Rostohar 2017-10-27 10:44:59 +02:00 committed by TomoYamanaka
parent 4f4b4ddf36
commit 461c215636
3 changed files with 89 additions and 93 deletions
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27
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S
View File

@ -384,19 +384,18 @@ osRtxContextSave
VMRS R2, FPSCR
STMDB R3!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16
VSTMDB R3!, {D0-D15}
LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that VFP/D16 state is stacked
ORR R2, R2, #2
STRB R2, [R0, #TCB_SP_FRAME]
ENDIF
VSTMDB R3!, {D0-D15} ; Save D0-D15
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VSTMDB R3!, {D0-D15}
VSTMDB R3!, {D16-D31}
LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that NEON/D32 state is stacked
ORR R2, R2, #4
STRB R2, [R0, #TCB_SP_FRAME]
VSTMDB R3!, {D16-D31} ; Save D16-D31
ENDIF
LDRB R2, [R0, #TCB_SP_FRAME]
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
ORR R2, R2, #4 ; NEON state
ELSE
ORR R2, R2, #2 ; VFP state
ENDIF
STRB R2, [R0, #TCB_SP_FRAME] ; Record VFP/NEON state
osRtxContextSave1
STR R3, [R0, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr
@ -414,11 +413,11 @@ osRtxContextRestore
BEQ osRtxContextRestore1 ; No VFP
ISB ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VLDMIA R3!, {D16-D31}
VLDMIA R3!, {D16-D31} ; Restore D16-D31
ENDIF
VLDMIA R3!, {D0-D15}
VLDMIA R3!, {D0-D15} ; Restore D0-D15
LDR R2, [R3]
VMSR FPSCR, R2
VMSR FPSCR, R2 ; Restore FPSCR
ADD R3, R3, #8
osRtxContextRestore1

29
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S
View File

@ -391,19 +391,18 @@ osRtxContextSave:
VMRS R2, FPSCR
STMDB R3!, {R2,R12} // Push FPSCR, maintain 8-byte alignment
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 16
VSTMDB R3!, {D0-D15}
LDRB R2, [R0, #TCB_SP_FRAME] // Record in TCB that VFP/D16 state is stacked
ORR R2, R2, #2
STRB R2, [R0, #TCB_SP_FRAME]
VSTMDB R3!, {D0-D15} // Save D0-D15
#if __ARM_NEON == 1
VSTMDB R3!, {D16-D31} // Save D16-D31
#endif
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
VSTMDB R3!, {D0-D15}
VSTMDB R3!, {D16-D31}
LDRB R2, [R0, #TCB_SP_FRAME] // Record in TCB that NEON/D32 state is stacked
ORR R2, R2, #4
STRB R2, [R0, #TCB_SP_FRAME]
LDRB R2, [R0, #TCB_SP_FRAME]
#if __ARM_NEON == 1
ORR R2, R2, #4 // NEON state
#else
ORR R2, R2, #2 // VFP state
#endif
STRB R2, [R0, #TCB_SP_FRAME] // Record VFP/NEON state
osRtxContextSave1:
STR R3, [R0, #TCB_SP_OFS] // Store user sp to osRtxInfo.thread.run.curr
@ -420,12 +419,12 @@ osRtxContextRestore:
MCR p15, 0, R2, c1, c0, 2 // Write CPACR
BEQ osRtxContextRestore1 // No VFP
ISB // Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
VLDMIA R3!, {D16-D31}
#if __ARM_NEON == 1
VLDMIA R3!, {D16-D31} // Restore D16-D31
#endif
VLDMIA R3!, {D0-D15}
VLDMIA R3!, {D0-D15} // Restore D0-D15
LDR R2, [R3]
VMSR FPSCR, R2
VMSR FPSCR, R2 // Restore FPSCR
ADD R3, R3, #8
osRtxContextRestore1:

36
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S
View File

@ -42,7 +42,6 @@ TCB_SP_OFS EQU 56 ; osRtxThread_t.sp offset
PRESERVE8
ARM
SECTION .rodata:DATA:NOROOT(2)
@ -370,19 +369,18 @@ osRtxContextSave
VMRS R2, FPSCR
STMDB R3!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16
VSTMDB R3!, {D0-D15}
LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that VFP/D16 state is stacked
ORR R2, R2, #2
STRB R2, [R0, #TCB_SP_FRAME]
ENDIF
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VSTMDB R3!, {D0-D15}
VSTMDB R3!, {D16-D31}
LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that NEON/D32 state is stacked
ORR R2, R2, #4
STRB R2, [R0, #TCB_SP_FRAME]
ENDIF
VSTMDB R3!, {D0-D15} ; Save D0-D15
#ifdef __ARM_ADVANCED_SIMD__
VSTMDB R3!, {D16-D31} ; Save D16-D31
#endif
LDRB R2, [R0, #TCB_SP_FRAME]
#ifdef __ARM_ADVANCED_SIMD__
ORR R2, R2, #4 ; NEON state
#else
ORR R2, R2, #2 ; VFP state
#endif
STRB R2, [R0, #TCB_SP_FRAME] ; Record VFP/NEON state
osRtxContextSave1
STR R3, [R0, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr
@ -399,12 +397,12 @@ osRtxContextRestore
MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
BEQ osRtxContextRestore1 ; No VFP
ISB ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VLDMIA R3!, {D16-D31}
ENDIF
VLDMIA R3!, {D0-D15}
#ifdef __ARM_ADVANCED_SIMD__
VLDMIA R3!, {D16-D31} ; Restore D16-D31
#endif
VLDMIA R3!, {D0-D15} ; Restore D0-D15
LDR R2, [R3]
VMSR FPSCR, R2
VMSR FPSCR, R2 ; Restore FPSCR
ADD R3, R3, #8
osRtxContextRestore1