mirror of https://github.com/ARMmbed/mbed-os.git
S2-LP: Sync with development repository
Jarkko Paso
parent
421ad37433
commit
45d1c68814
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@ -172,7 +172,6 @@ RFPins::RFPins(PinName spi_sdi, PinName spi_sdo,
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static uint8_t rf_read_register(uint8_t addr);
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static s2lp_states_e rf_read_state(void);
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static void rf_write_register(uint8_t addr, uint8_t data);
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static void rf_print_registers(void);
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static void rf_interrupt_handler(void);
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static void rf_receive(uint8_t rx_channel);
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static void rf_cca_timer_stop(void);
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@ -211,6 +210,8 @@ static bool rf_update_config = false;
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static uint16_t cur_packet_len = 0xffff;
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static uint32_t receiver_ready_timestamp;
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static int16_t rssi_threshold = RSSI_THRESHOLD;
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/* Channel configurations for sub-GHz */
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static phy_rf_channel_configuration_s phy_subghz = {
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.channel_0_center_frequency = 868300000U,
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@ -501,6 +502,10 @@ static uint32_t read_irq_status(void)
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static void rf_set_channel_configuration_registers(void)
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{
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// Set RSSI threshold
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uint8_t rssi_th;
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rf_conf_calculate_rssi_threshold_registers(rssi_threshold, &rssi_th);
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rf_write_register(RSSI_TH, rssi_th);
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// Set deviation
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uint32_t deviation = rf_conf_calculate_deviation(phy_subghz.modulation_index, phy_subghz.datarate);
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if (!deviation) {
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@ -557,10 +562,6 @@ static void rf_init_registers(void)
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rf_write_register_field(QI, SQI_EN_FIELD, SQI_EN);
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rf_write_register(SYNC0, SFD0);
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rf_write_register(SYNC1, SFD1);
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// Set RSSI threshold
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uint8_t rssi_th;
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rf_conf_calculate_rssi_threshold_registers(RSSI_THRESHOLD, &rssi_th);
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rf_write_register(RSSI_TH, rssi_th);
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rf_set_channel_configuration_registers();
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}
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@ -666,6 +667,16 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
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rf_receive(rf_rx_channel);
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}
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break;
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case PHY_EXTENSION_SET_TX_POWER:
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// TODO: Set TX output power
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break;
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case PHY_EXTENSION_SET_CCA_THRESHOLD:
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rssi_threshold = rf_conf_cca_threshold_percent_to_rssi(*data_ptr);
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rf_update_config = true;
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if (rf_state == RF_IDLE) {
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rf_receive(rf_rx_channel);
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}
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break;
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default:
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break;
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}
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@ -683,6 +694,14 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_
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break;
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/*Disable PHY Interface driver*/
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case PHY_INTERFACE_DOWN:
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rf_lock();
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rf_send_command(S2LP_CMD_SABORT);
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rf_disable_all_interrupts();
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rf_poll_state_change(S2LP_STATE_READY);
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rf_flush_rx_fifo();
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rf_flush_tx_fifo();
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rf_state = RF_IDLE;
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rf_unlock();
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break;
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/*Enable PHY Interface driver*/
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case PHY_INTERFACE_UP:
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@ -810,6 +829,15 @@ static void rf_cca_timer_start(uint32_t slots)
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static void rf_backup_timer_interrupt(void)
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{
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tx_finnish_time = rf_get_timestamp();
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if (rf_state == RF_RX_STARTED) {
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if (device_driver.phy_rf_statistics) {
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device_driver.phy_rf_statistics->rx_timeouts++;
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}
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} else {
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if (device_driver.phy_rf_statistics) {
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device_driver.phy_rf_statistics->tx_timeouts++;
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}
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}
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if (rf_state == RF_TX_STARTED) {
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if (device_driver.phy_tx_done_cb) {
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device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0);
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@ -1054,6 +1082,9 @@ static void rf_irq_task_process_irq(void)
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rf_state = RF_IDLE;
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// In case the channel change was called during reception, driver is responsible to change the channel if CRC failed.
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rf_receive(rf_new_channel);
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if (device_driver.phy_rf_statistics) {
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device_driver.phy_rf_statistics->crc_fails++;
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}
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}
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}
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if ((irq_status & (1 << RX_FIFO_ALMOST_FULL)) && (enabled_interrupts & (1 << RX_FIFO_ALMOST_FULL))) {
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@ -1103,7 +1134,6 @@ static void rf_init(void)
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rf_enable_gpio_interrupt();
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rf_calculate_symbol_rate(phy_subghz.datarate, phy_subghz.modulation);
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rf->tx_timer.start();
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rf_print_registers();
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}
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static int8_t rf_device_register(const uint8_t *mac_addr)
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@ -1199,7 +1229,6 @@ int8_t NanostackRfPhys2lp::rf_register()
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s2lp_MAC[0] &= ~1; //Clear multicast bit
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#endif
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set_mac_address(s2lp_MAC);
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tr_info("MAC address: %s", trace_array(_mac_addr, 8));
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}
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rf = _rf;
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@ -1349,137 +1378,6 @@ static bool rf_rx_filter(uint8_t *mac_header, uint8_t *mac_64bit_addr, uint8_t *
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return true;
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}
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static void rf_print_registers(void)
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{
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tr_debug("GPIO0_CONF: %x", rf_read_register(GPIO0_CONF));
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tr_debug("GPIO1_CONF: %x", rf_read_register(GPIO1_CONF));
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tr_debug("GPIO2_CONF: %x", rf_read_register(GPIO2_CONF));
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tr_debug("GPIO3_CONF: %x", rf_read_register(GPIO3_CONF));
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tr_debug("SYNT3: %x", rf_read_register(SYNT3));
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tr_debug("SYNT2: %x", rf_read_register(SYNT2));
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tr_debug("SYNT1: %x", rf_read_register(SYNT1));
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tr_debug("SYNT0: %x", rf_read_register(SYNT0));
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tr_debug("IF_OFFSET_ANA: %x", rf_read_register(IF_OFFSET_ANA));
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tr_debug("IF_OFFSET_DIG: %x", rf_read_register(IF_OFFSET_DIG));
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tr_debug("CHSPACE: %x", rf_read_register(CHSPACE));
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tr_debug("CHNUM: %x", rf_read_register(CHNUM));
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tr_debug("MOD4: %x", rf_read_register(MOD4));
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tr_debug("MOD3: %x", rf_read_register(MOD3));
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tr_debug("MOD2: %x", rf_read_register(MOD2));
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tr_debug("MOD1: %x", rf_read_register(MOD1));
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tr_debug("MOD0: %x", rf_read_register(MOD0));
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tr_debug("CHFLT: %x", rf_read_register(CHFLT));
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tr_debug("AFC2: %x", rf_read_register(AFC2));
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tr_debug("AFC1: %x", rf_read_register(AFC1));
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tr_debug("AFC0: %x", rf_read_register(AFC0));
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tr_debug("RSSI_FLT: %x", rf_read_register(RSSI_FLT));
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tr_debug("RSSI_TH: %x", rf_read_register(RSSI_TH));
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tr_debug("AGCCTRL4: %x", rf_read_register(AGCCTRL4));
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tr_debug("AGCCTRL3: %x", rf_read_register(AGCCTRL3));
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tr_debug("AGCCTRL2: %x", rf_read_register(AGCCTRL2));
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tr_debug("AGCCTRL1: %x", rf_read_register(AGCCTRL1));
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tr_debug("AGCCTRL0: %x", rf_read_register(AGCCTRL0));
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tr_debug("ANT_SELECT_CONF: %x", rf_read_register(ANT_SELECT_CONF));
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tr_debug("CLOCKREC2: %x", rf_read_register(CLOCKREC2));
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tr_debug("CLOCKREC1: %x", rf_read_register(CLOCKREC1));
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tr_debug("PCKTCTRL6: %x", rf_read_register(PCKTCTRL6));
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tr_debug("PCKTCTRL5: %x", rf_read_register(PCKTCTRL5));
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tr_debug("PCKTCTRL4: %x", rf_read_register(PCKTCTRL4));
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tr_debug("PCKTCTRL3: %x", rf_read_register(PCKTCTRL3));
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tr_debug("PCKTCTRL2: %x", rf_read_register(PCKTCTRL2));
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tr_debug("PCKTCTRL1: %x", rf_read_register(PCKTCTRL1));
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tr_debug("PCKTLEN1: %x", rf_read_register(PCKTLEN1));
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tr_debug("PCKTLEN0: %x", rf_read_register(PCKTLEN0));
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tr_debug("SYNC3: %x", rf_read_register(SYNC3));
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tr_debug("SYNC2: %x", rf_read_register(SYNC2));
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tr_debug("SYNC1: %x", rf_read_register(SYNC1));
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tr_debug("SYNC0: %x", rf_read_register(SYNC0));
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tr_debug("QI: %x", rf_read_register(QI));
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tr_debug("PCKT_PSTMBL: %x", rf_read_register(PCKT_PSTMBL));
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tr_debug("PROTOCOL2: %x", rf_read_register(PROTOCOL2));
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tr_debug("PROTOCOL1: %x", rf_read_register(PROTOCOL1));
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tr_debug("PROTOCOL0: %x", rf_read_register(PROTOCOL0));
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tr_debug("FIFO_CONFIG3: %x", rf_read_register(FIFO_CONFIG3));
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tr_debug("FIFO_CONFIG2: %x", rf_read_register(FIFO_CONFIG2));
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tr_debug("FIFO_CONFIG1: %x", rf_read_register(FIFO_CONFIG1));
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tr_debug("FIFO_CONFIG0: %x", rf_read_register(FIFO_CONFIG0));
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tr_debug("PCKT_FLT_OPTIONS: %x", rf_read_register(PCKT_FLT_OPTIONS));
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tr_debug("PCKT_FLT_GOALS4: %x", rf_read_register(PCKT_FLT_GOALS4));
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tr_debug("PCKT_FLT_GOALS3: %x", rf_read_register(PCKT_FLT_GOALS3));
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tr_debug("PCKT_FLT_GOALS2: %x", rf_read_register(PCKT_FLT_GOALS2));
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tr_debug("PCKT_FLT_GOALS1: %x", rf_read_register(PCKT_FLT_GOALS1));
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tr_debug("PCKT_FLT_GOALS0: %x", rf_read_register(PCKT_FLT_GOALS0));
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tr_debug("TIMERS5: %x", rf_read_register(TIMERS5));
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tr_debug("TIMERS4: %x", rf_read_register(TIMERS4));
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tr_debug("TIMERS3: %x", rf_read_register(TIMERS3));
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tr_debug("TIMERS2: %x", rf_read_register(TIMERS2));
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tr_debug("TIMERS1: %x", rf_read_register(TIMERS1));
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tr_debug("TIMERS0: %x", rf_read_register(TIMERS0));
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tr_debug("CSMA_CONF3: %x", rf_read_register(CSMA_CONF3));
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tr_debug("CSMA_CONF2: %x", rf_read_register(CSMA_CONF2));
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tr_debug("CSMA_CONF1: %x", rf_read_register(CSMA_CONF1));
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tr_debug("CSMA_CONF0: %x", rf_read_register(CSMA_CONF0));
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tr_debug("IRQ_MASK3: %x", rf_read_register(IRQ_MASK3));
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tr_debug("IRQ_MASK2: %x", rf_read_register(IRQ_MASK2));
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tr_debug("IRQ_MASK1: %x", rf_read_register(IRQ_MASK1));
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tr_debug("IRQ_MASK0: %x", rf_read_register(IRQ_MASK0));
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tr_debug("FAST_RX_TIMER: %x", rf_read_register(FAST_RX_TIMER));
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tr_debug("PA_POWER8: %x", rf_read_register(PA_POWER8));
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tr_debug("PA_POWER7: %x", rf_read_register(PA_POWER7));
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tr_debug("PA_POWER6: %x", rf_read_register(PA_POWER6));
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tr_debug("PA_POWER5: %x", rf_read_register(PA_POWER5));
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tr_debug("PA_POWER4: %x", rf_read_register(PA_POWER4));
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tr_debug("PA_POWER3: %x", rf_read_register(PA_POWER3));
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tr_debug("PA_POWER2: %x", rf_read_register(PA_POWER2));
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tr_debug("PA_POWER1: %x", rf_read_register(PA_POWER1));
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tr_debug("PA_POWER0: %x", rf_read_register(PA_POWER0));
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tr_debug("PA_CONFIG1: %x", rf_read_register(PA_CONFIG1));
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tr_debug("PA_CONFIG0: %x", rf_read_register(PA_CONFIG0));
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tr_debug("SYNTH_CONFIG2: %x", rf_read_register(SYNTH_CONFIG2));
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tr_debug("VCO_CONFIG: %x", rf_read_register(VCO_CONFIG));
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tr_debug("VCO_CALIBR_IN2: %x", rf_read_register(VCO_CALIBR_IN2));
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tr_debug("VCO_CALIBR_IN1: %x", rf_read_register(VCO_CALIBR_IN1));
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tr_debug("VCO_CALIBR_IN0: %x", rf_read_register(VCO_CALIBR_IN0));
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tr_debug("XO_RCO_CONF1: %x", rf_read_register(XO_RCO_CONF1));
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tr_debug("XO_RCO_CONF0: %x", rf_read_register(XO_RCO_CONF0));
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tr_debug("RCO_CALIBR_CONF3: %x", rf_read_register(RCO_CALIBR_CONF3));
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tr_debug("RCO_CALIBR_CONF2: %x", rf_read_register(RCO_CALIBR_CONF2));
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tr_debug("PM_CONF4: %x", rf_read_register(PM_CONF4));
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tr_debug("PM_CONF3: %x", rf_read_register(PM_CONF3));
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tr_debug("PM_CONF2: %x", rf_read_register(PM_CONF2));
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tr_debug("PM_CONF1: %x", rf_read_register(PM_CONF1));
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tr_debug("PM_CONF0: %x", rf_read_register(PM_CONF0));
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tr_debug("MC_STATE1: %x", rf_read_register(MC_STATE1));
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tr_debug("MC_STATE0: %x", rf_read_register(MC_STATE0));
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tr_debug("TX_FIFO_STATUS: %x", rf_read_register(TX_FIFO_STATUS));
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tr_debug("RX_FIFO_STATUS: %x", rf_read_register(RX_FIFO_STATUS));
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tr_debug("RCO_CALIBR_OUT4: %x", rf_read_register(RCO_CALIBR_OUT4));
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tr_debug("RCO_CALIBR_OUT3: %x", rf_read_register(RCO_CALIBR_OUT3));
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tr_debug("VCO_CALIBR_OUT1: %x", rf_read_register(VCO_CALIBR_OUT1));
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tr_debug("VCO_CALIBR_OUT0: %x", rf_read_register(VCO_CALIBR_OUT0));
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tr_debug("TX_PCKT_INFO: %x", rf_read_register(TX_PCKT_INFO));
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tr_debug("RX_PCKT_INFO: %x", rf_read_register(RX_PCKT_INFO));
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tr_debug("AFC_CORR: %x", rf_read_register(AFC_CORR));
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tr_debug("LINK_QUALIF2: %x", rf_read_register(LINK_QUALIF2));
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tr_debug("LINK_QUALIF1: %x", rf_read_register(LINK_QUALIF1));
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tr_debug("RSSI_LEVEL: %x", rf_read_register(RSSI_LEVEL));
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tr_debug("RX_PCKT_LEN1: %x", rf_read_register(RX_PCKT_LEN1));
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tr_debug("RX_PCKT_LEN0: %x", rf_read_register(RX_PCKT_LEN0));
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tr_debug("CRC_FIELD3: %x", rf_read_register(CRC_FIELD3));
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tr_debug("CRC_FIELD2: %x", rf_read_register(CRC_FIELD2));
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tr_debug("CRC_FIELD1: %x", rf_read_register(CRC_FIELD1));
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tr_debug("CRC_FIELD0: %x", rf_read_register(CRC_FIELD0));
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tr_debug("RX_ADDRE_FIELD1: %x", rf_read_register(RX_ADDRE_FIELD1));
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tr_debug("RX_ADDRE_FIELD0: %x", rf_read_register(RX_ADDRE_FIELD0));
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tr_debug("RSSI_LEVEL_RUN: %x", rf_read_register(RSSI_LEVEL_RUN));
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tr_debug("DEVICE_INFO1: %x", rf_read_register(DEVICE_INFO1));
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tr_debug("DEVICE_INFO0: %x", rf_read_register(DEVICE_INFO0));
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tr_debug("IRQ_STATUS3: %x", rf_read_register(IRQ_STATUS3));
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tr_debug("IRQ_STATUS2: %x", rf_read_register(IRQ_STATUS2));
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tr_debug("IRQ_STATUS1: %x", rf_read_register(IRQ_STATUS1));
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tr_debug("IRQ_STATUS0: %x", rf_read_register(IRQ_STATUS0));
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}
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#if MBED_CONF_S2LP_PROVIDE_DEFAULT
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NanostackRfPhy &NanostackRfPhy::get_default_instance()
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{
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@ -35,6 +35,10 @@
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// Use multiplier for better resolution
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#define RESOLUTION_MULTIPLIER 1000000
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// RSSI_TH is a 8-bit register which can be converted to dBm using formula RSSI_TH-146
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#define MIN_RSSI_THRESHOLD -146
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#define MAX_RSSI_THRESHOLD 109
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void rf_conf_calculate_datarate_registers(uint32_t datarate, uint16_t *datarate_mantissa, uint8_t *datarate_exponent)
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{
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uint64_t datarate_m = (uint64_t)datarate * DEF_2EXP33;
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@ -151,6 +155,12 @@ void rf_conf_calculate_rx_filter_bandwidth_registers(uint32_t rx_bandwidth, uint
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*chflt_e = chflt_e_tmp;
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}
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int16_t rf_conf_cca_threshold_percent_to_rssi(uint8_t percent)
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{
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uint8_t step = (MAX_RSSI_THRESHOLD-MIN_RSSI_THRESHOLD);
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return MIN_RSSI_THRESHOLD + (step * percent) / 100;
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}
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void rf_conf_calculate_rssi_threshold_registers(int16_t rssi_threshold, uint8_t *rssi_th)
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{
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*rssi_th = rssi_threshold + RSSI_OFFSET;
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@ -32,6 +32,7 @@ int rf_conf_calculate_channel_spacing_registers(uint32_t channel_spacing, uint8_
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void rf_conf_calculate_rx_filter_bandwidth_registers(uint32_t rx_bandwidth, uint8_t *chflt_m, uint8_t *chflt_e);
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void rf_conf_calculate_rssi_threshold_registers(int16_t rssi_threshold, uint8_t *rssi_th);
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uint32_t rf_conf_calculate_deviation(phy_modulation_index_e modulation_index, uint32_t datarate);
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int16_t rf_conf_cca_threshold_percent_to_rssi(uint8_t percent);
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#ifdef __cplusplus
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}
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@ -229,7 +229,7 @@ extern "C" {
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#define DEFAULT_DEVIATION 125000
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#define RX_FILTER_BANDWIDTH 540000
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#define RSSI_THRESHOLD -60
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#define RSSI_THRESHOLD -85
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// PCKTCTRL6
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#define PCKT_SYNCLEN_FIELD 0xFC
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