From ea032bebc422a86587efa9ca5fba607754a9f023 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Tue, 9 Jul 2019 16:40:38 -0500 Subject: [PATCH 1/5] Add XIP capability, enable QSPI. XIP can be enable by adding macro XIP_ENABLE in mbed_app.json. It's disabled by default. --- .../TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S | 17 ---- .../GeneratedSource/cycfg_qspi_memslot.h | 71 ++++++++++++++++ .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld | 32 +++++-- .../TARGET_PSOC6/mbed_overrides.c | 6 ++ .../TARGET_Cypress/TARGET_PSOC6/xip_user.c | 84 +++++++++++++++++++ targets/targets.json | 1 + tools/toolchains/mbed_toolchain.py | 6 ++ 7 files changed, 191 insertions(+), 26 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S index 3c2f44d1e0..009b58b94c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -53,23 +53,6 @@ __StackLimit: __StackTop: .size __StackTop, . - __StackTop - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - .section .vectors .align 2 .globl __Vectors diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 5e541bb902..7f24948623 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -22,6 +22,76 @@ * limitations under the License. ********************************************************************************/ +/******************************************************************************* + +QSPI_CONFIG_START + + + PSoC 6.xml + + + 0 + S25FL512S + true + None + 0x18000000 + 0x40000 + 0x1803FFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + + +QSPI_CONFIG_END + +*******************************************************************************/ + #ifndef CYCFG_QSPI_MEMSLOT_H #define CYCFG_QSPI_MEMSLOT_H #include "cy_smif_memslot.h" @@ -41,6 +111,7 @@ extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd; extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0; extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0; + extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld index ebb6f76525..5a98e24715 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -162,6 +162,21 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application image */ + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + . = ALIGN(4); + __cy_xip_start__ = .; + KEEP(*(.cy_xip)) + #if XIP_ENABLE == 1 + *lwipstack*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + *mbed-cloud-client*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + #endif + __cy_xip_end__ = .; + } > xip + .text FLASH_CM4_START : { . = ALIGN(4); @@ -173,7 +188,11 @@ SECTIONS __end__ = .; . = ALIGN(4); + #if XIP_ENABLE == 1 + *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .text .text*) + #else *(.text*) + #endif KEEP(*(.init)) KEEP(*(.fini)) @@ -193,7 +212,11 @@ SECTIONS *(.dtors) /* Read-only code (constants). */ + #if XIP_ENABLE == 1 + *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + #else *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + #endif KEEP(*(.eh_frame*)) } > flash @@ -400,15 +423,6 @@ SECTIONS } > sflash_rtoc_2 - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - /* eFuse */ .cy_efuse : { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c index 26b366c32a..a555049347 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c @@ -31,6 +31,9 @@ void mailbox_init(void); #endif +#if defined(XIP_ENABLE) +extern void qspi_xip_start(); +#endif #if (defined(CY_CFG_PWR_SYS_IDLE_MODE) && (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_ACTIVE)) /******************************************************************************* @@ -100,6 +103,9 @@ void mbed_sdk_init(void) /* Enable global interrupts (disabled in CM4 startup assembly) */ __enable_irq(); #endif +#if defined(XIP_ENABLE) + qspi_xip_start(); +#endif #if defined (CY_CFG_PWR_SYS_IDLE_MODE) /* Configure the lowest power state the system is allowed to enter diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c b/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c new file mode 100644 index 0000000000..6366a78a36 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef XIP_ENABLE +#include "cy_smif.h" +#include "cy_smif_memslot.h" +#include "cycfg_qspi_memslot.h" +#include "qspi_api.h" + +/******************************************************************** +* NULL terminated array of SMIF structures for use in TOC2 +********************************************************************/ +typedef struct +{ + const cy_stc_smif_block_config_t * smifCfg; /* Pointer to SMIF top-level configuration */ + const uint32_t null_t; /* NULL termination */ +} stc_smif_ipblocks_arr_t; + +/* + * PSoC 6 boot sequence is such that the TOC2 needs to verified before switching to the application code. + * In the mbed build system the CRC for TOC2 is not calculated. Hence CRC has to be manually placed in the TOC2 + * SMIF config structure is placed at a fixed address so as to fix the CRC for table of contents2 (TOC2). +*/ +__attribute__((section(".cy_sflash_user_data"))) __attribute__((used)) +const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig, 0x00000000}; + +/******************************************************************** +* Point to the SMIF block structure in the table of contents2 (TOC2). +* +* This enables memory reads using Cypress Programmer, without this +* structure, external memory access from Cypress Programmer will not +* work +********************************************************************/ + +__attribute__((section(".cy_toc_part2"))) __attribute__((used)) +const int cyToc[128] = +{ + 0x200-4, /* Offset=0x00: Object Size, bytes */ + 0x01211220, /* Offset=0x04: Magic Number (TOC Part 2, ID) */ + 0, /* Offset=0x08: Key Storage Address */ + (int)&smifIpBlocksArr, /* Offset=0x0C: This points to a null terminated array of SMIF structures. */ + 0x10000000u, /* Offset=0x10: App image start address */ + [127] = 0x0B1F0000 /* Offset=0x1FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */ +}; + +/* QSPI HAL object */ +qspi_t QSPI_HW; + +void qspi_xip_start() +{ + QSPI_HW.hal_qspi.base = SMIF0; + QSPI_HW.hal_qspi.slave_select = CY_SMIF_SLAVE_SELECT_0; + qspi_status_t qspi_api_result = QSPI_STATUS_OK; + + /* Initialize the QSPI interface */ + qspi_api_result = qspi_init(&QSPI_HW, QSPI_IO_0, QSPI_IO_1, QSPI_IO_2, QSPI_IO_3, QSPI_CLK, QSPI_SEL, 0, 0); + + if(qspi_api_result == QSPI_STATUS_OK) + { + /* Initialize the memory device connected to SMIF slot */ + Cy_SMIF_Memslot_Init(QSPI_HW.hal_qspi.base, (cy_stc_smif_block_config_t*)&smifBlockConfig, &(QSPI_HW.hal_qspi.context)); + + /* Enable quad mode of operation */ + Cy_SMIF_Memslot_QuadEnable(QSPI_HW.hal_qspi.base, (cy_stc_smif_mem_config_t*)smifMemConfigs[0], &(QSPI_HW.hal_qspi.context)); + + /* Set the operation mode to XIP */ + Cy_SMIF_SetMode(QSPI_HW.hal_qspi.base, CY_SMIF_MEMORY); + } +} +#endif diff --git a/targets/targets.json b/targets/targets.json index 9e3d854e2e..301c5a3464 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8579,6 +8579,7 @@ "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", + "QSPI", "SPI", "SPI_ASYNCH", "SPISLAVE", diff --git a/tools/toolchains/mbed_toolchain.py b/tools/toolchains/mbed_toolchain.py index 7352338831..8d0c81c906 100755 --- a/tools/toolchains/mbed_toolchain.py +++ b/tools/toolchains/mbed_toolchain.py @@ -990,6 +990,12 @@ class mbedToolchain: self.ld.append(define_string) self.flags["ld"].append(define_string) + if "XIP_ENABLE" in self.target.macros : + define_string = self.make_ld_define( + "XIP_ENABLE", 1) + self.ld.append(define_string) + self.flags["ld"].append(define_string) + # Set the configuration data def set_config_data(self, config_data): self.config_data = config_data From 2a78a9ba13577dd9894336c94da83b788635f08c Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Wed, 31 Jul 2019 15:05:01 -0500 Subject: [PATCH 2/5] Refactored code to not use macro. Created config xip-enable --- .../TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c | 4 ++-- targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c | 2 +- targets/targets.json | 4 ++++ tools/toolchains/mbed_toolchain.py | 15 +++++++++------ 4 files changed, 16 insertions(+), 9 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c index a555049347..53bdf4bb0a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c @@ -31,7 +31,7 @@ void mailbox_init(void); #endif -#if defined(XIP_ENABLE) +#if MBED_CONF_TARGET_XIP_ENABLE extern void qspi_xip_start(); #endif @@ -103,7 +103,7 @@ void mbed_sdk_init(void) /* Enable global interrupts (disabled in CM4 startup assembly) */ __enable_irq(); #endif -#if defined(XIP_ENABLE) +#if MBED_CONF_TARGET_XIP_ENABLE qspi_xip_start(); #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c b/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c index 6366a78a36..e8503f473a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c @@ -15,7 +15,7 @@ * limitations under the License. */ -#ifdef XIP_ENABLE +#if MBED_CONF_TARGET_XIP_ENABLE #include "cy_smif.h" #include "cy_smif_memslot.h" #include "cycfg_qspi_memslot.h" diff --git a/targets/targets.json b/targets/targets.json index 301c5a3464..93cae5c03a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -51,6 +51,10 @@ "init-us-ticker-at-boot": { "help": "Initialize the microsecond ticker at boot rather than on first use, and leave it initialized. This speeds up wait_us in particular.", "value": false + }, + "xip-enable": { + "help": "Enable Execute In Place (XIP) on this target. Value is only significant if the board has executable external storage such as QSPIF. If this is enabled, customize the linker file to choose what text segments are placed on external storage", + "value": false } } }, diff --git a/tools/toolchains/mbed_toolchain.py b/tools/toolchains/mbed_toolchain.py index 8d0c81c906..0e042a8c0f 100755 --- a/tools/toolchains/mbed_toolchain.py +++ b/tools/toolchains/mbed_toolchain.py @@ -953,6 +953,7 @@ class mbedToolchain: STACK_PARAM = "target.boot-stack-size" TFM_LVL_PARAM = "tfm.level" + XIP_ENABLE_PARAM = "target.xip-enable" def add_linker_defines(self): params, _ = self.config_data @@ -974,6 +975,14 @@ class mbedToolchain: self.ld.append(define_string) self.flags["ld"].append(define_string) + if self.XIP_ENABLE_PARAM in params: + define_string = self.make_ld_define( + "XIP_ENABLE", + params[self.XIP_ENABLE_PARAM].value + ) + self.ld.append(define_string) + self.flags["ld"].append(define_string) + if self.target.is_PSA_secure_target: for flag, param in [ ("MBED_PUBLIC_RAM_START", "target.public-ram-start"), @@ -990,12 +999,6 @@ class mbedToolchain: self.ld.append(define_string) self.flags["ld"].append(define_string) - if "XIP_ENABLE" in self.target.macros : - define_string = self.make_ld_define( - "XIP_ENABLE", 1) - self.ld.append(define_string) - self.flags["ld"].append(define_string) - # Set the configuration data def set_config_data(self, config_data): self.config_data = config_data From b9f8e2ac5310f761eea3a921a24b528811042803 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Tue, 6 Aug 2019 11:28:29 -0500 Subject: [PATCH 3/5] Remove QSPI for Future targets --- .../TARGET_PSOC6/mbed_overrides.c | 7 +- .../TARGET_Cypress/TARGET_PSOC6/xip_user.c | 84 ------------------- 2 files changed, 2 insertions(+), 89 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c index 53bdf4bb0a..7f836f5b3a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c @@ -94,18 +94,15 @@ void mbed_sdk_init(void) us_ticker_init(); #endif -#if defined(CYBSP_ENABLE_FLASH_STORAGE) +#if MBED_CONF_TARGET_XIP_ENABLE /* The linker script allows storing data in external memory, if needed, enable access to that memory. */ cybsp_serial_flash_init(); cybsp_serial_flash_enable_xip(true); -#endif /* defined(CYBSP_ENABLE_FLASH_STORAGE) */ +#endif /* Enable global interrupts (disabled in CM4 startup assembly) */ __enable_irq(); #endif -#if MBED_CONF_TARGET_XIP_ENABLE - qspi_xip_start(); -#endif #if defined (CY_CFG_PWR_SYS_IDLE_MODE) /* Configure the lowest power state the system is allowed to enter diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c b/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c deleted file mode 100644 index e8503f473a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if MBED_CONF_TARGET_XIP_ENABLE -#include "cy_smif.h" -#include "cy_smif_memslot.h" -#include "cycfg_qspi_memslot.h" -#include "qspi_api.h" - -/******************************************************************** -* NULL terminated array of SMIF structures for use in TOC2 -********************************************************************/ -typedef struct -{ - const cy_stc_smif_block_config_t * smifCfg; /* Pointer to SMIF top-level configuration */ - const uint32_t null_t; /* NULL termination */ -} stc_smif_ipblocks_arr_t; - -/* - * PSoC 6 boot sequence is such that the TOC2 needs to verified before switching to the application code. - * In the mbed build system the CRC for TOC2 is not calculated. Hence CRC has to be manually placed in the TOC2 - * SMIF config structure is placed at a fixed address so as to fix the CRC for table of contents2 (TOC2). -*/ -__attribute__((section(".cy_sflash_user_data"))) __attribute__((used)) -const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig, 0x00000000}; - -/******************************************************************** -* Point to the SMIF block structure in the table of contents2 (TOC2). -* -* This enables memory reads using Cypress Programmer, without this -* structure, external memory access from Cypress Programmer will not -* work -********************************************************************/ - -__attribute__((section(".cy_toc_part2"))) __attribute__((used)) -const int cyToc[128] = -{ - 0x200-4, /* Offset=0x00: Object Size, bytes */ - 0x01211220, /* Offset=0x04: Magic Number (TOC Part 2, ID) */ - 0, /* Offset=0x08: Key Storage Address */ - (int)&smifIpBlocksArr, /* Offset=0x0C: This points to a null terminated array of SMIF structures. */ - 0x10000000u, /* Offset=0x10: App image start address */ - [127] = 0x0B1F0000 /* Offset=0x1FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */ -}; - -/* QSPI HAL object */ -qspi_t QSPI_HW; - -void qspi_xip_start() -{ - QSPI_HW.hal_qspi.base = SMIF0; - QSPI_HW.hal_qspi.slave_select = CY_SMIF_SLAVE_SELECT_0; - qspi_status_t qspi_api_result = QSPI_STATUS_OK; - - /* Initialize the QSPI interface */ - qspi_api_result = qspi_init(&QSPI_HW, QSPI_IO_0, QSPI_IO_1, QSPI_IO_2, QSPI_IO_3, QSPI_CLK, QSPI_SEL, 0, 0); - - if(qspi_api_result == QSPI_STATUS_OK) - { - /* Initialize the memory device connected to SMIF slot */ - Cy_SMIF_Memslot_Init(QSPI_HW.hal_qspi.base, (cy_stc_smif_block_config_t*)&smifBlockConfig, &(QSPI_HW.hal_qspi.context)); - - /* Enable quad mode of operation */ - Cy_SMIF_Memslot_QuadEnable(QSPI_HW.hal_qspi.base, (cy_stc_smif_mem_config_t*)smifMemConfigs[0], &(QSPI_HW.hal_qspi.context)); - - /* Set the operation mode to XIP */ - Cy_SMIF_SetMode(QSPI_HW.hal_qspi.base, CY_SMIF_MEMORY); - } -} -#endif From f1813e5bccdc34f24cef19f94c4ff550389f1e64 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Tue, 20 Aug 2019 16:06:41 -0500 Subject: [PATCH 4/5] Remove keep keyword for .heap section --- .../device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld index 5a98e24715..30c0a98584 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -357,7 +357,7 @@ SECTIONS __HeapBase = .; __end__ = .; end = __end__; - KEEP(*(.heap*)) + *(.heap*) . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; __HeapLimit = .; } > ram From 67c6bdbf2d5691397e7c4709f4d005e99de7b494 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Tue, 3 Sep 2019 16:14:38 -0500 Subject: [PATCH 5/5] removed xip unrelated changes --- .../TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S | 17 +++++ .../GeneratedSource/cycfg_qspi_memslot.h | 71 ------------------- .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld | 34 +++------ .../TARGET_PSOC6/mbed_overrides.c | 3 - targets/targets.json | 1 - 5 files changed, 27 insertions(+), 99 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S index 009b58b94c..3c2f44d1e0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -53,6 +53,23 @@ __StackLimit: __StackTop: .size __StackTop, . - __StackTop + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .section .vectors .align 2 .globl __Vectors diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 7f24948623..5e541bb902 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -22,76 +22,6 @@ * limitations under the License. ********************************************************************************/ -/******************************************************************************* - -QSPI_CONFIG_START - - - PSoC 6.xml - - - 0 - S25FL512S - true - None - 0x18000000 - 0x40000 - 0x1803FFFF - true - false - QUAD_SPI_DATA_0_3 - S25FL512S - true - - - 1 - Not used - false - None - 0x18010000 - 0x10000 - 0x1801FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 2 - Not used - false - None - 0x18020000 - 0x10000 - 0x1802FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 3 - Not used - false - None - 0x18030000 - 0x10000 - 0x1803FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - - -QSPI_CONFIG_END - -*******************************************************************************/ - #ifndef CYCFG_QSPI_MEMSLOT_H #define CYCFG_QSPI_MEMSLOT_H #include "cy_smif_memslot.h" @@ -111,7 +41,6 @@ extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd; extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0; extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0; - extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld index 30c0a98584..ebb6f76525 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -162,21 +162,6 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application image */ - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - . = ALIGN(4); - __cy_xip_start__ = .; - KEEP(*(.cy_xip)) - #if XIP_ENABLE == 1 - *lwipstack*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - *mbed-cloud-client*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - #endif - __cy_xip_end__ = .; - } > xip - .text FLASH_CM4_START : { . = ALIGN(4); @@ -188,11 +173,7 @@ SECTIONS __end__ = .; . = ALIGN(4); - #if XIP_ENABLE == 1 - *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .text .text*) - #else *(.text*) - #endif KEEP(*(.init)) KEEP(*(.fini)) @@ -212,11 +193,7 @@ SECTIONS *(.dtors) /* Read-only code (constants). */ - #if XIP_ENABLE == 1 - *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - #else *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - #endif KEEP(*(.eh_frame*)) } > flash @@ -357,7 +334,7 @@ SECTIONS __HeapBase = .; __end__ = .; end = __end__; - *(.heap*) + KEEP(*(.heap*)) . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; __HeapLimit = .; } > ram @@ -423,6 +400,15 @@ SECTIONS } > sflash_rtoc_2 + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + /* eFuse */ .cy_efuse : { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c index 7f836f5b3a..f57c948b99 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c @@ -31,9 +31,6 @@ void mailbox_init(void); #endif -#if MBED_CONF_TARGET_XIP_ENABLE -extern void qspi_xip_start(); -#endif #if (defined(CY_CFG_PWR_SYS_IDLE_MODE) && (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_ACTIVE)) /******************************************************************************* diff --git a/targets/targets.json b/targets/targets.json index 93cae5c03a..cb51afadc8 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8583,7 +8583,6 @@ "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", - "QSPI", "SPI", "SPI_ASYNCH", "SPISLAVE",