mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_F446RE] create new target - part 2
Update system_stm32f4xx to new version, generated by STM32CubeMX Add target name to digital_loop test Update coide export templatepull/1110/head
ohagendorf
parent
8edb20bed6
commit
455b417b8f
|
|
@ -77,7 +77,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
|
|||
// Configure time base
|
||||
TimMasterHandle.Instance = TIM_MST;
|
||||
TimMasterHandle.Init.Period = 0xFFFFFFFF;
|
||||
TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
|
||||
TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
|
||||
TimMasterHandle.Init.ClockDivision = 0;
|
||||
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
TimMasterHandle.Init.RepetitionCounter = 0;
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-June-2014
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
|
|
@ -27,20 +27,20 @@
|
|||
* | 2- PLL_HSE_XTAL |
|
||||
* | (external 8 MHz xtal) |
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 96 | 96
|
||||
* SYSCLK(MHz) | 180 | 16
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 96 | 96
|
||||
* AHBCLK (MHz) | 180 | 16
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 48 | 48
|
||||
* APB1CLK (MHz) | 45 | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 96 | 96
|
||||
* APB2CLK (MHz) | 90 | 8
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB capable (48 MHz precise clock) | YES | YES
|
||||
* USB capable (48 MHz precise clock) | YES | NO
|
||||
*-----------------------------------------------------------------------------
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -108,15 +108,17 @@
|
|||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
|
||||
on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|
||||
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|
||||
|| defined(STM32F446xx)
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F446xx */
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|
||||
|| defined(STM32F446xx)
|
||||
/* #define DATA_IN_ExtSDRAM */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
|
||||
|
||||
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
|
||||
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
|
||||
|
|
@ -139,7 +141,7 @@
|
|||
|
||||
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
||||
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
||||
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
||||
#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -156,8 +158,8 @@
|
|||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 16000000;
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
uint32_t SystemCoreClock = 18000000;
|
||||
__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -229,7 +231,7 @@ void SystemInit(void)
|
|||
#endif
|
||||
|
||||
/* Configure the Cube driver */
|
||||
SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
|
||||
SystemCoreClock = 18000000; // At this stage the HSI is used as system clock
|
||||
HAL_Init();
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
|
|
@ -336,7 +338,7 @@ void SystemCoreClockUpdate(void)
|
|||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
|
||||
#if defined (DATA_IN_ExtSDRAM)
|
||||
register uint32_t tmpreg = 0, timeout = 0xFFFF;
|
||||
register uint32_t index;
|
||||
|
|
@ -422,7 +424,7 @@ void SystemInit_ExtMemCtl(void)
|
|||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
/* Configure and enable SDRAM bank1 */
|
||||
FMC_Bank5_6->SDCR[0] = 0x000019E0;
|
||||
FMC_Bank5_6->SDCR[0] = 0x000019E4;
|
||||
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
||||
|
||||
/* SDRAM initialization sequence */
|
||||
|
|
@ -469,9 +471,12 @@ void SystemInit_ExtMemCtl(void)
|
|||
tmpreg = FMC_Bank5_6->SDCR[0];
|
||||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||||
#endif /* DATA_IN_ExtSDRAM */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|
||||
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|
||||
|| defined(STM32F446xx)
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
#if defined(DATA_IN_ExtSRAM)
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
|
|
@ -529,12 +534,12 @@ void SystemInit_ExtMemCtl(void)
|
|||
/* Enable the FMC/FSMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx */
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
|
|
@ -544,7 +549,7 @@ void SystemInit_ExtMemCtl(void)
|
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
||||
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||||
|
||||
|
|
@ -596,7 +601,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
|||
clocked below the maximum system frequency, to update the voltage scaling value
|
||||
regarding system frequency refer to product datasheet. */
|
||||
__PWR_CLK_ENABLE();
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||
|
||||
/* Enable HSE oscillator and activate PLL with HSE as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
|
|
@ -608,26 +613,27 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
|||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
|
||||
}
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
//RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
|
||||
RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
|
||||
RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 8;
|
||||
RCC_OscInitStruct.PLL.PLLN = 360;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 7;
|
||||
RCC_OscInitStruct.PLL.PLLR = 4;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
HAL_PWREx_ActivateOverDrive();
|
||||
|
||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ DigitalIn in(D2);
|
|||
defined(TARGET_NUCLEO_F334R8) || \
|
||||
defined(TARGET_NUCLEO_F401RE) || \
|
||||
defined(TARGET_NUCLEO_F411RE) || \
|
||||
defined(TARGET_NUCLEO_F446RE) || \
|
||||
defined(TARGET_NUCLEO_L053R8) || \
|
||||
defined(TARGET_NUCLEO_L073RZ) || \
|
||||
defined(TARGET_NUCLEO_L152RE)
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ DigitalInOut d2(D7);
|
|||
defined(TARGET_NUCLEO_F334R8) || \
|
||||
defined(TARGET_NUCLEO_F401RE) || \
|
||||
defined(TARGET_NUCLEO_F411RE) || \
|
||||
defined(TARGET_NUCLEO_F446RE) || \
|
||||
defined(TARGET_NUCLEO_L053R8) || \
|
||||
defined(TARGET_NUCLEO_L073RZ) || \
|
||||
defined(TARGET_NUCLEO_L152RE)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,84 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<Project version="2G - 1.7.5" name="{{name}}">
|
||||
<Target name="{{name}}" isCurrent="1">
|
||||
<Target name="Debug" isCurrent="1">
|
||||
<Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F446RE" boardId="" boardName=""/>
|
||||
<BuildOption>
|
||||
<Compile>
|
||||
<Option name="OptimizationLevel" value="0"/>
|
||||
<Option name="UseFPU" value="0"/>
|
||||
<Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
|
||||
<Option name="FPU" value="1"/>
|
||||
<Option name="SupportCPlusplus" value="1"/>
|
||||
<Includepaths>
|
||||
{% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
|
||||
</Includepaths>
|
||||
<DefinedSymbols>
|
||||
{% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
|
||||
</DefinedSymbols>
|
||||
</Compile>
|
||||
<Link useDefault="0">
|
||||
<Option name="DiscardUnusedSection" value="1"/>
|
||||
<Option name="UserEditLinkder" value=""/>
|
||||
<Option name="UseMemoryLayout" value="0"/>
|
||||
<Option name="LTO" value="0"/>
|
||||
<Option name="IsNewStartupCode" value="1"/>
|
||||
<Option name="Library" value="Not use C Library"/>
|
||||
<Option name="nostartfiles" value="0"/>
|
||||
<Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
|
||||
${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
|
||||
<LinkedLibraries>
|
||||
{% for lib in libraries %}
|
||||
<Libset dir="" libs="{{lib}}"/>
|
||||
{% endfor %}
|
||||
<Libset dir="" libs="stdc++"/>
|
||||
<Libset dir="" libs="supc++"/>
|
||||
<Libset dir="" libs="m"/>
|
||||
<Libset dir="" libs="gcc"/>
|
||||
<Libset dir="" libs="c"/>
|
||||
<Libset dir="" libs="nosys"/>
|
||||
</LinkedLibraries>
|
||||
<MemoryAreas debugInFlashNotRAM="1">
|
||||
<Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
|
||||
<Memory name="IRAM1" type="ReadWrite" size="0x0001FE68" startValue="0x20000198"/>
|
||||
<Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
|
||||
<Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
|
||||
</MemoryAreas>
|
||||
<LocateLinkFile path="{{scatter_file}}" type="0"/>
|
||||
</Link>
|
||||
<Output>
|
||||
<Option name="OutputFileType" value="0"/>
|
||||
<Option name="Path" value="./"/>
|
||||
<Option name="Name" value="{{name}}"/>
|
||||
<Option name="HEX" value="1"/>
|
||||
<Option name="BIN" value="1"/>
|
||||
</Output>
|
||||
<User>
|
||||
<UserRun name="Run#1" type="Before" checked="0" value=""/>
|
||||
<UserRun name="Run#1" type="After" checked="0" value=""/>
|
||||
</User>
|
||||
</BuildOption>
|
||||
<DebugOption>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_512.elf"/>
|
||||
</DebugOption>
|
||||
<ExcludeFile/>
|
||||
</Target>
|
||||
<Target name="Release" isCurrent="0">
|
||||
<Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F446RE" boardId="" boardName=""/>
|
||||
<BuildOption>
|
||||
<Compile>
|
||||
|
|
@ -24,7 +102,7 @@
|
|||
<Option name="IsNewStartupCode" value="1"/>
|
||||
<Option name="Library" value="Not use C Library"/>
|
||||
<Option name="nostartfiles" value="0"/>
|
||||
<Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
|
||||
<Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
|
||||
${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
|
||||
<LinkedLibraries>
|
||||
{% for lib in libraries %}
|
||||
|
|
|
|||
Loading…
Reference in New Issue