mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_F446RE] create new target - part 2
Update system_stm32f4xx to new version, generated by STM32CubeMX Add target name to digital_loop test Update coide export templatepull/1110/head
ohagendorf
parent
8edb20bed6
commit
455b417b8f
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@ -77,7 +77,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
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// Configure time base
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TimMasterHandle.Instance = TIM_MST;
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TimMasterHandle.Init.Period = 0xFFFFFFFF;
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TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
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TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
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TimMasterHandle.Init.ClockDivision = 0;
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TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
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TimMasterHandle.Init.RepetitionCounter = 0;
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file system_stm32f4xx.c
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* @author MCD Application Team
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* @version V2.1.0
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* @date 19-June-2014
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* @version V2.3.0
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* @date 02-March-2015
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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@ -27,20 +27,20 @@
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* | 2- PLL_HSE_XTAL |
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* | (external 8 MHz xtal) |
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*-----------------------------------------------------------------------------
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* SYSCLK(MHz) | 96 | 96
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* SYSCLK(MHz) | 180 | 16
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*-----------------------------------------------------------------------------
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* AHBCLK (MHz) | 96 | 96
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* AHBCLK (MHz) | 180 | 16
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*-----------------------------------------------------------------------------
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* APB1CLK (MHz) | 48 | 48
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* APB1CLK (MHz) | 45 | 4
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*-----------------------------------------------------------------------------
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* APB2CLK (MHz) | 96 | 96
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* APB2CLK (MHz) | 90 | 8
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*-----------------------------------------------------------------------------
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* USB capable (48 MHz precise clock) | YES | YES
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* USB capable (48 MHz precise clock) | YES | NO
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*-----------------------------------------------------------------------------
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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@ -108,15 +108,17 @@
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
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on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
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|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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|| defined(STM32F446xx)
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/* #define DATA_IN_ExtSRAM */
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F446xx */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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|| defined(STM32F446xx)
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/* #define DATA_IN_ExtSDRAM */
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
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#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
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#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
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@ -139,7 +141,7 @@
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/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
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#define USE_PLL_HSE_EXTC (1) /* Use external clock */
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#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
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#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
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/**
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* @}
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@ -156,8 +158,8 @@
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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uint32_t SystemCoreClock = 18000000;
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__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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@ -229,7 +231,7 @@ void SystemInit(void)
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#endif
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/* Configure the Cube driver */
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SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
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SystemCoreClock = 18000000; // At this stage the HSI is used as system clock
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HAL_Init();
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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@ -336,7 +338,7 @@ void SystemCoreClockUpdate(void)
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*/
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void SystemInit_ExtMemCtl(void)
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{
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
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#if defined (DATA_IN_ExtSDRAM)
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register uint32_t index;
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@ -422,7 +424,7 @@ void SystemInit_ExtMemCtl(void)
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RCC->AHB3ENR |= 0x00000001;
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/* Configure and enable SDRAM bank1 */
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FMC_Bank5_6->SDCR[0] = 0x000019E0;
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FMC_Bank5_6->SDCR[0] = 0x000019E4;
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FMC_Bank5_6->SDTR[0] = 0x01115351;
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/* SDRAM initialization sequence */
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@ -469,9 +471,12 @@ void SystemInit_ExtMemCtl(void)
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tmpreg = FMC_Bank5_6->SDCR[0];
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FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
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#endif /* DATA_IN_ExtSDRAM */
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
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|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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|| defined(STM32F446xx)
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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#if defined(DATA_IN_ExtSRAM)
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
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@ -529,12 +534,12 @@ void SystemInit_ExtMemCtl(void)
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/* Enable the FMC/FSMC interface clock */
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RCC->AHB3ENR |= 0x00000001;
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
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/* Configure and enable Bank1_SRAM2 */
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FMC_Bank1->BTCR[2] = 0x00001011;
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FMC_Bank1->BTCR[3] = 0x00000201;
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FMC_Bank1E->BWTR[2] = 0x0fffffff;
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
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/* Configure and enable Bank1_SRAM2 */
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@ -544,7 +549,7 @@ void SystemInit_ExtMemCtl(void)
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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#endif /* DATA_IN_ExtSRAM */
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
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}
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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@ -596,7 +601,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Enable HSE oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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@ -608,26 +613,27 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
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}
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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//RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
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//RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
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RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
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RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
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RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 360;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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RCC_OscInitStruct.PLL.PLLR = 4;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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return 0; // FAIL
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}
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HAL_PWREx_ActivateOverDrive();
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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return 0; // FAIL
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}
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@ -20,6 +20,7 @@ DigitalIn in(D2);
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defined(TARGET_NUCLEO_F334R8) || \
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defined(TARGET_NUCLEO_F401RE) || \
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defined(TARGET_NUCLEO_F411RE) || \
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defined(TARGET_NUCLEO_F446RE) || \
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defined(TARGET_NUCLEO_L053R8) || \
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defined(TARGET_NUCLEO_L073RZ) || \
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defined(TARGET_NUCLEO_L152RE)
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@ -20,6 +20,7 @@ DigitalInOut d2(D7);
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defined(TARGET_NUCLEO_F334R8) || \
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defined(TARGET_NUCLEO_F401RE) || \
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defined(TARGET_NUCLEO_F411RE) || \
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defined(TARGET_NUCLEO_F446RE) || \
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defined(TARGET_NUCLEO_L053R8) || \
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defined(TARGET_NUCLEO_L073RZ) || \
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defined(TARGET_NUCLEO_L152RE)
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@ -1,6 +1,84 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<Project version="2G - 1.7.5" name="{{name}}">
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<Target name="{{name}}" isCurrent="1">
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<Target name="Debug" isCurrent="1">
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<Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F446RE" boardId="" boardName=""/>
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<BuildOption>
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<Compile>
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<Option name="OptimizationLevel" value="0"/>
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<Option name="UseFPU" value="0"/>
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<Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
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<Option name="FPU" value="1"/>
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<Option name="SupportCPlusplus" value="1"/>
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<Includepaths>
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{% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
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</Includepaths>
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<DefinedSymbols>
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{% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
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</DefinedSymbols>
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</Compile>
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<Link useDefault="0">
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<Option name="DiscardUnusedSection" value="1"/>
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<Option name="UserEditLinkder" value=""/>
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<Option name="UseMemoryLayout" value="0"/>
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<Option name="LTO" value="0"/>
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<Option name="IsNewStartupCode" value="1"/>
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<Option name="Library" value="Not use C Library"/>
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<Option name="nostartfiles" value="0"/>
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<Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
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${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
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<LinkedLibraries>
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{% for lib in libraries %}
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<Libset dir="" libs="{{lib}}"/>
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{% endfor %}
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<Libset dir="" libs="stdc++"/>
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<Libset dir="" libs="supc++"/>
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<Libset dir="" libs="m"/>
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<Libset dir="" libs="gcc"/>
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<Libset dir="" libs="c"/>
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<Libset dir="" libs="nosys"/>
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</LinkedLibraries>
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<MemoryAreas debugInFlashNotRAM="1">
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<Memory name="IROM1" type="ReadOnly" size="0x00080000" startValue="0x08000000"/>
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<Memory name="IRAM1" type="ReadWrite" size="0x0001FE68" startValue="0x20000198"/>
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<Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
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<Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
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</MemoryAreas>
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<LocateLinkFile path="{{scatter_file}}" type="0"/>
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</Link>
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<Output>
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<Option name="OutputFileType" value="0"/>
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<Option name="Path" value="./"/>
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<Option name="Name" value="{{name}}"/>
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<Option name="HEX" value="1"/>
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<Option name="BIN" value="1"/>
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</Output>
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<User>
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<UserRun name="Run#1" type="Before" checked="0" value=""/>
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<UserRun name="Run#1" type="After" checked="0" value=""/>
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</User>
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</BuildOption>
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<DebugOption>
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<Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
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<Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
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<Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
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<Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
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<Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="stm32f4xx_512.elf"/>
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</DebugOption>
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<ExcludeFile/>
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</Target>
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<Target name="Release" isCurrent="0">
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<Device manufacturerId="9" manufacturerName="ST" chipId="499" chipName="STM32F446RE" boardId="" boardName=""/>
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<BuildOption>
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<Compile>
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@ -24,7 +102,7 @@
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<Option name="IsNewStartupCode" value="1"/>
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<Option name="Library" value="Not use C Library"/>
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<Option name="nostartfiles" value="0"/>
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||||
<Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
|
||||
<Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u_printf_float; -u_scanf_float; {% for file in object_files %}
|
||||
${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
|
||||
<LinkedLibraries>
|
||||
{% for lib in libraries %}
|
||||
|
|
|
|||
Loading…
Reference in New Issue