mirror of https://github.com/ARMmbed/mbed-os.git
STM32WL : I2C full support
parent
96e6d8bb7b
commit
4550f92565
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@ -37,36 +37,20 @@ extern "C" {
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static inline uint32_t get_i2c_timing(int hz)
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{
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uint32_t tim = 0;
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if (SystemCoreClock == 64000000) {
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// Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0
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switch (hz) {
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case 100000:
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tim = 0x10707DBC; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
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break;
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case 400000:
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tim = 0x00602173; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
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break;
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case 1000000:
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tim = 0x00300B29; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
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break;
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default:
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break;
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}
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} else if (SystemCoreClock == 32000000) {
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// Common settings: I2C clock = 32 MHz, Analog filter = ON, Digital filter coefficient = 0
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switch (hz) {
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case 100000:
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tim = 0x00707CBB; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
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break;
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case 400000:
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tim = 0x00300F38; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
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break;
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case 1000000:
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tim = 0x00100413; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
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break;
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default:
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break;
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}
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// Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
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switch (hz) {
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case 100000:
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tim = 0x20E03F53; // Standard mode with Rise Time = 640ns and Fall Time = 20ns
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break;
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case 400000:
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tim = 0x20500817; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
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break;
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case 1000000:
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tim = 0x00500A18; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
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break;
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default:
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break;
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}
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return tim;
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}
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@ -41,6 +41,7 @@
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#include "PeripheralPins.h"
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#include "i2c_device.h" // family specific defines
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#include "mbed_error.h"
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#include "platform/mbed_power_mgmt.h"
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#ifndef DEBUG_STDIO
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# define DEBUG_STDIO 0
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@ -294,6 +295,11 @@ void i2c_init_internal(i2c_t *obj, const i2c_pinmap_t *pinmap)
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// Configure I2C pins
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obj_s->event_i2cIRQ = I2C1_EV_IRQn;
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obj_s->error_i2cIRQ = I2C1_ER_IRQn;
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#if defined(TARGET_STM32WL)
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/* In Stop2 mode, I2C1 and I2C2 instances are powered down (only I2C3 register content is kept) */
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sleep_manager_lock_deep_sleep();
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#endif
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}
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#endif
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#if defined I2C2_BASE
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@ -303,6 +309,11 @@ void i2c_init_internal(i2c_t *obj, const i2c_pinmap_t *pinmap)
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__HAL_RCC_I2C2_CLK_ENABLE();
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obj_s->event_i2cIRQ = I2C2_EV_IRQn;
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obj_s->error_i2cIRQ = I2C2_ER_IRQn;
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#if defined(TARGET_STM32WL)
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/* In Stop2 mode, I2C1 and I2C2 instances are powered down (only I2C3 register content is kept) */
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sleep_manager_lock_deep_sleep();
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#endif
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}
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#endif
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#if defined I2C3_BASE
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@ -380,11 +391,17 @@ void i2c_deinit_internal(i2c_t *obj)
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#if defined I2C1_BASE
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if (obj_s->i2c == I2C_1) {
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__HAL_RCC_I2C1_CLK_DISABLE();
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#if defined(TARGET_STM32WL)
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sleep_manager_unlock_deep_sleep();
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#endif
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}
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#endif
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#if defined I2C2_BASE
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if (obj_s->i2c == I2C_2) {
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__HAL_RCC_I2C2_CLK_DISABLE();
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#if defined(TARGET_STM32WL)
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sleep_manager_unlock_deep_sleep();
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#endif
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}
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#endif
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#if defined I2C3_BASE
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@ -758,7 +775,7 @@ int i2c_byte_read(i2c_t *obj, int last)
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if ((tmpreg & I2C_CR2_RELOAD) != 0) {
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while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
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if ((timeout--) == 0) {
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DEBUG_PRINTF("timeout in byte_read\r\n");
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DEBUG_PRINTF("timeout in i2c_byte_read\r\n");
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return -1;
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}
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}
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@ -827,7 +844,7 @@ int i2c_byte_write(i2c_t *obj, int data)
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if ((tmpreg & I2C_CR2_RELOAD) != 0) {
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while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
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if ((timeout--) == 0) {
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DEBUG_PRINTF("timeout in byte_write\r\n");
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DEBUG_PRINTF("timeout in i2c_byte_write\r\n");
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return 2;
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}
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}
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@ -912,7 +929,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
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i2c_ev_err_disable(obj);
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if ((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
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DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
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DEBUG_PRINTF("TIMEOUT or error in i2c_read\r\n");
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/* re-init IP to try and get back in a working state */
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i2c_init_internal(obj, NULL);
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} else {
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@ -986,7 +1003,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
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count = length;
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}
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} else {
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DEBUG_PRINTF("ERROR in i2c_read\r\n");
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DEBUG_PRINTF("ERROR in i2c_write\r\n");
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}
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return count;
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