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Run astyle on all FPGA files 

Run astyle to correct formatting.
pull/10540/head
Russ Butler 2019-05-07 17:05:03 -05:00
parent 11bd96601b
commit 45301ea718
8 changed files with 75 additions and 78 deletions
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16
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/I2CTester.cpp
View File

@ -35,14 +35,14 @@ uint8_t I2CTester::num_stops()
uint16_t I2CTester::num_acks()
{
uint16_t num_acks = 0;
read(TESTER_I2C_ACKS, (uint8_t*)&num_acks, sizeof(num_acks));
read(TESTER_I2C_ACKS, (uint8_t *)&num_acks, sizeof(num_acks));
return num_acks;
}
uint16_t I2CTester::num_nacks()
{
uint16_t num_nacks = 0;
read(TESTER_I2C_NACKS, (uint8_t*)&num_nacks, sizeof(num_nacks));
read(TESTER_I2C_NACKS, (uint8_t *)&num_nacks, sizeof(num_nacks));
return num_nacks;
}
@ -50,7 +50,7 @@ uint16_t I2CTester::transfer_count()
{
uint16_t transfers = 0;
MBED_ASSERT(sizeof(transfers) == TESTER_I2C_TRANSFERS_SIZE);
read(TESTER_I2C_TRANSFERS, (uint8_t*)&transfers, sizeof(transfers));
read(TESTER_I2C_TRANSFERS, (uint8_t *)&transfers, sizeof(transfers));
return transfers;
}
@ -58,7 +58,7 @@ uint32_t I2CTester::get_receive_checksum()
{
uint32_t to_slave_checksum = 0;
MBED_ASSERT(sizeof(to_slave_checksum) == TESTER_I2C_TO_SLAVE_CHECKSUM_SIZE);
read(TESTER_I2C_TO_SLAVE_CHECKSUM, (uint8_t*)&to_slave_checksum, sizeof(to_slave_checksum));
read(TESTER_I2C_TO_SLAVE_CHECKSUM, (uint8_t *)&to_slave_checksum, sizeof(to_slave_checksum));
return to_slave_checksum;
}
@ -79,13 +79,13 @@ uint8_t I2CTester::num_dev_addr_matches()
void I2CTester::set_device_address(uint16_t addr)
{
uint16_t data = addr;
write(TESTER_I2C_DEVICE_ADDRESS, (uint8_t*)&data, sizeof(data));
write(TESTER_I2C_DEVICE_ADDRESS, (uint8_t *)&data, sizeof(data));
}
uint16_t I2CTester::get_device_address()
{
uint16_t addr = 0;
read(TESTER_I2C_DEVICE_ADDRESS, (uint8_t*)&addr, sizeof(addr));
read(TESTER_I2C_DEVICE_ADDRESS, (uint8_t *)&addr, sizeof(addr));
return addr;
}
@ -133,12 +133,12 @@ uint8_t I2CTester::get_next_from_slave()
uint16_t I2CTester::num_writes()
{
uint16_t num_writes = 0;
read(TESTER_I2C_NUM_WRITES, (uint8_t*)&num_writes, sizeof(num_writes));
read(TESTER_I2C_NUM_WRITES, (uint8_t *)&num_writes, sizeof(num_writes));
return num_writes;
}
uint16_t I2CTester::num_reads()
{
uint16_t num_reads = 0;
read(TESTER_I2C_NUM_READS, (uint8_t*)&num_reads, sizeof(num_reads));
read(TESTER_I2C_NUM_READS, (uint8_t *)&num_reads, sizeof(num_reads));
return num_reads;
}

69
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/MbedTester.cpp
View File

@ -46,27 +46,31 @@ template<size_t width>
class MbedTesterBitMap {
public:
MbedTesterBitMap() {
MbedTesterBitMap()
{
for (size_t i = 0; i < _count; i++) {
_bitmap[i] = 0;
}
}
bool get(size_t index) {
bool get(size_t index)
{
if (index >= width) {
return false;
}
return _bitmap[index / 32] & (1 << (index % 32)) ? true : false;
}
void set(size_t index) {
void set(size_t index)
{
if (index >= width) {
return;
}
_bitmap[index / 32] |= 1 << (index % 32);
}
void clear(size_t index) {
void clear(size_t index)
{
if (index >= width) {
return;
}
@ -142,7 +146,8 @@ class MbedTesterBlockDevice : public BlockDevice {
public:
MbedTesterBlockDevice(mbed::DigitalInOut &mosi, mbed::DigitalInOut &miso, mbed::DigitalInOut &clk, mbed::DigitalInOut &cs, uint32_t frequency)
: _mosi(mosi), _miso(miso), _clk(clk), _cs(cs), _wait_ns(1000000000 / frequency / 2), _init(false) {
: _mosi(mosi), _miso(miso), _clk(clk), _cs(cs), _wait_ns(1000000000 / frequency / 2), _init(false)
{
// Set initial values
_cs.write(1);
@ -397,7 +402,8 @@ protected:
return true;
}
void _write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
void _write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length)
{
int transfers = 0;
if (tx_length > transfers) {
transfers = tx_length;
@ -426,7 +432,8 @@ protected:
}
}
void _assert_cs(bool asserted) {
void _assert_cs(bool asserted)
{
_clk = 0;
wait_ns(_wait_ns);
_cs = asserted ? 0 : 1;
@ -649,8 +656,8 @@ bool MbedTester::firmware_dump(mbed::FileHandle *dest, mbed::Callback<void(uint8
// Mapping intentionally different from control channel to prevent
// unintentional activation (clk and mosi flipped)
MbedTesterBlockDevice flash(*_clk, *_miso , *_mosi, *_aux, FLASH_SPI_FREQ_HZ);
sys_pin_mode_spi_serial_flash(_clk_index , _miso_index, _mosi_index, _aux_index);
MbedTesterBlockDevice flash(*_clk, *_miso, *_mosi, *_aux, FLASH_SPI_FREQ_HZ);
sys_pin_mode_spi_serial_flash(_clk_index, _miso_index, _mosi_index, _aux_index);
progress(0);
@ -730,8 +737,8 @@ bool MbedTester::firmware_dump_all(mbed::FileHandle *dest, mbed::Callback<void(u
// Mapping intentionally different from control channel to prevent
// unintentional activation (clk and mosi flipped)
MbedTesterBlockDevice flash(*_clk, *_miso , *_mosi, *_aux, FLASH_SPI_FREQ_HZ);
sys_pin_mode_spi_serial_flash(_clk_index , _miso_index, _mosi_index, _aux_index);
MbedTesterBlockDevice flash(*_clk, *_miso, *_mosi, *_aux, FLASH_SPI_FREQ_HZ);
sys_pin_mode_spi_serial_flash(_clk_index, _miso_index, _mosi_index, _aux_index);
progress(0);
@ -783,8 +790,8 @@ bool MbedTester::firmware_update(mbed::FileHandle *src, mbed::Callback<void(uint
// Mapping intentionally different from control channel to prevent
// unintentional activation (clk and mosi flipped)
MbedTesterBlockDevice flash(*_clk, *_miso , *_mosi, *_aux, FLASH_SPI_FREQ_HZ);
sys_pin_mode_spi_serial_flash(_clk_index , _miso_index, _mosi_index, _aux_index);
MbedTesterBlockDevice flash(*_clk, *_miso, *_mosi, *_aux, FLASH_SPI_FREQ_HZ);
sys_pin_mode_spi_serial_flash(_clk_index, _miso_index, _mosi_index, _aux_index);
progress(0);
@ -1258,7 +1265,7 @@ int MbedTester::io_expander_i2c_read(uint8_t i2c_index, uint8_t dev_addr, uint8_
*scl_val = 0;
wait_ns(2500);
} else {
if (j == (length-1)) {//NACK to signal end of read
if (j == (length - 1)) { //NACK to signal end of read
*sda_val = 1;
wait_ns(1000);
*scl_val = 1;
@ -1458,8 +1465,8 @@ uint8_t MbedTester::io_expander_read_bb(PinName pin, IOExpanderReg reg_type)
sda = I2CSda2;
scl = I2CScl2;
} else {
sda = (SystemPin)-1;
scl = (SystemPin)-1;
sda = (SystemPin) - 1;
scl = (SystemPin) - 1;
error("Invalid pin index, index should be in the range of 0-127");
}
@ -1567,7 +1574,7 @@ int MbedTester::io_expander_i2c_read_bb(SystemPin sda, SystemPin scl, uint8_t de
}
sys_pin_write(scl, 0, true);
} else {
if (j == (length-1)) {//NACK to signal end of read
if (j == (length - 1)) { //NACK to signal end of read
sys_pin_write(sda, 0, false);
sys_pin_write(scl, 0, false);
sys_pin_write(scl, 0, true);
@ -1666,8 +1673,7 @@ void MbedTester::set_mux_enable(bool val)
{
if (val == true) {
sys_pin_write(AnalogMuxEnable, 1, true);
}
else if (val == false) {
} else if (val == false) {
sys_pin_write(AnalogMuxEnable, 0, true);
}
wait_us(10);
@ -1678,8 +1684,7 @@ void MbedTester::set_pwm_enable(bool val)
uint8_t data;
if (val == true) {
data = 1;
}
else if (val == false) {
} else if (val == false) {
data = 0;
}
write(TESTER_SYS_IO_PWM_ENABLE, &data, sizeof(data));
@ -1691,8 +1696,7 @@ bool MbedTester::get_pwm_enable()
read(TESTER_SYS_IO_PWM_ENABLE, &val, sizeof(val));
if (val == 1) {
return true;
}
else if (val == 0) {
} else if (val == 0) {
return false;
} else {
error("Corrupt pwm enable value");
@ -1705,15 +1709,15 @@ void MbedTester::set_pwm_period_and_cycles_high(uint32_t period, uint32_t cycles
set_pwm_enable(false);
uint32_t p = period - 1;//period in cycles
uint32_t d = cycles_high;//number of cycles pwm out is high
write(TESTER_SYS_IO_PWM_PERIOD, (uint8_t*)&p, sizeof(p));
write(TESTER_SYS_IO_PWM_CYCLES_HIGH, (uint8_t*)&d, sizeof(d));
write(TESTER_SYS_IO_PWM_PERIOD, (uint8_t *)&p, sizeof(p));
write(TESTER_SYS_IO_PWM_CYCLES_HIGH, (uint8_t *)&d, sizeof(d));
set_pwm_enable(true);
}
uint32_t MbedTester::get_pwm_period()
{
uint32_t period = 0;
read(TESTER_SYS_IO_PWM_PERIOD, (uint8_t*)&period, sizeof(period));
read(TESTER_SYS_IO_PWM_PERIOD, (uint8_t *)&period, sizeof(period));
return period + 1;//clk cycles
}
@ -1730,7 +1734,7 @@ uint16_t MbedTester::get_analogmuxin_measurement()
//take snapshot of conversion value to make safe for reading
set_snapshot();
uint16_t an_mux_analogin_measurement = 0;
read(TESTER_SYS_AN_MUX_ANALOGIN_MEASUREMENT, (uint8_t*)&an_mux_analogin_measurement, sizeof(an_mux_analogin_measurement));
read(TESTER_SYS_AN_MUX_ANALOGIN_MEASUREMENT, (uint8_t *)&an_mux_analogin_measurement, sizeof(an_mux_analogin_measurement));
return an_mux_analogin_measurement;
}
@ -1743,7 +1747,7 @@ uint16_t MbedTester::get_anin_measurement(int index)
//take snapshot of conversion value to make safe for reading
set_snapshot();
uint16_t anin_measurement = 0;
read((TESTER_SYS_ANIN0_MEASUREMENT + (index * 10)), (uint8_t*)&anin_measurement, sizeof(anin_measurement));//10 because sizeof measurement + sizeof measurements_sum = 10
read((TESTER_SYS_ANIN0_MEASUREMENT + (index * 10)), (uint8_t *)&anin_measurement, sizeof(anin_measurement)); //10 because sizeof measurement + sizeof measurements_sum = 10
return anin_measurement;
}
@ -1755,9 +1759,9 @@ void MbedTester::get_anin_sum_samples_cycles(int index, uint64_t *sum, uint32_t
}
//take snapshot of the sum/samples/cycles so that all 3 values are correct in relation to each other
set_snapshot();
read((TESTER_SYS_ANIN0_MEASUREMENTS_SUM + (index * 10)), (uint8_t*)sum, sizeof(*sum));//10 because sizeof measurement + sizeof measurements_sum = 10
read(TESTER_SYS_NUM_POWER_SAMPLES, (uint8_t*)samples, sizeof(*samples));
read(TESTER_SYS_NUM_POWER_CYCLES, (uint8_t*)cycles, sizeof(*cycles));
read((TESTER_SYS_ANIN0_MEASUREMENTS_SUM + (index * 10)), (uint8_t *)sum, sizeof(*sum)); //10 because sizeof measurement + sizeof measurements_sum = 10
read(TESTER_SYS_NUM_POWER_SAMPLES, (uint8_t *)samples, sizeof(*samples));
read(TESTER_SYS_NUM_POWER_CYCLES, (uint8_t *)cycles, sizeof(*cycles));
}
void MbedTester::set_snapshot()
@ -1772,8 +1776,7 @@ void MbedTester::set_sample_adc(bool val)
uint8_t data;
if (val == true) {
data = 1;
}
else if (val == false) {
} else if (val == false) {
data = 0;
}
write(TESTER_SYS_SAMPLE_ADC, &data, sizeof(data));

4
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.cpp
View File

@ -56,7 +56,7 @@ void SPIMasterTester::set_hd_tx_rx_cnt(uint16_t tx_cnt, uint16_t rx_cnt)
uint32_t SPIMasterTester::get_cs_to_first_clk_edge_ns()
{
uint32_t delay_ns;
read(TESTER_SPI_MASTER_CS_TO_FIRST_SCLK_CNT, (uint8_t*)&delay_ns, TESTER_SPI_MASTER_CS_TO_FIRST_SCLK_CNT_SIZE);
read(TESTER_SPI_MASTER_CS_TO_FIRST_SCLK_CNT, (uint8_t *)&delay_ns, TESTER_SPI_MASTER_CS_TO_FIRST_SCLK_CNT_SIZE);
return (delay_ns * 10);
}
@ -64,7 +64,7 @@ uint32_t SPIMasterTester::get_cs_to_first_clk_edge_ns()
uint32_t SPIMasterTester::get_last_clk_edge_to_cs_ns()
{
uint32_t delay_ns;
read(TESTER_SPI_MASTER_LAST_SCLK_TO_CS_CNT, (uint8_t*)&delay_ns, TESTER_SPI_MASTER_LAST_SCLK_TO_CS_CNT_SIZE);
read(TESTER_SPI_MASTER_LAST_SCLK_TO_CS_CNT, (uint8_t *)&delay_ns, TESTER_SPI_MASTER_LAST_SCLK_TO_CS_CNT_SIZE);
return (delay_ns * 10);
}

12
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPISlaveTester.cpp
View File

@ -55,30 +55,30 @@ void SPISlaveTester::set_hd_tx_rx_cnt(uint16_t tx_cnt, uint16_t rx_cnt)
void SPISlaveTester::set_spi_master_freq(uint16_t clk_div)
{
write(TESTER_SPI_SLAVE_CLK_DIV, (uint8_t*)&clk_div, TESTER_SPI_SLAVE_CLK_DIV_SIZE);
write(TESTER_SPI_SLAVE_CLK_DIV, (uint8_t *)&clk_div, TESTER_SPI_SLAVE_CLK_DIV_SIZE);
}
void SPISlaveTester::set_num_of_symbols(uint16_t num_of_sym)
{
write(TESTER_SPI_SLAVE_NUM_OF_SYMBOLS, (uint8_t*)&num_of_sym, TESTER_SPI_SLAVE_NUM_OF_SYMBOLS_SIZE);
write(TESTER_SPI_SLAVE_NUM_OF_SYMBOLS, (uint8_t *)&num_of_sym, TESTER_SPI_SLAVE_NUM_OF_SYMBOLS_SIZE);
}
void SPISlaveTester::set_start_delay_us(uint8_t start_delay_us)
{
write(TESTER_SPI_SLAVE_START_DELAY_US, (uint8_t*)&start_delay_us, TESTER_SPI_SLAVE_START_DELAY_US_SIZE);
write(TESTER_SPI_SLAVE_START_DELAY_US, (uint8_t *)&start_delay_us, TESTER_SPI_SLAVE_START_DELAY_US_SIZE);
}
void SPISlaveTester::set_sym_delay_ns(uint16_t sym_delay_ns)
{
const uint16_t sym_delay_ticks = (sym_delay_ns + 9) / 10; // round up
write(TESTER_SPI_SLAVE_SYM_DELAY_TICKS, (uint8_t*)&sym_delay_ticks, TESTER_SPI_SLAVE_SYM_DELAY_TICKS_SIZE);
write(TESTER_SPI_SLAVE_SYM_DELAY_TICKS, (uint8_t *)&sym_delay_ticks, TESTER_SPI_SLAVE_SYM_DELAY_TICKS_SIZE);
}
void SPISlaveTester::start_transfer()
{
uint32_t spi_ctrl = 0;
read(TESTER_SPI_SLAVE_CTRL, (uint8_t*)&spi_ctrl, TESTER_SPI_SLAVE_CTRL_SIZE);
read(TESTER_SPI_SLAVE_CTRL, (uint8_t *)&spi_ctrl, TESTER_SPI_SLAVE_CTRL_SIZE);
spi_ctrl &= ~(((1 << TESTER_SPI_SLAVE_START_REQUEST_SIZE) - 1) << TESTER_SPI_SLAVE_START_REQUEST_OFFSET);
spi_ctrl |= (1 << TESTER_SPI_SLAVE_START_REQUEST_OFFSET);
write(TESTER_SPI_SLAVE_CTRL, (uint8_t*)&spi_ctrl, TESTER_SPI_SLAVE_CTRL_SIZE);
write(TESTER_SPI_SLAVE_CTRL, (uint8_t *)&spi_ctrl, TESTER_SPI_SLAVE_CTRL_SIZE);
}

20
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPITester.cpp
View File

@ -37,41 +37,41 @@ uint32_t SPITester::get_receive_checksum(uint32_t addr_checksum, uint32_t size_c
void SPITester::set_mode(SPITester::SpiMode mode, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_clk_mode, uint32_t size_clk_mode)
{
uint32_t spi_ctrl = 0;
read(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
read(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
spi_ctrl &= ~(((1 << size_clk_mode) - 1) << offset_clk_mode);
spi_ctrl |= (mode << offset_clk_mode);
write(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
write(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
}
void SPITester::set_bit_order(SPITester::SpiBitOrder bit_order, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_bit_order, uint32_t size_bit_order)
{
uint32_t spi_ctrl = 0;
read(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
read(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
spi_ctrl &= ~(((1 << size_bit_order) - 1) << offset_bit_order);
spi_ctrl |= (bit_order << offset_bit_order);
write(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
write(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
}
void SPITester::set_sym_size(uint32_t sym_size, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_sym_size, uint32_t size_sym_size)
{
uint32_t spi_ctrl = 0;
read(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
read(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
spi_ctrl &= ~(((1 << size_sym_size) - 1) << offset_sym_size) ;
spi_ctrl |= (sym_size << offset_sym_size);
write(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
write(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
}
void SPITester::set_duplex_mode(SPITester::SpiDuplex duplex, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_duplex, uint32_t size_duplex)
{
uint32_t spi_ctrl = 0;
read(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
read(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
spi_ctrl &= ~(((1 << size_duplex) - 1) << offset_duplex);
spi_ctrl |= (duplex << offset_duplex);
write(addr_spi_ctrl, (uint8_t*)&spi_ctrl, size_spi_ctrl);
write(addr_spi_ctrl, (uint8_t *)&spi_ctrl, size_spi_ctrl);
}
void SPITester::set_hd_tx_rx_cnt(uint16_t tx_cnt, uint16_t rx_cnt, uint32_t addr_hd_rx_cnt, uint32_t size_hd_rx_cnt, uint32_t addr_hd_tx_cnt, uint32_t size_hd_tx_cnt)
{
write(addr_hd_rx_cnt, (uint8_t*)&rx_cnt, size_hd_rx_cnt);
write(addr_hd_tx_cnt, (uint8_t*)&tx_cnt, size_hd_tx_cnt);
write(addr_hd_rx_cnt, (uint8_t *)&rx_cnt, size_hd_rx_cnt);
write(addr_hd_tx_cnt, (uint8_t *)&tx_cnt, size_hd_tx_cnt);
}

2
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/UARTTester.h
View File

@ -119,7 +119,7 @@ public:
/**
* Start UART transmission
*/
void tx_start(bool cts_enabled=false);
void tx_start(bool cts_enabled = false);
/**
* Stop UART transmission

18
components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h
View File

@ -28,14 +28,12 @@ typedef void (*TF4)(PinName p0, PinName p1, PinName p2, PinName p3);
typedef void (*TF5)(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4);
template<typename PortType, typename FunctionType, FunctionType f>
struct FunctionCaller
{
struct FunctionCaller {
};
template<typename PortType, TF1 f>
struct FunctionCaller<PortType, TF1, f>
{
struct FunctionCaller<PortType, TF1, f> {
void operator()(PortType &port)
{
f(port.pins[0]);
@ -43,8 +41,7 @@ struct FunctionCaller<PortType, TF1, f>
};
template<typename PortType, TF2 f>
struct FunctionCaller<PortType, TF2, f>
{
struct FunctionCaller<PortType, TF2, f> {
void operator()(PortType &port)
{
f(port.pins[0], port.pins[1]);
@ -52,8 +49,7 @@ struct FunctionCaller<PortType, TF2, f>
};
template<typename PortType, TF3 f>
struct FunctionCaller<PortType, TF3, f>
{
struct FunctionCaller<PortType, TF3, f> {
void operator()(PortType &port)
{
f(port.pins[0], port.pins[1], port.pins[2]);
@ -61,8 +57,7 @@ struct FunctionCaller<PortType, TF3, f>
};
template<typename PortType, TF4 f>
struct FunctionCaller<PortType, TF4, f>
{
struct FunctionCaller<PortType, TF4, f> {
void operator()(PortType &port)
{
f(port.pins[0], port.pins[1], port.pins[2], port.pins[3]);
@ -70,8 +65,7 @@ struct FunctionCaller<PortType, TF4, f>
};
template<typename PortType, TF5 f>
struct FunctionCaller<PortType, TF5, f>
{
struct FunctionCaller<PortType, TF5, f> {
void operator()(PortType &port)
{
f(port.pins[0], port.pins[1], port.pins[2], port.pins[3], port.pins[4]);