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Style Format for GD32F30x standard peripheral files

pull/9208/head
c_jin 2018-12-07 17:00:10 +08:00 committed by Cruz Monrreal II
parent 07698022fd
commit 44cd38cdfe
48 changed files with 4527 additions and 4591 deletions
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3
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h
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@ -146,8 +146,7 @@ OF SUCH DAMAGE.
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */
/* BKP data register number */
typedef enum
{
typedef enum {
BKP_DATA_0 = 1, /*!< BKP data register 0 */
BKP_DATA_1, /*!< BKP data register 1 */
BKP_DATA_2, /*!< BKP data register 2 */

24
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h
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@ -327,8 +327,7 @@ OF SUCH DAMAGE.
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
/* CAN flags */
typedef enum
{
typedef enum {
/* flags in TSTAT register */
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
@ -349,8 +348,7 @@ typedef enum
} can_flag_enum;
/* CAN interrupt flags */
typedef enum
{
typedef enum {
/* interrupt flags in STAT register */
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
@ -368,8 +366,7 @@ typedef enum
} can_interrupt_flag_enum;
/* CAN initiliaze parameters struct */
typedef struct
{
typedef struct {
uint8_t working_mode; /*!< CAN working mode */
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
uint8_t time_segment_1; /*!< time segment 1 */
@ -384,8 +381,7 @@ typedef struct
} can_parameter_struct;
/* CAN transmit message struct */
typedef struct
{
typedef struct {
uint32_t tx_sfid; /*!< standard format frame identifier */
uint32_t tx_efid; /*!< extended format frame identifier */
uint8_t tx_ff; /*!< format of frame, standard or extended format */
@ -395,8 +391,7 @@ typedef struct
} can_trasnmit_message_struct;
/* CAN receive message struct */
typedef struct
{
typedef struct {
uint32_t rx_sfid; /*!< standard format frame identifier */
uint32_t rx_efid; /*!< extended format frame identifier */
uint8_t rx_ff; /*!< format of frame, standard or extended format */
@ -407,8 +402,7 @@ typedef struct
} can_receive_message_struct;
/* CAN filter parameters struct */
typedef struct
{
typedef struct {
uint16_t filter_list_high; /*!< filter list number high bits*/
uint16_t filter_list_low; /*!< filter list number low bits */
uint16_t filter_mask_high; /*!< filter mask number high bits */
@ -421,8 +415,7 @@ typedef struct
} can_filter_parameter_struct;
/* CAN errors */
typedef enum
{
typedef enum {
CAN_ERROR_NONE = 0, /*!< no error */
CAN_ERROR_FILL, /*!< fill error */
CAN_ERROR_FORMATE, /*!< format error */
@ -434,8 +427,7 @@ typedef enum
} can_error_enum;
/* transmit states */
typedef enum
{
typedef enum {
CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */
CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */
CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */

3
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h
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@ -86,8 +86,7 @@ OF SUCH DAMAGE.
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
typedef enum
{
typedef enum {
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */

6
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h
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@ -120,8 +120,7 @@ OF SUCH DAMAGE.
/* constants definitions */
/* DMA channel select */
typedef enum
{
typedef enum {
DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */
@ -132,8 +131,7 @@ typedef enum
} dma_channel_enum;
/* DMA initialize struct */
typedef struct
{
typedef struct {
uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t memory_addr; /*!< memory base address */

63
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h
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@ -657,8 +657,7 @@ OF SUCH DAMAGE.
#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */
/* ENET status flag get */
typedef enum
{
typedef enum {
/* ENET_MAC_WUM register */
ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */
ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */
@ -706,8 +705,7 @@ typedef enum
} enet_flag_enum;
/* ENET stutus flag clear */
typedef enum
{
typedef enum {
/* ENET_DMA_STAT register */
ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
@ -727,8 +725,7 @@ typedef enum
} enet_flag_clear_enum;
/* ENET interrupt enable/disable */
typedef enum
{
typedef enum {
/* ENET_MAC_INTMSK register */
ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */
ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */
@ -759,8 +756,7 @@ typedef enum
} enet_int_enum;
/* ENET interrupt flag get */
typedef enum
{
typedef enum {
/* ENET_MAC_INTF register */
ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */
ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */
@ -797,8 +793,7 @@ typedef enum
} enet_int_flag_enum;
/* ENET interrupt flag clear */
typedef enum
{
typedef enum {
/* ENET_DMA_STAT register */
ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
@ -818,8 +813,7 @@ typedef enum
} enet_int_flag_clear_enum;
/* current RX/TX descriptor/buffer/descriptor table address get */
typedef enum
{
typedef enum {
ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */
ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */
ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */
@ -829,8 +823,7 @@ typedef enum
} enet_desc_reg_enum;
/* MAC statistics counter get */
typedef enum
{
typedef enum {
ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */
ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */
ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */
@ -840,8 +833,7 @@ typedef enum
} enet_msc_counter_enum;
/* function option, used for ENET initialization */
typedef enum
{
typedef enum {
FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */
DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */
DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */
@ -859,8 +851,7 @@ typedef enum
} enet_option_enum;
/* phy mode and mac loopback configurations */
typedef enum
{
typedef enum {
ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */
ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */
ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD, /*!< 100Mbit/s, half-duplex */
@ -870,8 +861,7 @@ typedef enum
} enet_mediamode_enum;
/* IP frame checksum function */
typedef enum
{
typedef enum {
ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */
ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */
ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO | ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame
@ -879,8 +869,7 @@ typedef enum
} enet_chksumconf_enum;
/* received frame filter function */
typedef enum
{
typedef enum {
ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */
ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */
ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */
@ -888,8 +877,7 @@ typedef enum
} enet_frmrecept_enum;
/* register group value get */
typedef enum
{
typedef enum {
ALL_MAC_REG = 0, /*!< MAC register group */
ALL_MSC_REG = 22, /*!< MSC register group */
ALL_PTP_REG = 33, /*!< PTP register group */
@ -897,29 +885,25 @@ typedef enum
} enet_registers_type_enum;
/* dma direction select */
typedef enum
{
typedef enum {
ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */
ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */
} enet_dmadirection_enum;
/* PHY operation direction select */
typedef enum
{
typedef enum {
ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */
ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */
} enet_phydirection_enum;
/* register operation direction select */
typedef enum
{
typedef enum {
ENET_REG_READ, /*!< read register */
ENET_REG_WRITE /*!< write register */
} enet_regdirection_enum;
/* ENET MAC addresses */
typedef enum
{
typedef enum {
ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */
ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */
ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */
@ -927,8 +911,7 @@ typedef enum
} enet_macaddress_enum;
/* descriptor information */
typedef enum
{
typedef enum {
TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */
TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */
RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */
@ -938,16 +921,14 @@ typedef enum
} enet_descstate_enum;
/* MSC counters preset mode */
typedef enum
{
typedef enum {
ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */
ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */
ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */
} enet_msc_preset_enum;
/* structure for initialization of the ENET */
typedef struct
{
typedef struct {
uint32_t option_enable; /*!< select which function to configure */
uint32_t forward_frame; /*!< frame forward related parameters */
uint32_t dmabus_mode; /*!< DMA bus mode related parameters */
@ -966,8 +947,7 @@ typedef struct
} enet_initpara_struct;
/* structure for ENET DMA desciptors */
typedef struct
{
typedef struct {
uint32_t status; /*!< status */
uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */
uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */
@ -983,8 +963,7 @@ typedef struct
} enet_descriptors_struct;
/* structure of PTP system time */
typedef struct
{
typedef struct {
uint32_t second; /*!< second of system time */
uint32_t nanosecond; /*!< nanosecond of system time */
uint32_t sign; /*!< sign of system time */

15
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h
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@ -155,8 +155,7 @@ OF SUCH DAMAGE.
/* constants definitions */
/* EXMC NOR/SRAM timing initialize struct */
typedef struct
{
typedef struct {
uint32_t asyn_access_mode; /*!< asynchronous access mode */
uint32_t syn_data_latency; /*!< configure the data latency */
uint32_t syn_clk_division; /*!< configure the clock divide ratio */
@ -167,8 +166,7 @@ typedef struct
} exmc_norsram_timing_parameter_struct;
/* EXMC NOR/SRAM initialize struct */
typedef struct
{
typedef struct {
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
uint32_t extended_mode; /*!< enable or disable the extended mode */
@ -188,8 +186,7 @@ typedef struct
} exmc_norsram_parameter_struct;
/* EXMC NAND/PC card timing initialize struct */
typedef struct
{
typedef struct {
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
uint32_t waittime; /*!< configure the minimum wait time */
@ -197,8 +194,7 @@ typedef struct
} exmc_nand_pccard_timing_parameter_struct;
/* EXMC NAND initialize struct */
typedef struct
{
typedef struct {
uint32_t nand_bank; /*!< select the bank of NAND */
uint32_t ecc_size; /*!< the page size for the ECC calculation */
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
@ -211,8 +207,7 @@ typedef struct
} exmc_nand_parameter_struct;
/* EXMC PC card initialize struct */
typedef struct
{
typedef struct {
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
uint32_t wait_feature; /*!< enables or disables the Wait feature */

9
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h
View File

@ -185,8 +185,7 @@ OF SUCH DAMAGE.
/* constants definitions */
/* EXTI line number */
typedef enum
{
typedef enum {
EXTI_0 = BIT(0), /*!< EXTI line 0 */
EXTI_1 = BIT(1), /*!< EXTI line 1 */
EXTI_2 = BIT(2), /*!< EXTI line 2 */
@ -210,15 +209,13 @@ typedef enum
} exti_line_enum;
/* external interrupt and event */
typedef enum
{
typedef enum {
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
EXTI_EVENT /*!< EXTI event mode */
} exti_mode_enum;
/* interrupt trigger mode */
typedef enum
{
typedef enum {
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */

12
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h
View File

@ -152,8 +152,7 @@ OF SUCH DAMAGE.
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
/* fmc state */
typedef enum
{
typedef enum {
FMC_READY, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */
FMC_PGERR, /*!< program error */
@ -162,8 +161,7 @@ typedef enum
} fmc_state_enum;
/* FMC interrupt enable */
typedef enum
{
typedef enum {
FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */
@ -171,8 +169,7 @@ typedef enum
} fmc_int_enum;
/* FMC flags */
typedef enum
{
typedef enum {
FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */
FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */
FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */
@ -185,8 +182,7 @@ typedef enum
} fmc_flag_enum;
/* FMC interrupt flags */
typedef enum
{
typedef enum {
FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */
FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */
FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */

3
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h
View File

@ -262,8 +262,7 @@ OF SUCH DAMAGE.
#define SLAVE10_FIRST_BYTE(addr10) ((0xF0) | (uint8_t)((addr10 & 0x0300)>>7))
#define SLAVE10_SECOND_BYTE(addr10) ((uint8_t)(addr10 & 0x00FF))
typedef enum
{
typedef enum {
I2C_MODE_NONE = 0x00U, /*!< I2C device is idle */
I2C_MODE_MASTER = 0x10U, /*!< I2C device is in Master Mode */
I2C_MODE_SLAVE = 0x20U /*!< I2C device is in Slave Mode */

27
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h
View File

@ -416,8 +416,7 @@ OF SUCH DAMAGE.
#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */
/* peripheral clock enable */
typedef enum
{
typedef enum {
/* AHB peripherals */
RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */
RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */
@ -492,16 +491,14 @@ typedef enum
} rcu_periph_enum;
/* peripheral clock enable when sleep mode*/
typedef enum
{
typedef enum {
/* AHB peripherals */
RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */
RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */
} rcu_periph_sleep_enum;
/* peripherals reset */
typedef enum
{
typedef enum {
/* AHB peripherals */
#ifdef GD32F30X_CL
RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
@ -567,8 +564,7 @@ typedef enum
} rcu_periph_reset_enum;
/* clock stabilization and peripheral reset flags */
typedef enum
{
typedef enum {
/* clock stabilization flags */
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */
RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */
@ -590,8 +586,7 @@ typedef enum
} rcu_flag_enum;
/* clock stabilization and ckm interrupt flags */
typedef enum
{
typedef enum {
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */
RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */
RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */
@ -606,8 +601,7 @@ typedef enum
} rcu_int_flag_enum;
/* clock stabilization and stuck interrupt flags clear */
typedef enum
{
typedef enum {
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */
@ -622,8 +616,7 @@ typedef enum
} rcu_int_flag_clear_enum;
/* clock stabilization interrupt enable or disable */
typedef enum
{
typedef enum {
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */
RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */
RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */
@ -637,8 +630,7 @@ typedef enum
} rcu_int_enum;
/* oscillator types */
typedef enum
{
typedef enum {
RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */
RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */
RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */
@ -652,8 +644,7 @@ typedef enum
} rcu_osci_type_enum;
/* rcu clock frequency */
typedef enum
{
typedef enum {
CK_SYS = 0, /*!< system clock */
CK_AHB, /*!< AHB clock */
CK_APB1, /*!< APB1 clock */

3
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h
View File

@ -128,8 +128,7 @@ OF SUCH DAMAGE.
/* constants definitions */
/* SPI and I2S parameter struct definitions */
typedef struct
{
typedef struct {
uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */
uint32_t frame_size; /*!< SPI frame size */

12
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h
View File

@ -256,8 +256,7 @@ OF SUCH DAMAGE.
/* constants definitions */
/* TIMER init parameter struct definitions*/
typedef struct
{
typedef struct {
uint16_t prescaler; /*!< prescaler value */
uint16_t alignedmode; /*!< aligned mode */
uint16_t counterdirection; /*!< counter direction */
@ -267,8 +266,7 @@ typedef struct
} timer_parameter_struct;
/* break parameter struct definitions*/
typedef struct
{
typedef struct {
uint16_t runoffstate; /*!< run mode off-state */
uint32_t ideloffstate; /*!< idle mode off-state */
uint16_t deadtime; /*!< dead time */
@ -279,8 +277,7 @@ typedef struct
} timer_break_parameter_struct;
/* channel output parameter struct definitions */
typedef struct
{
typedef struct {
uint32_t outputstate; /*!< channel output state */
uint16_t outputnstate; /*!< channel complementary output state */
uint16_t ocpolarity; /*!< channel output polarity */
@ -290,8 +287,7 @@ typedef struct
} timer_oc_parameter_struct;
/* channel input parameter struct definitions */
typedef struct
{
typedef struct {
uint16_t icpolarity; /*!< channel input polarity */
uint16_t icselection; /*!< channel input mode selection */
uint16_t icprescaler; /*!< channel input capture prescaler */

12
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h
View File

@ -160,8 +160,7 @@ OF SUCH DAMAGE.
#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */
/* USART flags */
typedef enum
{
typedef enum {
/* flags in STAT0 register */
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */
@ -180,8 +179,7 @@ typedef enum
} usart_flag_enum;
/* USART interrupt flags */
typedef enum
{
typedef enum {
/* interrupt flags in CTL0 register */
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
@ -202,8 +200,7 @@ typedef enum
} usart_interrupt_flag_enum;
/* USART interrupt enable or disable */
typedef enum
{
typedef enum {
/* interrupt in CTL0 register */
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
@ -221,8 +218,7 @@ typedef enum
} usart_interrupt_enum;
/* USART invert configure */
typedef enum
{
typedef enum {
/* data bit level inversion */
USART_DINV_ENABLE, /*!< data bit level inversion */
USART_DINV_DISABLE, /*!< data bit level not inversion */

6
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c
View File

@ -88,7 +88,8 @@ static const uint16_t enet_reg_tab[] = {
0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C,
0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048,
0x104C, 0x1050, 0x1054};
0x104C, 0x1050, 0x1054
};
/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */
static void enet_default_init(void);
@ -1604,8 +1605,7 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add
do {
phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
timeout++;
}
while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
} while ((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
/* write/read operation complete */
if (RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) {