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Style Format for GD32F30x standard peripheral files

pull/9208/head
c_jin 2018-12-07 17:00:10 +08:00 committed by Cruz Monrreal II
parent 07698022fd
commit 44cd38cdfe
48 changed files with 4527 additions and 4591 deletions
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36
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h
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@ -333,50 +333,50 @@ void adc_tempsensor_vrefint_enable(void);
void adc_tempsensor_vrefint_disable(void); void adc_tempsensor_vrefint_disable(void);
/* configure ADC resolution */ /* configure ADC resolution */
void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
/* configure ADC discontinuous mode */ /* configure ADC discontinuous mode */
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
/* configure the ADC mode */ /* configure the ADC mode */
void adc_mode_config(uint32_t mode); void adc_mode_config(uint32_t mode);
/* enable or disable ADC special function */ /* enable or disable ADC special function */
void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
/* configure ADC data alignment */ /* configure ADC data alignment */
void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
/* configure the length of regular channel group or inserted channel group */ /* configure the length of regular channel group or inserted channel group */
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
/* configure ADC regular channel */ /* configure ADC regular channel */
void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
/* configure ADC inserted channel */ /* configure ADC inserted channel */
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
/* configure ADC inserted channel offset */ /* configure ADC inserted channel offset */
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
/* enable ADC external trigger */ /* enable ADC external trigger */
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
/* configure ADC external trigger source */ /* configure ADC external trigger source */
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
/* enable ADC software trigger */ /* enable ADC software trigger */
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
/* read ADC regular group data register */ /* read ADC regular group data register */
uint16_t adc_regular_data_read(uint32_t adc_periph); uint16_t adc_regular_data_read(uint32_t adc_periph);
/* read ADC inserted group data register */ /* read ADC inserted group data register */
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
/* read the last ADC0 and ADC1 conversion result data in sync mode */ /* read the last ADC0 and ADC1 conversion result data in sync mode */
uint32_t adc_sync_mode_convert_value_read(void); uint32_t adc_sync_mode_convert_value_read(void);
/* get the ADC flag bits */ /* get the ADC flag bits */
FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
/* clear the ADC flag bits */ /* clear the ADC flag bits */
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
/* get the ADC interrupt bits */ /* get the ADC interrupt bits */
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
/* clear the ADC flag */ /* clear the ADC flag */
void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
/* enable ADC interrupt */ /* enable ADC interrupt */
void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
/* disable ADC interrupt */ /* disable ADC interrupt */
void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
/* configure ADC analog watchdog single channel */ /* configure ADC analog watchdog single channel */
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
@ -385,10 +385,10 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_
/* disable ADC analog watchdog */ /* disable ADC analog watchdog */
void adc_watchdog_disable(uint32_t adc_periph); void adc_watchdog_disable(uint32_t adc_periph);
/* configure ADC analog watchdog threshold */ /* configure ADC analog watchdog threshold */
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
/* configure ADC oversample mode */ /* configure ADC oversample mode */
void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio); void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio);
/* enable ADC oversample mode */ /* enable ADC oversample mode */
void adc_oversample_mode_enable(uint32_t adc_periph); void adc_oversample_mode_enable(uint32_t adc_periph);
/* disable ADC oversample mode */ /* disable ADC oversample mode */

5
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h
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@ -146,8 +146,7 @@ OF SUCH DAMAGE.
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ #define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */
/* BKP data register number */ /* BKP data register number */
typedef enum typedef enum {
{
BKP_DATA_0 = 1, /*!< BKP data register 0 */ BKP_DATA_0 = 1, /*!< BKP data register 0 */
BKP_DATA_1, /*!< BKP data register 1 */ BKP_DATA_1, /*!< BKP data register 1 */
BKP_DATA_2, /*!< BKP data register 2 */ BKP_DATA_2, /*!< BKP data register 2 */
@ -190,7 +189,7 @@ typedef enum
BKP_DATA_39, /*!< BKP data register 39 */ BKP_DATA_39, /*!< BKP data register 39 */
BKP_DATA_40, /*!< BKP data register 40 */ BKP_DATA_40, /*!< BKP data register 40 */
BKP_DATA_41, /*!< BKP data register 41 */ BKP_DATA_41, /*!< BKP data register 41 */
}bkp_data_register_enum; } bkp_data_register_enum;
/* function declarations */ /* function declarations */
/* reset BKP registers */ /* reset BKP registers */

48
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h
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@ -327,8 +327,7 @@ OF SUCH DAMAGE.
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
/* CAN flags */ /* CAN flags */
typedef enum typedef enum {
{
/* flags in TSTAT register */ /* flags in TSTAT register */
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
@ -346,11 +345,10 @@ typedef enum
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
}can_flag_enum; } can_flag_enum;
/* CAN interrupt flags */ /* CAN interrupt flags */
typedef enum typedef enum {
{
/* interrupt flags in STAT register */ /* interrupt flags in STAT register */
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
@ -365,11 +363,10 @@ typedef enum
/* interrupt flags in RFIFO0 register */ /* interrupt flags in RFIFO0 register */
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
}can_interrupt_flag_enum; } can_interrupt_flag_enum;
/* CAN initiliaze parameters struct */ /* CAN initiliaze parameters struct */
typedef struct typedef struct {
{
uint8_t working_mode; /*!< CAN working mode */ uint8_t working_mode; /*!< CAN working mode */
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
uint8_t time_segment_1; /*!< time segment 1 */ uint8_t time_segment_1; /*!< time segment 1 */
@ -381,22 +378,20 @@ typedef struct
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
ControlStatus trans_fifo_order; /*!< transmit FIFO order */ ControlStatus trans_fifo_order; /*!< transmit FIFO order */
uint16_t prescaler; /*!< baudrate prescaler */ uint16_t prescaler; /*!< baudrate prescaler */
}can_parameter_struct; } can_parameter_struct;
/* CAN transmit message struct */ /* CAN transmit message struct */
typedef struct typedef struct {
{
uint32_t tx_sfid; /*!< standard format frame identifier */ uint32_t tx_sfid; /*!< standard format frame identifier */
uint32_t tx_efid; /*!< extended format frame identifier */ uint32_t tx_efid; /*!< extended format frame identifier */
uint8_t tx_ff; /*!< format of frame, standard or extended format */ uint8_t tx_ff; /*!< format of frame, standard or extended format */
uint8_t tx_ft; /*!< type of frame, data or remote */ uint8_t tx_ft; /*!< type of frame, data or remote */
uint8_t tx_dlen; /*!< data length */ uint8_t tx_dlen; /*!< data length */
uint8_t tx_data[8]; /*!< transmit data */ uint8_t tx_data[8]; /*!< transmit data */
}can_trasnmit_message_struct; } can_trasnmit_message_struct;
/* CAN receive message struct */ /* CAN receive message struct */
typedef struct typedef struct {
{
uint32_t rx_sfid; /*!< standard format frame identifier */ uint32_t rx_sfid; /*!< standard format frame identifier */
uint32_t rx_efid; /*!< extended format frame identifier */ uint32_t rx_efid; /*!< extended format frame identifier */
uint8_t rx_ff; /*!< format of frame, standard or extended format */ uint8_t rx_ff; /*!< format of frame, standard or extended format */
@ -407,8 +402,7 @@ typedef struct
} can_receive_message_struct; } can_receive_message_struct;
/* CAN filter parameters struct */ /* CAN filter parameters struct */
typedef struct typedef struct {
{
uint16_t filter_list_high; /*!< filter list number high bits*/ uint16_t filter_list_high; /*!< filter list number high bits*/
uint16_t filter_list_low; /*!< filter list number low bits */ uint16_t filter_list_low; /*!< filter list number low bits */
uint16_t filter_mask_high; /*!< filter mask number high bits */ uint16_t filter_mask_high; /*!< filter mask number high bits */
@ -418,11 +412,10 @@ typedef struct
uint16_t filter_mode; /*!< filter mode, list or mask */ uint16_t filter_mode; /*!< filter mode, list or mask */
uint16_t filter_bits; /*!< filter scale */ uint16_t filter_bits; /*!< filter scale */
ControlStatus filter_enable; /*!< filter work or not */ ControlStatus filter_enable; /*!< filter work or not */
}can_filter_parameter_struct; } can_filter_parameter_struct;
/* CAN errors */ /* CAN errors */
typedef enum typedef enum {
{
CAN_ERROR_NONE = 0, /*!< no error */ CAN_ERROR_NONE = 0, /*!< no error */
CAN_ERROR_FILL, /*!< fill error */ CAN_ERROR_FILL, /*!< fill error */
CAN_ERROR_FORMATE, /*!< format error */ CAN_ERROR_FORMATE, /*!< format error */
@ -431,16 +424,15 @@ typedef enum
CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
CAN_ERROR_CRC, /*!< CRC error */ CAN_ERROR_CRC, /*!< CRC error */
CAN_ERROR_SOFTWARECFG, /*!< software configure */ CAN_ERROR_SOFTWARECFG, /*!< software configure */
}can_error_enum; } can_error_enum;
/* transmit states */ /* transmit states */
typedef enum typedef enum {
{
CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */
CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */
CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */
CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */
}can_transmit_state_enum; } can_transmit_state_enum;
/* CAN baudrate prescaler*/ /* CAN baudrate prescaler*/
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
@ -649,12 +641,12 @@ typedef enum
void can_deinit(uint32_t can_periph); void can_deinit(uint32_t can_periph);
/* initialize CAN */ /* initialize CAN */
#ifdef GD_MBED_USED #ifdef GD_MBED_USED
ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
#else #else
ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
#endif #endif
/* CAN filter init */ /* CAN filter init */
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
/* set can1 fliter start bank number */ /* set can1 fliter start bank number */
void can1_filter_start_bank(uint8_t start_bank); void can1_filter_start_bank(uint8_t start_bank);
@ -670,13 +662,13 @@ void can_time_trigger_mode_disable(uint32_t can_periph);
/* transmit functions */ /* transmit functions */
/* transmit CAN message */ /* transmit CAN message */
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message);
/* get CAN transmit state */ /* get CAN transmit state */
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
/* stop CAN transmission */ /* stop CAN transmission */
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
/* CAN receive message */ /* CAN receive message */
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
/* CAN release fifo */ /* CAN release fifo */
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
/* CAN receive message length */ /* CAN receive message length */

5
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h
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@ -86,8 +86,7 @@ OF SUCH DAMAGE.
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
typedef enum typedef enum {
{
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
@ -112,7 +111,7 @@ typedef enum
DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */
DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */
#endif /* GD32F30X_HD */ #endif /* GD32F30X_HD */
}dbg_periph_enum; } dbg_periph_enum;
#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) #define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6))
#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ #define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */

10
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h
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@ -120,8 +120,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* DMA channel select */ /* DMA channel select */
typedef enum typedef enum {
{
DMA_CH0 = 0, /*!< DMA Channel0 */ DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */ DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */ DMA_CH2, /*!< DMA Channel2 */
@ -132,8 +131,7 @@ typedef enum
} dma_channel_enum; } dma_channel_enum;
/* DMA initialize struct */ /* DMA initialize struct */
typedef struct typedef struct {
{
uint32_t periph_addr; /*!< peripheral base address */ uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */ uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t memory_addr; /*!< memory base address */ uint32_t memory_addr; /*!< memory base address */
@ -259,9 +257,9 @@ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
/* configure priority level of DMA channel */ /* configure priority level of DMA channel */
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
/* configure transfer data size of memory */ /* configure transfer data size of memory */
void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
/* configure transfer data size of peripheral */ /* configure transfer data size of peripheral */
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
/* enable next address increasement algorithm of memory */ /* enable next address increasement algorithm of memory */
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable next address increasement algorithm of memory */ /* disable next address increasement algorithm of memory */

121
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h
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@ -657,8 +657,7 @@ OF SUCH DAMAGE.
#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ #define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */
/* ENET status flag get */ /* ENET status flag get */
typedef enum typedef enum {
{
/* ENET_MAC_WUM register */ /* ENET_MAC_WUM register */
ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */
ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */
@ -703,11 +702,10 @@ typedef enum
ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */
ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */
ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */
}enet_flag_enum; } enet_flag_enum;
/* ENET stutus flag clear */ /* ENET stutus flag clear */
typedef enum typedef enum {
{
/* ENET_DMA_STAT register */ /* ENET_DMA_STAT register */
ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
@ -724,11 +722,10 @@ typedef enum
ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
}enet_flag_clear_enum; } enet_flag_clear_enum;
/* ENET interrupt enable/disable */ /* ENET interrupt enable/disable */
typedef enum typedef enum {
{
/* ENET_MAC_INTMSK register */ /* ENET_MAC_INTMSK register */
ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */
ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */
@ -756,11 +753,10 @@ typedef enum
ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */
ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */
ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */
}enet_int_enum; } enet_int_enum;
/* ENET interrupt flag get */ /* ENET interrupt flag get */
typedef enum typedef enum {
{
/* ENET_MAC_INTF register */ /* ENET_MAC_INTF register */
ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */
ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */
@ -794,11 +790,10 @@ typedef enum
ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */
ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */
ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */
}enet_int_flag_enum; } enet_int_flag_enum;
/* ENET interrupt flag clear */ /* ENET interrupt flag clear */
typedef enum typedef enum {
{
/* ENET_DMA_STAT register */ /* ENET_DMA_STAT register */
ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
@ -815,33 +810,30 @@ typedef enum
ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
}enet_int_flag_clear_enum; } enet_int_flag_clear_enum;
/* current RX/TX descriptor/buffer/descriptor table address get */ /* current RX/TX descriptor/buffer/descriptor table address get */
typedef enum typedef enum {
{
ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */
ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */
ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */
ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */
ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */
ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */
}enet_desc_reg_enum; } enet_desc_reg_enum;
/* MAC statistics counter get */ /* MAC statistics counter get */
typedef enum typedef enum {
{
ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */
ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */
ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */
ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */
ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */
ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */
}enet_msc_counter_enum; } enet_msc_counter_enum;
/* function option, used for ENET initialization */ /* function option, used for ENET initialization */
typedef enum typedef enum {
{
FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */
DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */
DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */
@ -856,98 +848,87 @@ typedef enum
HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */
TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */
INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */
}enet_option_enum; } enet_option_enum;
/* phy mode and mac loopback configurations */ /* phy mode and mac loopback configurations */
typedef enum typedef enum {
{
ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */
ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */
ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD, /*!< 100Mbit/s, half-duplex */
ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */
ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */
ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */
}enet_mediamode_enum; } enet_mediamode_enum;
/* IP frame checksum function */ /* IP frame checksum function */
typedef enum typedef enum {
{
ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */
ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */
ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO | ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame
with only payload error but no other errors will not be dropped */ with only payload error but no other errors will not be dropped */
}enet_chksumconf_enum; } enet_chksumconf_enum;
/* received frame filter function */ /* received frame filter function */
typedef enum typedef enum {
{
ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */
ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */
ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */
ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */
}enet_frmrecept_enum; } enet_frmrecept_enum;
/* register group value get */ /* register group value get */
typedef enum typedef enum {
{
ALL_MAC_REG = 0, /*!< MAC register group */ ALL_MAC_REG = 0, /*!< MAC register group */
ALL_MSC_REG = 22, /*!< MSC register group */ ALL_MSC_REG = 22, /*!< MSC register group */
ALL_PTP_REG = 33, /*!< PTP register group */ ALL_PTP_REG = 33, /*!< PTP register group */
ALL_DMA_REG = 44, /*!< DMA register group */ ALL_DMA_REG = 44, /*!< DMA register group */
}enet_registers_type_enum; } enet_registers_type_enum;
/* dma direction select */ /* dma direction select */
typedef enum typedef enum {
{
ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */
ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */
}enet_dmadirection_enum; } enet_dmadirection_enum;
/* PHY operation direction select */ /* PHY operation direction select */
typedef enum typedef enum {
{
ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */
ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */
}enet_phydirection_enum; } enet_phydirection_enum;
/* register operation direction select */ /* register operation direction select */
typedef enum typedef enum {
{
ENET_REG_READ, /*!< read register */ ENET_REG_READ, /*!< read register */
ENET_REG_WRITE /*!< write register */ ENET_REG_WRITE /*!< write register */
}enet_regdirection_enum; } enet_regdirection_enum;
/* ENET MAC addresses */ /* ENET MAC addresses */
typedef enum typedef enum {
{
ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */
ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */
ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */
ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */
}enet_macaddress_enum; } enet_macaddress_enum;
/* descriptor information */ /* descriptor information */
typedef enum typedef enum {
{
TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */
TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */
RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */
RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */
RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */
RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */
}enet_descstate_enum; } enet_descstate_enum;
/* MSC counters preset mode */ /* MSC counters preset mode */
typedef enum typedef enum {
{
ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */
ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */
ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */
}enet_msc_preset_enum; } enet_msc_preset_enum;
/* structure for initialization of the ENET */ /* structure for initialization of the ENET */
typedef struct typedef struct {
{
uint32_t option_enable; /*!< select which function to configure */ uint32_t option_enable; /*!< select which function to configure */
uint32_t forward_frame; /*!< frame forward related parameters */ uint32_t forward_frame; /*!< frame forward related parameters */
uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ uint32_t dmabus_mode; /*!< DMA bus mode related parameters */
@ -963,11 +944,10 @@ typedef struct
uint32_t halfduplex_param; /*!< halfduplex related parameters */ uint32_t halfduplex_param; /*!< halfduplex related parameters */
uint32_t timer_config; /*!< frame timer related parameters */ uint32_t timer_config; /*!< frame timer related parameters */
uint32_t interframegap; /*!< inter frame gap related parameters */ uint32_t interframegap; /*!< inter frame gap related parameters */
}enet_initpara_struct; } enet_initpara_struct;
/* structure for ENET DMA desciptors */ /* structure for ENET DMA desciptors */
typedef struct typedef struct {
{
uint32_t status; /*!< status */ uint32_t status; /*!< status */
uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */
uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */
@ -983,12 +963,11 @@ typedef struct
} enet_descriptors_struct; } enet_descriptors_struct;
/* structure of PTP system time */ /* structure of PTP system time */
typedef struct typedef struct {
{
uint32_t second; /*!< second of system time */ uint32_t second; /*!< second of system time */
uint32_t nanosecond; /*!< nanosecond of system time */ uint32_t nanosecond; /*!< nanosecond of system time */
uint32_t sign; /*!< sign of system time */ uint32_t sign; /*!< sign of system time */
}enet_ptp_systime_struct; } enet_ptp_systime_struct;
/* mac_cfg register value */ /* mac_cfg register value */
#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ #define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */
@ -1427,7 +1406,7 @@ typedef struct
#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */
typedef enum{ typedef enum {
ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */
ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */
ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */
@ -1435,17 +1414,17 @@ typedef enum{
ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */
ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */
ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */
ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU | BIT(31)), /*!< the system timestamp uses the fine method for updating */
ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */
ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */
ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */
ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)), /*!< version 2 */ ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV | BIT(31)), /*!< version 2 */
ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */
ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)), /*!< only event type messages are taken snapshot */ ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN | BIT(31)), /*!< only event type messages are taken snapshot */
ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */
ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)), /*!< snapshot is only take for master node message */ ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN | BIT(31)), /*!< snapshot is only take for master node message */
ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */
}enet_ptp_function_enum; } enet_ptp_function_enum;
/* ENET remote wake-up frame register length */ /* ENET remote wake-up frame register length */
@ -1683,7 +1662,7 @@ void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg);
/* update system time in coarse method */ /* update system time in coarse method */
void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct);
/* set system time in fine method */ /* set system time in fine method */
void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct);
/* get the ptp flag status */ /* get the ptp flag status */
FlagStatus enet_ptp_flag_get(uint32_t flag); FlagStatus enet_ptp_flag_get(uint32_t flag);

63
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h
View File

@ -155,8 +155,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* EXMC NOR/SRAM timing initialize struct */ /* EXMC NOR/SRAM timing initialize struct */
typedef struct typedef struct {
{
uint32_t asyn_access_mode; /*!< asynchronous access mode */ uint32_t asyn_access_mode; /*!< asynchronous access mode */
uint32_t syn_data_latency; /*!< configure the data latency */ uint32_t syn_data_latency; /*!< configure the data latency */
uint32_t syn_clk_division; /*!< configure the clock divide ratio */ uint32_t syn_clk_division; /*!< configure the clock divide ratio */
@ -164,11 +163,10 @@ typedef struct
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
}exmc_norsram_timing_parameter_struct; } exmc_norsram_timing_parameter_struct;
/* EXMC NOR/SRAM initialize struct */ /* EXMC NOR/SRAM initialize struct */
typedef struct typedef struct {
{
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
uint32_t extended_mode; /*!< enable or disable the extended mode */ uint32_t extended_mode; /*!< enable or disable the extended mode */
@ -182,23 +180,21 @@ typedef struct
uint32_t databus_width; /*!< specifies the databus width of external memory */ uint32_t databus_width; /*!< specifies the databus width of external memory */
uint32_t memory_type; /*!< specifies the type of external memory */ uint32_t memory_type; /*!< specifies the type of external memory */
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing exmc_norsram_timing_parameter_struct *read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing
parameters for read if the extended mode is used */ parameters for read if the extended mode is used */
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ exmc_norsram_timing_parameter_struct *write_timing; /*!< timing parameters for write when the extended mode is used */
}exmc_norsram_parameter_struct; } exmc_norsram_parameter_struct;
/* EXMC NAND/PC card timing initialize struct */ /* EXMC NAND/PC card timing initialize struct */
typedef struct typedef struct {
{
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
uint32_t waittime; /*!< configure the minimum wait time */ uint32_t waittime; /*!< configure the minimum wait time */
uint32_t setuptime; /*!< configure the address setup time */ uint32_t setuptime; /*!< configure the address setup time */
}exmc_nand_pccard_timing_parameter_struct; } exmc_nand_pccard_timing_parameter_struct;
/* EXMC NAND initialize struct */ /* EXMC NAND initialize struct */
typedef struct typedef struct {
{
uint32_t nand_bank; /*!< select the bank of NAND */ uint32_t nand_bank; /*!< select the bank of NAND */
uint32_t ecc_size; /*!< the page size for the ECC calculation */ uint32_t ecc_size; /*!< the page size for the ECC calculation */
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
@ -206,20 +202,19 @@ typedef struct
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
uint32_t databus_width; /*!< the NAND flash databus width */ uint32_t databus_width; /*!< the NAND flash databus width */
uint32_t wait_feature; /*!< enables or disables the wait feature */ uint32_t wait_feature; /*!< enables or disables the wait feature */
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ exmc_nand_pccard_timing_parameter_struct *common_space_timing; /*!< the timing parameters for NAND flash common space */
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ exmc_nand_pccard_timing_parameter_struct *attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
}exmc_nand_parameter_struct; } exmc_nand_parameter_struct;
/* EXMC PC card initialize struct */ /* EXMC PC card initialize struct */
typedef struct typedef struct {
{
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
uint32_t wait_feature; /*!< enables or disables the Wait feature */ uint32_t wait_feature; /*!< enables or disables the Wait feature */
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ exmc_nand_pccard_timing_parameter_struct *common_space_timing; /*!< the timing parameters for NAND flash common space */
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ exmc_nand_pccard_timing_parameter_struct *attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ exmc_nand_pccard_timing_parameter_struct *io_space_timing; /*!< the timing parameters for NAND flash IO space */
}exmc_pccard_parameter_struct;; } exmc_pccard_parameter_struct;;
/* EXMC_register address */ /* EXMC_register address */
@ -392,9 +387,9 @@ typedef struct
/* deinitialize EXMC NOR/SRAM region */ /* deinitialize EXMC NOR/SRAM region */
void exmc_norsram_deinit(uint32_t exmc_norsram_region); void exmc_norsram_deinit(uint32_t exmc_norsram_region);
/* initialize EXMC NOR/SRAM region */ /* initialize EXMC NOR/SRAM region */
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct);
/* exmc_norsram_parameter_struct parameter initialize */ /* exmc_norsram_parameter_struct parameter initialize */
void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); void exmc_norsram_parameter_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct);
/* CRAM page size configure */ /* CRAM page size configure */
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size);
/* EXMC NOR/SRAM bank enable */ /* EXMC NOR/SRAM bank enable */
@ -406,9 +401,9 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region);
/* deinitialize EXMC NAND bank */ /* deinitialize EXMC NAND bank */
void exmc_nand_deinit(uint32_t exmc_nand_bank); void exmc_nand_deinit(uint32_t exmc_nand_bank);
/* initialize EXMC NAND bank */ /* initialize EXMC NAND bank */
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct);
/* exmc_norsram_parameter_struct parameter initialize */ /* exmc_norsram_parameter_struct parameter initialize */
void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct); void exmc_nand_parameter_init(exmc_nand_parameter_struct *exmc_nand_init_struct);
/* EXMC NAND bank enable */ /* EXMC NAND bank enable */
void exmc_nand_enable(uint32_t exmc_nand_bank); void exmc_nand_enable(uint32_t exmc_nand_bank);
/* EXMC NAND bank disable */ /* EXMC NAND bank disable */
@ -421,25 +416,25 @@ uint32_t exmc_ecc_get(uint32_t exmc_nand_bank);
/* deinitialize EXMC PC card bank */ /* deinitialize EXMC PC card bank */
void exmc_pccard_deinit(void); void exmc_pccard_deinit(void);
/* initialize EXMC PC card bank */ /* initialize EXMC PC card bank */
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct);
/* exmc_pccard_parameter_struct parameter initialize */ /* exmc_pccard_parameter_struct parameter initialize */
void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); void exmc_pccard_parameter_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct);
/* EXMC PC card bank enable */ /* EXMC PC card bank enable */
void exmc_pccard_enable(void); void exmc_pccard_enable(void);
/* EXMC PC card bank disable */ /* EXMC PC card bank disable */
void exmc_pccard_disable(void); void exmc_pccard_disable(void);
/* check EXMC flag is set or not */ /* check EXMC flag is set or not */
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag);
/* clear EXMC flag */ /* clear EXMC flag */
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag);
/* check EXMC flag is set or not */ /* check EXMC flag is set or not */
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source); FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt_source);
/* clear EXMC flag */ /* clear EXMC flag */
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source); void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt_source);
/* enable EXMC interrupt */ /* enable EXMC interrupt */
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source); void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt_source);
/* disable EXMC interrupt */ /* disable EXMC interrupt */
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source); void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt_source);
#endif /* GD32F30X_EXMC_H */ #endif /* GD32F30X_EXMC_H */

15
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h
View File

@ -185,8 +185,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* EXTI line number */ /* EXTI line number */
typedef enum typedef enum {
{
EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_0 = BIT(0), /*!< EXTI line 0 */
EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */
EXTI_2 = BIT(2), /*!< EXTI line 2 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */
@ -207,22 +206,20 @@ typedef enum
EXTI_17 = BIT(17), /*!< EXTI line 17 */ EXTI_17 = BIT(17), /*!< EXTI line 17 */
EXTI_18 = BIT(18), /*!< EXTI line 18 */ EXTI_18 = BIT(18), /*!< EXTI line 18 */
EXTI_19 = BIT(19), /*!< EXTI line 19 */ EXTI_19 = BIT(19), /*!< EXTI line 19 */
}exti_line_enum; } exti_line_enum;
/* external interrupt and event */ /* external interrupt and event */
typedef enum typedef enum {
{
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
EXTI_EVENT /*!< EXTI event mode */ EXTI_EVENT /*!< EXTI event mode */
}exti_mode_enum; } exti_mode_enum;
/* interrupt trigger mode */ /* interrupt trigger mode */
typedef enum typedef enum {
{
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */
}exti_trig_type_enum; } exti_trig_type_enum;
/* function declarations */ /* function declarations */
/* deinitialize the EXTI */ /* deinitialize the EXTI */

20
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h
View File

@ -152,27 +152,24 @@ OF SUCH DAMAGE.
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ #define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
/* fmc state */ /* fmc state */
typedef enum typedef enum {
{
FMC_READY, /*!< the operation has been completed */ FMC_READY, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */ FMC_BUSY, /*!< the operation is in progress */
FMC_PGERR, /*!< program error */ FMC_PGERR, /*!< program error */
FMC_WPERR, /*!< erase/program protection error */ FMC_WPERR, /*!< erase/program protection error */
FMC_TOERR, /*!< timeout error */ FMC_TOERR, /*!< timeout error */
}fmc_state_enum; } fmc_state_enum;
/* FMC interrupt enable */ /* FMC interrupt enable */
typedef enum typedef enum {
{
FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */
FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */
}fmc_int_enum; } fmc_int_enum;
/* FMC flags */ /* FMC flags */
typedef enum typedef enum {
{
FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */
FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */
FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */
@ -182,18 +179,17 @@ typedef enum
FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */
FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */
FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */
}fmc_flag_enum; } fmc_flag_enum;
/* FMC interrupt flags */ /* FMC interrupt flags */
typedef enum typedef enum {
{
FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */
FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */
FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */
FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */
FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */
FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */
}fmc_interrupt_flag_enum; } fmc_interrupt_flag_enum;
/* unlock key */ /* unlock key */
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */

17
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h
View File

@ -262,12 +262,11 @@ OF SUCH DAMAGE.
#define SLAVE10_FIRST_BYTE(addr10) ((0xF0) | (uint8_t)((addr10 & 0x0300)>>7)) #define SLAVE10_FIRST_BYTE(addr10) ((0xF0) | (uint8_t)((addr10 & 0x0300)>>7))
#define SLAVE10_SECOND_BYTE(addr10) ((uint8_t)(addr10 & 0x00FF)) #define SLAVE10_SECOND_BYTE(addr10) ((uint8_t)(addr10 & 0x00FF))
typedef enum typedef enum {
{ I2C_MODE_NONE = 0x00U, /*!< I2C device is idle */
I2C_MODE_NONE = 0x00U, /*!< I2C device is idle */ I2C_MODE_MASTER = 0x10U, /*!< I2C device is in Master Mode */
I2C_MODE_MASTER = 0x10U, /*!< I2C device is in Master Mode */ I2C_MODE_SLAVE = 0x20U /*!< I2C device is in Slave Mode */
I2C_MODE_SLAVE = 0x20U /*!< I2C device is in Slave Mode */ } i2c_mode_enum;
}i2c_mode_enum;
/* I2C state definitions */ /* I2C state definitions */
#define I2C_STATE_MSK ((uint32_t)((OP_STATE_BUSY_TX | OP_STATE_BUSY_RX) & (~(uint32_t)OP_STATE_BUSY))) #define I2C_STATE_MSK ((uint32_t)((OP_STATE_BUSY_TX | OP_STATE_BUSY_RX) & (~(uint32_t)OP_STATE_BUSY)))
@ -332,7 +331,7 @@ void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
/* flag indicating DMA last transfer */ /* flag indicating DMA last transfer */
void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast); void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast);
/* whether to stretch SCL low when data is not ready in slave mode */ /* whether to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara ); void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
/* whether or not to response to a general call */ /* whether or not to response to a general call */
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
/* software reset I2C */ /* software reset I2C */
@ -347,9 +346,9 @@ void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype);
/* disable I2C interrupt */ /* disable I2C interrupt */
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype); void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype);
/* check I2C interrupt flag */ /* check I2C interrupt flag */
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,uint32_t intflag); FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag);
/* clear I2C interrupt flag */ /* clear I2C interrupt flag */
void i2c_interrupt_flag_clear(uint32_t i2c_periph,uint32_t intflag); void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag);
/* I2C PEC calculation on or off */ /* I2C PEC calculation on or off */
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);

45
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h
View File

@ -416,8 +416,7 @@ OF SUCH DAMAGE.
#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ #define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */
/* peripheral clock enable */ /* peripheral clock enable */
typedef enum typedef enum {
{
/* AHB peripherals */ /* AHB peripherals */
RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */
RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */
@ -489,19 +488,17 @@ typedef enum
RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */
RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */
#endif /* GD32F30X_HD */ #endif /* GD32F30X_HD */
}rcu_periph_enum; } rcu_periph_enum;
/* peripheral clock enable when sleep mode*/ /* peripheral clock enable when sleep mode*/
typedef enum typedef enum {
{
/* AHB peripherals */ /* AHB peripherals */
RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */
RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */
}rcu_periph_sleep_enum; } rcu_periph_sleep_enum;
/* peripherals reset */ /* peripherals reset */
typedef enum typedef enum {
{
/* AHB peripherals */ /* AHB peripherals */
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
@ -564,11 +561,10 @@ typedef enum
RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */
RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */
#endif /* GD32F30X_HD */ #endif /* GD32F30X_HD */
}rcu_periph_reset_enum; } rcu_periph_reset_enum;
/* clock stabilization and peripheral reset flags */ /* clock stabilization and peripheral reset flags */
typedef enum typedef enum {
{
/* clock stabilization flags */ /* clock stabilization flags */
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */
RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */
@ -587,11 +583,10 @@ typedef enum
RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */
RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */
RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */
}rcu_flag_enum; } rcu_flag_enum;
/* clock stabilization and ckm interrupt flags */ /* clock stabilization and ckm interrupt flags */
typedef enum typedef enum {
{
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */
RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */
RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */
@ -603,11 +598,10 @@ typedef enum
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */
RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */
}rcu_int_flag_enum; } rcu_int_flag_enum;
/* clock stabilization and stuck interrupt flags clear */ /* clock stabilization and stuck interrupt flags clear */
typedef enum typedef enum {
{
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */
@ -619,11 +613,10 @@ typedef enum
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */
RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */
}rcu_int_flag_clear_enum; } rcu_int_flag_clear_enum;
/* clock stabilization interrupt enable or disable */ /* clock stabilization interrupt enable or disable */
typedef enum typedef enum {
{
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */
RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */
RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */
@ -634,11 +627,10 @@ typedef enum
RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */
}rcu_int_enum; } rcu_int_enum;
/* oscillator types */ /* oscillator types */
typedef enum typedef enum {
{
RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */
RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */
RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */
@ -649,16 +641,15 @@ typedef enum
RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */
RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
}rcu_osci_type_enum; } rcu_osci_type_enum;
/* rcu clock frequency */ /* rcu clock frequency */
typedef enum typedef enum {
{
CK_SYS = 0, /*!< system clock */ CK_SYS = 0, /*!< system clock */
CK_AHB, /*!< AHB clock */ CK_AHB, /*!< AHB clock */
CK_APB1, /*!< APB1 clock */ CK_APB1, /*!< APB1 clock */
CK_APB2, /*!< APB2 clock */ CK_APB2, /*!< APB2 clock */
}rcu_clock_freq_enum; } rcu_clock_freq_enum;
/* RCU_CFG0 register bit define */ /* RCU_CFG0 register bit define */
/* system clock source select */ /* system clock source select */

11
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h
View File

@ -128,8 +128,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* SPI and I2S parameter struct definitions */ /* SPI and I2S parameter struct definitions */
typedef struct typedef struct {
{
uint32_t device_mode; /*!< SPI master or slave */ uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */ uint32_t trans_mode; /*!< SPI transtype */
uint32_t frame_size; /*!< SPI frame size */ uint32_t frame_size; /*!< SPI frame size */
@ -137,7 +136,7 @@ typedef struct
uint32_t endian; /*!< SPI big endian or little endian */ uint32_t endian; /*!< SPI big endian or little endian */
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
uint32_t prescale; /*!< SPI prescale factor */ uint32_t prescale; /*!< SPI prescale factor */
}spi_parameter_struct; } spi_parameter_struct;
/* SPI mode definitions */ /* SPI mode definitions */
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
@ -264,11 +263,11 @@ typedef struct
/* function declarations */ /* function declarations */
/* reset SPI and I2S */ /* reset SPI and I2S */
void spi_i2s_deinit(uint32_t spi_periph); void spi_i2s_deinit(uint32_t spi_periph);
#ifdef GD_MBED_USED #ifdef GD_MBED_USED
/* initialize SPI parameter */ /* initialize SPI parameter */
void spi_para_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); void spi_para_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
#else #else
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
#endif #endif
/* enable SPI */ /* enable SPI */
void spi_enable(uint32_t spi_periph); void spi_enable(uint32_t spi_periph);

30
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h
View File

@ -256,19 +256,17 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* TIMER init parameter struct definitions*/ /* TIMER init parameter struct definitions*/
typedef struct typedef struct {
{
uint16_t prescaler; /*!< prescaler value */ uint16_t prescaler; /*!< prescaler value */
uint16_t alignedmode; /*!< aligned mode */ uint16_t alignedmode; /*!< aligned mode */
uint16_t counterdirection; /*!< counter direction */ uint16_t counterdirection; /*!< counter direction */
uint32_t period; /*!< period value */ uint32_t period; /*!< period value */
uint16_t clockdivision; /*!< clock division value */ uint16_t clockdivision; /*!< clock division value */
uint8_t repetitioncounter; /*!< the counter repetition value */ uint8_t repetitioncounter; /*!< the counter repetition value */
}timer_parameter_struct; } timer_parameter_struct;
/* break parameter struct definitions*/ /* break parameter struct definitions*/
typedef struct typedef struct {
{
uint16_t runoffstate; /*!< run mode off-state */ uint16_t runoffstate; /*!< run mode off-state */
uint32_t ideloffstate; /*!< idle mode off-state */ uint32_t ideloffstate; /*!< idle mode off-state */
uint16_t deadtime; /*!< dead time */ uint16_t deadtime; /*!< dead time */
@ -276,27 +274,25 @@ typedef struct
uint16_t outputautostate; /*!< output automatic enable */ uint16_t outputautostate; /*!< output automatic enable */
uint16_t protectmode; /*!< complementary register protect control */ uint16_t protectmode; /*!< complementary register protect control */
uint16_t breakstate; /*!< break enable */ uint16_t breakstate; /*!< break enable */
}timer_break_parameter_struct; } timer_break_parameter_struct;
/* channel output parameter struct definitions */ /* channel output parameter struct definitions */
typedef struct typedef struct {
{
uint32_t outputstate; /*!< channel output state */ uint32_t outputstate; /*!< channel output state */
uint16_t outputnstate; /*!< channel complementary output state */ uint16_t outputnstate; /*!< channel complementary output state */
uint16_t ocpolarity; /*!< channel output polarity */ uint16_t ocpolarity; /*!< channel output polarity */
uint16_t ocnpolarity; /*!< channel complementary output polarity */ uint16_t ocnpolarity; /*!< channel complementary output polarity */
uint16_t ocidlestate; /*!< idle state of channel output */ uint16_t ocidlestate; /*!< idle state of channel output */
uint16_t ocnidlestate; /*!< idle state of channel complementary output */ uint16_t ocnidlestate; /*!< idle state of channel complementary output */
}timer_oc_parameter_struct; } timer_oc_parameter_struct;
/* channel input parameter struct definitions */ /* channel input parameter struct definitions */
typedef struct typedef struct {
{
uint16_t icpolarity; /*!< channel input polarity */ uint16_t icpolarity; /*!< channel input polarity */
uint16_t icselection; /*!< channel input mode selection */ uint16_t icselection; /*!< channel input mode selection */
uint16_t icprescaler; /*!< channel input capture prescaler */ uint16_t icprescaler; /*!< channel input capture prescaler */
uint16_t icfilter; /*!< channel input capture filter control */ uint16_t icfilter; /*!< channel input capture filter control */
}timer_ic_parameter_struct; } timer_ic_parameter_struct;
/* TIMER interrupt enable or disable */ /* TIMER interrupt enable or disable */
#define TIMER_INT_UP ((uint32_t)0x00000001U) /*!< update interrupt */ #define TIMER_INT_UP ((uint32_t)0x00000001U) /*!< update interrupt */
@ -592,7 +588,7 @@ typedef struct
/* deinit a TIMER */ /* deinit a TIMER */
void timer_deinit(uint32_t timer_periph); void timer_deinit(uint32_t timer_periph);
/* initialize TIMER counter */ /* initialize TIMER counter */
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara);
/* enable a TIMER */ /* enable a TIMER */
void timer_enable(uint32_t timer_periph); void timer_enable(uint32_t timer_periph);
/* disable a TIMER */ /* disable a TIMER */
@ -656,7 +652,7 @@ void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
/* timer channel complementary protection */ /* timer channel complementary protection */
/* configure TIMER break function */ /* configure TIMER break function */
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara);
/* enable TIMER break function */ /* enable TIMER break function */
void timer_break_enable(uint32_t timer_periph); void timer_break_enable(uint32_t timer_periph);
/* disable TIMER break function */ /* disable TIMER break function */
@ -674,7 +670,7 @@ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t c
/* TIMER channel output */ /* TIMER channel output */
/* configure TIMER channel output function */ /* configure TIMER channel output function */
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara);
/* configure TIMER channel output compare mode */ /* configure TIMER channel output compare mode */
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
/* configure TIMER channel output pulse value */ /* configure TIMER channel output pulse value */
@ -696,13 +692,13 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint
/* TIMER channel input */ /* TIMER channel input */
/* configure TIMER input capture parameter */ /* configure TIMER input capture parameter */
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara);
/* configure TIMER channel input capture prescaler value */ /* configure TIMER channel input capture prescaler value */
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
/* read TIMER channel capture compare register value */ /* read TIMER channel capture compare register value */
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
/* configure TIMER input pwm capture function */ /* configure TIMER input pwm capture function */
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm);
/* configure TIMER hall sensor mode */ /* configure TIMER hall sensor mode */
void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode); void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode);

22
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h
View File

@ -160,8 +160,7 @@ OF SUCH DAMAGE.
#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ #define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */
/* USART flags */ /* USART flags */
typedef enum typedef enum {
{
/* flags in STAT0 register */ /* flags in STAT0 register */
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */
@ -177,11 +176,10 @@ typedef enum
USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */
USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */
USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */
}usart_flag_enum; } usart_flag_enum;
/* USART interrupt flags */ /* USART interrupt flags */
typedef enum typedef enum {
{
/* interrupt flags in CTL0 register */ /* interrupt flags in CTL0 register */
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
@ -199,11 +197,10 @@ typedef enum
/* interrupt flags in CTL3 register */ /* interrupt flags in CTL3 register */
USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */
USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */
}usart_interrupt_flag_enum; } usart_interrupt_flag_enum;
/* USART interrupt enable or disable */ /* USART interrupt enable or disable */
typedef enum typedef enum {
{
/* interrupt in CTL0 register */ /* interrupt in CTL0 register */
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
@ -218,11 +215,10 @@ typedef enum
/* interrupt in CTL3 register */ /* interrupt in CTL3 register */
USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */
USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */
}usart_interrupt_enum; } usart_interrupt_enum;
/* USART invert configure */ /* USART invert configure */
typedef enum typedef enum {
{
/* data bit level inversion */ /* data bit level inversion */
USART_DINV_ENABLE, /*!< data bit level inversion */ USART_DINV_ENABLE, /*!< data bit level inversion */
USART_DINV_DISABLE, /*!< data bit level not inversion */ USART_DINV_DISABLE, /*!< data bit level not inversion */
@ -232,7 +228,7 @@ typedef enum
/* RX pin level inversion */ /* RX pin level inversion */
USART_RXPIN_ENABLE, /*!< RX pin level inversion */ USART_RXPIN_ENABLE, /*!< RX pin level inversion */
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
}usart_invert_enum; } usart_invert_enum;
/* USART receiver configure */ /* USART receiver configure */
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
@ -405,7 +401,7 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32
/* smartcard communication */ /* smartcard communication */
/* guard time value configure in smartcard mode */ /* guard time value configure in smartcard mode */
void usart_guard_time_config(uint32_t usart_periph,uint32_t guat); void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
/* smartcard mode enable */ /* smartcard mode enable */
void usart_smartcard_mode_enable(uint32_t usart_periph); void usart_smartcard_mode_enable(uint32_t usart_periph);
/* smartcard mode disable */ /* smartcard mode disable */

350
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c
View File

@ -45,23 +45,23 @@ OF SUCH DAMAGE.
*/ */
void adc_deinit(uint32_t adc_periph) void adc_deinit(uint32_t adc_periph)
{ {
switch(adc_periph){ switch (adc_periph) {
case ADC0: case ADC0:
rcu_periph_reset_enable(RCU_ADC0RST); rcu_periph_reset_enable(RCU_ADC0RST);
rcu_periph_reset_disable(RCU_ADC0RST); rcu_periph_reset_disable(RCU_ADC0RST);
break; break;
case ADC1: case ADC1:
rcu_periph_reset_enable(RCU_ADC1RST); rcu_periph_reset_enable(RCU_ADC1RST);
rcu_periph_reset_disable(RCU_ADC1RST); rcu_periph_reset_disable(RCU_ADC1RST);
break; break;
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
case ADC2: case ADC2:
rcu_periph_reset_enable(RCU_ADC2RST); rcu_periph_reset_enable(RCU_ADC2RST);
rcu_periph_reset_disable(RCU_ADC2RST); rcu_periph_reset_disable(RCU_ADC2RST);
break; break;
#endif #endif
default: default:
break; break;
} }
} }
@ -74,7 +74,7 @@ void adc_deinit(uint32_t adc_periph)
*/ */
void adc_enable(uint32_t adc_periph) void adc_enable(uint32_t adc_periph)
{ {
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ if (RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) {
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
} }
} }
@ -103,12 +103,12 @@ void adc_calibration_enable(uint32_t adc_periph)
/* reset the selected ADC1 calibration registers */ /* reset the selected ADC1 calibration registers */
ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
/* check the RSTCLB bit state */ /* check the RSTCLB bit state */
while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ while ((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) {
} }
/* enable ADC calibration process */ /* enable ADC calibration process */
ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
/* check the CLB bit state */ /* check the CLB bit state */
while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ while ((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) {
} }
} }
@ -173,7 +173,7 @@ void adc_tempsensor_vrefint_disable(void)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
{ {
ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES);
ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution;
@ -195,21 +195,21 @@ void adc_resolution_config(uint32_t adc_periph , uint32_t resolution)
*/ */
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
{ {
ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
switch(adc_channel_group){ switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
/* config the number of conversions in discontinuous mode */ /* config the number of conversions in discontinuous mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U)); ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U));
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
break; break;
case ADC_INSERTED_CHANNEL: case ADC_INSERTED_CHANNEL:
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
break; break;
case ADC_CHANNEL_DISCON_DISABLE: case ADC_CHANNEL_DISCON_DISABLE:
default: default:
break; break;
} }
} }
@ -249,26 +249,26 @@ void adc_mode_config(uint32_t mode)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
{ {
if(newvalue){ if (newvalue) {
if(0U != (function & ADC_SCAN_MODE)){ if (0U != (function & ADC_SCAN_MODE)) {
ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
} }
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
} }
if(0U != (function & ADC_CONTINUOUS_MODE)){ if (0U != (function & ADC_CONTINUOUS_MODE)) {
ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
} }
}else{ } else {
if(0U != (function & ADC_SCAN_MODE)){ if (0U != (function & ADC_SCAN_MODE)) {
ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
} }
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
} }
if(0U != (function & ADC_CONTINUOUS_MODE)){ if (0U != (function & ADC_CONTINUOUS_MODE)) {
ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
} }
} }
@ -285,11 +285,11 @@ void adc_special_function_config(uint32_t adc_periph , uint32_t function , Contr
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
{ {
if(ADC_DATAALIGN_RIGHT != data_alignment){ if (ADC_DATAALIGN_RIGHT != data_alignment) {
ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
}else{ } else {
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
} }
} }
@ -310,19 +310,19 @@ void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment)
*/ */
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
{ {
switch(adc_channel_group){ switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - 1U));
break; break;
case ADC_INSERTED_CHANNEL: case ADC_INSERTED_CHANNEL:
ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U)); ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - 1U));
break; break;
default: default:
break; break;
} }
} }
@ -347,41 +347,41 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
{ {
uint32_t rsq,sampt; uint32_t rsq, sampt;
/* ADC regular sequence config */ /* ADC regular sequence config */
if(rank < 6U){ if (rank < 6U) {
rsq = ADC_RSQ2(adc_periph); rsq = ADC_RSQ2(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * rank)));
rsq |= ((uint32_t)adc_channel << (5U*rank)); rsq |= ((uint32_t)adc_channel << (5U * rank));
ADC_RSQ2(adc_periph) = rsq; ADC_RSQ2(adc_periph) = rsq;
}else if(rank < 12U){ } else if (rank < 12U) {
rsq = ADC_RSQ1(adc_periph); rsq = ADC_RSQ1(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 6U))));
rsq |= ((uint32_t)adc_channel << (5U*(rank-6U))); rsq |= ((uint32_t)adc_channel << (5U * (rank - 6U)));
ADC_RSQ1(adc_periph) = rsq; ADC_RSQ1(adc_periph) = rsq;
}else if(rank < 16U){ } else if (rank < 16U) {
rsq = ADC_RSQ0(adc_periph); rsq = ADC_RSQ0(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 12U))));
rsq |= ((uint32_t)adc_channel << (5U*(rank-12U))); rsq |= ((uint32_t)adc_channel << (5U * (rank - 12U)));
ADC_RSQ0(adc_periph) = rsq; ADC_RSQ0(adc_periph) = rsq;
}else{ } else {
} }
/* ADC sampling time config */ /* ADC sampling time config */
if(adc_channel < 10U){ if (adc_channel < 10U) {
sampt = ADC_SAMPT1(adc_periph); sampt = ADC_SAMPT1(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * adc_channel)));
sampt |= (uint32_t)(sample_time << (3U*adc_channel)); sampt |= (uint32_t)(sample_time << (3U * adc_channel));
ADC_SAMPT1(adc_periph) = sampt; ADC_SAMPT1(adc_periph) = sampt;
}else if(adc_channel < 18U){ } else if (adc_channel < 18U) {
sampt = ADC_SAMPT0(adc_periph); sampt = ADC_SAMPT0(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (adc_channel - 10U))));
sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U))); sampt |= (uint32_t)(sample_time << (3U * (adc_channel - 10U)));
ADC_SAMPT0(adc_periph) = sampt; ADC_SAMPT0(adc_periph) = sampt;
}else{ } else {
} }
} }
@ -406,30 +406,30 @@ void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
{ {
uint8_t inserted_length; uint8_t inserted_length;
uint32_t isq,sampt; uint32_t isq, sampt;
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
isq = ADC_ISQ(adc_periph); isq = ADC_ISQ(adc_periph);
isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U))); isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank) * 5U)));
isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U)); isq |= ((uint32_t)adc_channel << (15U - (inserted_length - rank) * 5U));
ADC_ISQ(adc_periph) = isq; ADC_ISQ(adc_periph) = isq;
/* ADC sampling time config */ /* ADC sampling time config */
if(adc_channel < 10U){ if (adc_channel < 10U) {
sampt = ADC_SAMPT1(adc_periph); sampt = ADC_SAMPT1(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * adc_channel)));
sampt |= (uint32_t) sample_time << (3U*adc_channel); sampt |= (uint32_t) sample_time << (3U * adc_channel);
ADC_SAMPT1(adc_periph) = sampt; ADC_SAMPT1(adc_periph) = sampt;
}else if(adc_channel < 18U){ } else if (adc_channel < 18U) {
sampt = ADC_SAMPT0(adc_periph); sampt = ADC_SAMPT0(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (adc_channel - 10U))));
sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U))); sampt |= ((uint32_t)sample_time << (3U * (adc_channel - 10U)));
ADC_SAMPT0(adc_periph) = sampt; ADC_SAMPT0(adc_periph) = sampt;
}else{ } else {
} }
} }
@ -447,15 +447,15 @@ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t ad
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
{ {
uint8_t inserted_length; uint8_t inserted_length;
uint32_t num = 0U; uint32_t num = 0U;
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
num = 3U - (inserted_length - inserted_channel); num = 3U - (inserted_length - inserted_channel);
if(num <= 3U){ if (num <= 3U) {
/* calculate the offset of the register */ /* calculate the offset of the register */
num = num * 4U; num = num * 4U;
/* config the offset of the selected channels */ /* config the offset of the selected channels */
@ -477,18 +477,18 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_c
*/ */
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
{ {
if(newvalue){ if (newvalue) {
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
} }
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
} }
}else{ } else {
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
} }
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
} }
} }
@ -543,17 +543,17 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group,
*/ */
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
{ {
switch(adc_channel_group){ switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
break; break;
case ADC_INSERTED_CHANNEL: case ADC_INSERTED_CHANNEL:
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
break; break;
default: default:
break; break;
} }
} }
@ -568,12 +568,12 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group) void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{ {
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
} }
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
} }
} }
@ -604,26 +604,26 @@ uint16_t adc_regular_data_read(uint32_t adc_periph)
\param[out] none \param[out] none
\retval the conversion value \retval the conversion value
*/ */
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
{ {
uint32_t idata; uint32_t idata;
/* read the data of the selected channel */ /* read the data of the selected channel */
switch(inserted_channel){ switch (inserted_channel) {
case ADC_INSERTED_CHANNEL_0: case ADC_INSERTED_CHANNEL_0:
idata = ADC_IDATA0(adc_periph); idata = ADC_IDATA0(adc_periph);
break; break;
case ADC_INSERTED_CHANNEL_1: case ADC_INSERTED_CHANNEL_1:
idata = ADC_IDATA1(adc_periph); idata = ADC_IDATA1(adc_periph);
break; break;
case ADC_INSERTED_CHANNEL_2: case ADC_INSERTED_CHANNEL_2:
idata = ADC_IDATA2(adc_periph); idata = ADC_IDATA2(adc_periph);
break; break;
case ADC_INSERTED_CHANNEL_3: case ADC_INSERTED_CHANNEL_3:
idata = ADC_IDATA3(adc_periph); idata = ADC_IDATA3(adc_periph);
break; break;
default: default:
idata = 0U; idata = 0U;
break; break;
} }
return (uint16_t)idata; return (uint16_t)idata;
} }
@ -654,10 +654,10 @@ uint32_t adc_sync_mode_convert_value_read(void)
\param[out] none \param[out] none
\retval FlagStatus: SET or RESET \retval FlagStatus: SET or RESET
*/ */
FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
{ {
FlagStatus reval = RESET; FlagStatus reval = RESET;
if(ADC_STAT(adc_periph) & adc_flag){ if (ADC_STAT(adc_periph) & adc_flag) {
reval = SET; reval = SET;
} }
return reval; return reval;
@ -677,7 +677,7 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
{ {
ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
} }
@ -694,32 +694,32 @@ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag)
\param[out] none \param[out] none
\retval FlagStatus: SET or RESET \retval FlagStatus: SET or RESET
*/ */
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
{ {
FlagStatus interrupt_flag = RESET; FlagStatus interrupt_flag = RESET;
uint32_t state; uint32_t state;
/* check the interrupt bits */ /* check the interrupt bits */
switch(adc_interrupt){ switch (adc_interrupt) {
case ADC_INT_FLAG_WDE: case ADC_INT_FLAG_WDE:
state = ADC_STAT(adc_periph) & ADC_STAT_WDE; state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ if ((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) {
interrupt_flag = SET; interrupt_flag = SET;
} }
break; break;
case ADC_INT_FLAG_EOC: case ADC_INT_FLAG_EOC:
state = ADC_STAT(adc_periph) & ADC_STAT_EOC; state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) {
interrupt_flag = SET; interrupt_flag = SET;
} }
break; break;
case ADC_INT_FLAG_EOIC: case ADC_INT_FLAG_EOIC:
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) {
interrupt_flag = SET; interrupt_flag = SET;
} }
break; break;
default: default:
break; break;
} }
return interrupt_flag; return interrupt_flag;
} }
@ -736,7 +736,7 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
{ {
ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
} }
@ -753,17 +753,17 @@ void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
{ {
if(0U != (adc_interrupt & ADC_INT_WDE)){ if (0U != (adc_interrupt & ADC_INT_WDE)) {
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
} }
if(0U != (adc_interrupt & ADC_INT_EOC)){ if (0U != (adc_interrupt & ADC_INT_EOC)) {
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
} }
if(0U != (adc_interrupt & ADC_INT_EOIC)){ if (0U != (adc_interrupt & ADC_INT_EOIC)) {
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
} }
} }
@ -782,15 +782,15 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt)
*/ */
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
{ {
if(0U != (adc_interrupt & ADC_INT_WDE)){ if (0U != (adc_interrupt & ADC_INT_WDE)) {
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
} }
if(0U != (adc_interrupt & ADC_INT_EOC)){ if (0U != (adc_interrupt & ADC_INT_EOC)) {
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
} }
if(0U != (adc_interrupt & ADC_INT_EOIC)){ if (0U != (adc_interrupt & ADC_INT_EOIC)) {
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
} }
} }
@ -829,18 +829,18 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_
{ {
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
/* select the group */ /* select the group */
switch(adc_channel_group){ switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
break; break;
case ADC_INSERTED_CHANNEL: case ADC_INSERTED_CHANNEL:
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
break; break;
case ADC_REGULAR_INSERTED_CHANNEL: case ADC_REGULAR_INSERTED_CHANNEL:
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
break; break;
default: default:
break; break;
} }
} }
@ -865,7 +865,7 @@ void adc_watchdog_disable(uint32_t adc_periph)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
{ {
ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
@ -905,9 +905,9 @@ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold
*/ */
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio)
{ {
if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ if (ADC_OVERSAMPLING_ONE_CONVERT == mode) {
ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS;
}else{ } else {
ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
} }
/* config the shift and ratio */ /* config the shift and ratio */

30
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c
View File

@ -61,11 +61,11 @@ void bkp_deinit(void)
*/ */
void bkp_write_data(bkp_data_register_enum register_number, uint16_t data) void bkp_write_data(bkp_data_register_enum register_number, uint16_t data)
{ {
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) {
BKP_DATA10_41(register_number-1U) = data; BKP_DATA10_41(register_number - 1U) = data;
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) {
BKP_DATA0_9(register_number-1U) = data; BKP_DATA0_9(register_number - 1U) = data;
}else{ } else {
/* illegal parameters */ /* illegal parameters */
} }
} }
@ -82,11 +82,11 @@ uint16_t bkp_read_data(bkp_data_register_enum register_number)
uint16_t data = 0U; uint16_t data = 0U;
/* get the data from the BKP data register */ /* get the data from the BKP data register */
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) {
data = BKP_DATA10_41(register_number-1U); data = BKP_DATA10_41(register_number - 1U);
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) {
data = BKP_DATA0_9(register_number-1U); data = BKP_DATA0_9(register_number - 1U);
}else{ } else {
/* illegal parameters */ /* illegal parameters */
} }
return data; return data;
@ -278,9 +278,9 @@ void bkp_tamper_interrupt_disable(void)
*/ */
FlagStatus bkp_flag_get(uint16_t flag) FlagStatus bkp_flag_get(uint16_t flag)
{ {
if(RESET != (BKP_TPCS & flag)){ if (RESET != (BKP_TPCS & flag)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -294,7 +294,7 @@ FlagStatus bkp_flag_get(uint16_t flag)
*/ */
void bkp_flag_clear(uint16_t flag) void bkp_flag_clear(uint16_t flag)
{ {
BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
} }
/*! /*!
@ -306,9 +306,9 @@ void bkp_flag_clear(uint16_t flag)
*/ */
FlagStatus bkp_interrupt_flag_get(uint16_t flag) FlagStatus bkp_interrupt_flag_get(uint16_t flag)
{ {
if(RESET != (BKP_TPCS & flag)){ if (RESET != (BKP_TPCS & flag)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }

242
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_can.c
View File

@ -46,15 +46,15 @@ OF SUCH DAMAGE.
void can_deinit(uint32_t can_periph) void can_deinit(uint32_t can_periph)
{ {
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
if(CAN0 == can_periph){ if (CAN0 == can_periph) {
rcu_periph_reset_enable(RCU_CAN0RST); rcu_periph_reset_enable(RCU_CAN0RST);
rcu_periph_reset_disable(RCU_CAN0RST); rcu_periph_reset_disable(RCU_CAN0RST);
}else{ } else {
rcu_periph_reset_enable(RCU_CAN1RST); rcu_periph_reset_enable(RCU_CAN1RST);
rcu_periph_reset_disable(RCU_CAN1RST); rcu_periph_reset_disable(RCU_CAN1RST);
} }
#else #else
if(CAN0 == can_periph){ if (CAN0 == can_periph) {
rcu_periph_reset_enable(RCU_CAN0RST); rcu_periph_reset_enable(RCU_CAN0RST);
rcu_periph_reset_disable(RCU_CAN0RST); rcu_periph_reset_disable(RCU_CAN0RST);
} }
@ -81,9 +81,9 @@ void can_deinit(uint32_t can_periph)
\retval ErrStatus: SUCCESS or ERROR \retval ErrStatus: SUCCESS or ERROR
*/ */
#ifdef GD_MBED_USED #ifdef GD_MBED_USED
ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct *can_parameter_init)
#else #else
ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init)
#endif #endif
{ {
uint32_t timeout = CAN_TIMEOUT; uint32_t timeout = CAN_TIMEOUT;
@ -94,13 +94,13 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
/* enable initialize mode */ /* enable initialize mode */
CAN_CTL(can_periph) |= CAN_CTL_IWMOD; CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
/* wait ACK */ /* wait ACK */
while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)) {
timeout--; timeout--;
} }
/* check initialize working success */ /* check initialize working success */
if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) {
flag = ERROR; flag = ERROR;
}else{ } else {
/* set the bit timing register */ /* set the bit timing register */
CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
@ -108,50 +108,50 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
/* time trigger communication mode */ /* time trigger communication mode */
if(ENABLE == can_parameter_init->time_triggered){ if (ENABLE == can_parameter_init->time_triggered) {
CAN_CTL(can_periph) |= CAN_CTL_TTC; CAN_CTL(can_periph) |= CAN_CTL_TTC;
}else{ } else {
CAN_CTL(can_periph) &= ~CAN_CTL_TTC; CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
} }
/* automatic bus-off managment */ /* automatic bus-off managment */
if(ENABLE == can_parameter_init->auto_bus_off_recovery){ if (ENABLE == can_parameter_init->auto_bus_off_recovery) {
CAN_CTL(can_periph) |= CAN_CTL_ABOR; CAN_CTL(can_periph) |= CAN_CTL_ABOR;
}else{ } else {
CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
} }
/* automatic wakeup mode */ /* automatic wakeup mode */
if(ENABLE == can_parameter_init->auto_wake_up){ if (ENABLE == can_parameter_init->auto_wake_up) {
CAN_CTL(can_periph) |= CAN_CTL_AWU; CAN_CTL(can_periph) |= CAN_CTL_AWU;
}else{ } else {
CAN_CTL(can_periph) &= ~CAN_CTL_AWU; CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
} }
/* automatic retransmission mode */ /* automatic retransmission mode */
if(ENABLE == can_parameter_init->auto_retrans){ if (ENABLE == can_parameter_init->auto_retrans) {
CAN_CTL(can_periph) |= CAN_CTL_ARD; CAN_CTL(can_periph) |= CAN_CTL_ARD;
}else{ } else {
CAN_CTL(can_periph) &= ~CAN_CTL_ARD; CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
} }
/* receive fifo overwrite mode */ /* receive fifo overwrite mode */
if(ENABLE == can_parameter_init->rec_fifo_overwrite){ if (ENABLE == can_parameter_init->rec_fifo_overwrite) {
CAN_CTL(can_periph) |= CAN_CTL_RFOD; CAN_CTL(can_periph) |= CAN_CTL_RFOD;
}else{ } else {
CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
} }
/* transmit fifo order */ /* transmit fifo order */
if(ENABLE == can_parameter_init->trans_fifo_order){ if (ENABLE == can_parameter_init->trans_fifo_order) {
CAN_CTL(can_periph) |= CAN_CTL_TFO; CAN_CTL(can_periph) |= CAN_CTL_TFO;
}else{ } else {
CAN_CTL(can_periph) &= ~CAN_CTL_TFO; CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
} }
/* disable initialize mode */ /* disable initialize mode */
CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
timeout = CAN_TIMEOUT; timeout = CAN_TIMEOUT;
/* wait the ACK */ /* wait the ACK */
while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ while ((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)) {
timeout--; timeout--;
} }
/* check exit initialize mode */ /* check exit initialize mode */
if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){ if (CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) {
flag = SUCCESS; flag = SUCCESS;
} }
} }
@ -173,7 +173,7 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
\param[out] none \param[out] none
\retval none \retval none
*/ */
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init)
{ {
uint32_t val = 0U; uint32_t val = 0U;
@ -184,52 +184,52 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
CAN_FW(CAN0) &= ~(uint32_t)val; CAN_FW(CAN0) &= ~(uint32_t)val;
/* filter 16 bits */ /* filter 16 bits */
if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ if (CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) {
/* set filter 16 bits */ /* set filter 16 bits */
CAN_FSCFG(CAN0) &= ~(uint32_t)val; CAN_FSCFG(CAN0) &= ~(uint32_t)val;
/* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
/* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
} }
/* filter 32 bits */ /* filter 32 bits */
if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ if (CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) {
/* set filter 32 bits */ /* set filter 32 bits */
CAN_FSCFG(CAN0) |= (uint32_t)val; CAN_FSCFG(CAN0) |= (uint32_t)val;
/* 32 bits list or first 32 bits list */ /* 32 bits list or first 32 bits list */
CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
/* 32 bits mask or second 32 bits list */ /* 32 bits mask or second 32 bits list */
CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
} }
/* filter mode */ /* filter mode */
if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ if (CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) {
/* mask mode */ /* mask mode */
CAN_FMCFG(CAN0) &= ~(uint32_t)val; CAN_FMCFG(CAN0) &= ~(uint32_t)val;
}else{ } else {
/* list mode */ /* list mode */
CAN_FMCFG(CAN0) |= (uint32_t)val; CAN_FMCFG(CAN0) |= (uint32_t)val;
} }
/* filter FIFO */ /* filter FIFO */
if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ if (CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) {
/* FIFO0 */ /* FIFO0 */
CAN_FAFIFO(CAN0) &= ~(uint32_t)val; CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
}else{ } else {
/* FIFO1 */ /* FIFO1 */
CAN_FAFIFO(CAN0) |= (uint32_t)val; CAN_FAFIFO(CAN0) |= (uint32_t)val;
} }
/* filter working */ /* filter working */
if(ENABLE == can_filter_parameter_init->filter_enable){ if (ENABLE == can_filter_parameter_init->filter_enable) {
CAN_FW(CAN0) |= (uint32_t)val; CAN_FW(CAN0) |= (uint32_t)val;
} }
@ -267,13 +267,13 @@ void can_debug_freeze_enable(uint32_t can_periph)
{ {
CAN_CTL(can_periph) |= CAN_CTL_DFZ; CAN_CTL(can_periph) |= CAN_CTL_DFZ;
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
if(CAN0 == can_periph){ if (CAN0 == can_periph) {
dbg_periph_enable(DBG_CAN0_HOLD); dbg_periph_enable(DBG_CAN0_HOLD);
}else{ } else {
dbg_periph_enable(DBG_CAN1_HOLD); dbg_periph_enable(DBG_CAN1_HOLD);
} }
#else #else
if(CAN0 == can_periph){ if (CAN0 == can_periph) {
dbg_periph_enable(DBG_CAN0_HOLD); dbg_periph_enable(DBG_CAN0_HOLD);
} }
#endif #endif
@ -290,13 +290,13 @@ void can_debug_freeze_disable(uint32_t can_periph)
{ {
CAN_CTL(can_periph) |= CAN_CTL_DFZ; CAN_CTL(can_periph) |= CAN_CTL_DFZ;
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
if(CAN0 == can_periph){ if (CAN0 == can_periph) {
dbg_periph_disable(DBG_CAN0_HOLD); dbg_periph_disable(DBG_CAN0_HOLD);
}else{ } else {
dbg_periph_disable(DBG_CAN1_HOLD); dbg_periph_disable(DBG_CAN1_HOLD);
} }
#else #else
if(CAN0 == can_periph){ if (CAN0 == can_periph) {
dbg_periph_enable(DBG_CAN0_HOLD); dbg_periph_enable(DBG_CAN0_HOLD);
} }
#endif #endif
@ -316,7 +316,7 @@ void can_time_trigger_mode_enable(uint32_t can_periph)
/* enable the tcc mode */ /* enable the tcc mode */
CAN_CTL(can_periph) |= CAN_CTL_TTC; CAN_CTL(can_periph) |= CAN_CTL_TTC;
/* enable time stamp */ /* enable time stamp */
for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
} }
} }
@ -335,7 +335,7 @@ void can_time_trigger_mode_disable(uint32_t can_periph)
/* disable the TCC mode */ /* disable the TCC mode */
CAN_CTL(can_periph) &= ~CAN_CTL_TTC; CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
/* reset TSEN bits */ /* reset TSEN bits */
for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
} }
} }
@ -354,34 +354,34 @@ void can_time_trigger_mode_disable(uint32_t can_periph)
\param[out] none \param[out] none
\retval mailbox_number \retval mailbox_number
*/ */
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message)
{ {
uint8_t mailbox_number = CAN_MAILBOX0; uint8_t mailbox_number = CAN_MAILBOX0;
/* select one empty mailbox */ /* select one empty mailbox */
if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ if (CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) {
mailbox_number = CAN_MAILBOX0; mailbox_number = CAN_MAILBOX0;
}else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ } else if (CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) {
mailbox_number = CAN_MAILBOX1; mailbox_number = CAN_MAILBOX1;
}else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ } else if (CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) {
mailbox_number = CAN_MAILBOX2; mailbox_number = CAN_MAILBOX2;
}else{ } else {
mailbox_number = CAN_NOMAILBOX; mailbox_number = CAN_NOMAILBOX;
} }
if(CAN_NOMAILBOX == mailbox_number){ if (CAN_NOMAILBOX == mailbox_number) {
return CAN_NOMAILBOX; return CAN_NOMAILBOX;
} }
CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
if(CAN_FF_STANDARD == transmit_message->tx_ff){ if (CAN_FF_STANDARD == transmit_message->tx_ff) {
/* set transmit mailbox standard identifier */ /* set transmit mailbox standard identifier */
CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
transmit_message->tx_ft); transmit_message->tx_ft);
}else{ } else {
/* set transmit mailbox extended identifier */ /* set transmit mailbox extended identifier */
CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
transmit_message->tx_ff | \ transmit_message->tx_ff | \
transmit_message->tx_ft); transmit_message->tx_ft);
} }
/* set the data length */ /* set the data length */
CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC); CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC);
@ -415,38 +415,38 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox
can_transmit_state_enum state = CAN_TRANSMIT_FAILED; can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
uint32_t val = 0U; uint32_t val = 0U;
switch(mailbox_number){ switch (mailbox_number) {
case CAN_MAILBOX0: case CAN_MAILBOX0:
val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
break; break;
case CAN_MAILBOX1: case CAN_MAILBOX1:
val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1);
break; break;
case CAN_MAILBOX2: case CAN_MAILBOX2:
val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2);
break; break;
default: default:
val = CAN_TRANSMIT_FAILED; val = CAN_TRANSMIT_FAILED;
break; break;
} }
switch(val){ switch (val) {
/* transmit pending */ /* transmit pending */
case (CAN_STATE_PENDING): case (CAN_STATE_PENDING):
state = CAN_TRANSMIT_PENDING; state = CAN_TRANSMIT_PENDING;
break; break;
/* transmit succeeded */ /* transmit succeeded */
case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
state = CAN_TRANSMIT_OK; state = CAN_TRANSMIT_OK;
break; break;
case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1):
state = CAN_TRANSMIT_OK; state = CAN_TRANSMIT_OK;
break; break;
case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2):
state = CAN_TRANSMIT_OK; state = CAN_TRANSMIT_OK;
break; break;
default: default:
state = CAN_TRANSMIT_FAILED; state = CAN_TRANSMIT_FAILED;
break; break;
} }
return state; return state;
} }
@ -463,13 +463,13 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox
*/ */
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
{ {
if(CAN_MAILBOX0 == mailbox_number){ if (CAN_MAILBOX0 == mailbox_number) {
CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
}else if(CAN_MAILBOX1 == mailbox_number){ } else if (CAN_MAILBOX1 == mailbox_number) {
CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
}else if(CAN_MAILBOX2 == mailbox_number){ } else if (CAN_MAILBOX2 == mailbox_number) {
CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
}else{ } else {
/* illegal parameters */ /* illegal parameters */
} }
} }
@ -490,14 +490,14 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
\arg rx_fi: 0 - 27 \arg rx_fi: 0 - 27
\retval none \retval none
*/ */
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message)
{ {
/* get the frame format */ /* get the frame format */
receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
if(CAN_FF_STANDARD == receive_message->rx_ff){ if (CAN_FF_STANDARD == receive_message->rx_ff) {
/* get standard identifier */ /* get standard identifier */
receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
}else{ } else {
/* get extended identifier */ /* get extended identifier */
receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
} }
@ -520,9 +520,9 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m
receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
/* release FIFO */ /* release FIFO */
if(CAN_FIFO0 == fifo_number){ if (CAN_FIFO0 == fifo_number) {
CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
}else{ } else {
CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
} }
} }
@ -538,11 +538,11 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m
*/ */
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
{ {
if(CAN_FIFO0 == fifo_number){ if (CAN_FIFO0 == fifo_number) {
CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
}else if(CAN_FIFO1 == fifo_number){ } else if (CAN_FIFO1 == fifo_number) {
CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
}else{ } else {
/* illegal parameters */ /* illegal parameters */
} }
} }
@ -560,11 +560,11 @@ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
{ {
uint8_t val = 0U; uint8_t val = 0U;
if(CAN_FIFO0 == fifo_number){ if (CAN_FIFO0 == fifo_number) {
val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
}else if(CAN_FIFO1 == fifo_number){ } else if (CAN_FIFO1 == fifo_number) {
val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
}else{ } else {
/* illegal parameters */ /* illegal parameters */
} }
return val; return val;
@ -587,47 +587,47 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
/* timeout for IWS or also for SLPWS bits */ /* timeout for IWS or also for SLPWS bits */
uint32_t timeout = CAN_TIMEOUT; uint32_t timeout = CAN_TIMEOUT;
if(CAN_MODE_INITIALIZE == working_mode){ if (CAN_MODE_INITIALIZE == working_mode) {
/* disable sleep mode */ /* disable sleep mode */
CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
/* set initialize mode */ /* set initialize mode */
CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
/* wait the acknowledge */ /* wait the acknowledge */
while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) {
timeout--; timeout--;
} }
if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) {
flag = ERROR; flag = ERROR;
}else{ } else {
flag = SUCCESS; flag = SUCCESS;
} }
}else if(CAN_MODE_NORMAL == working_mode){ } else if (CAN_MODE_NORMAL == working_mode) {
/* enter normal mode */ /* enter normal mode */
CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
/* wait the acknowledge */ /* wait the acknowledge */
while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ while ((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) {
timeout--; timeout--;
} }
if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ if (0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) {
flag = ERROR; flag = ERROR;
}else{ } else {
flag = SUCCESS; flag = SUCCESS;
} }
}else if(CAN_MODE_SLEEP == working_mode){ } else if (CAN_MODE_SLEEP == working_mode) {
/* disable initialize mode */ /* disable initialize mode */
CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
/* set sleep mode */ /* set sleep mode */
CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
/* wait the acknowledge */ /* wait the acknowledge */
while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ while ((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) {
timeout--; timeout--;
} }
if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ if (CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) {
flag = ERROR; flag = ERROR;
}else{ } else {
flag = SUCCESS; flag = SUCCESS;
} }
}else{ } else {
flag = ERROR; flag = ERROR;
} }
return flag; return flag;
@ -648,12 +648,12 @@ ErrStatus can_wakeup(uint32_t can_periph)
/* wakeup */ /* wakeup */
CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ while ((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) {
timeout--; timeout--;
} }
if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ if (0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) {
flag = ERROR; flag = ERROR;
}else{ } else {
flag = SUCCESS; flag = SUCCESS;
} }
return flag; return flag;
@ -784,9 +784,9 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
*/ */
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
{ {
if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ if (RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -843,9 +843,9 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f
ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)));
/* get the staus of interrupt enale bit */ /* get the staus of interrupt enale bit */
ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)));
if(ret1 && ret2){ if (ret1 && ret2) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }

2
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c
View File

@ -119,7 +119,7 @@ uint32_t crc_single_data_calculate(uint32_t sdata)
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
{ {
uint32_t index; uint32_t index;
for(index = 0U; index < size; index++){ for (index = 0U; index < size; index++) {
CRC_DATA = array[index]; CRC_DATA = array[index];
} }
return (CRC_DATA); return (CRC_DATA);

26
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c
View File

@ -194,7 +194,7 @@ void ctc_counter_reload_value_config(uint16_t ctc_reload_value)
uint16_t ctc_counter_capture_value_read(void) uint16_t ctc_counter_capture_value_read(void)
{ {
uint16_t capture_value = 0U; uint16_t capture_value = 0U;
capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> 16); capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> 16);
return (capture_value); return (capture_value);
} }
@ -208,9 +208,9 @@ uint16_t ctc_counter_capture_value_read(void)
*/ */
FlagStatus ctc_counter_direction_read(void) FlagStatus ctc_counter_direction_read(void)
{ {
if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ if (RESET != (CTC_STAT & CTC_STAT_REFDIR)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -288,16 +288,16 @@ FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt)
{ {
uint32_t interrupt = 0U, intenable = 0U; uint32_t interrupt = 0U, intenable = 0U;
if(ctc_interrupt & CTC_FLAG_MASK){ if (ctc_interrupt & CTC_FLAG_MASK) {
intenable = CTC_CTL0 & CTC_CTL0_ERRIE; intenable = CTC_CTL0 & CTC_CTL0_ERRIE;
}else{ } else {
intenable = CTC_CTL0 & ctc_interrupt; intenable = CTC_CTL0 & ctc_interrupt;
} }
interrupt = CTC_STAT & ctc_interrupt; interrupt = CTC_STAT & ctc_interrupt;
if(interrupt && intenable){ if (interrupt && intenable) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -317,9 +317,9 @@ FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt)
*/ */
void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) void ctc_interrupt_flag_clear(uint32_t ctc_interrupt)
{ {
if(ctc_interrupt & CTC_FLAG_MASK){ if (ctc_interrupt & CTC_FLAG_MASK) {
CTC_INTC |= CTC_INTC_ERRIC; CTC_INTC |= CTC_INTC_ERRIC;
}else{ } else {
CTC_INTC |= ctc_interrupt; CTC_INTC |= ctc_interrupt;
} }
} }
@ -339,9 +339,9 @@ void ctc_interrupt_flag_clear(uint32_t ctc_interrupt)
*/ */
FlagStatus ctc_flag_get(uint32_t ctc_flag) FlagStatus ctc_flag_get(uint32_t ctc_flag)
{ {
if(RESET != (CTC_STAT & ctc_flag)){ if (RESET != (CTC_STAT & ctc_flag)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -361,9 +361,9 @@ FlagStatus ctc_flag_get(uint32_t ctc_flag)
*/ */
void ctc_flag_clear(uint32_t ctc_flag) void ctc_flag_clear(uint32_t ctc_flag)
{ {
if(ctc_flag & CTC_FLAG_MASK){ if (ctc_flag & CTC_FLAG_MASK) {
CTC_INTC |= CTC_INTC_ERRIC; CTC_INTC |= CTC_INTC_ERRIC;
}else{ } else {
CTC_INTC |= ctc_flag; CTC_INTC |= ctc_flag;
} }
} }

166
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c
View File

@ -57,9 +57,9 @@ void dac_deinit(void)
*/ */
void dac_enable(uint32_t dac_periph) void dac_enable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DEN0; DAC_CTL |= DAC_CTL_DEN0;
}else{ } else {
DAC_CTL |= DAC_CTL_DEN1; DAC_CTL |= DAC_CTL_DEN1;
} }
} }
@ -73,9 +73,9 @@ void dac_enable(uint32_t dac_periph)
*/ */
void dac_disable(uint32_t dac_periph) void dac_disable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DEN0; DAC_CTL &= ~DAC_CTL_DEN0;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DEN1; DAC_CTL &= ~DAC_CTL_DEN1;
} }
} }
@ -89,9 +89,9 @@ void dac_disable(uint32_t dac_periph)
*/ */
void dac_dma_enable(uint32_t dac_periph) void dac_dma_enable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DDMAEN0; DAC_CTL |= DAC_CTL_DDMAEN0;
}else{ } else {
DAC_CTL |= DAC_CTL_DDMAEN1; DAC_CTL |= DAC_CTL_DDMAEN1;
} }
} }
@ -105,9 +105,9 @@ void dac_dma_enable(uint32_t dac_periph)
*/ */
void dac_dma_disable(uint32_t dac_periph) void dac_dma_disable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DDMAEN0; DAC_CTL &= ~DAC_CTL_DDMAEN0;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DDMAEN1; DAC_CTL &= ~DAC_CTL_DDMAEN1;
} }
} }
@ -121,9 +121,9 @@ void dac_dma_disable(uint32_t dac_periph)
*/ */
void dac_output_buffer_enable(uint32_t dac_periph) void dac_output_buffer_enable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DBOFF0; DAC_CTL &= ~DAC_CTL_DBOFF0;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DBOFF1; DAC_CTL &= ~DAC_CTL_DBOFF1;
} }
} }
@ -137,9 +137,9 @@ void dac_output_buffer_enable(uint32_t dac_periph)
*/ */
void dac_output_buffer_disable(uint32_t dac_periph) void dac_output_buffer_disable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DBOFF0; DAC_CTL |= DAC_CTL_DBOFF0;
}else{ } else {
DAC_CTL |= DAC_CTL_DBOFF1; DAC_CTL |= DAC_CTL_DBOFF1;
} }
} }
@ -153,9 +153,9 @@ void dac_output_buffer_disable(uint32_t dac_periph)
*/ */
void dac_trigger_enable(uint32_t dac_periph) void dac_trigger_enable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DTEN0; DAC_CTL |= DAC_CTL_DTEN0;
}else{ } else {
DAC_CTL |= DAC_CTL_DTEN1; DAC_CTL |= DAC_CTL_DTEN1;
} }
} }
@ -169,9 +169,9 @@ void dac_trigger_enable(uint32_t dac_periph)
*/ */
void dac_trigger_disable(uint32_t dac_periph) void dac_trigger_disable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DTEN0; DAC_CTL &= ~DAC_CTL_DTEN0;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DTEN1; DAC_CTL &= ~DAC_CTL_DTEN1;
} }
} }
@ -184,9 +184,9 @@ void dac_trigger_disable(uint32_t dac_periph)
*/ */
void dac_software_trigger_enable(uint32_t dac_periph) void dac_software_trigger_enable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_SWT |= DAC_SWT_SWTR0; DAC_SWT |= DAC_SWT_SWTR0;
}else{ } else {
DAC_SWT |= DAC_SWT_SWTR1; DAC_SWT |= DAC_SWT_SWTR1;
} }
} }
@ -200,9 +200,9 @@ void dac_software_trigger_enable(uint32_t dac_periph)
*/ */
void dac_software_trigger_disable(uint32_t dac_periph) void dac_software_trigger_disable(uint32_t dac_periph)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_SWT &= ~DAC_SWT_SWTR0; DAC_SWT &= ~DAC_SWT_SWTR0;
}else{ } else {
DAC_SWT &= ~DAC_SWT_SWTR1; DAC_SWT &= ~DAC_SWT_SWTR1;
} }
} }
@ -224,12 +224,12 @@ void dac_software_trigger_disable(uint32_t dac_periph)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DTSEL0; DAC_CTL &= ~DAC_CTL_DTSEL0;
DAC_CTL |= triggersource; DAC_CTL |= triggersource;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DTSEL1; DAC_CTL &= ~DAC_CTL_DTSEL1;
DAC_CTL |= (triggersource << 16); DAC_CTL |= (triggersource << 16);
} }
@ -248,10 +248,10 @@ void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
*/ */
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DWM0; DAC_CTL &= ~DAC_CTL_DWM0;
DAC_CTL |= wave_mode; DAC_CTL |= wave_mode;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DWM1; DAC_CTL &= ~DAC_CTL_DWM1;
DAC_CTL |= wave_mode << 16; DAC_CTL |= wave_mode << 16;
} }
@ -279,10 +279,10 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
*/ */
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL &= ~DAC_CTL_DWBW0;
DAC_CTL |= bit_width; DAC_CTL |= bit_width;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL &= ~DAC_CTL_DWBW1;
DAC_CTL |= bit_width << 16; DAC_CTL |= bit_width << 16;
} }
@ -310,10 +310,10 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
*/ */
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL &= ~DAC_CTL_DWBW0;
DAC_CTL |= unmask_bits; DAC_CTL |= unmask_bits;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL &= ~DAC_CTL_DWBW1;
DAC_CTL |= unmask_bits << 16; DAC_CTL |= unmask_bits << 16;
} }
@ -341,10 +341,10 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
*/ */
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL &= ~DAC_CTL_DWBW0;
DAC_CTL |= amplitude; DAC_CTL |= amplitude;
}else{ } else {
DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL &= ~DAC_CTL_DWBW1;
DAC_CTL |= amplitude << 16; DAC_CTL |= amplitude << 16;
} }
@ -360,9 +360,9 @@ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
uint16_t dac_output_value_get(uint32_t dac_periph) uint16_t dac_output_value_get(uint32_t dac_periph)
{ {
uint16_t data = 0U; uint16_t data = 0U;
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
data = (uint16_t)DAC0_DO; data = (uint16_t)DAC0_DO;
}else{ } else {
data = (uint16_t)DAC1_DO; data = (uint16_t)DAC1_DO;
} }
return data; return data;
@ -460,39 +460,39 @@ void dac_concurrent_output_buffer_disable(void)
*/ */
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
{ {
if(DAC0 == dac_periph){ if (DAC0 == dac_periph) {
switch(dac_align){ switch (dac_align) {
/* data right 12b alignment */ /* data right 12b alignment */
case DAC_ALIGN_12B_R: case DAC_ALIGN_12B_R:
DAC0_R12DH = data; DAC0_R12DH = data;
break; break;
/* data left 12b alignment */ /* data left 12b alignment */
case DAC_ALIGN_12B_L: case DAC_ALIGN_12B_L:
DAC0_L12DH = data; DAC0_L12DH = data;
break; break;
/* data right 8b alignment */ /* data right 8b alignment */
case DAC_ALIGN_8B_R: case DAC_ALIGN_8B_R:
DAC0_R8DH = data; DAC0_R8DH = data;
break; break;
default: default:
break; break;
} }
}else{ } else {
switch(dac_align){ switch (dac_align) {
/* data right 12b alignment */ /* data right 12b alignment */
case DAC_ALIGN_12B_R: case DAC_ALIGN_12B_R:
DAC1_R12DH = data; DAC1_R12DH = data;
break; break;
/* data left 12b alignment */ /* data left 12b alignment */
case DAC_ALIGN_12B_L: case DAC_ALIGN_12B_L:
DAC1_L12DH = data; DAC1_L12DH = data;
break; break;
/* data right 8b alignment */ /* data right 8b alignment */
case DAC_ALIGN_8B_R: case DAC_ALIGN_8B_R:
DAC1_R8DH = data; DAC1_R8DH = data;
break; break;
default: default:
break; break;
} }
} }
} }
@ -511,23 +511,23 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
{ {
uint32_t data = 0U; uint32_t data = 0U;
switch(dac_align){ switch (dac_align) {
/* data right 12b alignment */ /* data right 12b alignment */
case DAC_ALIGN_12B_R: case DAC_ALIGN_12B_R:
data = ((uint32_t)data1 << 16) | data0; data = ((uint32_t)data1 << 16) | data0;
DACC_R12DH = data; DACC_R12DH = data;
break; break;
/* data left 12b alignment */ /* data left 12b alignment */
case DAC_ALIGN_12B_L: case DAC_ALIGN_12B_L:
data = ((uint32_t)data1 << 16) | data0; data = ((uint32_t)data1 << 16) | data0;
DACC_L12DH = data; DACC_L12DH = data;
break; break;
/* data right 8b alignment */ /* data right 8b alignment */
case DAC_ALIGN_8B_R: case DAC_ALIGN_8B_R:
data = ((uint32_t)data1 << 8) | data0; data = ((uint32_t)data1 << 8) | data0;
DACC_R8DH = data; DACC_R8DH = data;
break; break;
default: default:
break; break;
} }
} }

78
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c
View File

@ -51,7 +51,7 @@ static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_e
*/ */
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -92,7 +92,7 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru
{ {
uint32_t ctl; uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -112,23 +112,23 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru
DMA_CHCTL(dma_periph, channelx) = ctl; DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */ /* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ if (DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc) {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}else{ } else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} }
/* configure memory increasing mode */ /* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ if (DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc) {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}else{ } else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
} }
/* configure the direction of data transfer */ /* configure the direction of data transfer */
if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){ if (DMA_PERIPHERAL_TO_MEMORY == init_struct.direction) {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
}else{ } else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
} }
} }
@ -144,7 +144,7 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru
*/ */
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -162,7 +162,7 @@ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -180,7 +180,7 @@ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -198,7 +198,7 @@ void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -216,7 +216,7 @@ void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx
*/ */
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -234,7 +234,7 @@ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -253,7 +253,7 @@ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -272,7 +272,7 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u
*/ */
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -291,7 +291,7 @@ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, u
*/ */
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -309,7 +309,7 @@ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx,
*/ */
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -334,7 +334,7 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_
{ {
uint32_t ctl; uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -359,11 +359,11 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_
\param[out] none \param[out] none
\retval none \retval none
*/ */
void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
{ {
uint32_t ctl; uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -388,11 +388,11 @@ void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, ui
\param[out] none \param[out] none
\retval none \retval none
*/ */
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
{ {
uint32_t ctl; uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -415,7 +415,7 @@ void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, ui
*/ */
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -433,7 +433,7 @@ void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -451,7 +451,7 @@ void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -469,7 +469,7 @@ void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -490,11 +490,11 @@ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
if(DMA_PERIPHERAL_TO_MEMORY == direction){ if (DMA_PERIPHERAL_TO_MEMORY == direction) {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
} else { } else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
@ -520,9 +520,9 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t
{ {
FlagStatus reval; FlagStatus reval;
if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ if (RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))) {
reval = SET; reval = SET;
}else{ } else {
reval = RESET; reval = RESET;
} }
@ -567,7 +567,7 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
{ {
uint32_t interrupt_enable = 0U, interrupt_flag = 0U; uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(flag){ switch (flag) {
case DMA_INT_FLAG_FTF: case DMA_INT_FLAG_FTF:
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
@ -582,11 +582,11 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
break; break;
default: default:
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
if(interrupt_flag && interrupt_enable){ if (interrupt_flag && interrupt_enable) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -627,7 +627,7 @@ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, ui
*/ */
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -650,7 +650,7 @@ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32
*/ */
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{ {
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -670,8 +670,8 @@ static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_e
{ {
ErrStatus val = SUCCESS; ErrStatus val = SUCCESS;
if(DMA1 == dma_periph){ if (DMA1 == dma_periph) {
if(channelx > DMA_CH4){ if (channelx > DMA_CH4) {
val = ERROR; val = ERROR;
} }
} }

1010
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c
View File

File diff suppressed because it is too large Load Diff

160
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c
View File

@ -99,9 +99,9 @@ OF SUCH DAMAGE.
void exmc_norsram_deinit(uint32_t exmc_norsram_region) void exmc_norsram_deinit(uint32_t exmc_norsram_region)
{ {
/* reset the registers */ /* reset the registers */
if(EXMC_BANK0_NORSRAM_REGION0 == exmc_norsram_region){ if (EXMC_BANK0_NORSRAM_REGION0 == exmc_norsram_region) {
EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET; EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET;
}else{ } else {
EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET; EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET;
} }
EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET;
@ -129,9 +129,9 @@ void exmc_norsram_deinit(uint32_t exmc_norsram_region)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
{ {
uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U;
/* get the register value */ /* get the register value */
snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
@ -140,42 +140,42 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG |
EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT |
EXMC_SNCTL_SYNCWR )); EXMC_SNCTL_SYNCWR));
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
exmc_norsram_init_struct->memory_type | exmc_norsram_init_struct->memory_type |
exmc_norsram_init_struct->databus_width | exmc_norsram_init_struct->databus_width |
(exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) |
exmc_norsram_init_struct->nwait_polarity | exmc_norsram_init_struct->nwait_polarity |
(exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) |
exmc_norsram_init_struct->nwait_config | exmc_norsram_init_struct->nwait_config |
(exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
(exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
(exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) |
(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
exmc_norsram_init_struct->write_mode; exmc_norsram_init_struct->write_mode;
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET) |
(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD) |
(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET) |
(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )| (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT) |
exmc_norsram_init_struct->read_write_timing->syn_clk_division | exmc_norsram_init_struct->read_write_timing->syn_clk_division |
exmc_norsram_init_struct->read_write_timing->syn_data_latency | exmc_norsram_init_struct->read_write_timing->syn_data_latency |
exmc_norsram_init_struct->read_write_timing->asyn_access_mode; exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
/* nor flash access enable */ /* nor flash access enable */
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ if (EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) {
snctl |= (uint32_t)EXMC_SNCTL_NREN; snctl |= (uint32_t)EXMC_SNCTL_NREN;
} }
/* extended mode configure */ /* extended mode configure */
if(ENABLE == exmc_norsram_init_struct->extended_mode){ if (ENABLE == exmc_norsram_init_struct->extended_mode) {
snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET ) | snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) |
(((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD )| (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNWTCFG_WAHLD_OFFSET) & EXMC_SNWTCFG_WAHLD) |
(((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & EXMC_SNWTCFG_WDSET )| (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNWTCFG_WDSET_OFFSET) & EXMC_SNWTCFG_WDSET) |
(((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_SNWTCFG_WBUSLAT ) | (((exmc_norsram_init_struct->write_timing->bus_latency - 1U) << SNWTCFG_WBUSLAT_OFFSET) & EXMC_SNWTCFG_WBUSLAT) |
exmc_norsram_init_struct->write_timing->asyn_access_mode; exmc_norsram_init_struct->write_timing->asyn_access_mode;
}else{ } else {
snwtcfg = BANK0_SNWTCFG_RESET; snwtcfg = BANK0_SNWTCFG_RESET;
} }
@ -191,7 +191,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
\param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer
\retval none \retval none
*/ */
void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) void exmc_norsram_parameter_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
{ {
/* configure the structure with default value */ /* configure the structure with default value */
exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
@ -302,27 +302,27 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct)
{ {
uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U;
npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) |
EXMC_NPCTL_NDTP | EXMC_NPCTL_NDTP |
exmc_nand_init_struct->databus_width | exmc_nand_init_struct->databus_width |
(exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET) |
exmc_nand_init_struct->ecc_size | exmc_nand_init_struct->ecc_size |
exmc_nand_init_struct->ctr_latency | exmc_nand_init_struct->ctr_latency |
exmc_nand_init_struct->atr_latency; exmc_nand_init_struct->atr_latency;
npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) |
(((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) |
((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) |
(((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ);
npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) |
(((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) |
((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) |
(((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ);
/* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */
EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
@ -336,7 +336,7 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
\param[out] the initialized struct exmc_norsram_parameter_struct pointer \param[out] the initialized struct exmc_norsram_parameter_struct pointer
\retval none \retval none
*/ */
void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct) void exmc_nand_parameter_init(exmc_nand_parameter_struct *exmc_nand_init_struct)
{ {
/* configure the structure with default value */ /* configure the structure with default value */
exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND;
@ -390,10 +390,10 @@ void exmc_nand_disable(uint32_t exmc_nand_bank)
*/ */
void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue)
{ {
if (ENABLE == newvalue){ if (ENABLE == newvalue) {
/* enable the selected NAND bank ECC function */ /* enable the selected NAND bank ECC function */
EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN;
}else{ } else {
/* disable the selected NAND bank ECC function */ /* disable the selected NAND bank ECC function */
EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_ECCEN); EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_ECCEN);
} }
@ -439,31 +439,31 @@ void exmc_pccard_deinit(void)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct)
{ {
/* configure the EXMC bank3 PC card control register */ /* configure the EXMC bank3 PC card control register */
EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) |
EXMC_NAND_DATABUS_WIDTH_16B | EXMC_NAND_DATABUS_WIDTH_16B |
exmc_pccard_init_struct->ctr_latency | exmc_pccard_init_struct->ctr_latency |
exmc_pccard_init_struct->atr_latency ; exmc_pccard_init_struct->atr_latency ;
/* configure the EXMC bank3 PC card common space timing configuration register */ /* configure the EXMC bank3 PC card common space timing configuration register */
EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) | EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET) |
(((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) |
((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) |
(((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ);
/* configure the EXMC bank3 PC card attribute space timing configuration register */ /* configure the EXMC bank3 PC card attribute space timing configuration register */
EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) |
(((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) |
((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )| ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) |
(((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ);
/* configure the EXMC bank3 PC card io space timing configuration register */ /* configure the EXMC bank3 PC card io space timing configuration register */
EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET) |
(((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT) |
((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )| ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD) |
((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ);
} }
/*! /*!
@ -472,7 +472,7 @@ void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct)
\param[out] the initialized struct exmc_pccard_parameter_struct pointer \param[out] the initialized struct exmc_pccard_parameter_struct pointer
\retval none \retval none
*/ */
void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) void exmc_pccard_parameter_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct)
{ {
/* configure the structure with default value */ /* configure the structure with default value */
exmc_pccard_init_struct->wait_feature = DISABLE; exmc_pccard_init_struct->wait_feature = DISABLE;
@ -511,7 +511,7 @@ void exmc_pccard_enable(void)
*/ */
void exmc_pccard_disable(void) void exmc_pccard_disable(void)
{ {
EXMC_NPCTL3 &= (~EXMC_NPCTL_NDBKEN); EXMC_NPCTL3 &= (~EXMC_NPCTL_NDBKEN);
} }
/*! /*!
@ -528,17 +528,17 @@ void exmc_pccard_disable(void)
\param[out] none \param[out] none
\retval FlagStatus: SET or RESET \retval FlagStatus: SET or RESET
*/ */
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag)
{ {
uint32_t status = 0x00000000U; uint32_t status = 0x00000000U;
/* NAND bank1,bank2 or PC card bank3 */ /* NAND bank1,bank2 or PC card bank3 */
status = EXMC_NPINTEN(exmc_bank); status = EXMC_NPINTEN(exmc_bank);
if ((status & flag) != (uint32_t)flag ){ if ((status & flag) != (uint32_t)flag) {
/* flag is reset */ /* flag is reset */
return RESET; return RESET;
}else{ } else {
/* flag is set */ /* flag is set */
return SET; return SET;
} }
@ -558,7 +558,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag)
{ {
/* NAND bank1,bank2 or PC card bank3 */ /* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) &= (~flag); EXMC_NPINTEN(exmc_bank) &= (~flag);
@ -577,9 +577,9 @@ void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag)
\param[out] none \param[out] none
\retval FlagStatus: SET or RESET \retval FlagStatus: SET or RESET
*/ */
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source) FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt_source)
{ {
uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U;
/* NAND bank1,bank2 or PC card bank3 */ /* NAND bank1,bank2 or PC card bank3 */
status = EXMC_NPINTEN(exmc_bank); status = EXMC_NPINTEN(exmc_bank);
@ -587,10 +587,10 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source)
interrupt_enable = (status & interrupt_source); interrupt_enable = (status & interrupt_source);
if ((interrupt_enable) && (interrupt_state)){ if ((interrupt_enable) && (interrupt_state)) {
/* interrupt flag is set */ /* interrupt flag is set */
return SET; return SET;
}else{ } else {
/* interrupt flag is reset */ /* interrupt flag is reset */
return RESET; return RESET;
} }
@ -609,7 +609,7 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source) void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt_source)
{ {
/* NAND bank1,bank2 or PC card bank3 */ /* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); EXMC_NPINTEN(exmc_bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET);
@ -628,7 +628,7 @@ void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source) void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt_source)
{ {
/* NAND bank1,bank2 or PC card bank3 */ /* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) |= interrupt_source; EXMC_NPINTEN(exmc_bank) |= interrupt_source;
@ -647,7 +647,7 @@ void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source) void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt_source)
{ {
/* NAND bank1,bank2 or PC card bank3 */ /* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) &= (~interrupt_source); EXMC_NPINTEN(exmc_bank) &= (~interrupt_source);

56
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c
View File

@ -78,33 +78,33 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
EXTI_FTEN &= ~(uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex;
/* set the EXTI mode and enable the interrupts or events from EXTI line x */ /* set the EXTI mode and enable the interrupts or events from EXTI line x */
switch(mode){ switch (mode) {
case EXTI_INTERRUPT: case EXTI_INTERRUPT:
EXTI_INTEN |= (uint32_t)linex; EXTI_INTEN |= (uint32_t)linex;
break; break;
case EXTI_EVENT: case EXTI_EVENT:
EXTI_EVEN |= (uint32_t)linex; EXTI_EVEN |= (uint32_t)linex;
break; break;
default: default:
break; break;
} }
/* set the EXTI trigger type */ /* set the EXTI trigger type */
switch(trig_type){ switch (trig_type) {
case EXTI_TRIG_RISING: case EXTI_TRIG_RISING:
EXTI_RTEN |= (uint32_t)linex; EXTI_RTEN |= (uint32_t)linex;
EXTI_FTEN &= ~(uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex;
break; break;
case EXTI_TRIG_FALLING: case EXTI_TRIG_FALLING:
EXTI_RTEN &= ~(uint32_t)linex; EXTI_RTEN &= ~(uint32_t)linex;
EXTI_FTEN |= (uint32_t)linex; EXTI_FTEN |= (uint32_t)linex;
break; break;
case EXTI_TRIG_BOTH: case EXTI_TRIG_BOTH:
EXTI_RTEN |= (uint32_t)linex; EXTI_RTEN |= (uint32_t)linex;
EXTI_FTEN |= (uint32_t)linex; EXTI_FTEN |= (uint32_t)linex;
break; break;
default: default:
break; break;
} }
} }
@ -170,9 +170,9 @@ void exti_event_disable(exti_line_enum linex)
*/ */
FlagStatus exti_flag_get(exti_line_enum linex) FlagStatus exti_flag_get(exti_line_enum linex)
{ {
if(RESET != (EXTI_PD & (uint32_t)linex)){ if (RESET != (EXTI_PD & (uint32_t)linex)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -205,9 +205,9 @@ FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
flag_left = EXTI_PD & (uint32_t)linex; flag_left = EXTI_PD & (uint32_t)linex;
flag_right = EXTI_INTEN & (uint32_t)linex; flag_right = EXTI_INTEN & (uint32_t)linex;
if((RESET != flag_left) && (RESET != flag_right)){ if ((RESET != flag_left) && (RESET != flag_right)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }

162
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c
View File

@ -63,14 +63,14 @@ void fmc_wscnt_set(uint32_t wscnt)
*/ */
void fmc_unlock(void) void fmc_unlock(void)
{ {
if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ if ((RESET != (FMC_CTL0 & FMC_CTL0_LK))) {
/* write the FMC unlock key */ /* write the FMC unlock key */
FMC_KEY0 = UNLOCK_KEY0; FMC_KEY0 = UNLOCK_KEY0;
FMC_KEY0 = UNLOCK_KEY1; FMC_KEY0 = UNLOCK_KEY1;
} }
if(FMC_BANK0_SIZE < FMC_SIZE){ if (FMC_BANK0_SIZE < FMC_SIZE) {
/* write the FMC unlock key */ /* write the FMC unlock key */
if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ if (RESET != (FMC_CTL1 & FMC_CTL1_LK)) {
FMC_KEY1 = UNLOCK_KEY0; FMC_KEY1 = UNLOCK_KEY0;
FMC_KEY1 = UNLOCK_KEY1; FMC_KEY1 = UNLOCK_KEY1;
} }
@ -88,7 +88,7 @@ void fmc_unlock(void)
*/ */
void fmc_bank0_unlock(void) void fmc_bank0_unlock(void)
{ {
if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ if ((RESET != (FMC_CTL0 & FMC_CTL0_LK))) {
/* write the FMC unlock key */ /* write the FMC unlock key */
FMC_KEY0 = UNLOCK_KEY0; FMC_KEY0 = UNLOCK_KEY0;
FMC_KEY0 = UNLOCK_KEY1; FMC_KEY0 = UNLOCK_KEY1;
@ -104,7 +104,7 @@ void fmc_bank0_unlock(void)
*/ */
void fmc_bank1_unlock(void) void fmc_bank1_unlock(void)
{ {
if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ if ((RESET != (FMC_CTL1 & FMC_CTL1_LK))) {
/* write the FMC unlock key */ /* write the FMC unlock key */
FMC_KEY1 = UNLOCK_KEY0; FMC_KEY1 = UNLOCK_KEY0;
FMC_KEY1 = UNLOCK_KEY1; FMC_KEY1 = UNLOCK_KEY1;
@ -122,7 +122,7 @@ void fmc_lock(void)
/* set the LK bit */ /* set the LK bit */
FMC_CTL0 |= FMC_CTL0_LK; FMC_CTL0 |= FMC_CTL0_LK;
if(FMC_BANK0_SIZE < FMC_SIZE){ if (FMC_BANK0_SIZE < FMC_SIZE) {
/* set the LK bit */ /* set the LK bit */
FMC_CTL1 |= FMC_CTL1_LK; FMC_CTL1 |= FMC_CTL1_LK;
} }
@ -166,11 +166,11 @@ fmc_state_enum fmc_page_erase(uint32_t page_address)
{ {
fmc_state_enum fmc_state; fmc_state_enum fmc_state;
if(FMC_BANK0_SIZE < FMC_SIZE){ if (FMC_BANK0_SIZE < FMC_SIZE) {
if(FMC_BANK0_END_ADDRESS > page_address){ if (FMC_BANK0_END_ADDRESS > page_address) {
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
/* if the last operation is completed, start page erase */ /* if the last operation is completed, start page erase */
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
FMC_CTL0 |= FMC_CTL0_PER; FMC_CTL0 |= FMC_CTL0_PER;
FMC_ADDR0 = page_address; FMC_ADDR0 = page_address;
FMC_CTL0 |= FMC_CTL0_START; FMC_CTL0 |= FMC_CTL0_START;
@ -179,14 +179,14 @@ fmc_state_enum fmc_page_erase(uint32_t page_address)
/* reset the PER bit */ /* reset the PER bit */
FMC_CTL0 &= ~FMC_CTL0_PER; FMC_CTL0 &= ~FMC_CTL0_PER;
} }
}else{ } else {
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
/* if the last operation is completed, start page erase */ /* if the last operation is completed, start page erase */
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
FMC_CTL1 |= FMC_CTL1_PER; FMC_CTL1 |= FMC_CTL1_PER;
FMC_ADDR1 = page_address; FMC_ADDR1 = page_address;
if(FMC_OBSTAT & FMC_OBSTAT_SPC){ if (FMC_OBSTAT & FMC_OBSTAT_SPC) {
FMC_ADDR0 = page_address; FMC_ADDR0 = page_address;
} }
FMC_CTL1 |= FMC_CTL1_START; FMC_CTL1 |= FMC_CTL1_START;
@ -196,10 +196,10 @@ fmc_state_enum fmc_page_erase(uint32_t page_address)
FMC_CTL1 &= ~FMC_CTL1_PER; FMC_CTL1 &= ~FMC_CTL1_PER;
} }
} }
}else{ } else {
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
/* if the last operation is completed, start page erase */ /* if the last operation is completed, start page erase */
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
FMC_CTL0 |= FMC_CTL0_PER; FMC_CTL0 |= FMC_CTL0_PER;
FMC_ADDR0 = page_address; FMC_ADDR0 = page_address;
FMC_CTL0 |= FMC_CTL0_START; FMC_CTL0 |= FMC_CTL0_START;
@ -222,10 +222,10 @@ fmc_state_enum fmc_page_erase(uint32_t page_address)
fmc_state_enum fmc_mass_erase(void) fmc_state_enum fmc_mass_erase(void)
{ {
fmc_state_enum fmc_state; fmc_state_enum fmc_state;
if(FMC_BANK0_SIZE < FMC_SIZE){ if (FMC_BANK0_SIZE < FMC_SIZE) {
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* start whole chip erase */ /* start whole chip erase */
FMC_CTL0 |= FMC_CTL0_MER; FMC_CTL0 |= FMC_CTL0_MER;
FMC_CTL0 |= FMC_CTL0_START; FMC_CTL0 |= FMC_CTL0_START;
@ -235,7 +235,7 @@ fmc_state_enum fmc_mass_erase(void)
FMC_CTL0 &= ~FMC_CTL0_MER; FMC_CTL0 &= ~FMC_CTL0_MER;
} }
fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* start whole chip erase */ /* start whole chip erase */
FMC_CTL1 |= FMC_CTL1_MER; FMC_CTL1 |= FMC_CTL1_MER;
FMC_CTL1 |= FMC_CTL1_START; FMC_CTL1 |= FMC_CTL1_START;
@ -244,10 +244,10 @@ fmc_state_enum fmc_mass_erase(void)
/* reset the MER bit */ /* reset the MER bit */
FMC_CTL1 &= ~FMC_CTL1_MER; FMC_CTL1 &= ~FMC_CTL1_MER;
} }
}else{ } else {
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* start whole chip erase */ /* start whole chip erase */
FMC_CTL0 |= FMC_CTL0_MER; FMC_CTL0 |= FMC_CTL0_MER;
FMC_CTL0 |= FMC_CTL0_START; FMC_CTL0 |= FMC_CTL0_START;
@ -273,7 +273,7 @@ fmc_state_enum fmc_bank0_erase(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* start FMC bank0 erase */ /* start FMC bank0 erase */
FMC_CTL0 |= FMC_CTL0_MER; FMC_CTL0 |= FMC_CTL0_MER;
FMC_CTL0 |= FMC_CTL0_START; FMC_CTL0 |= FMC_CTL0_START;
@ -298,7 +298,7 @@ fmc_state_enum fmc_bank1_erase(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* start FMC bank1 erase */ /* start FMC bank1 erase */
FMC_CTL1 |= FMC_CTL1_MER; FMC_CTL1 |= FMC_CTL1_MER;
FMC_CTL1 |= FMC_CTL1_START; FMC_CTL1 |= FMC_CTL1_START;
@ -321,11 +321,11 @@ fmc_state_enum fmc_bank1_erase(void)
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
{ {
fmc_state_enum fmc_state = FMC_READY; fmc_state_enum fmc_state = FMC_READY;
if(FMC_BANK0_SIZE < FMC_SIZE){ if (FMC_BANK0_SIZE < FMC_SIZE) {
if(FMC_BANK0_END_ADDRESS > address){ if (FMC_BANK0_END_ADDRESS > address) {
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG; FMC_CTL0 |= FMC_CTL0_PG;
REG32(address) = data; REG32(address) = data;
@ -334,10 +334,10 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
/* reset the PG bit */ /* reset the PG bit */
FMC_CTL0 &= ~FMC_CTL0_PG; FMC_CTL0 &= ~FMC_CTL0_PG;
} }
}else{ } else {
fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL1 |= FMC_CTL1_PG; FMC_CTL1 |= FMC_CTL1_PG;
REG32(address) = data; REG32(address) = data;
@ -347,10 +347,10 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
FMC_CTL1 &= ~FMC_CTL1_PG; FMC_CTL1 &= ~FMC_CTL1_PG;
} }
} }
}else{ } else {
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG; FMC_CTL0 |= FMC_CTL0_PG;
REG32(address) = data; REG32(address) = data;
@ -374,11 +374,11 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
{ {
fmc_state_enum fmc_state = FMC_READY; fmc_state_enum fmc_state = FMC_READY;
if(FMC_BANK0_SIZE < FMC_SIZE){ if (FMC_BANK0_SIZE < FMC_SIZE) {
if(FMC_BANK0_END_ADDRESS > address){ if (FMC_BANK0_END_ADDRESS > address) {
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG; FMC_CTL0 |= FMC_CTL0_PG;
REG16(address) = data; REG16(address) = data;
@ -387,10 +387,10 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
/* reset the PG bit */ /* reset the PG bit */
FMC_CTL0 &= ~FMC_CTL0_PG; FMC_CTL0 &= ~FMC_CTL0_PG;
} }
}else{ } else {
fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL1 |= FMC_CTL1_PG; FMC_CTL1 |= FMC_CTL1_PG;
REG16(address) = data; REG16(address) = data;
@ -400,10 +400,10 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
FMC_CTL1 &= ~FMC_CTL1_PG; FMC_CTL1 &= ~FMC_CTL1_PG;
} }
} }
}else{ } else {
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG; FMC_CTL0 |= FMC_CTL0_PG;
REG16(address) = data; REG16(address) = data;
@ -425,7 +425,7 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
*/ */
void ob_unlock(void) void ob_unlock(void)
{ {
if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ if (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) {
/* write the FMC key */ /* write the FMC key */
FMC_OBKEY = UNLOCK_KEY0; FMC_OBKEY = UNLOCK_KEY0;
FMC_OBKEY = UNLOCK_KEY1; FMC_OBKEY = UNLOCK_KEY1;
@ -458,11 +458,11 @@ fmc_state_enum ob_erase(void)
fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
/* check the option byte security protection value */ /* check the option byte security protection value */
if(RESET != ob_spc_get()){ if (RESET != ob_spc_get()) {
temp_spc = FMC_USPC; temp_spc = FMC_USPC;
} }
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* start erase the option byte */ /* start erase the option byte */
FMC_CTL0 |= FMC_CTL0_OBER; FMC_CTL0 |= FMC_CTL0_OBER;
@ -471,7 +471,7 @@ fmc_state_enum ob_erase(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* reset the OBER bit */ /* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER; FMC_CTL0 &= ~FMC_CTL0_OBER;
/* set the OBPG bit */ /* set the OBPG bit */
@ -480,12 +480,12 @@ fmc_state_enum ob_erase(void)
OB_SPC = (uint16_t)temp_spc; OB_SPC = (uint16_t)temp_spc;
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_TOERR != fmc_state){ if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */ /* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG; FMC_CTL0 &= ~FMC_CTL0_OBPG;
} }
}else{ } else {
if(FMC_TOERR != fmc_state){ if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */ /* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG; FMC_CTL0 &= ~FMC_CTL0_OBPG;
} }
@ -515,36 +515,36 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U);
temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the OBPG bit*/ /* set the OBPG bit*/
FMC_CTL0 |= FMC_CTL0_OBPG; FMC_CTL0 |= FMC_CTL0_OBPG;
if(0xFFU != temp_wp0){ if (0xFFU != temp_wp0) {
OB_WP0 = temp_wp0; OB_WP0 = temp_wp0;
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
} }
if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ if ((FMC_READY == fmc_state) && (0xFFU != temp_wp1)) {
OB_WP1 = temp_wp1; OB_WP1 = temp_wp1;
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
} }
if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ if ((FMC_READY == fmc_state) && (0xFFU != temp_wp2)) {
OB_WP2 = temp_wp2; OB_WP2 = temp_wp2;
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
} }
if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ if ((FMC_READY == fmc_state) && (0xFFU != temp_wp3)) {
OB_WP3 = temp_wp3; OB_WP3 = temp_wp3;
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
} }
if(FMC_TOERR != fmc_state){ if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */ /* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG; FMC_CTL0 &= ~FMC_CTL0_OBPG;
} }
@ -565,14 +565,14 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
{ {
fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
FMC_CTL0 |= FMC_CTL0_OBER; FMC_CTL0 |= FMC_CTL0_OBER;
FMC_CTL0 |= FMC_CTL0_START; FMC_CTL0 |= FMC_CTL0_START;
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* reset the OBER bit */ /* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER; FMC_CTL0 &= ~FMC_CTL0_OBER;
@ -584,12 +584,12 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_TOERR != fmc_state){ if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */ /* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG; FMC_CTL0 &= ~FMC_CTL0_OBPG;
} }
}else{ } else {
if(FMC_TOERR != fmc_state){ if (FMC_TOERR != fmc_state) {
/* reset the OBER bit */ /* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER; FMC_CTL0 &= ~FMC_CTL0_OBER;
} }
@ -624,7 +624,7 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the OBPG bit*/ /* set the OBPG bit*/
FMC_CTL0 |= FMC_CTL0_OBPG; FMC_CTL0 |= FMC_CTL0_OBPG;
@ -634,7 +634,7 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_TOERR != fmc_state){ if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */ /* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG; FMC_CTL0 &= ~FMC_CTL0_OBPG;
} }
@ -654,7 +654,7 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
{ {
fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){ if (FMC_READY == fmc_state) {
/* set the OBPG bit */ /* set the OBPG bit */
FMC_CTL0 |= FMC_CTL0_OBPG; FMC_CTL0 |= FMC_CTL0_OBPG;
REG16(address) = data; REG16(address) = data;
@ -662,7 +662,7 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_TOERR != fmc_state){ if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */ /* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG; FMC_CTL0 &= ~FMC_CTL0_OBPG;
} }
@ -716,9 +716,9 @@ FlagStatus ob_spc_get(void)
{ {
FlagStatus spc_state = RESET; FlagStatus spc_state = RESET;
if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ if (RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)) {
spc_state = SET; spc_state = SET;
}else{ } else {
spc_state = RESET; spc_state = RESET;
} }
return spc_state; return spc_state;
@ -772,9 +772,9 @@ void fmc_interrupt_disable(uint32_t interrupt)
*/ */
FlagStatus fmc_flag_get(uint32_t flag) FlagStatus fmc_flag_get(uint32_t flag)
{ {
if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ if (RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -815,21 +815,21 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
FlagStatus ret1 = RESET; FlagStatus ret1 = RESET;
FlagStatus ret2 = RESET; FlagStatus ret2 = RESET;
if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ if (FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)) {
/* get the staus of interrupt flag */ /* get the staus of interrupt flag */
ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
/* get the staus of interrupt enale bit */ /* get the staus of interrupt enale bit */
ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
}else{ } else {
/* get the staus of interrupt flag */ /* get the staus of interrupt flag */
ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
/* get the staus of interrupt enale bit */ /* get the staus of interrupt enale bit */
ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag)));
} }
if(ret1 && ret2){ if (ret1 && ret2) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -862,13 +862,13 @@ fmc_state_enum fmc_bank0_state_get(void)
{ {
fmc_state_enum fmc_state = FMC_READY; fmc_state_enum fmc_state = FMC_READY;
if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ if ((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)) {
fmc_state = FMC_BUSY; fmc_state = FMC_BUSY;
}else{ } else {
if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ if ((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)) {
fmc_state = FMC_WPERR; fmc_state = FMC_WPERR;
}else{ } else {
if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ if ((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))) {
fmc_state = FMC_PGERR; fmc_state = FMC_PGERR;
} }
} }
@ -887,13 +887,13 @@ fmc_state_enum fmc_bank1_state_get(void)
{ {
fmc_state_enum fmc_state = FMC_READY; fmc_state_enum fmc_state = FMC_READY;
if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ if ((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)) {
fmc_state = FMC_BUSY; fmc_state = FMC_BUSY;
}else{ } else {
if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ if ((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)) {
fmc_state = FMC_WPERR; fmc_state = FMC_WPERR;
}else{ } else {
if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ if ((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)) {
fmc_state = FMC_PGERR; fmc_state = FMC_PGERR;
} }
} }
@ -914,13 +914,13 @@ fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
fmc_state_enum fmc_state = FMC_BUSY; fmc_state_enum fmc_state = FMC_BUSY;
/* wait for FMC ready */ /* wait for FMC ready */
do{ do {
/* get FMC state */ /* get FMC state */
fmc_state = fmc_bank0_state_get(); fmc_state = fmc_bank0_state_get();
timeout--; timeout--;
}while((FMC_BUSY == fmc_state) && (0x00U != timeout)); } while ((FMC_BUSY == fmc_state) && (0x00U != timeout));
if(FMC_BUSY == fmc_state){ if (FMC_BUSY == fmc_state) {
fmc_state = FMC_TOERR; fmc_state = FMC_TOERR;
} }
/* return the FMC state */ /* return the FMC state */
@ -938,13 +938,13 @@ fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
fmc_state_enum fmc_state = FMC_BUSY; fmc_state_enum fmc_state = FMC_BUSY;
/* wait for FMC ready */ /* wait for FMC ready */
do{ do {
/* get FMC state */ /* get FMC state */
fmc_state = fmc_bank1_state_get(); fmc_state = fmc_bank1_state_get();
timeout--; timeout--;
}while((FMC_BUSY == fmc_state) && (0x00U != timeout)); } while ((FMC_BUSY == fmc_state) && (0x00U != timeout));
if(FMC_BUSY == fmc_state){ if (FMC_BUSY == fmc_state) {
fmc_state = FMC_TOERR; fmc_state = FMC_TOERR;
} }
/* return the FMC state */ /* return the FMC state */

20
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c
View File

@ -98,11 +98,11 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
/* wait until the PUD flag to be reset */ /* wait until the PUD flag to be reset */
do{ do {
flag_status = FWDGT_STAT & FWDGT_STAT_PUD; flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){ if ((uint32_t)RESET != flag_status) {
return ERROR; return ERROR;
} }
@ -111,11 +111,11 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
timeout = FWDGT_RLD_TIMEOUT; timeout = FWDGT_RLD_TIMEOUT;
/* wait until the RUD flag to be reset */ /* wait until the RUD flag to be reset */
do{ do {
flag_status = FWDGT_STAT & FWDGT_STAT_RUD; flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){ if ((uint32_t)RESET != flag_status) {
return ERROR; return ERROR;
} }
@ -137,9 +137,9 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
*/ */
FlagStatus fwdgt_flag_get(uint16_t flag) FlagStatus fwdgt_flag_get(uint16_t flag)
{ {
if(FWDGT_STAT & flag){ if (FWDGT_STAT & flag) {
return SET; return SET;
} }
return RESET; return RESET;
} }

162
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c
View File

@ -52,44 +52,44 @@ OF SUCH DAMAGE.
*/ */
void gpio_deinit(uint32_t gpio_periph) void gpio_deinit(uint32_t gpio_periph)
{ {
switch(gpio_periph){ switch (gpio_periph) {
case GPIOA: case GPIOA:
/* reset GPIOA */ /* reset GPIOA */
rcu_periph_reset_enable(RCU_GPIOARST); rcu_periph_reset_enable(RCU_GPIOARST);
rcu_periph_reset_disable(RCU_GPIOARST); rcu_periph_reset_disable(RCU_GPIOARST);
break; break;
case GPIOB: case GPIOB:
/* reset GPIOB */ /* reset GPIOB */
rcu_periph_reset_enable(RCU_GPIOBRST); rcu_periph_reset_enable(RCU_GPIOBRST);
rcu_periph_reset_disable(RCU_GPIOBRST); rcu_periph_reset_disable(RCU_GPIOBRST);
break; break;
case GPIOC: case GPIOC:
/* reset GPIOC */ /* reset GPIOC */
rcu_periph_reset_enable(RCU_GPIOCRST); rcu_periph_reset_enable(RCU_GPIOCRST);
rcu_periph_reset_disable(RCU_GPIOCRST); rcu_periph_reset_disable(RCU_GPIOCRST);
break; break;
case GPIOD: case GPIOD:
/* reset GPIOD */ /* reset GPIOD */
rcu_periph_reset_enable(RCU_GPIODRST); rcu_periph_reset_enable(RCU_GPIODRST);
rcu_periph_reset_disable(RCU_GPIODRST); rcu_periph_reset_disable(RCU_GPIODRST);
break; break;
case GPIOE: case GPIOE:
/* reset GPIOE */ /* reset GPIOE */
rcu_periph_reset_enable(RCU_GPIOERST); rcu_periph_reset_enable(RCU_GPIOERST);
rcu_periph_reset_disable(RCU_GPIOERST); rcu_periph_reset_disable(RCU_GPIOERST);
break; break;
case GPIOF: case GPIOF:
/* reset GPIOF */ /* reset GPIOF */
rcu_periph_reset_enable(RCU_GPIOFRST); rcu_periph_reset_enable(RCU_GPIOFRST);
rcu_periph_reset_disable(RCU_GPIOFRST); rcu_periph_reset_disable(RCU_GPIOFRST);
break; break;
case GPIOG: case GPIOG:
/* reset GPIOG */ /* reset GPIOG */
rcu_periph_reset_enable(RCU_GPIOGRST); rcu_periph_reset_enable(RCU_GPIOGRST);
rcu_periph_reset_disable(RCU_GPIOGRST); rcu_periph_reset_disable(RCU_GPIOGRST);
break; break;
default: default:
break; break;
} }
} }
@ -141,21 +141,21 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin
temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU));
/* GPIO speed configuration */ /* GPIO speed configuration */
if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ if (((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))) {
/* output mode max speed */ /* output mode max speed */
if(GPIO_OSPEED_MAX == (uint32_t)speed){ if (GPIO_OSPEED_MAX == (uint32_t)speed) {
temp_mode |= (uint32_t)0x03U; temp_mode |= (uint32_t)0x03U;
/* set the corresponding SPD bit */ /* set the corresponding SPD bit */
GPIOx_SPD(gpio_periph) |= (uint32_t)pin ; GPIOx_SPD(gpio_periph) |= (uint32_t)pin ;
}else{ } else {
/* output mode max speed:10MHz,2MHz,50MHz */ /* output mode max speed:10MHz,2MHz,50MHz */
temp_mode |= (uint32_t)speed; temp_mode |= (uint32_t)speed;
} }
} }
/* configure the eight low port pins with GPIO_CTL0 */ /* configure the eight low port pins with GPIO_CTL0 */
for(i = 0U;i < 8U;i++){ for (i = 0U; i < 8U; i++) {
if((1U << i) & pin){ if ((1U << i) & pin) {
reg = GPIO_CTL0(gpio_periph); reg = GPIO_CTL0(gpio_periph);
/* clear the specified pin mode bits */ /* clear the specified pin mode bits */
@ -164,12 +164,12 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin
reg |= GPIO_MODE_SET(i, temp_mode); reg |= GPIO_MODE_SET(i, temp_mode);
/* set IPD or IPU */ /* set IPD or IPU */
if(GPIO_MODE_IPD == mode){ if (GPIO_MODE_IPD == mode) {
/* reset the corresponding OCTL bit */ /* reset the corresponding OCTL bit */
GPIO_BC(gpio_periph) = (uint32_t)pin; GPIO_BC(gpio_periph) = (uint32_t)pin;
}else{ } else {
/* set the corresponding OCTL bit */ /* set the corresponding OCTL bit */
if(GPIO_MODE_IPU == mode){ if (GPIO_MODE_IPU == mode) {
GPIO_BOP(gpio_periph) = (uint32_t)pin; GPIO_BOP(gpio_periph) = (uint32_t)pin;
} }
} }
@ -178,8 +178,8 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin
} }
} }
/* configure the eight high port pins with GPIO_CTL1 */ /* configure the eight high port pins with GPIO_CTL1 */
for(i = 8U;i < 16U;i++){ for (i = 8U; i < 16U; i++) {
if((1U << i) & pin){ if ((1U << i) & pin) {
reg = GPIO_CTL1(gpio_periph); reg = GPIO_CTL1(gpio_periph);
/* clear the specified pin mode bits */ /* clear the specified pin mode bits */
@ -188,12 +188,12 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin
reg |= GPIO_MODE_SET(i - 8U, temp_mode); reg |= GPIO_MODE_SET(i - 8U, temp_mode);
/* set IPD or IPU */ /* set IPD or IPU */
if(GPIO_MODE_IPD == mode){ if (GPIO_MODE_IPD == mode) {
/* reset the corresponding OCTL bit */ /* reset the corresponding OCTL bit */
GPIO_BC(gpio_periph) = (uint32_t)pin; GPIO_BC(gpio_periph) = (uint32_t)pin;
}else{ } else {
/* set the corresponding OCTL bit */ /* set the corresponding OCTL bit */
if(GPIO_MODE_IPU == mode){ if (GPIO_MODE_IPU == mode) {
GPIO_BOP(gpio_periph) = (uint32_t)pin; GPIO_BOP(gpio_periph) = (uint32_t)pin;
} }
} }
@ -210,7 +210,7 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin
\param[out] none \param[out] none
\retval none \retval none
*/ */
void gpio_bit_set(uint32_t gpio_periph,uint32_t pin) void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
{ {
GPIO_BOP(gpio_periph) = (uint32_t)pin; GPIO_BOP(gpio_periph) = (uint32_t)pin;
} }
@ -222,7 +222,7 @@ void gpio_bit_set(uint32_t gpio_periph,uint32_t pin)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
{ {
GPIO_BC(gpio_periph) = (uint32_t)pin; GPIO_BC(gpio_periph) = (uint32_t)pin;
} }
@ -237,11 +237,11 @@ void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
{ {
if(RESET != bit_value){ if (RESET != bit_value) {
GPIO_BOP(gpio_periph) = (uint32_t)pin; GPIO_BOP(gpio_periph) = (uint32_t)pin;
}else{ } else {
GPIO_BC(gpio_periph) = (uint32_t)pin; GPIO_BC(gpio_periph) = (uint32_t)pin;
} }
} }
@ -253,7 +253,7 @@ void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void gpio_port_write(uint32_t gpio_periph,uint16_t data) void gpio_port_write(uint32_t gpio_periph, uint16_t data)
{ {
GPIO_OCTL(gpio_periph) = (uint32_t)data; GPIO_OCTL(gpio_periph) = (uint32_t)data;
} }
@ -265,11 +265,11 @@ void gpio_port_write(uint32_t gpio_periph,uint16_t data)
\param[out] none \param[out] none
\retval input status of gpio pin: SET or RESET \retval input status of gpio pin: SET or RESET
*/ */
FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
{ {
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ if ((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -292,11 +292,11 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph)
\param[out] none \param[out] none
\retval output status of gpio pin: SET or RESET \retval output status of gpio pin: SET or RESET
*/ */
FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
{ {
if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ if ((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -319,7 +319,7 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
{ {
uint32_t lock = 0x00010000U; uint32_t lock = 0x00010000U;
lock |= pin; lock |= pin;
@ -350,7 +350,7 @@ void gpio_event_output_config(uint8_t output_port, uint8_t output_pin)
reg = AFIO_EC; reg = AFIO_EC;
/* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); reg &= (uint32_t)(~(AFIO_EC_PORT | AFIO_EC_PIN));
reg |= (uint32_t)((uint32_t)output_port << 0x04U); reg |= (uint32_t)((uint32_t)output_port << 0x04U);
reg |= (uint32_t)output_pin; reg |= (uint32_t)output_pin;
@ -400,19 +400,19 @@ void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin)
source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)); source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U));
/* select EXTI sources */ /* select EXTI sources */
if(GPIO_PIN_SOURCE_4 > output_pin){ if (GPIO_PIN_SOURCE_4 > output_pin) {
/* select EXTI0/EXTI1/EXTI2/EXTI3 */ /* select EXTI0/EXTI1/EXTI2/EXTI3 */
AFIO_EXTISS0 &= ~source; AFIO_EXTISS0 &= ~source;
AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)));
}else if(GPIO_PIN_SOURCE_8 > output_pin){ } else if (GPIO_PIN_SOURCE_8 > output_pin) {
/* select EXTI4/EXTI5/EXTI6/EXTI7 */ /* select EXTI4/EXTI5/EXTI6/EXTI7 */
AFIO_EXTISS1 &= ~source; AFIO_EXTISS1 &= ~source;
AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)));
}else if(GPIO_PIN_SOURCE_12 > output_pin){ } else if (GPIO_PIN_SOURCE_12 > output_pin) {
/* select EXTI8/EXTI9/EXTI10/EXTI11 */ /* select EXTI8/EXTI9/EXTI10/EXTI11 */
AFIO_EXTISS2 &= ~source; AFIO_EXTISS2 &= ~source;
AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)));
}else{ } else {
/* select EXTI12/EXTI13/EXTI14/EXTI15 */ /* select EXTI12/EXTI13/EXTI14/EXTI15 */
AFIO_EXTISS3 &= ~source; AFIO_EXTISS3 &= ~source;
AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)));
@ -489,10 +489,10 @@ void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue)
{ {
uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
if(((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)){ if (((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)) {
/* get AFIO_PCF1 regiter value */ /* get AFIO_PCF1 regiter value */
temp_reg = AFIO_PCF1; temp_reg = AFIO_PCF1;
}else{ } else {
/* get AFIO_PCF0 regiter value */ /* get AFIO_PCF0 regiter value */
temp_reg = AFIO_PCF0; temp_reg = AFIO_PCF0;
} }
@ -501,27 +501,27 @@ void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue)
remap1 = gpio_remap & LSB_16BIT_MASK; remap1 = gpio_remap & LSB_16BIT_MASK;
/* judge pin remap type */ /* judge pin remap type */
if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) {
temp_reg &= PCF_SWJCFG_MASK; temp_reg &= PCF_SWJCFG_MASK;
AFIO_PCF0 &= PCF_SWJCFG_MASK; AFIO_PCF0 &= PCF_SWJCFG_MASK;
}else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){ } else if (PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)) {
remap2 = ((uint32_t)0x03U) << temp_mask; remap2 = ((uint32_t)0x03U) << temp_mask;
temp_reg &= ~remap2; temp_reg &= ~remap2;
temp_reg |= ~PCF_SWJCFG_MASK; temp_reg |= ~PCF_SWJCFG_MASK;
}else{ } else {
temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U)); temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U) * 0x10U));
temp_reg |= ~PCF_SWJCFG_MASK; temp_reg |= ~PCF_SWJCFG_MASK;
} }
/* set pin remap value */ /* set pin remap value */
if(DISABLE != newvalue){ if (DISABLE != newvalue) {
temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U)); temp_reg |= (remap1 << ((gpio_remap >> 0x15U) * 0x10U));
} }
if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){ if (AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)) {
/* set AFIO_PCF1 regiter value */ /* set AFIO_PCF1 regiter value */
AFIO_PCF1 = temp_reg; AFIO_PCF1 = temp_reg;
}else{ } else {
/* set AFIO_PCF0 regiter value */ /* set AFIO_PCF0 regiter value */
AFIO_PCF0 = temp_reg; AFIO_PCF0 = temp_reg;
} }
@ -553,9 +553,9 @@ void gpio_compensation_config(uint32_t compensation)
*/ */
FlagStatus gpio_compensation_flag_get(void) FlagStatus gpio_compensation_flag_get(void)
{ {
if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){ if (((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }

140
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c
View File

@ -47,19 +47,19 @@ OF SUCH DAMAGE.
*/ */
void i2c_deinit(uint32_t i2c_periph) void i2c_deinit(uint32_t i2c_periph)
{ {
switch(i2c_periph){ switch (i2c_periph) {
case I2C0: case I2C0:
/* reset I2C0 */ /* reset I2C0 */
rcu_periph_reset_enable(RCU_I2C0RST); rcu_periph_reset_enable(RCU_I2C0RST);
rcu_periph_reset_disable(RCU_I2C0RST); rcu_periph_reset_disable(RCU_I2C0RST);
break; break;
case I2C1: case I2C1:
/* reset I2C1 */ /* reset I2C1 */
rcu_periph_reset_enable(RCU_I2C1RST); rcu_periph_reset_enable(RCU_I2C1RST);
rcu_periph_reset_disable(RCU_I2C1RST); rcu_periph_reset_disable(RCU_I2C1RST);
break; break;
default: default:
break; break;
} }
} }
@ -76,13 +76,13 @@ void i2c_deinit(uint32_t i2c_periph)
*/ */
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
{ {
uint32_t pclk1,clkc,freq,risetime; uint32_t pclk1, clkc, freq, risetime;
uint32_t temp; uint32_t temp;
pclk1 = rcu_clock_freq_get(CK_APB1); pclk1 = rcu_clock_freq_get(CK_APB1);
/* I2C peripheral clock frequency */ /* I2C peripheral clock frequency */
freq = (uint32_t)(pclk1/1000000U); freq = (uint32_t)(pclk1 / 1000000U);
if(freq >= I2CCLK_MAX){ if (freq >= I2CCLK_MAX) {
freq = I2CCLK_MAX; freq = I2CCLK_MAX;
} }
temp = I2C_CTL1(i2c_periph); temp = I2C_CTL1(i2c_periph);
@ -91,49 +91,49 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
I2C_CTL1(i2c_periph) = temp; I2C_CTL1(i2c_periph) = temp;
if(100000U >= clkspeed){ if (100000U >= clkspeed) {
/* the maximum SCL rise time is 1000ns in standard mode */ /* the maximum SCL rise time is 1000ns in standard mode */
risetime = (uint32_t)((pclk1/1000000U)+1U); risetime = (uint32_t)((pclk1 / 1000000U) + 1U);
if(risetime >= I2CCLK_MAX){ if (risetime >= I2CCLK_MAX) {
I2C_RT(i2c_periph) = I2CCLK_MAX; I2C_RT(i2c_periph) = I2CCLK_MAX;
}else{ } else {
I2C_RT(i2c_periph) = risetime; I2C_RT(i2c_periph) = risetime;
} }
clkc = (uint32_t)(pclk1/(clkspeed*2U)); clkc = (uint32_t)(pclk1 / (clkspeed * 2U));
if(clkc < 0x04U){ if (clkc < 0x04U) {
/* the CLKC in standard mode minmum value is 4 */ /* the CLKC in standard mode minmum value is 4 */
clkc = 0x04U; clkc = 0x04U;
} }
I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
}else if(400000U >= clkspeed){ } else if (400000U >= clkspeed) {
/* the maximum SCL rise time is 300ns in fast mode */ /* the maximum SCL rise time is 300ns in fast mode */
I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U);
if(I2C_DTCY_2 == dutycyc){ if (I2C_DTCY_2 == dutycyc) {
/* I2C duty cycle is 2 */ /* I2C duty cycle is 2 */
clkc = (uint32_t)(pclk1/(clkspeed*3U)); clkc = (uint32_t)(pclk1 / (clkspeed * 3U));
I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
}else{ } else {
/* I2C duty cycle is 16/9 */ /* I2C duty cycle is 16/9 */
clkc = (uint32_t)(pclk1/(clkspeed*25U)); clkc = (uint32_t)(pclk1 / (clkspeed * 25U));
I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
} }
if(0U == (clkc & I2C_CKCFG_CLKC)){ if (0U == (clkc & I2C_CKCFG_CLKC)) {
/* the CLKC in fast mode minmum value is 1 */ /* the CLKC in fast mode minmum value is 1 */
clkc |= 0x0001U; clkc |= 0x0001U;
} }
I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
I2C_CKCFG(i2c_periph) |= clkc; I2C_CKCFG(i2c_periph) |= clkc;
}else{ } else {
/* fast mode plus, the maximum SCL rise time is 120ns */ /* fast mode plus, the maximum SCL rise time is 120ns */
I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U); I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)120U) / (uint32_t)1000U) + (uint32_t)1U);
if(I2C_DTCY_2 == dutycyc){ if (I2C_DTCY_2 == dutycyc) {
/* I2C duty cycle is 2 */ /* I2C duty cycle is 2 */
clkc = (uint32_t)(pclk1/(clkspeed*3U)); clkc = (uint32_t)(pclk1 / (clkspeed * 3U));
I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
}else{ } else {
/* I2C duty cycle is 16/9 */ /* I2C duty cycle is 16/9 */
clkc = (uint32_t)(pclk1/(clkspeed*25U)); clkc = (uint32_t)(pclk1 / (clkspeed * 25U));
I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
} }
/* enable fast mode */ /* enable fast mode */
@ -180,9 +180,9 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat
*/ */
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
{ {
if(I2C_SMBUS_HOST == type){ if (I2C_SMBUS_HOST == type) {
I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
}else{ } else {
I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
} }
} }
@ -198,9 +198,9 @@ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
*/ */
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
{ {
if(I2C_ACK_ENABLE == ack){ if (I2C_ACK_ENABLE == ack) {
I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
}else{ } else {
I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
} }
} }
@ -217,9 +217,9 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
{ {
/* configure I2C POAP position */ /* configure I2C POAP position */
if(I2C_ACKPOS_NEXT == pos){ if (I2C_ACKPOS_NEXT == pos) {
I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
}else{ } else {
I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
} }
} }
@ -236,9 +236,9 @@ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
*/ */
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
{ {
if(I2C_TRANSMITTER == trandirection){ if (I2C_TRANSMITTER == trandirection) {
addr = addr & I2C_TRANSMITTER; addr = addr & I2C_TRANSMITTER;
}else{ } else {
addr = addr | I2C_RECEIVER; addr = addr | I2C_RECEIVER;
} }
I2C_DATA(i2c_periph) = addr; I2C_DATA(i2c_periph) = addr;
@ -255,9 +255,9 @@ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandire
*/ */
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
{ {
if(I2C_DUADEN_ENABLE == dualaddr){ if (I2C_DUADEN_ENABLE == dualaddr) {
I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
}else{ } else {
I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
} }
} }
@ -458,16 +458,16 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
FlagStatus reval = RESET; FlagStatus reval = RESET;
/* get the flag in which register */ /* get the flag in which register */
reg = (BIT(31) & flag); reg = (BIT(31) & flag);
if((BIT(31) == reg)){ if ((BIT(31) == reg)) {
if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){ if ((I2C_STAT1(i2c_periph) & (flag & I2C_FLAG_MASK))) {
reval = SET; reval = SET;
}else{ } else {
reval = RESET; reval = RESET;
} }
}else{ } else {
if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){ if ((I2C_STAT0(i2c_periph) & (flag & I2C_FLAG_MASK))) {
reval = SET; reval = SET;
}else{ } else {
reval = RESET; reval = RESET;
} }
} }
@ -492,11 +492,11 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
*/ */
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag) void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
{ {
if(I2C_FLAG_ADDSEND == flag){ if (I2C_FLAG_ADDSEND == flag) {
/* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
I2C_STAT0(i2c_periph); I2C_STAT0(i2c_periph);
I2C_STAT1(i2c_periph); I2C_STAT1(i2c_periph);
}else{ } else {
I2C_STAT0(i2c_periph) &= ~(flag); I2C_STAT0(i2c_periph) &= ~(flag);
} }
} }
@ -559,36 +559,36 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE; evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE; errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
/* check I2C event interrupt enable bit */ /* check I2C event interrupt enable bit */
if((intflag&0x00ffU) && evie){ if ((intflag & 0x00ffU) && evie) {
if(intflag&0x001fU){ if (intflag & 0x001fU) {
/* check I2C event flags except TBE and RBNE */ /* check I2C event flags except TBE and RBNE */
if(intflag & I2C_STAT0(i2c_periph)){ if (intflag & I2C_STAT0(i2c_periph)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
}else{ } else {
/* check I2C event flags TBE and RBNE */ /* check I2C event flags TBE and RBNE */
bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
if(bufie){ if (bufie) {
if(intflag & I2C_STAT0(i2c_periph)){ if (intflag & I2C_STAT0(i2c_periph)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
}else{ } else {
return RESET; return RESET;
} }
} }
/* check I2C error interrupt enable bit */ /* check I2C error interrupt enable bit */
}else if((intflag&0xff00U) && errie){ } else if ((intflag & 0xff00U) && errie) {
/* check I2C error flags */ /* check I2C error flags */
if(intflag & I2C_STAT0(i2c_periph)){ if (intflag & I2C_STAT0(i2c_periph)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
}else{ } else {
return RESET; return RESET;
} }
} }
@ -610,11 +610,11 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
*/ */
void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag) void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
{ {
if(I2C_INT_FLAG_ADDSEND == intflag){ if (I2C_INT_FLAG_ADDSEND == intflag) {
/* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
I2C_STAT0(i2c_periph); I2C_STAT0(i2c_periph);
I2C_STAT1(i2c_periph); I2C_STAT1(i2c_periph);
}else{ } else {
I2C_STAT0(i2c_periph) &= ~(intflag); I2C_STAT0(i2c_periph) &= ~(intflag);
} }
} }
@ -665,7 +665,7 @@ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
*/ */
uint8_t i2c_pec_value_get(uint32_t i2c_periph) uint8_t i2c_pec_value_get(uint32_t i2c_periph)
{ {
return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8); return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV) >> 8);
} }
/*! /*!

38
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c
View File

@ -66,26 +66,26 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
{ {
uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
/* use the priority group value to get the temp_pre and the temp_sub */ /* use the priority group value to get the temp_pre and the temp_sub */
if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) {
temp_pre=0U; temp_pre = 0U;
temp_sub=0x4U; temp_sub = 0x4U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) {
temp_pre=1U; temp_pre = 1U;
temp_sub=0x3U; temp_sub = 0x3U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) {
temp_pre=2U; temp_pre = 2U;
temp_sub=0x2U; temp_sub = 0x2U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) {
temp_pre=3U; temp_pre = 3U;
temp_sub=0x1U; temp_sub = 0x1U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) {
temp_pre=4U; temp_pre = 4U;
temp_sub=0x0U; temp_sub = 0x0U;
}else{ } else {
} }
/* get the temp_priority to fill the NVIC->IP register */ /* get the temp_priority to fill the NVIC->IP register */
temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub));
temp_priority = temp_priority << 0x04U; temp_priority = temp_priority << 0x04U;
NVIC->IP[nvic_irq] = (uint8_t)temp_priority; NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
/* enable the selected IRQ */ /* enable the selected IRQ */
@ -161,10 +161,10 @@ void system_lowpower_reset(uint8_t lowpower_mode)
void systick_clksource_set(uint32_t systick_clksource) void systick_clksource_set(uint32_t systick_clksource)
{ {
if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ if (SYSTICK_CLKSOURCE_HCLK == systick_clksource) {
/* set the systick clock source from HCLK */ /* set the systick clock source from HCLK */
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}else{ } else {
/* set the systick clock source from HCLK/8 */ /* set the systick clock source from HCLK/8 */
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
} }

42
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c
View File

@ -103,7 +103,7 @@ void pmu_ldo_output_select(uint32_t ldo_output)
void pmu_highdriver_switch_select(uint32_t highdr_switch) void pmu_highdriver_switch_select(uint32_t highdr_switch)
{ {
/* wait for HDRF flag set */ /* wait for HDRF flag set */
while(SET != pmu_flag_get(PMU_FLAG_HDRF)){ while (SET != pmu_flag_get(PMU_FLAG_HDRF)) {
} }
PMU_CTL &= ~PMU_CTL_HDS; PMU_CTL &= ~PMU_CTL_HDS;
PMU_CTL |= highdr_switch; PMU_CTL |= highdr_switch;
@ -208,9 +208,9 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd)
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
/* select WFI or WFE command to enter sleep mode */ /* select WFI or WFE command to enter sleep mode */
if(WFI_CMD == sleepmodecmd){ if (WFI_CMD == sleepmodecmd) {
__WFI(); __WFI();
}else{ } else {
__WFE(); __WFE();
} }
} }
@ -226,7 +226,7 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
{ {
/* clear stbmod and ldolp bits */ /* clear stbmod and ldolp bits */
PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
@ -238,9 +238,9 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* select WFI or WFE command to enter deepsleep mode */ /* select WFI or WFE command to enter deepsleep mode */
if(WFI_CMD == deepsleepmodecmd){ if (WFI_CMD == deepsleepmodecmd) {
__WFI(); __WFI();
}else{ } else {
__SEV(); __SEV();
__WFE(); __WFE();
__WFE(); __WFE();
@ -269,9 +269,9 @@ void pmu_to_standbymode(uint8_t standbymodecmd)
PMU_CTL |= PMU_CTL_WURST; PMU_CTL |= PMU_CTL_WURST;
/* select WFI or WFE command to enter standby mode */ /* select WFI or WFE command to enter standby mode */
if(WFI_CMD == standbymodecmd){ if (WFI_CMD == standbymodecmd) {
__WFI(); __WFI();
}else{ } else {
__WFE(); __WFE();
} }
} }
@ -286,17 +286,17 @@ void pmu_to_standbymode(uint8_t standbymodecmd)
*/ */
void pmu_flag_clear(uint32_t flag_reset) void pmu_flag_clear(uint32_t flag_reset)
{ {
switch(flag_reset){ switch (flag_reset) {
case PMU_FLAG_RESET_WAKEUP: case PMU_FLAG_RESET_WAKEUP:
/* reset wakeup flag */ /* reset wakeup flag */
PMU_CTL |= PMU_CTL_WURST; PMU_CTL |= PMU_CTL_WURST;
break; break;
case PMU_FLAG_RESET_STANDBY: case PMU_FLAG_RESET_STANDBY:
/* reset standby flag */ /* reset standby flag */
PMU_CTL |= PMU_CTL_STBRST; PMU_CTL |= PMU_CTL_STBRST;
break; break;
default : default :
break; break;
} }
} }
@ -315,9 +315,9 @@ void pmu_flag_clear(uint32_t flag_reset)
*/ */
FlagStatus pmu_flag_get(uint32_t flag) FlagStatus pmu_flag_get(uint32_t flag)
{ {
if(PMU_CS & flag){ if (PMU_CS & flag) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }

458
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c
View File

@ -451,7 +451,7 @@ void rcu_predv0_config(uint32_t predv0_div)
reg = RCU_CFG0; reg = RCU_CFG0;
/* reset PREDV0 bit */ /* reset PREDV0 bit */
reg &= ~RCU_CFG0_PREDV0; reg &= ~RCU_CFG0_PREDV0;
if(RCU_PREDV0_DIV2 == predv0_div){ if (RCU_PREDV0_DIV2 == predv0_div) {
/* set the PREDV0 bit */ /* set the PREDV0 bit */
reg |= RCU_CFG0_PREDV0; reg |= RCU_CFG0_PREDV0;
} }
@ -547,7 +547,7 @@ void rcu_pll2_config(uint32_t pll_mul)
*/ */
void rcu_adc_clock_config(uint32_t adc_psc) void rcu_adc_clock_config(uint32_t adc_psc)
{ {
uint32_t reg0,reg1; uint32_t reg0, reg1;
/* reset the ADCPSC bits */ /* reset the ADCPSC bits */
reg0 = RCU_CFG0; reg0 = RCU_CFG0;
@ -556,7 +556,7 @@ void rcu_adc_clock_config(uint32_t adc_psc)
reg1 &= ~RCU_CFG1_ADCPSC_3; reg1 &= ~RCU_CFG1_ADCPSC_3;
/* set the ADC prescaler factor */ /* set the ADC prescaler factor */
switch(adc_psc){ switch (adc_psc) {
case RCU_CKADC_CKAPB2_DIV2: case RCU_CKADC_CKAPB2_DIV2:
case RCU_CKADC_CKAPB2_DIV4: case RCU_CKADC_CKAPB2_DIV4:
case RCU_CKADC_CKAPB2_DIV6: case RCU_CKADC_CKAPB2_DIV6:
@ -574,7 +574,7 @@ void rcu_adc_clock_config(uint32_t adc_psc)
case RCU_CKADC_CKAHB_DIV6: case RCU_CKADC_CKAHB_DIV6:
case RCU_CKADC_CKAHB_DIV10: case RCU_CKADC_CKAHB_DIV10:
case RCU_CKADC_CKAHB_DIV20: case RCU_CKADC_CKAHB_DIV20:
adc_psc &= ~BITS(2,3); adc_psc &= ~BITS(2, 3);
reg0 |= (adc_psc << 14); reg0 |= (adc_psc << 14);
reg1 |= RCU_CFG1_ADCPSC_3; reg1 |= RCU_CFG1_ADCPSC_3;
break; break;
@ -721,9 +721,9 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source)
FlagStatus rcu_flag_get(rcu_flag_enum flag) FlagStatus rcu_flag_get(rcu_flag_enum flag)
{ {
/* get the rcu flag */ /* get the rcu flag */
if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ if (RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -758,9 +758,9 @@ void rcu_all_reset_flag_clear(void)
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
{ {
/* get the rcu interrupt flag */ /* get the rcu interrupt flag */
if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ if (RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -869,114 +869,114 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
ErrStatus reval = ERROR; ErrStatus reval = ERROR;
FlagStatus osci_stat = RESET; FlagStatus osci_stat = RESET;
switch(osci){ switch (osci) {
/* wait HXTAL stable */ /* wait HXTAL stable */
case RCU_HXTAL: case RCU_HXTAL:
while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ if (RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait LXTAL stable */ /* wait LXTAL stable */
case RCU_LXTAL: case RCU_LXTAL:
while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ if (RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait IRC8M stable */ /* wait IRC8M stable */
case RCU_IRC8M: case RCU_IRC8M:
while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ if (RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait IRC48M stable */ /* wait IRC48M stable */
case RCU_IRC48M: case RCU_IRC48M:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait IRC40K stable */ /* wait IRC40K stable */
case RCU_IRC40K: case RCU_IRC40K:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ if (RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait PLL stable */ /* wait PLL stable */
case RCU_PLL_CK: case RCU_PLL_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ if (RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
/* wait PLL1 stable */ /* wait PLL1 stable */
case RCU_PLL1_CK: case RCU_PLL1_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ if (RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait PLL2 stable */ /* wait PLL2 stable */
case RCU_PLL2_CK: case RCU_PLL2_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set or not */ /* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ if (RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) {
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
default: default:
break; break;
} }
/* return value */ /* return value */
@ -1036,30 +1036,30 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
{ {
uint32_t reg; uint32_t reg;
switch(osci){ switch (osci) {
/* enable HXTAL to bypass mode */ /* enable HXTAL to bypass mode */
case RCU_HXTAL: case RCU_HXTAL:
reg = RCU_CTL; reg = RCU_CTL;
RCU_CTL &= ~RCU_CTL_HXTALEN; RCU_CTL &= ~RCU_CTL_HXTALEN;
RCU_CTL = (reg | RCU_CTL_HXTALBPS); RCU_CTL = (reg | RCU_CTL_HXTALBPS);
break; break;
/* enable LXTAL to bypass mode */ /* enable LXTAL to bypass mode */
case RCU_LXTAL: case RCU_LXTAL:
reg = RCU_BDCTL; reg = RCU_BDCTL;
RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
break; break;
case RCU_IRC8M: case RCU_IRC8M:
case RCU_IRC48M: case RCU_IRC48M:
case RCU_IRC40K: case RCU_IRC40K:
case RCU_PLL_CK: case RCU_PLL_CK:
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
case RCU_PLL1_CK: case RCU_PLL1_CK:
case RCU_PLL2_CK: case RCU_PLL2_CK:
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
break; break;
default: default:
break; break;
} }
} }
@ -1076,30 +1076,30 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
{ {
uint32_t reg; uint32_t reg;
switch(osci){ switch (osci) {
/* disable HXTAL to bypass mode */ /* disable HXTAL to bypass mode */
case RCU_HXTAL: case RCU_HXTAL:
reg = RCU_CTL; reg = RCU_CTL;
RCU_CTL &= ~RCU_CTL_HXTALEN; RCU_CTL &= ~RCU_CTL_HXTALEN;
RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
break; break;
/* disable LXTAL to bypass mode */ /* disable LXTAL to bypass mode */
case RCU_LXTAL: case RCU_LXTAL:
reg = RCU_BDCTL; reg = RCU_BDCTL;
RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
break; break;
case RCU_IRC8M: case RCU_IRC8M:
case RCU_IRC48M: case RCU_IRC48M:
case RCU_IRC40K: case RCU_IRC40K:
case RCU_PLL_CK: case RCU_PLL_CK:
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
case RCU_PLL1_CK: case RCU_PLL1_CK:
case RCU_PLL2_CK: case RCU_PLL2_CK:
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
break; break;
default: default:
break; break;
} }
} }
@ -1174,7 +1174,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
{ {
uint32_t sws, ck_freq = 0U; uint32_t sws, ck_freq = 0U;
uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src, idx, clk_exp; uint32_t pllsel, pllpresel, predv0sel, pllmf, ck_src, idx, clk_exp;
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
uint32_t predv0, predv1, pll1mf; uint32_t predv0, predv1, pll1mf;
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
@ -1185,84 +1185,84 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
sws = GET_BITS(RCU_CFG0, 2, 3); sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws){ switch (sws) {
/* IRC8M is selected as CK_SYS */ /* IRC8M is selected as CK_SYS */
case SEL_IRC8M: case SEL_IRC8M:
cksys_freq = IRC8M_VALUE; cksys_freq = IRC8M_VALUE;
break; break;
/* HXTAL is selected as CK_SYS */ /* HXTAL is selected as CK_SYS */
case SEL_HXTAL: case SEL_HXTAL:
cksys_freq = HXTAL_VALUE; cksys_freq = HXTAL_VALUE;
break; break;
/* PLL is selected as CK_SYS */ /* PLL is selected as CK_SYS */
case SEL_PLL: case SEL_PLL:
/* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */
pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
if(RCU_PLLSRC_HXTAL_IRC48M == pllsel) { if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) {
/* PLL clock source is HXTAL or IRC48M */ /* PLL clock source is HXTAL or IRC48M */
pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL);
if(RCU_PLLPRESRC_HXTAL == pllpresel){ if (RCU_PLLPRESRC_HXTAL == pllpresel) {
/* PLL clock source is HXTAL */ /* PLL clock source is HXTAL */
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
}else{ } else {
/* PLL clock source is IRC48 */ /* PLL clock source is IRC48 */
ck_src = IRC48M_VALUE; ck_src = IRC48M_VALUE;
} }
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
/* PREDV0 input source clock divided by 2 */ /* PREDV0 input source clock divided by 2 */
if(RCU_CFG0_PREDV0 == predv0sel){ if (RCU_CFG0_PREDV0 == predv0sel) {
ck_src = HXTAL_VALUE/2U; ck_src = HXTAL_VALUE / 2U;
}
#elif defined(GD32F30X_CL)
predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
/* source clock use PLL1 */
if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
if(17U == pll1mf){
pll1mf = 20U;
} }
ck_src = (ck_src/predv1)*pll1mf; #elif defined(GD32F30X_CL)
} predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; /* source clock use PLL1 */
ck_src /= predv0; if (RCU_PREDV0SRC_CKPLL1 == predv0sel) {
predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
if (17U == pll1mf) {
pll1mf = 20U;
}
ck_src = (ck_src / predv1) * pll1mf;
}
predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
ck_src /= predv0;
#endif /* GD32F30X_HD and GD32F30X_XD */ #endif /* GD32F30X_HD and GD32F30X_XD */
}else{ } else {
/* PLL clock source is IRC8M/2 */ /* PLL clock source is IRC8M/2 */
ck_src = IRC8M_VALUE/2U; ck_src = IRC8M_VALUE / 2U;
} }
/* PLL multiplication factor */ /* PLL multiplication factor */
pllmf = GET_BITS(RCU_CFG0, 18, 21); pllmf = GET_BITS(RCU_CFG0, 18, 21);
if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) {
pllmf |= 0x10U; pllmf |= 0x10U;
} }
if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){ if ((RCU_CFG0 & RCU_CFG0_PLLMF_5)) {
pllmf |= 0x20U; pllmf |= 0x20U;
} }
if(pllmf < 15U){ if (pllmf < 15U) {
pllmf += 2U; pllmf += 2U;
}else if((pllmf >= 15U) && (pllmf <= 62U)){ } else if ((pllmf >= 15U) && (pllmf <= 62U)) {
pllmf += 1U; pllmf += 1U;
}else{ } else {
pllmf = 63U; pllmf = 63U;
} }
cksys_freq = ck_src*pllmf; cksys_freq = ck_src * pllmf;
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
if(15U == pllmf){ if (15U == pllmf) {
cksys_freq = ck_src*6U + ck_src/2U; cksys_freq = ck_src * 6U + ck_src / 2U;
} }
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
break; break;
/* IRC8M is selected as CK_SYS */ /* IRC8M is selected as CK_SYS */
default: default:
cksys_freq = IRC8M_VALUE; cksys_freq = IRC8M_VALUE;
break; break;
} }
/* calculate AHB clock frequency */ /* calculate AHB clock frequency */
@ -1281,21 +1281,21 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
apb2_freq = ahb_freq >> clk_exp; apb2_freq = ahb_freq >> clk_exp;
/* return the clocks frequency */ /* return the clocks frequency */
switch(clock){ switch (clock) {
case CK_SYS: case CK_SYS:
ck_freq = cksys_freq; ck_freq = cksys_freq;
break; break;
case CK_AHB: case CK_AHB:
ck_freq = ahb_freq; ck_freq = ahb_freq;
break; break;
case CK_APB1: case CK_APB1:
ck_freq = apb1_freq; ck_freq = apb1_freq;
break; break;
case CK_APB2: case CK_APB2:
ck_freq = apb2_freq; ck_freq = apb2_freq;
break; break;
default: default:
break; break;
} }
return ck_freq; return ck_freq;
} }

12
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c
View File

@ -94,8 +94,8 @@ void rtc_configuration_mode_exit(void)
*/ */
void rtc_lwoff_wait(void) void rtc_lwoff_wait(void)
{ {
/* loop until LWOFF flag is set */ /* loop until LWOFF flag is set */
while (RESET == (RTC_CTL & RTC_CTL_LWOFF)){ while (RESET == (RTC_CTL & RTC_CTL_LWOFF)) {
} }
} }
@ -107,10 +107,10 @@ void rtc_lwoff_wait(void)
*/ */
void rtc_register_sync_wait(void) void rtc_register_sync_wait(void)
{ {
/* clear RSYNF flag */ /* clear RSYNF flag */
RTC_CTL &= ~RTC_CTL_RSYNF; RTC_CTL &= ~RTC_CTL_RSYNF;
/* loop until RSYNF flag is set */ /* loop until RSYNF flag is set */
while (RESET == (RTC_CTL & RTC_CTL_RSYNF)){ while (RESET == (RTC_CTL & RTC_CTL_RSYNF)) {
} }
} }
@ -203,9 +203,9 @@ uint32_t rtc_divider_get(void)
*/ */
FlagStatus rtc_flag_get(uint32_t flag) FlagStatus rtc_flag_get(uint32_t flag)
{ {
if(RESET != (RTC_CTL & flag)){ if (RESET != (RTC_CTL & flag)) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }

42
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c
View File

@ -79,7 +79,7 @@ void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t cloc
/* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */
clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV);
/* if the clock division is greater or equal to 256, set the DIV[8] */ /* if the clock division is greater or equal to 256, set the DIV[8] */
if(clock_division >= 256U){ if (clock_division >= 256U) {
clock_config |= SDIO_CLKCTL_DIV8; clock_config |= SDIO_CLKCTL_DIV8;
clock_division -= 256U; clock_division -= 256U;
} }
@ -261,21 +261,21 @@ uint8_t sdio_command_index_get(void)
uint32_t sdio_response_get(uint32_t responsex) uint32_t sdio_response_get(uint32_t responsex)
{ {
uint32_t resp_content = 0U; uint32_t resp_content = 0U;
switch(responsex){ switch (responsex) {
case SDIO_RESPONSE0: case SDIO_RESPONSE0:
resp_content = SDIO_RESP0; resp_content = SDIO_RESP0;
break; break;
case SDIO_RESPONSE1: case SDIO_RESPONSE1:
resp_content = SDIO_RESP1; resp_content = SDIO_RESP1;
break; break;
case SDIO_RESPONSE2: case SDIO_RESPONSE2:
resp_content = SDIO_RESP2; resp_content = SDIO_RESP2;
break; break;
case SDIO_RESPONSE3: case SDIO_RESPONSE3:
resp_content = SDIO_RESP3; resp_content = SDIO_RESP3;
break; break;
default: default:
break; break;
} }
return resp_content; return resp_content;
} }
@ -457,7 +457,7 @@ void sdio_dma_disable(void)
FlagStatus sdio_flag_get(uint32_t flag) FlagStatus sdio_flag_get(uint32_t flag)
{ {
FlagStatus temp_flag = RESET; FlagStatus temp_flag = RESET;
if(RESET != (SDIO_STAT & flag)){ if (RESET != (SDIO_STAT & flag)) {
temp_flag = SET; temp_flag = SET;
} }
return temp_flag; return temp_flag;
@ -591,10 +591,10 @@ FlagStatus sdio_interrupt_flag_get(uint32_t int_flag)
{ {
uint32_t state = 0U; uint32_t state = 0U;
state = SDIO_STAT; state = SDIO_STAT;
if(state & int_flag){ if (state & int_flag) {
state = SDIO_INTEN; state = SDIO_INTEN;
/* check whether the corresponding bit in SDIO_INTEN is set or not */ /* check whether the corresponding bit in SDIO_INTEN is set or not */
if(state & int_flag){ if (state & int_flag) {
return SET; return SET;
} }
} }
@ -679,9 +679,9 @@ void sdio_stop_readwait_disable(void)
*/ */
void sdio_readwait_type_set(uint32_t readwait_type) void sdio_readwait_type_set(uint32_t readwait_type)
{ {
if(SDIO_READWAITTYPE_CLK == readwait_type){ if (SDIO_READWAITTYPE_CLK == readwait_type) {
SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; SDIO_DATACTL |= SDIO_DATACTL_RWTYPE;
}else{ } else {
SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE;
} }
} }

258
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c
View File

@ -52,24 +52,24 @@ OF SUCH DAMAGE.
*/ */
void spi_i2s_deinit(uint32_t spi_periph) void spi_i2s_deinit(uint32_t spi_periph)
{ {
switch(spi_periph){ switch (spi_periph) {
case SPI0: case SPI0:
/* reset SPI0 */ /* reset SPI0 */
rcu_periph_reset_enable(RCU_SPI0RST); rcu_periph_reset_enable(RCU_SPI0RST);
rcu_periph_reset_disable(RCU_SPI0RST); rcu_periph_reset_disable(RCU_SPI0RST);
break; break;
case SPI1: case SPI1:
/* reset SPI1 and I2S1 */ /* reset SPI1 and I2S1 */
rcu_periph_reset_enable(RCU_SPI1RST); rcu_periph_reset_enable(RCU_SPI1RST);
rcu_periph_reset_disable(RCU_SPI1RST); rcu_periph_reset_disable(RCU_SPI1RST);
break; break;
case SPI2: case SPI2:
/* reset SPI2 and I2S2 */ /* reset SPI2 and I2S2 */
rcu_periph_reset_enable(RCU_SPI2RST); rcu_periph_reset_enable(RCU_SPI2RST);
rcu_periph_reset_disable(RCU_SPI2RST); rcu_periph_reset_disable(RCU_SPI2RST);
break; break;
default : default :
break; break;
} }
} }
@ -90,11 +90,11 @@ void spi_i2s_deinit(uint32_t spi_periph)
\param[out] none \param[out] none
\retval none \retval none
*/ */
#ifdef GD_MBED_USED #ifdef GD_MBED_USED
/* initialize SPI parameter */ /* initialize SPI parameter */
void spi_para_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) void spi_para_init(uint32_t spi_periph, spi_parameter_struct *spi_struct)
#else #else
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct)
#endif #endif
{ {
uint32_t reg = 0U; uint32_t reg = 0U;
@ -183,36 +183,36 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
#ifdef GD32F30X_CL #ifdef GD32F30X_CL
/* get the I2S clock source */ /* get the I2S clock source */
if(((uint32_t)spi_periph) == SPI1){ if (((uint32_t)spi_periph) == SPI1) {
/* I2S1 clock source selection */ /* I2S1 clock source selection */
clks = I2S1_CLOCK_SEL; clks = I2S1_CLOCK_SEL;
}else{ } else {
/* I2S2 clock source selection */ /* I2S2 clock source selection */
clks = I2S2_CLOCK_SEL; clks = I2S2_CLOCK_SEL;
} }
if(0U != (RCU_CFG1 & clks)){ if (0U != (RCU_CFG1 & clks)) {
/* get RCU PLL2 clock multiplication factor */ /* get RCU PLL2 clock multiplication factor */
clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U); clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U);
pll2mf_4 = RCU_CFG1 & RCU_CFG1_PLL2MF_4; pll2mf_4 = RCU_CFG1 & RCU_CFG1_PLL2MF_4;
if( 0U == pll2mf_4){ if (0U == pll2mf_4) {
if((clks > 5U) && (clks < 15U)){ if ((clks > 5U) && (clks < 15U)) {
/* multiplier is between 8 and 16 */ /* multiplier is between 8 and 16 */
clks += 2U; clks += 2U;
}else{ } else {
if(15U == clks){ if (15U == clks) {
/* multiplier is 20 */ /* multiplier is 20 */
clks = 20U; clks = 20U;
} }
} }
}else{ } else {
if(clks < 15U){ if (clks < 15U) {
/* multiplier is between 18 and 32 */ /* multiplier is between 18 and 32 */
clks += 18U; clks += 18U;
}else{ } else {
if(15U == clks){ if (15U == clks) {
/* multiplier is 40 */ /* multiplier is 40 */
clks = 40U; clks = 40U;
} }
@ -223,7 +223,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U); i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U);
/* calculate i2sclock based on PLL2 and PREDV1 */ /* calculate i2sclock based on PLL2 and PREDV1 */
i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
}else{ } else {
/* get system clock */ /* get system clock */
i2sclock = rcu_clock_freq_get(CK_SYS); i2sclock = rcu_clock_freq_get(CK_SYS);
} }
@ -233,13 +233,13 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
#endif /* GD32F30X_CL */ #endif /* GD32F30X_CL */
/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
if(I2S_MCKOUT_ENABLE == mckout){ if (I2S_MCKOUT_ENABLE == mckout) {
clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
}else{ } else {
if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ if (I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) {
clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample);
}else{ } else {
clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample);
} }
} }
@ -250,7 +250,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
i2sof = (i2sof << 8U); i2sof = (i2sof << 8U);
/* set the default values */ /* set the default values */
if((i2sdiv < 2U) || (i2sdiv > 255U)){ if ((i2sdiv < 2U) || (i2sdiv > 255U)) {
i2sdiv = 2U; i2sdiv = 2U;
i2sof = 0U; i2sof = 0U;
} }
@ -286,7 +286,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
*/ */
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
{ {
uint32_t reg= 0U; uint32_t reg = 0U;
reg = SPI_I2SCTL(spi_periph); reg = SPI_I2SCTL(spi_periph);
reg &= I2S_INIT_MASK; reg &= I2S_INIT_MASK;
@ -380,9 +380,9 @@ void spi_nss_internal_low(uint32_t spi_periph)
*/ */
void spi_dma_enable(uint32_t spi_periph, uint8_t dma) void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
{ {
if(SPI_DMA_TRANSMIT == dma){ if (SPI_DMA_TRANSMIT == dma) {
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
}else{ } else {
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
} }
} }
@ -398,9 +398,9 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
*/ */
void spi_dma_disable(uint32_t spi_periph, uint8_t dma) void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
{ {
if(SPI_DMA_TRANSMIT == dma){ if (SPI_DMA_TRANSMIT == dma) {
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
}else{ } else {
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
} }
} }
@ -455,10 +455,10 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph)
*/ */
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
{ {
if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ if (SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) {
/* set the transmit only mode */ /* set the transmit only mode */
SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
}else{ } else {
/* set the receive only mode */ /* set the receive only mode */
SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
} }
@ -477,21 +477,21 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di
*/ */
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
{ {
switch(interrupt){ switch (interrupt) {
/* SPI/I2S transmit buffer empty interrupt */ /* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_TBE: case SPI_I2S_INT_TBE:
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
break; break;
/* SPI/I2S receive buffer not empty interrupt */ /* SPI/I2S receive buffer not empty interrupt */
case SPI_I2S_INT_RBNE: case SPI_I2S_INT_RBNE:
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
break; break;
/* SPI/I2S error */ /* SPI/I2S error */
case SPI_I2S_INT_ERR: case SPI_I2S_INT_ERR:
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
break; break;
default: default:
break; break;
} }
} }
@ -508,21 +508,21 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
*/ */
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
{ {
switch(interrupt){ switch (interrupt) {
/* SPI/I2S transmit buffer empty interrupt */ /* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_TBE: case SPI_I2S_INT_TBE:
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
break; break;
/* SPI/I2S receive buffer not empty interrupt */ /* SPI/I2S receive buffer not empty interrupt */
case SPI_I2S_INT_RBNE: case SPI_I2S_INT_RBNE:
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
break; break;
/* SPI/I2S error */ /* SPI/I2S error */
case SPI_I2S_INT_ERR: case SPI_I2S_INT_ERR:
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
break; break;
default : default :
break; break;
} }
} }
@ -545,49 +545,49 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg1 = SPI_STAT(spi_periph);
uint32_t reg2 = SPI_CTL1(spi_periph); uint32_t reg2 = SPI_CTL1(spi_periph);
switch(interrupt){ switch (interrupt) {
/* SPI/I2S transmit buffer empty interrupt */ /* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_FLAG_TBE: case SPI_I2S_INT_FLAG_TBE:
reg1 = reg1 & SPI_STAT_TBE; reg1 = reg1 & SPI_STAT_TBE;
reg2 = reg2 & SPI_CTL1_TBEIE; reg2 = reg2 & SPI_CTL1_TBEIE;
break; break;
/* SPI/I2S receive buffer not empty interrupt */ /* SPI/I2S receive buffer not empty interrupt */
case SPI_I2S_INT_FLAG_RBNE: case SPI_I2S_INT_FLAG_RBNE:
reg1 = reg1 & SPI_STAT_RBNE; reg1 = reg1 & SPI_STAT_RBNE;
reg2 = reg2 & SPI_CTL1_RBNEIE; reg2 = reg2 & SPI_CTL1_RBNEIE;
break; break;
/* SPI/I2S overrun interrupt */ /* SPI/I2S overrun interrupt */
case SPI_I2S_INT_FLAG_RXORERR: case SPI_I2S_INT_FLAG_RXORERR:
reg1 = reg1 & SPI_STAT_RXORERR; reg1 = reg1 & SPI_STAT_RXORERR;
reg2 = reg2 & SPI_CTL1_ERRIE; reg2 = reg2 & SPI_CTL1_ERRIE;
break; break;
/* SPI config error interrupt */ /* SPI config error interrupt */
case SPI_INT_FLAG_CONFERR: case SPI_INT_FLAG_CONFERR:
reg1 = reg1 & SPI_STAT_CONFERR; reg1 = reg1 & SPI_STAT_CONFERR;
reg2 = reg2 & SPI_CTL1_ERRIE; reg2 = reg2 & SPI_CTL1_ERRIE;
break; break;
/* SPI CRC error interrupt */ /* SPI CRC error interrupt */
case SPI_INT_FLAG_CRCERR: case SPI_INT_FLAG_CRCERR:
reg1 = reg1 & SPI_STAT_CRCERR; reg1 = reg1 & SPI_STAT_CRCERR;
reg2 = reg2 & SPI_CTL1_ERRIE; reg2 = reg2 & SPI_CTL1_ERRIE;
break; break;
/* I2S underrun error interrupt */ /* I2S underrun error interrupt */
case I2S_INT_FLAG_TXURERR: case I2S_INT_FLAG_TXURERR:
reg1 = reg1 & SPI_STAT_TXURERR; reg1 = reg1 & SPI_STAT_TXURERR;
reg2 = reg2 & SPI_CTL1_ERRIE; reg2 = reg2 & SPI_CTL1_ERRIE;
break; break;
/* SPI/I2S format error interrupt */ /* SPI/I2S format error interrupt */
case SPI_I2S_INT_FLAG_FERR: case SPI_I2S_INT_FLAG_FERR:
reg1 = reg1 & SPI_STAT_FERR; reg1 = reg1 & SPI_STAT_FERR;
reg2 = reg2 & SPI_CTL1_ERRIE; reg2 = reg2 & SPI_CTL1_ERRIE;
break; break;
default : default :
break; break;
} }
/*get SPI/I2S interrupt flag status */ /*get SPI/I2S interrupt flag status */
if(reg1 && reg2){ if (reg1 && reg2) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -615,9 +615,9 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
*/ */
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
{ {
if(SPI_STAT(spi_periph) & flag){ if (SPI_STAT(spi_periph) & flag) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -662,7 +662,7 @@ void spi_crc_off(uint32_t spi_periph)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
{ {
/* enable SPI CRC */ /* enable SPI CRC */
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
@ -702,11 +702,11 @@ void spi_crc_next(uint32_t spi_periph)
\param[out] none \param[out] none
\retval 16-bit CRC value \retval 16-bit CRC value
*/ */
uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc) uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
{ {
if(SPI_CRC_TX == crc){ if (SPI_CRC_TX == crc) {
return ((uint16_t)(SPI_TCRC(spi_periph))); return ((uint16_t)(SPI_TCRC(spi_periph)));
}else{ } else {
return ((uint16_t)(SPI_RCRC(spi_periph))); return ((uint16_t)(SPI_RCRC(spi_periph)));
} }
} }
@ -810,13 +810,13 @@ void qspi_io23_output_enable(uint32_t spi_periph)
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
} }
/*! /*!
\brief disable SPI_IO2 and SPI_IO3 pin output \brief disable SPI_IO2 and SPI_IO3 pin output
\param[in] spi_periph: SPIx(only x=0) \param[in] spi_periph: SPIx(only x=0)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void qspi_io23_output_disable(uint32_t spi_periph) void qspi_io23_output_disable(uint32_t spi_periph)
{ {
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
} }

1224
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c
View File

File diff suppressed because it is too large Load Diff

150
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c
View File

@ -44,29 +44,29 @@ OF SUCH DAMAGE.
*/ */
void usart_deinit(uint32_t usart_periph) void usart_deinit(uint32_t usart_periph)
{ {
switch(usart_periph){ switch (usart_periph) {
case USART0: case USART0:
rcu_periph_reset_enable(RCU_USART0RST); rcu_periph_reset_enable(RCU_USART0RST);
rcu_periph_reset_disable(RCU_USART0RST); rcu_periph_reset_disable(RCU_USART0RST);
break; break;
case USART1: case USART1:
rcu_periph_reset_enable(RCU_USART1RST); rcu_periph_reset_enable(RCU_USART1RST);
rcu_periph_reset_disable(RCU_USART1RST); rcu_periph_reset_disable(RCU_USART1RST);
break; break;
case USART2: case USART2:
rcu_periph_reset_enable(RCU_USART2RST); rcu_periph_reset_enable(RCU_USART2RST);
rcu_periph_reset_disable(RCU_USART2RST); rcu_periph_reset_disable(RCU_USART2RST);
break; break;
case UART3: case UART3:
rcu_periph_reset_enable(RCU_UART3RST); rcu_periph_reset_enable(RCU_UART3RST);
rcu_periph_reset_disable(RCU_UART3RST); rcu_periph_reset_disable(RCU_UART3RST);
break; break;
case UART4: case UART4:
rcu_periph_reset_enable(RCU_UART4RST); rcu_periph_reset_enable(RCU_UART4RST);
rcu_periph_reset_disable(RCU_UART4RST); rcu_periph_reset_disable(RCU_UART4RST);
break; break;
default: default:
break; break;
} }
} }
@ -79,29 +79,29 @@ void usart_deinit(uint32_t usart_periph)
*/ */
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
{ {
uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
switch(usart_periph){ switch (usart_periph) {
/* get clock frequency */ /* get clock frequency */
case USART0: case USART0:
uclk=rcu_clock_freq_get(CK_APB2); uclk = rcu_clock_freq_get(CK_APB2);
break; break;
case USART1: case USART1:
uclk=rcu_clock_freq_get(CK_APB1); uclk = rcu_clock_freq_get(CK_APB1);
break; break;
case USART2: case USART2:
uclk=rcu_clock_freq_get(CK_APB1); uclk = rcu_clock_freq_get(CK_APB1);
break; break;
case UART3: case UART3:
uclk=rcu_clock_freq_get(CK_APB1); uclk = rcu_clock_freq_get(CK_APB1);
break; break;
case UART4: case UART4:
uclk=rcu_clock_freq_get(CK_APB1); uclk = rcu_clock_freq_get(CK_APB1);
break; break;
default: default:
break; break;
} }
/* oversampling by 16, configure the value of USART_BAUD */ /* oversampling by 16, configure the value of USART_BAUD */
udiv = (uclk+baudval/2U)/baudval; udiv = (uclk + baudval / 2U) / baudval;
intdiv = udiv & 0xfff0U; intdiv = udiv & 0xfff0U;
fradiv = udiv & 0xfU; fradiv = udiv & 0xfU;
USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
@ -253,27 +253,27 @@ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf)
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
{ {
/* inverted or not the specified siginal */ /* inverted or not the specified siginal */
switch(invertpara){ switch (invertpara) {
case USART_DINV_ENABLE: case USART_DINV_ENABLE:
USART_CTL3(usart_periph) |= USART_CTL3_DINV; USART_CTL3(usart_periph) |= USART_CTL3_DINV;
break; break;
case USART_TXPIN_ENABLE: case USART_TXPIN_ENABLE:
USART_CTL3(usart_periph) |= USART_CTL3_TINV; USART_CTL3(usart_periph) |= USART_CTL3_TINV;
break; break;
case USART_RXPIN_ENABLE: case USART_RXPIN_ENABLE:
USART_CTL3(usart_periph) |= USART_CTL3_RINV; USART_CTL3(usart_periph) |= USART_CTL3_RINV;
break; break;
case USART_DINV_DISABLE: case USART_DINV_DISABLE:
USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV);
break; break;
case USART_TXPIN_DISABLE: case USART_TXPIN_DISABLE:
USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV);
break; break;
case USART_RXPIN_DISABLE: case USART_RXPIN_DISABLE:
USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV);
break; break;
default: default:
break; break;
} }
} }
@ -512,10 +512,10 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32
\param[out] none \param[out] none
\retval none \retval none
*/ */
void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) void usart_guard_time_config(uint32_t usart_periph, uint32_t guat)
{ {
USART_GP(usart_periph) &= ~(USART_GP_GUAT); USART_GP(usart_periph) &= ~(USART_GP_GUAT);
USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<<8)); USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8));
} }
/*! /*!
@ -572,7 +572,7 @@ void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
{ {
USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM);
USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum)<<1)); USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum) << 1));
} }
/*! /*!
@ -585,7 +585,7 @@ void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
void usart_block_length_config(uint32_t usart_periph, uint32_t bl) void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
{ {
USART_RT(usart_periph) &= ~(USART_RT_BL); USART_RT(usart_periph) &= ~(USART_RT_BL);
USART_RT(usart_periph) |= (USART_RT_BL & ((bl)<<24)); USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24));
} }
/*! /*!
@ -741,9 +741,9 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
*/ */
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
{ {
if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ if (RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }
@ -789,11 +789,11 @@ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
*/ */
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
{ {
if((BIT(USART_BIT_POS(flag)) & 0x1f) != 0U){ if ((BIT(USART_BIT_POS(flag)) & 0x1f) != 0U) {
/* read USART_STAT0 and then read USART_DATA to clear error flag */ /* read USART_STAT0 and then read USART_DATA to clear error flag */
USART_STAT0(usart_periph); USART_STAT0(usart_periph);
USART_DATA(usart_periph); USART_DATA(usart_periph);
}else if((BIT(USART_BIT_POS(flag)) & 0x1b60) != 0U){ } else if ((BIT(USART_BIT_POS(flag)) & 0x1b60) != 0U) {
USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag));
} }
} }
@ -873,9 +873,9 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
/* get the corresponding flag bit status */ /* get the corresponding flag bit status */
flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
if(flagstatus && intenable){ if (flagstatus && intenable) {
return SET; return SET;
}else{ } else {
return RESET; return RESET;
} }
} }

6
targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c
View File

@ -97,8 +97,8 @@ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
uint32_t reg_cfg = 0U, reg_ctl = 0U; uint32_t reg_cfg = 0U, reg_ctl = 0U;
/* clear WIN and PSC bits, clear CNT bit */ /* clear WIN and PSC bits, clear CNT bit */
reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); reg_cfg = (WWDGT_CFG & (~(WWDGT_CFG_WIN | WWDGT_CFG_PSC)));
reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); reg_ctl = (WWDGT_CTL & (~WWDGT_CTL_CNT));
/* configure WIN and PSC bits, configure CNT bit */ /* configure WIN and PSC bits, configure CNT bit */
reg_cfg |= CFG_WIN(window); reg_cfg |= CFG_WIN(window);
@ -128,7 +128,7 @@ void wwdgt_interrupt_enable(void)
*/ */
FlagStatus wwdgt_flag_get(void) FlagStatus wwdgt_flag_get(void)
{ {
if(WWDGT_STAT & WWDGT_STAT_EWIF){ if (WWDGT_STAT & WWDGT_STAT_EWIF) {
return SET; return SET;
} }