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[BEETLE] Add initial Beetle CMSIS files 

This patch adds support for BEETLE SoC Target into the CMSIS layer.
It contains:
* Beetle System Core
* APB DualTimer Driver
* APB Timer Driver
* eFlash Driver
* Flash Cache Driver
* ARM Toolchain Support
* GCC ARM Toolchain Support

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
pull/1852/head
Vincenzo Frascino 2016-05-11 15:45:03 +01:00
parent 0d3268b61c
commit 44be0626a6
24 changed files with 4182 additions and 0 deletions
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1027
hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/CMSDK_BEETLE.h Normal file
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35
hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/BEETLE.sct Normal file
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;/*
; * BEETLE CMSIS Library
; */
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +FIRST)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
RW_IRAM1 (0x20000000+0x140) (0x20000-0x140) { ; RW data
.ANY (+RW +ZI)
}
}

316
hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/startup_BEETLE.s Normal file
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;/*
; * BEETLE CMSIS Library
; */
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; This file is derivative of CMSIS V5.00 startup_ARMCM3.s
;
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0_Handler ; UART 0 RX and TX Handler
DCD Spare_IRQ_Handler ; Undefined
DCD UART1_Handler ; UART 1 RX and TX Handler
DCD I2C0_Handler ; I2C 0 Handler
DCD I2C1_Handler ; I2C 1 Handler
DCD RTC_Handler ; RTC Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI0_Handler ; SPI 0 Handler
DCD UARTOVF_Handler ; UART 0,1 Overflow Handler
DCD SPI1_Handler ; SPI 1 Handler
DCD QSPI_Handler ; QSPI Handler
DCD DMA_Handler ; DMA handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
DCD SysError_Handler ; System Error (Flash Cache)
DCD EFLASH_Handler ; Embedded Flash
DCD LLCC_TXCMD_EMPTY_Handler ; LLCC_TXCMDIRQ
DCD LLCC_TXEVT_EMPTY_Handler ; LLCC_TXEVTIRQ
DCD LLCC_TXDMAH_DONE_Handler ; LLCC_TXDMA0IRQ
DCD LLCC_TXDMAL_DONE_Handler ; LLCC_TXDMA1IRQ
DCD LLCC_RXCMD_VALID_Handler ; LLCC_RXCMDIRQ
DCD LLCC_RXEVT_VALID_Handler ; LLCC_RXEVTIRQ
DCD LLCC_RXDMAH_DONE_Handler ; LLCC_RXDMA0IRQ
DCD LLCC_RXDMAL_DONE_Handler ; LLCC_RXDMA1IRQ
DCD PORT2_COMB_Handler ; GPIO 2
DCD PORT3_COMB_Handler ; GPIO 3
DCD TRNG_Handler ; TRNG
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0_Handler [WEAK]
EXPORT Spare_IRQ_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT I2C0_Handler [WEAK]
EXPORT I2C1_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
EXPORT PORT1_COMB_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT UARTOVF_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
EXPORT QSPI_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
EXPORT PORT0_3_Handler [WEAK]
EXPORT PORT0_4_Handler [WEAK]
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
EXPORT SysError_Handler [WEAK]
EXPORT EFLASH_Handler [WEAK]
EXPORT LLCC_TXEVT_EMPTY_Handler [WEAK]
EXPORT LLCC_TXCMD_EMPTY_Handler [WEAK]
EXPORT LLCC_RXEVT_VALID_Handler [WEAK]
EXPORT LLCC_RXCMD_VALID_Handler [WEAK]
EXPORT LLCC_TXDMAL_DONE_Handler [WEAK]
EXPORT LLCC_RXDMAL_DONE_Handler [WEAK]
EXPORT LLCC_TXDMAH_DONE_Handler [WEAK]
EXPORT LLCC_RXDMAH_DONE_Handler [WEAK]
EXPORT PORT2_COMB_Handler [WEAK]
EXPORT PORT3_COMB_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
UART0_Handler
Spare_IRQ_Handler
UART1_Handler
I2C0_Handler
I2C1_Handler
RTC_Handler
PORT0_COMB_Handler
PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
SPI0_Handler
UARTOVF_Handler
SPI1_Handler
QSPI_Handler
DMA_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
SysError_Handler
EFLASH_Handler
LLCC_TXEVT_EMPTY_Handler
LLCC_TXCMD_EMPTY_Handler
LLCC_RXEVT_VALID_Handler
LLCC_RXCMD_VALID_Handler
LLCC_TXDMAL_DONE_Handler
LLCC_RXDMAL_DONE_Handler
LLCC_TXDMAH_DONE_Handler
LLCC_RXDMAH_DONE_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
TRNG_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

181
hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/BEETLE.ld Normal file
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/*
* BEETLE CMSIS Library
*/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 gcc_arm.ld
*/
/* Linker script for mbed BEETLE SoC */
/* Linker script to configure memory regions. */
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x00020000 - 0x00000140
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
. = ALIGN(4);
} > VECTORS
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

273
hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/startup_BEETLE.S Normal file
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/*
* BEETLE CMSIS Library
*/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 startup_ARMCM3.S
*/
.syntax unified
.arch armv7-m
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0xC00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long UART0_Handler /* 0:UART 0 RX and TX Combined Interrupt */
.long Spare_Handler /* 1:Undefined */
.long UART1_Handler /* 2:UART 1 RX and TX Combined Interrupt */
.long I2C0_Handler /* 3:I2C 0 Interrupt */
.long I2C1_Handler /* 4:I2C 1 Interrupt */
.long RTC_Handler /* 5:RTC Interrupt */
.long PORT0_Handler /* 6:GPIO Port 0 combined Interrupt */
.long PORT1_ALL_Handler /* 7:GPIO Port 1 combined Interrupt */
.long TIMER0_Handler /* 8:TIMER 0 Interrupt */
.long TIMER1_Handler /* 9:TIMER 1 Interrupt */
.long DUALTIMER_Handler /* 10:Dual Timer Interrupt */
.long SPI0_Handler /* 11:SPI 0 Interrupt */
.long UARTOVF_Handler /* 12:UART 0,1,2 Overflow Interrupt */
.long SPI1_Handler /* 13:SPI 1 Interrupt */
.long QSPI_Handler /* 14:QUAD SPI Interrupt */
.long DMA_Handler /* 15:Touch Screen Interrupt */
.long PORT0_0_Handler /* 16:All P0 and P1I/O pins used as irq source */
.long PORT0_1_Handler /* 17:There are 16 pins in total */
.long PORT0_2_Handler /* 18: */
.long PORT0_3_Handler /* 19: */
.long PORT0_4_Handler /* 20: */
.long PORT0_5_Handler /* 21: */
.long PORT0_6_Handler /* 22: */
.long PORT0_7_Handler /* 23: */
.long PORT0_8_Handler /* 24: */
.long PORT0_9_Handler /* 25: */
.long PORT0_10_Handler /* 26: */
.long PORT0_11_Handler /* 27: */
.long PORT0_12_Handler /* 28: */
.long PORT0_13_Handler /* 29: */
.long PORT0_14_Handler /* 30: */
.long PORT0_15_Handler /* 31: */
.long SysError_Handler /* 32: System Error (Flash Cache) */
.long EFLASH_Handler /* 33: Embedded Flash */
.long LLCC_TXCMD_EMPTY_Handler /* 34: LLCC_TXCMDIRQ */
.long LLCC_TXEVT_EMPTY_Handler /* 35: LLCC_TXEVTIRQ */
.long LLCC_TXDMAH_DONE_Handler /* 36: LLCC_TXDMA0IRQ */
.long LLCC_TXDMAL_DONE_Handler /* 37: LLCC_TXDMA1IRQ */
.long LLCC_RXCMD_VALID_Handler /* 38: LLCC_RXCMDIRQ */
.long LLCC_RXEVT_VALID_Handler /* 39: LLCC_RXEVTIRQ */
.long LLCC_RXDMAH_DONE_Handler /* 40: LLCC_RXDMA0IRQ */
.long LLCC_RXDMAL_DONE_Handler /* 41: LLCC_RXDMA1IRQ */
.long PORT2_COMB_Handler /* 42: GPIO 2 */
.long PORT3_COMB_Handler /* 43: GPIO 3 */
.long TRNG_Handler /* 44: TRNG */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
mov r4, #0
zero:
strb r4, [r1], #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UART0_Handler /* 0:UART 0 RX and TX Combined Interrupt */
def_irq_default_handler Spare_Handler /* 1:Undefined */
def_irq_default_handler UART1_Handler /* 2:UART 1 RX and TX Combined Interrupt */
def_irq_default_handler I2C0_Handler /* 3:I2C 0 Interrupt */
def_irq_default_handler I2C1_Handler /* 4:I2C 1 Interrupt */
def_irq_default_handler RTC_Handler /* 5:RTC Interrupt */
def_irq_default_handler PORT0_Handler /* 6:GPIO Port 0 combined Interrupt */
def_irq_default_handler PORT1_ALL_Handler /* 7:GPIO Port 1 combined Interrupt */
def_irq_default_handler TIMER0_Handler /* 8:TIMER 0 Interrupt */
def_irq_default_handler TIMER1_Handler /* 9:TIMER 1 Interrupt */
def_irq_default_handler DUALTIMER_Handler /* 10:Dual Timer Interrupt */
def_irq_default_handler SPI0_Handler /* 11:SPI 0 Interrupt */
def_irq_default_handler UARTOVF_Handler /* 12:UART 0,1,2 Overflow Interrupt */
def_irq_default_handler SPI1_Handler /* 13:SPI 1 Interrupt */
def_irq_default_handler QSPI_Handler /* 14:QUAD SPI Interrupt */
def_irq_default_handler DMA_Handler /* 15:Touch Screen Interrupt */
def_irq_default_handler PORT0_0_Handler /* 16:All P0 and P1I/O pins used as irq source */
def_irq_default_handler PORT0_1_Handler /* 17:There are 16 pins in total */
def_irq_default_handler PORT0_2_Handler /* 18: */
def_irq_default_handler PORT0_3_Handler /* 19: */
def_irq_default_handler PORT0_4_Handler /* 20: */
def_irq_default_handler PORT0_5_Handler /* 21: */
def_irq_default_handler PORT0_6_Handler /* 22: */
def_irq_default_handler PORT0_7_Handler /* 23: */
def_irq_default_handler PORT0_8_Handler /* 24: */
def_irq_default_handler PORT0_9_Handler /* 25: */
def_irq_default_handler PORT0_10_Handler /* 26: */
def_irq_default_handler PORT0_11_Handler /* 27: */
def_irq_default_handler PORT0_12_Handler /* 28: */
def_irq_default_handler PORT0_13_Handler /* 29: */
def_irq_default_handler PORT0_14_Handler /* 30: */
def_irq_default_handler PORT0_15_Handler /* 31: */
def_irq_default_handler SysError_Handler /* 32: System Error (Flash Cache) */
def_irq_default_handler EFLASH_Handler /* 33: Embedded Flash */
def_irq_default_handler LLCC_TXCMD_EMPTY_Handler /* 34: LLCC_TXCMDIRQ */
def_irq_default_handler LLCC_TXEVT_EMPTY_Handler /* 35: LLCC_TXEVTIRQ */
def_irq_default_handler LLCC_TXDMAH_DONE_Handler /* 36: LLCC_TXDMA0IRQ */
def_irq_default_handler LLCC_TXDMAL_DONE_Handler /* 37: LLCC_TXDMA1IRQ */
def_irq_default_handler LLCC_RXCMD_VALID_Handler /* 38: LLCC_RXCMDIRQ */
def_irq_default_handler LLCC_RXEVT_VALID_Handler /* 39: LLCC_RXEVTIRQ */
def_irq_default_handler LLCC_RXDMAH_DONE_Handler /* 40: LLCC_RXDMA0IRQ */
def_irq_default_handler LLCC_RXDMAL_DONE_Handler /* 41: LLCC_RXDMA1IRQ */
def_irq_default_handler PORT2_COMB_Handler /* 42: GPIO 2 */
def_irq_default_handler PORT3_COMB_Handler /* 43: GPIO 3 */
def_irq_default_handler TRNG_Handler /* 44: TRNG */
.end

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/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "apb_dualtimer.h"
/* DualTimer Private Data */
typedef struct {
/* DualTimer 1 Definition */
CMSDK_DUALTIMER_SINGLE_TypeDef *dualtimer1;
/* DualTimer 2 Definition */
CMSDK_DUALTIMER_SINGLE_TypeDef *dualtimer2;
/* Dual Timer IRQn */
uint32_t dualtimerIRQn;
/* DualTimer 1 Reload Value */
uint32_t dualtimer1Reload;
/* DualTimer 2 Reload Value */
uint32_t dualtimer2Reload;
/* Timer state */
uint32_t state;
} apb_dualtimer_t;
/* Timer state definitions */
#define DUALTIMER_INITIALIZED (1)
#define DUALTIMER_ENABLED (1 << 1)
/*
* This Timer is written for MBED OS and keeps count
* of the ticks. All the elaboration logic is demanded
* to the upper layers.
*/
#define DUALTIMER_MAX_VALUE 0xFFFFFFFF
#define DUALTIMER_TICKS_US (SystemCoreClock/1000000)
/* Dual Timers Array */
static apb_dualtimer_t DualTimers[NUM_DUALTIMERS];
/*
* DualTimer_Initialize(): Initializes a hardware timer
* timer: timer to be Initialized
* time_us: timer reload value in us - 0 to reload to timer max value
* time_us = ticks_value / TIMER_TICK_US
*/
void DualTimer_Initialize(uint32_t timer, uint32_t time_us)
{
uint32_t reload = 0;
if (timer < NUM_DUALTIMERS)
{
if (time_us == 0)
reload = DUALTIMER_MAX_VALUE;
else
reload = (time_us) * DUALTIMER_TICKS_US;
switch(timer) {
case 0: DualTimers[timer].dualtimer1 = CMSDK_DUALTIMER1;
DualTimers[timer].dualtimer2 = CMSDK_DUALTIMER2;
DualTimers[timer].dualtimerIRQn = DUALTIMER_IRQn;
DualTimers[timer].dualtimer1Reload = reload;
DualTimers[timer].dualtimer2Reload = reload;
DualTimers[timer].state = DUALTIMER_INITIALIZED;
default: break;
}
}
}
/*
* DualTimer_ReturnMode(): returns the correct mode for Dual Timer Control
* mode: mode set by user
* @return: mode for TimeControl register
*/
uint32_t DualTimer_ReturnMode(timerenable_t mode)
{
uint32_t return_mode = 0;
/* Check Interrupt Enable */
if (((mode & DUALTIMER_INT) >> DUALTIMER_INT_MASK) == 1)
return_mode |= CMSDK_DUALTIMER_CTRL_INTEN_Msk;
/* Check 32 bit Counter */
if (((mode & DUALTIMER_COUNT_32) >> DUALTIMER_COUNT_32_MASK) == 1)
return_mode |= CMSDK_DUALTIMER_CTRL_SIZE_Msk;
/* Check Periodic Mode */
if (((mode & DUALTIMER_PERIODIC) >> DUALTIMER_PERIODIC_MASK) == 1)
return_mode |= CMSDK_DUALTIMER_CTRL_MODE_Msk;
/* Check OneShot Mode */
if (((mode & DUALTIMER_ONESHOT) >> DUALTIMER_ONESHOT_MASK) == 1)
return_mode |= CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk;
return return_mode;
}
/*
* DualTimer_Enable(): Enables a hardware timer
* timer: timer to be enabled
* mode: enable mode
*/
void DualTimer_Enable(uint32_t timer, timerenable_t mode)
{
uint32_t dualtimerControl = 0;
/* The timer has to be contained in a valid range */
if (timer < NUM_DUALTIMERS) {
/* Timer has to be already initialized */
if (DualTimers[timer].state == DUALTIMER_INITIALIZED) {
/* Disable Timer */
(DualTimers[timer].dualtimer1)->TimerControl = 0x0;
(DualTimers[timer].dualtimer2)->TimerControl = 0x0;
/* Reload Value */
(DualTimers[timer].dualtimer1)->TimerLoad =
DualTimers[timer].dualtimer1Reload;
(DualTimers[timer].dualtimer2)->TimerLoad =
DualTimers[timer].dualtimer2Reload;
/* Set up Dual Timer Control */
dualtimerControl = DualTimer_ReturnMode(mode);
(DualTimers[timer].dualtimer1)->TimerControl = dualtimerControl;
(DualTimers[timer].dualtimer2)->TimerControl = dualtimerControl;
/* Enable Counter */
(DualTimers[timer].dualtimer1)->TimerControl |=
CMSDK_DUALTIMER_CTRL_EN_Msk;
(DualTimers[timer].dualtimer2)->TimerControl |=
CMSDK_DUALTIMER_CTRL_EN_Msk;
/* Change timer state */
DualTimers[timer].state |= DUALTIMER_ENABLED;
}
}
}
/*
* DualTimer_Disable(): Disables a hardware timer
* timer: timer to be disabled
* dis_timer: 0 both - 1 dual timer 1 - 2 dual timer 2
*/
void DualTimer_Disable(uint32_t timer, uint32_t dis_timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_DUALTIMERS) {
/* Timer has to be already initialized and enabled */
if (DualTimers[timer].state == (DUALTIMER_INITIALIZED | DUALTIMER_ENABLED)) {
/* Disable Timer */
switch (dis_timer)
{
case 0: (DualTimers[timer].dualtimer1)->TimerControl = 0x0;
(DualTimers[timer].dualtimer2)->TimerControl = 0x0;
break;
case 1: (DualTimers[timer].dualtimer1)->TimerControl = 0x0;
break;
case 2: (DualTimers[timer].dualtimer2)->TimerControl = 0x0;
break;
default: break;
}
/* Change timer state */
DualTimers[timer].state = DUALTIMER_INITIALIZED;
}
}
}
/*
* DualTimer_isEnabled(): verifies if a timer is enabled
* timer: timer to be verified
* @return: 0 disabled - 1 enabled
*/
uint32_t DualTimer_isEnabled(uint32_t timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_DUALTIMERS) {
/* Timer has to be already initialized and enabled */
if (DualTimers[timer].state == (DUALTIMER_INITIALIZED | DUALTIMER_ENABLED))
return 1;
} else {
return 0;
}
return 0;
}
/*
* DualTimer_Read_1(): provides single timer 1 VALUE
* timer: timer to be read
* @return: timer VALUE
*/
uint32_t DualTimer_Read_1(uint32_t timer)
{
uint32_t return_value = 0;
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
return_value = (DualTimers[timer].dualtimer1Reload
- (DualTimers[timer].dualtimer1)->TimerValue)
/ DUALTIMER_TICKS_US;
}
return return_value;
}
/*
* DualTimer_Read_2(): provides single timer 2 VALUE
* timer: timer to be read
* @return: timer VALUE
*/
uint32_t DualTimer_Read_2(uint32_t timer)
{
uint32_t return_value = 0;
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
return_value = (DualTimers[timer].dualtimer2Reload
- (DualTimers[timer].dualtimer2)->TimerValue)
/ DUALTIMER_TICKS_US;
}
return return_value;
}
/*
* DualTimer_SetInterrupt_1(): sets timer 1 Interrupt
* timer: timer on which interrupt is set
* time_us: reloading value us
* mode: enable mode
*/
void DualTimer_SetInterrupt_1(uint32_t timer, uint32_t time_us,
timerenable_t mode)
{
uint32_t dualtimerControl = 0;
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
/* Disable Timer */
DualTimer_Disable(timer, SINGLETIMER1);
/* Set up Dual Timer Control */
dualtimerControl = DualTimer_ReturnMode(mode);
(DualTimers[timer].dualtimer1)->TimerControl =
CMSDK_DUALTIMER_CTRL_INTEN_Msk
| dualtimerControl;
/* Reload Value */
DualTimers[timer].dualtimer1Reload = (time_us)
* DUALTIMER_TICKS_US;
(DualTimers[timer].dualtimer1)->TimerLoad =
DualTimers[timer].dualtimer1Reload;
/* Enable Counter */
(DualTimers[timer].dualtimer1)->TimerControl |=
CMSDK_DUALTIMER_CTRL_EN_Msk;
/* Change timer state */
DualTimers[timer].state |= DUALTIMER_ENABLED;
}
}
/*
* DualTimer_SetInterrupt_2(): sets timer 2 Interrupt
* timer: timer on which interrupt is set
* time_us: reloading value us
* mode: enable mode
*/
void DualTimer_SetInterrupt_2(uint32_t timer, uint32_t time_us,
timerenable_t mode)
{
uint32_t dualtimerControl = 0;
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
/* Disable Timer */
DualTimer_Disable(timer, SINGLETIMER2);
/* Set up Dual Timer Control */
dualtimerControl = DualTimer_ReturnMode(mode);
(DualTimers[timer].dualtimer2)->TimerControl =
CMSDK_DUALTIMER_CTRL_INTEN_Msk
| dualtimerControl;
/* Reload Value */
DualTimers[timer].dualtimer2Reload = (time_us)
* DUALTIMER_TICKS_US;
(DualTimers[timer].dualtimer2)->TimerLoad =
DualTimers[timer].dualtimer2Reload;
/* Enable Counter */
(DualTimers[timer].dualtimer2)->TimerControl |=
CMSDK_DUALTIMER_CTRL_EN_Msk;
/* Change timer state */
DualTimers[timer].state |= DUALTIMER_ENABLED;
}
}
/*
* DualTimer_DisableInterrupt(): disables timer interrupt
* timer: timer on which interrupt is disabled
*/
void DualTimer_DisableInterrupt(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
/* Disable Interrupt */
(DualTimers[timer].dualtimer1)->TimerControl &=
CMSDK_DUALTIMER_CTRL_EN_Msk;
(DualTimers[timer].dualtimer2)->TimerControl &=
CMSDK_DUALTIMER_CTRL_EN_Msk;
}
}
/*
* DualTimer_ClearInterrupt(): clear timer interrupt
* timer: timer on which interrupt needs to be cleared
*/
void DualTimer_ClearInterrupt(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
/* Clear Interrupt */
(DualTimers[timer].dualtimer1)->TimerIntClr =
CMSDK_DUALTIMER_INTCLR_Msk;
(DualTimers[timer].dualtimer2)->TimerIntClr =
CMSDK_DUALTIMER_INTCLR_Msk;
}
}
/*
* DualTimer_GetIRQn(): returns IRQn of a DualTimer
* timer: timer on which IRQn is defined - 0 if it is not defined
*/
uint32_t DualTimer_GetIRQn(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
return DualTimers[timer].dualtimerIRQn;
}
return 0;
}
/*
* DualTimer_GetIRQInfo(): provides the single timer who caused
* the interrupt.
* dualtimer: dualtimer that triggered the IRQ
* @return: a single timer - 0 if it is not defined
*/
uint32_t DualTimer_GetIRQInfo(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
if((DualTimers[timer].dualtimer1)->TimerRIS)
return SINGLETIMER1;
else
return SINGLETIMER2;
}
return 0;
}
/*
* DualTimer_GetTicksUS(): returns the Ticks per us
* timer: timer associated with the Ticks per us
* @return: Ticks per us - 0 if the timer is disables
*/
uint32_t DualTimer_GetTicksUS(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (DualTimer_isEnabled(timer) == 1) {
return DUALTIMER_TICKS_US;
}
return 0;
}

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/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _APB_DUAL_TIMER_DRV_H
#define _APB_DUAL_TIMER_DRV_H
#ifdef __cplusplus
extern "C" {
#endif
/* Supported Number of Dual Timers */
#define NUM_DUALTIMERS 1
#define DUALTIMER0 0
#define SINGLETIMER1 1
#define SINGLETIMER2 2
/*
* DualTimer_Initialize(): Initializes a hardware timer
* timer: timer to be Initialized
* time_us: timer reload value in us - 0 to reload to timer max value
* time_us = tick_value / TIMER_TICK_US
*/
void DualTimer_Initialize(uint32_t timer, uint32_t time_us);
/* Enable Mode */
typedef uint8_t timerenable_t;
/* Interrupt */
#define DUALTIMER_INT_MASK (0)
#define DUALTIMER_INT (1 << DUALTIMER_INT_MASK)
/* 32 bit Counter */
#define DUALTIMER_COUNT_32_MASK (1)
#define DUALTIMER_COUNT_32 (1 << DUALTIMER_COUNT_32_MASK)
/* Periodic mode */
#define DUALTIMER_PERIODIC_MASK (2)
#define DUALTIMER_PERIODIC (1 << DUALTIMER_PERIODIC_MASK)
/* OneShot mode */
#define DUALTIMER_ONESHOT_MASK (3)
#define DUALTIMER_ONESHOT (1 << DUALTIMER_ONESHOT_MASK)
/*
* DualTimer_Enable(): Enables a hardware timer
* timer: timer to be enabled
* mode: enable mode
*/
void DualTimer_Enable(uint32_t timer, timerenable_t mode);
/*
* DualTimer_Disable(): Disables a hardware timer
* timer: timer to be disabled
* dis_timer: 0 both - 1 dual timer 1 - 2 dual timer 2
*/
void DualTimer_Disable(uint32_t timer, uint32_t dis_timer);
/*
* DualTimer_isEnabled(): verifies if a timer is enabled
* timer: timer to be verified
* @return: 0 disabled - 1 enabled
*/
uint32_t DualTimer_isEnabled(uint32_t timer);
/*
* DualTimer_Read_1(): provides single timer 1 VALUE
* timer: timer to be read
* @return: timer VALUE us
*/
uint32_t DualTimer_Read_1(uint32_t timer);
/*
* DualTimer_Read_2(): provides single timer 2 VALUE
* timer: timer to be read
* @return: timer VALUE us
*/
uint32_t DualTimer_Read_2(uint32_t timer);
/*
* DualTimer_SetInterrupt_1(): sets timer 1 Interrupt
* timer: timer on which interrupt is set
* time_us: reloading value us
* mode: enable mode
*/
void DualTimer_SetInterrupt_1(uint32_t timer, uint32_t time_us,
timerenable_t mode);
/*
* DualTimer_SetInterrupt_2(): sets timer 2 Interrupt
* timer: timer on which interrupt is set
* time_us: reloading value us
* mode: enable mode
*/
void DualTimer_SetInterrupt_2(uint32_t timer, uint32_t time_us,
timerenable_t mode);
/*
* DualTimer_DisableInterrupt(): disables timer interrupt
* timer: timer on which interrupt is disabled
*/
void DualTimer_DisableInterrupt(uint32_t timer);
/*
* DualTimer_ClearInterrupt(): clear timer interrupt
* timer: timer on which interrupt needs to be cleared
*/
void DualTimer_ClearInterrupt(uint32_t timer);
/*
* DualTimer_GetIRQn(): returns IRQn of a DualTimer
* timer: timer on which IRQn is defined - 0 if it is not defined
*/
uint32_t DualTimer_GetIRQn(uint32_t timer);
/*
* DualTimer_GetIRQInfo(): provides the single timer who caused
* the interrupt.
* timer: dualtimer that triggered the IRQ
* @return: a single timer
*/
uint32_t DualTimer_GetIRQInfo(uint32_t dualtimer);
/*
* DualTimer_GetTicksUS(): returns the Ticks per us
* timer: timer associated with the Ticks per us
* @return: Ticks per us - 0 if the timer is disables
*/
uint32_t DualTimer_GetTicksUS(uint32_t timer);
#ifdef __cplusplus
}
#endif
#endif /* _APB_DUAL_TIMER_DRV_H */

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/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "apb_timer.h"
/* Timer Private Data */
typedef struct {
/* Timer Definition */
CMSDK_TIMER_TypeDef *timerN;
/* Timer IRQn */
uint32_t timerIRQn;
/* Timer Reload Value */
uint32_t timerReload;
/* Timer state */
uint32_t state;
} apb_timer_t;
/* Timer state definitions */
#define TIMER_INITIALIZED (1)
#define TIMER_ENABLED (1 << 1)
/*
* This Timer is written for MBED OS and keeps count
* of the ticks. All the elaboration logic is demanded
* to the upper layers.
*/
#define TIMER_MAX_VALUE 0xFFFFFFFF
#define TIMER_TICKS_US (SystemCoreClock/1000000)
/* Timers Array */
static apb_timer_t Timers[NUM_TIMERS];
void Timer_Index_Init(uint32_t timer, uint32_t reload,
CMSDK_TIMER_TypeDef *TimerN, uint32_t IRQn)
{
Timers[timer].timerN = TimerN;
Timers[timer].timerIRQn = IRQn;
Timers[timer].timerReload = reload;
Timers[timer].state = TIMER_INITIALIZED;
}
/*
* Timer_Initialize(): Initializes an hardware timer
* timer: timer to be Initialized
* time_us: timer reload value in us - 0 to reload to timer max value
* time_us = tick_value / TIMER_TICKS_US
*/
#define TIMER_INIT(index, reload) Timer_Index_Init(index, reload, CMSDK_TIMER##index, TIMER##index##_IRQn)
void Timer_Initialize(uint32_t timer, uint32_t time_us)
{
uint32_t reload = 0;
if (timer < NUM_TIMERS)
{
if (time_us == 0)
reload = TIMER_MAX_VALUE;
else
reload = (time_us) * TIMER_TICKS_US;
switch(timer) {
case 0: TIMER_INIT(0, reload);
break;
case 1: TIMER_INIT(1, reload);
break;
default: break;
}
}
}
/*
* Timer_Enable(): Enables a hardware timer
* timer: timer to be enabled
*/
void Timer_Enable(uint32_t timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_TIMERS) {
/* Timer has to be already initialized */
if (Timers[timer].state == TIMER_INITIALIZED) {
/* Disable Timer */
(Timers[timer].timerN)->CTRL = 0x0;
/* Reload Value */
(Timers[timer].timerN)->RELOAD = Timers[timer].timerReload;
/* Enable Interrupt */
(Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk;
/* Enable Counter */
(Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
/* Change timer state */
Timers[timer].state |= TIMER_ENABLED;
}
}
}
/*
* Timer_Disable(): Disables a hardware timer
* timer: timer to be disabled
*/
void Timer_Disable(uint32_t timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_TIMERS) {
/* Timer has to be already initialized and enabled */
if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED)) {
/* Disable Timer */
(Timers[timer].timerN)->CTRL = 0x0;
/* Change timer state */
Timers[timer].state = TIMER_INITIALIZED;
}
}
}
/*
* Timer_isEnabled(): verifies if a timer is enabled
* timer: timer to be verified
* @return: 0 disabled - 1 enabled
*/
uint32_t Timer_isEnabled(uint32_t timer)
{
/* The timer has to be contained in a valid range */
if (timer < NUM_TIMERS) {
/* Timer has to be already initialized and enabled */
if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED))
return 1;
} else {
return 0;
}
return 0;
}
/*
* Timer_Read(): provides timer VALUE
* timer: timer to be read
* @return: timer VALUE us
*/
uint32_t Timer_Read(uint32_t timer)
{
uint32_t return_value = 0;
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
return_value = (Timers[timer].timerReload
- (Timers[timer].timerN)->VALUE)
/ TIMER_TICKS_US;
}
return return_value;
}
/*
* Timer_SetInterrupt(): sets timer Interrupt
* timer: timer on which interrupt is set
* time_us: reloading time in us
*/
void Timer_SetInterrupt(uint32_t timer, uint32_t time_us)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
/* Disable Timer */
Timer_Disable(timer);
/* Enable Interrupt */
(Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk;
/* Initialize Timer Value */
Timers[timer].timerReload = (time_us) * TIMER_TICKS_US;
(Timers[timer].timerN)->RELOAD = Timers[timer].timerReload;
(Timers[timer].timerN)->VALUE = Timers[timer].timerReload;
/* Enable Counter */
(Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
/* Change timer state */
Timers[timer].state |= TIMER_ENABLED;
}
}
/*
* Timer_DisableInterrupt(): disables timer interrupt
* timer: timer on which interrupt is disabled
*/
void Timer_DisableInterrupt(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
/* Disable Interrupt */
(Timers[timer].timerN)->CTRL &= CMSDK_TIMER_CTRL_EN_Msk;
}
}
/*
* Timer_ClearInterrupt(): clear timer interrupt
* timer: timer on which interrupt needs to be cleared
*/
void Timer_ClearInterrupt(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
/* Clear Interrupt */
(Timers[timer].timerN)->INTCLEAR = CMSDK_TIMER_INTCLEAR_Msk;
}
}
/*
* Timer_GetIRQn(): returns IRQn of a Timer
* timer: timer on which IRQn is defined - 0 if it is not defined
*/
uint32_t Timer_GetIRQn(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
return Timers[timer].timerIRQn;
}
return 0;
}
/*
* Timer_GetTicksUS(): returns the number of Ticks per us
* timer: timer associated with the Ticks per us
* @return: Ticks per us - 0 if the timer is disables
*/
uint32_t Timer_GetTicksUS(uint32_t timer)
{
/* Verify if the Timer is enabled */
if (Timer_isEnabled(timer) == 1) {
return TIMER_TICKS_US;
}
return 0;
}

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/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _APB_TIMER_DRV_H
#define _APB_TIMER_DRV_H
#ifdef __cplusplus
extern "C" {
#endif
/* Supported Number of Timers */
#define NUM_TIMERS 2
#define TIMER0 0
#define TIMER1 1
/*
* Timer_Initialize(): Initializes an hardware timer
* timer: timer to be Initialized
* time_us: timer reload value in us - 0 to reload to timer max value
* time_us = tick_value / TIMER_TICK_US
*/
void Timer_Initialize(uint32_t timer, uint32_t time_us);
/*
* Timer_Enable(): Enables an hardware timer
* timer: timer to be enabled
*/
void Timer_Enable(uint32_t timer);
/*
* Timer_Disable(): Disables an hardware timer
* timer: timer to be disabled
*/
void Timer_Disable(uint32_t timer);
/*
* Timer_isEnabled(): verifies if a timer is enabled
* timer: timer to be verified
* @return: 0 disabled - 1 enabled
*/
uint32_t Timer_isEnabled(uint32_t timer);
/*
* Timer_Read(): provides timer VALUE
* timer: timer to be read
* @return: timer VALUE
*/
uint32_t Timer_Read(uint32_t timer);
/*
* Timer_SetInterrupt(): sets timer Interrupt
* timer: timer on which interrupt is set
* time_us: reloading time in us
*/
void Timer_SetInterrupt(uint32_t timer, uint32_t time_us);
/*
* Timer_DisableInterrupt(): disables timer interrupt
* timer: timer on which interrupt is disabled
*/
void Timer_DisableInterrupt(uint32_t timer);
/*
* Timer_ClearInterrupt(): clear timer interrupt
* timer: timer on which interrupt needs to be cleared
*/
void Timer_ClearInterrupt(uint32_t timer);
/*
* Timer_GetIRQn(): returns IRQn of a Timer
* timer: timer on which IRQn is defined - 0 if it is not defined
*/
uint32_t Timer_GetIRQn(uint32_t timer);
/*
* Timer_GetTicksUS(): returns the number of Ticks per us
* timer: timer associated with the Ticks per us
* @return: Ticks per us - 0 if the timer is disables
*/
uint32_t Timer_GetTicksUS(uint32_t timer);
#ifdef __cplusplus
}
#endif
#endif /* _APB_TIMER_DRV_H */

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/* mbed Microcontroller Library
* Copyright (c) 2015-2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* A generic CMSIS include header, pulling in BEETLE SoC specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
/* Beetle Core */
#include "CMSDK_BEETLE.h"
/* Beetle System Core */
#include "system_CMSDK_BEETLE.h"
/* Beetle Core Config */
#include "system_core_beetle.h"
/* APB Dual Timer */
#include "apb_dualtimer.h"
/* APB Timer */
#include "apb_timer.h"
/* Cortex M3 SysTick Driver */
#include "systick_timer.h"
/* Flash Cache Driver */
#include "fcache_api.h"
/* Embedded Flash Driver */
#include "eflash_api.h"
/* NVIC Driver */
#include "cmsis_nvic.h"
/* System Core Version */
#include "system_core_version.h"
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2015-2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) //Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) //Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}

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/* mbed Microcontroller Library
* Copyright (c) 2015-2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "eflash_api.h"
/* EFlash Private Data */
typedef struct {
/* basebank0 start address */
unsigned int basebank0;
/* basebank0 mass erase + info pages address */
unsigned int basebank0_me;
/* basebank1 start address */
unsigned int basebank1;
/* basebank1 mass erase + info pages address */
unsigned int basebank1_me;
} eflash_t;
static eflash_t eflash;
/* EFlash_IdCheck: Detect the part number to see if device is present */
int EFlash_IdCheck()
{
unsigned int eflash_id;
eflash_id = readl(SYS_EFLASH_PIDR2) & (EFLASH_DES_1 | EFLASH_JEDEC);
if (readl(SYS_EFLASH_PIDR0) != FLS_PID0
|| readl(SYS_EFLASH_PIDR1) != FLS_PID1
|| eflash_id != FLS_PID2)
/* port ID and ARM ID does not match */
return 1;
else
return 0;
}
/* EFlash_ReturnBank1BaseAddress: Returns start address of bank 1 */
int EFlash_ReturnBank1BaseAddress()
{
unsigned int hwparams0;
int baseaddr;
hwparams0 = readl(SYS_EFLASH_HWPARAMS0) & EFLASH_FLASHSIZE;
switch(hwparams0)
{
case 0x11:
/* 128kb flash size - first page of bank 1 is 0x20000 */
baseaddr = 0x20000;
break;
case 0x12:
/* 256kb flash size - first page of bank 1 is 0x40000 */
baseaddr = 0x40000;
break;
default:
/* unsupported flash size */
baseaddr = -1;
break;
}
return baseaddr;
}
/* EFlash_Initialize: eFlash Initialize function */
void EFlash_Initialize()
{
/* Find the start address of banks */
eflash.basebank0 = 0x0;
eflash.basebank0_me = 0x40000000;
eflash.basebank1 = EFlash_ReturnBank1BaseAddress();
eflash.basebank1_me = 0x80000000;
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK);
/*
* Configure to use external clock
* EXTCL = 31250 ns ->
* 1 ms = 32 clock count 32khz ext_clk -> ER_CLK_COUNT = 32
* 1 us = 84 clock count system_clk -> WR_CLK_COUNT = 84
* EXT_CLK_CONF = 0x1 [Erase] External clock used for erase counters (>1ms)
* HCLK used for write counters
* RD_CLK_COUNT = 0x3
*/
writel(SYS_EFLASH_CONFIG0, 0x00200B43);
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY);
}
/*
* EFlash_Erase: Erases flash banks
* Mode:
* 0 - erases bank 0
* 1 - erases bank 1
* 2 - erases bank 0 + info pages
* 3 - erases bank 1 + info pages
* 4 - erases bank 0 + 1
* 5 - erases bank 0 + 1 with info pages
*/
void EFlash_Erase(int mode)
{
switch (mode)
{
case 0:
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #0 */
writel(SYS_EFLASH_WADDR, eflash.basebank0);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
break;
case 1:
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #1 */
writel(SYS_EFLASH_WADDR, eflash.basebank1);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
break;
case 2:
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #0 + info pages */
writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
break;
case 3:
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #1 + info pages */
writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
break;
case 4:
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #0 */
writel(SYS_EFLASH_WADDR, eflash.basebank0);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #1 */
writel(SYS_EFLASH_WADDR, eflash.basebank1);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller gets unlocked */
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
break;
case 5:
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #0 + info pages */
writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
/* Erase Block #1 + info pages */
writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
/* Wait until eFlash controller is not busy */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
break;
default:
break;
}
}
/* EFlash_ErasePage: Erase a Page */
void EFlash_ErasePage(unsigned int waddr)
{
/* Erase the page starting a waddr */
writel(SYS_EFLASH_WADDR, waddr);
writel(SYS_EFLASH_CTRL, EFLASH_ERASE);
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
}
/*
* EFlash_Write: Write function
* Parameters:
* waddr - address in flash
* data - data to be written
*/
void EFlash_Write(unsigned int waddr, unsigned int data)
{
/* Set Write Data Register */
writel(SYS_EFLASH_WDATA, data);
/* Set Write Address Register */
writel(SYS_EFLASH_WADDR, waddr);
/* Start Write Operation through CTRL register */
writel(SYS_EFLASH_CTRL, EFLASH_WRITE);
/* Wait until eFlash controller gets unlocked */
while ((readl(SYS_EFLASH_STATUS)
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
/* Flash Cache invalidate if FCache enabled */
if (FCache_isEnabled() == 1)
FCache_Invalidate();
}
/*
* EFlash_WritePage: Write Page function
* Parameters:
* waddr - address in flash
* page_size - data to be written
* buf - buffer containing the data
*/
int EFlash_WritePage(unsigned int waddr, unsigned int page_size,
unsigned char *buf)
{
unsigned int page_index;
unsigned int data;
/* To be verified */
for(page_index = 0; page_index < page_size; page_index = page_index + 4) {
/* Recreate the 32 bit word */
data = ((unsigned int) buf[page_index + 3]) << 24 |
((unsigned int) buf[page_index + 2]) << 16 |
((unsigned int) buf[page_index + 1]) << 8 |
((unsigned int) buf[page_index]);
/* Write the word in memory */
EFlash_Write(waddr, data);
waddr += 4;
}
return 0;
}
/*
* EFlash_Read: Read function
* Parameters:
* waddr - address in flash
* Returns:
* the vaule read at address waddr
*/
unsigned int EFlash_Read(unsigned int waddr)
{
unsigned int eflash_read = readl(waddr);
return eflash_read;
}
/*
* EFlash_Verify: Verifies if the eFlash has been written correctly.
* Parameters:
* waddr - address in flash
* page_size - data to be written
* buf - buffer containing the data
* Returns:
* (waddr+page_size) - OK or Failed Address
*/
unsigned int EFlash_Verify(unsigned int waddr, unsigned int page_size,
unsigned char *buf)
{
unsigned int page_index;
unsigned int eflash_data, buf_data;
/* To be verified */
for(page_index = 0; page_index < page_size; page_index = page_index + 4) {
/* Recreate the 32 bit word */
buf_data = ((unsigned int) buf[page_index + 3]) << 24 |
((unsigned int) buf[page_index + 2]) << 16 |
((unsigned int) buf[page_index + 1]) << 8 |
((unsigned int) buf[page_index]);
/* Read the word in memory */
eflash_data = EFlash_Read(waddr);
if (eflash_data != buf_data)
break;
waddr += 4;
}
/* Allign the address before return */
return (waddr);
}
/*
* EFlash_BlankCheck: Verifies if there is any Blank Block in eFlash
* Parameters:
* waddr - address in flash
* page_size - data to be written
* pat - pattern of a blank block
* Returns:
* 0 - OK or 1- Failed
*/
int EFlash_BlankCheck(unsigned int waddr, unsigned int page_size,
unsigned char pat)
{
unsigned int page_index;
unsigned int eflash_data, buf_data;
/* Page size div by 4 */
page_size = page_size >> 2;
/* To be verified */
for(page_index = 0; page_index < page_size; page_index = page_index + 4) {
/* Recreate the 32 bit word */
buf_data = ((unsigned int) pat) << 24 |
((unsigned int) pat) << 16 |
((unsigned int) pat) << 8 |
((unsigned int) pat);
/* Read the word in memory */
eflash_data = EFlash_Read(waddr);
if (eflash_data != buf_data)
return 1;
waddr += 4;
}
return 0;
}
/*
* Delay ns (uncalibrated delay)
*/
void EFlash_Delay(unsigned int period) {
int loop;
for (loop = 0; loop < period; loop++)
continue;
}

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/* mbed Microcontroller Library
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _EFLASH_DRV_H
#define _EFLASH_DRV_H
#include "fcache_api.h"
#ifdef __cplusplus
extern "C" {
#else
#include <stdio.h>
#endif
/* eFLASH Address Map */
#define SYS_EFLASH_BASE 0x40009000
#define SYS_EFLASH_IRQ_SET_STATUS (SYS_EFLASH_BASE + 0x008)
#define SYS_EFLASH_IRQ_CLR_STATUS (SYS_EFLASH_BASE + 0x008)
#define SYS_EFLASH_CTRL (SYS_EFLASH_BASE + 0x014)
#define SYS_EFLASH_STATUS (SYS_EFLASH_BASE + 0x018)
#define SYS_EFLASH_CONFIG0 (SYS_EFLASH_BASE + 0x01C)
#define SYS_EFLASH_WADDR (SYS_EFLASH_BASE + 0x028)
#define SYS_EFLASH_WDATA (SYS_EFLASH_BASE + 0x02C)
#define SYS_EFLASH_HWPARAMS0 (SYS_EFLASH_BASE + 0x034)
#define SYS_EFLASH_PIDR0 (SYS_EFLASH_BASE + 0xFE0)
#define SYS_EFLASH_PIDR1 (SYS_EFLASH_BASE + 0xFE4)
#define SYS_EFLASH_PIDR2 (SYS_EFLASH_BASE + 0xFE8)
/* SYS_EFLASH_CTRL (RW): Flash Control Register */
#define EFLASH_WRITE 1 /* Write one word on eFlash */
#define EFLASH_ROW_WRITE (1 << 1) /* Write a row of eFlash */
#define EFLASH_ERASE (1 << 2) /* Erase one page of eFlash */
#define EFLASH_MASS_ERASE (1 << 3) /* Erases all pages of the eFlash*/
#define EFLASH_STOP (1 << 4) /* Stop any write erase operation */
/* SYS_EFLASH_STATUS (RO): Status Register */
#define EFLASH_BUSY_MASK 1 /* EFlash Busy Mask */
#define EFLASH_BUSY 1 /* EFlash Busy */
#define EFLASH_LOCK_MASK (1 << 1) /* EFlash Lock Mask */
#define EFLASH_LOCK (1 << 1) /* EFlash Lock */
/* SYS_EFLASH_HWPARAMS0 (RO): HW parameters */
#define EFLASH_FLASHSIZE 0x1F /* Flash Size */
/* SYS_EFLASH_PIDR2 (RO): Flash Memory Information */
#define EFLASH_DES_1 0x7 /* JEP106 Id Mask */
#define EFLASH_JEDEC 0x8 /* JEDEC assigned val Mask */
#define EFLASH_REVISION 0xF0 /* Revision number */
/* Macros */
#define readl(reg) *(volatile unsigned int *)reg
#define writel(reg, val) *(unsigned int *)reg = val;
/* peripheral and component ID values */
#define FLS_PID4 0x14
#define FLS_PID5 0x00
#define FLS_PID6 0x00
#define FLS_PID7 0x00
#define FLS_PID0 0x30
#define FLS_PID1 0xB8
#define FLS_PID2 0x0B
#define FLS_PID3 0x00
#define FLS_CID0 0x0D
#define FLS_CID1 0xF0
#define FLS_CID2 0x05
#define FLS_CID3 0xB1
/* Functions */
/* EFlash_Initialize: eFlash Initialize function */
void EFlash_Initialize(void);
/*
* EFlash_Erase: Erases flash banks
* Mode:
* 0 - erases bank 0
* 1 - erases bank 1
* 2 - erases bank 0 + info pages
* 3 - erases bank 1 + info pages
* 4 - erases bank 0 + 1
* 5 - erases bank 0 + 1 with info pages
*/
void EFlash_Erase(int mode);
/* EFlash_ErasePage: Erase a Page */
void EFlash_ErasePage(unsigned int waddr);
/*
* EFlash_Write: Write function
* Parameters:
* waddr - address in flash
* data - data to be written
*/
void EFlash_Write(unsigned int waddr, unsigned int data);
/*
* EFlash_WritePage: Write Page function
* Parameters:
* waddr - address in flash
* page_size - data to be written
* buf - buffer containing the data
*/
int EFlash_WritePage(unsigned int waddr,
unsigned int page_size, unsigned char *buf);
/*
* EFlash_Read: Read function
* Parameters:
* waddr - address in flash
* Returns:
* the vaule read at address waddr
*/
unsigned int EFlash_Read(unsigned int waddr);
/*
* EFlash_Verify: Verifies if the eFlash has been written correctly.
* Parameters:
* waddr - address in flash
* page_size - data to be written
* buf - buffer containing the data
* Returns:
* (waddr+page_size) - OK or Failed Address
*/
unsigned int EFlash_Verify(unsigned int waddr,
unsigned int page_size, unsigned char *buf);
/*
* EFlash_BlankCheck: Verifies if there is any Blank Block in eFlash
* Parameters:
* waddr - address in flash
* page_size - data to be written
* pat - pattern of a blank block
* Returns:
* 0 - OK or 1- Failed
*/
int EFlash_BlankCheck(unsigned int waddr,
unsigned int page_size, unsigned char pat);
/* EFlash_Delay function */
void EFlash_Delay(unsigned int period);
/* EFlash_ReturnBank1BaseAddress: Returns start address of bank 1 */
int EFlash_ReturnBank1BaseAddress(void);
#ifdef __cplusplus
}
#endif
#endif /* _FCACHE_DRV_H */

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/* mbed Microcontroller Library
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "fcache_api.h"
static unsigned int enabled;
static unsigned int fcache_mode;
/* Functions */
/*
* FCache_Initialize: flash cache initialize funtion
*/
void FCache_Initialize()
{
unsigned int irqstat;
/* Clear interrupt status register */
irqstat = readl(SYS_FCACHE_IRQSTAT) & (FCACHE_POW_ERR | FCACHE_MAN_INV_ERR);
writel(SYS_FCACHE_IRQSTAT, irqstat);
/* Cache Disabled: Set enabled to 0 */
enabled = 0;
}
/*
* FCache_Enable: Enables the flash cache
* mode: supported modes:
* 0 - auto-power auto-invalidate
* 1 - manual-power, manual-invalidate
*/
void FCache_Enable(int mode)
{
/* Save Enable Mode */
fcache_mode = mode;
/* Enable the FCache */
switch (fcache_mode) {
case 0:
/* Statistic counters enabled, Cache enable,
* auto-inval, auto-power control
*/
writel(SYS_FCACHE_CCR, (FCACHE_EN | FCACHE_STATISTIC_EN));
/* Wait until the cache is enabled */
while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED);
/* Cache Enabled: Set enabled to 1 */
enabled = 1;
break;
case 1:
/*
* Statistic counters enabled, Cache disabled,
* Manual power request (Setting: Power CTRL:
* Manual, Invalidate: Manual)
*/
writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ
| FCACHE_SET_MAN_POW
| FCACHE_SET_MAN_INV
| FCACHE_STATISTIC_EN));
/* Wait until the cache rams are powered */
while ((readl(SYS_FCACHE_SR) & FCACHE_POW_STAT) != FCACHE_POW_STAT);
/* Statistic counters enabled, Cache enabled
* Manual invalidate request (Setting: Power CTRL:
* Manual, Invalidate: Manual)
*/
writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ
| FCACHE_POW_REQ
| FCACHE_SET_MAN_POW
| FCACHE_SET_MAN_INV
| FCACHE_STATISTIC_EN));
/* Wait until the cache is invalidated */
while ((readl(SYS_FCACHE_SR) & FCACHE_INV_STAT) == FCACHE_INV_STAT);
/* Statistic counters enabled, Cache enable,
* manual-inval, manual-power control
*/
writel(SYS_FCACHE_CCR, (FCACHE_EN
| FCACHE_POW_REQ
| FCACHE_SET_MAN_POW
| FCACHE_SET_MAN_INV
| FCACHE_STATISTIC_EN));
/* Wait until the cache is enabled */
while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED);
/* Cache Enabled: Set enabled to 1 */
enabled = 1;
break;
default:
break;
}
}
/*
* FCache_Disable: Disables the cache
*/
void FCache_Disable()
{
/* Disable the FCache */
switch (fcache_mode) {
case 0:
/* Statistic counters enabled, Cache disable,
* auto-inval, auto-power control
*/
writel(SYS_FCACHE_CCR, FCACHE_STATISTIC_EN);
/* Wait until the cache is disabled */
while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
/* Cache Enabled: Set enabled to 0 */
enabled = 0;
break;
case 1:
/* Statistic counters enabled, Cache disable,
* manual-inval, manual-power control
*/
writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ
| FCACHE_SET_MAN_POW
| FCACHE_SET_MAN_INV
| FCACHE_STATISTIC_EN));
/* Wait until the cache is disabled */
while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
/* Cache Enabled: Set enabled to 0 */
enabled = 0;
break;
default:
break;
}
}
/*
* FCache_Invalidate: to be invalidated the cache needs to be disabled.
* return -1: flash cannot be disabled
* -2: flash cannot be enabled
*/
int FCache_Invalidate()
{
/* Manual cache invalidate */
if (fcache_mode == 1)
{
/* Disable Flash Cache */
if (enabled == 1)
FCache_Disable();
else
goto error;
/* Trigger INV_REQ */
writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ
| FCACHE_POW_REQ
| FCACHE_SET_MAN_POW
| FCACHE_SET_MAN_INV
| FCACHE_STATISTIC_EN));
/* Wait until INV_REQ is finished */
while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
/* Clear Stats */
writel(SYS_FCACHE_CSHR, 0);
writel(SYS_FCACHE_CSMR, 0);
/* Enable Flash Cache */
if (enabled == 0)
FCache_Enable(1);
error:
if (enabled == 0)
return -1;
else
return -2;
}
return 0;
}
unsigned int * FCache_GetStats()
{
static unsigned int stats[2];
/* Cache Statistics HIT Register */
stats[0] = readl(SYS_FCACHE_CSHR);
/* Cache Statistics MISS Register */
stats[1] = readl(SYS_FCACHE_CSMR);
return stats;
}
/*
* FCache_isEnabled: returns 1 if FCache is enabled
*/
unsigned int FCache_isEnabled()
{
return enabled;
}

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/* mbed Microcontroller Library
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _FCACHE_DRV_H
#define _FCACHE_DRV_H
#ifdef __cplusplus
extern "C" {
#else
#include <stdio.h>
#endif
/* Flash Cache Address Map */
#define SYS_FCACHE_BASE 0x40003000
/* Configuration and Control Register */
#define SYS_FCACHE_CCR (SYS_FCACHE_BASE)
/* Status Register */
#define SYS_FCACHE_SR (SYS_FCACHE_BASE + 0x4)
/* Interrupt Req Status Register */
#define SYS_FCACHE_IRQSTAT (SYS_FCACHE_BASE + 0x8)
/* Cache Statistic Hit Register */
#define SYS_FCACHE_CSHR (SYS_FCACHE_BASE + 0x14)
/* Cache Statistic Miss Register */
#define SYS_FCACHE_CSMR (SYS_FCACHE_BASE + 0x18)
/* SYS_FCACHE_CCR (RW): Configuration and Control Register */
#define FCACHE_EN 1 /* FCache Enable */
#define FCACHE_INV_REQ (1 << 1) /* Manual Invalidate Request */
#define FCACHE_POW_REQ (1 << 2) /* Manual SRAM Power Request */
#define FCACHE_SET_MAN_POW (1 << 3) /* Power Control Setting */
#define FCACHE_SET_MAN_INV (1 << 4) /* Invalidate Control Setting */
#define FCACHE_SET_PREFETCH (1 << 5) /* Cache Prefetch Setting */
#define FCACHE_STATISTIC_EN (1 << 6) /* Enable Statistics Logic */
/* SYS_FCACHE_SR (RO): Status Register */
#define FCACHE_CS 0x3 /* Cache Status Mask */
#define FCACHE_CS_DISABLED 0x0
#define FCACHE_CS_ENABLING 0x1
#define FCACHE_CS_ENABLED 0x2
#define FCACHE_CS_DISABLING 0x3
#define FCACHE_INV_STAT 0x4 /* Invalidating Status */
#define FCACHE_POW_STAT 0x10 /* SRAM Power Ack */
/* SYS_FCACHE_IRQSTAT (RW): Interrupt Req Status Register */
#define FCACHE_POW_ERR 1 /* SRAM Power Error */
#define FCACHE_MAN_INV_ERR (1 << 1) /* Manual Invalidation error status */
/* Macros */
#define readl(reg) *(volatile unsigned int *)reg
#define writel(reg, val) *(unsigned int *)reg = val;
/* Functions */
/*
* FCache_Initialize: flash cache initialize funtion
*/
void FCache_Initialize(void);
/*
* FCache_Enable: Enables the flash cache
* mode: supported modes:
* 0 - auto-power auto-invalidate
* 1 - manual-power, manual-invalidate
*/
void FCache_Enable(int mode);
/*
* FCache_Disable: Disables the cache
*/
void FCache_Disable(void);
/*
* FCache_Invalidate: to be invalidated the cache needs to be disabled.
* return -1: flash cannot be disabled
* -2: flash cannot be enabled
*/
int FCache_Invalidate(void);
/*
* FCache_GetStats: provides cache stats
*/
unsigned int * FCache_GetStats(void);
/*
* FCache_isEnabled: returns 1 if FCache is enabled
*/
unsigned int FCache_isEnabled(void);
#ifdef __cplusplus
}
#endif
#endif /* _FCACHE_DRV_H */

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/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 system_ARMCM3.c
*/
#include "cmsis.h"
/*----------------------------------------------------------------------------
* Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (48000000UL) /* Oscillator frequency */
#define __SYSTEM_CLOCK (__XTAL / 2)
/*----------------------------------------------------------------------------
* Clock Variable definitions
*----------------------------------------------------------------------------*/
/* !< System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = __SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
* Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
// Enable AHB and APB clock
/* GPIO */
CMSDK_SYSCON->AHBCLKCFG0SET = 0xF;
/*
* Activate clock for: I2C1, SPI1, SPIO, QUADSPI, WDOG,
* I2C0, UART0, UART1, TIMER0, TIMER1, DUAL TIMER, TRNG
*/
CMSDK_SYSCON->APBCLKCFG0SET = SYSTEM_CORE_TIMER0
| SYSTEM_CORE_TIMER1
| SYSTEM_CORE_DUALTIMER0
| SYSTEM_CORE_UART0
| SYSTEM_CORE_UART1
| SYSTEM_CORE_I2C0
| SYSTEM_CORE_WDOG
| SYSTEM_CORE_QSPI
| SYSTEM_CORE_SPI0
| SYSTEM_CORE_SPI1
| SYSTEM_CORE_I2C1
| SYSTEM_CORE_TRNG;
/* Beetle System Core Config */
SystemCoreConfig();
}

59
hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.h Normal file
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/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 system_ARMCM3.h
*/
#ifndef SYSTEM_CMSDK_BEETLE_H
#define SYSTEM_CMSDK_BEETLE_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_BEETLE_H */

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/*
* PackageLicenseDeclared: Apache-2.0
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "CMSDK_BEETLE.h"
#include "system_core_beetle.h"
/*
* SystemCoreConfig(): Configure the System Core
*/
void SystemCoreConfig()
{
/* Set GPIO Alternate Functions */
CMSDK_GPIO0->ALTFUNCSET = (1<<0); /* Sheild 0 UART 0 RXD */
CMSDK_GPIO0->ALTFUNCSET |= (1<<1); /* Sheild 0 UART 0 TXD */
CMSDK_GPIO0->ALTFUNCSET |= (1<<14); /* Sheild 0 I2C SDA SBCON2 */
CMSDK_GPIO0->ALTFUNCSET |= (1<<15); /* Sheild 0 I2C SCL SBCON2 */
CMSDK_GPIO0->ALTFUNCSET |= (1<<10); /* Sheild 0 SPI_3 nCS */
CMSDK_GPIO0->ALTFUNCSET |= (1<<11); /* Sheild 0 SPI_3 MOSI */
CMSDK_GPIO0->ALTFUNCSET |= (1<<12); /* Sheild 0 SPI_3 MISO */
CMSDK_GPIO0->ALTFUNCSET |= (1<<13); /* Sheild 0 SPI_3 SCK */
CMSDK_GPIO1->ALTFUNCSET = (1<<0); /* UART 1 RXD */
CMSDK_GPIO1->ALTFUNCSET |= (1<<1); /* UART 1 TXD */
CMSDK_GPIO1->ALTFUNCSET |= (1<<6); /* Sheild 1 I2C SDA */
CMSDK_GPIO1->ALTFUNCSET |= (1<<7); /* Sheild 1 I2C SCL */
CMSDK_GPIO1->ALTFUNCSET |= (1<<2); /* ADC SPI_2 nCS */
CMSDK_GPIO1->ALTFUNCSET |= (1<<3); /* ADC SPI_2 MOSI */
CMSDK_GPIO1->ALTFUNCSET |= (1<<4); /* ADC SPI_2 MISO */
CMSDK_GPIO1->ALTFUNCSET |= (1<<5); /* ADC SPI_2 SCK */
CMSDK_GPIO1->ALTFUNCSET |= (1<<8); /* QSPI CS 2 */
CMSDK_GPIO1->ALTFUNCSET |= (1<<9); /* QSPI CS 1 */
CMSDK_GPIO1->ALTFUNCSET |= (1<<10); /* QSPI IO 0 */
CMSDK_GPIO1->ALTFUNCSET |= (1<<11); /* QSPI IO 1 */
CMSDK_GPIO1->ALTFUNCSET |= (1<<12); /* QSPI IO 2 */
CMSDK_GPIO1->ALTFUNCSET |= (1<<13); /* QSPI IO 3 */
CMSDK_GPIO1->ALTFUNCSET |= (1<<14); /* QSPI SCK */
/* Set the ARD_PWR_EN GPIO1[15] as an output */
CMSDK_GPIO1->OUTENABLESET |= (0x1 << 15);
/* Set on 3v3 (for ARDUINO HDR compliancy) */
CMSDK_GPIO1->DATA |= (0x1 << 15);
}
/* POWER MANAGEMENT */
/*
* SystemPowerConfig(): Configures the System Power Modes
*/
void SystemPowerConfig()
{
/* Configure APB Peripheral Clock in sleep state */
CMSDK_SYSCON->APBCLKCFG1SET = SYSTEM_CORE_TIMER0
| SYSTEM_CORE_TIMER1
| SYSTEM_CORE_DUALTIMER0
| SYSTEM_CORE_UART1
| SYSTEM_CORE_I2C0
| SYSTEM_CORE_QSPI
| SYSTEM_CORE_SPI0
| SYSTEM_CORE_SPI1
| SYSTEM_CORE_I2C1;
/* Configure APB Peripheral Clock in deep sleep state */
CMSDK_SYSCON->APBCLKCFG2SET = SYSTEM_CORE_TIMER0
| SYSTEM_CORE_TIMER1
| SYSTEM_CORE_DUALTIMER0
| SYSTEM_CORE_UART1
| SYSTEM_CORE_I2C0
| SYSTEM_CORE_QSPI
| SYSTEM_CORE_SPI0
| SYSTEM_CORE_SPI1
| SYSTEM_CORE_I2C1;
/* Configure Wakeup Sources */
CMSDK_SYSCON->PWRDNCFG1SET = SYSTEM_CORE_DUALTIMER0;
}
/*
* SystemPowerSuspend(): Enters in System Suspend
*/
void SystemPowerSuspend(power_mode_t mode)
{
if (mode == POWER_MODE_DEEP_SLEEP) {
/* Enable deepsleep */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Ensure effect of last store takes effect */
__DSB();
/* Enter sleep mode */
__WFI();
} else {
/* Enter sleep mode */
__WFI();
}
}
/*
* SystemPowerResume(): Returns from System Suspend
*/
void SystemPowerResume(power_mode_t mode)
{
if (mode == POWER_MODE_DEEP_SLEEP) {
/* Disable sleeponexit */
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
/* Ensure effect of last store takes effect */
__DSB();
}
}

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hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.h Normal file
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/*
* PackageLicenseDeclared: Apache-2.0
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_CORE_BEETLE_H
#define SYSTEM_CORE_BEETLE_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* SystemCoreConfig(): Configure the System Core
*/
void SystemCoreConfig(void);
/* POWER MANAGEMENT */
/* Power Mode Type Definition */
typedef enum {
/* Sleep Power Mode */
POWER_MODE_SLEEP = 0,
/* Deep Sleep Power Mode */
POWER_MODE_DEEP_SLEEP = 1
} power_mode_t;
/* APB System Core Clocks */
#define SYSTEM_CORE_TIMER0 (1 << 0)
#define SYSTEM_CORE_TIMER1 (1 << 1)
#define SYSTEM_CORE_DUALTIMER0 (1 << 2)
#define SYSTEM_CORE_UART0 (1 << 4)
#define SYSTEM_CORE_UART1 (1 << 5)
#define SYSTEM_CORE_I2C0 (1 << 7)
#define SYSTEM_CORE_WDOG (1 << 8)
#define SYSTEM_CORE_QSPI (1 << 11)
#define SYSTEM_CORE_SPI0 (1 << 12)
#define SYSTEM_CORE_SPI1 (1 << 13)
#define SYSTEM_CORE_I2C1 (1 << 14)
#define SYSTEM_CORE_TRNG (1 << 15) /* TRNG can not be a wakeup source */
/*
* SystemPowerConfig(): Configures the System Power Modes
*/
void SystemPowerConfig(void);
/*
* SystemPowerSuspend(): Enters in System Suspend
*/
void SystemPowerSuspend(power_mode_t mode);
/*
* SystemPowerResume(): Returns from System Suspend
*/
void SystemPowerResume(power_mode_t mode);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CORE_BEETLE_H */

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hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.c Normal file
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/*
* PackageLicenseDeclared: Apache-2.0
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <stdint.h>
#include "system_core_version.h"
#define REALLY_MAKE_STR(y) #y
#define MAKE_STR(x) REALLY_MAKE_STR(x)
#define SYSTEM_CORE_VERSION() (SYSTEM_CORE_PLATFORM ".SYSTEM.CORE." \
MAKE_STR(SYSTEM_CORE_OS) \
"." MAKE_STR(SYSTEM_CORE_VERSION_MAJOR) \
"." MAKE_STR(SYSTEM_CORE_VERSION_MINOR) \
"." MAKE_STR(SYSTEM_CORE_VERSION_PATCH) \
" " SYSTEM_CORE_DATE \
" " SYSTEM_CORE_TIME)
/* Private Data */
static uint32_t initialized = 0;
const char *system_core_version = SYSTEM_CORE_VERSION();
/* Get System Core Version */
const char* SystemCoreGetVersion()
{
return system_core_version;
}

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hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.h Normal file
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/*
* PackageLicenseDeclared: Apache-2.0
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_CORE_VERSION_H
#define SYSTEM_CORE_VERSION_H
#ifdef __cplusplus
extern "C" {
#endif
/* Platform Name */
#define SYSTEM_CORE_PLATFORM "ARM SSG BEETLE"
/* OS Version */
#define SYSTEM_CORE_OS 2
/* System Core Version */
#define SYSTEM_CORE_VERSION_MAJOR 0
#define SYSTEM_CORE_VERSION_MINOR 1
#define SYSTEM_CORE_VERSION_PATCH 0
#define SYSTEM_CORE_DATE __DATE__
#define SYSTEM_CORE_TIME __TIME__
/* Get System Core Version */
const char* SystemCoreGetVersion(void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CORE_VERSION_H */

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hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.c Normal file
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/*
* PackageLicenseDeclared: Apache-2.0
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "systick_timer.h"
volatile uint32_t MyTicks;
/* Private Data SysTick */
static uint32_t clock;
/*
* This Timer is written for MBED OS so the interrupt
* is used to keep track of the overflow.
*/
#define SYSTICK_MAX_RELOAD 0xFFFFFFFF
#define SYSTICK_DIVIDER_US (SystemCoreClock/1000000)
void SysTick_Handler(void)
{
MyTicks++;
#if 0
printf("System Tick Interrupt: %u\n\r", MyTicks);
#endif
}
/*
* SysTick_Initialize(): Initializes the SysTick timer
*/
void SysTick_Initialize(void)
{
clock = SYSTICK_MAX_RELOAD;
#if 0
printf("\n\rEnable System Tick Interrupt...\n\r");
#endif
MyTicks=0;
/* SysTick Reload Value Register */
SysTick->LOAD = clock;
/*
* SysTick_CTRL_CLKSOURCE_Msk : Use core's clock
* SysTick_CTRL_ENABLE_Msk : Enable SysTick
* SysTick_CTRL_TICKINT_Msk : Active the SysTick interrupt on the NVIC
*/
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk
| SysTick_CTRL_ENABLE_Msk
| SysTick_CTRL_TICKINT_Msk;
}
/*
* SysTick_Disable(): Disables the SysTick timer
*/
void SysTick_Disable(void)
{
/* Disable SysTick */
SysTick->CTRL = 0;
}
/*
* SysTick_Read(): Read SysTick Value
* @return: the SysTick VALUE
*/
uint32_t SysTick_Read(void)
{
return ((clock - (SysTick->VAL)) / SYSTICK_DIVIDER_US);
}
/*
* SysTick_Overflow(): Read SysTick Overflow Value
* @return: the SysTick Overflow VALUE
*/
uint32_t SysTick_Overflow(void)
{
return MyTicks;
}

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hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.h Normal file
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@ -0,0 +1,51 @@
/*
* PackageLicenseDeclared: Apache-2.0
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _SYSTICK_TIMER_H
#define _SYSTICK_TIMER_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* SysTick_Initialize(): Initializes the SysTick timer
*/
void SysTick_Initialize(void);
/*
* SysTick_Disable(): Disables the SysTick timer
*/
void SysTick_Disable(void);
/*
* SysTick_Read(): Read SysTick Value
* @return: the SysTick VALUE
*/
uint32_t SysTick_Read(void);
/*
* SysTick_Overflow(): Read SysTick Overflow Value
* @return: the SysTick Overflow VALUE
*/
uint32_t SysTick_Overflow(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTICK_TIMER_H */