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Merge pull request #4226 from Wiznet/master 

[WIZnet][W7500*] Support for mbed OS 5
pull/4322/head
Martin Kojtal 2017-05-15 16:00:23 +01:00 committed by GitHub
parent 7385a88017 34da12ace2
commit 444ff098fd
19 changed files with 1489 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S
View File

@ -188,8 +188,8 @@ Reset_Handler:
.LC3:
#endif /* __STARTUP_CLEAR_BSS */
/*bl _start*/
bl main
bl _start
//bl main
.pool
.size Reset_Handler, . - Reset_Handler

31
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf Normal file
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@ -0,0 +1,31 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x00000400;
define symbol __ICFEDIT_size_heap__ = 0x00000400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

305
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s Normal file
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@ -0,0 +1,305 @@
;/*******************************************************************************************************************************************************
; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;
; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;*********************************************************************************************************************************************************/
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device Series
; * @version V1.08
; * @date 23. November 2012
; *
; * @note
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Exterval Interrupts
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK SSP0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SSP0_Handler
B SSP0_Handler
PUBWEAK SSP1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SSP1_Handler
B SSP1_Handler
PUBWEAK UART0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_Handler
B UART0_Handler
PUBWEAK UART1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART1_Handler
B UART1_Handler
PUBWEAK UART2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART2_Handler
B UART2_Handler
PUBWEAK I2C0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C0_Handler
B I2C0_Handler
PUBWEAK I2C1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_Handler
B I2C1_Handler
PUBWEAK PORT0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_Handler
B PORT0_Handler
PUBWEAK PORT1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_Handler
B PORT1_Handler
PUBWEAK PORT2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_Handler
B PORT2_Handler
PUBWEAK PORT3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_Handler
B PORT3_Handler
PUBWEAK DMA_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA_Handler
B DMA_Handler
PUBWEAK DUALTIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER0_Handler
B DUALTIMER0_Handler
PUBWEAK DUALTIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER1_Handler
B DUALTIMER1_Handler
PUBWEAK PWM0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM0_Handler
B PWM0_Handler
PUBWEAK PWM1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM1_Handler
B PWM1_Handler
PUBWEAK PWM2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM2_Handler
B PWM2_Handler
PUBWEAK PWM3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM3_Handler
B PWM3_Handler
PUBWEAK PWM4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM4_Handler
B PWM4_Handler
PUBWEAK PWM5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM5_Handler
B PWM5_Handler
PUBWEAK PWM6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM6_Handler
B PWM6_Handler
PUBWEAK PWM7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM7_Handler
B PWM7_Handler
PUBWEAK RTC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Handler
B RTC_Handler
PUBWEAK ADC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_Handler
B ADC_Handler
PUBWEAK WZTOE_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
WZTOE_Handler
B WZTOE_Handler
PUBWEAK EXTI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI_Handler
B EXTI_Handler
END

4
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S
View File

@ -188,8 +188,8 @@ Reset_Handler:
.LC3:
#endif /* __STARTUP_CLEAR_BSS */
/*bl _start*/
bl main
bl _start
//bl main
.pool
.size Reset_Handler, . - Reset_Handler

BIN
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.o
View File

Binary file not shown.

31
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf Normal file
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@ -0,0 +1,31 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x00000400;
define symbol __ICFEDIT_size_heap__ = 0x00000400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

305
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s Normal file
View File

@ -0,0 +1,305 @@
;/*******************************************************************************************************************************************************
; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;
; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;*********************************************************************************************************************************************************/
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device Series
; * @version V1.08
; * @date 23. November 2012
; *
; * @note
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Exterval Interrupts
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK SSP0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SSP0_Handler
B SSP0_Handler
PUBWEAK SSP1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SSP1_Handler
B SSP1_Handler
PUBWEAK UART0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_Handler
B UART0_Handler
PUBWEAK UART1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART1_Handler
B UART1_Handler
PUBWEAK UART2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART2_Handler
B UART2_Handler
PUBWEAK I2C0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C0_Handler
B I2C0_Handler
PUBWEAK I2C1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_Handler
B I2C1_Handler
PUBWEAK PORT0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_Handler
B PORT0_Handler
PUBWEAK PORT1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_Handler
B PORT1_Handler
PUBWEAK PORT2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_Handler
B PORT2_Handler
PUBWEAK PORT3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_Handler
B PORT3_Handler
PUBWEAK DMA_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA_Handler
B DMA_Handler
PUBWEAK DUALTIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER0_Handler
B DUALTIMER0_Handler
PUBWEAK DUALTIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER1_Handler
B DUALTIMER1_Handler
PUBWEAK PWM0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM0_Handler
B PWM0_Handler
PUBWEAK PWM1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM1_Handler
B PWM1_Handler
PUBWEAK PWM2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM2_Handler
B PWM2_Handler
PUBWEAK PWM3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM3_Handler
B PWM3_Handler
PUBWEAK PWM4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM4_Handler
B PWM4_Handler
PUBWEAK PWM5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM5_Handler
B PWM5_Handler
PUBWEAK PWM6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM6_Handler
B PWM6_Handler
PUBWEAK PWM7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM7_Handler
B PWM7_Handler
PUBWEAK RTC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Handler
B RTC_Handler
PUBWEAK ADC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_Handler
B ADC_Handler
PUBWEAK WZTOE_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
WZTOE_Handler
B WZTOE_Handler
PUBWEAK EXTI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI_Handler
B EXTI_Handler
END

4
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S
View File

@ -188,8 +188,8 @@ Reset_Handler:
.LC3:
#endif /* __STARTUP_CLEAR_BSS */
/*bl _start*/
bl main
bl _start
//bl main
.pool
.size Reset_Handler, . - Reset_Handler

31
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf Normal file
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@ -0,0 +1,31 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x00000400;
define symbol __ICFEDIT_size_heap__ = 0x00000400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

305
targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s Normal file
View File

@ -0,0 +1,305 @@
;/*******************************************************************************************************************************************************
; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;
; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;*********************************************************************************************************************************************************/
;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device Series
; * @version V1.08
; * @date 23. November 2012
; *
; * @note
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Exterval Interrupts
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK SSP0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SSP0_Handler
B SSP0_Handler
PUBWEAK SSP1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SSP1_Handler
B SSP1_Handler
PUBWEAK UART0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_Handler
B UART0_Handler
PUBWEAK UART1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART1_Handler
B UART1_Handler
PUBWEAK UART2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART2_Handler
B UART2_Handler
PUBWEAK I2C0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C0_Handler
B I2C0_Handler
PUBWEAK I2C1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_Handler
B I2C1_Handler
PUBWEAK PORT0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_Handler
B PORT0_Handler
PUBWEAK PORT1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_Handler
B PORT1_Handler
PUBWEAK PORT2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_Handler
B PORT2_Handler
PUBWEAK PORT3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_Handler
B PORT3_Handler
PUBWEAK DMA_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA_Handler
B DMA_Handler
PUBWEAK DUALTIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER0_Handler
B DUALTIMER0_Handler
PUBWEAK DUALTIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER1_Handler
B DUALTIMER1_Handler
PUBWEAK PWM0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM0_Handler
B PWM0_Handler
PUBWEAK PWM1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM1_Handler
B PWM1_Handler
PUBWEAK PWM2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM2_Handler
B PWM2_Handler
PUBWEAK PWM3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM3_Handler
B PWM3_Handler
PUBWEAK PWM4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM4_Handler
B PWM4_Handler
PUBWEAK PWM5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM5_Handler
B PWM5_Handler
PUBWEAK PWM6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM6_Handler
B PWM6_Handler
PUBWEAK PWM7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM7_Handler
B PWM7_Handler
PUBWEAK RTC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Handler
B RTC_Handler
PUBWEAK ADC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_Handler
B ADC_Handler
PUBWEAK WZTOE_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
WZTOE_Handler
B WZTOE_Handler
PUBWEAK EXTI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI_Handler
B EXTI_Handler
END

15
targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c
View File

@ -36,20 +36,21 @@ uint8_t ADC_IsInterrupt (void)
void ADC_InterruptClear (void)
{
ADC->ADC_INT = ADC_INTCLEAR;
ADC->ADC_INT = ADC_INTCLEAR;
}
void ADC_Init (void)
{
// ADC_CLK on
ADC_PowerDownEnable(DISABLE);
//ADC_ChannelSelect(num);
// ADC_CLK on
ADC_PowerDownEnable(ENABLE);
ADC_PowerDownEnable(DISABLE);
//ADC_ChannelSelect(num);
}
void ADC_DeInit (void)
{
// ADC_CLK off
ADC_PowerDownEnable(ENABLE);
ADC_InterruptMask(DISABLE);
// ADC_CLK off
ADC_PowerDownEnable(ENABLE);
ADC_InterruptMask(DISABLE);
}

22
targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.c
View File

@ -67,6 +67,8 @@ void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
// assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
GPIOx->INTTYPESET = 0x00FF;
if (GPIOx == GPIOA) px_pcr = PA_PCR;
else if (GPIOx == GPIOB) px_pcr = PB_PCR;
else if (GPIOx == GPIOC) px_pcr = PC_PCR;
@ -260,26 +262,30 @@ void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF)
if(Px == PAD_PA)
{
assert_param(IS_PA_NUM(i));
PA_AFSR->Port[i] &= ~(0x03ul);
PA_AFSR->Port[i] |= P_AF;
//PA_AFSR->Port[i] &= ~(0x03ul);
//PA_AFSR->Port[i] |= P_AF;
PA_AFSR->Port[i] = P_AF;
}
else if(Px == PAD_PB)
{
assert_param(IS_PB_NUM(i));
PB_AFSR->Port[i] &= ~(0x03ul);
PB_AFSR->Port[i] |= P_AF;
//PB_AFSR->Port[i] &= ~(0x03ul);
//PB_AFSR->Port[i] |= P_AF;
PB_AFSR->Port[i] = P_AF;
}
else if(Px == PAD_PC)
{
assert_param(IS_PC_NUM(i));
PC_AFSR->Port[i] &= ~(0x03ul);
PC_AFSR->Port[i] |= P_AF;
//PC_AFSR->Port[i] &= ~(0x03ul);
//PC_AFSR->Port[i] |= P_AF;
PC_AFSR->Port[i] = P_AF;
}
else
{
assert_param(IS_PD_NUM(i));
PD_AFSR->Port[i] &= ~(0x03ul);
PD_AFSR->Port[i] |= P_AF;
//PD_AFSR->Port[i] &= ~(0x03ul);
//PD_AFSR->Port[i] |= P_AF;
PD_AFSR->Port[i] = P_AF;
}
}
}

338
targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c
View File

@ -1,21 +1,59 @@
/*******************************************************************************************************************************************************
* Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
* to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*********************************************************************************************************************************************************/
/**
******************************************************************************
* @file W7500x_uart.c
* @author
* @version
* @date
* @brief
* @file W7500x_stdPeriph_Driver/src/W7500x_uart.c
* @author IOP Team
* @version v1.0.0
* @date 01-May-2015
* @brief This file contains all the functions prototypes for the uart
* firmware library.
******************************************************************************
* @attention
*
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
#include "W7500x_uart.h"
/** @addtogroup W7500x_Periph_Driver
* @{
*/
/** @defgroup UART
* @brief UART driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup UART_Private_Functions
* @{
*/
/**
* @brief Fills each UART_InitStruct member with its default value.
* @param UART_StructInit: pointer to a UART_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
{
/* UART_InitStruct members default value */
@ -24,20 +62,34 @@ void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
UART_InitStruct->UART_StopBits = UART_StopBits_1;
UART_InitStruct->UART_Parity = UART_Parity_No ;
UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ;
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ;
}
/* Function check */
/* This function is checking now. Update or remove maybe. */
//Why be????
void UART_DeInit(UART_TypeDef *UARTx)
{
}
/**
* @brief Initializes the UART peripheral according to the specified
* parameters in the UART_InitStruct .
* @param UARTx: where x can be 1, 2 or 3
* @param UART_InitStruct: pointer to a UART_InitTypeDef structure that contains
* the configuration information for the specified UART peripheral.
* @retval None
*/
uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct)
{
float baud_divisor;
uint32_t tmpreg=0x00, uartclock=0x00;
uint32_t integer_baud = 0x00, fractional_baud = 0x00;
float baud_divisor;
uint32_t tmpreg=0x00, uartclock=0x00;
uint32_t integer_baud = 0x00, fractional_baud = 0x00;
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength));
assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
@ -45,53 +97,101 @@ uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct)
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl));
assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode));
/* Write to UART CR */
UARTx->CR &= ~(UART_CR_UARTEN);
UARTx->CR &= ~(UART_CR_UARTEN);
/* Set baudrate */
/* CRG_UARTCLK_SSR_RCLK: Set UART Clock using internal Oscilator ( 8MHz ) */
/* CRG_UARTCLK_SSR_OCLK: Set UART Clock using external Oscilator */
CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz )
//CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK; // Set UART Clock using external Oscilator
// Set baudrate
CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz )
uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR);
/* Set uartclock */
uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR);
/*----------------------------- UARTx IBRD and FBRD Configuration ------------------------------*/
baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate));
integer_baud = (uint32_t)baud_divisor;
fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5);
baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate));
integer_baud = (uint32_t)baud_divisor;
fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5);
UARTx->IBRD = integer_baud;
UARTx->FBRD = fractional_baud;
UARTx->IBRD = integer_baud;
UARTx->FBRD = fractional_baud;
tmpreg = UARTx->LCR_H;
tmpreg &= ~(0x00EE);
tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity);
UARTx->LCR_H |= tmpreg;
UARTx->LCR_H = tmpreg;
tmpreg = UARTx->CR;
tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN);
tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl);
UARTx->CR |= tmpreg;
UARTx->CR = tmpreg;
/* Debug */
/* UARTx->LCR_H |=0x10; */
/* UARTx->IFLS | = 0x00; */
UARTx->CR |= UART_CR_UARTEN;
return 0;
}
/**
* @brief UART_FIFO_Enable
* @param case rx_fifo_level=0: 1/8 full, case rx_fifo_level=1: 1/4 full, case rx_fifo_level=2: 1/2 full,
* case rx_fifo_level=3: 3/4 full, case rx_fifo_level=4: 7/8 full
* @param case tx_fifo_level=0: 1/8 full, case tx_fifo_level=1: 1/4 full, case tx_fifo_level=2: 1/2 full,
* case tx_fifo_level=3: 3/4 full, case tx_fifo_level=4: 7/8 full
* @retval None
*/
void UART_FIFO_Enable(UART_TypeDef *UARTx, uint16_t rx_fifo_level, uint16_t tx_fifo_level)
{
UARTx->LCR_H |= UART_LCR_H_FEN;
UARTx->IFLS = (UART_IFLS_RXIFLSEL(rx_fifo_level) | UART_IFLS_TXIFLSEL(tx_fifo_level));
}
/**
* @brief UART_FIFO_Disable
* @param UARTx: Define structure at "W7500x.h"
* @retval None
*/
void UART_FIFO_Disable(UART_TypeDef *UARTx)
{
UARTx->LCR_H &= ~(UART_LCR_H_FEN);
}
/**
* @brief UART_SendData
* @param UARTx: Define structure at "W7500x.h"
* @param Data: Unsigned short value
* @retval None
*/
void UART_SendData(UART_TypeDef* UARTx, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
UARTx->DR = Data;
}
/**
* @brief UART_ReceiveData
* @param UARTx: Define structure at "W7500x.h"
* @retval None
*/
uint16_t UART_ReceiveData(UART_TypeDef* UARTx)
{
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
return (uint16_t)(UARTx->DR);
}
/**
* @brief UART_SendBreak
* @param UARTx: Define structure at "W7500x.h"
* @retval None
*/
void UART_SendBreak(UART_TypeDef* UARTx)
{
assert_param(IS_UART_01_PERIPH(UARTx));
@ -99,11 +199,17 @@ void UART_SendBreak(UART_TypeDef* UARTx)
UARTx->LCR_H |= UART_LCR_H_BRK;
}
/**
* @brief UART_GetRecvStatus
* @param UARTx: Define structure at "W7500x.h"
* @param UART_RECV_STATUS
* @retval bitstatus
*/
FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
@ -119,29 +225,44 @@ FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
return bitstatus;
}
/**
* @brief UART_ClearRecvStatus
* @param UARTx: Define structure at "W7500x.h"
* @param UART_RECV_STATUS
* @retval None
*/
void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
{
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
/* Set STATUS.ECR*/
UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS;
}
/**
* @brief UART_GetFlagStatus
* @param UARTx: Define structure at "W7500x.h"
* @param UART_FLAG
* @retval bitstatus
*/
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_FLAG(UART_FLAG));
if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET)
{
/* bitstatus setting to SET*/
bitstatus = SET;
}
else
{
/*bitstatus setting to RESET*/
bitstatus = RESET;
}
@ -149,109 +270,194 @@ FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
}
/*
/* Function check */
/* This function is checking now. Update or remove maybe. */
//Why be?
void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
}
*/
/**
* @brief UART_ITConfig
* @param UARTx: Define structure at "W7500x.h"
* @param UART_IT
* @param NewState
* @retval None
*/
void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
if ( NewState != DISABLE )
{
/*Set the IMSC*/
UARTx->IMSC |= UART_IT;
}
else
{
/*Set the ICR*/
UARTx->ICR |= UART_IT;
}
}
/**
* @brief UART_GetITStatus
* @param UARTx: Define structure at "W7500x.h"
* @param UART_IT
* @param bitstatus
* @retval None
*/
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
if ((UARTx->MIS & UART_IT) != (uint16_t)RESET)
{
/*Set bitstatus = SET */
bitstatus = SET;
}
else
{
/*Set bitstatus = RESET */
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief UART_ITPendingBit
* @param UARTx: Define structure at "W7500x.h"
* @param UART_IT
* @retval None
*/
void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT)
{
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
/* Set ICR */
UARTx->ICR |= UART_IT;
}
/**
* @brief UART_DMA_Config
* @param UARTx: Define structure at "W7500x.h"
* @param UART_DMA_CONTROL
* @retval None
*/
void UART_DMA_Config(UART_TypeDef* UARTx, uint16_t UART_DMA_CONTROL)
{
/* Check the parameters */
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_DMA_CONTROL(UART_DMA_CONTROL));
/*Set DMACR */
UARTx->DMACR |= UART_DMA_CONTROL;
}
/* Function check */
/* This function is checking now. Update or remove maybe. */
//Why be?
void S_UART_DeInit()
{
}
/**
* @brief S_UART_Init
* @param baud
* @retval None
*/
uint32_t S_UART_Init(uint32_t baud)
{
uint32_t tmpreg=0x00;
S_UART_SetBaud(baud);
/* Set temp register for UART2 CTRL */
tmpreg = UART2->CTRL;
tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
/* Write to UART2 CTRL */
UART2->CTRL = tmpreg;
return 0;
}
/**
* @brief S_UART_SetBaud
* @param baud
* @retval None
*/
void S_UART_SetBaud(uint32_t baud)
{
uint32_t uartclock = 0x00, integer_baud = 0x00;
/* Check the parameters */
assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode));
if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK)
{
uartclock = INTERN_XTAL;
/* Set uartclock: INTERN_XTAL */
uartclock = INTERN_XTAL;
}
else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK)
{
/* Set uartclock: EXTERN_XTAL */
uartclock = EXTERN_XTAL;
}
else
{
/* Set uartclock: GetSystemClock */
uartclock = GetSystemClock();
}
/* Set (Calculate) integer_baud */
integer_baud = (uint32_t)(uartclock / baud);
/* Write UART2 BAUDDIV */
UART2->BAUDDIV = integer_baud;
}
/**
* @brief S_UART_SendData
* @param Data
* @retval None
*/
void S_UART_SendData(uint16_t Data)
{
while(UART2->STATE & S_UART_STATE_TX_BUF_FULL);
/* Write UART2 DATA */
UART2->DATA = Data;
}
/**
* @brief S_UART_ReceiveData
* @retval UART2 DATA
*/
uint16_t S_UART_ReceiveData()
{
return (uint16_t)(UART2->DATA);
}
/**
* @brief S_UART_GetFlagStatus
* @param UART_STATE
* @retval bitstatus
*/
FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_STATE)
{
FlagStatus bitstatus = RESET;
@ -270,6 +476,13 @@ FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_STATE)
return bitstatus;
}
/**
* @brief S_UART_SetCTRL
* @param S_UART_CTRL
* @param NewState
* @retval None
*/
void S_UART_SetCTRL(uint16_t S_UART_CTRL, FunctionalState NewState)
{
if ( NewState != DISABLE )
@ -283,49 +496,77 @@ void S_UART_SetCTRL(uint16_t S_UART_CTRL, FunctionalState NewState)
}
/**
* @brief S_UART_ITConfig
* @param S_UART_CTRL
* @param NewState
* @retval None
*/
void S_UART_ITConfig(uint16_t S_UART_CTRL, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_S_UART_CTRL_FLAG(S_UART_CTRL));
if ( NewState != DISABLE )
{
/* Set UART2 CTRL: S_UART_CTRL */
UART2->CTRL |= S_UART_CTRL;
}
else
{
/*Set UART2 CTRL: ~S_UART_CTRL */
UART2->CTRL &= ~(S_UART_CTRL);
}
}
/**
* @brief S_UART_GetTStatus
* @param S_UART_INTSTATUS
* @retval bitstatus
*/
ITStatus S_UART_GetITStatus(uint16_t S_UART_INTSTATUS)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS));
if ((UART2->INT.STATUS & (S_UART_INTSTATUS)) != (uint16_t) RESET)
{
/* Set bitstatus: SET */
bitstatus = SET;
}
else
{
/* Set bitstatus: RESET */
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief S_UART_ClearITPendingBit
* @param S_UART_INTSTATUS
* @retval None
*/
void S_UART_ClearITPendingBit(uint16_t S_UART_INTSTATUS)
{
/* Check the parameters */
assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS));
/* Write UART2 INT.CLEAR: S_UART_INSTATUS */
UART2->INT.CLEAR |= (S_UART_INTSTATUS);
}
/**************************************************/
// It will be moved to application board's driver */
/**************************************************/
uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch)
{
UART_SendData(UARTx,ch);
@ -335,6 +576,8 @@ uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch)
return (ch);
}
void UartPuts(UART_TypeDef* UARTx, uint8_t *str)
{
uint8_t ch;
@ -349,6 +592,7 @@ void UartPuts(UART_TypeDef* UARTx, uint8_t *str)
}while(ch != 0);
}
uint8_t UartGetc(UART_TypeDef* UARTx)
{
while(UARTx->FR & UART_FR_RXFE);
@ -364,6 +608,8 @@ uint8_t S_UartPutc(uint8_t ch)
return (ch);
}
void S_UartPuts(uint8_t *str)
{
uint8_t ch;
@ -378,6 +624,7 @@ void S_UartPuts(uint8_t *str)
}while(ch != 0);
}
uint8_t S_UartGetc()
{
while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 );
@ -385,3 +632,16 @@ uint8_t S_UartGetc()
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

61
targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h
View File

@ -1,9 +1,22 @@
/*******************************************************************************************************************************************************
* Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
* to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*********************************************************************************************************************************************************/
/**
******************************************************************************
* @file
* @author
* @version
* @date
* @file W7500x_stdPeriph_Driver/inc/W7500x_uart.h
* @author IOP Team
* @version V1.0.0
* @date 01-May-2015
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
@ -23,6 +36,15 @@
#include "W7500x.h"
/** @addtogroup W7500x_Periph_Driver
* @{
*/
/** @addtogroup UART
* @{
*/
/**
* @brief UART Init Structure definition
*/
@ -108,7 +130,8 @@ typedef struct
#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE))
#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE))
#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \
((MODE) == UART_Mode_Tx))
((MODE) == UART_Mode_Tx) || \
((MODE) == (UART_Mode_Rx | UART_Mode_Tx)))
/**
* @}
@ -133,6 +156,22 @@ typedef struct
*/
/** @addtogroup UART_DMA_Control
* @{
*/
#define UART_DMAControl_DMAONERR ((uint16_t)UART_DMACR_DMAONERR)
#define UART_DMAControl_RXDMAE ((uint16_t)UART_DMACR_TXDMAE)
#define UART_DMAControl_TXDMAE ((uint16_t)UART_DMACR_RXDMAE)
#define IS_UART_DMA_CONTROL(CONTROL) \
(((CONTROL) == UART_DMAControl_DMAONERR) || \
((CONTROL) == UART_DMAControl_TXDMAE) || \
((CONTROL) == UART_DMAControl_RXDMAE))
/**
* @}
*/
/** @addtogroup UART_Receive Status
* @{
*/
@ -183,7 +222,7 @@ typedef struct
#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */
#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */
#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */
#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */
#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */
#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */
#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */
#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */
@ -273,6 +312,8 @@ typedef struct
void UART_StructInit (UART_InitTypeDef* UART_InitStruct);
uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_FIFO_Enable (UART_TypeDef *UARTx, uint16_t rx_fifo_level, uint16_t tx_fifo_level);
void UART_FIFO_Disable (UART_TypeDef *UARTx);
void UART_SendData (UART_TypeDef* UARTx, uint16_t Data);
uint16_t UART_ReceiveData (UART_TypeDef* UARTx);
void UART_SendBreak (UART_TypeDef* UARTx);
@ -281,6 +322,7 @@ FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG);
void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState);
ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT);
void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT);
void UART_DMA_Config(UART_TypeDef* UARTx, uint16_t UART_DMA_CONTROL);
uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch);
void UartPuts (UART_TypeDef* UARTx, uint8_t *str);
@ -311,3 +353,10 @@ void S_UART_ClearITPendingBit(uint16_t S_UART_IT);
#endif // __W7500X_UART_H
/**
* @}
*/
/**
* @}
*/

10
targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c
View File

@ -42,8 +42,6 @@
ADC_TypeDef * AdcHandle;
static int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin)
{
// Get the peripheral name from the pin and assign it to the object
@ -57,12 +55,8 @@ void analogin_init(analogin_t *obj, PinName pin)
// Save pin number for the read function
obj->pin = pin;
// The ADC initialization is done once
if (adc_inited == 0) {
adc_inited = 1;
ADC_Init();
}
// The ADC initialization
ADC_Init();
}
static inline uint16_t adc_read(analogin_t *obj)

14
targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c
View File

@ -43,6 +43,7 @@ static gpio_irq_handler irq_handler;
static uint32_t channel_ids[4][16];
#ifdef __cplusplus
extern "C"{
#endif
@ -50,6 +51,7 @@ void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num);
void PORT0_Handler(void)
{
NVIC_ClearPendingIRQ(PORT0_IRQn);
port_generic_handler(GPIOA, 0);
}
@ -99,6 +101,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
obj->pin_num = WIZ_PIN_NUM(pin);
obj->pin_index = WIZ_PIN_INDEX(pin);
//gpio_irq_disable(obj);
if (pin == NC) return -1;
if(obj->port_num == 0)
@ -110,10 +114,11 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
else
obj->irq_n = PORT3_IRQn;
//obj->event = EDGE_FALL;
obj->pin = pin;
obj->event = EDGE_NONE;
// Enable EXTI interrupt
NVIC_ClearPendingIRQ(obj->irq_n);
NVIC_EnableIRQ(obj->irq_n);
channel_ids[obj->port_num][obj->pin_num] = id;
@ -141,10 +146,13 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
obj->rise_null = 0;
}
else if (event == IRQ_FALL) {
gpio->INTPOLSET &= ~obj->pin_index;
gpio->INTPOLCLR |= obj->pin_index;
obj->event = EDGE_FALL;
obj->fall_null = 0;
}
gpio->INTENCLR |= obj->pin_index;
gpio->INTTYPESET |= obj->pin_index;
gpio->INTENSET |= obj->pin_index;

14
targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c
View File

@ -117,17 +117,29 @@ void pin_mode(PinName pin, PinMode pupd)
uint32_t port_num = WIZ_PORT(pin);
uint32_t pin_num = WIZ_PIN_NUM(pin);
switch(port_num) {
switch(port_num) {
case PortA:
if(pupd != 0) {
PA_PCR->Port[pin_num] &= 0xFFFFFFFC;
}
PA_PCR->Port[pin_num] |= pupd;
break;
case PortB:
if(pupd != 0) {
PB_PCR->Port[pin_num] &= 0xFFFFFFFC;
}
PB_PCR->Port[pin_num] |= pupd;
break;
case PortC:
if(pupd != 0) {
PC_PCR->Port[pin_num] &= 0xFFFFFFFC;
}
PC_PCR->Port[pin_num] |= pupd;
break;
case PortD:
if(pupd != 0) {
PD_PCR->Port[pin_num] &= 0xFFFFFFFC;
}
PD_PCR->Port[pin_num] |= pupd;
break;
default:

67
targets/TARGET_WIZNET/mbed_rtx.h Normal file
View File

@ -0,0 +1,67 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_MBED_RTX_H
#define MBED_MBED_RTX_H
#if defined(TARGET_WIZWIKI_W7500)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20004000UL)
#endif
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 128
#endif
#ifndef OS_CLOCK
#define OS_CLOCK 20000000
#endif
#elif defined(TARGET_WIZWIKI_W7500P)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20004000UL)
#endif
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 128
#endif
#ifndef OS_CLOCK
#define OS_CLOCK 20000000
#endif
#elif defined(TARGET_WIZWIKI_W7500ECO)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20004000UL)
#endif
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 128
#endif
#ifndef OS_CLOCK
#define OS_CLOCK 20000000
#endif
#endif //
#endif // MBED_MBED_RTX_H

12
targets/targets.json
View File

@ -2449,27 +2449,27 @@
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M0",
"extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
"supported_toolchains": ["uARM", "ARM"],
"supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2"]
"release_versions": ["2", "5"]
},
"WIZWIKI_W7500P": {
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M0",
"extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
"supported_toolchains": ["uARM", "ARM"],
"supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2"]
"release_versions": ["2", "5"]
},
"WIZWIKI_W7500ECO": {
"inherits": ["Target"],
"core": "Cortex-M0",
"extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
"supported_toolchains": ["uARM", "ARM"],
"supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2"]
"release_versions": ["2", "5"]
},
"SAMR21G18A": {
"inherits": ["Target"],