mirror of https://github.com/ARMmbed/mbed-os.git
MXRT1050: Add support for Flash driver
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>pull/12317/head
Mahesh Mahadevan
parent
e46e48249a
commit
42a90cc8b0
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@ -0,0 +1,374 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2019 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "flash_api.h"
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#include "mbed_toolchain.h"
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#include "mbed_critical.h"
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#if DEVICE_FLASH
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#include "fsl_flexspi.h"
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#include "fsl_cache.h"
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#include "flash_defines.h"
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AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void));
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr));
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_wait_bus_busy_ram(void));
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_erase_sector_ram(uint32_t address));
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AT_QUICKACCESS_SECTION_CODE(static void flexspi_lower_clock_ram(void));
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AT_QUICKACCESS_SECTION_CODE(static void flexspi_clock_update_ram(void));
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t address,
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const uint32_t *src,
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uint32_t size));
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AT_QUICKACCESS_SECTION_CODE(void flexspi_nor_flash_read_data_ram(uint32_t addr,
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uint32_t *buffer,
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uint32_t size));
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void flexspi_update_lut_ram(void)
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{
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flexspi_config_t config;
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memset(&config, 0, sizeof(config));
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/*Get FLEXSPI default settings and configure the flexspi. */
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FLEXSPI_GetDefaultConfig(&config);
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/*Set AHB buffer size for reading data through AHB bus. */
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config.ahbConfig.enableAHBPrefetch = true;
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/*Allow AHB read start address do not follow the alignment requirement. */
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config.ahbConfig.enableReadAddressOpt = true;
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config.ahbConfig.enableAHBBufferable = true;
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config.ahbConfig.enableAHBCachable = true;
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/* enable diff clock and DQS */
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config.enableSckBDiffOpt = true;
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config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
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config.enableCombination = true;
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FLEXSPI_Init(FLEXSPI, &config);
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/* Configure flash settings according to serial flash feature. */
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FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
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/* Update LUT table. */
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FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
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FLEXSPI_SoftwareReset(FLEXSPI);
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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}
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status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
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{
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flexspi_transfer_t flashXfer;
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status_t status = kStatus_Success;
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memset(&flashXfer, 0, sizeof(flashXfer));
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/* Write enable */
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flashXfer.deviceAddress = baseAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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return status;
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}
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status_t flexspi_nor_wait_bus_busy_ram(void)
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{
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/* Wait status ready. */
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bool isBusy = false;
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uint32_t readValue = 0;
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status_t status = kStatus_Success;
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flexspi_transfer_t flashXfer;
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memset(&flashXfer, 0, sizeof(flashXfer));
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
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flashXfer.data = &readValue;
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flashXfer.dataSize = 2;
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do {
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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if (readValue & 0x8000) {
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isBusy = false;
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} else {
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isBusy = true;
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}
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if (readValue & 0x3200) {
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status = kStatus_Fail;
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break;
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}
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} while (isBusy);
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return status;
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}
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status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
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{
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status_t status = kStatus_Success;
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flexspi_transfer_t flashXfer;
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memset(&flashXfer, 0, sizeof(flashXfer));
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/* Write enable */
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status = flexspi_nor_write_enable_ram(address);
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if (status != kStatus_Success) {
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return status;
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}
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 4;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy_ram();
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/* Do software reset. */
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FLEXSPI_SoftwareReset(FLEXSPI);
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return status;
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}
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static void flexspi_lower_clock_ram(void)
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{
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unsigned int reg = 0;
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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FLEXSPI_Enable(FLEXSPI, false);
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/* Disable FlexSPI clock */
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CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
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/* flexspi clock 66M, DDR mode, internal clock 33M. */
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reg = CCM->CSCMR1;
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reg &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
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reg |= CCM_CSCMR1_FLEXSPI_PODF(3);
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CCM->CSCMR1 = reg;
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/* Enable FlexSPI clock */
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CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
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FLEXSPI_Enable(FLEXSPI, true);
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/* Do software reset. */
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FLEXSPI_SoftwareReset(FLEXSPI);
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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}
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static void flexspi_clock_update_ram(void)
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{
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/* Program finished, speed the clock to 133M. */
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/* Wait for bus idle before change flash configuration. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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FLEXSPI_Enable(FLEXSPI, false);
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/* Disable FlexSPI clock */
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CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
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/* flexspi clock 260M, DDR mode, internal clock 130M. */
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CCM->CSCMR1 &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
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/* Enable FlexSPI clock */
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CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
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FLEXSPI_Enable(FLEXSPI, true);
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/* Do software reset. */
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FLEXSPI_SoftwareReset(FLEXSPI);
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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}
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status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)
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{
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status_t status = kStatus_Success;
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flexspi_transfer_t flashXfer;
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uint32_t offset = 0;
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memset(&flashXfer, 0, sizeof(flashXfer));
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flexspi_lower_clock_ram();
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while (size > 0) {
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/* Write enable */
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status = flexspi_nor_write_enable_ram(address + offset);
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if (status != kStatus_Success) {
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return status;
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}
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/* Prepare page program command */
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flashXfer.deviceAddress = address + offset;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
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flashXfer.data = (uint32_t *)(src + offset);
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flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE;
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy_ram();
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if (status != kStatus_Success) {
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return status;
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}
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size -= BOARD_FLASH_PAGE_SIZE;
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offset += BOARD_FLASH_PAGE_SIZE;
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}
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flexspi_clock_update_ram();
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return status;
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}
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void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)
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{
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memcpy(buffer, (void *)addr, size);
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}
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int32_t flash_init(flash_t *obj)
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{
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flexspi_update_lut_ram();
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return 0;
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}
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int32_t flash_erase_sector(flash_t *obj, uint32_t address)
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{
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status_t status = kStatus_Success;
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int32_t ret = 0;
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core_util_critical_section_enter();
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status = flexspi_nor_flash_erase_sector_ram(address - FlexSPI_AMBA_BASE);
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if (status != kStatus_Success) {
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ret = -1;
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} else {
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DCACHE_InvalidateByRange(address, BOARD_FLASH_SECTOR_SIZE);
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}
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core_util_critical_section_exit();
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return ret;
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}
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int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
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{
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status_t status = kStatus_Success;
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int32_t ret = 0;
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core_util_critical_section_enter();
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status = flexspi_nor_flash_page_program_ram(address - FlexSPI_AMBA_BASE, (uint32_t *)data, size);
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if (status != kStatus_Success) {
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ret = -1;
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} else {
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DCACHE_InvalidateByRange(address, size);
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}
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core_util_critical_section_exit();
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return ret;
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}
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int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
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{
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flexspi_nor_flash_read_data_ram(address, (uint32_t *)data, size);
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return 0;
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}
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int32_t flash_free(flash_t *obj)
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{
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return 0;
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}
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uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
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{
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uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
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uint32_t devicesize = BOARD_FLASH_SIZE;
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uint32_t startaddr = BOARD_FLASH_START_ADDR;
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if ((address >= startaddr) && (address < (startaddr + devicesize))) {
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sectorsize = BOARD_FLASH_SECTOR_SIZE;
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}
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return sectorsize;
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}
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uint32_t flash_get_page_size(const flash_t *obj)
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{
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return BOARD_FLASH_PAGE_SIZE;
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}
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uint32_t flash_get_start_address(const flash_t *obj)
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{
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return BOARD_FLASH_START_ADDR;
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}
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uint32_t flash_get_size(const flash_t *obj)
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{
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return BOARD_FLASH_SIZE;
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}
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uint8_t flash_get_erase_value(const flash_t *obj)
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{
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(void)obj;
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return 0xFF;
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}
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#endif //DEVICE_FLASH
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@ -66,6 +66,12 @@ struct trng_s {
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uint8_t dummy;
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uint8_t dummy;
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};
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};
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#if DEVICE_FLASH
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struct flash_s {
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uint8_t dummy;
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};
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#endif
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#include "gpio_object.h"
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#include "gpio_object.h"
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -19,7 +19,13 @@
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#define MBED_DEVICE_H
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#define MBED_DEVICE_H
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#define DEVICE_ID_LENGTH 24
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#define DEVICE_ID_LENGTH 24
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#define BOARD_FLASH_SIZE (0x4000000U)
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/* 4MB reserved for mbed-os */
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#define BOARD_FLASH_SIZE (0x3C00000U)
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||||||
|
#define BOARD_FLASH_START_ADDR (0x60400000U)
|
||||||
|
|
||||||
|
#define BOARD_FLASH_PAGE_SIZE (512)
|
||||||
|
#define BOARD_FLASH_SECTOR_SIZE (262144)
|
||||||
|
|
||||||
#define BOARD_ENET_PHY_ADDR (2)
|
#define BOARD_ENET_PHY_ADDR (2)
|
||||||
|
|
||||||
#include "objects.h"
|
#include "objects.h"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,180 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2019 ARM Limited
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#ifndef _NXP_FLASH_DEFINES_H_
|
||||||
|
#define _NXP_FLASH_DEFINES_H_
|
||||||
|
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
|
||||||
|
#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
|
||||||
|
#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
|
||||||
|
#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
|
||||||
|
#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
|
||||||
|
#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
|
||||||
|
#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP 12
|
||||||
|
#define CUSTOM_LUT_LENGTH 64
|
||||||
|
|
||||||
|
static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
|
||||||
|
/* Read Data */
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
|
||||||
|
|
||||||
|
/* Write Data */
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
|
||||||
|
/* Read Status */
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
|
||||||
|
|
||||||
|
/* Write Enable */
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||||
|
|
||||||
|
/* Erase Sector */
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
|
||||||
|
|
||||||
|
/* program page */
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
|
||||||
|
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
|
||||||
|
|
||||||
|
/* Erase chip */
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80),
|
||||||
|
// 1
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||||
|
// 2
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||||
|
// 3
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||||
|
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] =
|
||||||
|
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10),
|
||||||
|
};
|
||||||
|
|
||||||
|
flexspi_device_config_t deviceconfig = {
|
||||||
|
.flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */
|
||||||
|
.isSck2Enabled = false,
|
||||||
|
.flashSize = BOARD_FLASH_SIZE,
|
||||||
|
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
|
||||||
|
.CSInterval = 2,
|
||||||
|
.CSHoldTime = 0,
|
||||||
|
.CSSetupTime = 3,
|
||||||
|
.dataValidTime = 1,
|
||||||
|
.columnspace = 3,
|
||||||
|
.enableWordAddress = true,
|
||||||
|
.AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA,
|
||||||
|
.AWRSeqNumber = 1,
|
||||||
|
.ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA,
|
||||||
|
.ARDSeqNumber = 1,
|
||||||
|
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
|
||||||
|
.AHBWriteWaitInterval = 20,
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _NXP_FLASH_DEFINES_H_ */
|
||||||
|
|
@ -2441,7 +2441,7 @@
|
||||||
"TRNG",
|
"TRNG",
|
||||||
"FLASH",
|
"FLASH",
|
||||||
"WATCHDOG"
|
"WATCHDOG"
|
||||||
],
|
],
|
||||||
"release_versions": [
|
"release_versions": [
|
||||||
"2",
|
"2",
|
||||||
"5"
|
"5"
|
||||||
|
|
@ -2464,7 +2464,7 @@
|
||||||
"FSL_RTOS_MBED",
|
"FSL_RTOS_MBED",
|
||||||
"USE_EXTERNAL_RTC"
|
"USE_EXTERNAL_RTC"
|
||||||
],
|
],
|
||||||
"default_toolchain": "ARM",
|
"default_toolchain": "ARM",
|
||||||
"forced_reset_timeout": 7,
|
"forced_reset_timeout": 7,
|
||||||
"release_versions": [
|
"release_versions": [
|
||||||
"2",
|
"2",
|
||||||
|
|
@ -2850,7 +2850,8 @@
|
||||||
"SPISLAVE",
|
"SPISLAVE",
|
||||||
"STDIO_MESSAGES",
|
"STDIO_MESSAGES",
|
||||||
"TRNG",
|
"TRNG",
|
||||||
"WATCHDOG"
|
"WATCHDOG",
|
||||||
|
"FLASH"
|
||||||
],
|
],
|
||||||
"release_versions": [
|
"release_versions": [
|
||||||
"2",
|
"2",
|
||||||
|
|
@ -14128,7 +14129,7 @@
|
||||||
"smclk_select": "HFXT",
|
"smclk_select": "HFXT",
|
||||||
"smclk_div": "DIV2",
|
"smclk_div": "DIV2",
|
||||||
"adc_auto_scan": 1
|
"adc_auto_scan": 1
|
||||||
},
|
},
|
||||||
"release_versions": [
|
"release_versions": [
|
||||||
"2",
|
"2",
|
||||||
"5"
|
"5"
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue