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STM32L496 : add QSPI definition

pull/9208/head
jeromecoutant 2018-09-26 13:02:50 +02:00 committed by Cruz Monrreal II
parent c0ad4621e0
commit 41cd8b3d10
3 changed files with 13 additions and 3 deletions
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2
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h
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@ -86,7 +86,7 @@ typedef enum {
} CANName; } CANName;
typedef enum { typedef enum {
QSPI_1 = (int)QSPI_BASE QSPI_1 = (int)QSPI_R_BASE
} QSPIName; } QSPIName;
#ifdef __cplusplus #ifdef __cplusplus

4
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h
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@ -346,8 +346,8 @@ typedef enum {
QSPI_FLASH1_IO1 = PB_0, QSPI_FLASH1_IO1 = PB_0,
QSPI_FLASH1_IO2 = PA_7, QSPI_FLASH1_IO2 = PA_7,
QSPI_FLASH1_IO3 = PA_6, QSPI_FLASH1_IO3 = PA_6,
QSPI_FLASH1_SCK = PB_11, QSPI_FLASH1_SCK = PA_3,
QSPI_FLASH1_CSN = PA_3, QSPI_FLASH1_CSN = PB_11,
// Not connected // Not connected
NC = (int)0xFFFFFFFF NC = (int)0xFFFFFFFF

10
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h
View File

@ -58,6 +58,16 @@ struct trng_s {
RNG_HandleTypeDef handle; RNG_HandleTypeDef handle;
}; };
struct qspi_s {
QSPI_HandleTypeDef handle;
PinName io0;
PinName io1;
PinName io2;
PinName io3;
PinName sclk;
PinName ssel;
};
#include "common_objects.h" #include "common_objects.h"
#ifdef __cplusplus #ifdef __cplusplus