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[mbed][MTS_DRAGONFLY_F411RE] change wrong PLL members to correct values from ST Cube code

pull/787/head
Mike Fiore 2014-11-20 12:36:01 -06:00
parent bb4c5f4ab5
commit 4196364088
1 changed files with 3 additions and 3 deletions
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6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c
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@ -611,10 +611,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
//RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
//RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
RCC_OscInitStruct.PLL.PLLM = 26; // VCO input clock = 2 MHz (8 MHz / 4) RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4)
RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 400 MHz (2 MHz * 200) RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{ {
return 0; // FAIL return 0; // FAIL