mirror of https://github.com/ARMmbed/mbed-os.git
Add analogin, serial and spi support for NUCLEO_F103RB
bcostm
parent
70dd0d891e
commit
415ac34b56
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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
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;* File Name : startup_stm32f10x_md.s
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;* Author : MCD Application Team
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;* Version : V3.5.0
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;* Date : 11-March-2011
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;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
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;* toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Configure the clock system
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM3 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20000000 ; Top of RAM
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window Watchdog
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DCD PVD_IRQHandler ; PVD through EXTI Line detect
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DCD TAMPER_IRQHandler ; Tamper
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DCD RTC_IRQHandler ; RTC
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DCD FLASH_IRQHandler ; Flash
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line 0
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DCD EXTI1_IRQHandler ; EXTI Line 1
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DCD EXTI2_IRQHandler ; EXTI Line 2
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DCD EXTI3_IRQHandler ; EXTI Line 3
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DCD EXTI4_IRQHandler ; EXTI Line 4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
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DCD ADC1_2_IRQHandler ; ADC1_2
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DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
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DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
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DCD CAN1_RX1_IRQHandler ; CAN1 RX1
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DCD CAN1_SCE_IRQHandler ; CAN1 SCE
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DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
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DCD TIM1_BRK_IRQHandler ; TIM1 Break
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DCD TIM1_UP_IRQHandler ; TIM1 Update
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DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
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DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
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DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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IMPORT SystemInit
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT TAMPER_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_IRQHandler [WEAK]
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EXPORT DMA1_Channel2_IRQHandler [WEAK]
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EXPORT DMA1_Channel3_IRQHandler [WEAK]
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EXPORT DMA1_Channel4_IRQHandler [WEAK]
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EXPORT DMA1_Channel5_IRQHandler [WEAK]
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EXPORT DMA1_Channel6_IRQHandler [WEAK]
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EXPORT DMA1_Channel7_IRQHandler [WEAK]
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EXPORT ADC1_2_IRQHandler [WEAK]
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EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
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EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
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EXPORT CAN1_RX1_IRQHandler [WEAK]
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EXPORT CAN1_SCE_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_IRQHandler [WEAK]
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EXPORT TIM1_UP_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM4_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTCAlarm_IRQHandler [WEAK]
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EXPORT USBWakeUp_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_IRQHandler
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TAMPER_IRQHandler
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RTC_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Channel1_IRQHandler
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DMA1_Channel2_IRQHandler
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DMA1_Channel3_IRQHandler
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DMA1_Channel4_IRQHandler
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DMA1_Channel5_IRQHandler
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DMA1_Channel6_IRQHandler
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DMA1_Channel7_IRQHandler
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ADC1_2_IRQHandler
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USB_HP_CAN1_TX_IRQHandler
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USB_LP_CAN1_RX0_IRQHandler
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CAN1_RX1_IRQHandler
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CAN1_SCE_IRQHandler
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EXTI9_5_IRQHandler
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TIM1_BRK_IRQHandler
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TIM1_UP_IRQHandler
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TIM1_TRG_COM_IRQHandler
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TIM1_CC_IRQHandler
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TIM2_IRQHandler
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TIM3_IRQHandler
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TIM4_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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I2C2_EV_IRQHandler
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I2C2_ER_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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USART3_IRQHandler
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EXTI15_10_IRQHandler
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RTCAlarm_IRQHandler
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USBWakeUp_IRQHandler
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B .
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ENDP
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ALIGN
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;*******************************************************************************
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; User Stack and Heap initialization
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;*******************************************************************************
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;IF :DEF:__MICROLIB
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;EXPORT __initial_sp
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;EXPORT __heap_base
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;EXPORT __heap_limit
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;ELSE
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;IMPORT __use_two_region_memory
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;EXPORT __user_initial_stackheap
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;__user_initial_stackheap
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;LDR R0, = Heap_Mem
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;LDR R1, =(Stack_Mem + Stack_Size)
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;LDR R2, = (Heap_Mem + Heap_Size)
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;LDR R3, = Stack_Mem
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;BX LR
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;ALIGN
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;ENDIF
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END
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;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
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@ -0,0 +1,19 @@
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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LR_IROM1 0x08000000 0x20000 { ; load region size_region (128K)
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ER_IROM1 0x08000000 0x20000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
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RW_IRAM1 (0x20000000+0xEC) (0x5000-0xEC) { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,31 @@
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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif
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; *** Scatter-Loading Description File generated by uVision ***
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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; *************************************************************
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LR_IROM1 0x08000000 0x00010000 { ; load region size_region
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LR_IROM1 0x08000000 0x20000 { ; load region size_region (128K)
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ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
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ER_IROM1 0x08000000 0x20000 { ; load address = execution address
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*.o (RESET, +First)
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*.o (RESET, +First)
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*(InRoot$$Sections)
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+RO)
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}
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}
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;RW_IRAM1 0x20000000 0x00005000 { ; RW data
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; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
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; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
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; 20KB - 0xEC = 0x5000 - 0xEC = 0x4F14 bytes after reserved area
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RW_IRAM1 (0x20000000+0xEC) (0x5000-0xEC) { ; RW data
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RW_IRAM1 0x200000EC 0x00004F14 { ; RW data
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.ANY (+RW +ZI)
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.ANY (+RW +ZI)
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,104 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2013 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
//==============================================================================
|
||||||
|
// STM32F103
|
||||||
|
//==============================================================================
|
||||||
|
#include "analogin_api.h"
|
||||||
|
#include "wait_api.h"
|
||||||
|
|
||||||
|
#if DEVICE_ANALOGIN
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "error.h"
|
||||||
|
|
||||||
|
static const PinMap PinMap_ADC[] = {
|
||||||
|
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
|
||||||
|
{PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
|
||||||
|
{PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
|
||||||
|
{PB_0, ADC_2, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
|
||||||
|
{PC_1, ADC_2, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
|
||||||
|
{PC_0, ADC_2, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
void analogin_init(analogin_t *obj, PinName pin) {
|
||||||
|
|
||||||
|
ADC_TypeDef *adc;
|
||||||
|
ADC_InitTypeDef ADC_InitStructure;
|
||||||
|
|
||||||
|
// Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object
|
||||||
|
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
|
||||||
|
|
||||||
|
if (obj->adc == (ADCName)NC) {
|
||||||
|
error("ADC pin mapping failed");
|
||||||
|
}
|
||||||
|
|
||||||
|
// Get ADC registers structure address
|
||||||
|
adc = (ADC_TypeDef *)(obj->adc);
|
||||||
|
|
||||||
|
// Enable ADC clock
|
||||||
|
RCC_ADCCLKConfig(RCC_PCLK2_Div4);
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2, ENABLE);
|
||||||
|
|
||||||
|
// Configure GPIO
|
||||||
|
pinmap_pinout(pin, PinMap_ADC);
|
||||||
|
|
||||||
|
// Configure ADC
|
||||||
|
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
|
||||||
|
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
|
||||||
|
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
|
||||||
|
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
|
||||||
|
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
|
||||||
|
ADC_InitStructure.ADC_NbrOfChannel = 1;
|
||||||
|
ADC_Init(adc, &ADC_InitStructure);
|
||||||
|
|
||||||
|
// Configure ADC channel
|
||||||
|
if (pin == PA_0) { ADC_RegularChannelConfig(adc, ADC_Channel_0, 1, ADC_SampleTime_7Cycles5); }
|
||||||
|
if (pin == PA_1) { ADC_RegularChannelConfig(adc, ADC_Channel_1, 1, ADC_SampleTime_7Cycles5); }
|
||||||
|
if (pin == PA_4) { ADC_RegularChannelConfig(adc, ADC_Channel_4, 1, ADC_SampleTime_7Cycles5); }
|
||||||
|
if (pin == PB_0) { ADC_RegularChannelConfig(adc, ADC_Channel_8, 1, ADC_SampleTime_7Cycles5); }
|
||||||
|
if (pin == PC_1) { ADC_RegularChannelConfig(adc, ADC_Channel_11, 1, ADC_SampleTime_7Cycles5); }
|
||||||
|
if (pin == PC_0) { ADC_RegularChannelConfig(adc, ADC_Channel_10, 1, ADC_SampleTime_7Cycles5); }
|
||||||
|
|
||||||
|
// Enable ADC
|
||||||
|
ADC_Cmd(adc, ENABLE);
|
||||||
|
|
||||||
|
// Calibrate ADC
|
||||||
|
ADC_ResetCalibration(adc);
|
||||||
|
while(ADC_GetResetCalibrationStatus(adc));
|
||||||
|
ADC_StartCalibration(adc);
|
||||||
|
while(ADC_GetCalibrationStatus(adc));
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline uint16_t adc_read(analogin_t *obj) {
|
||||||
|
// Get ADC registers structure address
|
||||||
|
ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
|
||||||
|
ADC_SoftwareStartConvCmd(adc, ENABLE); // Start conversion
|
||||||
|
while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
|
||||||
|
return(ADC_GetConversionValue(adc)); // Get conversion value
|
||||||
|
}
|
||||||
|
|
||||||
|
uint16_t analogin_read_u16(analogin_t *obj) {
|
||||||
|
return(adc_read(obj));
|
||||||
|
}
|
||||||
|
|
||||||
|
float analogin_read(analogin_t *obj) {
|
||||||
|
uint16_t value = adc_read(obj);
|
||||||
|
return (float)value * (1.0f / (float)0xFFF); // 12 bits range
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -22,15 +22,15 @@
|
||||||
|
|
||||||
#define DEVICE_INTERRUPTIN 0
|
#define DEVICE_INTERRUPTIN 0
|
||||||
|
|
||||||
#define DEVICE_ANALOGIN 0
|
#define DEVICE_ANALOGIN 1
|
||||||
#define DEVICE_ANALOGOUT 0
|
#define DEVICE_ANALOGOUT 0
|
||||||
|
|
||||||
#define DEVICE_SERIAL 0
|
#define DEVICE_SERIAL 1
|
||||||
|
|
||||||
#define DEVICE_I2C 0
|
#define DEVICE_I2C 0
|
||||||
#define DEVICE_I2CSLAVE 0
|
#define DEVICE_I2CSLAVE 0
|
||||||
|
|
||||||
#define DEVICE_SPI 0
|
#define DEVICE_SPI 1
|
||||||
#define DEVICE_SPISLAVE 0
|
#define DEVICE_SPISLAVE 0
|
||||||
|
|
||||||
#define DEVICE_RTC 0
|
#define DEVICE_RTC 0
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,310 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2013 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
//==============================================================================
|
||||||
|
// STM32F103
|
||||||
|
//==============================================================================
|
||||||
|
#include "serial_api.h"
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "error.h"
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* INITIALIZATION
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
static const PinMap PinMap_UART_TX[] = {
|
||||||
|
{PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
|
||||||
|
{PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const PinMap PinMap_UART_RX[] = {
|
||||||
|
{PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)},
|
||||||
|
{PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)},
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
#define UART_NUM (2)
|
||||||
|
|
||||||
|
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||||
|
|
||||||
|
static uart_irq_handler irq_handler;
|
||||||
|
|
||||||
|
int stdio_uart_inited = 0;
|
||||||
|
serial_t stdio_uart;
|
||||||
|
|
||||||
|
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||||
|
|
||||||
|
USART_TypeDef *usart;
|
||||||
|
USART_InitTypeDef USART_InitStructure;
|
||||||
|
|
||||||
|
// Determine the UART to use (UART_1, UART_2, ...)
|
||||||
|
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
|
||||||
|
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
|
||||||
|
|
||||||
|
// Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
|
||||||
|
obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
|
||||||
|
|
||||||
|
if (obj->uart == (UARTName)NC) {
|
||||||
|
error("Serial pinout mapping failed");
|
||||||
|
}
|
||||||
|
|
||||||
|
// Get UART registers structure address
|
||||||
|
usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
|
||||||
|
// Enable USART clock
|
||||||
|
if (obj->uart == UART_1) {
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
|
||||||
|
}
|
||||||
|
if (obj->uart == UART_2) {
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Configure the UART pins
|
||||||
|
pinmap_pinout(tx, PinMap_UART_TX);
|
||||||
|
pinmap_pinout(rx, PinMap_UART_RX);
|
||||||
|
|
||||||
|
// Configure UART
|
||||||
|
obj->baudrate = 9600;
|
||||||
|
obj->databits = USART_WordLength_8b;
|
||||||
|
obj->stopbits = USART_StopBits_1;
|
||||||
|
obj->parity = USART_Parity_No;
|
||||||
|
|
||||||
|
USART_InitStructure.USART_BaudRate = obj->baudrate;
|
||||||
|
USART_InitStructure.USART_WordLength = obj->databits;
|
||||||
|
USART_InitStructure.USART_StopBits = obj->stopbits;
|
||||||
|
USART_InitStructure.USART_Parity = obj->parity;
|
||||||
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||||
|
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||||
|
USART_Init(usart, &USART_InitStructure);
|
||||||
|
|
||||||
|
USART_Cmd(usart, ENABLE);
|
||||||
|
|
||||||
|
// The index is used by irq
|
||||||
|
if (obj->uart == UART_1) obj->index = 0;
|
||||||
|
if (obj->uart == UART_2) obj->index = 1;
|
||||||
|
|
||||||
|
// For stdio management
|
||||||
|
if (obj->uart == STDIO_UART) {
|
||||||
|
stdio_uart_inited = 1;
|
||||||
|
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_free(serial_t *obj) {
|
||||||
|
serial_irq_ids[obj->index] = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_baud(serial_t *obj, int baudrate) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
USART_InitTypeDef USART_InitStructure;
|
||||||
|
|
||||||
|
// Save new value
|
||||||
|
obj->baudrate = baudrate;
|
||||||
|
|
||||||
|
USART_Cmd(usart, DISABLE);
|
||||||
|
|
||||||
|
USART_InitStructure.USART_BaudRate = obj->baudrate;
|
||||||
|
USART_InitStructure.USART_WordLength = obj->databits;
|
||||||
|
USART_InitStructure.USART_StopBits = obj->stopbits;
|
||||||
|
USART_InitStructure.USART_Parity = obj->parity;
|
||||||
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||||
|
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||||
|
USART_Init(usart, &USART_InitStructure);
|
||||||
|
|
||||||
|
USART_Cmd(usart, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
USART_InitTypeDef USART_InitStructure;
|
||||||
|
|
||||||
|
// Save new values
|
||||||
|
|
||||||
|
if (data_bits == 8) {
|
||||||
|
obj->databits = USART_WordLength_8b;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
obj->databits = USART_WordLength_9b;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (parity) {
|
||||||
|
case ParityOdd:
|
||||||
|
case ParityForced0:
|
||||||
|
obj->parity = USART_Parity_Odd;
|
||||||
|
break;
|
||||||
|
case ParityEven:
|
||||||
|
case ParityForced1:
|
||||||
|
obj->parity = USART_Parity_Even;
|
||||||
|
break;
|
||||||
|
default: // ParityNone
|
||||||
|
obj->parity = USART_Parity_No;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (stop_bits == 2) {
|
||||||
|
obj->stopbits = USART_StopBits_2;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
obj->stopbits = USART_StopBits_1;
|
||||||
|
}
|
||||||
|
|
||||||
|
USART_Cmd(usart, DISABLE);
|
||||||
|
|
||||||
|
USART_InitStructure.USART_BaudRate = obj->baudrate;
|
||||||
|
USART_InitStructure.USART_WordLength = obj->databits;
|
||||||
|
USART_InitStructure.USART_StopBits = obj->stopbits;
|
||||||
|
USART_InitStructure.USART_Parity = obj->parity;
|
||||||
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||||
|
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||||
|
USART_Init(usart, &USART_InitStructure);
|
||||||
|
|
||||||
|
USART_Cmd(usart, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* INTERRUPTS HANDLING
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
// not api
|
||||||
|
void uart1_irq(void) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)UART_1;
|
||||||
|
if (serial_irq_ids[0] != 0) {
|
||||||
|
if (USART_GetITStatus(usart, USART_IT_TXE) != RESET) {
|
||||||
|
irq_handler(serial_irq_ids[0], TxIrq);
|
||||||
|
}
|
||||||
|
if (USART_GetITStatus(usart, USART_IT_RXNE) != RESET) {
|
||||||
|
irq_handler(serial_irq_ids[0], RxIrq);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// not api
|
||||||
|
void uart2_irq(void) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)UART_2;
|
||||||
|
if (serial_irq_ids[1] != 0) {
|
||||||
|
if (USART_GetITStatus(usart, USART_IT_TXE) != RESET) {
|
||||||
|
irq_handler(serial_irq_ids[1], TxIrq);
|
||||||
|
}
|
||||||
|
if (USART_GetITStatus(usart, USART_IT_RXNE) != RESET) {
|
||||||
|
irq_handler(serial_irq_ids[1], RxIrq);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
||||||
|
irq_handler = handler;
|
||||||
|
serial_irq_ids[obj->index] = id;
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
||||||
|
IRQn_Type irq_n = (IRQn_Type)0;
|
||||||
|
uint32_t vector = 0;
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
|
||||||
|
if (obj->uart == UART_1) {
|
||||||
|
irq_n = USART1_IRQn;
|
||||||
|
vector = (uint32_t)&uart1_irq;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (obj->uart == UART_2) {
|
||||||
|
irq_n = USART2_IRQn;
|
||||||
|
vector = (uint32_t)&uart2_irq;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (enable) {
|
||||||
|
|
||||||
|
if (irq == RxIrq) {
|
||||||
|
USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
|
||||||
|
}
|
||||||
|
else { // TxIrq
|
||||||
|
USART_ITConfig(usart, USART_IT_TXE, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
NVIC_SetVector(irq_n, vector);
|
||||||
|
NVIC_EnableIRQ(irq_n);
|
||||||
|
|
||||||
|
} else { // disable
|
||||||
|
|
||||||
|
int all_disabled = 0;
|
||||||
|
|
||||||
|
if (irq == RxIrq) {
|
||||||
|
USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
|
||||||
|
// Check if TxIrq is disabled too
|
||||||
|
if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
|
||||||
|
}
|
||||||
|
else { // TxIrq
|
||||||
|
USART_ITConfig(usart, USART_IT_TXE, DISABLE);
|
||||||
|
// Check if RxIrq is disabled too
|
||||||
|
if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (all_disabled) NVIC_DisableIRQ(irq_n);
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* READ/WRITE
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
int serial_getc(serial_t *obj) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
while (!serial_readable(obj));
|
||||||
|
return (int)(USART_ReceiveData(usart));
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_putc(serial_t *obj, int c) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
while (!serial_writable(obj));
|
||||||
|
USART_SendData(usart, (uint16_t)c);
|
||||||
|
}
|
||||||
|
|
||||||
|
int serial_readable(serial_t *obj) {
|
||||||
|
int status;
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
// Check if data is received
|
||||||
|
status = ((USART_GetFlagStatus(usart, USART_FLAG_RXNE) != RESET) ? 1 : 0);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
int serial_writable(serial_t *obj) {
|
||||||
|
int status;
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
// Check if data is transmitted
|
||||||
|
status = ((USART_GetFlagStatus(usart, USART_FLAG_TXE) != RESET) ? 1 : 0);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_clear(serial_t *obj) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
USART_ClearFlag(usart, USART_FLAG_TXE);
|
||||||
|
USART_ClearFlag(usart, USART_FLAG_RXNE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_pinout_tx(PinName tx) {
|
||||||
|
pinmap_pinout(tx, PinMap_UART_TX);
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_break_set(serial_t *obj) {
|
||||||
|
USART_TypeDef *usart = (USART_TypeDef *)(obj->uart);
|
||||||
|
USART_SendBreak(usart);
|
||||||
|
}
|
||||||
|
|
||||||
|
void serial_break_clear(serial_t *obj) {
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,281 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2013 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
//==============================================================================
|
||||||
|
// STM32F103
|
||||||
|
//==============================================================================
|
||||||
|
#include "spi_api.h"
|
||||||
|
|
||||||
|
#if DEVICE_SPI
|
||||||
|
|
||||||
|
#include <math.h>
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "error.h"
|
||||||
|
|
||||||
|
static const PinMap PinMap_SPI_MOSI[] = {
|
||||||
|
{PA_7, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
|
||||||
|
{PB_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const PinMap PinMap_SPI_MISO[] = {
|
||||||
|
{PA_6, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
|
||||||
|
{PB_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const PinMap PinMap_SPI_SCLK[] = {
|
||||||
|
{PA_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
|
||||||
|
{PB_3, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
// Only used in Slave mode
|
||||||
|
static const PinMap PinMap_SPI_SSEL[] = {
|
||||||
|
{PA_4, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)},
|
||||||
|
{PA_15, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 1)}, // Remap
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
|
||||||
|
|
||||||
|
SPI_TypeDef *spi;
|
||||||
|
SPI_InitTypeDef SPI_InitStructure;
|
||||||
|
|
||||||
|
// Determine the SPI to use
|
||||||
|
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
|
||||||
|
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
|
||||||
|
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
|
||||||
|
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
|
||||||
|
|
||||||
|
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
|
||||||
|
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
|
||||||
|
|
||||||
|
obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
|
||||||
|
|
||||||
|
if (obj->spi == (SPIName)NC) {
|
||||||
|
error("SPI pinout mapping failed");
|
||||||
|
}
|
||||||
|
|
||||||
|
// Get SPI registers structure address
|
||||||
|
spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
|
||||||
|
// Enable SPI clock
|
||||||
|
if (obj->spi == SPI_1) {
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||||
|
}
|
||||||
|
if (obj->spi == SPI_2) {
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Configure the SPI pins
|
||||||
|
pinmap_pinout(mosi, PinMap_SPI_MOSI);
|
||||||
|
pinmap_pinout(miso, PinMap_SPI_MISO);
|
||||||
|
pinmap_pinout(sclk, PinMap_SPI_SCLK);
|
||||||
|
|
||||||
|
// Save new values
|
||||||
|
obj->bits = SPI_DataSize_8b;
|
||||||
|
obj->cpol = SPI_CPOL_Low;
|
||||||
|
obj->cpha = SPI_CPHA_1Edge;
|
||||||
|
obj->br_presc = SPI_BaudRatePrescaler_64; // Closest to 1MHz (72MHz/64 = 1.125MHz)
|
||||||
|
|
||||||
|
if (ssel == NC) { // Master
|
||||||
|
obj->mode = SPI_Mode_Master;
|
||||||
|
obj->nss = SPI_NSS_Soft;
|
||||||
|
}
|
||||||
|
else { // Slave
|
||||||
|
pinmap_pinout(ssel, PinMap_SPI_SSEL);
|
||||||
|
obj->mode = SPI_Mode_Slave;
|
||||||
|
obj->nss = SPI_NSS_Hard;
|
||||||
|
}
|
||||||
|
|
||||||
|
// SPI configuration
|
||||||
|
SPI_InitStructure.SPI_Mode = obj->mode;
|
||||||
|
SPI_InitStructure.SPI_NSS = obj->nss;
|
||||||
|
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||||
|
SPI_InitStructure.SPI_DataSize = obj->bits;
|
||||||
|
SPI_InitStructure.SPI_CPOL = obj->cpol;
|
||||||
|
SPI_InitStructure.SPI_CPHA = obj->cpha;
|
||||||
|
SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc;
|
||||||
|
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
|
||||||
|
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
||||||
|
SPI_Init(spi, &SPI_InitStructure);
|
||||||
|
|
||||||
|
SPI_Cmd(spi, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_free(spi_t *obj) {
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
SPI_I2S_DeInit(spi);
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_format(spi_t *obj, int bits, int mode, int slave) {
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
SPI_InitTypeDef SPI_InitStructure;
|
||||||
|
|
||||||
|
// Save new values
|
||||||
|
|
||||||
|
if (bits == 8) {
|
||||||
|
obj->bits = SPI_DataSize_8b;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
obj->bits = SPI_DataSize_16b;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (mode) {
|
||||||
|
case 0:
|
||||||
|
obj->cpol = SPI_CPOL_Low;
|
||||||
|
obj->cpha = SPI_CPHA_1Edge;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
obj->cpol = SPI_CPOL_Low;
|
||||||
|
obj->cpha = SPI_CPHA_2Edge;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
obj->cpol = SPI_CPOL_High;
|
||||||
|
obj->cpha = SPI_CPHA_1Edge;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
obj->cpol = SPI_CPOL_High;
|
||||||
|
obj->cpha = SPI_CPHA_2Edge;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (slave == 0) {
|
||||||
|
obj->mode = SPI_Mode_Master;
|
||||||
|
obj->nss = SPI_NSS_Soft;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
obj->mode = SPI_Mode_Slave;
|
||||||
|
obj->nss = SPI_NSS_Hard;
|
||||||
|
}
|
||||||
|
|
||||||
|
SPI_Cmd(spi, DISABLE);
|
||||||
|
|
||||||
|
SPI_InitStructure.SPI_Mode = obj->mode;
|
||||||
|
SPI_InitStructure.SPI_NSS = obj->nss;
|
||||||
|
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||||
|
SPI_InitStructure.SPI_DataSize = obj->bits;
|
||||||
|
SPI_InitStructure.SPI_CPOL = obj->cpol;
|
||||||
|
SPI_InitStructure.SPI_CPHA = obj->cpha;
|
||||||
|
SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc;
|
||||||
|
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
|
||||||
|
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
||||||
|
SPI_Init(spi, &SPI_InitStructure);
|
||||||
|
|
||||||
|
SPI_Cmd(spi, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_frequency(spi_t *obj, int hz) {
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
SPI_InitTypeDef SPI_InitStructure;
|
||||||
|
|
||||||
|
// Get SPI clock frequency
|
||||||
|
uint32_t PCLK = SystemCoreClock >> 1;
|
||||||
|
|
||||||
|
// Choose the baud rate divisor (between 2 and 256)
|
||||||
|
uint32_t divisor = PCLK / hz;
|
||||||
|
|
||||||
|
// Find the nearest power-of-2
|
||||||
|
divisor = (divisor > 0 ? divisor-1 : 0);
|
||||||
|
divisor |= divisor >> 1;
|
||||||
|
divisor |= divisor >> 2;
|
||||||
|
divisor |= divisor >> 4;
|
||||||
|
divisor |= divisor >> 8;
|
||||||
|
divisor |= divisor >> 16;
|
||||||
|
divisor++;
|
||||||
|
|
||||||
|
uint32_t baud_rate = __builtin_ffs(divisor) - 2;
|
||||||
|
|
||||||
|
// Save new value
|
||||||
|
obj->br_presc = ((baud_rate > 7) ? (7 << 3) : (baud_rate << 3));
|
||||||
|
|
||||||
|
SPI_Cmd(spi, DISABLE);
|
||||||
|
|
||||||
|
SPI_InitStructure.SPI_Mode = obj->mode;
|
||||||
|
SPI_InitStructure.SPI_NSS = obj->nss;
|
||||||
|
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||||
|
SPI_InitStructure.SPI_DataSize = obj->bits;
|
||||||
|
SPI_InitStructure.SPI_CPOL = obj->cpol;
|
||||||
|
SPI_InitStructure.SPI_CPHA = obj->cpha;
|
||||||
|
SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc;
|
||||||
|
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
|
||||||
|
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
||||||
|
SPI_Init(spi, &SPI_InitStructure);
|
||||||
|
|
||||||
|
SPI_Cmd(spi, ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int ssp_readable(spi_t *obj) {
|
||||||
|
int status;
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
// Check if data is received
|
||||||
|
status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_RXNE) != RESET) ? 1 : 0);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int ssp_writeable(spi_t *obj) {
|
||||||
|
int status;
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
// Check if data is transmitted
|
||||||
|
status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_TXE) != RESET) ? 1 : 0);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void ssp_write(spi_t *obj, int value) {
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
while (!ssp_writeable(obj));
|
||||||
|
SPI_I2S_SendData(spi, (uint16_t)value);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int ssp_read(spi_t *obj) {
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
while (!ssp_readable(obj));
|
||||||
|
return (int)SPI_I2S_ReceiveData(spi);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int ssp_busy(spi_t *obj) {
|
||||||
|
int status;
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_BSY) != RESET) ? 1 : 0);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
int spi_master_write(spi_t *obj, int value) {
|
||||||
|
ssp_write(obj, value);
|
||||||
|
return ssp_read(obj);
|
||||||
|
}
|
||||||
|
|
||||||
|
int spi_slave_receive(spi_t *obj) {
|
||||||
|
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
|
||||||
|
};
|
||||||
|
|
||||||
|
int spi_slave_read(spi_t *obj) {
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
return (int)SPI_I2S_ReceiveData(spi);
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_slave_write(spi_t *obj, int value) {
|
||||||
|
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
|
||||||
|
while (!ssp_writeable(obj));
|
||||||
|
SPI_I2S_SendData(spi, (uint16_t)value);
|
||||||
|
}
|
||||||
|
|
||||||
|
int spi_busy(spi_t *obj) {
|
||||||
|
return ssp_busy(obj);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue