mirror of https://github.com/ARMmbed/mbed-os.git
Add MTB_ADV_WISE_1570 target
Kimmo Vaisanen
parent
3e5fafdca9
commit
41490f48d0
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/*
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* mbedtls_device.h
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*******************************************************************************
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* Copyright (c) 2017, STMicroelectronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef MBEDTLS_DEVICE_H
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#define MBEDTLS_DEVICE_H
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#define MBEDTLS_AES_ALT
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#endif /* MBEDTLS_DEVICE_H */
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2015, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ADC_1 = (int)ADC1_BASE,
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ADC_2 = (int)ADC2_BASE,
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ADC_3 = (int)ADC3_BASE
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} ADCName;
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typedef enum {
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DAC_1 = (int)DAC_BASE
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} DACName;
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typedef enum {
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UART_1 = (int)USART1_BASE,
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UART_2 = (int)USART2_BASE,
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UART_3 = (int)USART3_BASE,
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UART_4 = (int)UART4_BASE,
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UART_5 = (int)UART5_BASE,
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LPUART_1 = (int)LPUART1_BASE
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} UARTName;
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typedef enum {
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SPI_1 = (int)SPI1_BASE,
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SPI_2 = (int)SPI2_BASE,
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SPI_3 = (int)SPI3_BASE
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} SPIName;
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typedef enum {
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I2C_1 = (int)I2C1_BASE,
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I2C_2 = (int)I2C2_BASE,
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I2C_3 = (int)I2C3_BASE
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} I2CName;
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typedef enum {
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PWM_1 = (int)TIM1_BASE,
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PWM_2 = (int)TIM2_BASE,
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PWM_3 = (int)TIM3_BASE,
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PWM_4 = (int)TIM4_BASE,
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PWM_5 = (int)TIM5_BASE,
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PWM_8 = (int)TIM8_BASE,
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PWM_15 = (int)TIM15_BASE,
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PWM_16 = (int)TIM16_BASE,
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PWM_17 = (int)TIM17_BASE
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} PWMName;
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typedef enum {
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CAN_1 = (int)CAN1_BASE
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} CANName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,137 @@
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2016, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#include "PeripheralPins.h"
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// =====
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// Note: Commented lines are alternative possibilities which are not used per default.
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// If you change them, you will have also to modify the corresponding xxx_api.c file
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// for pwmout, analogin, analogout, ...
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// =====
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//*** ADC ***
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const PinMap PinMap_ADC[] = {
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{ADC00, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // IN6
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{ADC01, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // IN3
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{ADC02, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
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{NC, NC, 0}
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};
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const PinMap PinMap_ADC_Internal[] = {
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{NC, NC, 0}
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};
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//*** DAC ***
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const PinMap PinMap_DAC[] = {
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{NC, NC, 0}
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};
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//*** I2C ***
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const PinMap PinMap_I2C_SDA[] = {
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{I2C0_SDA, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{I2C1_SDA, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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{NC, NC, 0}
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};
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const PinMap PinMap_I2C_SCL[] = {
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{I2C0_SCL, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{I2C1_SCL, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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{NC, NC, 0}
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};
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//*** PWM ***
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// Warning: TIM5 cannot be used because already used by the us_ticker.
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const PinMap PinMap_PWM[] = {
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{PWM0_OUT, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
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{PWM1_OUT, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
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{NC, NC, 0}
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};
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//*** SERIAL ***
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const PinMap PinMap_UART_TX[] = {
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{UART2_TX, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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{UART_TXD, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
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{LPUART1_TX, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{UART1_TX, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{NC, NC, 0}
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};
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const PinMap PinMap_UART_RX[] = {
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{UART2_RX, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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{UART_RXD, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
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{LPUART1_RX, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{UART1_RX, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{NC, NC, 0}
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};
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const PinMap PinMap_UART_RTS[] = {
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{UART_RTS, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
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{NC, NC, 0}
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};
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const PinMap PinMap_UART_CTS[] = {
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{UART_CTS, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
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{NC, NC, 0}
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};
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//*** SPI ***
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const PinMap PinMap_SPI_MOSI[] = {
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{SPI_MOSI, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_MISO[] = {
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{SPI_MISO, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_SCLK[] = {
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{SPI_SCK, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_SSEL[] = {
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{SPI_CS0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{NC, NC, 0}
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};
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const PinMap PinMap_CAN_RD[] = {
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{NC, NC, 0}
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};
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const PinMap PinMap_CAN_TD[] = {
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{NC, NC, 0}
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};
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@ -0,0 +1,194 @@
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2016, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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||||||
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* this list of conditions and the following disclaimer.
|
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|
* 2. Redistributions in binary form must reproduce the above copyright notice,
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||||||
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#ifndef MBED_PINNAMES_H
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#define MBED_PINNAMES_H
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#include "cmsis.h"
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#include "PinNamesTypes.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PA_0 = 0x00,
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PA_1 = 0x01,
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PA_2 = 0x02,
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PA_3 = 0x03,
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PA_4 = 0x04,
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PA_5 = 0x05,
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PA_6 = 0x06,
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PA_7 = 0x07,
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PA_8 = 0x08,
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PA_9 = 0x09,
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PA_10 = 0x0A,
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PA_11 = 0x0B,
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PA_12 = 0x0C,
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PA_13 = 0x0D,
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PA_14 = 0x0E,
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PA_15 = 0x0F,
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PB_0 = 0x10,
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PB_1 = 0x11,
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PB_2 = 0x12,
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PB_3 = 0x13,
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PB_4 = 0x14,
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PB_5 = 0x15,
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PB_6 = 0x16,
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PB_7 = 0x17,
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PB_8 = 0x18,
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PB_9 = 0x19,
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PB_10 = 0x1A,
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PB_11 = 0x1B,
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PB_12 = 0x1C,
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PB_13 = 0x1D,
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PB_14 = 0x1E,
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PB_15 = 0x1F,
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PC_0 = 0x20,
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PC_1 = 0x21,
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PC_2 = 0x22,
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PC_3 = 0x23,
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PC_4 = 0x24,
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PC_5 = 0x25,
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PC_6 = 0x26,
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PC_7 = 0x27,
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PC_8 = 0x28,
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PC_9 = 0x29,
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PC_10 = 0x2A,
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PC_11 = 0x2B,
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PC_12 = 0x2C,
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PC_13 = 0x2D,
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PC_14 = 0x2E,
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PC_15 = 0x2F,
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PD_2 = 0x32,
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PH_0 = 0x70,
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PH_1 = 0x71,
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// Not connected
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NC = (int)0xFFFFFFFF,
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// MCU pins
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||||||
|
CB_RESET_OUT = PA_8,
|
||||||
|
CB_PWR_ON = PA_11,
|
||||||
|
|
||||||
|
UART3_TX = PC_10,
|
||||||
|
UART3_RX = PC_11,
|
||||||
|
UART3_RTS = PB_13,
|
||||||
|
UART3_CTS = PB_14,
|
||||||
|
|
||||||
|
GPIO0 = PB_9,
|
||||||
|
GPIO1 = PC_7,
|
||||||
|
GPIO2 = PB_15,
|
||||||
|
GPIO3 = PB_12,
|
||||||
|
GPIO4 = PC_8,
|
||||||
|
GPIO5 = PC_13,
|
||||||
|
|
||||||
|
W_DISABLE = PB_2,
|
||||||
|
|
||||||
|
I2C0_SDA = PB_7,
|
||||||
|
I2C0_SCL = PB_6,
|
||||||
|
|
||||||
|
SPI_MOSI = PA_7,
|
||||||
|
SPI_MISO = PA_6,
|
||||||
|
SPI_SCK = PA_5,
|
||||||
|
SPI_CS0 = PA_4,
|
||||||
|
SPI_CS = SPI_CS0,
|
||||||
|
|
||||||
|
I2C1_SDA = PB_11,
|
||||||
|
I2C1_SCL = PB_10,
|
||||||
|
|
||||||
|
PWM0_OUT = PB_0,
|
||||||
|
PWM1_OUT = PB_1,
|
||||||
|
|
||||||
|
ADC00 = PA_1,
|
||||||
|
ADC01 = PC_2,
|
||||||
|
ADC02 = PC_4,
|
||||||
|
|
||||||
|
BACKUP = PA_12,
|
||||||
|
RESET_IN = PC_9,
|
||||||
|
WAKE = PA_0,
|
||||||
|
|
||||||
|
// UARTs
|
||||||
|
UART1_TX = PA_9,
|
||||||
|
UART1_RX = PA_10,
|
||||||
|
|
||||||
|
LPUART1_TX = PC_1,
|
||||||
|
LPUART1_RX = PC_0,
|
||||||
|
|
||||||
|
UART2_TX = PA_2,
|
||||||
|
UART2_RX = PA_3,
|
||||||
|
|
||||||
|
// Aliases
|
||||||
|
SERIAL_TX = UART3_TX,
|
||||||
|
SERIAL_RX = UART3_RX,
|
||||||
|
SERIAL_CTS = UART3_CTS,
|
||||||
|
SERIAL_RTS = UART3_RTS,
|
||||||
|
|
||||||
|
UART_TXD = UART3_TX,
|
||||||
|
UART_RXD = UART3_RX,
|
||||||
|
UART_CTS = UART3_CTS,
|
||||||
|
UART_RTS = UART3_RTS,
|
||||||
|
|
||||||
|
LED1 = GPIO2, // Green
|
||||||
|
LED2 = PWM1_OUT, // Blue
|
||||||
|
LED3 = PWM0_OUT, // Red
|
||||||
|
|
||||||
|
ADC_BC95 = PC_5,
|
||||||
|
MDMTXD = LPUART1_TX,
|
||||||
|
MDMRXD = LPUART1_RX,
|
||||||
|
|
||||||
|
USBTX = UART3_TX,
|
||||||
|
USBRX = UART3_RX,
|
||||||
|
|
||||||
|
USER_BUTTON = GPIO5,
|
||||||
|
|
||||||
|
// STDIO for console print
|
||||||
|
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
|
||||||
|
STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
|
||||||
|
#else
|
||||||
|
STDIO_UART_TX = UART3_TX,
|
||||||
|
#endif
|
||||||
|
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
|
||||||
|
STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
|
||||||
|
#else
|
||||||
|
STDIO_UART_RX = UART3_RX,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
} PinName;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,373 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2017 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This file configures the system clock as follows:
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||||
|
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||||
|
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||||
|
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* SYSCLK(MHz) | 80
|
||||||
|
* AHBCLK (MHz) | 80
|
||||||
|
* APB1CLK (MHz) | 80
|
||||||
|
* APB2CLK (MHz) | 80
|
||||||
|
* USB capable | YES
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
**/
|
||||||
|
|
||||||
|
#include "stm32l4xx.h"
|
||||||
|
#include "nvic_addr.h"
|
||||||
|
#include "mbed_assert.h"
|
||||||
|
|
||||||
|
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||||
|
Internal SRAM. */
|
||||||
|
/* #define VECT_TAB_SRAM */
|
||||||
|
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
|
||||||
|
|
||||||
|
// clock source is selected with CLOCK_SOURCE in json config
|
||||||
|
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||||
|
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||||
|
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||||
|
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||||
|
|
||||||
|
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||||
|
|
||||||
|
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||||
|
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||||
|
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||||
|
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||||
|
uint8_t SetSysClock_PLL_HSI(void);
|
||||||
|
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||||
|
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||||
|
uint8_t SetSysClock_PLL_MSI(void);
|
||||||
|
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
|
||||||
|
void SystemInit(void)
|
||||||
|
{
|
||||||
|
/* FPU settings ------------------------------------------------------------*/
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||||
|
#endif
|
||||||
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||||
|
/* Set MSION bit */
|
||||||
|
RCC->CR |= RCC_CR_MSION;
|
||||||
|
|
||||||
|
/* Reset CFGR register */
|
||||||
|
RCC->CFGR = 0x00000000;
|
||||||
|
|
||||||
|
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||||
|
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||||
|
|
||||||
|
/* Reset PLLCFGR register */
|
||||||
|
RCC->PLLCFGR = 0x00001000;
|
||||||
|
|
||||||
|
/* Reset HSEBYP bit */
|
||||||
|
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||||
|
|
||||||
|
/* Disable all interrupts */
|
||||||
|
RCC->CIER = 0x00000000;
|
||||||
|
|
||||||
|
/* Configure the Vector Table location add offset address ------------------*/
|
||||||
|
#ifdef VECT_TAB_SRAM
|
||||||
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||||
|
#else
|
||||||
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||||
|
* AHB/APBx prescalers and Flash settings
|
||||||
|
* @note This function should be called only once the RCC clock configuration
|
||||||
|
* is reset to the default reset state (done in SystemInit() function).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
|
||||||
|
void SetSysClock(void)
|
||||||
|
{
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||||
|
/* 1- Try to start with HSE and external clock */
|
||||||
|
if (SetSysClock_PLL_HSE(1) == 0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||||
|
/* 2- If fail try to start with HSE and external xtal */
|
||||||
|
if (SetSysClock_PLL_HSE(0) == 0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||||
|
/* 3- If fail start with HSI clock */
|
||||||
|
if (SetSysClock_PLL_HSI()==0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||||
|
/* 4- If fail start with MSI clock */
|
||||||
|
if (SetSysClock_PLL_MSI() == 0)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
while(1) {
|
||||||
|
MBED_ASSERT(1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||||
|
#if DEBUG_MCO == 1
|
||||||
|
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||||
|
/******************************************************************************/
|
||||||
|
/* PLL (clocked by HSE) used as System clock source */
|
||||||
|
/******************************************************************************/
|
||||||
|
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||||
|
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||||
|
|
||||||
|
// Used to gain time after DeepSleep in case HSI is used
|
||||||
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||||
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||||
|
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||||
|
|
||||||
|
// Enable HSE oscillator and activate PLL with HSE as source
|
||||||
|
//RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI;
|
||||||
|
if (bypass == 0) {
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||||
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||||
|
} else {
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||||
|
}
|
||||||
|
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||||
|
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||||
|
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||||
|
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||||
|
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||||
|
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||||
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||||
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||||
|
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||||
|
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Select LSE output as LPUART1 clock source
|
||||||
|
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPUART1;
|
||||||
|
RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
|
||||||
|
RCC_PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
||||||
|
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Disable MSI Oscillator
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||||
|
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||||
|
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||||
|
|
||||||
|
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||||
|
#if DEBUG_MCO == 2
|
||||||
|
if (bypass == 0)
|
||||||
|
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||||
|
else
|
||||||
|
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 1; // OK
|
||||||
|
}
|
||||||
|
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||||
|
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||||
|
/******************************************************************************/
|
||||||
|
/* PLL (clocked by HSI) used as System clock source */
|
||||||
|
/******************************************************************************/
|
||||||
|
uint8_t SetSysClock_PLL_HSI(void)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||||
|
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||||
|
|
||||||
|
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||||
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||||
|
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||||
|
|
||||||
|
// Enable HSI oscillator and activate PLL with HSI as source
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||||
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||||
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||||
|
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||||
|
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||||
|
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||||
|
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||||
|
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||||
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||||
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||||
|
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||||
|
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||||
|
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Disable MSI Oscillator
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||||
|
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||||
|
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||||
|
|
||||||
|
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||||
|
#if DEBUG_MCO == 3
|
||||||
|
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 1; // OK
|
||||||
|
}
|
||||||
|
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||||
|
|
||||||
|
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||||
|
/******************************************************************************/
|
||||||
|
/* PLL (clocked by MSI) used as System clock source */
|
||||||
|
/******************************************************************************/
|
||||||
|
uint8_t SetSysClock_PLL_MSI(void)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||||
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||||
|
|
||||||
|
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||||
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||||
|
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||||
|
}
|
||||||
|
|
||||||
|
HAL_RCCEx_DisableLSECSS();
|
||||||
|
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||||
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||||
|
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||||
|
|
||||||
|
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||||
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||||
|
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||||
|
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||||
|
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||||
|
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||||
|
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
/* Enable MSI Auto-calibration through LSE */
|
||||||
|
HAL_RCCEx_EnableMSIPLLMode();
|
||||||
|
/* Select MSI output as USB clock source */
|
||||||
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||||
|
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||||
|
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||||
|
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||||
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||||
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||||
|
return 0; // FAIL
|
||||||
|
}
|
||||||
|
|
||||||
|
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||||
|
#if DEBUG_MCO == 4
|
||||||
|
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 1; // OK
|
||||||
|
}
|
||||||
|
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||||
|
|
@ -1583,6 +1583,23 @@
|
||||||
"release_versions": ["2", "5"],
|
"release_versions": ["2", "5"],
|
||||||
"device_name": "STM32L486RG"
|
"device_name": "STM32L486RG"
|
||||||
},
|
},
|
||||||
|
"MTB_ADV_WISE_1570": {
|
||||||
|
"inherits": ["FAMILY_STM32"],
|
||||||
|
"core": "Cortex-M4F",
|
||||||
|
"extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG", "WISE_1570"],
|
||||||
|
"config": {
|
||||||
|
"clock_source": {
|
||||||
|
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
|
||||||
|
"value": "USE_PLL_HSE_XTAL",
|
||||||
|
"macro_name": "CLOCK_SOURCE"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"detect_code": ["0460"],
|
||||||
|
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570"],
|
||||||
|
"device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
|
||||||
|
"release_versions": ["5"],
|
||||||
|
"device_name": "STM32L486RG"
|
||||||
|
},
|
||||||
"ARCH_MAX": {
|
"ARCH_MAX": {
|
||||||
"inherits": ["FAMILY_STM32"],
|
"inherits": ["FAMILY_STM32"],
|
||||||
"supported_form_factors": ["ARDUINO"],
|
"supported_form_factors": ["ARDUINO"],
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue