From 401a6b4f2bd29db43c988eabb7606b8cdd2cf385 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bora=20=C3=96zgen?= Date: Mon, 21 Sep 2020 14:52:22 +0200 Subject: [PATCH] Apply review suggestions --- .../TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c index 3207ffeca9..03a0abd10d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c @@ -56,7 +56,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @retval None */ -__weak void SetSysClock(void) +void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -88,7 +88,7 @@ __weak void SetSysClock(void) /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ -__weak uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct; @@ -167,7 +167,7 @@ __weak uint8_t SetSysClock_PLL_HSE(uint8_t bypass) /******************************************************************************/ /* PLL (clocked by HSI) used as System clock source */ /******************************************************************************/ -__weak uint8_t SetSysClock_PLL_HSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_HSI(void) { RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct;